WO2024065877A1 - 半导体结构及其读写控制方法和制造方法 - Google Patents

半导体结构及其读写控制方法和制造方法 Download PDF

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Publication number
WO2024065877A1
WO2024065877A1 PCT/CN2022/124679 CN2022124679W WO2024065877A1 WO 2024065877 A1 WO2024065877 A1 WO 2024065877A1 CN 2022124679 W CN2022124679 W CN 2022124679W WO 2024065877 A1 WO2024065877 A1 WO 2024065877A1
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Prior art keywords
semiconductor
semiconductor column
region
transistor
conductive layer
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French (fr)
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韩清华
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/402—Single electron transistors; Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/122—Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure, a read/write control method, and a manufacturing method thereof.
  • the area it occupies can reach 4F2 (F: the minimum pattern size obtainable under given process conditions). In principle, higher density efficiency can be achieved.
  • the capacitor structure that cooperates with the GAA transistor to complete data storage and reading is not easy to manufacture, and it is not easy to form a capacitor structure with a large aspect ratio and high dimensional accuracy, which makes it difficult to further improve the electrical performance of the dynamic memory.
  • the embodiments of the present disclosure provide a semiconductor structure and a read/write control method and a manufacturing method thereof, which are at least beneficial for reducing the leakage current in the first transistor while improving the sensing sensitivity of the second transistor to the current change in the first transistor, so as to improve the electrical performance of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate and a data line located on the substrate, the data line extending along a first direction; a first transistor located on the data line and a second transistor located on a side of the first transistor away from the data line; wherein the first transistor and the second transistor both include: a semiconductor column, the semiconductor column is located on a portion of the top surface of the data line and extends along a third direction; the semiconductor column has an isolation structure inside, along the second direction, the isolation structure in different areas has different thicknesses in the third direction, and the isolation structure runs through the semiconductor column, and the first direction, the second direction and the third direction intersect each other.
  • the semiconductor column has a first side and a second side relative to each other in the second direction, and the thickness of the isolation structure in the third direction gradually decreases in a direction pointing toward the interior of the semiconductor column along the first side and in a direction pointing toward the interior of the semiconductor column along the second side.
  • the semiconductor column on the side of the isolation structure close to the data line is a first semiconductor column
  • the first transistor includes the first semiconductor column; the first transistor also includes: a gate structure located on a portion of the side wall extending along the second direction and surrounding the first semiconductor column.
  • the semiconductor column located on the side of the isolation structure away from the data line is a second semiconductor column
  • the second transistor includes the second semiconductor column
  • the second transistor also includes: a first conductive layer, located on at least a portion of the side wall of the second semiconductor column extending along the third direction; a second conductive layer, located on the top surface of the second semiconductor column away from the data line; a dielectric layer, located between the first conductive layer and the second semiconductor column, and between the second conductive layer and the second semiconductor column.
  • the second semiconductor column directly opposite to the first conductive layer and directly opposite to the second conductive layer constitutes a channel region of the second transistor, and the first conductive layer, the second conductive layer and the channel region constitute a transmission path for the on-state current of the second transistor.
  • the second transistor comprises a single electron transistor.
  • the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located between the first conductive layer and the second semiconductor column, and the second dielectric layer is located between the second conductive layer and the second semiconductor column; along the third direction, the average value of the thickness of the isolation structure is the first thickness, the thickness of the second dielectric layer is the second thickness, along the second direction, the thickness of the first dielectric layer is the third thickness, the first thickness is greater than the second thickness, and the first thickness is greater than the third thickness.
  • the second thickness is equal to the third thickness.
  • the dielectric layer surrounds the sidewalls of the second semiconductor pillars extending along the third direction; the first conductive layer extends along the second direction, and the first conductive layer corresponds to a plurality of second semiconductor pillars arranged at intervals along the second direction.
  • the second conductive layer extends along the first direction, and the second conductive layer corresponds to a plurality of the semiconductor pillars arranged at intervals along the first direction.
  • the first semiconductor column includes a first region, a second region, and a third region arranged in sequence; wherein, the first region is in contact with the data line, the gate structure surrounds the side wall of the second region extending along the third direction, and the third region is in contact with the isolation structure; the orthographic projection of the third region on the substrate is a first orthographic projection, the orthographic projection of the second semiconductor column on the substrate is a second orthographic projection, and the second orthographic projection is located in the first orthographic projection.
  • the gate structure includes: a gate dielectric layer extending along the second direction and surrounding a portion of the side wall of the first semiconductor column; a gate surrounding a side of the gate dielectric layer away from the second semiconductor column; along the second direction, the thickness of the gate dielectric layer is a fourth thickness, the thickness of the dielectric layer located between the first conductive layer and the second semiconductor column is a third thickness, and the fourth thickness is greater than the third thickness.
  • an embodiment of the present disclosure further provides a read-write control method for a semiconductor structure, comprising: providing a semiconductor structure as described in any of the above items, wherein the semiconductor column located on the side of the isolation structure close to the data line is a first semiconductor column, and the semiconductor column located on the side of the isolation structure away from the data line is a second semiconductor column, and a portion of the first semiconductor column in contact with the isolation structure is a storage node; the second transistor comprises: a first conductive layer, located on at least a portion of the sidewall of the second semiconductor column extending along the third direction; a second conductive layer, located on the top surface of the second semiconductor column away from the data line; turning on the first transistor to adjust the voltage at the storage node to implement a write operation on the storage node; the magnitude of the voltage at the storage node determines the degree of conduction of the second semiconductor column, applying a first voltage to one of the first conductive layer and the second conductive layer, detecting the voltage
  • the first transistor along the third direction, includes a first region, a second region, and a third region arranged in sequence, and a gate structure surrounding a side wall of the second region extending along the third direction, the first region is in contact with the data line, the third region is in contact with the isolation structure, and the third region is the storage node; implementing a write operation to the storage node includes: applying a third voltage to the data line, applying a fourth voltage to the gate structure to turn on a transmission path between the first region and the third region, so that the voltage at the third region is affected by the voltage on the data line, so as to implement a write operation to the third region.
  • another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: providing an initial substrate; forming a data line and a first transistor in the initial substrate, wherein the data line extends along a first direction, one end of the first transistor is in contact with and connected to the data line, and the remaining initial substrate serves as a substrate; forming a second transistor on a side of the first transistor away from the data line; wherein the first transistor and the second transistor both include: a semiconductor column, wherein the semiconductor column is located on a portion of the top surface of the data line and extends along a third direction; an isolation structure is provided inside the semiconductor column, wherein the thickness of the isolation structure in different regions along the second direction is different in the third direction, and the isolation structure runs through the semiconductor column, and the first direction, the second direction and the third direction intersect with each other.
  • forming a data line and a first transistor in the initial substrate includes: patterning the initial substrate to form the data lines extending along the first direction and arranged at intervals along the second direction, and forming an initial semiconductor column located on a portion of the top surface of the data line, with the remaining initial substrate serving as a substrate; forming a gate structure, the gate structure extending along the second direction and surrounding a portion of the side wall of the initial semiconductor column, a portion of the initial semiconductor column and the gate structure constituting the first transistor.
  • the initial semiconductor column includes a first region, a second region, a third region, a fourth region and a fifth region arranged in sequence, and the gate structure surrounds the side wall of the second region extending along the third direction;
  • the step of forming the isolation structure includes: forming a protective layer on the side walls of the first region, the third region and the fifth region extending along the third direction, exposing only the side walls of the fourth region extending along the third direction; oxidizing the exposed side walls of the fourth region to convert the fourth region into the isolation structure, and the remaining initial semiconductor column serves as the semiconductor column; wherein the semiconductor column located on the side of the isolation structure close to the data line is the first semiconductor column, and the semiconductor column located on the side of the isolation structure away from the data line is the second semiconductor column, the first region, the second region and the third region constitute the first semiconductor column, and the fifth region serves as the second semiconductor column.
  • the oxidation treatment of the exposed sidewalls of the fourth region includes: performing an in-situ water vapor generation process on the exposed sidewalls of the fourth region.
  • the step of forming the second transistor includes: forming a first conductive layer, a dielectric layer, and a second conductive layer, the first conductive layer is located at least partially on the side wall of the second semiconductor column extending along the third direction, the second conductive layer is located on the top surface of the second semiconductor column away from the data line, the dielectric layer is located between the first conductive layer and the second semiconductor column, and between the second conductive layer and the second semiconductor column.
  • the step of forming the dielectric layer includes: removing at least a portion of the protective layer from the sidewall of the second semiconductor column extending along the third direction to expose at least a portion of the sidewall of the second semiconductor column extending along the third direction, and exposing a side of the second semiconductor column away from the isolation structure; and forming the dielectric layer on the exposed surface of the second semiconductor column.
  • forming the dielectric layer on the exposed surface of the second semiconductor column includes: performing oxidation treatment on the exposed second semiconductor column to form the dielectric layer on the surface of the remaining second semiconductor column.
  • the protective layer is located on the other surfaces of the second semiconductor column; after forming the second semiconductor column and before removing the protective layer, it also includes: forming a first isolation layer extending along the second direction, and the first isolation layer is located between adjacent second semiconductor columns arranged at intervals along the first direction.
  • the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is located between the first conductive layer and the second semiconductor column, and the second dielectric layer is located between the second conductive layer and the second semiconductor column; the steps of forming the first dielectric layer, the first conductive layer and the second dielectric layer include: forming an initial first dielectric layer on the exposed surface of the second semiconductor column, the first isolation layer and the initial first dielectric layer enclosing a first interval; forming an initial first conductive layer in the first interval, the initial first conductive layer filling the first interval and being located on a side of the initial first dielectric layer away from the second semiconductor column; etching back the initial first conductive layer, leaving the initial first conductive layer as the first conductive layer, in the etching back step, removing the initial first dielectric layer located on the top surface of the second semiconductor column away from the isolation structure, leaving the initial first dielectric layer as the first dielectric layer, and exposing a portion of the sidewall of the first
  • another aspect of the present disclosure further provides a transistor structure.
  • the first transistor includes a portion of a semiconductor column extending along a third direction, and the first transistor can be used as a GAA transistor, which is beneficial to reducing the leakage current in the first transistor.
  • the second transistor includes another portion of a semiconductor column extending along the third direction. It can be understood that the semiconductor column in the first transistor and the semiconductor column in the second transistor can be an integrally formed structure, and there is an isolation structure between the first transistor and the second transistor. In this way, it is beneficial to reduce the defect state density between the semiconductor column in the first transistor and the isolation structure, and reduce the defect state density between the semiconductor column in the second transistor and the isolation structure, thereby helping to improve the overall electrical performance of the semiconductor structure.
  • the first transistor can be used as a dynamic memory selection transistor
  • the second transistor can be used as a structure for storing data, that is, it plays the role of a capacitor structure. In this way, the storage or reading operation of data is realized by the first transistor and the second transistor.
  • FIG1 is a schematic diagram of a three-dimensional structure corresponding to a semiconductor structure provided by an embodiment of the present disclosure
  • FIG2 is a cross-sectional schematic diagram of the structure shown in FIG1 along a first cross-sectional direction AA1;
  • FIG3 is a schematic cross-sectional view of the structure shown in FIG1 along a second cross-sectional direction BB1;
  • FIG4 is a schematic diagram of a top view of a gate structure and a first conductive layer in a semiconductor structure provided by an embodiment of the present disclosure
  • FIG5 is a flow chart of a read/write control method for a semiconductor structure provided by another embodiment of the present disclosure.
  • 6 to 27 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a semiconductor structure and a read-write control method and manufacturing method thereof.
  • the first transistor includes a portion of a semiconductor column extending along a third direction, and the first transistor can be used as a GAA transistor, which is conducive to improving the integration density of the first transistor in the semiconductor structure and reducing the leakage current in the first transistor.
  • the second transistor includes another portion of a semiconductor column extending along the third direction.
  • the semiconductor column in the first transistor and the semiconductor column in the second transistor can be an integrally formed structure, and there is an isolation structure between the first transistor and the second transistor, so that it is conducive to reducing the defect state density between the semiconductor column in the first transistor and the isolation structure, and reducing the defect state density between the semiconductor column in the second transistor and the isolation structure, so as to improve the electrical performance of the semiconductor structure as a whole.
  • the first transistor can be used as a dynamic memory selection transistor
  • the second transistor can be used as a structure for storing data, that is, it plays the role of a capacitor structure. In this way, the storage or reading operation of data is realized by the first transistor and the second transistor together, and the second transistor has a smaller size and a higher sensitivity to the current change in the first transistor compared to the previous capacitor structure.
  • FIG1 is a schematic diagram of a three-dimensional structure corresponding to a semiconductor structure provided by an embodiment of the present disclosure
  • FIG2 is a schematic cross-sectional diagram of the structure shown in FIG1 along a first cross-sectional direction AA1
  • FIG3 is a schematic cross-sectional diagram of the structure shown in FIG1 along a second cross-sectional direction BB1
  • FIG4 is a schematic diagram of a top view of a gate structure and a first conductive layer in a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 1 to FIG. 4 in this embodiment are schematic diagrams of partial structures of the semiconductor structure.
  • the semiconductor structure includes: a substrate 100 and a data line 110 located on the substrate 100, wherein the data line 110 extends along a first direction X; a first transistor 101 located on the data line 110 and a second transistor 102 located on a side of the first transistor 101 away from the data line 110; wherein the first transistor 101 and the second transistor 102 both include: a semiconductor column 103, wherein the semiconductor column 103 is located on a portion of the top surface of the data line 110 and extends along a third direction Z; an isolation structure 133 is provided inside the semiconductor column 103, wherein the thickness of the isolation structure 133 in different regions along the second direction Y in the third direction Z is different, and the isolation structure 133 runs through the semiconductor column 103, and the first direction X, the second direction Y and the third direction Z intersect each other.
  • the first transistor 101 can be used as a dynamic memory selection transistor
  • the second transistor 102 can be used as a structure for storing data, that is, it plays the role of a capacitor structure.
  • the first transistor 101 and the second transistor 102 can jointly implement data storage or reading operations
  • the second transistor 102 has a smaller size than the previous capacitor structure, which is conducive to further reducing the overall size of the semiconductor structure.
  • the second transistor 102 has a higher sensitivity to the current change in the first transistor 101 than the previous capacitor structure, which is conducive to implementing data storage or reading operations within a smaller current change range, thereby helping to reduce the power consumption of the semiconductor structure when it is working.
  • the material type of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.
  • the data line 110 can be a bit line, and the substrate 100, the bit line and the semiconductor column 103 have the same semiconductor element. Then, the substrate 100, the bit line and the semiconductor column 103 can be formed using the same film layer structure, and the film layer structure is composed of semiconductor elements, so that the semiconductor column 103 and the bit line are an integrated structure, thereby improving the interface state defects between the semiconductor column 103 and the bit line to improve the performance of the semiconductor structure.
  • the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium.
  • the bit line and the semiconductor pillar 103 both include silicon.
  • the material of the data line 110 may also include a metal semiconductor compound, which has a relatively small resistivity compared to unmetallized semiconductor materials. Therefore, compared to the semiconductor pillar 103, the resistivity of the data line 110 is smaller, which is conducive to reducing the resistance of the data line 110 and reducing the contact resistance between the data line 110 and the semiconductor pillar 103, further improving the electrical performance of the semiconductor structure.
  • the metal semiconductor compound may include at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide or tantalum silicide.
  • a plurality of data lines 110 arranged at intervals may be formed on the substrate 100, and each data line 110 may be in contact with at least one semiconductor column 103.
  • FIGS. 1 to 3 take four mutually spaced data lines 110 formed on the substrate 100, and each data line 110 in contact with four semiconductor columns 103 as an example. In practical applications, the number of data lines 110 and the number of semiconductor columns 103 in contact with each data line 110 may be reasonably set according to actual electrical requirements.
  • the third direction Z may be a direction from the substrate 100 to the data line 110 .
  • the semiconductor column 103 has a first side a and a second side b relative to each other in the second direction Y, and the thickness of the isolation structure 133 in the third direction Z gradually decreases in the direction Y1 pointing to the inside of the semiconductor column 103 along the first side a, and in the direction Y2 pointing to the inside of the semiconductor column 103 along the second side b.
  • the isolation structure 133 can be prepared by performing thermal oxidation treatment on part of the semiconductor column 103. During the thermal oxidation treatment, as time goes by, the area of the semiconductor column 103 closer to the inside of the semiconductor column 103 is converted into the isolation structure 133, thereby causing the thickness of the isolation structure 133 in the third direction Z to gradually decrease along the directions Y1 and Y2.
  • the isolation structure 133 is processed by in-situ thermal oxidation of part of the semiconductor column 103.
  • the in-situ oxidation of the side wall of the semiconductor column 103 is beneficial to make the formed isolation structure 133 penetrate the semiconductor column 103 and to improve the density of the isolation structure 133.
  • the thickness of the isolation structure 133 in the third direction Z gradually decreases, which is beneficial to reduce the probability of electron tunneling and improve the device performance of the semiconductor structure.
  • the semiconductor column 103 located on the side of the isolation structure 133 close to the data line 110 is a first semiconductor column 113, and the first transistor 101 includes the first semiconductor column 113; the first transistor 101 also includes: a gate structure 111, extending along the second direction Y and surrounding a portion of the side wall of the first semiconductor column 113.
  • the gate structure 111 includes: a gate dielectric layer 121, surrounding a portion of the sidewall of the first semiconductor column 113 extending along the third direction Z; and a gate 131, extending along the second direction Y and surrounding the sidewall of the gate dielectric layer 121 away from the first semiconductor column 113. It can be understood that the gate structure 111 corresponds to a plurality of first semiconductor columns 113 arranged at intervals along the second direction Y.
  • the semiconductor column 103 located on the side of the isolation structure 133 away from the data line 110 is a second semiconductor column 123, and the second transistor 102 includes the second semiconductor column 123; the second transistor 102 also includes: a first conductive layer 112, located on at least a portion of the side wall of the second semiconductor column 123 extending along the third direction Z; a second conductive layer 122, located on the top surface of the second semiconductor column 123 away from the data line 110; a dielectric layer 132, located between the first conductive layer 112 and the second semiconductor column 123, and between the second conductive layer 122 and the second semiconductor column 123.
  • the dielectric layer 132 and the first conductive layer 112 are described in detail below through two specific embodiments.
  • the dielectric layer 132 surrounds the sidewall of the second semiconductor pillar 123 extending along the third direction Z, and the first conductive layer 112 extends along the second direction Y and surrounds the sidewall of the dielectric layer 132 away from the second semiconductor pillar 123.
  • the first conductive layer 112 extends along the second direction Y, and the first conductive layer 112 corresponds to a plurality of second semiconductor pillars 123 arranged at intervals along the second direction Y. In this way, it is helpful to simplify the preparation process of the first conductive layer 112, and it is helpful to control or detect the conduction degree of the second semiconductor pillar 123 at different times through the same first conductive layer 112.
  • the dielectric layer 132 is only located on two opposite side walls of the second semiconductor pillar 123 along the second direction Y, and the first conductive layer 112 is located on two side walls of the dielectric layer 132 away from the second semiconductor pillar 123.
  • one first conductive layer 112 corresponds to one second semiconductor pillar 123, and two opposite side walls of the second semiconductor pillar 123 along the first direction X are in contact with and connected to the first isolation layer 114.
  • the first isolation layer 114 will be described in detail later.
  • the dielectric layer 132 may surround the side walls of the second semiconductor pillar 123 extending along the third direction Z, and the first conductive layer 112 is only located on two opposite side walls of the dielectric layer 132 along the second direction Y.
  • the second conductive layer 122 extends along the first direction X, and the second conductive layer 122 corresponds to a plurality of semiconductor pillars 103 arranged at intervals along the first direction X. In this way, it is helpful to simplify the preparation process of the second conductive layer 122, and it is helpful to control or detect the conduction degree of the second semiconductor pillar 123 at different times through the same second conductive layer 122.
  • the second semiconductor column 123 directly opposite to the first conductive layer 112 and directly opposite to the second conductive layer 122 constitutes the channel region of the second transistor 102, and the first conductive layer 112, the second conductive layer 122 and the channel region constitute the transmission path of the on-current of the second transistor 102.
  • first conductive layer 112 is located on the side wall of the second semiconductor column 123 extending along the third direction Z, and the second conductive layer 122 is located on the top surface of the second semiconductor column 123 away from the substrate 100, that is, the first conductive layer 112 and the second conductive layer 122 are not located in the same plane, so that the on-current is not transmitted in one plane, but in three-dimensional space.
  • the transmission path of the on-current passes through the first conductive layer 112 through the dielectric layer 132 into the second semiconductor column 123, turns in the second semiconductor column 123, and passes through the dielectric layer 132 into the second conductive layer 122.
  • the entire second semiconductor column 123 can be used as a channel region when the second transistor 102 is in the on state.
  • the first conductive layer 112 can serve as the source of the second transistor 102, and the second conductive layer 122 can serve as the drain of the second transistor 102; in other embodiments, the first conductive layer 112 can also serve as the drain of the second transistor 102, and the second conductive layer 122 can also serve as the source of the second transistor 102.
  • the second transistor 102 includes a single electron transistor (SET).
  • the first semiconductor column 113 in the first transistor 101 that is partially in contact with the isolation structure 133 serves as the gate of the second transistor 102.
  • the single electron transistor requires only a few electrons when working, so that when the gate of the second transistor 102 undergoes a small voltage change, the single electron transistor can sensitively and accurately sense the difference in voltage at the gate of the second transistor 102, thereby facilitating the second transistor 102 to sense the current change in the first semiconductor column 113 in the first transistor 101 that is partially in contact with the isolation structure 133.
  • the second transistor 102 has extremely low power consumption and extremely high switching speed. It can be understood that, compared with traditional transistors, single electron transistors have the advantages of small size, high speed, high sensitivity, and most importantly, low power consumption.
  • the second transistor 102 has a smaller volume than the conventional capacitor structure, which is beneficial to further reduce the size of the entire semiconductor structure.
  • the dielectric layer 132 includes a first dielectric layer 142 and a second dielectric layer 152, the first dielectric layer 142 is located between the first conductive layer 112 and the second semiconductor column 123, and the second dielectric layer 152 is located between the second conductive layer 122 and the second semiconductor column 123; along the third direction Z, the average value of the thickness of the isolation structure 133 is the first thickness, the thickness of the second dielectric layer 152 is the second thickness, and along the second direction Y, the thickness of the first dielectric layer 142 is the third thickness, the first thickness is greater than the second thickness, and the first thickness is greater than the third thickness T3.
  • the first dielectric layer 142 and the second dielectric layer 152 may be an integrally formed structure, that is, the first dielectric layer 142 and the second dielectric layer 152 are formed by the same preparation process, and the dielectric layer 132 is a whole.
  • FIGS. 1 to 3 take the first dielectric layer 142 and the second dielectric layer 152 as an integrally formed structure as an example; in other embodiments, the first dielectric layer 142 and the second dielectric layer 152 may be different film layer structures, that is, the dielectric layer 132 is a multi-layer structure.
  • the second thickness is equal to the third thickness.
  • the first thickness can be 5 nm
  • the second thickness and the third thickness can be 1 nm.
  • the first semiconductor column 113 includes a first region I, a second region II and a third region III arranged in sequence; wherein the first region I is in contact with the data line 110, the gate structure 111 surrounds the side wall of the second region II extending along the third direction Z, and the third region III is in contact with the isolation structure 133; the orthographic projection of the third region III on the substrate 100 is the first orthographic projection, and the orthographic projection of the second semiconductor column 123 on the substrate 100 is the second orthographic projection, and the second orthographic projection is located in the first orthographic projection.
  • the second region II directly opposite to the gate structure 111 can serve as a channel region when the first transistor 101 is in the on state, and the gate structure 111 and the first semiconductor column 113 can constitute a GAA transistor, that is, the first transistor 101 can be a GAA transistor, and the data line 110 is located between the substrate 100 and the GAA transistor, thereby being able to constitute a 3D stacked storage device, which is beneficial to improving the integration density of the semiconductor structure.
  • the dielectric layer 132 can be obtained by performing thermal oxidation treatment on the surface of the second semiconductor column 123, that is, converting the portion of the second semiconductor column 123 located at the periphery of the second semiconductor column 123 into the dielectric layer 132, so that the orthographic projection of the second semiconductor column 123 on the substrate 100, that is, the second orthographic projection, is reduced, so that the second orthographic projection is located in the first orthographic projection.
  • the orthographic projection of the second region II on the substrate 100 is smaller than the orthographic projection of the third region III on the substrate 100, and smaller than the orthographic projection of the first region I on the substrate 100, which is conducive to forming a second region II with a smaller cross-sectional area in a cross section perpendicular to the third direction Z, and is conducive to improving the control capability of the gate structure 111 surrounding the sidewall of the second region II over the second region II, thereby making it easier to control the on or off of the GAA transistor.
  • the orthographic projections of the first region, the second region, and the third region on the substrate may be equal; or, the orthographic projections of the second region and the third region on the substrate are both smaller than the orthographic projection of the first region on the substrate.
  • the first semiconductor pillar 113 is doped with doping ions, and the doping ions doped in the first region I and the third region III are of the same type, and the doping ions doped in the second region II are of a different type from the doping ions doped in the first region I, which is beneficial to improving the electrical performance of the first transistor 101, for example, improving the conductivity of the first region I and the third region III and improving the on/off ratio of the second region II.
  • the doping ions include N-type ions and P-type ions.
  • the N-type ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; and the P-type ions may include at least one of boron ions, indium ions, or gallium ions.
  • the gate structure 111 includes: a gate dielectric layer 121, which is located on a portion of the side wall extending along the second direction Y and surrounding the first semiconductor column 113; a gate 131, which surrounds the side of the gate dielectric layer 121 away from the second semiconductor column 123; along the second direction Y, the thickness of the gate dielectric layer 121 is a fourth thickness, the thickness of the dielectric layer 132 located between the first conductive layer 112 and the second semiconductor column 123 is a third thickness, and the fourth thickness is greater than the third thickness.
  • the first transistor 101 can be a GAA transistor
  • the second transistor 102 can be a single electron transistor
  • at least part of the third region III in the first transistor 101 that contacts the isolation structure 133 constitutes the gate of the second transistor 102.
  • the thickness of the dielectric layer 132 corresponding to the first conductive layer 112 and the second conductive layer is very thin, about 1nm, to ensure the high working performance of the single electron transistor; in the GAA transistor, the thickness of the gate dielectric layer 121 between the gate 131 and the second region II is relatively large, about 5nm to 10nm, to ensure the high working performance of the GAA transistor.
  • the fourth thickness is greater than the third thickness, which is conducive to improving the overall electrical performance of the first transistor 101 and the second transistor 102.
  • the region in the gate structure 111 that is in contact with the channel region II can be prepared by thermally oxidizing the surface of the channel region II, that is, converting the portion of the channel region III that is located outside the channel region III into a portion of the gate structure; in the second transistor 102, the dielectric layer 132 can be obtained by thermally oxidizing the surface of the second semiconductor column 123, or by performing a deposition process on the surface of the second semiconductor column 123; and the fourth thickness is greater than the third thickness. In this way, the orthographic projection of the second region II on the substrate 100 is located at the orthographic projection of the second semiconductor column 123 on the substrate 100.
  • the semiconductor structure further includes:
  • the first isolation layer 114 is at least located between the first conductive layers 112 adjacent to each other along the first direction X.
  • the first isolation layer 114 is used to achieve electrical isolation between the first conductive layers 112 adjacent to each other along the first direction X.
  • the second isolation layer 124 covers the side of the first conductive layer 112 away from the substrate 100.
  • the second isolation layer 124 and the first conductive layer 112 jointly cover the side wall of the dielectric layer 132 extending along the third direction X.
  • the second isolation layer 124 is used to protect the first conductive layer 112 to prevent other electrical structures in the semiconductor structure from causing electrical interference to the first conductive layer 112.
  • the third isolation layer 134 is located at least between the gate structures 111 adjacent to each other along the first direction X, and is used to achieve electrical isolation between the gate structures 111 adjacent to each other along the first direction X.
  • the fourth isolation layer 144 surrounds the sidewalls of the third region III extending along the third direction Z, and is used to achieve electrical isolation between the third regions III that are adjacent in the first direction X or in the second direction Y.
  • first isolation layer 114, the second isolation layer 124, the third isolation layer 134 and the fourth isolation layer 144 can all be single-layer structures or multi-layer structures.
  • first isolation layer 114, the second isolation layer 124, the third isolation layer 134 and the fourth isolation layer 144 can all be single-layer structures or multi-layer structures.
  • Figures 1 to 3 are only an example of the total isolation layer composed of the above four isolation layers.
  • the first isolation layer 114 and the third isolation layer 134 are illustrated in the same filling method, and the second isolation layer 124 and the fourth isolation layer 144 are illustrated in another filling method.
  • the materials of at least two of the first isolation layer 114, the second isolation layer 124, the third isolation layer 134, and the fourth isolation layer 144 may be the same.
  • the materials of the first isolation layer 114, the second isolation layer 124, the third isolation layer 134, and the fourth isolation layer 144 may all be at least one of silicon nitride or silicon oxynitride.
  • the semiconductor structure further includes:
  • the first insulating layer 115 is located between the data lines 110 adjacent to each other in the second direction Y, and surrounds the side walls of the first region I extending along the third direction Z, so as to achieve electrical insulation between the data lines 110 adjacent to each other in the second direction Y, and achieve electrical insulation between the first regions I adjacent to each other in the first direction X or in the second direction Y.
  • the second insulating layer 125 fills up the second gap to improve the electrical insulation effect between the third regions III adjacent to each other along the second direction Y.
  • the third insulating layer 135 extends along the second direction Y and is located between the adjacent isolation structures 133 along the second direction Y. Moreover, the third isolation layer is also located between the adjacent third insulating layers 135 along the first direction X to improve the stability of the semiconductor structure.
  • the materials of at least two of the first insulating layer 115, the second insulating layer 125 and the third insulating layer 135 can be the same.
  • the materials of the first insulating layer 115, the second insulating layer 125 and the third insulating layer 135 can all be silicon oxide.
  • the first insulating layer 115, the second insulating layer 125 and the third insulating layer 135 can all be single-film layer structures or multi-film layer structures. For the clarity of the diagram, only the outer contours of the above three insulating layers are illustrated in Figures 1 to 3.
  • Figures 1 to 3 are only an example of the total insulating layer composed of the above three insulating layers.
  • the gate 131, the first conductive layer 112, and the second conductive layer 122 are illustrated in the same filling manner.
  • at least two of the gate 131, the first conductive layer 112, and the second conductive layer 122 may be made of the same material, or the gate 131, the first conductive layer 112, and the second conductive layer 122 may be made of different conductive materials.
  • the gate 131, the first conductive layer 112, and the second conductive layer 122 may be made of titanium nitride.
  • the first transistor 101 can be used as a dynamic memory selection transistor, and the second transistor 102 can be used as a structure for storing data, that is, it plays the role of a capacitor structure.
  • the first transistor 101 and the second transistor 102 can be used together to implement data storage or reading operations.
  • the first transistor 101 can be a GAA transistor, which is beneficial to improving the integration density of the semiconductor structure.
  • the second transistor 102 has a smaller size than the previous capacitor structure, which is beneficial to further reducing the overall size of the semiconductor structure.
  • the second transistor 102 has a higher sensitivity to current changes in the first transistor 101 than the previous capacitor structure, which is beneficial to implement data storage or reading operations within a smaller current change range, thereby helping to reduce the power consumption of the semiconductor structure when it is working.
  • FIG5 is a flow chart of a read-write control method for a semiconductor structure provided by another embodiment of the present disclosure.
  • the read/write control method of the semiconductor structure includes the following steps:
  • S101 Provide a semiconductor structure as described in an embodiment of the present disclosure.
  • the semiconductor column 103 located on the side of the isolation structure 133 close to the data line 110 is the first semiconductor column 113
  • the semiconductor column 103 located on the side of the isolation structure 133 away from the data line 110 is the second semiconductor column 123
  • the partial area of the first semiconductor column 113 that contacts the isolation structure 133 is the storage node 143.
  • the storage node 143 may be a portion of the third region III.
  • the second transistor 102 includes: a first conductive layer 112, located on at least a portion of the sidewall of the second semiconductor pillar 123 extending along the third direction Z; and a second conductive layer 122, located on the top surface of the second semiconductor pillar 123 away from the data line 110.
  • the first conductive layer 112 may be a source of the second transistor 102
  • the second conductive layer 122 may be a drain of the second transistor 102.
  • the voltage at the first region I is affected by the data line 110.
  • the first region I and the third region III are turned on, so that the voltage at the third region III is affected by the first region I and changes, thereby adjusting the voltage at the storage node 143 to achieve a write operation on the storage node 143.
  • the data line 110 transmits a high level to the first region I.
  • the voltage at the third region III also becomes a high level, so that the voltage at the storage node 143 also becomes a high level.
  • the storage node 143 is equivalent to storing data "1".
  • S104 Detect the voltage at the other of the first conductive layer 112 and the second conductive layer 122 and use it as the second voltage, determine the degree of conductivity of the second semiconductor column 123 based on the difference between the second voltage and the first voltage, and determine the voltage at the storage node 143 based on the degree of conductivity of the second semiconductor column 123 to implement a read operation on the storage node 143.
  • a first voltage is applied to the first conductive layer 112, and a voltage at the second conductive layer 122 is detected and used as a second voltage.
  • the magnitude of the voltage at the storage node 143 determines the degree of conduction of the second semiconductor column 123. The greater the voltage at the storage node 143, the greater the degree of conduction of the second semiconductor column 123. Based on the different degrees of conduction of the second semiconductor column 123, under the premise that the value of the first voltage remains unchanged, the values of the second voltage detected are different. The higher the degree of conduction of the second semiconductor column 123, the closer the value of the second voltage is to the value of the first voltage.
  • the degree of conduction of the second semiconductor column 123 can be judged based on the difference between the second voltage and the first voltage. The smaller the difference between the second voltage and the first voltage, the greater the degree of conduction of the second semiconductor column 123, and the greater the voltage at the storage node 143.
  • the conductivity of the second semiconductor column 123 is high, and the value of the detected second voltage is close to the value of the first voltage, that is, the difference between the second voltage and the first voltage is small, and the data read at this time is determined to be "1" to implement the read operation on the storage node 143.
  • the first transistor 101 includes a first region I, a second region II, and a third region III arranged in sequence, and a gate structure 111 surrounding the sidewalls of the second region II extending along the third direction Z, the first region I is in contact with the data line 110, the third region III is in contact with the isolation structure 133, and the third region III is a storage node 143; implementing a write operation on the storage node 143, including: applying a third voltage to the data line 110, applying a fourth voltage to the gate structure 111 to turn on the transmission path between the first region I and the third region III, so that the voltage at the third region III is affected by the voltage on the data line 110, so as to implement a write operation on the third region III.
  • the third voltage applied to the data line 110 is the voltage to be stored at the storage node 143
  • the fourth voltage applied to the gate structure 111 is the voltage that turns on the first transistor 101.
  • the first transistor 101 can be a GAA transistor, and a fourth voltage with a smaller value can be used to make the first transistor 101 in an on state.
  • the second transistor 102 can be a single-electron transistor. When the voltage at the storage node 143 changes slightly, there will be a difference between the second voltage and the first voltage. Therefore, using the first transistor 101 and the second transistor 102 to implement data writing and reading operations is beneficial to reducing power consumption when the semiconductor structure is working.
  • the semiconductor structure provided in one embodiment of the present disclosure is used to implement data writing and reading operations, which is beneficial for implementing data storage or reading operations within a smaller voltage variation range, thereby helping to reduce power consumption when the semiconductor structure is working.
  • FIG. 6 to 27 are schematic structural diagrams corresponding to the steps of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure. It should be noted that the parts that are the same or corresponding to the aforementioned embodiments are not repeated here. In addition, in order to facilitate the description and clearly illustrate the steps of the method for manufacturing a semiconductor structure, Figures 6 to 27 are all schematic structural diagrams of local semiconductor structures.
  • Fig. 8 is a cross-sectional schematic diagram of the structure shown in Fig. 7 along the first cross-sectional direction AA1
  • Fig. 9 is a cross-sectional schematic diagram of the structure shown in Fig. 7 along the second cross-sectional direction BB1. It should be noted that, one or both of the cross-sectional schematic diagram along the first cross-sectional direction AA1 and the cross-sectional schematic diagram along the second cross-sectional direction BB1 will be provided later according to the need of description.
  • the figure is a cross-sectional schematic diagram along the first cross-sectional direction AA1; when two figures are referred to at the same time, the figure is first a cross-sectional schematic diagram along the first cross-sectional direction AA1, and then a cross-sectional schematic diagram along the second cross-sectional direction BB1.
  • the method for manufacturing a semiconductor structure includes the following steps:
  • An initial substrate is provided, and the material type of the initial substrate can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material.
  • the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or indium gallium, etc.
  • a data line 110 and a first transistor 101 are formed in an initial substrate, the data line 110 extends along a first direction X, one end of the first transistor 101 is in contact with the data line 110 , and the remaining initial substrate serves as the substrate 100 .
  • forming the data line 110 and the first transistor 101 in the initial substrate may include the following steps:
  • the initial substrate is patterned to form data lines 110 extending along the first direction X and arranged at intervals along the second direction Y, and initial semiconductor pillars 153 are formed on partial top surfaces of the data lines 110 , and the remaining initial substrate serves as the substrate 100 .
  • the process of patterning the initial substrate to form the data line 110 and the initial semiconductor pillar 153 can be divided into two etchings of the initial substrate.
  • the initial substrate is etched using a first mask layer having a plurality of first openings that are separated from each other and extend along the first direction X, and the length of the first opening is consistent with the length of the data line to be formed subsequently, so as to form a plurality of first trenches extending along the first direction X; and an initial fourth insulating layer filling the first trenches is formed;
  • the initial substrate and the initial fourth insulating layer are etched using a second mask layer having a plurality of second openings that are separated from each other and extend along the second direction Y, and the length of the second opening is consistent with the length of the gate structure to be formed subsequently, so as to form a plurality of second trenches 108 extending along the second direction Y, and the remaining initial fourth insulating layer is used as
  • the initial semiconductor column 153 includes an initial first region 163 , an initial second region 173 , and an initial third region 183 arranged in sequence; before forming the gate structure 111 , the manufacturing method further includes the following steps:
  • An initial fifth insulating layer is formed, and the initial fifth insulating layer is located on the side wall of the second trench 108 extending along the third direction Z, and a third trench is provided between the initial fifth insulating layer located on the side wall of the second trench 108; referring to FIG7, an initial third isolation layer 154 filling the third trench is formed; the initial fifth insulating layer and the fourth insulating layer 145 in contact with the initial third region 183 are removed to expose all the side walls extending along the third direction Z of the initial third region; an initial fourth isolation layer 164 is formed to cover all the side walls extending along the third direction Z of the initial third region, and the initial fourth isolation layer 164 forms a through hole f between the adjacent initial third regions 183 along the second direction Y, and the through hole f exposes a portion of the top surface of the fourth insulating layer 145.
  • the initial third isolation layer 154 and the initial fourth isolation layer 164 together constitute a support skeleton, and the initial fifth insulation layer and the fourth insulation layer 145 shown in FIG. 6 are etched using the support skeleton as a mask, and the remaining initial fifth insulation layer serves as the fifth insulation layer 155.
  • the remaining fourth insulation layer 145 is located between adjacent data lines 110 along the second direction Y, and between adjacent initial first regions 163 along the second direction Y.
  • the fifth insulation layer 155 extends along the second direction Y, and is located between adjacent initial first regions 163 along the first direction X.
  • the fourth insulation layer 145 and the fifth insulation layer 155 in FIG. 7 together constitute the first insulation layer 115, and the initial first region 163 is subsequently used as the first region of the first semiconductor column.
  • the support skeleton is in contact with the initial third region 183, and part of the support skeleton is embedded in the first insulating layer 115.
  • the support skeleton plays a supporting and fixing role for the initial semiconductor column 153.
  • the etching process generates a squeezing force on the initial semiconductor column 153, it is helpful to prevent the initial semiconductor column 153 from tilting or shifting due to squeezing, so as to improve the stability of the semiconductor structure; on the other hand, the support skeleton wraps the side wall of the initial third region 183, which is helpful to prevent the etching process from causing damage to the initial third region 183.
  • a third gap g is formed between the initial second region 173 and the initial third isolation layer 154, and the through hole f and the third gap g together form a cave structure h.
  • the initial second region 173 is subsequently used as the second region of the first semiconductor column.
  • a gate structure 111 is formed.
  • the gate structure 111 extends along the second direction Y and surrounds a portion of the sidewall of the initial semiconductor column 153 .
  • a portion of the initial semiconductor column 153 and the gate structure 111 constitute the first transistor 101 .
  • the steps of forming the gate structure 111 include: forming a first sacrificial layer 109 on the top surface of the initial third region 183 away from the substrate 100; taking the material of the initial semiconductor column 153 as silicon as an example, the sidewalls of the exposed third gap g, that is, the sidewalls of the initial second region 173 extending along the third direction Z, are thermally oxidized to form a gate dielectric layer 121, and a fourth gap extending along the second direction Y is provided between the gate dielectric layer 121 and the initial third isolation layer 154; and a gate 131 is formed to fill the fourth gap, and the gate dielectric layer 121 and the gate 131 together constitute the gate structure 111.
  • an initial second insulating layer 165 is formed to fill the through hole f.
  • the initial second insulating layer 165 is a basis for the subsequent formation of a second insulating layer, and the first sacrificial layer 109 is removed.
  • the above embodiment is only an example of forming the first transistor 101.
  • the manufacturing method provided in another embodiment of the present disclosure does not limit the method for forming the first transistor 101.
  • the gate dielectric layer can also be formed by a deposition process.
  • a second transistor 102 is formed on a side of the first transistor 101 away from the data line 110; wherein the first transistor 101 and the second transistor 102 both include: a semiconductor column 103, the semiconductor column 103 is located on a portion of the top surface of the data line 110 and extends along a third direction Z; an isolation structure 133 is provided inside the semiconductor column 103, and along the second direction Y, the isolation structure 133 in different areas has different thicknesses in the third direction Z, and the isolation structure 133 runs through the semiconductor column 103, and the first direction X, the second direction Y and the third direction Z intersect each other.
  • isolation structure 133 and the second transistor 102 are described in detail below.
  • the initial semiconductor pillar 153 includes a first region I, a second region II, a third region III, a fourth region IV, and a fifth region V arranged in sequence, and the gate structure 111 surrounds the sidewall of the second region II extending along the third direction Z.
  • the first region I is the initial first region 163
  • the second region II is the initial second region 173
  • the third region III, the fourth region IV, and the fifth region V together constitute the initial third region 183.
  • the step of forming the isolation structure 133 includes forming a protection layer 106 on the sidewalls of the first region I, the third region III and the fifth region V extending along the third direction Z, leaving only the sidewall of the fourth region IV extending along the third direction Z exposed.
  • forming the protective layer 106 includes the following steps:
  • the initial third isolation layer 154 and the initial fourth isolation layer 164 are etched to expose the sidewalls of the fourth region IV and the fifth region V extending along the third direction Z, and the remaining initial third isolation layer 154 serves as a part of the third isolation layer 134, and the remaining initial fourth isolation layer 164 serves as the fourth isolation layer 144.
  • a second sacrificial layer 119 is formed, and the second sacrificial layer 119 is located on the side walls of the fourth region IV and the fifth region V extending along the third direction Z, and the initial second insulating layer 165 is in contact with the second sacrificial layer 119, and a fifth gap i is provided between the second sacrificial layers 119 located on the adjacent side walls of the fourth region IV and the adjacent side walls of the fifth region V along the second direction Y, and the fifth gap i extends along the second direction Y.
  • a fifth isolation layer 174 filling the fifth gap i is formed.
  • the second sacrificial layer 119 and the initial second insulating layer 165 are etched using the fifth isolation layer 174 and the semiconductor pillar 103 as masks, and the remaining second sacrificial layer 119 only surrounds the sidewall of the fourth region IV extending along the third direction Z, and the remaining initial second insulating layer 165 is located between the fourth isolation layers 144 adjacent to each other in the second direction Y, and between the second sacrificial layers 119 adjacent to each other in the second direction Y.
  • the material of the second sacrificial layer 119 and the material of the initial second insulating layer 165 may be the same, and the second sacrificial layer 119 and the initial second insulating layer 165 may be synchronously etched by the same etching process.
  • the material of the second sacrificial layer 119 may also be different from the material of the initial second insulating layer 165, and the material of the second sacrificial layer 119 and the initial second insulating layer 165 may be etched respectively by different etching processes.
  • a third sacrificial layer 129 is formed, the third sacrificial layer 129 surrounds the side wall of the fifth region V extending along the third direction Z, and the third sacrificial layer 129 is in contact with the fifth isolation layer 174; using the third sacrificial layer 129, the semiconductor column 103 and the fifth isolation layer 174 as masks, the remaining second sacrificial layer 119 is removed, and the initial second insulating layer 165 (refer to Figure 16) located between adjacent second sacrificial layers 119 along the second direction Y is removed, and the remaining initial second insulating layer 165 serves as the second insulating layer 125 to form a protective layer 106 and a sixth gap k that only expose the side wall of the fourth region IV extending along the third direction Z.
  • the protection layer 106 may include: a first insulating layer 115 surrounding the sidewalls of the first region I extending along the third direction Z, a fourth isolation layer 144 surrounding the sidewalls of the third region III extending along the third direction Z, and a third sacrificial layer 129 surrounding the sidewalls of the fifth region V extending along the third direction Z.
  • the third sacrificial layer 129 and the fifth isolation layer 174 may also serve as a supporting skeleton.
  • the side walls of the exposed fourth region IV are oxidized to convert the fourth region IV into an isolation structure 133, and the remaining initial semiconductor column 153 serves as the semiconductor column 103; wherein, the semiconductor column 103 located on the side of the isolation structure 133 close to the data line 110 is the first semiconductor column 113, and the semiconductor column 103 located on the side of the isolation structure 133 away from the data line 110 is the second semiconductor column 123, the first region I, the second region II and the third region III constitute the first semiconductor column 113, and the fifth region V serves as the second semiconductor column 123.
  • the sidewalls of the exposed fourth region IV are oxidized, including: performing an in-situ steam generation process (ISSG) on the sidewalls of the exposed fourth region IV.
  • the ISSG process is a process for growing an oxide layer through a high-temperature water vapor atmosphere, and the speed of growing the oxide layer is relatively fast.
  • the oxide layer grown by the ISSG method has better electrical properties than the oxide layer obtained by furnace tube wet oxidation.
  • the step of forming the second transistor 102 may include: forming a first conductive layer 112, a dielectric layer 132 and a second conductive layer 122, the first conductive layer 112 is located at least partially on the side wall of the second semiconductor column 123 extending along the third direction Z, the second conductive layer 122 is located on the top surface of the second semiconductor column 123 away from the data line 110, the dielectric layer 132 is located between the first conductive layer 112 and the second semiconductor column 123, and between the second conductive layer 122 and the second semiconductor column 123.
  • forming the dielectric layer 132 on the surface of the exposed second semiconductor pillar 123 includes: oxidizing the exposed second semiconductor pillar 123 to form the dielectric layer 132 on the surface of the remaining second semiconductor pillar 123.
  • the exposed second semiconductor pillar 123 may be oxidized by an in-situ water vapor generation process.
  • forming the dielectric layer 132 may include the following steps:
  • At least a portion of the protective layer 106 is removed from the sidewalls of the second semiconductor pillar 123 extending along the third direction Z to expose at least a portion of the sidewalls of the second semiconductor pillar 123 extending along the third direction Z and a side of the second semiconductor pillar 123 away from the isolation structure 133 .
  • the protective layer 106 of the side wall of the second semiconductor column 123 extending along the third direction Z before removing at least a portion of the protective layer 106 of the side wall of the second semiconductor column 123 extending along the third direction Z, it also includes: referring to Figures 21 to 22, forming an initial third insulating layer 175 that fills the sixth gap k, and the initial third insulating layer 175 is the basis for the subsequent formation of the third insulating layer 135.
  • the step of removing at least a portion of the protective layer 106 of the sidewalls of the second semiconductor pillar 123 extending along the third direction Z includes: removing the third sacrificial layer 129 surrounding the sidewalls of the fifth region V extending along the third direction Z, and removing the fifth isolation layer 174 between the adjacent third sacrificial layers 129 along the first direction X, and the remaining fifth isolation layer 174 is located between the adjacent initial third insulating layers 175 along the first direction X.
  • the fifth isolation layer 174 and the initial third isolation layer 154 together constitute the third isolation layer 134 (refer to FIG. 1 ).
  • a fourth sacrificial layer 139 is formed, the fourth sacrificial layer 139 is located on the side wall of the fifth region V extending along the third direction Z, and the fourth sacrificial layer 139 is in contact with the initial third insulating layer 175, and a seventh gap is formed between adjacent fourth sacrificial layers 139 along the first direction; continuing to refer to Figures 23 to 24, a first isolation layer 114 is formed to fill the seventh gap.
  • the fourth sacrificial layer 139 and part of the initial third insulating layer 175 are removed, and the removed initial third insulating layer 175 is located between adjacent fourth sacrificial layers 139 along the second direction Y, and the remaining initial third insulating layer 175 serves as the third insulating layer 135.
  • a dielectric layer 132 is formed on the surface of the exposed second semiconductor column 123. It should be noted that the dielectric layer 132 can be formed by oxidizing the surface of the exposed second semiconductor column 123, or by a deposition process.
  • the dielectric layer 132 can be integrally formed, and subsequently the first conductive layer 112 , the second isolation layer 124 and the second conductive layer 122 are formed on the basis of FIGS. 25 and 26 .
  • the dielectric layer 132 may be formed in steps. The step-by-step formation of the dielectric layer 132 is described in detail below.
  • the second semiconductor pillar 123 has all its surfaces exposed except for the side surface in contact with the isolation structure 133, and the protection layer 106 is located on the other surfaces of the second semiconductor pillar 123; after forming the second semiconductor pillar 123 and before removing the protection layer 106, the method further includes: forming a first isolation layer 114 extending along the second direction Y, wherein the first isolation layer 114 is located between adjacent second semiconductor pillars 123 arranged at intervals along the first direction X.
  • the method for forming the first isolation layer 114 has been described in the aforementioned embodiment and will not be repeated here.
  • the dielectric layer 132 includes a first dielectric layer 142 and a second dielectric layer 152.
  • the first dielectric layer 142 is located between the first conductive layer 112 and the second semiconductor pillar 123.
  • the second dielectric layer 152 is located between the second conductive layer 122 and the second semiconductor pillar 123.
  • the formation of the first dielectric layer 142, the first conductive layer 112 and the second dielectric layer 152 includes the following steps:
  • an initial first dielectric layer 162 is formed on the surface of the exposed second semiconductor column 123, and the first isolation layer 114 and the initial first dielectric layer 162 form a first interval; an initial first conductive layer 172 is formed in the first interval, and the initial first conductive layer 172 fills the first interval and is located on a side of the initial first dielectric layer 162 away from the second semiconductor column 123.
  • the initial first conductive layer 172 is etched back, and the remaining initial first conductive layer 172 serves as the first conductive layer 112.
  • the initial first dielectric layer 162 located on the top surface of the second semiconductor column 123 away from the isolation structure 133 is removed, and the remaining initial first dielectric layer 162 serves as the first dielectric layer 142, and a portion of the side wall of the first dielectric layer 142 extending along the third direction Z is exposed.
  • a second isolation layer 124 is formed, and the second isolation layer 124 and the first conductive layer 112 together fill the first gap; and with continued reference to FIG2 and 4, a second dielectric layer 152 is formed on the second semiconductor pillar 123 away from the top surface of the first dielectric layer 142.
  • the process of forming the initial first dielectric layer 162 and the second dielectric layer 152 can be either an ISSG or a deposition process.
  • a second conductive layer 122 is formed on a side of the second dielectric layer 152 away from the substrate 100 , and the second conductive layer extends along the first direction X.
  • the first transistor 101 can be used as a dynamic memory selection transistor, and the second transistor 102 can be used as a structure for storing data, that is, it plays the role of a capacitor structure.
  • the first transistor 101 and the second transistor 102 can be used together to implement data storage or reading operations.
  • the first transistor 101 can be a GAA transistor, which is beneficial to improving the integration density of the semiconductor structure.
  • the second transistor 102 has a smaller size than the previous capacitor structure, which is beneficial to further reducing the overall size of the semiconductor structure.
  • the second transistor 102 has a higher sensitivity to current changes in the first transistor 101 than the previous capacitor structure, which is beneficial to implement data storage or reading operations within a smaller current change range, thereby helping to reduce the power consumption of the semiconductor structure when it is working.

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Abstract

本公开实施例涉及半导体技术领域，提供一种半导体结构及其读写控制方法和制造方法，半导体结构包括：基底以及位于基底上的数据线，数据线沿第一方向延伸；位于数据线上的第一晶体管和位于第一晶体管远离数据线的一侧的第二晶体管；其中，第一晶体管和第二晶体管中均包括：半导体柱，半导体柱位于数据线的部分顶面且沿第三方向延伸；半导体柱内部具有隔离结构，沿第二方向上，不同区域的隔离结构在第三方向上的厚度不同，且隔离结构贯穿半导体柱，第一方向、第二方向和第三方向两两相交。本公开实施例至少有利于在降低第一晶体管中的漏电流的同时，提高第二晶体管对第一晶体管中电流变化的感应灵敏度，以提高半导体结构的电学性能。

Description

半导体结构及其读写控制方法和制造方法
交叉引用
本申请要求于2022年09月27日递交的名称为“半导体结构及其读写控制方法和制造方法”、申请号为202211185511.6的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种半导体结构及其读写控制方法和制造方法。
背景技术
随着动态存储器的集成密度朝着更高的方向发展，在对动态存储器阵列结构中晶体管的排布方式以及如何缩小动态存储器阵列结构中单个功能器件的尺寸进行研究的同时，也需要提高小尺寸的功能器件的电学性能。
利用垂直的全环绕栅极(GAA，Gate-All-Around)晶体管结构作为动态存储器选择晶体管(access transistor)时，其占据的面积可以达到4F2(F：在给定工艺条件下可获得的最小图案尺寸)，原则上可以实现更高的密度效率，但与GAA晶体管配合完成数据存储和读取工作的电容结构不易制作，不易形成深宽比大且尺寸精度高的电容结构，从而难以进一步提高动态存储器的电学性能。
发明内容
本公开实施例提供一种半导体结构及其读写控制方法和制造方法，至少有利于在降低第一晶体管中的漏电流的同时，提高第二晶体管对第一晶体管中电流变化的感应灵敏度，以提高半导体结构的电学性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底以及位于所述基底上的数据线，所述数据线沿第一方向延伸；位于所述数据线上的第一晶体管和位于所述第一晶体管远离所述数据线的一侧的第二晶体管；其中，所述第一晶体管和所述第二晶体管中均包括：半导体柱，所述半导体柱位于所述数据线的部分顶面且沿第三方向延伸；所述半导体柱内部具有隔离结构，沿第二方向上，不同区域的所述隔离结构在所述第三方向上的厚度不同，且所述隔离结构贯穿所述半导体柱，所述第一方向、所述第二方向和所述第三方向两两相交。
在一些实施例中，所述半导体柱在所述第二方向上具有相对的第一侧和第二侧，沿所述第一侧指向所述半导体柱内部的方向，以及沿所述第二侧指向所述半导体柱内部的方向上，所述隔离结构在所述第三方向上的厚度逐渐减小。
在一些实施例中，所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，所述第一晶体管包括所述第一半导体柱；所述第一晶体管还包括：栅极结构，位于沿所述第二方向延伸且环绕所述第一半导体柱的部分侧壁。
在一些实施例中，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第二晶体管包括所述第二半导体柱；所述第二晶体管还包括：第一导电层，位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁；第二导电层，位于所述第二半导体柱远离所述数据线的顶面；介质层，位于所述第一导电层和所述第二半导体柱之间，以及位于所述第二导电层和所述第二半导体柱之间。
在一些实施例中，若所述第二晶体管处于导通状态，与所述第一导电层正对且与所述第二导电层正对的所述第二半导体柱构成所述第二晶体管的沟道区，所述第一导电层、所述第二导电层和所述沟道区构成所述第二晶体管的导通电流的传输路径。
在一些实施例中，所述第二晶体管包括单电子晶体管。
在一些实施例中，所述介质层包括第一介质层和第二介质层，所述第一介质层位于所述第一导电层和所述第二半导体柱之间，所述第二介质层位于所述第二导电层和所述第二半导体柱之间；沿所述第三方向上，所述隔离结构的厚度的平均值为第一厚度，所述第二介质层的厚度为第二厚度，沿所述第二方向上，所述第一介质层的厚度为第三厚度，所述第一厚度大于所述第二厚度，且所述第一厚度大于所述第三厚度。
在一些实施例中，所述第二厚度等于所述第三厚度。
在一些实施例中，所述介质层环绕所述第二半导体柱沿所述第三方向延伸的侧壁；所述第一导电层沿所述第二方向延伸，所述第一导电层与沿所述第二方向间隔排布的多个所述第二半导体柱对应。
在一些实施例中，所述第二导电层沿所述第一方向延伸，所述第二导电层与沿所述第一方向间隔排布的多个所述半导体柱对应。
在一些实施例中，沿所述第三方向上，所述第一半导体柱包括依次排列的第一区、第二区以及第三区；其中，所述第一区与所述数据线接触连接，所述栅极结构环绕所述第二区沿所述第三方向延伸的侧壁，所述第三区与所述隔离结构接触连接；所述第三区在所述基底上的正投影为第一正投影，所述第二半导体柱在所述基底上的正投影为第二正投影，所述第二正投影位于所述第一正投影中。
在一些实施例中，所述栅极结构包括：栅介质层，沿所述第二方向延伸且环绕所述第一半导体柱的部分侧壁；栅极，环绕所述栅介质层远离所述第二半导体柱的一侧；沿所述第二方向上，所述栅介质层的厚度为第四厚度，位于所述第一导电层和所述第二半导体柱之间的所述介质层的厚度为第三厚度，所述第四厚度大于所述第三厚度。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的读写控制方法，包括：提供如上述任一项所述的半导体结构，位于所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第一半导体柱中与所述隔离结构接触的部分区域为存储节点；所述第二晶体管包括：第一导电层，位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁；第二导电层，位于所述第二半导体柱远离所述数据线的顶面；导通所述第一晶体管，以调整所述存储节点处的电压，以实现对所述存储节点的写操作；所述存储节点处电压的大小决定所述第二半导体柱的导通程度，向所述第一导电层和所述第二导电层中的一者施加第一电压，检测所述第一导电层和所述第二导电层中的另一者处的电压并作为第二电压，基于所述第二电压与所述第一电压的差值判断所述第二半导体柱的导通程度，基于所述第二半导体柱的导通程度判断所述存储节点处的电压大小，以实现对所述存储节点的读操作。
在一些实施例中，沿所述第三方向上，所述第一晶体管包括依次排列的第一区、第二区和第三区，以及环绕所述第二区沿所述第三方向延伸的侧壁的栅极结构，所述第一区与所述数据线接触连接，所述第三区与所述隔离结构接触连接，所述第三区为所述存储节点；所述实现对所述存储节点的写操作，包括：向所述数据线施加第三电压，向所述栅极结构施加第四电压，以导通所述第一区和所述第三区之间的传输路径，使所述第三区处的电压受到所述数据线上的电压的影响，以实现对所述第三区的写操作。
根据本公开一些实施例，本公开实施例又一方面还提供一种半导体结构的制造方法，包括：提供初始基底；在所述初始基底中形成数据线和第一晶体管，所述数据线沿第一方向延伸，所述第一晶体管的一端与所述数据线接触连接，剩余所述初始基底作为基底；在所述第一晶体管远离所述数据线的一侧形成第二晶体管；其中，所述第一晶体管和所述第二晶体管中均包括：半导体柱，所述半导体柱位于所述数据线的部分顶面且沿第三方向延伸；所述半导体柱内部具有隔离结构，沿第二方向上，不同区域的所述隔离结构在所述第三方向上的厚度不同，且所述隔离结构贯穿所述半导体柱，所述第一方向、所述第二方向和所述第三方向两两相交。
在一些实施例中，所述在所述初始基底中形成数据线和第一晶体管，包括：图形化所述初始基底，以形成沿所述第一方向延伸且沿所述第二方向间隔排布的所述数据线，以及形成位于所述数据线的部分顶面的初始半导体柱，剩余所述初始基底作为基底；形成栅极结构，所述栅极结构沿所述第二方向延伸且环绕所述初始半导体柱的部分侧壁，部分所述初始半导体柱和所述栅极结构构成所述第一晶体管。
在一些实施例中，沿所述第三方向上，所述初始半导体柱包括依次排列的第一区、第二区、第三区、第四区和第五区，所述栅极结构环绕所述第二区沿所述第三方向延伸的侧壁；形成所述隔离结构的步骤包括：在所述第一区、所述第三区和所述第五区沿所述第三方向延伸的侧壁上形成保护层，仅露出所述第四区沿所述第三方向延伸的侧壁；对露出的所述第四区的侧壁进行氧化处理，以将所述第四区转化为所述隔离结构，剩余所述初始半导体柱作为所述半导体柱；其中，位于所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第一区、所述第二区和所述第三区构成所述第一半导体柱，所述第五区作为所述第二半导体柱。
在一些实施例中，所述对露出的所述第四区的侧壁进行氧化处理，包括：对露出的所述第四区的侧壁进行原位水汽生成工艺。
在一些实施例中，在形成所述隔离结构之后，形成所述第二晶体管的步骤包括：形成第一导电层、介质层和第二导电层，所述第一导电层位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁，所述第二导电层位于所述第二半导体柱远离所述数据线的顶面，所述介质层位于所述第一导电层和所述第二半导体柱之间，以及位于所述第二导电层和所述第二半导体柱之间。
在一些实施例中，形成所述介质层的步骤包括：去除所述第二半导体柱沿所述第三方向延伸的侧壁的至少部分所述保护层，以露出所述第二半导体柱沿所述第三方向延伸的至少部分侧壁，以及露出所述第二半导体柱远离所述隔离结构的一侧；在露出的所述第二半导体柱表面形成所述介质层。
在一些实施例中，所述在露出的所述第二半导体柱表面形成所述介质层，包括：对露出的所述第二半导体柱进行氧化处理，以在剩余所述第二半导体柱的表面形成所述介质层。
在一些实施例中，所述第二半导体柱除与所述隔离结构接触的侧面外，其他表面均露出，所述保护层位于所述第二半导体柱的其他表面；在形成所述第二半导体柱之后，在去除所述保护层之前，还包括：形成沿所述第二方向延伸的第一隔离层，所述第一隔离层位于沿所述第一方向上间隔排布的相邻所述第二半导体柱之间。
在一些实施例中，所述介质层包括第一介质层和第二介质层，所述第一介质层位于所述第一导电层和所述第二半导体柱之间，所述第二介质层位于所述第二导电层和所述第二半导体柱之间；形成所述第一介质层、所述第一导电层和所述第二介质层的步骤包括：在露出的所述第二半导体柱表面形成初始第一介质层，所述第一隔离层和所述初始第一介质层围成第一间隔；在所述第一间隔中形成初始第一导电层，所述初始第一导电层填充满所述第一间隔且位于所述初始第一介质层远离所述第二半导体柱的一侧；对所述初始第一导电层进行回刻蚀，剩余所述初始第一导电层作为所述第一导电层，在所述回刻蚀的步骤中， 去除位于所述第二半导体柱远离所述隔离结构的顶面的所述初始第一介质层，剩余所述初始第一介质层作为所述第一介质层，且露出所述第一介质层沿所述第三方向延伸的部分侧壁；形成第二隔离层，所述第二隔离层和所述第一导电层共同填充满所述第一间隔；在所述第二半导体柱远离所述第一介质层顶面形成所述第二介质层。
根据本公开一些实施例，本公开实施例另一方面还提供一种晶体管结构。
本公开实施例提供的技术方案至少具有以下优点：
第一晶体管包括沿第三方向延伸的一部分半导体柱，则第一晶体管可以作为GAA晶体管，如此有利于降低第一晶体管中的漏电流。而且，第二晶体管包括沿第三方向延伸的另一部分半导体柱，可以理解的是，第一晶体管中的半导体柱和第二晶体管中的半导体柱可以为一体成型结构，且第一晶体管和第二晶体管之间具有隔离结构，如此，有利于降低第一晶体管中的半导体柱与隔离结构之间的缺陷态密度，以及降低第二晶体管中的半导体柱与隔离结构之间的缺陷态密度，从而有利于提高半导体结构整体的电学性能。此外，第一晶体管可以作为动态存储器选择晶体管，第二晶体管可以作为存储数据的结构，即充当电容结构的角色，如此，通过第一晶体管和第二晶体管共同实现对数据的存储或读取操作。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的半导体结构对应的立体结构示意图；
图2为图1所示结构沿第一截面方向AA1的一种剖面示意图；
图3为图1所示结构沿第二截面方向BB1的剖面示意图；
图4为本公开一实施例提供的半导体结构中栅极结构和第一导电层的俯视结构示意图；
图5为本公开另一实施例提供的一种半导体结构的读写控制方法的流程图；
图6至图27为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
具体实施方式
本公开实施例提供一种半导体结构及其读写控制方法和制造方法，半导体结构中，第一晶体管包括沿第三方向延伸的一部分半导体柱，则第一晶体管可以作为GAA晶体管，如此有利于提高第一晶体管在半导体结构中的集成密度，以及降低第一晶体管中的漏电流。而且，第二晶体管包括沿第三方向延伸的另一部分半导体柱，可以理解的是，第一晶体管中的半导体柱和第二晶体管中的半导体柱可以为一体成型结构，且第一晶体管和第二晶体管之间具有隔离结构，如此，有利于降低第一晶体管中的半导体柱与隔离结构之间的缺陷态密度，以及降低第二晶体管中的半导体柱与隔离结构之间的缺陷态密度，从而有利于提高半导体结构整体的电学性能。此外，第一晶体管可以作为动态存储器选择晶体管，第二晶体管可以作为存储数据的结构，即充当电容结构的角色，如此，通过第一晶体管和第二晶体管共同实现对数据的存储或读取操作，并且，第二晶体管相较于曰前的电容结构，具有更小的尺寸以及更高的对第一晶体管中电流变化的感应灵敏度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导体结构进行详细说明。图1为本公开一实施例提供的半导体结构对应的立体结构示意图；图2为图1所示结构沿第一截面方向AA1的一种剖面示意图；图3为图1所示结构沿第二截面方向BB1的剖面示意图；图4为本公开一实施例提供的半导体结构中栅极结构和第一导电层的俯视结构示意图。
需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，本实施例中的图1至图4均为半导体结构的局部结构示意图。
参考图1至图4，半导体结构包括：基底100以及位于基底100上的数据线110，数据线110沿第一方向X延伸；位于数据线110上的第一晶体管101和位于第一晶体管101远离数据线110的一侧的第二晶体管102；其中，第一晶体管101和第二晶体管102中均包括：半导体柱103，半导体柱103位于数据线110的部分顶面且沿第三方向Z延伸；半导体柱103内部具有隔离结构133，沿第二方向Y上，不同区域的隔离结构133在第三方向Z上的厚度不同，且隔离结构133贯穿半导体柱103，第一方向X、第二方向Y和第三方向Z两两相交。
可以理解的是，第一晶体管101可以作为动态存储器选择晶体管，第二晶体管102可以作为存储数据的结构，即充当电容结构的角色，如此，可以通过第一晶体管101和第二晶体管102共同实现对数据的存储或读取操作，并且，第二晶体管102相较于曰前的电容结构具有更小的尺寸，有利于进一步缩小半导体结构整体的尺寸，而且，第二晶体管102相较于曰前的电容结构具有更高的对第一晶体管101中电流 变化的感应灵敏度，有利于在更小的电流变化幅度内实现对数据的存储或读取操作，从而有利于降低半导体结构工作时的功耗。
以下将结合附图对本公开实施例进行更为详细的说明。
在一些实施例中，基底100的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
在一些实施例中，数据线110可以为位线，基底100、位线和半导体柱103具有相同的半导体元素，则基底100、位线和半导体柱103三者可以利用同一膜层结构形成，该膜层结构由半导体元素构成，使得半导体柱103与位线为一体结构，从而改善半导体柱103与位线之间的界面态缺陷，以改善半导体结构的性能。
其中，半导体元素可以包括硅、碳、锗、砷、镓、铟中的至少一种。在一个例子中，位线与半导体柱103均包括硅元素。
在一些实施例中，数据线110的材料还可以包括金属半导体化合物，金属半导体化合物相较于未金属化的半导体材料而言，具有相对较小的电阻率，因此，相较于半导体柱103而言，数据线110的电阻率更小，从而有利于降低数据线110的电阻，且降低数据线110与半导体柱103之间的接触电阻，进一步改善半导体结构的电学性能。以半导体元素为硅为例，金属半导体化合物可以包括硅化钴、硅化镍、硅化钼、硅化钛、硅化钨或者硅化钽的至少一种。
在一些实施例中，基底100上可以形成有多个间隔排布的数据线110，每一数据线110可与至少一个半导体柱103相接触，图1至图3中以基底100上形成有4个相互间隔的数据线110，以及每一数据线110与4个半导体柱103相接触作为示例，实际应用中，可根据实际电学需求，合理设置数据线110的数量以及与每一数据线110相接触的半导体柱103的数量。
在一些实施例中，第三方向Z可以为基底100指向数据线110的方向。
在一些实施例中，参考图3，半导体柱103在第二方向Y上具有相对的第一侧a和第二侧b，沿第一侧a指向半导体柱103内部的方向Y1，以及沿第二侧b指向半导体柱103内部的方向Y2上，隔离结构133在第三方向Z上的厚度逐渐减小。
可以理解的是，隔离结构133可以是通过对部分半导体柱103进行热氧化处理而制备形成的，在热氧化处理的过程中，随着时间的推移，越靠近半导体柱103内部的半导体柱103转化为隔离结构133的区域越少，因而使得沿方向Y1和方向Y2上，隔离结构133在第三方向Z上的厚度逐渐减小。
此外，隔离结构133通过对部分半导体柱103进行原位热氧化处理，不同于采用顶部表面氧化工艺以及氧化沉积工艺，通过对半导体柱103侧壁的原位氧化处理，有利于使得形成的隔离结构133贯穿半导体柱103，且有利于提高隔离结构133的致密度，而且，沿方向Y1和方向Y2上，隔离结构133在第三方向Z上的厚度逐渐减小，有利于减小电子隧穿的概率，提高半导体结构的器件性能。
在一些实施例中，参考图1至图3，位于隔离结构133靠近数据线110一侧的半导体柱103为第一半导体柱113，第一晶体管101包括第一半导体柱113；第一晶体管101还包括：栅极结构111，沿第二方向Y延伸且环绕第一半导体柱113的部分侧壁。
在一些实施例中，参考图1至图4，栅极结构111包括：栅介质层121，环绕第一半导体柱113沿第三方向Z延伸的部分侧壁；栅极131，沿第二方向Y延伸且环绕栅介质层121远离第一半导体柱113的侧壁。可以理解的是，栅极结构111与沿第二方向Y上间隔排布的多个第一半导体柱113对应。
在一些实施例中，参考图1至图4，位于隔离结构133远离数据线110一侧的半导体柱103为第二半导体柱123，第二晶体管102包括第二半导体柱123；第二晶体管102还包括：第一导电层112，位于第二半导体柱123沿第三方向Z延伸的至少部分侧壁；第二导电层122，位于第二半导体柱123远离数据线110的顶面；介质层132，位于第一导电层112和第二半导体柱123之间，以及位于第二导电层122和第二半导体柱123之间。
以下通过两种具体的实施例对介质层132和第一导电层112进行详细说明。
在一些实施例中，参考图4中的4a，介质层132环绕第二半导体柱123沿第三方向Z延伸的侧壁，第一导电层112沿第二方向Y延伸且环绕介质层132远离第二半导体柱123的侧壁。可以理解的是，第一导电层112沿第二方向Y延伸，第一导电层112与沿第二方向Y间隔排布的多个第二半导体柱123对应。如此，有利于简化第一导电层112的制备工艺，以及有利于通过同一第一导电层112在不同时刻对第二半导体柱123进行控制或检测第二半导体柱123的导通程度。
在另一些实施例中，参考图4中的4b，介质层132仅位于第二半导体柱123沿第二方向Y上相对的两个侧壁，第一导电层112位于介质层132远离第二半导体柱123的两个侧壁，如此，一个第一导电层112与一个第二半导体柱123对应，第二半导体柱123沿第一方向X上相对的两个侧壁与第一隔离层114接触连接，后续会对第一隔离层114进行详细说明。此外，在实际应用中，介质层132可以环绕第二半导体柱123沿第三方向Z延伸的侧壁，且第一导电层112仅位于介质层132沿第二方向Y上相对的两个侧壁上。
在一些实施例中，第二导电层122沿第一方向X延伸，第二导电层122与沿第一方向X间隔排 布的多个半导体柱103对应。如此，有利于简化第二导电层122的制备工艺，以及有利于通过同一第二导电层122在不同时刻对第二半导体柱123进行控制或检测第二半导体柱123的导通程度。
在一些实施例中，若第二晶体管102处于导通状态，与第一导电层112正对且与第二导电层122正对的第二半导体柱123构成第二晶体管102的沟道区，第一导电层112、第二导电层122和沟道区构成第二晶体管102的导通电流的传输路径。可以理解的是，由于第一导电层112位于第二半导体柱123沿第三方向Z延伸的侧壁，第二导电层122位于第二半导体柱123远离基底100的顶面，即第一导电层112和第二导电层122并非位于同一平面内，如此，使得导通电流并非在一个平面内进行传递，而是在三维空间内进行传递。
在一个例子中，参考图3，导通电流的传输路径经由第一导电层112透过介质层132进入第二半导体柱123，并在第二半导体柱123中转折，透过介质层132进入第二导电层122中。如此，第二半导体柱123整体均可以作为第二晶体管102处于导通状态时的沟道区。
在一些实施例中，第一导电层112可以作为第二晶体管102的源极，第二导电层122可以作为第二晶体管102的漏极；在另一些实施例中，第一导电层112也可以作为第二晶体管102的漏极，第二导电层122也可以作为第二晶体管102的源极。
在一些实施例中，第二晶体管102包括单电子晶体管(SET，single electron transistor)。第一晶体管101中部分与隔离结构133接触连接的第一半导体柱113作为第二晶体管102的栅极，单电子晶体管工作时仅需要很少的电子，使得第二晶体管102的栅极发生小幅度的电压变化时，单电子晶体管能灵敏准确的感应出第二晶体管102的栅极处电压的区别，从而有利于提高第二晶体管102对第一晶体管101中部分与隔离结构133接触连接的第一半导体柱113中的电流变化的感应灵敏度，使得第二晶体管102具有极低的功耗和极高的开关速度。可以理解的是，与传统的晶体管相较，单电子晶体管具有体积小、速度快、灵敏度高的优点，而且最重要的是消耗功率低。
此外，第二晶体管102相较于曰前的电容结构具有更小的体积，有利于进一步缩小半导体结构整体的尺寸。
在一些实施例中，参考图1至图3，介质层132包括第一介质层142和第二介质层152，第一介质层142位于第一导电层112和第二半导体柱123之间，第二介质层152位于第二导电层122和第二半导体柱123之间；沿第三方向Z上，隔离结构133的厚度的平均值为第一厚度，第二介质层152的厚度为第二厚度，沿第二方向Y上，第一介质层142的厚度为第三厚度，第一厚度大于第二厚度，且第一厚度大于第三厚度T3。
需要说明的是，在一些实施例中，第一介质层142和第二介质层152可以为一体成型结构，即第一介质层142和第二介质层152通过同一制备工艺形成，介质层132为一个整体，图1至图3中以第一介质层142和第二介质层152为一体成型结构为示例；在另一些实施例中，第一介质层142和第二介质层152可以为不同的膜层结构，即介质层132为多默层结构。
在一些实施例中，第二厚度等于第三厚度。在一个例子中，第一厚度可以为5nm，第二厚度和第三厚度可以为1nm。
在一些实施例中，参考图1至图3，沿第三方向Z上，第一半导体柱113包括依次排列的第一区I、第二区II以及第三区III；其中，第一区I与数据线110接触连接，栅极结构111环绕第二区II沿第三方向Z延伸的侧壁，第三区III与隔离结构133接触连接；第三区III在基底100上的正投影为第一正投影，第二半导体柱123在基底100上的正投影为第二正投影，第二正投影位于第一正投影中。
可以理解的是，与栅极结构111正对的第二区II可以作为第一晶体管101处于导通状态时的沟道区，栅极结构111和第一半导体柱113可以构成GAA晶体管，即第一晶体管101可以为GAA晶体管，且数据线110位于基底100与GAA晶体管之间，因而能够构成3D堆叠的存储器件，有利于提高半导体结构的集成密度。
在一些实施例中，介质层132可以是通过对第二半导体柱123表面进行热氧化处理得到的，即将处于第二半导体柱123外围的部分第二半导体柱123转化为介质层132，如此，使得第二半导体柱123在基底100上的正投影，即第二正投影减小，从而使得第二正投影位于第一正投影中。
在一些实施例中，第二区II在基底100上的正投影小于第三区III在基底100上的正投影，且小于第一区I在基底100上的正投影，在垂直于第三方向Z的截面中，有利于形成截面面积更小的第二区II，有利于提高环绕第二区II侧壁的栅极结构111对第二区II的控制能力，从而更容易控制GAA晶体管的导通或者关断。在其他实施例中，第一区、第二区以及第三区在基底上的正投影可以相等；或者，第二区和第三区在基底上的正投影均小于第一区在基底上的正投影。
在一些实施例中，第一半导体柱113中掺杂有掺杂离子，且第一区I和第三区III中掺杂的掺杂离子类型相同，第二区II中掺杂的掺杂离子类型与第一区I中掺杂的掺杂离子类型不同，如此，有利于提高第一晶体管101的电学性能，例如，提高第一区I和第三区III的导电性能以及提高第二区II的导通/关断比例。其中，掺杂离子包括N型离子和P型离子。具体地，N型离子可以包括砷离子、磷离子或者锑离子中的至少一种；P型离子可以包括硼离子、铟离子或者镓离子中的至少一种。
在一些实施例中，栅极结构111包括：栅介质层121，位于沿第二方向Y延伸且环绕第一半导体柱113的部分侧壁；栅极131，环绕栅介质层121远离第二半导体柱123的一侧；沿第二方向Y上，栅介 质层121的厚度为第四厚度，位于第一导电层112和第二半导体柱123之间的介质层132的厚度为第三厚度，第四厚度大于第三厚度。
可以理解的是，第一晶体管101可以为GAA晶体管，第二晶体管102可以为单电子晶体管，且第一晶体管101中与隔离结构133接触的第三区III的至少部分区域构成第二晶体管102的栅极。单电子晶体管中，与第一导电层112和第二导电层对应的介质层132的厚度很薄，约为1nm，以保证单电子晶体管较高的工作性能；GAA晶体管中，位于栅极131和第二区II之间的栅介质层121的厚度较大，约为5nm～10nm，以保证GAA晶体管较高的工作性能。如此，使得第四厚度大于第三厚度，有利于提高第一晶体管101和第二晶体管102整体的电学性能。
此外，第一晶体管101中，栅极结构111中与沟道区II接触连接的区域可以通过对沟道区II的表面进行热氧化处理而制备形成，即将处于沟道区III外围的部分沟道区III转化为栅极结构的一部分；第二晶体管102中，介质层132可以是通过对第二半导体柱123表面进行热氧化处理得到的，也可以是在第二半导体柱123表面进行沉积工艺得到的；而且，第四厚度大于第三厚度。如此，使得第二区II在基底100上的正投影位于第二半导体柱123在基底100上的正投影。
在一些实施例中，参考图1至图3，半导体结构还包括：
第一隔离层114，至少位于沿第一方向X上相邻的第一导电层112之间，第一隔离层114用于实现沿第一方向X上相邻的第一导电层112之间的电隔离。
第二隔离层124，覆盖第一导电层112远离基底100的一侧，第二隔离层124和第一导电层112共同覆盖介质层132沿第三方向X延伸的侧壁，第二隔离层124用于保护第一导电层112，避免半导体结构中其他的电学结构对第一导电层112造成电干扰。
第三隔离层134，至少位于沿第一方向X上相邻的栅极结构111之间，用于实现沿第一方向X上相邻的栅极结构111之间的电隔离。
第四隔离层144，环绕第三区III沿第三方向Z上延伸的侧壁，用于实现无论是沿第一方向X上相邻，还是沿第二方向Y上相邻的第三区III之间的电隔离。
需要说明的是，第一隔离层114、第二隔离层124、第三隔离层134以及第四隔离层144均可以为单膜层结构或多膜层结构，为了图示的清晰性，图1至图3中仅示意出上述四种隔离层的外轮廓。此外，实际应用中，为实现半导体结构中相邻各种导电结构之间的电隔离，对隔离层的划分以及设置可以根据实际需要以及实际的制备工艺而定，图1至图3仅为上述四种隔离层构成的总隔离层的一种示例。
此外，为了图示的清晰性，图1至图3中，以相同的填充方式示意出第一隔离层114和第三隔离层134，以另外一种填充方式示意出第二隔离层124和第四隔离层144，在实际应用中，第一隔离层114、第二隔离层124、第三隔离层134以及第四隔离层144中至少两者的材料可以相同。在一个例子中，第一隔离层114、第二隔离层124、第三隔离层134以及第四隔离层144中四者的材料均可以为氮化硅或氮氧化硅中的至少一者。
在一些实施例中，参考图1至图3，第四隔离层144环绕第三区III沿第三方向Z延伸的侧壁时，一第四隔离层144与一第三区III对应，使得相邻的第四隔离层144在第一方向X上具有第一间隙，且在第二方向Y上具有第二间隙，且第一间隙和第二间隙相连通；第三隔离层134沿第二方向Y延伸，且填充满第一间隙；半导体结构还包括：
第一绝缘层115，位于沿第二方向Y上相邻的数据线110之间，且环绕第一区I沿第三方向Z上延伸的侧壁，如此，以实现沿第二方向Y上相邻的数据线110之间的电绝缘，以及实现无论是沿第一方向X上相邻，还是沿第二方向Y上相邻的第一区I之间的电绝缘。
第二绝缘层125，填充满第二间隙，以提高对沿第二方向Y上相邻的第三区III之间的电绝缘效果。
第三绝缘层135，沿第二方向Y延伸，且位于沿第二方向Y上相邻的隔离结构133之间，并且，第三隔离层还位于沿第一方向X上相邻的第三绝缘层135之间，以提高半导体结构的稳定性。
需要说明的是，实际应用中，第一绝缘层115、第二绝缘层125以及第三绝缘层135中至少两者的材料可以相同。在一个例子中，第一绝缘层115、第二绝缘层125以及第三绝缘层135中三者的材料均可以为氧化硅。此外，第一绝缘层115、第二绝缘层125以及第三绝缘层135均可以为单膜层结构或多膜层结构，为了图示的清晰性，图1至图3中仅示意出上述三种绝缘层的外轮廓。此外，实际应用中，为实现半导体结构中相邻各种导电结构之间的电隔离以及半导体结构整体的稳定性，对绝缘层的划分以及设置可以根据实际需要以及实际的制备工艺而定，图1至图3仅为上述三种绝缘层构成的总绝缘层的一种示例。
此外，为了图示的清晰性，图1至图3中，以相同的填充方式示意出栅极131、第一导电层112和第二导电层122，在实际应用中，栅极131、第一导电层112和第二导电层122中至少两者的材料可以相同，或者，栅极131、第一导电层112和第二导电层122中三者均为不同的导电材料。在一个例子中，栅极131、第一导电层112和第二导电层122中三者的材料均可以为氮化钛。
综上所述，第一晶体管101可以作为动态存储器选择晶体管，第二晶体管102可以作为存储数据的结构，即充当电容结构的角色，如此，可以通过第一晶体管101和第二晶体管102共同实现对数据的存储或读取操作，并且，第一晶体管101可以为GAA晶体管，有利于提高半导体结构的集成密度，第二晶 体管102相较于曰前的电容结构具有更小的尺寸，有利于进一步缩小半导体结构整体的尺寸，而且，第二晶体管102相较于曰前的电容结构具有更高的对第一晶体管101中电流变化的感应灵敏度，有利于在更小的电流变化幅度内实现对数据的存储或读取操作，从而有利于降低半导体结构工作时的功耗。
本公开另一实施例还提供一种半导体结构的读写控制方法，用于控制本公开一实施例提供的半导体结构。以下将结合附图对本公开另一实施例提供的半导体结构的读写控制方法进行详细说明。图5为本公开另一实施例提供的一种半导体结构的读写控制方法的流程图。
参考图1至图5，半导体结构的读写控制方法包括如下步骤：
S101：提供如本公开一实施例所述的半导体结构。
其中，位于隔离结构133靠近数据线110一侧的半导体柱103为第一半导体柱113，位于隔离结构133远离数据线110一侧的半导体柱103为第二半导体柱123，第一半导体柱113中与隔离结构133接触的部分区域为存储节点143。
在一些实施例中，存储节点143可以为第三区III中的一部分。
第二晶体管102包括：第一导电层112，位于第二半导体柱123沿第三方向Z延伸的至少部分侧壁；第二导电层122，位于第二半导体柱123远离数据线110的顶面。在一些实施例中，第一导电层112可以为第二晶体管102的源极，第二导电层122可以为第二晶体管102的漏极。
S102：导通第一晶体管101，以调整存储节点143处的电压，以实现对存储节点143的写操作。
可以理解的是，第一区I处的电压受数据线110的影响，第一晶体管101导通时，第一区I与第三区III之间导通，使得第三区III处的电压受到第一区I的影响而发生变化，从而实现对存储节点143处的电压的调整，以实现对存储节点143的写操作。在一个例子中，数据线110传递给第一区I一个高电平，第一晶体管101导通时，第三区III处的电压也变为高电平，使得存储节点143处的电压也变为高电平，此时，存储节点143相当于存储数据“1”。
S103：向第一导电层112和第二导电层122中的一者施加第一电压。
S104：检测第一导电层112和第二导电层122中的另一者处的电压并作为第二电压，基于第二电压与第一电压的差值判断第二半导体柱123的导通程度，基于第二半导体柱123的导通程度判断存储节点143处的电压大小，以实现对存储节点143的读操作。
在一些实施例中，向第一导电层112施加第一电压，检测第二导电层122处的电压并作为第二电压。可以理解的是，存储节点143处电压的大小决定第二半导体柱123的导通程度，存储节点143处的电压越大，第二半导体柱123的导通程度越大。基于第二半导体柱123的导通程度的不同，在第一电压的数值不变的前提下，检测到的第二电压的数值不同，第二半导体柱123的导通程度越高，第二电压的数值越靠近第一电压的数值。因此，可以基于第二电压与第一电压的差值判断第二半导体柱123的导通程度，第二电压与第一电压的差值越小，第二半导体柱123的导通程度越大，存储节点143处的电压越大。
在一个例子中，若存储节点143处的电压为高电平，第二半导体柱123的导通程度高，检测到的第二电压的数值靠近第一电压的数值，即第二电压与第一电压的差值小，判定此时读取的数据为“1”，以实现对存储节点143的读操作。
在一些实施例中，沿第三方向Z上，第一晶体管101包括依次排列的第一区I、第二区II和第三区III，以及环绕第二区II沿第三方向Z延伸的侧壁的栅极结构111，第一区I与数据线110接触连接，第三区III与隔离结构133接触连接，第三区III为存储节点143；实现对存储节点143的写操作，包括：向数据线110施加第三电压，向栅极结构111施加第四电压，以导通第一区I和第三区III之间的传输路径，使第三区III处的电压受到数据线110上的电压的影响，以实现对第三区III的写操作。
可以理解的是，向数据线110施加的第三电压即为想要存储至存储节点143处的电压，向栅极结构111施加的第四电压即为使得第一晶体管101处于导通状态的电压。
在一些实施例中，第一晶体管101可以为GAA晶体管，则可以采用数值较小的第四电压使得第一晶体管101处于导通状态，第二晶体管102可以为单电子晶体管，则存储节点143处的电压发生幅度较小的变化时，第二电压与第一电压就会存在差值，因此，利用第一晶体管101和第二晶体管102实现对数据的写操作和读操作，有利于降低半导体结构工作时的功耗。
综上所述，采用本公开一实施例提供的半导体结构实现对数据的写操作和读操作，有利于在更小的电压变化幅度内实现对数据的存储或读取操作，从而有利于降低半导体结构工作时的功耗。
本公开另一实施例还提供一种半导体结构的制造方法，用于制备本公开一实施例提供的半导体结构。以下将结合图1至图27对本公开另一实施例提供的半导体结构的制造方法进行详细说明。图6至图27为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。需要说明的是，与前述实施例相同或相应的部分在此不再赘述，此外，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图6至图27均为半导体结构的局部结构示意图。
其中，图8为图7所示结构沿第一截面方向AA1的剖面示意图，图9为图7所示结构沿第二截面方向BB1的剖面示意图。需要说明的是，后续将根据表述需要设置沿第一截面方向AA1的剖面示意图以及沿第二截面方向BB1的剖面示意图中的一者或者两者，当仅参考一个附图时，附图为沿第一截面方向 AA1的剖面示意图；当同时参考两个附图时，附图首先为沿第一截面方向AA1的剖面示意图，其次为沿第二截面方向BB1的剖面示意图。
参考图1至图27，半导体结构的制造方法包括如下步骤：
提供初始基底，初始基底的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料。元素半导体材料可以为硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
参考图6至图11，在初始基底中形成数据线110和第一晶体管101，数据线110沿第一方向X延伸，第一晶体管101的一端与数据线110接触连接，剩余初始基底作为基底100。
在一些实施例中，在初始基底中形成数据线110和第一晶体管101可以包括如下步骤：
参考图6，图形化初始基底，以形成沿第一方向X延伸且沿第二方向Y间隔排布的数据线110，以及形成位于数据线110的部分顶面的初始半导体柱153，剩余初始基底作为基底100。
在一些实施例中，图形化初始基底以形成数据线110和初始半导体柱153的过程可以分为对初始基底进行两次刻蚀。第一次刻蚀时，采用具有多个相互分立的且沿第一方向X延伸的第一开口的第一掩膜层对初始基底进行刻蚀，第一开口的长度与后续形成的数据线的长度一致，以形成多个沿第一方向X延伸的第一沟槽；形成填充满第一沟槽的初始第四绝缘层；第二次刻蚀时，采用具有多个相互分立且沿第二方向Y延伸的第二开口的第二掩膜层对初始基底和初始第四绝缘层进行刻蚀，第二开口的长度与后续形成的栅极结构的长度一致，以形成多个沿第二方向Y延伸的第二沟槽108，剩余初始第四绝缘层作为第四绝缘层145。
在一些实施例中，参考图7至图9，沿第三方向Z上，初始半导体柱153包括依次排列的初始第一区163、初始第二区173和初始第三区183；在形成所述栅极结构111之前，制造方法还包括如下步骤：
形成初始第五绝缘层，初始第五绝缘层位于第二沟槽108沿第三方向Z延伸的侧壁，且位于第二沟槽108侧壁的初始第五绝缘层之间具有第三沟槽；参考图7，形成填充满第三沟槽的初始第三隔离层154；去除与初始第三区183接触连接的初始第五绝缘层和第四绝缘层145，以露出初始第三区沿第三方向Z上延伸的所有侧壁；形成覆盖初始第三区沿第三方向Z上延伸的所有侧壁的初始第四隔离层164，且初始第四隔离层164在沿第二方向Y上相邻的初始第三区183之间围成通孔f，通孔f露出的是第四绝缘层145的部分顶面。
其中，继续参考图7至图9，初始第三隔离层154和初始第四隔离层164共同构成支撑骨架，以支撑骨架为掩膜刻蚀初始第五绝缘层和图6所示的第四绝缘层145，剩余初始第五绝缘层作为第五绝缘层155，参考图7，剩余第四绝缘层145位于沿第二方向Y上相邻的数据线110之间，且位于沿第二方向Y上相邻的初始第一区163之间，第五绝缘层155沿第二方向Y延伸，且位于沿第一方向X上相邻的初始第一区163之间。其中，图7中的第四绝缘层145和第五绝缘层155共同构成第一绝缘层115，初始第一区163后续作为第一半导体柱的第一区。
此外，支撑骨架与初始第三区183相接触连接，且部分支撑骨架嵌入第一绝缘层115中。在刻蚀初始第五绝缘层和第四绝缘层145的步骤中，一方面，支撑骨架有对初始半导体柱153起支撑固定的作用，当刻蚀工艺产生对初始半导体柱153的挤压力时，有利于避免初始半导体柱153受挤压发生倾斜或者偏移，以提高半导体结构的稳定性；另一方面，支撑骨架包裹着初始第三区183侧壁，有利于避免刻蚀工艺对初始第三区183造成损伤。在形成第一绝缘层115之后，初始第二区173与初始第三隔离层154之间形成第三间隙g，通孔f和第三间隙g共同组成洞穴结构h，初始第二区173后续作为第一半导体柱的第二区。
参考图10和图11，形成栅极结构111，栅极结构111沿第二方向Y延伸且环绕初始半导体柱153的部分侧壁，部分初始半导体柱153和栅极结构111构成第一晶体管101。
在一些实施例中，形成栅极结构111的步骤包括：在初始第三区183远离基底100的顶面形成第一牺牲层109；以初始半导体柱153的材料为硅为例，对露出的第三间隙g的侧壁，即初始第二区173沿第三方向Z延伸的侧壁进行热氧化处理，以形成栅介质层121，且栅介质层121和初始第三隔离层154之间具有沿第二方向Y延伸的第四间隙；形成填充满第四间隙的栅极131，栅介质层121和栅极131共同构成栅极结构111。
继续参考图11，形成填充满通孔f的初始第二绝缘层165，初始第二绝缘层165为后续形成第二绝缘层的基础，且去除第一牺牲层109。
需要说明的是，上述实施例仅仅是形成第一晶体管101的一种示例，本公开又一实施例提供的制造方法对第一晶体管101的形成方法不做限制，例如，栅介质层也可以通过沉积工艺形成。
参考图12至图27，在第一晶体管101远离数据线110的一侧形成第二晶体管102；其中，第一晶体管101和第二晶体管102中均包括：半导体柱103，半导体柱103位于数据线110的部分顶面且沿第三方向Z延伸；半导体柱103内部具有隔离结构133，沿第二方向Y上，不同区域的隔离结构133在第三方向Z上的厚度不同，且隔离结构133贯穿半导体柱103，第一方向X、第二方向Y和第三方向Z两两相交。
以下对形成隔离结构133和第二晶体管102进行详细说明。
在一些实施例中，沿第三方向Z上，初始半导体柱153包括依次排列的第一区I、第二区II、第 三区III、第四区IV和第五区V，栅极结构111环绕第二区II沿第三方向Z延伸的侧壁。可以理解的是，结合参考图11和图12，第一区I即为初始第一区163，第二区II即为初始第二区173，第三区III、第四区IV和第五区V共同构成初始第三区183。
参考图12至图18，形成隔离结构133的步骤包括：在第一区I、第三区III和第五区V沿第三方向Z延伸的侧壁上形成保护层106，仅露出第四区IV沿第三方向Z延伸的侧壁。
在一些实施例中，形成保护层106包括如下步骤：
参考图10至图13，对初始第三隔离层154和初始第四隔离层164进行刻蚀，以露出第四区IV和第五区V沿第三方向Z上延伸的侧壁，剩余初始第三隔离层154作为第三隔离层134的一部分，剩余初始第四隔离层164作为第四隔离层144。
参考图12和图13，形成第二牺牲层119，第二牺牲层119位于第四区IV和第五区V沿第三方向Z上延伸的侧壁上，且初始第二绝缘层165与第二牺牲层119接触连接，且位于沿第二方向Y上相邻的第四区IV侧壁上的以及邻的第五区V侧壁上的第二牺牲层119之间具有第五间隙i，第五间隙i沿第二方向Y延伸。
参考图14，形成填充满第五间隙i的第五隔离层174。
参考图15和图16，以第五隔离层174和半导体柱103为掩膜，对第二牺牲层119和初始第二绝缘层165进行刻蚀，剩余第二牺牲层119仅环绕第四区IV沿第三方向Z延伸的侧壁，剩余初始第二绝缘层165位于沿第二方向Y上相邻的第四隔离层144之间，以及位于沿第二方向Y上相邻的第二牺牲层119之间。在一些实施例中，第二牺牲层119的材料和初始第二绝缘层165的材料可以相同，可以通过同一刻蚀工艺对第二牺牲层119和初始第二绝缘层165进行同步刻蚀。在实际应用中，第二牺牲层119的材料也可以和初始第二绝缘层165的材料不同，通过不同的刻蚀工艺分别对第二牺牲层119的材料和初始第二绝缘层165进行刻蚀。
参考图17至图18，形成第三牺牲层129，第三牺牲层129环绕第五区V沿第三方向Z延伸的侧壁，且第三牺牲层129与第五隔离层174接触连接；以第三牺牲层129、半导体柱103和第五隔离层174为掩膜，去除剩余的第二牺牲层119，以及去除位于沿第二方向Y上相邻的第二牺牲层119之间的初始第二绝缘层165(参考图16)，剩余初始第二绝缘层165作为第二绝缘层125，以形成仅露出第四区IV沿第三方向Z延伸的侧壁的保护层106和第六间隙k。
可以理解的是，保护层106可以包括：环绕第一区I沿第三方向Z延伸的侧壁的第一绝缘层115，环绕第三区III沿第三方向Z延伸的侧壁的第四隔离层144，以及，环绕第五区V沿第三方向Z延伸的侧壁的第三牺牲层129。此外，在刻蚀第二牺牲层119和初始第二绝缘层165的步骤中，第三牺牲层129和第五隔离层174也可以作为支撑骨架。
参考图19至图20，对露出的第四区IV的侧壁进行氧化处理，以将第四区IV转化为隔离结构133，剩余初始半导体柱153作为半导体柱103；其中，位于隔离结构133靠近数据线110一侧的半导体柱103为第一半导体柱113，位于隔离结构133远离数据线110一侧的半导体柱103为第二半导体柱123，第一区I、第二区II和第三区III构成第一半导体柱113，第五区V作为第二半导体柱123。
在一些实施例中，对露出的第四区IV的侧壁进行氧化处理，包括：对露出的第四区IV的侧壁进行原位水汽生成工艺(ISSG，In-Situ Steam Generation)。原位水汽生成工艺是一种通过高温水汽氛围来生长氧化层的工艺，其生长氧化层的速度较快，并且，采用原位水汽生成方法所生长出的氧化层，相对于采用炉管湿法氧化而获得的氧化层，有着更优的电学性能。
在一些实施例中，参考图21至图26，在形成隔离结构133之后，形成第二晶体管102的步骤可以包括：形成第一导电层112、介质层132和第二导电层122，第一导电层112位于第二半导体柱123沿第三方向Z延伸的至少部分侧壁，第二导电层122位于第二半导体柱123远离数据线110的顶面，介质层132位于第一导电层112和第二半导体柱123之间，以及位于第二导电层122和第二半导体柱123之间。
在一些实施例中，在露出的第二半导体柱123表面形成介质层132，包括：对露出的第二半导体柱123进行氧化处理，以在剩余第二半导体柱123的表面形成介质层132。在一些实施例中，可以采用原位水汽生成工艺对露出的第二半导体柱123进行氧化处理。
在一些实施例中，形成介质层132可以包括如下步骤：
参考图21至图22，去除第二半导体柱123沿第三方向Z延伸的侧壁的至少部分保护层106，以露出第二半导体柱123沿第三方向Z延伸的至少部分侧壁，以及露出第二半导体柱123远离隔离结构133的一侧。
在一些实施例中，在去除第二半导体柱123沿第三方向Z延伸的侧壁的至少部分保护层106之前，还包括：参考图21至图22，形成填充满第六间隙k的初始第三绝缘层175，初始第三绝缘层175为后续形成第三绝缘层135的基础。
继续参考图21至图22，去除第二半导体柱123沿第三方向Z延伸的侧壁的至少部分保护层106的步骤包括：去除环绕第五区V沿第三方向Z延伸的侧壁的第三牺牲层129，以及去除沿第一方向X上相邻的第三牺牲层129之间的第五隔离层174，剩余的第五隔离层174位于沿第一方向X上相邻的初始第三绝缘层175之间。可以理解的是，图21所示的结构中，第五隔离层174和初始第三隔离层154共同构成 第三隔离层134(参考图1)。
参考图23至图24，形成第四牺牲层139，第四牺牲层139位于第五区V沿第三方向Z延伸的侧壁上，且第四牺牲层139与初始第三绝缘层175接触连接，沿第一方向上相邻的第四牺牲层139之间第七间隙；继续参考图23至图24，形成填充满第七间隙的第一隔离层114。
参考图25和图26，以第一隔离层114和第二半导体柱123为掩膜，去除第四牺牲层139和部分初始第三绝缘层175(参考图24)，去除的初始第三绝缘层175位于沿第二方向Y上相邻的第四牺牲层139之间，剩余初始第三绝缘层175作为第三绝缘层135。
继续参考图25和图26，在露出的第二半导体柱123表面形成介质层132。需要说明的是，可以采用对露出的第二半导体柱123表面进行氧化处理的方向形成介质层132，也可以采用沉积工艺，在露出的第二半导体柱123表面形成介质层132。
需要说明的是，介质层132可以一体成型，后续在图25和图26的基础上形成第一导电层112、第二隔离层124以及第二导电层122。
在另一些实施例中，介质层132可以分步形成，以下对分步形成介质层132进行详细说明。
第二半导体柱123除与隔离结构133接触的侧面外，其他表面均露出，保护层106位于第二半导体柱123的其他表面；在形成第二半导体柱123之后，在去除保护层106之前，还包括：形成沿第二方向Y延伸的第一隔离层114，第一隔离层114位于沿第一方向X上间隔排布的相邻第二半导体柱123之间。形成第一隔离层114的方法在前述实施例中已经描述，在此不做赘述。
介质层132包括第一介质层142和第二介质层152，第一介质层142位于第一导电层112和第二半导体柱123之间，第二介质层152位于第二导电层122和第二半导体柱123之间；形成第一介质层142、第一导电层112和第二介质层152包括如下步骤：
参考图27，在露出的第二半导体柱123表面形成初始第一介质层162，第一隔离层114和初始第一介质层162围成第一间隔；在第一间隔中形成初始第一导电层172，初始第一导电层172填充满第一间隔且位初始第一介质层162远离第二半导体柱123的一侧.
结合参考图27、图2和图4，对初始第一导电层172进行回刻蚀，剩余初始第一导电层172作为第一导电层112，在回刻蚀的步骤中，去除位于第二半导体柱123远离隔离结构133的顶面的初始第一介质层162，剩余初始第一介质层162作为第一介质层142，且露出第一介质层142沿第三方向Z延伸的部分侧壁。
参考图2和图4，形成第二隔离层124，第二隔离层124和第一导电层112共同填充满第一间隔；继续参考图2和图4，在第二半导体柱123远离第一介质层142顶面形成第二介质层152。需要说明的是，形成初始第一介质层162和第二介质层152的工艺均可以为ISSG或沉积工艺中的一者。
继续参考图2和图4，在第二介质层152远离基底100的一侧形成第二导电层122，且第二导电层沿第一方向X延伸。
综上所述，本公开又一实施例提供的制造方法形成的半导体结构中，第一晶体管101可以作为动态存储器选择晶体管，第二晶体管102可以作为存储数据的结构，即充当电容结构的角色，如此，可以通过第一晶体管101和第二晶体管102共同实现对数据的存储或读取操作，并且，第一晶体管101可以为GAA晶体管，有利于提高半导体结构的集成密度，第二晶体管102相较于曰前的电容结构具有更小的尺寸，有利于进一步缩小半导体结构整体的尺寸，而且，第二晶体管102相较于曰前的电容结构具有更高的对第一晶体管101中电流变化的感应灵敏度，有利于在更小的电流变化幅度内实现对数据的存储或读取操作，从而有利于降低半导体结构工作时的功耗。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各种改动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (23)

  1. 一种半导体结构，包括：
    基底以及位于所述基底上的数据线，所述数据线沿第一方向延伸；
    位于所述数据线上的第一晶体管和位于所述第一晶体管远离所述数据线的一侧的第二晶体管；
    其中，所述第一晶体管和所述第二晶体管中均包括：半导体柱，所述半导体柱位于所述数据线的部分顶面且沿第三方向延伸；
    所述半导体柱内部具有隔离结构，沿第二方向上，不同区域的所述隔离结构在所述第三方向上的厚度不同，且所述隔离结构贯穿所述半导体柱，所述第一方向、所述第二方向和所述第三方向两两相交。
  2. 如权利要求1所述的半导体结构，其中，所述半导体柱在所述第二方向上具有相对的第一侧和第二侧，沿所述第一侧指向所述半导体柱内部的方向，以及沿所述第二侧指向所述半导体柱内部的方向上，所述隔离结构在所述第三方向上的厚度逐渐减小。
  3. 如权利要求1或2所述的半导体结构，其中，所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，所述第一晶体管包括所述第一半导体柱；所述第一晶体管还包括：
    栅极结构，位于沿所述第二方向延伸且环绕所述第一半导体柱的部分侧壁。
  4. 如权利要求3所述的半导体结构，其中，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第二晶体管包括所述第二半导体柱；所述第二晶体管还包括：
    第一导电层，位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁；
    第二导电层，位于所述第二半导体柱远离所述数据线的顶面；
    介质层，位于所述第一导电层和所述第二半导体柱之间，以及位于所述第二导电层和所述第二半导体柱之间。
  5. 如权利要求4所述的半导体结构，其中，若所述第二晶体管处于导通状态，与所述第一导电层正对且与所述第二导电层正对的所述第二半导体柱构成所述第二晶体管的沟道区，所述第一导电层、所述第二导电层和所述沟道区构成所述第二晶体管的导通电流的传输路径。
  6. 如权利要求4或5所述的半导体结构，其特征在于，所述第二晶体管包括单电子晶体管。
  7. 如权利要求6所述的半导体结构，其中，所述介质层包括第一介质层和第二介质层，所述第一介质层位于所述第一导电层和所述第二半导体柱之间，所述第二介质层位于所述第二导电层和所述第二半导体柱之间；沿所述第三方向上，所述隔离结构的厚度的平均值为第一厚度，所述第二介质层的厚度为第二厚度，沿所述第二方向上，所述第一介质层的厚度为第三厚度，所述第一厚度大于所述第二厚度，且所述第一厚度大于所述第三厚度。
  8. 如权利要求7所述的半导体结构，其中，所述第二厚度等于所述第三厚度。
  9. 如权利要求4所述的半导体结构，其中，所述介质层环绕所述第二半导体柱沿所述第三方向延伸的侧壁；所述第一导电层沿所述第二方向延伸，所述第一导电层与沿所述第二方向间隔排布的多个所述第二半导体柱对应。
  10. 如权利要求4所述的半导体结构，其中，所述第二导电层沿所述第一方向延伸，所述第二导电层与沿所述第一方向间隔排布的多个所述半导体柱对应。
  11. 如权利要求4所述的半导体结构，其中，沿所述第三方向上，所述第一半导体柱包括依次排列的第一区、第二区以及第三区；
    其中，所述第一区与所述数据线接触连接，所述栅极结构环绕所述第二区沿所述第三方向延伸的侧壁，所述第三区与所述隔离结构接触连接；
    所述第三区在所述基底上的正投影为第一正投影，所述第二半导体柱在所述基底上的正投影为第二正投影，所述第二正投影位于所述第一正投影中。
  12. 如权利要求11所述的半导体结构，其中，所述栅极结构包括：栅介质层，沿所述第二方向延伸且环绕所述第一半导体柱的部分侧壁；栅极，环绕所述栅介质层远离所述第二半导体柱的一侧；
    沿所述第二方向上，所述栅介质层的厚度为第四厚度，位于所述第一导电层和所述第二半导体柱之间的所述介质层的厚度为第三厚度，所述第四厚度大于所述第三厚度。
  13. 一种半导体结构的读写控制方法，包括：
    提供如权利要求1至12任一项所述的半导体结构，位于所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第一半导体柱中与所述隔离结构接触的部分区域为存储节点；
    所述第二晶体管包括：第一导电层，位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁；第 二导电层，位于所述第二半导体柱远离所述数据线的顶面；
    导通所述第一晶体管，以调整所述存储节点处的电压，以实现对所述存储节点的写操作；
    所述存储节点处电压的大小决定所述第二半导体柱的导通程度，向所述第一导电层和所述第二导电层中的一者施加第一电压，检测所述第一导电层和所述第二导电层中的另一者处的电压并作为第二电压，基于所述第二电压与所述第一电压的差值判断所述第二半导体柱的导通程度，基于所述第二半导体柱的导通程度判断所述存储节点处的电压大小，以实现对所述存储节点的读操作。
  14. 如权利要求13所述的读写控制方法，其中，沿所述第三方向上，所述第一晶体管包括依次排列的第一区、第二区和第三区，以及环绕所述第二区沿所述第三方向延伸的侧壁的栅极结构，所述第一区与所述数据线接触连接，所述第三区与所述隔离结构接触连接，所述第三区为所述存储节点；
    所述实现对所述存储节点的写操作，包括：
    向所述数据线施加第三电压，向所述栅极结构施加第四电压，以导通所述第一区和所述第三区之间的传输路径，使所述第三区处的电压受到所述数据线上的电压的影响，以实现对所述第三区的写操作。
  15. 一种半导体结构的制造方法，包括：
    提供初始基底；
    在所述初始基底中形成数据线和第一晶体管，所述数据线沿第一方向延伸，所述第一晶体管的一端与所述数据线接触连接，剩余所述初始基底作为基底；
    在所述第一晶体管远离所述数据线的一侧形成第二晶体管；
    其中，所述第一晶体管和所述第二晶体管中均包括：半导体柱，所述半导体柱位于所述数据线的部分顶面且沿第三方向延伸；
    所述半导体柱内部具有隔离结构，沿第二方向上，不同区域的所述隔离结构在所述第三方向上的厚度不同，且所述隔离结构贯穿所述半导体柱，所述第一方向、所述第二方向和所述第三方向两两相交。
  16. 如权利要求15所述的制造方法，其中，所述在所述初始基底中形成数据线和第一晶体管，包括：
    图形化所述初始基底，以形成沿所述第一方向延伸且沿所述第二方向间隔排布的所述数据线，以及形成位于所述数据线的部分顶面的初始半导体柱，剩余所述初始基底作为基底；
    形成栅极结构，所述栅极结构沿所述第二方向延伸且环绕所述初始半导体柱的部分侧壁，部分所述初始半导体柱和所述栅极结构构成所述第一晶体管。
  17. 如权利要求16所述的制造方法，其中，沿所述第三方向上，所述初始半导体柱包括依次排列的第一区、第二区、第三区、第四区和第五区，所述栅极结构环绕所述第二区沿所述第三方向延伸的侧壁；
    形成所述隔离结构的步骤包括：
    在所述第一区、所述第三区和所述第五区沿所述第三方向延伸的侧壁上形成保护层，仅露出所述第四区沿所述第三方向延伸的侧壁；
    对露出的所述第四区的侧壁进行氧化处理，以将所述第四区转化为所述隔离结构，剩余所述初始半导体柱作为所述半导体柱；
    其中，位于所述隔离结构靠近所述数据线一侧的所述半导体柱为第一半导体柱，位于所述隔离结构远离所述数据线一侧的所述半导体柱为第二半导体柱，所述第一区、所述第二区和所述第三区构成所述第一半导体柱，所述第五区作为所述第二半导体柱。
  18. 如权利要求17所述的制造方法，其中，所述对露出的所述第四区的侧壁进行氧化处理，包括：
    对露出的所述第四区的侧壁进行原位水汽生成工艺。
  19. 如权利要求17所述的制造方法，其中，在形成所述隔离结构之后，形成所述第二晶体管的步骤包括：
    形成第一导电层、介质层和第二导电层，所述第一导电层位于所述第二半导体柱沿所述第三方向延伸的至少部分侧壁，所述第二导电层位于所述第二半导体柱远离所述数据线的顶面，所述介质层位于所述第一导电层和所述第二半导体柱之间，以及位于所述第二导电层和所述第二半导体柱之间。
  20. 如权利要求19所述的制造方法，其中，形成所述介质层的步骤包括：
    去除所述第二半导体柱沿所述第三方向延伸的侧壁的至少部分所述保护层，以露出所述第二半导体柱沿所述第三方向延伸的至少部分侧壁，以及露出所述第二半导体柱远离所述隔离结构的一侧；
    在露出的所述第二半导体柱表面形成所述介质层。
  21. 如权利要求20所述的制造方法，其中，所述在露出的所述第二半导体柱表面形成所述介质层，包括：
    对露出的所述第二半导体柱进行氧化处理，以在剩余所述第二半导体柱的表面形成所述介质层。
  22. 如权利要求19所述的制造方法，其中，所述第二半导体柱除与所述隔离结构接触的侧面外，其他表 面均露出，所述保护层位于所述第二半导体柱的其他表面；
    在形成所述第二半导体柱之后，在去除所述保护层之前，还包括：
    形成沿所述第二方向延伸的第一隔离层，所述第一隔离层位于沿所述第一方向上间隔排布的相邻所述第二半导体柱之间。
  23. 如权利要求22所述的制造方法，其中，所述介质层包括第一介质层和第二介质层，所述第一介质层位于所述第一导电层和所述第二半导体柱之间，所述第二介质层位于所述第二导电层和所述第二半导体柱之间；
    形成所述第一介质层、所述第一导电层和所述第二介质层的步骤包括：
    在露出的所述第二半导体柱表面形成初始第一介质层，所述第一隔离层和所述初始第一介质层围成第一间隔；
    在所述第一间隔中形成初始第一导电层，所述初始第一导电层填充满所述第一间隔且位于所述初始第一介质层远离所述第二半导体柱的一侧；
    对所述初始第一导电层进行回刻蚀，剩余所述初始第一导电层作为所述第一导电层，在所述回刻蚀的步骤中，去除位于所述第二半导体柱远离所述隔离结构的顶面的所述初始第一介质层，剩余所述初始第一介质层作为所述第一介质层，且露出所述第一介质层沿所述第三方向延伸的部分侧壁；
    形成第二隔离层，所述第二隔离层和所述第一导电层共同填充满所述第一间隔；
    在所述第二半导体柱远离所述第一介质层顶面形成所述第二介质层。
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