WO2024065106A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

Info

Publication number
WO2024065106A1
WO2024065106A1 PCT/CN2022/121445 CN2022121445W WO2024065106A1 WO 2024065106 A1 WO2024065106 A1 WO 2024065106A1 CN 2022121445 W CN2022121445 W CN 2022121445W WO 2024065106 A1 WO2024065106 A1 WO 2024065106A1
Authority
WO
WIPO (PCT)
Prior art keywords
patterns
array substrate
pattern
substrate
along
Prior art date
Application number
PCT/CN2022/121445
Other languages
English (en)
French (fr)
Inventor
杨国栋
王小元
郭晖
许晨
万彬
陈俊明
刘艳
蒲巡
朱嫄媛
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/121445 priority Critical patent/WO2024065106A1/zh
Publication of WO2024065106A1 publication Critical patent/WO2024065106A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • TFT Thin film transistors
  • the present application provides an array substrate, and the technical solution is as follows:
  • an array substrate comprising:
  • a substrate having a display area and a peripheral area surrounding the display area, the peripheral area at least including a row driving area extending along a first direction;
  • a plurality of thin film transistors arranged in the row driving area
  • the plurality of first patterns being located at least on one side of the row driving region, and the plurality of first patterns being arranged at intervals from the row driving region along the first direction, and the plurality of first patterns being located on the same side of the row driving region being arranged in an array;
  • the thin film transistor includes: a gate, a gate insulation layer, an active layer and a source and drain layer stacked in sequence in a direction away from the substrate, the source and drain layer includes a source and a drain arranged at intervals; the multiple first patterns are located in the same layer as at least one of the source and the drain.
  • the shape of the orthographic projection of the first pattern on the substrate is a rectangle.
  • the shape of the orthographic projection of the first pattern on the substrate is a square.
  • one of the two vertical boundaries in the first pattern is parallel to the first direction, and the other boundary is parallel to the second direction;
  • the second direction is parallel to an arrangement direction of the display area and the row drive area, and the first direction intersects with the second direction.
  • the length of the first pattern along the first direction is m1
  • the distance between any two adjacent first patterns along the first direction is n1
  • the ratio of m1/n1 ranges from 0.9 to 1.9
  • the length of the first pattern along the second direction is m2
  • the distance between any two adjacent first patterns along the second direction is n2
  • the ratio of m2/n2 ranges from 0.9 to 1.9.
  • the minimum distance between the orthographic projections of the plurality of first patterns on the substrate and the orthographic projections of other structures in the array substrate on the substrate ranges from 15 micrometers to 30 micrometers.
  • the peripheral area includes two row drive areas extending along the first direction, and the two row drive areas are respectively located on two sides of the display area;
  • the plurality of first patterns are located at two sides of each row driving region.
  • the peripheral area further includes a fan-out area extending along a second direction, and the second direction is parallel to an arrangement direction of the row drive area and the display area;
  • the array substrate further includes:
  • a plurality of second patterns wherein the plurality of second patterns are located at least on one side of the fan-out region, and the plurality of second patterns and the fan-out region are arranged at intervals along the second direction, and the plurality of second patterns located on the same side of the fan-out region are arranged in an array, and the second patterns are different from the first patterns in at least one of shape and size;
  • the plurality of second patterns include: a plurality of first-type second patterns and a plurality of second-type second patterns, the plurality of first-type second patterns and the gate are located at the same layer, and the plurality of second-type second patterns and the source and the drain are located at the same layer.
  • the orthographic projections of the plurality of first-type second patterns on the substrate do not overlap with the orthographic projections of the plurality of second-type second patterns on the substrate.
  • the orthographic projections of the plurality of first-type second patterns on the substrate and the orthographic projections of the plurality of second-type second patterns on the substrate are arranged alternately in the second direction.
  • the plurality of first-type second patterns and the plurality of second-type second patterns are the same in number and correspond one to one;
  • the orthographic projection of each of the first-type second patterns on the substrate overlaps with the orthographic projection of a corresponding one of the second-type second patterns on the substrate.
  • a shape of an orthographic projection of the second pattern on the substrate is a rectangle, and a length of the second pattern along the first direction is greater than a length of the second pattern along the second direction.
  • one of the two vertical boundaries in the second pattern is parallel to the first direction, and the other boundary is parallel to the second direction.
  • the length of the second pattern along the first direction is r1
  • the distance between any two adjacent second patterns along the first direction is s1
  • the ratio of r1/s1 ranges from 0.9 to 1.9;
  • the length of the second pattern along the second direction is r2, the distance between any two adjacent second patterns along the second direction is s2, and the ratio of r2/s2 ranges from 0.9 to 1.9.
  • a minimum distance between an orthographic projection of the second pattern on the substrate and an orthographic projection of other structures in the array substrate on the substrate ranges from 75 micrometers to 100 micrometers.
  • the multiple second patterns are located on both sides of the fan-out area.
  • the plurality of thin film transistors located in the row driving region constitute a plurality of cascaded shift register units, and each of the shift register units includes 18 thin film transistors and a storage capacitor.
  • the active layer of the thin film transistor is made of metal oxide material.
  • a display panel is provided, characterized in that the display panel comprises a plurality of pixel units and the array substrate as described in the above aspect;
  • the plurality of pixel units are located in a display area of the array substrate.
  • FIG1 is a curve diagram showing the relationship between resistance and voltage of an active layer of a thin film transistor before and after being conductively conductive, according to an embodiment of the present application;
  • FIG. 2 is a schematic diagram of a display effect after an active layer of a thin film transistor in an array substrate provided by an embodiment of the present application is conductive;
  • FIG3 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • FIG4 is a top view of a substrate provided in an embodiment of the present application.
  • FIG5 is a partial schematic diagram of the array substrate provided in an embodiment of the present application in area A of FIG4 ;
  • FIG6 is a schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.
  • FIG7 is a top view of a first pattern provided in an embodiment of the present application.
  • FIG8 is a partial schematic diagram of the array substrate provided in an embodiment of the present application in the area B in FIG4 ;
  • FIG9 is a partial schematic diagram of an array substrate provided in an embodiment of the present application in area C of FIG4 ;
  • FIG10 is a schematic cross-sectional view of FIG9 along the DD direction
  • FIG11 is a cross-sectional scanning electron microscope (SEM) image of FIG9 along the DD direction;
  • FIG12 is a cross-sectional schematic diagram of a second pattern provided in an embodiment of the present application.
  • FIG13 is a top view of a second pattern provided in an embodiment of the present application.
  • FIG14 is a circuit structure diagram of a shift register unit provided in an embodiment of the present application.
  • FIG15 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • a thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source-drain electrode layer stacked in sequence in a direction away from a substrate.
  • the source-drain electrode layer includes a source electrode and a drain electrode arranged at intervals.
  • the active layer of the thin film transistor is easily conductive during the preparation process, the characteristics of the thin film transistor may be abnormal, which may result in a low yield of the array substrate and a poor display effect of the display panel.
  • oxide thin film transistors are far fewer than those of low-temperature polysilicon thin film transistors, and the mobility of oxide thin film transistors is much higher than that of amorphous silicon thin film transistors.
  • Oxide thin film transistors also have good bending performance and low process temperature, and can be used to make flexible substrates. Therefore, oxide thin film transistors have good development prospects in the future of flexible display.
  • oxide thin film transistors are more likely to be conductive during the preparation of the array substrate, resulting in abnormal characteristics of the oxide thin film transistors, leading to abnormal display of the display panel, which greatly affects the yield and low-cost advantage of the oxide display panel.
  • oxide display panel can be used to indicate that the thin film transistors in the display panel are oxide thin film transistors.
  • the active layer of the thin film transistor in the row drive area is easily conductive.
  • the resistance is 10 10 ⁇ (ohm), and as the voltage increases, the resistance gradually decreases until the thin film transistor is turned on.
  • the resistance is 10 4 ⁇ , and the resistance does not change with the increase of voltage, which leads to the failure of the thin film transistor. Therefore, referring to Figure 2, the display effect of the display panel is poor, and horizontal stripes appear (weak dark lines appear every four rows).
  • 1.00E+01 is used to represent 10 1
  • 1.00E+02 is used to represent 10 2
  • 1.00E+3 is used to represent 10 3 , and so on, which will not be described in detail.
  • FIG3 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application.
  • the array substrate 10 may include a substrate 101 , a plurality of thin film transistors 102 and a plurality of first patterns 103 .
  • FIG4 is a top view of a substrate provided in an embodiment of the present application.
  • the substrate 101 also has a display area 101a and a peripheral area 101b surrounding the display area 101a.
  • the peripheral area 101b at least includes a row drive area 101b1 extending along a first direction X.
  • the thin film transistor 102 is at least located in the row drive area 101b1.
  • the thin film transistor 102 can also be located in the display area 101a.
  • the thin film transistor 102 located in the row driving area 101b1 can constitute the array substrate row driving (gate driven on array, GOA) circuit of the array substrate 10.
  • the thin film transistor 102 located in the display area 101a can constitute the driving circuit in the array substrate 10 for driving the light emitting unit to emit light.
  • Fig. 5 is a partial schematic diagram of the array substrate provided in the embodiment of the present application in the A area in Fig. 4.
  • the plurality of first patterns 103 are located at least on one side of the row driving region 101b1, and the plurality of first patterns 103 are arranged at intervals with the row driving region 101b1 along the first direction X, and the plurality of first patterns 103 on the same side of the row driving region 101b1 are arranged in an array.
  • FIG6 is a schematic diagram of the structure of a thin film transistor provided in an embodiment of the present application.
  • the thin film transistor 102 includes: a gate 1021, a gate insulating layer 1022, an active layer 1023, and a source-drain layer 1024 stacked in sequence in a direction away from the substrate 101.
  • the source-drain layer 1024 includes a source 10241 and a drain 10242 arranged at intervals.
  • the plurality of first patterns 103 included in the array substrate 10 are located in the same layer as at least one of the source 10241 and the drain 10242 of the thin film transistor 102.
  • the plurality of first patterns 103 and at least one of the source 10241 and the drain 10242 are located in the same layer, which may mean that the plurality of first patterns 103 can be prepared by using the same material and the same patterning process as at least one of the source 10241 and the drain 10242.
  • the source 10241 and the drain 10242 are prepared by using the same material and the same patterning process.
  • the array substrate 10 there is usually a large blank area (i.e., an area where no wiring and thin film transistors are set) on one side of the row driving area 101b1. Therefore, a plurality of first patterns 103 are designed on one side of the row driving area 101b1 to reduce the consumption of etching solution when etching the source and drain film layer to form the source 10241 and the drain 10242 of the thin film transistor 102.
  • the pattern of the source and drain film layer on one side of the row driving region 101b1 can be more uniform with the pattern of the source and drain film layer above the active layer in the display region.
  • an embodiment of the present application provides an array substrate, wherein a plurality of first patterns are designed on one side of a row driving region of the array substrate, thereby ensuring that there is sufficient etching solution to etch the source and drain electrodes of the thin-film transistors in the row driving region and the display region, thereby avoiding residual material of the source and drain film layers due to less etching solution in the row driving region and the display region, avoiding the channel of the thin-film transistor being turned on due to the material of the source and drain film layers remaining above the active layer, avoiding the active layer of the thin-film transistor being conductive, ensuring the characteristics of the thin-film transistor, and improving the yield of the array substrate and the display effect of the display panel.
  • an electrostatic discharge (ESD) unit is designed on one side of the row driving area 101b1.
  • the present application removes the ESD unit in this area, designs a plurality of first patterns 103, and designs the ESD unit in the peripheral area 101b on the upper side of the display area 101a (the side of the display area 101a in the peripheral area away from the fan-out area 101b2). For example, removing the ESD unit can be used to adjust the mask without increasing the mask cost and process difficulty.
  • the active layer of the thin film transistor 102 may be made of a metal oxide material, that is, the thin film transistor 102 may be an oxide thin film transistor.
  • the source-drain film layer may include a first film layer, a second film layer and a third film layer stacked in sequence.
  • the material of the first film layer and the material of the third film layer may be molybdenum-niobium alloy (MoNb), and the material of the second film layer may be copper (Cu). That is, the source-drain film layer may be a stacked structure of MoNb/Cu/MoNb.
  • the shape of the orthographic projection of the first pattern 103 on the substrate 101 is a rectangle.
  • the rectangle may be a right-angled rectangle, a chamfered rectangle or a rounded rectangle.
  • the shape of the orthographic projection of the first pattern 103 on the substrate 101 is a square. That is, the orthographic projection of the first pattern 103 on the substrate 101 includes at least two vertical boundaries of equal length.
  • first pattern 103 is parallel to the first direction X, and the other boundary is parallel to the second direction Y.
  • the second direction Y is parallel to the arrangement direction of the display area 101a and the row drive area 101b1.
  • the first direction X and the second direction Y intersect, for example, perpendicularly.
  • a plurality of first patterns 103 are arranged in an array in the first direction X and the second direction Y.
  • the length of the first pattern 103 along the first direction X is m1
  • the distance between any two first patterns 103 adjacent to each other along the first direction X is n1
  • the ratio of m1/n1 ranges from 0.9 to 1.9.
  • the length of the first pattern 103 along the second direction Y is m2
  • the distance between any two first patterns 103 adjacent to each other along the second direction Y is n2
  • the ratio of m2/n2 ranges from 0.9 to 1.9.
  • the length m1 of the first pattern 103 along the first direction X and the length m2 along the second direction Y are both in the range of 12 ⁇ m (micrometers) to 15 ⁇ m.
  • the distance n1 between any two first patterns 103 adjacent along the first direction X and the distance n2 between any two first patterns 103 adjacent along the second direction Y are both in the range of 8 ⁇ m to 13 ⁇ m.
  • the shape of the orthographic projection of the first pattern 103 on the substrate 101 can be a rectangle with four chamfered corners, that is, the shape of the orthographic projection of the first pattern 103 on the substrate 101 is a chamfered rectangle.
  • the minimum distance between the orthographic projections of the plurality of first patterns 103 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 15 ⁇ m to 30 ⁇ m. That is, the distance between the plurality of first patterns 103 and other structures in the array substrate 10 can be relatively large to avoid the plurality of first patterns 103 from affecting other structures in the array substrate 10.
  • the other structures may be traces in the array substrate 10 for transmitting signals, or may be thin film transistors.
  • the peripheral region 101b may include two row drive regions 101b1 extending along the first direction X, and the two row drive regions 101b1 are respectively located on both sides of the display region 101a.
  • a plurality of first patterns 103 are located on both sides of each row drive region 101b1. That is, the plurality of first patterns 103 may include a plurality of first patterns 103 located in the first region, a plurality of first patterns 103 located in the second region, a plurality of first patterns 103 located in the third region, and a plurality of first patterns 103 located in the fourth region.
  • the plurality of first patterns 103 located in the first region are arranged in an array in the upper left corner region of the substrate 101.
  • the plurality of first patterns 103 located in the second region are arranged in an array in the lower left corner region of the substrate 101
  • the plurality of first patterns 103 located in the third region are arranged in an array in the upper right corner region of the substrate 101
  • the plurality of first patterns 103 located in the fourth region are arranged in an array in the lower right corner region of the substrate 101.
  • the peripheral area 101b may also include a fan-out area 101b2 extending along the second direction Y.
  • FIG. 9 is a partial schematic diagram of the array substrate provided in the C area of FIG. 4 in an embodiment of the present application.
  • the array substrate 10 also includes: a plurality of second patterns 104.
  • the plurality of second patterns 104 are at least located on one side of the fan-out area 101b2, and the plurality of second patterns 104 are arranged at intervals with the fan-out area 101b2 along the second direction Y, and the plurality of second patterns 104 located on the same side of the fan-out area 101b2 are arranged in an array.
  • the second pattern 104 is different from the first pattern 103 in at least one of the shape and size.
  • the shape of the orthographic projection of the second pattern 104 on the substrate 101 may be a rectangle.
  • FIG10 is a cross-sectional view of FIG9 along the DD direction.
  • FIG11 is an electron microscope schematic view of FIG9 along the DD direction.
  • the plurality of second patterns 104 include: a plurality of first-type second patterns 104a and a plurality of second-type second patterns 104b.
  • the plurality of first-type second patterns 104a are located in the same layer as the gate 1021, and the plurality of second-type second patterns 104b are located in the same layer as the source 10241 and the drain 10242.
  • the plurality of first-type second patterns 104a and the gate 1021 being located in the same layer may mean that the plurality of first-type second patterns 104a and the gate 1021 are made of the same material and are prepared by the same patterning process.
  • the plurality of second-type second patterns 104b and the source 10241 and the drain 10242 being located in the same layer may mean that the plurality of second-type second patterns 104b and the source 10241 and the drain 10242 are made of the same material and are prepared by the same patterning process.
  • a plurality of second patterns 104 are designed in the fan-out area 101b2, which can also reduce the consumption of etching solution, thereby avoiding the residual material of the source and drain film layer due to less etching solution in the row driving area 101b1 and the display area 101a, avoiding the channel of the thin film transistor 102 from being turned on due to the residual source and drain film material above the active layer 1023, avoiding the active layer 1023 of the thin film transistor 102 from being conductorized, ensuring the characteristics of the thin film transistor 102, and improving the display effect and yield of the array substrate.
  • the fan-out region 101b2 of the array substrate 10 is usually designed with a plurality of signal lines, and a portion of at least one of the plurality of signal lines may be located at the same layer as the gate 1021, and another portion of the ...
  • the orthographic projections of the plurality of first-type second patterns 104a on the substrate 101 do not overlap with the orthographic projections of the plurality of second-type second patterns 104b on the substrate 101 , thereby avoiding mutual influence between the plurality of first-type second patterns 104a and the plurality of second-type second patterns 104b and ensuring the yield of the array substrate 10 .
  • the orthographic projections of a plurality of first-type second patterns 104 a on the substrate 101 and the orthographic projections of a plurality of second-type second patterns 104 b on the substrate 101 are arranged alternately in the second direction Y.
  • an angle ⁇ between a connecting line between a first-type second pattern 104a and a second-type second pattern 104b closest to the first-type second pattern 104a and the supporting surface of the base substrate 101 may range from 25 degrees to 60 degrees.
  • angle ⁇ between the boundary slope surface of each second pattern 104 and the supporting surface of the base substrate 101 ranges from 25 degrees to 60 degrees.
  • the number of the plurality of first-type second patterns 104a and the plurality of second-type second patterns 104b are the same and correspond one to one.
  • the orthographic projection of each first-type second pattern 104a on the substrate 101 overlaps with the orthographic projection of a corresponding second-type second pattern 104b on the substrate 101.
  • the orthographic projection of the second pattern 104 on the substrate 101 is a rectangle, and the length of the second pattern 104 along the first direction X may be greater than the length along the second direction Y.
  • the second pattern 104 may be a strip structure extending along the first direction X.
  • one of the two vertical boundaries of the first pattern 103 is parallel to the first direction X, and the other boundary is parallel to the second direction Y.
  • the second direction Y is parallel to the arrangement direction of the display area 101a and the row drive area 101b1. That is, the plurality of first patterns 103 are arranged in an array in the first direction X and the second direction Y.
  • the length of the second pattern 104 along the first direction X is r1
  • the distance between any two second patterns 104 adjacent along the first direction X is s1
  • the ratio of r1/s1 ranges from 0.9 to 1.9.
  • the length of the second pattern 104 along the second direction X is r2
  • the distance between any two second patterns 102 adjacent along the second direction Y is s2
  • the ratio of r2/s2 ranges from 0.9 to 1.9.
  • the length r1 of the second pattern 104 along the first direction X ranges from 50 ⁇ m to 100 ⁇ m
  • the length r2 of the second pattern 104 along the second direction Y ranges from 2 ⁇ m to 10 ⁇ m.
  • the length r1 of the second pattern 104 along the first direction X is not too large (the second pattern 104 may be a short rod-shaped structure), which can avoid the accumulation of charges at the second pattern 104 due to the excessive length of the second pattern 104, thereby avoiding the risk of electrostatic discharge.
  • a distance s1 between any two second patterns 104 adjacent to each other in the first direction X ranges from 50 ⁇ m to 100 ⁇ m
  • a distance s2 between any two second patterns 104 adjacent to each other in the second direction Y ranges from 3 ⁇ m to 10 ⁇ m.
  • the shape of the orthographic projection of the second pattern 104 on the substrate 101 may be a rectangle with four chamfered corners, that is, the shape of the orthographic projection of the second pattern 104 on the substrate 101 may be a chamfered rectangle.
  • the minimum distance between the orthographic projections of the plurality of second patterns 104 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 75 ⁇ m to 100 ⁇ m. That is, the distance between the plurality of second patterns 104 and other structures in the array substrate 10 can be relatively large to avoid the plurality of second patterns 104 affecting other structures in the array substrate 10.
  • the other structures may be traces for transmitting signals in the array substrate 10, or may be thin film transistors.
  • the plurality of second patterns 104 may be located on both sides of the fan-out region 101b2.
  • the plurality of second patterns 104 may include a plurality of second patterns 104 located in the fifth region and a plurality of second patterns 104 located in the sixth region.
  • the fifth region and the sixth region are located on both sides of the fan-out region 101b2, respectively.
  • the plurality of thin film transistors 102 located in the row driving region 101b1 may constitute a plurality of cascaded shift register units.
  • Each shift register unit may include 18 thin film transistors 102 and a storage capacitor.
  • the shift register unit may also be other structures, which are not limited in the embodiment of the present application.
  • FIG14 is a circuit structure diagram of a shift register unit provided in an embodiment of the present application.
  • the shift register unit 01 may include: an input circuit 011, a first reset circuit 012, an output circuit 013, a second reset circuit 014, a first pull control circuit 015, a first pull circuit 016, a second pull control circuit 017, a second pull circuit 018, and a storage capacitor C.
  • the input circuit 011 includes: a first transistor M1, a gate and a first electrode of the first transistor M1 are connected to the signal input terminal INPUT, and a second electrode of the first transistor M1 is connected to the pull-up node PU.
  • the first reset circuit 012 includes: a second transistor M2 and a third transistor M4.
  • the gate of the second transistor M2 is connected to the first reset signal terminal RES1, the first electrode of the second transistor M2 is connected to the pull-up node PU, and the second electrode of the second transistor M2 is connected to the first fixed voltage terminal LVGL.
  • the gate of the third transistor M4 is connected to the first reset signal terminal RES1, the first electrode of the third transistor M4 is connected to the first signal output terminal OUT1, and the second electrode of the third transistor M4 is connected to the second fixed voltage terminal VGL.
  • the output circuit 013 includes: a first output transistor M3 and a second output transistor M11.
  • the gate of the first output transistor M3 is connected to the pull-up node PU, the first electrode of the first output transistor M3 is connected to the clock signal terminal CLK, and the second electrode of the first output transistor M3 is connected to the first signal output terminal OUT1.
  • the gate of the second output transistor M11 is connected to the pull-up node PU, the first electrode of the second output transistor M11 is connected to the clock signal terminal CLK, and the second electrode of the second output transistor M11 is connected to the second signal output terminal OUT2.
  • the second reset circuit 014 comprises: a fourth transistor M15, a gate of the fourth transistor M15 is connected to the second reset signal terminal RES2, a first electrode of the fourth transistor M15 is connected to the pull-up node PU, and a second electrode of the fourth transistor M15 is connected to the first fixed voltage terminal LVGL;
  • the first pull control circuit 015 includes: a fifth transistor M5A, a sixth transistor M6A and a seventh transistor M7A.
  • the gate and the first electrode of the fifth transistor M5A are connected to the first control terminal VDDo, and the second electrode of the fifth transistor M5A is connected to the first pull-down node PD1.
  • the gate of the sixth transistor M6A is connected to the pull-up node PU, the first electrode of the sixth transistor M6A is connected to the first pull-down node PD1, and the second electrode of the sixth transistor M6A is connected to the first fixed voltage terminal LVGL.
  • the gate of the seventh transistor M7A is connected to the signal input terminal INPUT, the first electrode of the seventh transistor M7A is connected to the first pull-down node PD1, and the second electrode of the seventh transistor M7A is connected to the first fixed voltage terminal LVGL.
  • the first pull-up circuit 016 includes an eighth transistor M8A, a ninth transistor M12A, and a tenth transistor M13A.
  • the gate of the eighth transistor M8A is connected to the first pull-down node PD1, the first electrode of the eighth transistor M8A is connected to the pull-up node PU, and the second electrode of the eighth transistor M8A is connected to the first fixed voltage terminal LVGL.
  • the gate of the ninth transistor M12A is connected to the first pull-down node PD1, the first electrode of the ninth transistor M12A is connected to the second signal output terminal OUT2, and the second electrode of the ninth transistor M12A is connected to the first fixed voltage terminal LVGL.
  • the gate of the tenth transistor M13A is connected to the first pull-down node PD1, the first electrode of the tenth transistor M13A is connected to the first signal output terminal OUT1, and the second electrode of the tenth transistor M13A is connected to the second fixed voltage terminal VGL.
  • the second pull control circuit 017 includes: an eleventh transistor M5B, a twelfth transistor M6B and a thirteenth transistor M7B.
  • the gate and the first electrode of the eleventh transistor M5B are connected to the second control terminal VDDe, and the second electrode of the fifth transistor M5A is connected to the second pull-down node PD2.
  • the gate of the twelfth transistor M6B is connected to the pull-up node PU, the first electrode of the twelfth transistor M6B is connected to the second pull-down node PD2, and the second electrode of the twelfth transistor M6B is connected to the first fixed voltage terminal LVGL.
  • the gate of the thirteenth transistor M7B is connected to the signal input terminal INPUT, the first electrode of the thirteenth transistor M7B is connected to the second pull-down node PD2, and the second electrode of the thirteenth transistor M7B is connected to the first fixed voltage terminal LVGL.
  • the second pull-up circuit 018 includes: a fourteenth transistor M8B, a fifteenth transistor M12B, and a sixteenth transistor M13B.
  • the gate of the fourteenth transistor M8B is connected to the second pull-down node PD2
  • the first electrode of the fourteenth transistor M8B is connected to the pull-up node PU
  • the second electrode of the fourteenth transistor M8B is connected to the first fixed voltage terminal LVGL
  • the gate of the fifteenth transistor M12B is connected to the second pull-down node PD2
  • the first electrode of the fifteenth transistor M12B is connected to the second signal output terminal OUT2
  • the second electrode of the fifteenth transistor M12B is connected to the first fixed voltage terminal LVGL.
  • the gate of the sixteenth transistor M13B is connected to the second pull-down node PD2, the first electrode of the sixteenth transistor M13B is connected to the first signal output terminal OUT1, and the second electrode of the sixteenth transistor M13B is connected to the second fixed voltage terminal VGL.
  • a first electrode of the storage capacitor C is connected to the pull-up node PU, and a second electrode of the storage capacitor C is connected to the first signal output terminal OUT1.
  • one of the first electrode and the second electrode of each transistor is a source electrode, and the other is a drain electrode.
  • the thickness of the source and drain layer 1024 can be 350 nm (nanometers), and the thickness of the gate 1021 can be 345 nm.
  • the thickness of the source and drain layer 1024 and the thickness of the gate 1021 can also be other thicknesses, which are not limited in the embodiment of the present application.
  • an embodiment of the present application provides an array substrate, wherein a plurality of first patterns are designed on one side of a row driving region of the array substrate, thereby ensuring that there is sufficient etching solution to etch the source and drain electrodes of the thin-film transistors in the row driving region and the display region, thereby avoiding residual material of the source and drain film layers due to less etching solution in the row driving region and the display region, avoiding the channel of the thin-film transistor being turned on due to the material of the source and drain film layers remaining above the active layer, avoiding the active layer of the thin-film transistor being conductive, ensuring the characteristics of the thin-film transistor, and improving the yield of the array substrate and the display effect of the display panel.
  • FIG15 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • the display panel 01 may include a plurality of light-emitting units 20 and an array substrate 10 as provided in the above embodiment.
  • the plurality of light-emitting units 20 may be located in a display area 101a of the array substrate 10.
  • the light-emitting units 20 shown in FIG15 are only used to indicate that the light-emitting units 20 are arranged in the display area 101a, and are not used to indicate the actual shape of the light-emitting units 20.
  • Fig. 16 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the display device may include: a power supply component 02 and a display panel 01 provided in the above embodiment.
  • the power supply component 02 may be used to supply power to the display panel 01 .
  • the display device can be: a liquid crystal display device (LCD), an organic light-emitting diode (OLED) display device, electronic paper, a low-temperature polysilicon (LTPS) display device, a low-temperature polysilicon oxide (LTPO) display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • LCD liquid crystal display device
  • OLED organic light-emitting diode
  • LTPS low-temperature polysilicon
  • LTPO low-temperature polysilicon oxide
  • the transistors in all embodiments of the present application can be thin film transistors.
  • the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present application, the source is referred to as the first level and the drain is referred to as the second level. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present application may include any one of an N-type switching transistor and a P-type switching transistor, wherein the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level, and the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.
  • first, second, etc. may be used to describe various elements, components, regions, layers and/or parts in this article, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed above may be referred to as a second element, component, region, layer or part without departing from the teaching of the present disclosure.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly.
  • a layer is referred to as "between two layers", it can be the only layer between the two layers, or one or more intermediate layers may also be present.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种阵列基板及显示面板，涉及显示技术领域。该阵列基板的行驱动区域的一侧设计有多个第一图案，保证具有足够的刻蚀液以刻蚀形成行驱动区域以及显示区域的薄膜晶体管的源极和漏极，进而避免因行驱动区域和显示区域的刻蚀液较少而导致的源漏极膜层的材料残留，避免薄膜晶体管的沟道因有源层上方残留的源漏极膜层的材料而导通，避免薄膜晶体管的有源层被导体化，保证薄膜晶体管的特性，提高阵列基板的良率以及显示面板的显示效果。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板及显示面板。
背景技术
薄膜晶体管(thin film transistor，TFT)因其工艺步骤少，迁移率高，具有较好的弯曲性能以及工艺温度低等优势被广泛用于柔性显示面板。
发明内容
本申请提供了一种阵列基板，所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：
衬底，所述衬底具有显示区域，以及围绕所述显示区域的周边区域，所述周边区域至少包括沿第一方向延伸的行驱动区域；
所述行驱动区域内设置的多个薄膜晶体管；
以及，多个第一图案，所述多个第一图案至少位于所述行驱动区域的一侧，且所述多个第一图案与所述行驱动区域沿所述第一方向间隔排布，位于所述行驱动区域的同一侧的多个第一图案阵列排布；
其中，所述薄膜晶体管包括：沿远离所述衬底的方向依次层叠的栅极、栅极绝缘层、有源层以及源漏极层，所述源漏极层包括间隔设置的源极和漏极；所述多个第一图案与所述源极和所述漏极中的至少一个位于同层。
可选的，所述第一图案在所述衬底上的正投影的形状为矩形。
可选的，所述第一图案在所述衬底上的正投影的形状为正方形。
可选的，所述第一图案中垂直的两条边界中的其中一条边界平行于所述第一方向，另一条边界平行于第二方向；
所述第二方向平行于所述显示区域和所述行驱动区域的排布方向，所述第一方向和所述第二方向相交。
可选的，所述第一图案沿第一方向的长度为m1，沿所述第一方向相邻的任 意两个所述第一图案之间的距离为n1，m1/n1的比值范围为0.9至1.9；所述第一图案沿第二方向的长度为m2，沿所述第二方向相邻的任意两个所述第一图案之间的距离为n2，m2/n2的比值范围为0.9至1.9。
可选的，所述多个第一图案在所述衬底上的正投影与所述阵列基板中其他结构在所述衬底上的正投影之间的最小距离的范围为15微米至30微米。
可选的，所述周边区域包括沿所述第一方向延伸的两个所述行驱动区域，两个所述行驱动区域分别位于所述显示区域的两侧；
其中，所述多个第一图案位于每个所述行驱动区域的两侧。
可选的，所述周边区域还包括沿第二方向延伸的扇出区域，所述第二方向平行于所述行驱动区域和所述显示区域的排布方向；所述阵列基板还包括：
多个第二图案，所述多个第二图案至少位于所述扇出区域的一侧，且所述多个第二图案与所述扇出区域沿所述第二方向间隔排布，位于所述扇出区域的同一侧的多个第二图案阵列排布，所述第二图案与所述第一图案的形状和尺寸中的至少一种不同；
其中，所述多个第二图案包括：多个第一类第二图案和多个第二类第二图案，所述多个第一类第二图案与所述栅极位于同层，所述多个第二类第二图案与所述源极和所述漏极位于同层。
可选的，所述多个第一类第二图案在所述衬底上的正投影与所述多个第二类第二图案在所述衬底上的正投影不重叠。
可选的，所述多个第一类第二图案在所述衬底上的正投影与所述多个第二类第二图案在所述衬底上的正投影在所述第二方向上交错排布。
可选的，所述多个第一类第二图案与所述多个第二类第二图案的数量相同，且一一对应；
每个所述第一类第二图案在所述衬底上的正投影与对应的一个所述第二类第二图案在所述衬底上的正投影重叠。
可选的，所述第二图案在所述衬底上的正投影的形状为矩形，且所述第二图案沿所述第一方向的长度大于沿所述第二方向的长度。
可选的，所述第二图案中垂直的两条边界中的其中一条边界平行于所述第一方向，另一条边界平行于所述第二方向。
可选的，所述第二图案沿所述第一方向的长度为r1，沿所述第一方向相邻 的任意两个所述第二图案之间的距离为s1，r1/s1的比值范围为0.9至1.9；
所述第二图案沿所述第二方向的长度为r2，沿所述第二方向相邻的任意两个所述第二图案之间的距离为s2，r2/s2的比值范围为0.9至1.9。
可选的，所述第二图案在所述衬底上的正投影与所述阵列基板中其他结构在所述衬底上的正投影之间的最小距离的范围为75微米至100微米。
可选的，所述多个第二图案位于所述扇出区域的两侧。
可选的，位于所述行驱动区域的多个所述薄膜晶体管构成多个级联的移位寄存器单元，每个所述移位寄存器单元包括18个所述薄膜晶体管以及一个存储电容。
可选的，所述薄膜晶体管的有源层为金属氧化物材料。
另一方面，提供了一种显示面板，其特征在于，所述显示面板包括包括多个像素单元以及如上述方面所述的阵列基板；
其中，所述多个像素单元位于所述阵列基板的显示区域。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。本申请以氧化物薄膜晶体管为例进行说明。
图1是本申请实施例提供的一种薄膜晶体管的有源层被导体化之前以及导体化之后的电阻和电压的关系曲线图；
图2是本申请实施例提供的一种阵列基板中薄膜晶体管的有源层被导体化之后的显示效果示意图；
图3是本申请实施例提供的一种阵列基板的结构示意图；
图4是本申请实施例提供的一种衬底的俯视图；
图5是本申请实施例提供的阵列基板在图4中A区域的局部示意图；
图6是本申请实施例提供的一种薄膜晶体管的结构示意图；
图7是本申请实施例提供的一种第一图案的俯视图；
图8是本申请实施例提供的阵列基板在图4中B区域的局部示意图；
图9是本申请实施例提供的阵列基板在图4的C区域的局部示意图；
图10是图9沿DD方向的截面示意图；
图11是图9沿DD方向的截面扫描电镜(SEM)图；
图12是本申请实施例提供的一种第二图案的截面示意图；
图13是本申请实施例提供的一种第二图案的俯视图；
图14是本申请实施例提供的一种移位寄存器单元的电路结构图；
图15是本申请实施例提供的一种显示面板的结构示意图；
图16是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，薄膜晶体管包括：沿远离衬底的方向依次层叠的栅极、栅极绝缘层、有源层以及源漏极层。源漏极层包括间隔设置的源极和漏极。
但是，由于薄膜晶体管在制备过程中有源层容易发生导体化，容易导致薄膜晶体管的特性出现异常，因此会导致阵列基板的良率较低，显示面板的显示效果较差。
氧化物薄膜晶体管的工艺步骤远少于低温多晶硅薄膜晶体管的工艺步骤，且氧化物薄膜晶体管的迁移率远高于非晶硅薄膜晶体管。氧化物薄膜晶体管还具有较好的弯曲性能，工艺温度低，可以用于制作柔性基板，因此氧化物薄膜晶体管在未来的柔性显示时长具有良好的发展前景。
但是氧化物薄膜晶体管相较于非晶硅薄膜晶体管而言，容易在阵列基板的制备过程中发生导体化，造成氧化物薄膜晶体管的特性异常，导致显示面板异常显示，极大的影响了氧化物显示面板的良率以及低成本优势。其中，氧化物显示面板可以用于表示显示面板中的薄膜晶体管为氧化物薄膜晶体管。
经过测试发现，在氧化物显示面板中，由于行驱动区域的一侧存在的大面积的空白区，因此导致行驱动区域中的薄膜晶体管的有源层容易被导体化。参考图1，某一薄膜晶体管的有源层被导体化之前，电阻为10 10Ω(欧姆)，且随着电压的增大，电阻逐渐降低直至薄膜晶体管开启。但是薄膜晶体管的有源层被导体化之后，电阻为10 4Ω，电阻不会随着电压的增大而变化，进而导致薄膜 晶体管失效。由此，参考图2，显示面板的显示效果较差，出现了横纹不良(每隔四行出现弱暗线)。
其中，图1中1.00E+01用于表示10 1，1.00E+02用于表示10 2，1.00E+3用于表示10 3，依次类推，不再赘述。
图3是本申请实施例提供的一种阵列基板的结构示意图。参考图3可以看出，该阵列基板10可以包括衬底101，多个薄膜晶体管102以及多个第一图案103。
图4是本申请实施例提供的一种衬底的俯视图。参考图3和图4，该衬底101还具有显示区域101a，以及围绕显示区域101a的周边区域101b。该周边区域101b至少包括沿第一方向X延伸的行驱动区域101b1。薄膜晶体管102至少位于行驱动区域101b1。当然，薄膜晶体管102还可以位于显示区域101a。
其中，位于行驱动区域101b1的薄膜晶体管102可以构成该阵列基板10的阵列基板行驱动(gate driven on array，GOA)电路。位于显示区域101a的薄膜晶体管102可以构成该阵列基板10中用于驱动发光单元发光的驱动电路。
图5是本申请实施例提供的阵列基板在图4中A区域的局部示意图。结合图4和图5，多个第一图案103至少位于行驱动区域101b1的一侧，且多个第一图案103与行驱动区域101b1沿第一方向X间隔排布，且与行驱动区域101b1的同一侧的多个第一图案103阵列排布。
图6是本申请实施例提供的一种薄膜晶体管的结构示意图。参考图6，该薄膜晶体管102包括：沿远离衬底101的方向依次层叠的栅极1021、栅极绝缘层1022、有源层1023以及源漏极层1024。该源漏极层1024包括间隔设置的源极10241和漏极10242。阵列基板10包括的多个第一图案103与该薄膜晶体管102的源极10241和漏极10242中的至少一个位于同层。其中，多个第一图案103与源极10241和漏极10242中的至少一个位于同层可以是指：多个第一图案103可以与源极10241和漏极10242中的至少一个采用相同材料并由同一次构图工艺制备得到。通常情况下，源极10241和漏极10242是采用相同材料并由同一次构图工艺制备得到。
在阵列基板10中，行驱动区域101b1的一侧通常会存在大面积的空白区(即未设置走线以及薄膜晶体管的区域)，因此在行驱动区域101b1的一侧设计多 个第一图案103，可以在刻蚀源漏极膜层以形成薄膜晶体管102的源极10241和漏极10242时，减少刻蚀液的消耗量。由此可以避免大面积刻蚀而消耗大量的刻蚀液，保证具有足够的刻蚀液以刻蚀形成行驱动区域101b1以及显示区域101a的薄膜晶体管102的源极10241和漏极10242，进而避免因行驱动区域101b1和显示区域101a的刻蚀液较少而导致的源漏极膜层的材料残留，避免薄膜晶体管102的沟道因有源层1023上方残留的源漏极薄膜的材料而导通，避免薄膜晶体管102的有源层1023被导体化，保证薄膜晶体管102的特性，提高阵列基板10的良率以及显示面板的显示效果。
并且，在行驱动区域101b1的一侧设计多个第一图案103，可以使得行驱动区域101b1的一侧的源漏极膜层的图案，与显示区域中有源层上方的源漏极膜层的图案的均一性较好。
综上所述，本申请实施例提供了一种阵列基板，该阵列基板的行驱动区域的一侧设计有多个第一图案，保证具有足够的刻蚀液以刻蚀形成行驱动区域以及显示区域的薄膜晶体管的源极和漏极，进而避免因行驱动区域和显示区域的刻蚀液较少而导致的源漏极膜层的材料残留，避免薄膜晶体管的沟道因有源层上方残留的源漏极膜层的材料而导通，避免薄膜晶体管的有源层被导体化，保证薄膜晶体管的特性，提高阵列基板的良率以及显示面板的显示效果。
相关技术中，为避免静电影响，会在行驱动区域101b1的一侧设计静电释放(electro-static discharge，ESD)单元。本申请将此区域的ESD单元移除，而设计了多个第一图案103，并将ESD单元设计在周边区域101b中位于显示区域101a的上侧(周边区域中位于显示区域101a远离扇出区域101b2的一侧)。例如，移除ESD单元可以用于在不增加掩膜版mask成本以及工艺难度的情况下，对掩膜版进行调整。
在本申请实施例中，薄膜晶体管102的有源层可以为金属氧化物材料。也即是，该薄膜晶体管102可以为氧化物薄膜晶体管。
在本申请实施例中，源漏极膜层可以包括依次层叠的第一膜层，第二膜层以及第三膜层。该第一膜层的材料和第三膜层的材料可以为钼铌合金(MoNb)，第二膜层的材料可以为铜(Cu)。也即是，源漏极膜层可以为MoNb/Cu/MoNb的叠层结构。
可选的，该第一图案103在衬底101上的正投影的形状为矩形。其中，该 矩形可以为直角矩形、倒角矩形或圆角矩形。例如，第一图案103在衬底101上的正投影的形状为正方形。也即是，第一图案103在衬底101上的正投影至少包括垂直的两条边界的长度相等。
参考图5可以看出，该第一图案103中垂直的两条边界中的其中一条边界平行于第一方向X，另一条边界平行于第二方向Y。其中，第二方向Y平行于显示区域101a和行驱动区域101b1的排布方向。第一方向X和第二方向Y相交，例如垂直。多个第一图案103在第一方向X和第二方向Y上阵列排布。
可选的，参考图7，第一图案103沿第一方向X的长度为m1，沿第一方向X相邻的任意两个第一图案103之间的距离为n1，m1/n1的比值范围为0.9至1.9。第一图案103沿第二方向Y的长度为m2，沿第二方向Y相邻的任意两个第一图案103之间的距离为n2，m2/n2的比值范围为0.9至1.9。
示例的，第一图案103沿第一方向X的长度m1的范围，以及沿第二方向Y的长度m2的范围均为12μm(微米)至15μm。沿第一方向X相邻的任意两个第一图案103之间的距离n1，以及沿第二方向Y相邻的任意两个第一图案103之间的距离n2的范围均为8μm至13μm。参考图7，第一图案103在衬底101上的正投影的形状可以为在矩形的基础上四个角为倒角，即第一图案103在衬底101上的正投影的形状为倒角矩形。
可选的，多个第一图案103在衬底101上的正投影与阵列基板10中其他结构在衬底101上的正投影之间的最小距离的范围为15μm至30μm。也即是，多个第一图案103与阵列基板10中其他结构之间的距离可以较大，避免该多个第一图案103对阵列基板10中其他结构造成影响。其中，该其他结构可以是阵列基板10中用于传输信号的走线，也可以是薄膜晶体管。
参考图3和图4，周边区域101b可以包括沿第一方向X延伸的两个行驱动区域101b1，且两个行驱动区域101b1分别位于显示区域101a的两侧。多个第一图案103位于每个行驱动区域101b1的两侧。也即是，多个第一图案103可以包括多个位于第一区域的第一图案103，多个位于第二区域的第一图案103，多个位于第三区域的第一图案103以及多个位于第四区域的第一图案103。例如，参考图8，该多个位于第一区域的第一图案103阵列排布的位于衬底101的左上角区域。另外，多个位于第二区域的第一图案103阵列排布的位于衬底101的左下角区域，多个位于第三区域的第一图案103阵列排布的位于衬底101的右 上角区域，多个位于第四区域的第一图案103阵列排布的位于衬底101的右下角区域。
参考图4可以看出，该周边区域101b还可以包括沿第二方向Y延伸的扇出区域101b2。图9是本申请实施例提供的阵列基板在图4的C区域的局部示意图。参考图4和图9，该阵列基板10还包括：多个第二图案104。该多个第二图案104至少位于扇出区域101b2的一侧，且多个第二图案104与扇出区域101b2沿第二方向Y间隔排布，位于扇出区域101b2的同一侧的多个第二图案104阵列排布。该第二图案104与第一图案103的形状和尺寸中的至少一种不同。可选的，该第二图案104在衬底101上的正投影的形状可以为矩形。
图10是图9沿DD方向的截面图。图11是图9沿DD方向的电镜示意图。参考图10和图11，多个第二图案104包括：多个第一类第二图案104a和多个第二类第二图案104b。多个第一类第二图案104a与栅极1021位于同层，多个第二类第二图案104b与源极10241和漏极10242位于同层。
其中，多个第一类第二图案104a与栅极1021位于同层可以是指：多个第一类第二图案104a与栅极1021采用相同材料且由同一次构图工艺制备得到。多个第二类第二图案104b与源极10241和漏极10242位于同层可以是指：多个第二类第二图案104b与源极10241和漏极10242采用相同材料并由同一次构图工艺制备得到。
在本申请实施例中，在扇出区域101b2设计多个第二图案104，同样可以减少刻蚀液的消耗量，进而避免因行驱动区域101b1和显示区域101a的刻蚀液较少而导致的源漏极膜层的材料残留，避免薄膜晶体管102的沟道因有源层1023上方残留的源漏极膜层的材料而导通，避免薄膜晶体管102的有源层1023被导体化，保证薄膜晶体管102的特性，提高阵列基板的显示效果和良率。
并且，阵列基板10的扇出区域101b2通常设计有多个信号线，且多个信号线中至少一个信号线的部分线段可以与栅极1021位于同层，另一部分线段与源极10241和漏极10242位于同层。由此，通过使得多个第二图案104中的多个第一类第二图案104a和多个第二类第二图案104b分别与栅极1021以及源极10241(或漏极10242)位于同层，可以确保该多个第二图案104的设计与扇出区域101b2中图案(信号线)的设计的图案均一性较好，提高阵列基板10的良率。
参考图10，多个第一类第二图案104a在衬底101上的正投影与多个第二类第二图案104b在衬底101上的正投影不重叠，可以避免多个第一类第二图案104a和多个第二类第二图案104b相互影响，保证阵列基板10的良率。
可选的，参考图10，多个第一类第二图案104a在衬底101上的正投影与多个第二类第二图案104b在衬底101上的正投影在第二方向Y上交错排布。
可选的，参考图11，第一类第二图案104a与最靠近该第一类第二图案104a的一个第二类第二图案104b之间的连接线，与衬底基板101的承载面之间的夹角α的范围可以为25度至60度。
另外，每个第二图案104的边界坡面与衬底基板101的承载面之间的夹角β的范围为25度至60度。
或者，参考图12，多个第一类第二图案104a与多个第二类第二图案104b的数量相同，且一一对应。每个第一类第二图案104a在衬底101上的正投影与对应的一个第二类第二图案104b在衬底101上的正投影重叠。
在本申请实施例中，第二图案104在衬底101上的正投影的形状为矩形，且第二图案104沿第一方向X的长度可以大于沿第二方向Y的长度。例如，第二图案104可以为沿第一方向X延伸的条状结构。
可选的，该第一图案103中垂直的两条边界中的其中一条边界平行于第一方向X，另一条边界平行于第二方向Y。其中，第二方向Y平行于显示区域101a和行驱动区域101b1的排布方向。也即是，多个第一图案103在第一方向X和第二方向Y上阵列排布。
可选的，参考图13，第二图案104沿第一方向X的长度为r1，沿第一方向X相邻的任意两个第二图案104之间的距离为s1，r1/s1的比值范围为0.9至1.9。第二图案104沿第二方向X的长度为r2，沿第二方向Y相邻的任意两个第二图案102之间的距离为s2，r2/s2的比值范围为0.9至1.9。
可选的，第二图案104沿第一方向X的长度r1的范围为50μm至100μm，第二图案104沿第二方向Y的长度r2的范围为2μm至10μm。该第二图案104沿第一方向X的长度r1不会过大(该第二图案104可以为短棒状结构)，可以避免由于该第二图案104的长度过长而导致电荷聚集在该第二图案104处，避免发生静电放电的风险。
另外，沿第一方向X相邻的任意两个第二图案104之间的距离s1的范围为 50μm至100μm，沿第二方向Y相邻的任意两个第二图案104之间的距离s2的范围为3μm至10μm。
参考图13，第二图案104在衬底101上的正投影的形状可以为在矩形的基础上四个角为倒角，即第二图案104在衬底101上的正投影的形状可以为倒角矩形。
可选的，多个第二图案104在衬底101上的正投影与阵列基板10中其他结构在衬底101上的正投影之间的最小距离的范围为75μm至100μm。也即是，多个第二图案104与阵列基板10中其他结构之间的距离可以较大，避免该多个第二图案104对阵列基板10中其他结构造成影响。其中，该其他结构可以是阵列基板10中用于传输信号的走线，也可以是薄膜晶体管。
在本申请实施例中，多个第二图案104可以位于扇出区域101b2的两侧。例如，多个第二图案104可以包括多个位于第五区域的第二图案104以及多个位于第六区域的第二图案104。该第五区域和第六区域分别位于扇出区域101b2的两侧。
在本申请实施例中，位于行驱动区域101b1的多个薄膜晶体管102可以构成多个级联的移位寄存器单元。每个移位寄存器单元可以包括18个薄膜晶体管102以及一个存储电容。当然，移位寄存器单元也可以为其他结构，本申请实施例对此不做限定。
图14是本申请实施例提供的一种移位寄存器单元的电路结构图。参考图14可以看出，该移位寄存器单元01可以包括：输入电路011、第一复位电路012、输出电路013、第二复位电路014、第一拉动控制电路015、第一拉动电路016、第二拉动控制电路017、第二拉动电路018以及存储电容C。
输入电路011，包括：第一晶体管M1，第一晶体管M1的栅极和第一极与信号输入端INPUT连接，第一晶体管M1的第二极与上拉节点PU连接。
第一复位电路012，包括：第二晶体管M2和第三晶体管M4。第二晶体管M2的栅极与第一复位信号端RES1连接，第二晶体管M2的第一极与上拉节点PU连接，第二晶体管M2的第二极与第一固定电压端LVGL连接。第三晶体管M4的栅极与第一复位信号端RES1连接，第三晶体管M4的第一极与第一信号输出端OUT1连接，第三晶体管M4的第二极与第二固定电压端VGL连接。
输出电路013，包括：第一输出晶体管M3和第二输出晶体管M11。第一输 出晶体管M3的栅极与上拉节点PU连接，第一输出晶体管M3的第一极与时钟信号端CLK连接，第一输出晶体管M3的第二极与第一信号输出端OUT1连接。第二输出晶体管M11的栅极与上拉节点PU连接，第二输出晶体管M11的第一极与时钟信号端CLK连接，第二输出晶体管M11的第二极与第二信号输出端OUT2连接。
第二复位电路014，包括：第四晶体管M15，第四晶体管M15的栅极与第二复位信号端RES2连接，第四晶体管M15的第一极和上拉节点PU连接，第四晶体管M15的第二极和第一固定电压端LVGL连接；
第一拉动控制电路015，包括：第五晶体管M5A、第六晶体管M6A和第七晶体管M7A。第五晶体管M5A的栅极和第一极与第一控制端VDDo连接，第五晶体管M5A的第二极与第一下拉节点PD1连接。第六晶体管M6A的栅极与上拉节点PU连接，第六晶体管M6A的第一极与第一下拉节点PD1连接，第六晶体管M6A的第二极与第一固定电压端LVGL连接。第七晶体管M7A的栅极与信号输入端INPUT连接，第七晶体管M7A的第一极与第一下拉节点PD1连接，第七晶体管M7A的第二极与第一固定电压端LVGL连接。
第一拉动电路016，包括：第八晶体管M8A、第九晶体管M12A和第十晶体管M13A。第八晶体管M8A的栅极与第一下拉节点PD1连接，第八晶体管M8A的第一极与上拉节点PU连接，第八晶体管M8A的第二极与第一固定电压端LVGL连接。第九晶体管M12A的栅极与第一下拉节点PD1连接，第九晶体管M12A的第一极与第二信号输出端OUT2连接，第九晶体管M12A的第二极与第一固定电压端LVGL连接。第十晶体管M13A的栅极与第一下拉节点PD1连接，第十晶体管M13A的第一极与第一信号输出端OUT1连接，第十晶体管M13A的第二极与第二固定电压端VGL连接。
第二拉动控制电路017，包括：第十一晶体管M5B、第十二晶体管M6B和第十三晶体管M7B。第十一晶体管M5B的栅极和第一极与第二控制端VDDe连接，第五晶体管M5A的第二极与第二下拉节点PD2连接。第十二晶体管M6B的栅极与上拉节点PU连接，第十二晶体管M6B的第一极与第二下拉节点PD2连接，第十二晶体管M6B的第二极与第一固定电压端LVGL连接。第十三晶体管M7B的栅极与信号输入端INPUT连接，第十三晶体管M7B的第一极与第二下拉节点PD2连接，第十三晶体管M7B的第二极与第一固定电压端LVGL连接。
第二拉动电路018，包括：第十四晶体管M8B、第十五晶体管M12B和第十六晶体管M13B。第十四晶体管M8B的栅极与第二下拉节点PD2连接，第十四晶体管M8B的第一极与上拉节点PU连接，第十四晶体管M8B的第二极与第一固定电压端LVGL连接，第十五晶体管M12B的栅极与第二下拉节点PD2连接，第十五晶体管M12B的第一极与第二信号输出端OUT2连接，第十五晶体管M12B的第二极与第一固定电压端LVGL连接。第十六晶体管M13B的栅极与第二下拉节点PD2连接，第十六晶体管M13B的第一极与第一信号输出端OUT1连接，第十六晶体管M13B的第二极与第二固定电压端VGL连接。
存储电容C的第一极与上拉节点PU连接，存储电容C的第二极与第一信号输出端OUT1连接。
其中，每个晶体管的第一极和第二极中的一个为源极，另一个为漏极。
在本申请实施例中，源漏极层1024的厚度可以为350nm(纳米)，栅极1021的厚度可以为345nm。当然，源漏极层1024的厚度以及栅极1021的厚度还可以为其他厚度，本申请实施例对此不做限定。
综上所述，本申请实施例提供了一种阵列基板，该阵列基板的行驱动区域的一侧设计有多个第一图案，保证具有足够的刻蚀液以刻蚀形成行驱动区域以及显示区域的薄膜晶体管的源极和漏极，进而避免因行驱动区域和显示区域的刻蚀液较少而导致的源漏极膜层的材料残留，避免薄膜晶体管的沟道因有源层上方残留的源漏极膜层的材料而导通，避免薄膜晶体管的有源层被导体化，保证薄膜晶体管的特性，提高阵列基板的良率以及显示面板的显示效果。
图15是本申请实施例提供的一种显示面板的结构示意图。参考图15可以看出，该显示面板01可以包括多个发光单元20以及如上述实施例所提供的阵列基板10。该多个发光单元20可以位于阵列基板10的显示区域101a。其中，图15中的所示的发光单元20仅用于表示发光单元20设置在显示区域101a，并不用于表示发光单元20的实际形状。
图16是本申请实施例提供的一种显示装置的结构示意图。参考图16，该显示装置可以包括：供电组件02以及如上述实施例所提供的显示面板01。该供电组件02可以用于为显示面板01供电。
可选的，该显示装置可以为：液晶显示装置(liquid crystal display，LCD)、有机发光二极管(organic light-emitting diode，OLED)显示装置、电子纸、低温多晶硅(low temperature poly-silicon，LTPS)显示装置、低温多晶氧化物(low temperature poly-silicon oxide，LTPO)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请所有实施例中的晶体管均可以为薄膜晶体管，根据在电路中的作用本发明的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请实施例所采用的开关晶体管可以包括N型开关晶体管和P型开关晶体管中的任一种，其中，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止。
将理解的是，尽管术语第一、第二等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，上面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“行”、“列”、“在…之下”、“在…之上”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在…之下”可以涵盖在…之上和在…之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。 如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。在本说明书中，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种阵列基板，其特征在于，所述阵列基板(10)包括：
    衬底(101)，所述衬底(101)具有显示区域(101a)，以及围绕所述显示区域(101a)的周边区域(101b)，所述周边区域(101b)至少包括沿第一方向(X)延伸的行驱动区域(101b1)；
    多个薄膜晶体管(102)，所述多个薄膜晶体管(102)至少位于所述行驱动区域(101b1)内；
    以及，多个第一图案(103)，所述多个第一图案(103)至少位于所述行驱动区域(101b1)的一侧，且所述多个第一图案(103)与所述行驱动区域(101b1)沿所述第一方向(X)间隔排布，位于所述行驱动区域(101b1)的同一侧的多个第一图案(103)阵列排布；
    其中，所述薄膜晶体管(102)包括：沿远离所述衬底(101)的方向依次层叠的栅极(1021)、栅极绝缘层(1022)、有源层(1023)以及源漏极层(1024)，所述源漏极层(1024)包括间隔设置的源极(10241)和漏极(10242)；所述多个第一图案(103)与所述源极(10241)和所述漏极(10242)中的至少一个位于同层。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述第一图案(103)在所述衬底(101)上的正投影的形状为矩形。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述第一图案(103)在所述衬底(101)上的正投影的形状为正方形。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述第一图案(103)中垂直的两条边界中的其中一条边界平行于所述第一方向(X)，另一条边界平行于第二方向(Y)；
    所述第二方向(Y)平行于所述显示区域(101a)和所述行驱动区域(101b1)的排布方向，所述第一方向(X)和所述第二方向(Y)相交。
  5. 根据权利要求4所述的阵列基板，其特征在于，
    所述第一图案(103)沿第一方向(X)的长度为m1，沿所述第一方向(X)相邻的任意两个所述第一图案(103)之间的距离为n1，m1/n1的比值范围为0.9至1.9；
    所述第一图案(103)沿第二方向(Y)的长度为m2，沿所述第二方向(Y)相邻的任意两个所述第一图案(103)之间的距离为n2，m2/n2的比值范围为0.9至1.9。
  6. 根据权利要求1至5任一所述的阵列基板，其特征在于，所述多个第一图案(103)在所述衬底(101)上的正投影与所述阵列基板(10)中其他结构在所述衬底(101)上的正投影之间的最小距离的范围为15微米至30微米。
  7. 根据权利要求1至6任一所述的阵列基板，其特征在于，所述周边区域(101b)包括沿所述第一方向(X)延伸的两个所述行驱动区域(101b1)，两个所述行驱动区域(101b1)分别位于所述显示区域(101a)的两侧；
    其中，所述多个第一图案(103)位于每个所述行驱动区域(101b1)的两侧。
  8. 根据权利要求1至7任一所述的阵列基板，其特征在于，所述周边区域(101b)还包括沿第二方向(Y)延伸的扇出区域(101b2)，所述第二方向(Y)平行于所述行驱动区域(101b1)和所述显示区域(101a)的排布方向；所述阵列基板(10)还包括：
    多个第二图案(104)，所述多个第二图案(104)至少位于所述扇出区域(101b2)的一侧，且所述多个第二图案(104)与所述扇出区域(101b2)沿所述第二方向(Y)间隔排布，位于所述扇出区域(101b2)的同一侧的多个第二图案(104)阵列排布，所述第二图案(104)与所述第一图案(103)的形状和尺寸中的至少一种不同；
    其中，所述多个第二图案(104)包括：多个第一类第二图案(104a)和多个第二类第二图案(104b)，所述多个第一类第二图案(104a)与所述栅极(1021)位于同层，所述多个第二类第二图案(104b)与所述源极(10241)和所述漏极 (10242)位于同层。
  9. 根据权利要求8所述的阵列基板，其特征在于，所述多个第一类第二图案(104a)在所述衬底(101)上的正投影与所述多个第二类第二图案(104b)在所述衬底(101)上的正投影不重叠。
  10. 根据权利要求9所述的阵列基板，其特征在于，所述多个第一类第二图案(104a)在所述衬底(101)上的正投影与所述多个第二类第二图案(104b)在所述衬底(101)上的正投影在所述第二方向(Y)上交错排布。
  11. 根据权利要求8所述的阵列基板，其特征在于，所述多个第一类第二图案(104a)与所述多个第二类第二图案(104b)的数量相同，且一一对应；
    每个所述第一类第二图案(104a)在所述衬底(101)上的正投影与对应的一个所述第二类第二图案(104b)在所述衬底(101)上的正投影重叠。
  12. 根据权利要求8至11任一所述的阵列基板，其特征在于，所述第二图案(104)在所述衬底(101)上的正投影的形状为矩形，且所述第二图案(104)沿所述第一方向(X)的长度大于沿所述第二方向(Y)的长度。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述第二图案(104)中垂直的两条边界中的其中一条边界平行于所述第一方向(X)，另一条边界平行于所述第二方向(Y)。
  14. 根据权利要求13所述的阵列基板，其特征在于，
    所述第二图案(104)沿所述第一方向(X)的长度为r1，沿所述第一方向(X)相邻的任意两个所述第二图案(104)之间的距离为s1，r1/s1的比值范围为0.9至1.9；
    所述第二图案(104)沿所述第二方向(Y)的长度为r2，沿所述第二方向(Y)相邻的任意两个所述第二图案(104)之间的距离为s2，r2/s2的比值范围为0.9至1.9。
  15. 根据权利要求8至14任一所述的阵列基板，其特征在于，所述第二图案(104)在所述衬底(101)上的正投影与所述阵列基板(10)中其他结构在所述衬底(101)上的正投影之间的最小距离的范围为75微米至100微米。
  16. 根据权利要求8至15任一所述的阵列基板，其特征在于，所述多个第二图案(104)位于所述扇出区域(101b2)的两侧。
  17. 根据权利要求1至16任一所述的阵列基板，其特征在于，位于所述行驱动区域(101b1)的多个所述薄膜晶体管(102)构成多个级联的移位寄存器单元，每个所述移位寄存器单元包括18个所述薄膜晶体管(102)以及一个存储电容。
  18. 根据权利要求1至17任一所述的阵列基板，其特征在于，所述薄膜晶体管(102)的有源层为金属氧化物材料。
  19. 一种显示面板，其特征在于，所述显示面板包括多个发光单元(20)以及如权利要求1至18任一所述的阵列基板(10)；
    其中，所述多个发光单元(20)位于所述阵列基板(10)的显示区域(101a)。
PCT/CN2022/121445 2022-09-26 2022-09-26 阵列基板及显示面板 WO2024065106A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/121445 WO2024065106A1 (zh) 2022-09-26 2022-09-26 阵列基板及显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/121445 WO2024065106A1 (zh) 2022-09-26 2022-09-26 阵列基板及显示面板

Publications (1)

Publication Number Publication Date
WO2024065106A1 true WO2024065106A1 (zh) 2024-04-04

Family

ID=90475102

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/121445 WO2024065106A1 (zh) 2022-09-26 2022-09-26 阵列基板及显示面板

Country Status (1)

Country Link
WO (1) WO2024065106A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934445A (zh) * 2015-06-01 2015-09-23 深圳市华星光电技术有限公司 Tft基板组及其制作方法
US20170154904A1 (en) * 2015-07-15 2017-06-01 Shenzhen China Star OptoelectronicsTechnology Co. Ltd. Manufacturing method of display panel
US20180069031A1 (en) * 2016-09-07 2018-03-08 Au Optronics Corporation Array substrate and display device using the same
CN111129040A (zh) * 2020-01-02 2020-05-08 昆山国显光电有限公司 阵列基板及其制作方法、显示面板
CN112925136A (zh) * 2021-03-29 2021-06-08 绵阳惠科光电科技有限公司 一种驱动电路的控制开关、阵列基板和显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934445A (zh) * 2015-06-01 2015-09-23 深圳市华星光电技术有限公司 Tft基板组及其制作方法
US20170154904A1 (en) * 2015-07-15 2017-06-01 Shenzhen China Star OptoelectronicsTechnology Co. Ltd. Manufacturing method of display panel
US20180069031A1 (en) * 2016-09-07 2018-03-08 Au Optronics Corporation Array substrate and display device using the same
CN111129040A (zh) * 2020-01-02 2020-05-08 昆山国显光电有限公司 阵列基板及其制作方法、显示面板
CN112925136A (zh) * 2021-03-29 2021-06-08 绵阳惠科光电科技有限公司 一种驱动电路的控制开关、阵列基板和显示面板

Similar Documents

Publication Publication Date Title
CN108598087B (zh) 阵列基板及其制造方法、显示面板、电子装置
US10636505B2 (en) Display panel and display device
US10810944B2 (en) Array substrate, display panel and display device
US6472256B1 (en) Method of manufacturing a thin-film transistor with a short-circuiting pattern
WO2022067634A1 (zh) 显示基板及其制作方法、显示装置
EP4020443A1 (en) Display substrate and manufacturing method therefor, and display device
CN113785350B (zh) 显示基板及其制作方法、显示装置
US20220344480A1 (en) Thin film transistor, gate on array circuit and array substrate
CN108807488A (zh) 显示面板和显示装置
WO2021227122A1 (zh) 阵列基板和显示面板
WO2022057542A1 (zh) 一种显示背板及其制备方法、显示装置
KR100506006B1 (ko) 액정표시장치의 전계효과트랜지스터에 대한 오프-스테이트스트레스 인가용 패널구조
TWI406074B (zh) 主動元件陣列基板
WO2024065106A1 (zh) 阵列基板及显示面板
WO2021217759A1 (zh) 一种显示面板及其制作方法以及电子装置
TWI686647B (zh) Tft基板、esd保護電路及tft基板的製作方法
US20230154930A1 (en) Display panel and display device
CN112544002B (zh) 阵列基板及其制备方法、显示装置
JP3311835B2 (ja) 表示装置用駆動回路およびそれを用いた液晶表示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023115331A1 (zh) 移位寄存器、扫描驱动电路及显示基板
WO2024060082A1 (zh) 显示基板及其制备方法、显示装置
WO2023159516A1 (zh) 显示基板及显示装置
CN213023866U (zh) 阵列基板和显示装置
WO2023077269A1 (zh) 显示基板、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22959758

Country of ref document: EP

Kind code of ref document: A1