WO2024061153A1 - 伪电阻电路、rc滤波电路、电流镜电路及芯片 - Google Patents

伪电阻电路、rc滤波电路、电流镜电路及芯片 Download PDF

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WO2024061153A1
WO2024061153A1 PCT/CN2023/119352 CN2023119352W WO2024061153A1 WO 2024061153 A1 WO2024061153 A1 WO 2024061153A1 CN 2023119352 W CN2023119352 W CN 2023119352W WO 2024061153 A1 WO2024061153 A1 WO 2024061153A1
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Prior art keywords
circuit
mos transistor
current
source
resistance
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PCT/CN2023/119352
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English (en)
French (fr)
Inventor
陈志远
张�林
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思瑞浦微电子科技（苏州）股份有限公司
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Publication of WO2024061153A1 publication Critical patent/WO2024061153A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/06—Frequency selective two-port networks including resistors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to the field of integrated circuits, and in particular to a pseudo-resistance circuit, an RC filter circuit, a current mirror circuit and a chip.
  • an RC filter is often needed to filter out noise from bias current/voltage, etc.
  • larger resistors and capacitors are often required, which means a larger chip area is required and the cost is higher.
  • the resistor can be made into a high-resistance resistor at a small area cost, we can increase the resistance value and decrease the capacitance value to achieve an RC filter with the same filtering effect, which means that the RC filter The overall area can be greatly reduced. Therefore, a small-area, large-value resistor solution is very valuable for low-noise circuits.
  • Figure 1 shows a commonly used RC filter circuit.
  • polysilicon or active area is usually used as the resistor.
  • the resistor value of such a resistor scheme is small, and the semiconductor process level limits the minimum width of the resistor, which means The area efficiency is not high, and such an RC filter will occupy a larger chip area.
  • FIG. 2 shows the use of metal-oxide-semiconductor (MOS) tubes in the linear region as resistors.
  • MOS metal-oxide-semiconductor
  • Figure 3 shows a MOS transistor in the sub-threshold region used as a resistor.
  • the gate-source voltage of the MOS transistor is almost 0V, resulting in a huge resistance value of the resistor (about 100G ⁇ ).
  • Such a large resistor has a negative impact on the leakage current. Quite sensitive, and the resistance changes greatly under PVT.
  • the object of the present invention is to provide a pseudo-resistance circuit, RC filter circuit, current mirror circuit and chip, which can obtain a high-resistance resistor at a small area cost, and the resistance of the resistor is affected by process-voltage-temperature. (PVT) has a smaller impact.
  • PVT process-voltage-temperature
  • embodiments of the present invention provide a pseudo-resistance circuit, including: a first MOS transistor and a bias circuit.
  • the bias circuit is connected to the gate and source of the first MOS transistor to provide a bias voltage between the gate and source of the first MOS transistor for making the first MOS transistor operate in the sub-threshold region, and
  • the resistance of the first MOS transistor is adjusted by adjusting the bias voltage;
  • the bias circuit includes a second MOS transistor, a resistor and a first current source connected in sequence.
  • the source of the second MOS transistor is connected to the source of the first MOS transistor
  • the drain of the second MOS transistor is connected to the first end of the resistor and the gate of the first MOS transistor
  • the second end of the resistor is connected to the gate of the second MOS transistor
  • the connection point between the second end of the resistor and the second MOS transistor is connected to the ground voltage or the power supply voltage through the first current source.
  • the source of the first MOS transistor is short-circuited to the substrate, and/or the source of the second MOS transistor is short-circuited to the substrate.
  • the resistor includes a passive resistor or an active resistor.
  • the invention also discloses an RC filter circuit, which includes the pseudo-resistance circuit and a capacitor connected to the pseudo-resistance circuit.
  • the invention also discloses a current mirror circuit, which includes the RC filter circuit, an input circuit and an output circuit.
  • the input circuit is connected to an external circuit to receive the input current provided by the external circuit.
  • the RC filter circuit and the input circuit is connected to filter the input current, and the output circuit is connected to the RC filter circuit to copy the input current and output it.
  • the input circuit includes a third MOS transistor
  • the output circuit includes a fourth MOS transistor
  • the gate and drain of the third MOS transistor are short-circuited and connected to the external circuit.
  • the gate of the third MOS transistor is connected to the first end of the RC filter circuit
  • the gate of the fourth MOS transistor is connected to the second end of the RC filter circuit.
  • the current mirror circuit further includes a second current source, the first end of the second current source is connected to the power supply voltage and the first end of the external circuit, and the second The second end of the current source is connected to the second end of the external circuit and the gate and drain of the third MOS transistor.
  • the second current source is used to provide the same current as the bias current provided by the first current source.
  • the input current provided by the external circuit is much larger than the bias current provided by the first current source in the RC filter circuit.
  • the invention also discloses a chip, including the pseudo-resistance circuit, the RC filter circuit and/or the current mirror circuit.
  • the first MOS tube is used as a pseudo-resistance and the bias circuit is used to provide a voltage between the gate and the source of the first MOS tube.
  • Resistor on the one hand, the area of the resistor can be reduced.
  • the capacitance value can be made smaller, thereby reducing the area of the capacitor.
  • the resistance of the pseudo resistor is less affected by the process-voltage-temperature (PVT), which ensures that the filtering effect of the RC filter will not change significantly when the process-voltage-temperature (PVT) changes.
  • PVT process-voltage-temperature
  • the resistance value of the pseudo-resistor can be easily set to a reasonable resistance value by setting parameters, so that the resistance value is not too small and deteriorates the filtering effect, and it is not too large to be very sensitive to leakage current.
  • Figure 1 is a circuit schematic diagram of an RC filter circuit in the prior art.
  • FIG. 2 is a schematic circuit diagram of an RC filter using a pseudo resistor in the second prior art.
  • FIG. 3 is a circuit diagram of an RC filter using pseudo-resistance according to a third prior art.
  • FIG. 4 is a schematic circuit diagram of a pseudo-resistance circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic circuit diagram of a pseudo-resistance circuit according to Embodiment 2 of the present invention.
  • Figure 6 is a circuit principle diagram of an RC filter circuit according to Embodiment 3 of the present invention.
  • FIG. 7 is a schematic circuit diagram of a current mirror circuit according to Embodiment 4 of the present invention.
  • circuitry may include a single or multiple combinations of hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions executed by programmable circuits.
  • an element or circuit When an element or circuit is said to be “connected” to another element, or to another element, or an element/circuit is said to be “connected between” two nodes, it can be directly coupled or connected to the other element or it can Intermediate elements exist, and the connection between elements may be physical, logical, or a combination thereof.
  • an element is referred to as being “directly coupled” or “directly connected to” another element, there are no intervening elements present.
  • a pseudo-resistance circuit includes: a first MOS transistor M1 and a bias circuit 10.
  • the first MOS transistor M1 is a P-channel MOS transistor.
  • the bias circuit 10 is connected to the gate and the source of the first MOS transistor M1 to provide a bias voltage between the gate and the source of the first MOS transistor M1 for making the first MOS transistor M1 operate in the sub-threshold region. , and by adjusting the bias voltage to adjust the resistance of the first MOS transistor M1, that is, determining the gate-source voltage of the first MOS transistor M1 determines the resistance of the first MOS transistor M1.
  • the bias circuit 10 includes a second MOS transistor M2, a resistor R1 and a first current source A1.
  • the source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1.
  • the drain of the second MOS transistor M2 is connected to the first end of the resistor R1 and the gate of the first MOS transistor M1.
  • the second end of the resistor R1 The terminal is connected to the gate of the second MOS transistor M2 and the connection point is connected to the ground voltage through the first current source A1.
  • the second MOS transistor M2 is a P-channel MOS transistor.
  • the resistor R1 is a poly resistor. In other embodiments, the resistor R1 can be other passive resistors or active resistors.
  • the gate-source voltage of the first MOS transistor M1 is equal to the gate-source voltage of the second MOS transistor M2 minus the voltage on the resistor R1, so that by adjusting the gate-source voltage or resistance of the second MOS transistor M2
  • the voltage on R1 can easily adjust the resistance of the first MOS tube M1; that is,
  • the first current source A1 can be implemented by using an N-channel MOS transistor or other circuit structures that can serve as actual current sources.
  • the source and substrate of the first MOS transistor M1 may be short-circuited, and the source and substrate of the second MOS transistor M2 may be short-circuited.
  • of the second MOS transistor M2 are approximately equal.
  • the threshold voltage of the same type of MOS transistor is affected by the process. It is consistent because it is on both sides of formula (2), so the threshold voltage of the first MOS transistor M1
  • of the second MOS transistor M2 are less affected by process-voltage-temperature (PVT).
  • I 1 is obtained by dividing the reference voltage provided by the bandgap reference circuit by a resistor.
  • the resistor R1 is proportional to the resistor and can offset the process-voltage-temperature (PVT) effect on the resistor.
  • the bias voltage provided between the gate and the source of the first MOS transistor M1 is a voltage related to the threshold voltage
  • of the first MOS transistor M1 changes with the process-voltage-temperature (PVT).
  • PVT process-voltage-temperature
  • the resistance value of the first MOS transistor M1 changes relatively. Small.
  • the first MOS transistor M1 avoids applying a fixed voltage between the gate and drain of the first MOS transistor M1 (at this time, the first MOS transistor M1 is in the sub-threshold region) to allow As a large resistor, the first MOS transistor M1 causes the resistance value of the first MOS transistor M1 to change greatly and become unstable under different process-voltage-temperature (PVT) conditions.
  • PVT process-voltage-temperature
  • the difference between this embodiment and Embodiment 1 is that the first MOS transistor M1 is an N-channel MOS transistor, and the second MOS transistor M2 is an N-channel MOS transistor.
  • the connection method in the bias circuit 10 is also changed accordingly.
  • the source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, and the drain of the second MOS transistor M2 is connected to the first end of the resistor R1 and the gate of the first MOS transistor M1.
  • the resistor R1 The second terminal is connected to the gate of the second MOS transistor M2 and the connection point is connected to the power supply voltage through the first current source A1.
  • this embodiment discloses an RC filter circuit, which includes a pseudo-resistance circuit and a capacitor C1 connected to the pseudo-resistance circuit.
  • the first terminal of the capacitor C1 is connected to the drain of the first MOS transistor M1, and the second terminal of the capacitor C1 is connected to the ground voltage.
  • this embodiment discloses a current mirror circuit, including the RC filter circuit as shown in FIG6 , an input circuit, and an output circuit, wherein the input circuit is connected to the external circuit 20 to receive the input current I 2 provided by the external circuit 20 , the RC filter circuit is connected to the input circuit to filter the input current I 2 , and the output circuit is connected to the RC filter circuit to copy the input current I 2 and output it.
  • the input circuit includes the third MOS transistor M3, and the output circuit includes the fourth MOS transistor M4.
  • the input circuit and the output circuit may form a multi-layer cascade structure.
  • the third MOS transistor M3 and the fourth MOS transistor M4 are both NMOS transistors.
  • the gate and drain of the third MOS transistor M3 are connected and connected to the source of the first MOS transistor M1 and the external circuit 20 .
  • the external circuit 20 may be a current mirror, a current source, or a circuit with other structures.
  • the drain of the third MOS transistor M3 is used to receive the input current I 2 provided by the external circuit 20 , and the source of the third MOS transistor M3 is connected to the ground voltage.
  • the gate of the fourth MOS tube M4 is connected to the first terminal of the capacitor C1 and the drain of the first MOS tube M1.
  • the second terminal of the capacitor C1 is connected to the ground voltage.
  • the source of the fourth MOS tube is connected to the ground voltage.
  • the drain of the four-MOS transistor M4 is used to output current.
  • High-frequency noise can be filtered through capacitor C1 through the RC filter circuit, and for low-frequency signals, it can be considered that the gates of the third MOS tube and the fourth MOS tube are short-circuited together.
  • the third MOS transistor M3 and the fourth MOS transistor M4 may both be PMOS transistors, and correspondingly, the RC filter circuit shown in FIG. 5 may be used.
  • the current mirror circuit also includes a second current source A2.
  • the first terminal of the second current source A2 is connected to the power supply voltage.
  • the second terminal of the second current source A2 is connected to the gate of the third MOS transistor M3 and The drain is connected, and the second current source A2 is used to provide the same current as the bias current I1 provided by the first current source A1.
  • the input current I 2 of the external circuit 20 can be copied as accurately as possible by the current mirror circuit.
  • the bias current I 1 generated by it will become a source of error in the current mirror circuit image.
  • a second current source A2 is provided.
  • the bias current I1 generated by the first current source A1 is compensated by the current I1 generated by the second current source A2. This allows the input current I 2 of the external circuit 20 to be accurately copied by the current mirror circuit.
  • the input current I2 provided by the external circuit 20 can be much larger than the bias current I 1 provided by the first current source A1 in the RC filter circuit, thereby reducing the error caused by the bias current I 1 .
  • This embodiment discloses a chip including a pseudo-resistance circuit, an RC filter circuit and/or a current mirror circuit.

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Abstract

一种伪电阻电路、RC滤波电路、电流镜电路及芯片，伪电阻电路包括：第一MOS管（M1）以及偏置电路（10）；偏置电路（10）给第一MOS管（M1）的栅极和源极之间提供用于使得第一MOS管（M1）工作于亚阈值区的偏置电压，并通过调节该偏置电压以调节第一MOS管（M1）的阻值；可以用较小的面积代价得到一个高阻值的电阻，一方面可以降低电阻的面积，另一方面为了实现相同的RC时间常数，可以将电容值取小，从而降低电容的面积；此外，该伪电阻电路的阻值受工艺-电压-温度(PVT)的影响较小，保证在工艺-电压-温度(PVT)变化的时候，RC滤波器的滤波效果不会有大的变化。

Description

伪电阻电路、RC滤波电路、电流镜电路及芯片
本发明要求2022年09月20日向中国专利局提交的、申请号为202211143851.2、发明名称为“伪电阻电路、RC滤波电路、电流镜电路及芯片”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。
技术领域
本发明关于集成电路领域，特别是关于一种伪电阻电路、RC滤波电路、电流镜电路及芯片。
背景技术
对于芯片里的低噪声电路，经常需要一个RC滤波器来滤除来自偏置电流/电压等的噪声。为了实现更好的滤波效果，往往需要较大的电阻和电容，这意味着需要较大的芯片面积，成本较高。
同时，如果电阻可以用较小的面积代价来做到一个高阻值电阻，我们可以将电阻值取大以及电容值取小来实现一个相同滤波效果的RC滤波器，这意味着RC滤波器的整体面积可以极大的减小。因此，一种小面积、大阻值的电阻方案对于低噪声电路是非常有价值的。
图1为常用的RC滤波器电路，在半导体工艺中，通常采用多晶硅或者有源区来做电阻，这样的电阻方案的电阻阻值较小，而且半导体工艺水平限制了电阻最小的宽度，意味着面积效率不高，这样的RC滤波器会占用一个较大的芯片面积。
图2为用线性区的金属-氧化物-半导体(MOS)管来做电阻，为提高电阻阻值，需要多个MOS管串联，这样依然需要较大的芯片面积来实现一个高阻值电阻。
图3为用亚阈值区的MOS管来做电阻，在稳定状态下，该MOS管的栅-源电压几乎为0V，导致该电阻阻值巨大(约100GΩ)，这样大的一个电阻对漏电流相当敏感，且在PVT下的阻值的变化较大。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
本发明的目的在于提供一种伪电阻电路、RC滤波电路、电流镜电路及芯片，其能够用较小的面积代价得到一个高阻值的电阻，且该电阻的阻值受工艺-电压-温度(PVT)的影响较小。
为实现上述目的，本发明的实施例提供了一种伪电阻电路，包括：第一MOS管以及偏置电路。
所述偏置电路与第一MOS管的栅极和源极相连以给第一MOS管的栅极和源极之间提供用于使得第一MOS管工作于亚阈值区的偏置电压，并通过调节该偏置电压以调节第一MOS管的阻值；所述偏置电路包括依次相连的第二MOS管、电阻和第一电流源。
在本发明的一个或多个实施例中，所述第二MOS管的源极与第一MOS管的源极相连，所述第二MOS管的漏极与电阻的第一端和第一MOS管的栅极相连，所述电阻的第二端与第二MOS管的栅极相连，并且所述电阻的第二端与第二MOS管的连接点通过第一电流源与地电压或电源电压相连。
在本发明的一个或多个实施例中，所述第一MOS管的源极和衬底短接，和/或所述第二MOS管的源极和衬底短接。
在本发明的一个或多个实施例中，所述电阻包括无源电阻或有源电阻。
本发明还公开了一种RC滤波电路，包括所述的伪电阻电路以及与伪电阻电路相连的电容。
本发明还公开了一种电流镜电路，包括所述的RC滤波电路以及输入电路和输出电路，所述输入电路与外部电路相连以接收外部电路提供的输入电流，所述RC滤波电路与输入电路相连以对输入电流进行滤波，所述输出电路与RC滤波电路相连以复制输入电流并输出。
在本发明的一个或多个实施例中，所述输入电路包括第三MOS管，所述输出电路包括第四MOS管，所述第三MOS管的栅极和漏极短接且与外部电路相连，所述第三MOS管的栅极和RC滤波电路的第一端相连，所述第四MOS管的栅极与RC滤波电路的第二端相连。
在本发明的一个或多个实施例中，所述电流镜电路还包括第二电流源，所述第二电流源的第一端与电源电压、外部电路的第一端相连，所述第二电流源的第二端与外部电路第二端、第三MOS管的栅极和漏极相连，所述第二电流源用于提供与第一电流源提供的偏置电流相同的电流。
在本发明的一个或多个实施例中，所述外部电路提供的输入电流远大于RC滤波电路中的第一电流源提供的偏置电流。
本发明还公开了一种芯片，包括所述的伪电阻电路、所述的RC滤波电路和/或所述的电流镜电路。
与现有技术相比，根据本发明的伪电阻电路、RC滤波电路、电流镜电路及芯片，通过第一MOS管作为伪电阻并通过偏置电路给第一MOS管的栅极和源极之间提供用于使得第一MOS管工作于亚阈值区的偏置电压，并通过调节该偏置电压以调节第一MOS管的阻值，从而可以用较小的面积代价得到一个高阻值的电阻，这样一方面可以降低电阻的面积，另一方面为了实现相同的RC时间常数，可以将电容值取小，从而降低电容的面积。此外，该伪电阻的阻值受工艺-电压-温度(PVT)的影响较小，保证在工艺-电压-温度(PVT)变化的时候，该RC滤波器的滤波效果不会有大的变化。通过采用该伪电阻的方案，伪电阻的阻值可以很容易通过设置参数来达到一个合理的阻值，不至于阻值太小恶化滤波效果，也不至于太大而对漏电流非常敏感。
附图说明
图1是现有技术一的RC滤波器电路的电路原理图。
图2是现有技术二的采用伪电阻的RC滤波器的电路原理图。
图3是现有技术三的采用伪电阻的RC滤波器的电路原理图。
图4是根据本发明实施例一的伪电阻电路的电路原理图。
图5是根据本发明实施例二的伪电阻电路的电路原理图。
图6是根据本发明实施例三的RC滤波电路的电路原理图。
图7是根据本发明实施例四的电流镜电路的电路原理图。
具体实施方式
下面结合附图，对本发明的具体实施例进行详细描述，但应当理解本发明的保护范围并不受具体实施例的限制。
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
应当理解，在以下的描述中，“电路”可包括单个或多个组合的硬件电路、可编程电路、状态机电路和/或能存储由可编程电路执行的指令的元件。当称元件或电路“连接到”另一元件，或与另一元件“相连”，或称元件/电路“连接在”两个节点之间时，它可以直接耦合或连接到另一元件或者可以存在中间元件，元件之间的连接可以是物理上的、逻辑上的、或者其结合。相反，当称元件“直接耦合到”或“直接连接到”另一元件时，意味着两者不存在中间元件。
下面结合附图和实施例对本发明进一步说明。
实施例1
如图4所示，一种伪电阻电路，包括：第一MOS管M1以及偏置电路10，在本实施例中，第一MOS管M1为P沟道MOS管。
偏置电路10与第一MOS管M1的栅极和源极相连以给第一MOS管M1的栅极和源极之间提供用于使得第一MOS管M1工作于亚阈值区的偏置电压，并通过调节该偏置电压以调节第一MOS管M1的阻值，即确定了第一MOS管M1的栅-源电压就确定了第一MOS管M1的阻值。
如图4所示，偏置电路10包括第二MOS管M2、电阻R1和第一电流源A1。第二MOS管M2的源极与第一MOS管M1的源极相连，第二MOS管M2的漏极与电阻R1的第一端和第一MOS管M1的栅极相连，电阻R1的第二端与第二MOS管M2的栅极相连并且该连接点通过第一电流源A1与地电压相连。
在本实施例中，第二MOS管M2为P沟道MOS管。电阻R1为poly电阻，在其他实施例中，电阻R1可以为其他无源电阻或有源电阻。
在本实施例中，第一MOS管M1的栅-源电压等于第二MOS管M2的栅-源电压减去电阻R1上的电压，从而通过调节第二MOS管M2的栅-源电压或者电阻R1上的电压可以很方便地调节第一MOS管M1的阻值；即
|VgsM1|＝|VgsM2|-I1*R1  (1)，
|VgsM1|为第一MOS管M1的栅-源电压，|VgsM2|为第二MOS管M2的栅-源电压，I1为第一电流源A1给第二MOS管M2和电阻R1提供的偏置电流，R1为电阻R1的阻值。
若需增大第一MOS管M1的阻值，则需要减小|VgsM1|，可以通过增大I1*R1的值，或者也可以设定第一MOS管M1和第二MOS管M2的宽长比，第一MOS管M1的宽长比越小，第一MOS管M1的阻值越大，第二MOS管M2的宽长比越大，第一MOS管M1的阻值大。
在本实施例中，第一电流源A1可以是采用一个N沟道MOS管来实现或者其他可以充当实际电流源的电路结构来实现。
在本实施例中，为了减小漏电流，可以将第一MOS管M1的源极和衬底短接以及将第二MOS管M2的源极和衬底短接。
由公式(1)可得：
|VdsatM1|+|VthM1|＝|VdsatM2|+|VthM2|-I1*R1  (2)，
其中，|VdsatM1|为第一MOS管M1的饱和电压，|VthM1|为第一MOS管M1的阈值电压，|VdsatM2|为第二MOS管M2的饱和电压，|VthM2|为第二MOS管M2的阈值电压。
在本实施例中，第一MOS管M1的阈值电压|VthM1|和第二MOS管M2的阈值电压|VthM2|近似相等，在半导体工艺中，同一类型MOS管的阈值电压受工艺的影响具有一致性，因在公式(2)的两侧，所以第一MOS管M1的阈值电压|VthM1|随第二MOS管M2的阈值电压|VthM2|受工艺的影响可以相互抵消，由公式(2)可得：
|VdsatM2|＝|VdsatM1|+I1*R1  (3)。
第一MOS管M1的饱和电压|VdsatM2|和第二MOS管M2的饱和电压|VdsatM2|受工艺-电压-温度(PVT)的影响小。同时，I1由带隙基准电路提供的基准电压除以一电阻而得，电阻R1与该电阻成比例而能够将电阻所受到的工艺-电压-温度(PVT)的影响也抵消。
基于上述分析，通过提供给第一MOS管M1的栅极和源极之间的偏置电压为与第一MOS管M1的阈值电压|VthM1|相关的电压，从而使得偏置电路10能够跟踪第一MOS管M1的阈值电压|VthM1|随工艺-电压-温度(PVT)的变化，最终可使得在工艺-电压-温度(PVT)变化时，第一MOS管M1的阻值变化的较小。避免了在第一MOS管M1的栅极和漏极之间施加一固定电压(此时第一MOS管M1处于亚阈值区)来让 第一MOS管M1作为大电阻，在不同的工艺-电压-温度(PVT)下，导致第一MOS管M1的阻值变化较大、不稳定的问题。
实施例2
如图5所示，本实施例和实施例1的区别在于，第一MOS管M1为N沟道MOS管，第二MOS管M2为N沟道MOS管。对应的，偏置电路10内的连接方式也进行相应的改变。
具体的，第二MOS管M2的源极与第一MOS管M1的源极相连，第二MOS管M2的漏极与电阻R1的第一端和第一MOS管M1的栅极相连，电阻R1的第二端与第二MOS管M2的栅极相连并且该连接点通过第一电流源A1与电源电压相连。
实施例3
如图6所示，本实施例公开了一种RC滤波电路，包括伪电阻电路以及与伪电阻电路相连的电容C1。电容C1的第一端与第一MOS管M1的漏极相连，电容C1的第二端与地电压相连。
实施例4
如图7所示，本实施例公开了一种电流镜电路，包括如图6所示的RC滤波电路以及输入电路和输出电路，输入电路与外部电路20相连以接收外部电路20提供的输入电流I2，RC滤波电路与输入电路相连以对输入电流I2进行滤波，输出电路与RC滤波电路相连以复制输入电流I2并输出。
在本实施例中，输入电路包括第三MOS管M3，输出电路包括第四MOS管M4。在其他实施例中，输入电路和输出电路可以组成多层cascade结构。
在本实施例中，第三MOS管M3和第四MOS管M4均为NMOS管。
具体的，第三MOS管M3的栅极和漏极相连且与第一MOS管M1的源极以及外部电路20相连，外部电路20可以是电流镜、电流源或者其他结构的电路。第三MOS管M3的漏极用于接收外部电路20提供的输入电流I2，第三MOS管M3的源极与地电压相连。第四MOS管M4的栅极与电容C1的第一端以及第一MOS管M1的漏极相连，电容C1的第二端与地电压相连，第四MOS管的源极与地电压相连，第四MOS管M4的漏极用于输出电流。
通过RC滤波电路可以将高频噪声等通过电容C1过滤，而对于低频信号，则可以认为第三MOS管和第四MOS管的栅极短接在一起。
在其他实施例中，第三MOS管M3和第四MOS管M4可以均为PMOS管，对应的，可以采用图5所示的RC滤波电路。
在本实施例中，电流镜电路还包括第二电流源A2，第二电流源A2的第一端与电源电压相连，第二电流源A2的第二端与第三MOS管M3的栅极和漏极相连，第二电流源A2用于提供与第一电流源A1提供的偏置电流I1相同的电流。
通常对于电流镜电路来讲，希望外部电路20的输入电流I2可以被电流镜电路尽可能精确复制，而对于伪电阻电路内存在的第一电流源A1，其产生的偏置电流I1会成为电流镜电路镜像的一个误差来源。
所以设置第二电流源A2，在本实施例的电流镜电路与外部电路20相连时，通过第二电流源A2产生的电流I1对第一电流源A1产生的偏置电流I1进行补偿，使得外部电路20的输入电流I2能被电流镜电路精确复制。
在其他实施例中，可以使外部电路20提供的输入电流I2远大于RC滤波电路中的第一电流源A1提供的偏置电流I1，从而减小偏置电流I1带来的误差。
实施例5
本实施例公开了一种芯片，包括伪电阻电路、RC滤波电路和/或电流镜电路。
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。

Claims (10)

  1. 一种伪电阻电路，其特征在于，包括：
    第一MOS管；以及
    偏置电路，与第一MOS管的栅极和源极相连以给第一MOS管的栅极和源极之间提供用于使得第一MOS管工作于亚阈值区的偏置电压，并通过调节该偏置电压以调节第一MOS管的阻值；
    所述偏置电路包括依次相连的第二MOS管、电阻和第一电流源。
  2. 如权利要求1所述的伪电阻电路，其特征在于，所述第二MOS管的源极与第一MOS管的源极相连，所述第二MOS管的漏极与电阻的第一端和第一MOS管的栅极相连，所述电阻的第二端与第二MOS管的栅极相连，并且所述电阻的第二端与第二MOS管的连接点通过第一电流源与地电压或电源电压相连。
  3. 如权利要求1所述的伪电阻电路，其特征在于，所述第一MOS管的源极和衬底短接，和/或所述第二MOS管的源极和衬底短接。
  4. 如权利要求1所述的伪电阻电路，其特征在于，所述电阻包括无源电阻或有源电阻。
  5. 一种RC滤波电路，其特征在于，包括如权利要求1～4任一项所述的伪电阻电路以及与伪电阻电路相连的电容。
  6. 一种电流镜电路，其特征在于，包括如权利要求5所述的RC滤波电路以及输入电路和输出电路，所述输入电路与外部电路相连以接收外部电路提供的输入电流，所述RC滤波电路与输入电路相连以对输入电流进行滤波，所述输出电路与RC滤波电路相连以复制输入电流并输出。
  7. 如权利要求6所述的电流镜电路，其特征在于，所述输入电路包括第三MOS管，所述输出电路包括第四MOS管，所述第三MOS管的栅极和漏极短接且与外部电路相连，所述第三MOS管的栅极和RC滤波电路的第一端相连，所述第四MOS管的栅极与RC滤波电路的第二端相连。
  8. 如权利要求7所述的电流镜电路，其特征在于，所述电流镜电路还包括第二电流源，所述第二电流源的第一端与电源电压、外部电路的第一端相连，所述第二电流源的第二端与外部电路第二端、第三MOS管的栅极和漏极相连，所述第二电流源用于提供与第一电流源提供的偏置电流相同的电流。
  9. 如权利要求7所述的电流镜电路，其特征在于，所述外部电路提供的输入电流 远大于RC滤波电路中的第一电流源提供的偏置电流。
  10. 一种芯片，其特征在于，包括如权利要求1～4任一项所述的伪电阻电路、如权利要求5所述的RC滤波电路和/或如权利要求6～9任一项所述的电流镜电路。
PCT/CN2023/119352 2022-09-20 2023-09-18 伪电阻电路、rc滤波电路、电流镜电路及芯片 WO2024061153A1 (zh)

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