WO2024060757A1 - 一种芯片及其制备方法、电子设备 - Google Patents

一种芯片及其制备方法、电子设备 Download PDF

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Publication number
WO2024060757A1
WO2024060757A1 PCT/CN2023/103508 CN2023103508W WO2024060757A1 WO 2024060757 A1 WO2024060757 A1 WO 2024060757A1 CN 2023103508 W CN2023103508 W CN 2023103508W WO 2024060757 A1 WO2024060757 A1 WO 2024060757A1
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Prior art keywords
layer
substrate
hole section
chip
dielectric layer
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PCT/CN2023/103508
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English (en)
French (fr)
Inventor
李衡
董金文
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华为技术有限公司
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Publication of WO2024060757A1 publication Critical patent/WO2024060757A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the present application relates to the field of semiconductors, and in particular to a chip and its preparation method, and electronic equipment.
  • TSV Through silicon via
  • first illuminate the mask with an exposure light source copy the preset pattern on the mask to the photoresist, and then copy the pattern on the photoresist to the photoresist through etching.
  • the pattern on the photoresist can be etched onto a hard mask (HM), and then the pattern is etched and transferred to the substrate through the hard mask to form through holes inside the chip.
  • HM hard mask
  • the etching speed of some film layers is slow.
  • the etching speed of the low dielectric constant (low-k) layer is faster. Film layers with a fast etching rate and films with a slow etching rate will form holes on the side walls of the through holes. This phenomenon is called undercutting.
  • Embodiments of the present application provide a chip, a preparation method thereof, and electronic equipment. It solves the technical problem that the mask structure is side-cut during TSV etching, causing the metal pillar structure formed in the through hole to be discontinuous, resulting in poor electrical properties of the chip.
  • a chip in a first aspect, includes: a substrate, a stacked structure, a mask structure, a first dielectric layer, an insulating layer and a conductive layer; the stacked structure is stacked on the substrate; and the mask structure is stacked on On the stacked structure; a via hole extending in a direction perpendicular to the substrate is provided on the surface of the mask structure away from the substrate, and the via hole penetrates the mask structure, the stacked structure and the substrate; the via hole includes the through-mask structure, The first hole section of the laminated structure and the second hole section penetrating the substrate; the first dielectric layer covers the side wall of the first hole section; the insulating layer covers the first dielectric layer and the side wall of the second hole section, and is A filling space is enclosed within the via hole; the conductive layer is formed in the filling space.
  • a first dielectric layer is formed between the first hole section and the insulating layer.
  • the first dielectric layer is etched first, thereby protecting the portion of the stacked structure located in the first hole section from being etched, and avoiding the formation of side undercuts on the side walls of the first hole section.
  • the structure of the insulating layer will not be affected by damage defects on the inner wall surface of the first hole section. There will be no holes or other defects in the insulating layer that cause the insulating layer to be discontinuous, so that the conductive layer can achieve structural continuity. This ensures the electrical properties of the chip.
  • the substrate has a high etching selectivity ratio relative to the first dielectric layer.
  • the first dielectric layer will not be etched, and the stacked structure will not be dug out, thereby ensuring that the conductive layer is a continuous structure, thereby ensuring the electrical properties of the chip.
  • the edge of the first dielectric layer coincides with the edge of the second hole section.
  • the embodiment of the present application can ensure that the insulating layer There will be no sudden change in size at the position where the first dielectric layer and the second hole section are connected. In this way, the size of the conductive layer will not change suddenly, which is beneficial to ensuring the electrical properties of the chip.
  • the conductive layer has a first surface and a second surface parallel to the substrate, the first surface is a surface facing away from the substrate, and the second surface is a surface facing away from the mask structure; The surface is in the same plane as the surface of the mask structure facing away from the substrate; the second surface is in the same plane as the surface of the substrate facing away from the mask structure.
  • the conductive layer can be connected to the devices arranged on the side of the substrate away from the mask structure, and can also be connected to the devices arranged on the side of the mask structure away from the substrate, thereby achieving electrical connection between the conductive layer and multiple devices.
  • the first dielectric layer has a multi-layer structure; the multi-layer structure is sequentially stacked on the side wall of the first hole section along the radial direction of the via hole.
  • the first dielectric layer has a multi-layer structure, which further improves the reliability of the protective layer.
  • the material of the first dielectric layer includes at least one of silicon carbon nitride, silicon oxynitride, silicon oxide, silicon nitride, silicon oxycarbonitride, silicon carbide or silicon oxycarbon.
  • the chip further includes: a diffusion barrier layer, a liner layer and a seed layer; the insulating layer is covered with a diffusion barrier layer; the diffusion barrier layer is covered with a liner layer; the liner layer A seed layer is provided on the cover, and the seed layer is located between the insulating layer and the conductive layer.
  • the stacked structure is a multi-layer structure; the multi-layer structure is sequentially stacked on the substrate.
  • the stacked structure includes: a first oxide layer, a silicon nitride layer, a second oxide layer, a dielectric material layer, and a third oxide layer stacked in sequence on a substrate.
  • the chip further includes: a metal layer; the metal layer is disposed on the surface of the mask structure facing away from the substrate and/or on the surface of the substrate facing away from the mask structure; the conductive layer is electrically connected to the metal layer. connect.
  • the conductive layer and the device (or chip) are electrically connected through the metal layer to ensure the reliability of the electrical connection between the conductive layer and the device (or chip).
  • the chip further includes: a solder ball; the solder ball is disposed on the surface of the mask structure facing away from the substrate and/or on the surface of the substrate facing away from the mask structure, and on the surface of the conductive layer Contact, the solder ball is electrically connected to the conductive layer.
  • the material of the substrate includes single crystal silicon, single crystal germanium, gallium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, glass, At least one of plastic or sapphire wafers.
  • the mask structure includes a titanium nitride layer, a silicon nitride layer, an aluminum oxide or a silicon dioxide layer.
  • a method for manufacturing a chip includes: forming a stacked structure on a substrate, forming a mask structure on the stacked structure; and opening an opening on a surface of the mask structure facing away from the substrate perpendicular to the substrate.
  • the direction of the substrate penetrates the first hole section of the mask structure and the stacked structure; a first dielectric layer is formed on the side wall of the first hole section, so that the first dielectric layer covers the side wall of the first hole section; A second hole section penetrating the substrate in a direction perpendicular to the substrate is opened on the bottom surface of the first hole section with the first dielectric layer formed on the side wall, so as to open a hole section extending in the direction perpendicular to the substrate on the mask structure.
  • the side walls of the first hole section are A first dielectric layer is formed.
  • the first dielectric layer can protect the stacked structure, and the mask structure will not be lateral etched, thereby avoiding the formation of side undercuts on the side walls of the first hole section.
  • the insulating layer is formed on the first dielectric layer and the second hole segment, since there are no side undercuts formed on the side walls of the first hole segment, there will be no holes or other defects in the insulating layer that cause discontinuity in the insulating layer.
  • the conductive layer can achieve structural continuity, thereby ensuring the electrical properties of the chip.
  • the preparation method provided in the embodiment of the present application will not affect the process flow before forming the via hole, nor will it affect the process flow after forming the via hole, and is easy to implement.
  • forming the first dielectric layer includes: forming the first dielectric layer on the inner wall surface of the first hole section so that the first dielectric layer covers the inner wall surface of the first hole section; The first dielectric layer on the bottom surface of a hole segment is removed.
  • the first dielectric layer By removing the first dielectric layer on the bottom surface of the first hole section and then forming a second hole section located in the substrate, it can be ensured that the side wall surface of the first hole section is always covered with the first dielectric layer.
  • the first dielectric layer plays a role in protecting the stacked structure, and the mask structure will not be lateral etched, that is, no side digging will occur. In this way, when forming the conductive layer, it is possible to ensure the formation of a conductive layer with a continuous structure, thereby ensuring the electrical properties of the chip.
  • the edge of the first dielectric layer coincides with the edge of the second hole segment.
  • the chip produced in this way ensures that the side wall surface of the first hole section is always covered with the first dielectric layer, which plays a role in protecting the stacked structure.
  • the edge of the first dielectric layer coincides with the edge of the second hole segment, which can ensure that the size of the insulating layer will not change suddenly at the position where the first dielectric layer and the second hole segment are connected. In this way, the size of the conductive layer will not change.
  • the occurrence of mutations is beneficial to ensuring the electrical properties of the chip.
  • the first surface of the conductive layer and the surface of the mask structure facing away from the substrate are in the same plane; the second surface of the conductive layer and the surface of the substrate facing away from the mask structure are in the same plane; wherein the first surface is the surface of the conductive layer parallel to the substrate and facing away from the substrate, and the second surface is the surface of the conductive layer parallel to the substrate and facing away from the mask structure.
  • the conductive layer can be connected to the device arranged on the side of the substrate away from the mask structure, and can also be connected to the device arranged on the side of the mask structure away from the substrate, thereby realizing the conductive layer to be connected to multiple The electrical connections of the device.
  • forming the first dielectric layer includes: sequentially stacking a multi-layer structure on the sidewall of the first hole section along the radial direction of the via hole.
  • the preparation method further includes: forming a diffusion barrier layer on the insulation; forming a liner layer on the diffusion barrier layer; Forming a seed layer on the substrate to form a conductive layer includes: forming a conductive layer in an area surrounded by the seed layer.
  • forming a stacked structure includes: sequentially stacking a multi-layered structure on a substrate.
  • forming a stacked structure includes: sequentially stacking a first oxide layer, a silicon nitride layer, a second oxide layer, a dielectric material layer and a third oxide layer on a liner. bottom.
  • a metal layer is provided on a surface of the mask structure facing away from the substrate and/or on a surface of the substrate facing away from the mask structure; the metal layer and the conductive layer are electrically connected.
  • the substrate when the first dielectric layer is formed, the substrate has a high selectivity ratio relative to the first dielectric layer.
  • forming the conductive layer includes electroplating metal on the inner wall surface of the filling space surrounded by the seed layer to form the conductive layer.
  • metal materials can be stacked evenly everywhere on the surface of the seed layer, thereby forming a conductive layer with a continuous structure to ensure the electrical properties of the chip.
  • the same etching chamber is used when forming the via hole and when removing the first dielectric layer on the bottom surface of the via hole.
  • the processing accuracy can be guaranteed to the greatest extent.
  • the preparation method further includes: an ashing step, placing the chip in an ashing machine to remove the chip By-products in the preparation process; in the cleaning step, the chip is placed in a cleaning machine to remove by-products in the preparation process of the chip.
  • an electronic device in a third aspect, includes: a circuit board and the chip provided in the first aspect, and the chip is disposed on the circuit board.
  • Figure 1a is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 1b is a schematic diagram of the structure of a chip in an electronic device provided in FIG. 1a ;
  • Figure 2 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • Figure 3 is a disassembled schematic diagram of a chip shown in Figure 2;
  • FIG4 is a schematic diagram of forming a side recess on a chip
  • FIG. 5 is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of another chip provided by an embodiment of the present application.
  • Figure 9 is a process flow chart of a chip preparation method provided by an embodiment of the present application.
  • Figure 10a is a process structure diagram of a chip manufacturing method provided by an embodiment of the present application.
  • Figure 10b is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 10c is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • FIG10d is a process structure diagram of a chip manufacturing method provided in an embodiment of the present application.
  • Figure 10e is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 10f is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 11 is a process flow chart of a chip preparation method provided by an embodiment of the present application.
  • Figure 12a is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 12b is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 13 is a process flow chart of a chip preparation method provided by an embodiment of the present application.
  • Figure 14a is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 14b is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 15 is a process flow chart of a chip preparation method provided by an embodiment of the present application.
  • Figure 16a is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • Figure 16b is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • FIG16c is a process structure diagram of a chip manufacturing method provided in an embodiment of the present application.
  • Figure 17 is a process flow chart of a chip preparation method provided by an embodiment of the present application.
  • Figure 18a is a process structure diagram of a chip manufacturing method provided by an embodiment of the present application.
  • Figure 18b is a process structure diagram of a chip preparation method provided by an embodiment of the present application.
  • FIG18c is a process structure diagram of a chip manufacturing method provided in an embodiment of the present application.
  • Figure 19 is a process structure diagram of a chip manufacturing method provided by an embodiment of the present application.
  • Figure 20 is a process structure diagram of a chip manufacturing method provided by an embodiment of the present application.
  • At least one of the following or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple .
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same functions and effects.
  • words such as “first” and “second” do not refer to the quantity and order of execution. are limited, and words such as “first” and “second” are not limited to being different.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • An embodiment of the present application provides an electronic device, which is provided with an integrated chip.
  • the electronic device may be a mobile phone, a biological application device, etc.
  • the embodiments of the present application do not place any special restrictions on the specific form of the above-mentioned electronic device.
  • Figure 1a is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device includes: a chip 100 and a circuit board 200; the chip 100 is disposed on the circuit board 200.
  • the chip 100 can be provided on the electronic device as a memory, and the chip 100 can also be provided on the electronic device as a controller.
  • FIG. 1a only schematically shows some components included in the electronic device 10, and the actual shapes, actual sizes, actual positions and actual configurations of these components are not limited by FIG. 1a.
  • Figure 1b is a schematic structural diagram of a chip in the electronic device provided in Figure 1a.
  • the chip 100 includes a substrate 110, a stacked structure 1, a mask structure 2, a conductive layer 4, a via 5, a first device 120, a solder ball 130, and a second device 140 and metal layer 150 .
  • the stacked structure 1 and the mask structure 2 are arranged on the substrate 110 in sequence.
  • the via hole 5 penetrates the mask structure 2, the stacked structure 1 and the substrate 110 in a direction perpendicular to the substrate 110.
  • a conductive conductor is formed in the via hole 5.
  • the first device 120 disposed on the upper surface of the mask structure 2 is electrically connected to the conductive layer 4 through the metal layer 150 .
  • the second device 140 disposed on the lower surface of the substrate 110 is electrically connected to the conductive layer 4 through the solder ball 130 .
  • vertical electrical interconnection of the first device 120 and the second device 140 inside the chip 100 is achieved.
  • "vertical" in vertical electrical interconnection refers to the direction perpendicular to the substrate.
  • the chip provided by the embodiment of the present application can also realize vertical electrical interconnection between multiple chips. As shown in Figure 1b, the conductive layer 4 of the first chip 100a and the conductive layer 4 of the second chip 100b are connected through the metal layer 150 to achieve vertical electrical interconnection between the first chip 100a and the second chip 100b.
  • the three-dimensional stacking of the chips can be realized, making the chips have higher density and space utilization, thereby achieving a higher level of integration and performance of the chips. Better, thereby meeting the needs of smaller electronic devices and stronger performance.
  • the conductive layer As the key structure to achieve vertical electrical interconnection between devices and chips, should have a continuous structure. Specifically, if there are gaps or holes in the conductive layer locally, it will affect the resistance of the conductive layer, thereby affecting the electrical properties of the chip.
  • Embodiments of the present application provide a chip that can ensure uniform distribution of conductive layer materials, continuous structure, and no breakage, thereby ensuring the electrical properties of the chip.
  • FIG. 2 shows a schematic structural diagram of a chip provided by an embodiment of the present application.
  • the chip 100 includes a substrate 110 , a stacked structure 1 , a mask structure 2 , a first dielectric layer 3 , a conductive layer 4 and an insulating layer 6 .
  • substrate 110 there are many materials that can be selected for the substrate 110, including single crystal silicon (Si), single crystal germanium (Ge), gallium arsenide, indium phosphide, III-V compound semiconductor materials, II-VI compound semiconductor materials, or Alternatively, substrate 110 may be made from at least one of other semiconductor materials known in the art, or from a non-conductive material such as glass, plastic, or sapphire wafers.
  • the stacked structure 1 is stacked on the substrate 110 .
  • the laminated structure 1 may be a multi-layer structure.
  • the stacked structure 1 includes: a first oxide layer 11, a silicon nitride layer 12, a second oxide layer 13, a dielectric material layer 14 and a third oxide layer sequentially stacked on a substrate 110.
  • the first oxide layer 11 , the second oxide layer 13 and the third oxide layer 15 may be made of the same material or different materials.
  • the material of the dielectric material layer 14 is a low dielectric constant material.
  • the silicon nitride layer 12 has the function of shielding impurity contamination.
  • the material of the first oxide layer 11, the second oxide layer 13 and the third oxide layer 15 is silicon dioxide (SiO 2 )
  • the material of the dielectric material layer 14 is silicon nitride (Si 3 N4 ).
  • the material of the dielectric material layer 14 has low dielectric constant (low-k) characteristics, and is also called a low-k layer.
  • the low-k layer is a porous material and is easily etched.
  • the mask structure 2 is stacked on the stacked structure 1 to implement multiple photolithography processes. Specifically, the image of the photoresist can be transferred to the mask structure 2 by etching, and then the image on the mask structure 2 can be transferred to the stacked structure 1 and the substrate 110 by etching.
  • the mask structure 2 may be an inorganic thin film material generated by chemical vapor deposition (Chemical Vapor Deposition, CVD).
  • the mask structure 2 may be a multi-layer structure, and the materials used usually include titanium nitride (TiN), silicon nitride (Si 3 N 4 ), dioxide Silicon (SiO 2 ), etc.
  • the mask structure may include at least one of a titanium nitride layer, a silicon nitride layer, an aluminum oxide layer, or a silicon dioxide layer.
  • a via hole 5 extending in a direction A perpendicular to the substrate is opened on the upper surface 2a of the mask structure 2 away from the substrate 110, and the via hole 5 penetrates the mask Structure 2, stacked structure 1 and substrate 110.
  • the via hole 5 may be a round hole, a square hole, or a tapered hole with a gradually smaller cross-section along the direction A perpendicular to the substrate as shown in FIG. 2 . This application does not specifically limit the shape of the via hole 5 .
  • the via hole 5 includes a first hole section 51 that penetrates the mask structure 2 and the stacked structure 1, and a second hole section 52 that penetrates the substrate.
  • the process of forming the first hole segment 51 is a process of transferring the photoresist image to the mask structure 2 and the stacked structure 1 .
  • the process of forming the second hole section 52 is a process of transferring the image etching on the mask structure 2 to the substrate 110 .
  • etching starts from the side of the mask structure 2 away from the substrate 110. That is to say, the first hole segment 51 must be formed first, and then the third hole segment 51 must be formed. Two hole section 52.
  • the substrate 110 is not affected when the first hole section 51 is formed. However, when forming the second hole section 52, the substrate 110 is etched in the first hole section 51 along the direction A perpendicular to the substrate 110. Therefore, the sidewalls of the first hole section 51 will also be etched. Impact, that is, the mask structure 2 and the stacked structure 1 will also be affected.
  • the sidewall 51a of the first hole section 51 is covered with the first dielectric layer 3.
  • the first dielectric layer 3 is etched first.
  • the portions of the mask structure 2 and the stacked structure 1 located on the sidewall 51a of the first hole section 51 are not etched, and thus no damage is caused.
  • the first dielectric layer 3 there are many materials that can be selected for the first dielectric layer 3, such as silicon dioxide material, or other materials that form sidewall protection layers, including but not limited to at least one of silicon carbon nitride (SiCN), silicon oxynitride (SION), silicon oxide (SiO 2 ), silicon nitride (SIN), silicon oxycarbon nitride (SIOCN), silicon carbide (SIC) or silicon oxycarbon (SIOC).
  • SiCN silicon carbon nitride
  • SION silicon oxide
  • SiO 2 silicon nitride
  • SIN silicon nitride
  • SIOCN silicon oxycarbon nitride
  • SIOC silicon oxycarbon
  • the sidewall of the first hole segment 51 will be affected by etching. Lateral etching occurs (etching the mask structure 2 in a direction parallel to the substrate 110). Because the laminated structure 1 is a multi-layer structure, and the materials of each adjacent two-layer structure are different. Therefore, under the same etching conditions, the etching rates of each adjacent two-layer structure are different. In this way, the film layer with a faster etching rate will be concave relative to the film layer with a slower etching rate, forming an undercut.
  • the dielectric material layer 14 and the silicon nitride layer 12 have a faster etching rate. In the same time, they are etched More material is eroded away. In this way, since the silicon nitride layer 12 has more material etched away than the first oxide layer 11 and the second oxide layer 13 , a first hole will be formed on the side wall of the first hole section 51 . Hole 7. Since more material is etched away from the dielectric material layer 14 than from the second oxide layer 13 and the third oxide layer 15 , the second hole 8 will be formed on the side wall of the first hole section 51 .
  • the mask structure 2 can be protected. Therefore, during the process of forming the via hole 5, the laminated structure 1 will not be dug out.
  • the first dielectric layer 3 can be formed by vapor deposition.
  • the first dielectric layer 3 obtained in this way completely covers the sidewall 51a of the first hole section 51. Even if there are defects (such as depressions) on the sidewall 51a of the first hole section 51, the first dielectric layer 3 can completely cover the defects, so that the first dielectric layer 3 has a continuous structure without holes.
  • the substrate 110 has a high etching selectivity ratio relative to the first dielectric layer 3 .
  • the etching selectivity ratio is expressed as: the ratio of the etching rate of the material to be etched to the etching rate of another material.
  • a high selectivity means that only the layer of material you want to be etched away is removed.
  • the insulating layer 6 is covered on the first dielectric layer 3 and the side wall of the second hole segment 52 .
  • the structure of the insulating layer 6 will not be affected by damage defects on the sidewall 51a of the first hole section 51.
  • the insulation There will be no holes or other defects in layer 6 that would cause the insulating layer 6 to be discontinuous.
  • the conductive layer 4 is formed in the filling space 6 a surrounded by the insulating layer 6 .
  • conductive layer 4 is formed by electroplating. Since there are no holes or other defects in the insulating layer 6 that cause the insulating layer 6 to be discontinuous, the conductive layer 4 can achieve structural continuity, thereby ensuring the electrical properties of the chip 100 . It can be understood that the conductive layer 4 may be formed in the filling space 6a The columnar structure may also be a thin film structure formed in the filling space 6a.
  • the chip also includes a diffusion barrier layer 62, a liner layer 63 and a seed layer 64; the insulating layer 6 is covered with a diffusion barrier layer 62; The diffusion barrier layer 62 is covered with a liner layer 63; the liner layer 63 is covered with a seed layer 64, and the conductive layer 4 is formed in the area 64a surrounded by the seed layer 64.
  • the edge 3b of the first dielectric layer 3 coincides with the edge 52a1 of the second hole section 52. In this way, it is not only ensured that the size of the conductive layer 4 transitions naturally near the position where the first dielectric layer 3 and the second hole section 52 are connected, but also ensures that the side wall surface 51a of the first hole section 51 is always covered with the first dielectric layer 3 , playing the role of protecting the laminated structure 1.
  • the conductive layer 4 has a first surface 4a and a second surface 4b parallel to the substrate.
  • the first surface 4a is the surface facing away from the substrate 110
  • the second surface 4b is the surface facing away from the mask structure 2
  • the first surface 4a is in the same plane as the upper surface 2a of the mask structure 2 facing away from the substrate 110
  • the second surface 4b is in the same plane as the mask structure 2
  • the lower surface 110a of the bottom 110 facing away from the mask structure 2 is in the same plane.
  • the conductive layer 4 can be connected to devices or chips disposed on the side of the substrate 110 away from the mask structure 2, and can also be connected to devices or chips disposed on the side of the mask structure 2 away from the substrate 110, thereby realizing the conductive layer. 4. Electrical connection to multiple devices or chips.
  • the second surface 4b of the conductive layer 4 may extend beyond the lower surface 110a of the substrate 110 away from the mask structure 2, that is, the conductive layer 4 is exposed to the substrate 110 for a certain distance.
  • the conductive layer will not be directly electrically connected to the device (or chip), but will be electrically connected to the device (or chip) through a metal layer, or the conductive layer will be electrically connected to the device (or chip) through a solder ball (as shown in Figure 1a).
  • the layers are electrically connected to the device (or chip).
  • a metal layer 150 is disposed on the upper surface 2a of the mask structure 2 facing away from the substrate 110 and/or on the lower surface 110a of the substrate 110 facing away from the mask structure 2; the metal layer 150 is electrically connected to the conductive layer 4.
  • the metal layer 150 is disposed on the upper surface 2a of the mask structure 2 facing away from the substrate 110, and on the lower surface 110a of the substrate 110 facing away from the mask structure 2, and the metal layer 150 is located on the first surface 4a and the second surface 4b of the conductive layer 4.
  • the first dielectric layer 3 has a multi-layer structure; the multi-layer structure is sequentially stacked on the sidewall 51 a of the first hole section 51 along the radial direction B of the via hole 5 .
  • the first dielectric layer 3 includes a first film layer 31 and a second film layer 32 , and the first film layer 31 and the second film layer 32 are along the radial direction B of the via hole 5 Stacked on the side wall 51a (shown in Figure 3) of the first hole section 51 in sequence.
  • the first dielectric layer is formed between the first hole segment and the insulating layer.
  • the first dielectric layer is etched first, thereby protecting the portion of the stacked structure located in the first hole section from being etched, and avoiding the formation of side undercuts on the side walls of the first hole section.
  • the structure of the insulating layer will not be affected by damage defects on the inner wall surface of the first hole section. There will be no holes or other defects in the insulating layer that cause the insulating layer to be discontinuous, so that the conductive layer can achieve structural continuity. This ensures the electrical properties of the chip.
  • Embodiments of the present application also provide a method of manufacturing a chip. An achievable method of manufacturing a chip will be specifically introduced below in conjunction with the process flow chart shown in Figure 9 and the process structure diagrams of Figures 10a to 10f. As shown in Figure 9, the process flow chart includes steps S1-S7.
  • a stacked structure 1 is formed on the substrate 110.
  • the first oxide layer 11 , the silicon nitride layer 12 , the second oxide layer 13 , the dielectric material layer 14 and the third oxide layer 15 are sequentially stacked on the substrate 110 .
  • a mask structure 2 is formed on the stacked structure 1.
  • a first hole segment 51 is opened on the upper surface 2 a of the mask structure 2 facing away from the substrate 110 and passes through the mask structure 2 and the stacked structure 1 in a direction A perpendicular to the substrate 110 .
  • the first dielectric layer 3 is formed on the side wall 51a of the first hole section 51, so that the first dielectric layer 3 covers the side wall 51a of the first hole section 51.
  • a second hole penetrating the substrate 110 in the direction A perpendicular to the substrate 110 is opened on the first bottom surface 51b of the first hole section 51 of the first dielectric layer 3 on the side wall 51a.
  • the edge of the first dielectric layer 3 coincides with the edge of the second hole section 52 at the position where the first dielectric layer 3 and the second hole section 52 are connected.
  • the substrate 110 may be a silicon wafer, which is etched in a silicon etching chamber to form a second hole in the substrate 110 Paragraph 52.
  • an insulating layer 6 is formed on the side walls of the first dielectric layer 3 and the second hole section 52, so that the insulating layer 6 covers the first dielectric layer 3 and the second hole section 52.
  • thermal oxidation is used to grow the insulating layer 6, and the material of the insulating layer 6 may be silicon dioxide.
  • the conductive layer 4 is formed in the filling space 6a surrounded by the insulating layer 6.
  • step S4 after performing S3 and before performing S5, when forming the second hole segment 52, the first dielectric layer 3 can protect the mask structure 2, and the mask structure 2 will not be subjected to lateral etching. , to avoid undercutting from forming on the side wall 51a of the first hole section 51.
  • the insulating layer 6 is formed on the first dielectric layer 3 and the second hole segment 52, since there is no undercut formed on the side wall 51a of the first hole segment 51, there will be no holes or other defects in the insulating layer 6. 6 discontinuous defects.
  • the conductive layer 4 is formed in the filling space 6a surrounded by the insulating layer 6, the conductive layer 4 can achieve structural continuity, thereby ensuring the electrical properties of the chip.
  • the embodiments of the present application can fundamentally solve the problem of side digging of the laminated structure 1 without changing the process steps before step S3 and after step S5.
  • steps S401-S402 are included.
  • An achievable preparation method of the chip will be introduced in detail below in conjunction with the process flow chart shown in Figure 11 and the process structure diagrams of Figures 12a to 12b. As shown in Figure 11, the process flow chart includes steps S401-S402.
  • the first dielectric layer 3 is formed on the inner wall surface of the first hole section 51, so that the first dielectric layer 3 covers the inner wall surface of the first hole section 51.
  • the first dielectric layer 3 located on the first bottom surface 51b of the first hole section 51 can be removed in a dielectric etching cavity.
  • the first dielectric layer 3 located on the first bottom surface 51b of the first hole section 51 can be removed in a TSV etching cavity. In this way, when performing steps S5 and S402, the same etching cavity can be used to avoid replacing the etching cavity, thereby ensuring the processing accuracy to the maximum extent.
  • the first dielectric layer 3 includes a first portion 31 covering the side wall of the first hole segment 51 , and a second portion 32 located on the first bottom surface 51 b of the first hole segment 51 , and the second portion 32 is removed.
  • step S5 when the second hole segment 52 is formed, the substrate 110 may be directly penetrated. However, if the thickness of the substrate 110 is relatively large, or if it is not suitable to penetrate the substrate 110 , when forming the second hole section 52 , the substrate 110 may not be penetrated first. Instead, after the second hole section 52 is formed, excess material of the substrate 110 is removed to obtain a structure in which the second hole section 52 penetrates the substrate 110 .
  • steps S501-S502 are included.
  • An achievable preparation method of the chip will be introduced in detail below in conjunction with the process flow chart shown in Figure 13 and the process structure diagrams of Figures 14a to 14b. As shown in Figure 13, the process flow chart includes steps S501-S502.
  • a second hole section 52 extending in the direction A perpendicular to the substrate 110 is opened on the first bottom surface 51b of the first hole section 51 of the first dielectric layer 3 on the side wall 51a. At this time, the second hole section 52 does not penetrate the substrate 110 .
  • S502 as shown in FIG. 14b, remove the portion 11 of the substrate 110 from the second bottom surface 52a of the second hole segment 52 to the lower surface 110a of the substrate 110 away from the mask structure 2. At this time, as shown in FIG. 10d, the second hole segment 52 penetrates the substrate 110.
  • step S6 and step S7 are first executed.
  • a feasible method for preparing a chip is specifically introduced.
  • a stacked structure 1 is formed on the substrate 110.
  • a mask structure 2 is formed on the stacked structure 1.
  • a first hole segment 51 penetrating the mask structure 2 and the stacked structure 1 in the direction A perpendicular to the substrate 110 is opened on the upper surface 2a of the mask structure 2 away from the substrate 110.
  • the first dielectric layer 3 is formed on the side wall 51a of the first hole section 51, so that the first dielectric layer 3 covers the side wall 51a of the first hole section 51.
  • a second hole section 52 extending in the direction A perpendicular to the substrate 110 is opened on the first bottom surface 51b of the first hole section 51 of the first dielectric layer 3 on the side wall 51a. At this time, the second hole section 52 does not penetrate the substrate 110 .
  • an insulating layer 6 is formed on the side walls of the first dielectric layer 3 and the second hole section 52, so that the insulating layer 6 covers the first dielectric layer 3 and the second hole section 52.
  • the conductive layer 4 is formed in the filling space 6a surrounded by the insulating layer 6.
  • the preparation method also includes steps S61-S63.
  • steps S61-S63 The following will specifically introduce an alternative method of the chip in conjunction with the process flow chart shown in Figure 17 and the process structure diagrams of Figures 18a to 18c. Implemented preparation methods.
  • a diffusion barrier layer 62 is formed on the insulating layer 6.
  • PECVD plasma enhanced chemical vapor deposition
  • SACVD subatmospheric chemical vapor deposition
  • SACVD atmospheric pressure chemical vapor deposition
  • APCVD chemical vapor deposition or chemical liquid deposition method.
  • a seed layer 64 is formed on the liner layer 63.
  • the conductive layer 4 is formed in the area 64a surrounded by the seed layer 64.
  • the conductive layer can be electrically connected to a device or chip disposed on a side of the mask structure away from the substrate.
  • the conductive layer is exposed by removing material.
  • the preparation method further includes: when forming the conductive layer 4, such that The first surface 4a of the conductive layer 4 is in the same plane as the upper surface 2a of the mask structure 2 facing away from the substrate 110; the second surface 4b of the conductive layer 4 is in the same plane as the lower surface 110a of the substrate 110 facing away from the mask structure 2. In the same plane; wherein, the first surface 4a is the surface of the conductive layer 4 that is parallel to the substrate 110 and away from the substrate 110, and the second surface 4b is the surface of the conductive layer 4 that is parallel to the substrate 110 and away from the mask structure 2 s surface.
  • grinding can be used to realize that the first surface 4a of the conductive layer 4 and the upper surface 2a of the mask structure 2 facing away from the substrate 110 are in the same plane, and to realize that the second surface 4b of the conductive layer 4 is in the same plane. In the same plane as the lower surface 110 a of the substrate 110 facing away from the mask structure 2 .
  • the conductive layer will not be directly electrically connected to the device (or chip), but will be electrically connected to the device (or chip) through a metal layer, or the conductive layer and the device (or chip) will be electrically connected through solder balls. Electrical connection.
  • a metal layer 150 is provided on the upper surface 2a of the mask structure 2 facing away from the substrate 110 and/or on the lower surface 110a of the substrate 110 facing away from the mask structure 2; the metal layer 150 is electrically connected to the conductive layer 4.
  • the preparation method also includes an ashing step.
  • the cleaning step the chip is placed in an ashing machine to remove by-products of the chip preparation process; in the cleaning step, the chip is placed in a cleaning machine to remove by-products of the chip preparation process.

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Abstract

本申请实施例提供一种芯片及其制备方法、电子设备。解决了TSV刻蚀时掩膜结构发生侧掏导致通孔内形成的金属柱电性差的技术问题。该芯片包括：衬底、叠层结构、掩膜结构、第一介质层、绝缘层以及导电层；叠层结构、掩膜结构依次堆叠在叠层结构上；芯片包括贯通掩膜结构、叠层结构的第一孔段，以及贯通衬底的第二孔段；第一介质层覆盖第一孔段的侧壁；第一介质层能够保护掩膜结构不被刻蚀，避免第一孔段的侧壁上形成侧掏。绝缘层围成的填充空间内形成有导电层，这样，绝缘层的结构不会受到第一孔段的内壁面上的损伤缺陷的影响而产生孔洞等缺陷，进而导电层能够实现结构连续，从而保证芯片的电性。

Description

一种芯片及其制备方法、电子设备
本申请要求于2022年09月22日提交国家知识产权局、申请号为202211158528.2、申请名称为“一种芯片及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，尤其涉及一种芯片及其制备方法、电子设备。
背景技术
硅通孔(through silicon via，TSV)刻蚀，先通过曝光光源照射掩模版，将掩模版上的预设图案复制到光刻胶上，然后通过刻蚀将光刻胶上的图案复刻到其他结构上。比如，可以将光刻胶上的图案复刻到硬掩模(hard mask，HM)上，然后通过硬掩模将图案刻蚀转移到衬底上，以在芯片的内部形成通孔。
硬掩膜为多层结构时，在通过TSV刻蚀产生通孔的过程中，位于衬底和硬掩模之间的多个膜层由于膜层材料的不同，有的膜层刻蚀速度快，有的膜层刻蚀速度慢。比如相比氧化物层，低介电常数(low-k)层的刻蚀速度更快。刻蚀速率快的膜层和刻蚀速度慢的膜层会在通孔的侧壁上形成孔洞，这种现象叫做侧掏。
在产生侧掏的通孔的侧壁上继续堆叠绝缘层等其他膜层时，比如沉积氧化硅膜层时，氧化硅膜层部分生长在通孔的侧壁上，部分生长在孔洞内，会造成膜层不连续的问题。此时，通过电镀形成金属柱时，膜层不连续的位置由于不能通电而不能电镀金属，造成金属柱的结构不连续，影响芯片的电性。
发明内容
本申请实施例提供一种芯片及其制备方法、电子设备。解决了TSV刻蚀时掩膜结构发生侧掏导致通孔内形成的金属柱结构不连续，导致芯片电性差的技术问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种芯片，该芯片包括：衬底、叠层结构、掩膜结构、第一介质层、绝缘层以及导电层；叠层结构堆叠在衬底上；掩膜结构堆叠在叠层结构上；掩膜结构背离衬底的表面上开设有朝垂直于衬底的方向延伸的过孔，过孔贯通掩膜结构、叠层结构和衬底；过孔包括贯通掩膜结构、叠层结构的第一孔段，以及贯通衬底的第二孔段；第一介质层覆盖第一孔段的侧壁；绝缘层覆盖第一介质层、第二孔段的侧壁，并在过孔内围出填充空间；导电层形成在填充空间内。
基于上述对本申请实施例提供的芯片的结构描述，可以看出，该芯片中，相比第二孔段直接覆盖绝缘层，第一孔段和绝缘层之间形成有第一介质层。一方面，在发生横向刻蚀时，先被刻蚀的是第一介质层，从而保护叠层结构位于第一孔段的部分不被刻蚀，避免第一孔段的侧壁上形成侧掏。另一方面，绝缘层的结构不会受到第一孔段的内壁面上的损伤缺陷的影响，绝缘层上不会有孔洞或其他导致绝缘层不连续的缺陷，进而导电层能够实现结构连续，从而保证芯片的电性。
在第一方面可实现的实施方式中，衬底相对于第一介质层具有高刻蚀选择比。
这样，在形成第二孔段时，第一介质层越不会被刻蚀，叠层结构不会发生侧掏，从而保证导电层是连续的结构，进而保证芯片的电性。
在第一方面可实现的实施方式中，第一介质层与第二孔段相接的位置上，第一介质层的边缘与第二孔段的边缘重合。
这样，保证第一孔段的侧壁面上始终覆盖有第一介质层，起到保护叠层结构的作用。另外，第一介质层的边缘与第二孔段的边缘重合，相比第一介质层围成的过孔的径向尺寸大于第二孔段的径向尺寸，本申请实施例能够保证绝缘层在第一介质层与第二孔段相接的位置上尺寸不会发生突变，这样，导电层的尺寸不会发生突变，有利于保证芯片的电性。
在第一方面可实现的实施方式中，导电层具有平行于衬底的第一表面和第二表面，第一表面为背离衬底的表面，第二表面为背离掩膜结构的表面；第一表面与掩膜结构的背离衬底的表面在同一平面内；第二表面与衬底的背离掩膜结构的表面在同一平面内。
这样，导电层能够与设置在衬底远离掩膜结构的一侧的器件连接，也能与设置在掩膜结构远离衬底的一侧的器件连接，从而实现导电层与多个器件的电连接。在第一方面可实现的实施方式中，第一介质层为多层结构；多层结构沿过孔的径向依次层叠在第一孔段的侧壁上。
第一介质层为多层结构，进一步提高保护层的可靠性。
在第一方面可实现的实施方式中，第一介质层的材质包括硅碳氮、硅氧氮、氧化硅、氮化硅、硅氧碳氮、碳化硅或硅氧碳中的至少一种。
在第一方面可实现的实施方式中，芯片还包括：扩散阻挡层、衬垫层以及籽晶层；绝缘层上覆盖有扩散阻挡层；扩散阻挡层上覆盖有衬垫层；衬垫层上覆盖设置有籽晶层，籽晶层位于绝缘层和导电层之间。
这样，通过增加扩散阻挡层、衬垫层以及籽晶层，更有利于形成结构连续的导电层。
在第一方面可实现的实施方式中，叠层结构为多层结构；多层结构依次层叠在衬底上。
在第一方面可实现的实施方式中，叠层结构包括：依次堆叠在衬底上的第一氧化物层、氮化硅层、第二氧化物层、介电材料层以及第三氧化物层。
在第一方面可实现的实施方式中，芯片还包括：金属层；金属层设置在掩膜结构背离衬底的表面上和/或衬底背离掩膜结构的表面上；导电层与金属层电连接。
通过金属层将导电层和器件(或芯片)电连接，保证导电层与和器件(或芯片)电连接的可靠性。
在第一方面可实现的实施方式中，芯片还包括：锡球；锡球设置在掩膜结构背离衬底的表面上和/或衬底背离掩膜结构的表面上，且于导电层的表面接触，锡球与导电层电连接。
在第一方面可实现的实施方式中，衬底的材质包括单晶硅、单晶锗、砷化镓、磷化铟、III-V族化合物半导体材料、II-VI族化合物半导体材料、玻璃、塑料或蓝宝石晶圆中的至少一种。
在第一方面可实现的实施方式中，掩膜结构包括氮化钛层、氮化硅层、氧化铝或二氧化硅层。
第二方面，提供了一种芯片的制备方法，该制备方法包括：在衬底上形成叠层结构，在叠层结构形成掩膜结构；在掩膜结构背离衬底的表面上开设朝垂直于衬底的方向贯通掩膜结构、叠层结构的第一孔段；在第一孔段的侧壁上形成第一介质层，使得第一介质层覆盖在第一孔段的侧壁上；在侧壁上形成有第一介质层的第一孔段的底面上开设朝垂直于衬底的方向贯通衬底的第二孔段，以在掩膜结构上开设朝垂直于衬底的方向延伸的包含第一孔段和第二孔段在内的过孔；在第一介质层、第二孔段的侧壁上形成绝缘层，使得绝缘层覆盖第一介质层和第二孔段，且在过孔内围出填充空间；在填充空间内形成导电层。
基于上述对本申请实施例提供的芯片的制备方法的描述，可以看出，该制备方法中，在形成第一孔段之后，在形成第二孔段之前，要在第一孔段的侧壁上形成第一介质层。这样，在形成第二孔段时，第一介质层可以保护叠层结构，掩膜结构不会受到横向刻蚀，避免第一孔段的侧壁上形成侧掏。进而，在第一介质层和第二孔段上形成绝缘层时，由于第一孔段的侧壁上没有形成侧掏，绝缘层上不会有孔洞或其他导致绝缘层不连续的缺陷。在绝缘层上形成导电层时，导电层能够实现结构连续，从而保证芯片的电性。
以及，本申请实施例给出的制备方法，不会影响形成过孔之前的工艺流程，也不会影响形成过孔之后的工艺流程，具有实施便捷的特点。
在第二方面可实现的实施方式中，形成第一介质层，包括：在第一孔段的内壁面上形成第一介质层，使得第一介质层覆盖第一孔段的内壁面；将第一孔段的底面上的第一介质层去除。
通过将第一孔段的底面上的第一介质层去除，再形成位于衬底内的第二孔段，能够保证第一孔段的侧壁面上始终覆盖有第一介质层，在形成第二孔段的过程中，第一介质层起到保护叠层结构的作用，掩膜结构不会受到横向刻蚀，即侧掏不会产生侧掏。这样，在形成导电层时，能够保证形成结构连续的导电层，从而保证芯片的电性。
在第二方面可实现的实施方式中，形成第二孔段时，使得第一介质层与第二孔段相接的位置 上，第一介质层的边缘与第二孔段的边缘重合。
这样制得的芯片，保证第一孔段的侧壁面上始终覆盖有第一介质层，起到保护叠层结构的作用。另外，第一介质层的边缘与第二孔段的边缘重合，能够保证绝缘层在第一介质层与第二孔段相接的位置上尺寸不会发生突变，这样，导电层的尺寸不会发生突变，有利于保证芯片的电性。
在第二方面可实现的实施方式中，形成导电层时，使得导电层的第一表面与掩膜结构的背离所述衬底的表面在同一平面内；导电层的第二表面与衬底的背离所述掩膜结构的表面在同一平面内；其中，所述第一表面为导电层的平行于衬底且背离衬底的表面，第二表面为导电层的平行于衬底且背离掩膜结构的表面。
这样制得的芯片，导电层能够与设置在衬底远离掩膜结构的一侧的器件连接，也能与设置在掩膜结构远离衬底的一侧的器件连接，从而实现导电层与多个器件的电连接。
在第二方面可实现的实施方式中，形成第一介质层，包括：将多层结构沿过孔的径向依次层叠在第一孔段的侧壁上。
在第二方面可实现的实施方式中，在形成绝缘层之后，在形成导电层之前，制备方法还包括：在绝缘上形成扩散阻挡层；在扩散阻挡层上形成衬垫层；在衬垫层上形成籽晶层，形成导电层，包括：在籽晶层围成的区域内形成导电层。
在第二方面可实现的实施方式中，形成叠层结构，包括：将多层结构依次堆叠在衬底上。
在第二方面可实现的实施方式中，形成叠层结构，包括：将第一氧化物层、氮化硅层、第二氧化物层、介电材料层以及第三氧化物层依次堆叠在衬底上。
在第二方面可实现的实施方式中，在掩膜结构背离衬底的表面上和/或衬底背离掩膜结构的表面上设置金属层；将金属层和导电层电连接。
在第二方面可实现的实施方式中，在形成第一介质层时，使得衬底相对于第一介质层具有高选择比。
衬底相对于第一介质层的选择比越大，通过刻蚀衬底形成第二镂空区域时，第一介质层越不会被刻蚀，掩膜结构越不会受到横向刻蚀，从而提高第一介质层保护叠层结构的可靠性。
在第二方面可实现的实施方式中，在形成导电层时，包括：在籽晶层围成的填充空间的内壁面上电镀金属，以形成导电层。
通过电镀，使得籽晶层的表面上每一处都能够均匀的堆叠金属材料，进而形成结构连续的导电层，从而保证芯片的电性。
在第二方面可实现的实施方式中，在形成过孔时，以及，将过孔的底面上的第一介质层去除时，使用同一个刻蚀腔。
通过使用同一个刻蚀腔，避免更换刻蚀腔，能够最大限度的保证加工的精度。
在第二方面可实现的实施方式中，在第一介质层围成的填充空间内形成导电层之后，所述制备方法还包括：灰化步骤，将芯片置于灰化机台中，以去除芯片在制备过程中的副产物；清洗步骤，将芯片置于清洗机中，以去除芯片在制备过程中的副产物。
第三方面，提供一种电子设备，该电子设备包括：电路板和第一方面提供的芯片，芯片设置在电路板上。
附图说明
图1a为本申请实施例提供的一种电子设备的结构示意图；
图1b为图1a提供的一种电子设备中芯片的结构示意图；
图2为本申请实施例提供的一种芯片的结构示意图；
图3为图2所示的一种芯片的拆分示意图；
图4为芯片上形成侧掏的示意图；
图5为本申请实施例提供的另一种芯片的结构示意图；
图6为本申请实施例提供的另一种芯片的结构示意图；
图7为本申请实施例提供的另一种芯片的结构示意图；
图8为本申请实施例提供的又一种芯片的结构示意图；
图9为本申请实施例提供的一种芯片的制备方法的工艺流程图；
图10a为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图10b为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图10c为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图10d为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图10e为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图10f为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图11为本申请实施例提供的一种芯片的制备方法的工艺流程图；
图12a为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图12b为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图13为本申请实施例提供的一种芯片的制备方法的工艺流程图；
图14a为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图14b为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图15为本申请实施例提供的一种芯片的制备方法的工艺流程图；
图16a为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图16b为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图16c为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图17为本申请实施例提供的一种芯片的制备方法的工艺流程图；
图18a为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图18b为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图18c为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图19为本申请实施例提供的一种芯片的制备方法的工艺结构图；
图20为本申请实施例提供的一种芯片的制备方法的工艺结构图。
附图标记：
10-电子设备；
100-芯片，200-电路板；
120-第一器件，130-锡球，140-第二器件，150-金属层；
110-衬底，110a-下表面，111-第一部分，
1-叠层结构，11-第一氧化物层，12-氮化硅层，13-第二氧化物层，14-介电材料层，15-第三
氧化物层，
2-掩膜结构，2a-上表面，
3-第一介质层，
4-导电层，4a-第一表面，4b-第二表面，
5-过孔，51-第一孔段，51a-侧壁，51b-第一底面，52-第二孔段，52a-第二底面，
6-绝缘层，
7-第一孔洞，
8-第二孔洞。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A,B可以是单数或者复数。并且，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序 进行限定，并且“第一”、“第二”等字样也并不限定一定不同。同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
本申请实施例提供一种电子设备，该电子设备设置有集成芯片。具体的，该电子设备可以是手机、生物应用设备等，本申请实施例对上述电子设备的具体形式不做特殊限制。
图1a为本申请实施例提供的一种电子设备的结构示意图。如图1a所示，该电子设备包括：芯片100和电路板200；芯片100设置在电路板200上。芯片100与电路板200的连接方式有多种，比如焊接。具体的，芯片100可以作为存储器被设置在电子设备上，芯片100还可以作为控制器被设置在电子设备上。
可以理解的是，图1a仅示意性的示出了电子设备10包括的一些部件，这些部件的实际形状、实际大小、实际位置和实际构造不受图1a的限制。
图1b为图1a提供的一种电子设备中芯片的结构示意图。如图1b所示，在一些实施例中，芯片100包括衬底110、叠层结构1、掩膜结构2、导电层4、过孔5、第一器件120、锡球130、第二器件140以及金属层150。叠层结构1、掩膜结构2依次设置在衬底110上，过孔5朝垂直于衬底110的方向贯通掩膜结构2、叠层结构1和衬底110，过孔5内形成有导电层4。设置在掩膜结构2的上表面的第一器件120通过金属层150与导电层4电连接。设置在衬底110的的下表面的第二器件140通过锡球130与导电层4电连接。这样，实现了芯片100内部的第一器件120和第二器件140的垂直电互联。其中，垂直电互联中的“垂直”是指垂直于衬底的方向。
本申请实施例提供的芯片还能够实现多个芯片之间的垂直电互联。如图1b所示，第一芯片100a的导电层4和第二芯片100b的导电层4通过金属层150连接，以实现第一芯片100a和第二芯片100b之间的垂直电互联。
通过实现芯片内部器件的垂直电互联，以及多个芯片间的垂直电互联，能够实现芯片的三维堆叠，使得芯片具有更高的密度和空间利用率，从而实现芯片更高水平的集成度，性能更好，进而满足电子设备体积更小、性能更强的需求。
为了使芯片的电性更好，导电层作为实现器件、芯片之间垂直电互联的关键结构，应该具有连续的结构。具体的，若导电层局部有缝隙或有孔洞会影响导电层的电阻，进而影响芯片的电性。本申请实施例提供一种芯片，能够保证导电层材料分布均匀、结构连续、没有断裂，从而保证芯片的电性。下面结合附图进行详细说明。
图2示出了本申请实施例提供的一种芯片的结构示意图。如图2所示，该芯片100包括衬底110、叠层结构1、掩膜结构2、第一介质层3、导电层4以及绝缘层6。
衬底110可以选择的材料有多种，包括单晶硅(Si)、单晶锗(Ge)、砷化镓、磷化铟、III-V族化合物半导体材料、II-VI族化合物半导体材料或在本领域中已知的其它半导体材料中的至少一种，或者，衬底110也可以由诸如玻璃、塑料或蓝宝石晶圆之类的非导电材料制成。
叠层结构1堆叠在衬底110上。叠层结构1可以是多层结构。在一种实现方式中，叠层结构1包括：依次堆叠在衬底110上的第一氧化物层11、氮化硅层12、第二氧化物层13、介电材料层14以及第三氧化物层15。其中，第一氧化物层11、第二氧化物层13以及第三氧化物层15可以是同种材质，也可以是不同材质。介电材料层14的材质为低介电常数材料。氮化硅层12具有掩蔽杂质沾污的作用。示例性的，第一氧化物层11、第二氧化物层13以及第三氧化物层15的材质均为二氧化硅(SiO2)，介电材料层14的材质为氮化硅(Si3N4)。
其中，介电材料层14的材质具有低介电常数(low-k)的特性，也称作low-k层。low-k层为多孔材质，容易被刻蚀。
掩膜结构2堆叠在叠层结构1上，用于实现多重光刻工艺。具体的，可以通过刻蚀将光刻胶的图像转移到掩膜结构2上，再通过刻蚀将掩膜结构2上的图像刻蚀转移到叠层结构1和衬底110上。
掩膜结构2可以是一种通过化学气相沉积(Chemical Vapor Deposition,CVD)生成的无机薄膜材料。掩膜结构2可以是多层结构，采用的材料通常有氮化钛(TiN)、氮化硅(Si3N4)、二氧 化硅(SiO2)等。在一种实现方式中，掩膜结构可以包括氮化钛层、氮化硅层、氧化铝层或二氧化硅层中的至少一层。
一并结合图2和图3，在一些实施例中，掩膜结构2背离衬底110的上表面2a上开设有朝垂直于衬底的方向A延伸的过孔5，过孔5贯通掩膜结构2、叠层结构1和衬底110。其中，过孔5可以是圆孔，还可以是方孔，也可以是如图2所示的沿垂直于衬底的方向A截面逐渐变小的锥型孔。对于过孔5的形状，本申请不作具体限定。
过孔5包括贯通掩膜结构2、叠层结构1的第一孔段51，以及贯通衬底的第二孔段52。形成第一孔段51的过程，即为将光刻胶的图像转移到掩膜结构2、叠层结构1上的过程。形成第二孔段52的过程，即为将掩膜结构2上的图像刻蚀转移到衬底110上的过程。
由于要先将光刻胶的图像转移到掩膜结构2上，所以从掩膜结构2背离衬底110的一侧开始刻蚀，也就是说，要先形成第一孔段51，再形成第二孔段52。形成第一孔段51时，衬底110不会受到影响。但是，在形成第二孔段52时，是在第一孔段51内沿垂直于衬底110的方向A刻蚀衬底110，因此，第一孔段51的侧壁也会受到刻蚀的影响，即掩膜结构2和叠层结构1也会受到影响。
为了在形成第二孔段52的过程中保护叠层结构1，第一孔段51的侧壁51a上覆盖有第一介质层3。这样，在形成第二孔段52的过程中，发生横向刻蚀时，先被刻蚀的是第一介质层3。而掩膜结构2和叠层结构1的位于第一孔段51的侧壁51a上的部分不被刻蚀，也就不会产生损伤。
第一介质层3可以选择的材料有多种，比如可以是二氧化硅材料，还可以是形成侧壁保护层的其他材料，包括但不限于硅碳氮(SiCN)、硅氧氮(SION)、氧化硅(SiO2)、氮化硅(SIN)、硅氧碳氮(SIOCN)、碳化硅(SIC)或硅氧碳(SIOC)中的至少一种。
如图4所示，在形成第二孔段52的过程中，若第一孔段51的侧壁51a上没有第一介质层3，第一孔段51的侧壁受到刻蚀的影响，会发生横向刻蚀(沿平行于衬底110的方向刻蚀掩膜结构2)。由于叠层结构1为多层结构，且每相邻的两层结构的材质不同。因而，同一刻蚀条件下，每相邻的两层结构的刻蚀速率不同。这样，会导致刻蚀速率较快的膜层相对于刻蚀速度慢的膜层内凹，形成侧掏。示例性的，相对于第一氧化物层11、第二氧化物层13以及第三氧化物层15，介电材料层14、氮化硅层12的刻蚀速率更快，相同时间，被刻蚀掉的材料更多。这样，由于氮化硅层12被刻蚀掉的材料比第一氧化物层11、第二氧化物层13被刻蚀掉的材料多，在第一孔段51的侧壁上会形成第一孔洞7。由于介电材料层14被刻蚀掉的材料比第二氧化物层13、第三氧化物层15被刻蚀掉的材料多，在第一孔段51的侧壁上会形成第二孔洞8。
所以，通过在第一孔段51的侧壁51a上覆盖第一介质层3，能够保护掩膜结构2。使得在形成过孔5的过程中，叠层结构1不会发生侧掏。
在一种实现方式中，可以采用气相沉积的方式形成第一介质层3。这样得到的第一介质层3完全覆盖第一孔段51的侧壁51a。即使第一孔段51的侧壁51a上有缺陷(比如凹陷)，第一介质层3也能够将缺陷完全覆盖，使得第一介质层3为没有孔洞的连续结构。
为了增强第一介质层3对掩膜结构2的保护的可靠性，在一些实施例中，衬底110相对于第一介质层3具有高刻蚀选择比。这样，在形成第二孔段52时，第一介质层3越不会被刻蚀，从而保证叠层结构1不会发生侧掏。其中，刻蚀选择比表示为：被刻蚀材料的刻蚀速率与另一种材料的刻蚀速率的比。高选择比意味着只刻除想要刻去的那一层材料。
由于衬底110不能和导电层4接触，因而，在形成导电层4之前，要在第一介质层3上、第二孔段52的侧壁上覆盖绝缘层6。
由于绝缘层6和第一孔段51的侧壁51a之间设置有第一介质层3，因而绝缘层6的结构不会受到第一孔段51的侧壁51a上的损伤缺陷的影响，绝缘层6上不会有孔洞或其他导致绝缘层6不连续的缺陷。
请继续参见图2和图3。
导电层4，绝缘层6围成的填充空间6a内形成有导电层4。在一种实现方式中，通过电镀形成导电层4。由于绝缘层6上没有孔洞或其他导致绝缘层6不连续的缺陷，进而导电层4能够实现结构连续，从而保证芯片100的电性。可以理解的是，导电层4可以是形成在填充空间6a内的 柱状结构，也可以是形成在填充空间6a内的一层薄膜结构。
为了形成的导电层结构均匀连续，如图5所示，在一些实施例中，芯片还包括扩散阻挡层62、衬垫层63以及籽晶层64；绝缘层6上覆盖有扩散阻挡层62；扩散阻挡层62上覆盖有衬垫层63；衬垫层63上覆盖设置有籽晶层64，导电层4形成在籽晶层64围成的区域64a内。
为了避免导电层4在第一介质层3与第二孔段52相接的位置附近尺寸突变，导致导电层4的电阻受到影响，进而影响芯片100的电性。在一些实施例中，第一介质层3与第二孔段52相接的位置上，第一介质层3的边缘3b与第二孔段52的边缘52a1重合。这样，不但能够保证导电层4在第一介质层3与第二孔段52相接的位置附近尺寸过渡自然，也能够保证第一孔段51的侧壁面51a上始终覆盖有第一介质层3，起到保护叠层结构1的作用。
为了实现导电层4与和器件(或芯片)电连接，如图6所示，在一些实施例中，导电层4具有平行于衬底的第一表面4a和第二表面4b，第一表面4a为背离衬底110的表面，第二表面4b为背离掩膜结构2的表面；第一表面4a与掩膜结构2的背离衬底110的上表面2a在同一平面内；第二表面4b与衬底110的背离掩膜结构2的下表面110a在同一平面内。导电层4能够与设置在衬底110远离掩膜结构2的一侧的器件或芯片连接，也能与设置在掩膜结构2远离衬底110的一侧的器件或芯片连接，从而实现导电层4与多个器件或芯片的电连接。
在另一些实施例中，导电层4的第二表面4b可以延伸至衬底110的背离掩膜结构2的下表面110a之外，即导电层4露出衬底110一段距离。在一些情景中，导电层不会和器件(或芯片)直接电连接，而是通过金属层将导电层和器件(或芯片)电连接，或是通过焊球(如图1a所示)将导电层和器件(或芯片)电连接。
如图8所示，在一些实施例中，掩膜结构2背离衬底110的上表面2a上和/或衬底110背离掩膜结构2的下表面110a上设置有金属层150；金属层150和导电层4电连接。在一种实现方式中，如图8所示，金属层150设置在掩膜结构2背离衬底110的上表面2a上，以及衬底110背离掩膜结构2的下表面110a上，且金属层150位于导电层4的第一表面4a和第二表面4b上。
为了进一步提高第一介质层3对衬底110的保护的可靠性。如图7所示，在一些实施例中，第一介质层3为多层结构；多层结构沿过孔5的径向B依次层叠在第一孔段51的侧壁51a上。如图9所示，在一种实现方式中，第一介质层3包括第一膜层31和第二膜层32，第一膜层31和第二膜层32沿过孔5的径向B依次层叠在第一孔段51的侧壁51a(如图3所示)上。
以上，通过在第一孔段和绝缘层之间形成第一介质层。一方面，在发生横向刻蚀时，先被刻蚀的是第一介质层，从而保护叠层结构位于第一孔段的部分不被刻蚀，避免第一孔段的侧壁上形成侧掏。另一方面，绝缘层的结构不会受到第一孔段的内壁面上的损伤缺陷的影响，绝缘层上不会有孔洞或其他导致绝缘层不连续的缺陷，进而导电层能够实现结构连续，从而保证芯片的电性。本申请实施例还提供了一种芯片的制备方法，下面结合图9所示的工艺流程图，和图10a至图10f的工艺结构图，具体介绍芯片的一种可实现的制备方法。如图9所示，工艺流程图包括步骤S1-S7。
S1，如图10a所示，在衬底110上形成叠层结构1。
如图10a所示，在一些实施例中，形成叠层结构1时，将第一氧化物层11、氮化硅层12、第二氧化物层13、介电材料层14以及第三氧化物层15依次堆叠在衬底110上。
S2，如图10a所示，在叠层结构1形成掩膜结构2。
S3，如图10b所示，在掩膜结构2背离衬底110的上表面2a上开设朝垂直于衬底110的方向A贯通掩膜结构2、叠层结构1的第一孔段51。
S4，如图10c所示，在第一孔段51的侧壁51a上形成第一介质层3，使得第一介质层3覆盖在第一孔段51的侧壁上51a。
S5，如图10d所示，在侧壁51a上形成有第一介质层3的第一孔段51的第一底面51b上开设朝垂直于衬底110的方向A贯通衬底110的第二孔段52，以在掩膜结构2上开设朝垂直于衬底110的方向A延伸的包含第一孔段51和第二孔段52在内的过孔5。
在一种实现方式中，形成第二孔段52时，使得第一介质层3与第二孔段52相接的位置上，第一介质层3的边缘与第二孔段52的边缘重合。
在一种实现方式中，衬底110可以为硅片，在硅刻蚀腔中刻蚀，以在衬底110内形成第二孔 段52。
S6，如图10e所示，在第一介质层3、第二孔段52的侧壁上形成绝缘层6，使得绝缘层6覆盖第一介质层3和第二孔段52。
在一种实现方式中，采用热氧化方式生长绝缘层6，绝缘层6的材质可以是二氧化硅。
S7，如图10f所示，在绝缘层6围成的填充空间6a内形成导电层4。
本申请实施例通过执行步骤S3至S5，完成了将光刻胶的图像转移到掩膜结构2、叠层结构1上，再通过刻蚀将掩膜结构2上的图像刻蚀转移到衬底110上的工序。本申请实施例通过在执行S3之后，在执行S5之前，执行步骤S4，在形成第二孔段52时，第一介质层3可以保护掩膜结构2，掩膜结构2不会受到横向刻蚀，避免第一孔段51的侧壁51a上形成侧掏。进而，在第一介质层3和第二孔段52上形成绝缘层6时，由于第一孔段51的侧壁51a上没有形成侧掏，绝缘层6上不会有孔洞或其他导致绝缘层6不连续的缺陷。在绝缘层6围成的填充空间6a内形成导电层4时，导电层4能够实现结构连续，从而保证芯片的电性。本申请实施例可以在不改变步骤S3之前和步骤S5之后的工艺步骤，从根本上解决叠层结构1侧掏的问题。
下面给出在第一孔段的侧壁上形成第一介质层的一种实施例。
在一些实施例中，在执行步骤S4时，包括步骤S401-S402。下面结合图11所示的工艺流程图，和图12a至图12b的工艺结构图，具体介绍芯片的一种可实现的制备方法。如图11所示，工艺流程图包括步骤S401-S402。
S401，如图12a所示，在第一孔段51的内壁面上形成第一介质层3，使得第一介质层3覆盖第一孔段51的内壁面。
S402，如图12b所示，将位于第一孔段51的第一底面51b上的第一介质层3去除。
在一种实现方式中，可以在电介质刻蚀腔内，将位于第一孔段51的第一底面51b上的第一介质层3去除。
在一种实现方式中，可以在TSV刻蚀腔内，将位于第一孔段51的第一底面51b上的第一介质层3去除。这样，执行步骤S5和步骤S402时，可以使用同一个刻蚀腔，避免更换刻蚀腔，能够最大限度的保证加工的精度。
如图12b所示，第一介质层3包括覆盖在第一孔段51的侧壁上的第一部分31、以及位于第一孔段51的第一底面51b上的第二部分32，将第二部分32去除。
相对于直接在第一孔段51的侧壁51a上形成第一介质层3，采用步骤S401-S402的制备方法形成第一介质层3工艺难度低，易于实现，有利于芯片的批量生产。
在执行步骤S5时，在形成第二孔段52时，可以直接贯通衬底110。但是，在衬底110的厚度较大的情况下，或者不适于采用贯通衬底110的情况，在形成第二孔段52时，可以先不贯通衬底110。而是在形成第二孔段52之后，去除衬底110的多于材料，得到第二孔段52贯通衬底110的结构。
在一些实施例中，在执行步骤S5时，包括步骤S501-S502。下面结合图13所示的工艺流程图，和图14a至图14b的工艺结构图，具体介绍芯片的一种可实现的制备方法。如图13所示，工艺流程图包括步骤S501-S502。
S501，如图14a所示，在侧壁51a上形成有第一介质层3的第一孔段51的第一底面51b上开设朝垂直于衬底110的方向A延伸的第二孔段52，此时，第二孔段52未贯穿衬底110。
S502，如图14b所示，去除衬底110的自第二孔段52的第二底面52a起至衬底110的远离掩膜结构2的下表面110a之间的部分11，此时，如图10d所示，第二孔段52贯穿衬底110。
在另一些实施例中，如图15所示，在执行步骤S1-S4，以及步骤S501之后，执行步骤S502之前，先执行步骤S6和步骤S7。下面结合图15所示的工艺流程图，和图16a至图16c的工艺结构图，具体介绍芯片的一种可实现的制备方法。
S1，如图10a所示，在衬底110上形成叠层结构1。
S2，如图10a所示，在叠层结构1形成掩膜结构2。
S3，如图10b所示，在掩膜结构2背离衬底110的上表面2a上开设朝垂直于衬底110的方向A贯通掩膜结构2、叠层结构1的第一孔段51。
S4，如图10c所示，在第一孔段51的侧壁51a上形成第一介质层3，使得第一介质层3覆盖在第一孔段51的侧壁上51a。
S501，如图14a所示，在侧壁51a上形成有第一介质层3的第一孔段51的第一底面51b上开设朝垂直于衬底110的方向A延伸的第二孔段52，此时，第二孔段52未贯穿衬底110。
S6，如图16a所示，在第一介质层3、第二孔段52的侧壁上形成绝缘层6，使得绝缘层6覆盖第一介质层3和第二孔段52。
S7，如图16b所示，在绝缘层6围成的填充空间6a内形成导电层4。
S502，如图16c所示，去除衬底110的自第二孔段52的第二底面52a起至衬底110的远离掩膜结构2的表面之间的部分11，此时，如图10d所示，第二孔段52贯穿衬底110。同时，使得导电层4暴露在衬底110的表面上。
下面给出一种形成绝缘层的具体实现方式。
在执行步骤S6之后，在执行步骤7之前，制备方法还包括步骤S61-S63，下面结合图17所示的工艺流程图，和图18a至图18c的工艺结构图，具体介绍芯片的一种可实现的制备方法。
S61，如图18a所示，在绝缘层6上形成扩散阻挡层62。
在一种实现方式中，采用等离子体增强化学的气相沉积法(plasma enhanced chemical vapor deposition，PECVD)、亚常压气相沉积法(subatmospheric chemical vapor deposition，SACVD)、常压化学气相沉积法(atmospheric pressure chemical vapor deposition，APCVD)或化学液相沉积法。
S62，如图18b所示，在扩散阻挡层62上形成衬垫层63。
S63，如图18c所示，在衬垫层63上形成籽晶层64。
执行步骤S61-S63之后，执行步骤S7时，如图18c所示，在籽晶层64围成的区域64a形成导电层4。
为了使得导电层能够与设置在衬底远离掩膜结构的一侧的器件或芯片电连接，导电层能够与设置在掩膜结构远离衬底的一侧的器件或芯片电连接。本申请实施例通过去除材料的方式，使得导电层露出。
进一步，为了保证导电层和器件(或芯片)电连接的的可靠性，如图19所示，在一些实施例中，在执行步骤S7之后，制备方法还包括：在形成导电层4时，使得导电层4的第一表面4a与掩膜结构2的背离衬底110的上表面2a在同一平面内；导电层4的第二表面4b与衬底110的背离掩膜结构2的下表面110a在同一平面内；其中，所述第一表面4a为导电层4的平行于衬底110且背离衬底110的表面，第二表面4b为导电层4的平行于衬底110且背离掩膜结构2的表面。在一种实现方式中，可以采用打磨的方式实现导电层4的第一表面4a与掩膜结构2的背离衬底110的上表面2a在同一平面内，以及实现导电层4的第二表面4b与衬底110的背离掩膜结构2的下表面110a在同一平面内。
在一些情景中，导电层不会和器件(或芯片)直接电连接，而是通过金属层将导电层和器件(或芯片)电连接，或是通过焊球将导电层和器件(或芯片)电连接。如图20所示，在一些实施例中，在掩膜结构2背离衬底110的上表面2a上和/或衬底110背离掩膜结构2的下表面110a上设置金属层150；将金属层150和导电层4电连接。
以上，在刻蚀和沉积的过程中，芯片上会有残留的光刻胶、以及刻蚀液等副产物，为了将这些副产物去除，在一些实施例中，制备方法还包括：灰化步骤，将芯片置于灰化机台中，以去除芯片在制备过程中的副产物；清洗步骤，将芯片置于清洗机中，以去除芯片在制备过程中的副产物。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种芯片，其特征在于，包括：
    衬底；
    叠层结构，堆叠在所述衬底上；
    掩膜结构，堆叠在所述叠层结构上；所述掩膜结构背离所述衬底的表面上开设有朝垂直于所述衬底的方向延伸的过孔，所述过孔贯通所述掩膜结构、所述叠层结构和所述衬底；所述过孔包括贯通所述掩膜结构和所述叠层结构的第一孔段，以及贯通所述衬底的第二孔段；
    第一介质层，覆盖所述第一孔段的侧壁；
    绝缘层，覆盖所述第二孔段的侧壁和所述第一介质层，并在所述过孔内围出填充空间；
    导电层，形成在所述填充空间内。
  2. 根据权利要求1所述的芯片，其特征在于，所述第一介质层与所述第二孔段相接的位置上，所述第一介质层的边缘与所述第二孔段的边缘重合。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述导电层具有平行于所述衬底的第一表面和第二表面，所述第一表面为背离所述衬底的表面，所述第二表面为背离所述掩膜结构的表面；
    所述第一表面与所述掩膜结构的背离所述衬底的表面在同一平面内；
    所述第二表面与所述衬底的背离所述掩膜结构的表面在同一平面内。
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述第一介质层为多层结构；
    所述多层结构沿所述过孔的径向依次层叠在所述第一孔段的侧壁上。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，所述第一介质层的材质包括硅碳氮、硅氧氮、氧化硅、氮化硅、硅氧碳氮、碳化硅或硅氧碳中的至少一种。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述芯片还包括：扩散阻挡层、衬垫层以及籽晶层；
    所述绝缘层上覆盖有所述扩散阻挡层；
    所述扩散阻挡层上覆盖有所述衬垫层；
    所述衬垫层上覆盖设置有所述籽晶层；所述籽晶层位于所述绝缘层和所述导电层之间。
  7. 根据权利要求1-6任一项所述的芯片，其特征在于，所述叠层结构为多层结构；
    所述多层结构依次层叠在所述衬底上。
  8. 根据权利要求7所述的芯片，其特征在于，所述叠层结构包括：依次堆叠在所述衬底上的第一氧化物层、氮化硅层、第二氧化物层、介电材料层以及第三氧化物层。
  9. 根据权利要求1-8任一项所述的芯片，其特征在于，所述芯片还包括：
    金属层，设置在所述掩膜结构背离所述衬底的表面上和/或所述衬底背离所述掩膜结构的表面上；
    所述导电层与所述金属层电连接。
  10. 根据权利要求1-9任一项所述的芯片，其特征在于，所述衬底的材质包括单晶硅、单晶锗、砷化镓、磷化铟、III-V族化合物半导体材料、II-VI族化合物半导体材料、玻璃、塑料或蓝宝石晶圆中的至少一种。
  11. 根据权利要求1-10任一项所述的芯片，其特征在于，所述掩膜结构包括氮化钛层、氮化硅层、氧化铝层或二氧化硅层。
  12. 一种芯片的制备方法，其特征在于，包括：
    在衬底上形成叠层结构；
    在所述叠层结构上形成掩膜结构；在所述掩膜结构背离所述衬底的表面上开设朝垂直于所述衬底的方向贯通所述掩膜结构和所述叠层结构的第一孔段；
    在所述第一孔段的侧壁上形成第一介质层，使得所述第一介质层覆盖在所述第一孔段的侧壁上；
    在侧壁上形成有所述第一介质层的所述第一孔段的底面上开设朝垂直于所述衬底的方向贯通所述衬底的第二孔段，以在所述掩膜结构上开设朝垂直于所述衬底的方向延伸的包含所述第一孔段和所述第二孔段在内的过孔；
    在所述第一介质层、所述第二孔段的侧壁上形成绝缘层，使得所述绝缘层覆盖所述第一介质层和所述第二孔段，且在所述过孔内围出填充空间；
    在填充空间内形成导电层。
  13. 根据权利要求12所述的芯片的制备方法，其特征在于，形成所述第一介质层，包括：
    在所述第一孔段的内壁面上形成所述第一介质层，使得所述第一介质层覆盖所述第一孔段的内壁面；
    将所述第一孔段的底面上的所述第一介质层去除。
  14. 根据权利要求12或13所述的芯片的制备方法，其特征在于，形成所述第二孔段时，使得所述第一介质层与所述第二孔段相接的位置上，所述第一介质层的边缘与所述第二孔段的边缘重合。
  15. 根据权利要求12-14任一项所述的芯片的制备方法，其特征在于，在形成所述绝缘层之后，在形成所述导电层之前，所述制备方法还包括：
    在所述绝缘层上形成扩散阻挡层；
    在所述扩散阻挡层上形成衬垫层；
    在所述衬垫层上形成籽晶层；
    形成所述导电层，包括：在所述籽晶层围成的区域内形成所述导电层。
  16. 根据权利要求12-15任一项所述的芯片的制备方法，其特征在于，形成所述叠层结构，包括：
    将多层结构依次堆叠在所述衬底上。
  17. 根据权利要求16所述的芯片的制备方法，其特征在于，形成所述叠层结构，包括：
    将第一氧化物层、氮化硅层、第二氧化物层、介电材料层以及第三氧化物层依次堆叠在所述衬底上。
  18. 根据权利要求12-17任一项所述的芯片的制备方法，其特征在于，在形成所述导电层时，包括：
    在所述绝缘层的内壁面上电镀金属，以形成所述导电层。
  19. 根据权利要求13所述的芯片的制备方法，其特征在于，在形成所述第一孔段时，以及，将所述第一孔段的底面上的所述第一介质层去除时，使用同一个刻蚀腔。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1-11任一项所述的芯片，所述芯片设置在所述电路板上。
PCT/CN2023/103508 2022-09-22 2023-06-28 一种芯片及其制备方法、电子设备 WO2024060757A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364544A (zh) * 2019-07-24 2019-10-22 武汉新芯集成电路制造有限公司 一种晶圆结构及其制造方法、芯片结构
CN110931354A (zh) * 2018-09-19 2020-03-27 中芯国际集成电路制造(上海)有限公司 半导体结构以及半导体结构的制造方法
CN113066761A (zh) * 2021-03-18 2021-07-02 长鑫存储技术有限公司 一种半导体器件的制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110931354A (zh) * 2018-09-19 2020-03-27 中芯国际集成电路制造(上海)有限公司 半导体结构以及半导体结构的制造方法
CN110364544A (zh) * 2019-07-24 2019-10-22 武汉新芯集成电路制造有限公司 一种晶圆结构及其制造方法、芯片结构
CN113066761A (zh) * 2021-03-18 2021-07-02 长鑫存储技术有限公司 一种半导体器件的制作方法

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