WO2024058140A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2024058140A1
WO2024058140A1 PCT/JP2023/033089 JP2023033089W WO2024058140A1 WO 2024058140 A1 WO2024058140 A1 WO 2024058140A1 JP 2023033089 W JP2023033089 W JP 2023033089W WO 2024058140 A1 WO2024058140 A1 WO 2024058140A1
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Prior art keywords
insulating film
layer
semiconductor device
element isolation
gate electrode
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PCT/JP2023/033089
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English (en)
Japanese (ja)
Inventor
奨悟 池浦
振一郎 柳
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株式会社デンソー
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Publication of WO2024058140A1 publication Critical patent/WO2024058140A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to a semiconductor device having a gate electrode.
  • STI isolation section abbreviation for Shallow Trench Isolation
  • a gate electrode is disposed on the main surface of the semiconductor substrate using the element isolation insulating film forming the STI isolation section as a gate insulating film.
  • An object of the present disclosure is to provide a semiconductor device that can apply a high voltage to a gate electrode.
  • a semiconductor device includes a semiconductor substrate having a main surface, a first conductivity type drift layer formed in a surface layer portion on the main surface side, and a first conductivity type drift layer formed in a surface layer portion of the drift layer.
  • a device isolation insulating film for isolation is arranged, a laminated insulating film is arranged on the device isolation insulating film, and the gate insulating film includes the device isolation insulating film and the laminated insulating film.
  • the gate insulating film is configured to include an element isolation insulating film and a laminated insulating film. Therefore, the gate insulating film can be easily made thicker, and a sufficiently high voltage can be easily applied to the gate electrode.
  • FIG. 1 is a cross-sectional view of a semiconductor device in a first embodiment.
  • FIG. 2 is a plan view showing the positional relationship among a trench isolation section, a drain region, a source region, a gate insulating film, and a gate electrode shown in FIG. 1.
  • FIG. 3 is a cross-sectional view of a semiconductor device in a second embodiment.
  • FIG. 7 is a cross-sectional view of a semiconductor device in a third embodiment.
  • FIG. 7 is a cross-sectional view of a semiconductor device in a fourth embodiment.
  • FIG. 7 is a cross-sectional view of a semiconductor device in a fifth embodiment.
  • FIG. 7 is a plan view showing the positional relationship among the trench isolation section, drain region, source region, gate insulating film, and gate electrode shown in FIG. 6.
  • FIG. 7 is a cross-sectional view of a semiconductor device in a sixth embodiment.
  • FIG. 7 is a cross-sectional view of a semiconductor device in a seventh embodiment.
  • FIG. 7 is a cross-sectional view of a semiconductor device in an eighth embodiment.
  • FIG. 1 is a cross-sectional view taken along line II in FIG. 2.
  • FIG. 2 shows portions of a drain region 32 and a source region 35, which will be described later, that are exposed from the main surface 10a of the SOI substrate 10.
  • the semiconductor device of this embodiment is constructed using an SOI (Silicon On Insulator) substrate 10 in which an active layer 13 is stacked on a support substrate 11 with a buried insulating film 12 interposed therebetween.
  • the SOI substrate 10 corresponds to a semiconductor substrate.
  • the support substrate 11 is made of a silicon substrate or the like
  • the buried insulating film 12 is made of an oxide film or the like.
  • the active layer 13 is constructed using an n - type silicon substrate or the like with a predetermined impurity concentration.
  • the surface of the SOI substrate 10 that includes the surface of the active layer 13 will also be referred to as the main surface 10a of the SOI substrate 10.
  • the active layer 13 is divided into an element region 14 and a field ground region 15 by a trench isolation portion 20, thereby providing element isolation.
  • the active layer 13 is isolated by a trench isolation section 20 such that the element region 14 is surrounded by the field ground region 15.
  • the semiconductor device of this embodiment also has element regions 14 in a cross section different from that in FIG. 1, and a semiconductor element such as an LDMOS having a predetermined breakdown voltage is formed in each element region 14. Further, the semiconductor elements in each element region 14 may have the same breakdown voltage, or may have different breakdown voltages.
  • the trench isolation section 20 is configured by placing a buried insulating film 22 in a trench 21 formed to reach the buried insulating film 12 from the main surface 10a of the SOI substrate 10 so as to bury the trench 21. ing. Note that the buried insulating film 22 is placed in the trench 21 by filling in an insulating material by thermal oxidation or deposition.
  • an n ⁇ type drift layer 31 having a higher impurity concentration than the active layer 13 is formed in the center of the surface layer of the active layer 13.
  • An n + -type drain region 32 is formed in the surface layer of the drift layer 31 so as to be exposed from the main surface 10 a of the SOI substrate 10 .
  • an n-type buffer layer 33 is arranged between the drift layer 31 and the drain region 32 as an electric field relaxation layer for relaxing the drain voltage.
  • the buffer layer 33 has a higher impurity concentration than the drift layer 31 and a lower impurity concentration than the drain region 32.
  • a p-type body layer 34 is formed in the surface layer of the active layer 13 at a position away from the drift layer 31 and in contact with the trench isolation section 20 .
  • the body layer 34 is formed in a frame shape so as to surround the drift layer 31 in the normal direction to the main surface 10a of the SOI substrate 10 (hereinafter also simply referred to as the normal direction).
  • the normal direction to the main surface 10a of the SOI substrate 10 is a direction along the stacking direction of the support substrate 11 and the active layer 13.
  • "in the normal direction” can also mean when viewed from the normal direction.
  • the body layer 34 is formed to approximately the same depth as the drift layer 31.
  • n + -type source region 35 having a higher impurity concentration than the body layer 34 is formed in the surface layer of the body layer 34 so as to be exposed from the main surface 10 a of the SOI substrate 10 .
  • the source region 35 is formed on the trench isolation portion 20 side of the body layer 34 .
  • the source region 35 is formed to surround the drift layer 31. That is, the source region 35 is formed to surround the drain region 32. That is, in this embodiment, as will be described later, in the off state where no current flows between the source and drain, the drain region 32 becomes a high potential region where the potential is higher than that of the source region 35.
  • the semiconductor device has a structure in which the drain region 32, which is a high potential region, is surrounded by the source region 35, which is a low potential region. Note that, since the drain breakdown voltage is determined by the spacing between the body layer 34 and the drain region 32, it is preferable that the spacing between the body layer 34 and the drain region 32 be changed as appropriate depending on the required breakdown voltage.
  • an STI isolation section 40 is formed in the surface layer portion of the active layer 13.
  • the STI isolation section 40 is constructed by forming a trench 41 of a predetermined depth in the surface layer of the active layer 13, and burying an element isolation insulating film 42 in the trench 41.
  • the element isolation insulating film 42 is formed, for example, by filling the trench 41 after it is formed and then planarizing it by a CMP (Chemical Mechanical Polishing) method or the like.
  • the element isolation insulating film 42 is composed of, for example, an oxide film formed by a CVD (abbreviation for chemical vapor deposition) method. Note that when a plurality of element regions 14 are provided, the STI isolation portions 40 in each element region 14 have the same depth. In other words, the element isolation insulating films 42 in each element region 14 have the same thickness.
  • a first opening 40a and a second opening 40b are formed in the STI isolation section 40.
  • the first opening 40a is formed to expose the central portion of the main surface 10a of the SOI substrate 10.
  • the first opening 40a is formed to expose the drain region 32 from the main surface 10a of the SOI substrate 10.
  • the second opening 40b is formed to expose the outer edge of the main surface 10a of the SOI substrate 10.
  • the second opening 40b is formed to expose the source region 35. Therefore, the element isolation insulating film 42 (that is, the STI isolation part 40) is formed between the drain region 32 and the source region 35, and is a part that performs the function of isolating the drain region 32 and the source region 35. It can be said that there is.
  • the first opening 40a is formed such that the drift layer 31 is located below the STI isolation section 40.
  • the drift layer 31 is formed to have a portion in contact with the element isolation insulating film 42.
  • the second opening 40b is formed such that the body layer 34 is located below the STI isolation section 40.
  • the second opening 40b may be formed in a frame shape along the source region 35, or may be formed so as to expose one or more locations of the source region 35. In this embodiment, the second opening 40b is formed to expose a plurality of locations of the source region 35.
  • the drift layer 31, drain region 32, body layer 34, and source region 35 pass through the center of the element region 14 surrounded by the trench isolation section 20 and extend along the normal direction of the main surface 10a. It is formed approximately rotationally symmetrically with respect to the extending axis.
  • a gate electrode 51 is formed on the main surface 10a of the SOI substrate 10. Specifically, an additional insulating film 52 is disposed as a laminated insulating film on the element isolation insulating film 42 of this embodiment, so as to include a portion in contact with the body layer 34 and a portion facing the body layer 34.
  • the gate electrode 51 is disposed on the gate insulating film 53, with the element isolation insulating film 42 and the additional insulating film 52 serving as the gate insulating film 53.
  • the element isolation insulating film 42 and the additional insulating film 52 constituting the gate insulating film 53 are such that the length of the element isolation insulating film 42 is equal to or greater than the length of the additional insulating film 52 in the source-drain direction (i.e., the surface direction of the main surface 10a). Furthermore, the element isolation insulating film 42 and the additional insulating film 52 constituting the gate insulating film 53 are disposed such that the additional insulating film 52 is located within the element isolation insulating film 42 in the normal direction.
  • the element isolation insulating film 42 and the additional insulating film 52 constituting the gate insulating film 53 are disposed such that the additional insulating film 52 does not protrude from the element isolation insulating film 42 in the normal direction.
  • the gate electrode 51 is arranged so as to be located within the gate insulating film 53 in the normal direction.
  • the additional insulating film 52 is formed by forming an insulating film made of an oxide film or the like on the main surface 10a of the SOI substrate 10 by a CVD method or the like, and then patterning the film as appropriate. Therefore, the thickness and location of the additional insulating film 52 can be easily changed as appropriate. Further, the gate electrode 51 is made of, for example, doped polysilicon.
  • a protective insulating film 60 is formed on the main surface 10a of the SOI substrate 10 so as to cover the gate electrode 51 and the like.
  • the protective insulating film 60 is made of a nitride film or the like. This protective insulating film 60 is provided to suppress moisture and active ions contained in interlayer insulating films 81 to 83 (described later) from entering the SOI substrate 10.
  • a wiring layer 70 is formed on the main surface 10a of the SOI substrate 10 so as to cover the protective insulating film 60. That is, the protective insulating film 60 is formed between the SOI substrate 10 and the wiring layer 70.
  • the wiring layer 70 has a structure in which first to third interlayer insulating films 81 to 83 and first to third wiring parts 91 to 93 are alternately arranged.
  • the first interlayer insulating film 81 is formed on the main surface 10a of the SOI substrate 10 so as to cover the gate electrode 51 and the protective insulating film 60, and the first wiring part 91 is formed on the first interlayer insulating film 81.
  • the second interlayer insulating film 82 is formed on the first interlayer insulating film 81 so as to cover the first wiring part 91, and the second wiring part 92 is formed on the second interlayer insulating film 82.
  • the third interlayer insulating film 83 is formed on the second interlayer insulating film 82 so as to cover the second wiring part 92, and the third wiring part 93 is formed on the third interlayer insulating film 83.
  • the first to third interlayer insulating films 81 to 83 are composed of a TEOS film or the like.
  • the first to third wiring parts 91 to 93 are made of aluminum or the like.
  • the first wiring section 91 has a first drain wiring section 91a located on the drain region 32 and a first source wiring section 91b located on the source region 35.
  • the second wiring section 92 has a second drain wiring section 92 a located on the drain region 32 and a second source wiring section 92 b located on the source region 35 .
  • the third wiring section 93 has a third drain wiring section 93a located on the drain region 32 and a third source wiring section 93b located on the source region 35.
  • first to third source wiring portions 91b to 93b are formed in a frame shape along the source region 35. That is, in the normal direction, the first to third drain wiring parts 91a to 93a formed on the drain region 32 are connected to the first to third source wiring parts 91b to 93b formed on the source region 35. It is surrounded.
  • the first drain wiring portion 91a is electrically connected to the drain region 32 through the first drain via 81a formed in the protective insulating film 60 and the first interlayer insulating film 81.
  • the first source wiring section 91b is electrically connected to the source region 35 through the first source via 81b formed in the protective insulating film 60 and the first interlayer insulating film 81.
  • the second drain wiring part 92a is connected to the first drain wiring part 91a through a second drain via 82a formed in the second interlayer insulating film 82.
  • the third drain wiring part 93a is connected to the second drain wiring part 92a through a third drain via 83a formed in the third interlayer insulating film 83.
  • the second source wiring portion 92b is connected to the first source wiring portion 91b through the second source via 82b formed in the second interlayer insulating film 82.
  • the third source wiring section 93b is connected to the second source wiring section 92b through a third source via 83b formed in the third interlayer insulating film 83.
  • each of the vias 81a, 81b to 83a, and 83b is constructed by embedding tungsten into a contact hole formed in each insulating film 60, 81 to 83, respectively.
  • the n type corresponds to the first conductivity type
  • the p type corresponds to the second conductivity type.
  • the semiconductor device of this embodiment when a positive voltage is applied to the gate electrode 51, a body located on the opposite side of the gate electrode 51 with a gate insulating film 53 composed of an element isolation insulating film 42 and an additional insulating film 52 interposed therebetween. Electrons are attracted to layer 34 to form an inversion layer. This results in an on state in which current flows between the source and drain.
  • the element isolation insulating film 42 and the additional insulating film 52 constituting the STI isolation section 40 are used as the gate insulating film 53, and the gate insulating film 53 can be easily thickened. Therefore, it is possible to easily apply a sufficiently high voltage to the gate electrode 51. That is, it can be said that the semiconductor device of this embodiment is configured by forming an HV (abbreviation for High Voltage) MOS.
  • HV abbreviation for High Voltage
  • the inversion layer disappears and an OFF state is established in which no current flows between the source and drain, and the potential of the drain region 32 becomes higher than the potential of the source region 35.
  • the drain region 32 which is a high potential region
  • the source region 35 which is a low potential region. Therefore, the high electric field caused by the drain region 32 becomes difficult to reach the trench isolation part 20, and it is possible to suppress the buried insulating film 22 in the trench isolation part 20 from being destroyed.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the additional insulating film 52. Therefore, the gate insulating film 53 can be easily made thicker, and a sufficiently high voltage can be easily applied to the gate electrode 51.
  • the gate insulating film 53 is configured to include the element isolation insulating film 42 and the additional insulating film 52. Therefore, the reliability of the gate insulating film 53 can be improved. That is, when forming the element isolation insulating film 42 and the additional insulating film 52, defects may be formed in the insulating films. In this case, even if a defect occurs in the element isolation insulating film 42 and the additional insulating film 52, there is a low possibility that each defect will be formed at an overlapping position in the normal direction. Therefore, even if a defect occurs in one insulating film, the gate breakdown voltage can be easily ensured in the other insulating film, and the reliability of the gate insulating film 53 can be improved.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the additional insulating film 52. Therefore, in the case of a semiconductor device that includes a plurality of element regions 14 and applies different voltages to the gate electrode 51 in each element region 14, the presence or absence of the additional insulating film 52 and the thickness of the additional insulating film 52 may affect the gate electrode 51.
  • the voltage applied to can be easily changed. In this case, for example, it is possible to change the voltage applied to the gate electrode 51 by changing the thickness of the element isolation insulating film 42 of the STI isolation section 40. However, this configuration requires design changes such as partially changing the depth of the trench 41, and the configuration tends to become complicated. Therefore, by configuring the gate insulating film 53 to include the element isolation insulating film 42 and the additional insulating film 52 as in this embodiment, it is possible to easily change the voltage applied to the gate electrode 51.
  • the additional insulating film 52 is not formed, and the gate electrode 51 is formed on the first interlayer insulating film 81. That is, in the semiconductor device of this embodiment, the element isolation insulating film 42 and the first interlayer insulating film 81 are used as the gate insulating film 53.
  • the gate electrode 51 may be made of doped polysilicon, or may be made of aluminum or the like like the first wiring section 91 disposed on the first interlayer insulating film 81.
  • the first interlayer insulating film 81 corresponds to a laminated insulating film. Furthermore, in the semiconductor device of this embodiment, since the additional insulating film 52 is not disposed, the protective insulating film 60 is disposed along the main surface 10a of the SOI substrate 10.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the first interlayer insulating film 81. Therefore, the gate insulating film 53 can be easily thickened, and a sufficiently high voltage can be easily applied to the gate electrode 51.
  • the first interlayer insulating film 81 used to configure the wiring layer 70 is used as the gate insulating film 53. Therefore, compared to the first embodiment, it is not necessary to provide the additional insulating film 52, and the configuration can be simplified.
  • the portion of the protective insulating film 60 that overlaps with the gate electrode 51 in the normal direction is removed.
  • the protective insulating film 60 is disposed at a portion different from the portion overlapping with the gate electrode 51 in the normal direction.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the first interlayer insulating film 81, the same effects as in the second embodiment can be obtained.
  • the portion of the protective insulating film 60 that overlaps with the gate electrode 51 in the normal direction is removed. For this reason, the threshold voltage required to be applied to the gate electrode 51 to turn on the semiconductor device changes compared to the case where the protective insulating film 60 is arranged in a portion overlapping with the gate electrode 51 in the normal direction. can be suppressed. That is, when the protective insulating film 60 is made of a nitride film as in this embodiment, and the element isolation insulating film 42 is made of an oxide film, in the structure of the second embodiment, the SiN film-SiO 2 interface , the interface state density becomes high and charges are easily captured.
  • the electric field applied to the gate insulating film 53 when the semiconductor device is turned on may trap charges in the interface level, which may cause the threshold voltage to change easily. Therefore, as in this embodiment, by removing the portion of the protective insulating film 60 that overlaps with the gate electrode 51 in the normal direction, it is possible to suppress a change in the threshold voltage.
  • a portion of the body layer 34 that overlaps with the gate electrode 51 is provided with a p - type layer having an impurity concentration lower than that of the body layer 34.
  • a buried channel layer 36 is formed.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the first interlayer insulating film 81, the same effects as in the first embodiment can be obtained.
  • a buried channel layer 36 having an impurity concentration lower than that of the body layer 34 is formed in a portion of the body layer 34 that overlaps with the gate electrode 51 in the normal direction. Therefore, when the semiconductor device is turned on, an inversion layer is likely to be formed in the body layer 34 (that is, the buried channel layer 36), and the increase in threshold voltage due to the thickening of the gate insulating film 53 is suppressed. can.
  • the body layer 34 is of n ⁇ type and is formed in the center of the surface layer of the active layer 13.
  • the source region 35 is of p + type and is formed in the surface layer of the body layer 34 so as to be exposed from the main surface 10a of the SOI substrate 10. Note that the source region 35 of this embodiment is formed to extend below the element isolation insulating film 42 so as to overlap with the end of the gate electrode 51 on the source region 35 side in the normal direction.
  • FIG. 7 shows the portions of the drain region 32 and the source region 35 that are exposed from the main surface 10a of the SOI substrate 10.
  • FIG. 6 is a sectional view taken along line VI-VI in FIG. 7.
  • the drift layer 31 is p - type and is formed at the outer edge of the surface layer of the active layer 13 . Specifically, drift layer 31 is formed so as to be in contact with trench isolation section 20 .
  • the drain region 32 is of p + type and is formed in the surface layer of the drift layer 31 so as to be exposed from the main surface 10a of the SOI substrate 10.
  • the buffer layer 33 is of p ⁇ type and is formed between the drain region 32 and the drift layer 31. Note that the drain region 32 is formed in a frame shape so as to surround the source region 35 in the normal direction.
  • the positional relationship between the drift layer 31 and the drain region 32, and the body layer 34 and the source region 35 is opposite to that in the first embodiment.
  • the STI isolation section 40 is formed such that the source region 35 is exposed through the first opening 40a, and the drain region 32 is exposed through the second opening 40b.
  • Gate electrode 51 is formed to face n ⁇ type active layer 13 and n ⁇ type body layer 34 .
  • the gate electrode 51 is formed at a position where an inversion layer can be formed in the active layer 13 and the body layer 34 in contact with the element isolation insulating film 42.
  • An additional insulating film 52 is formed below the gate electrode 51, and the element isolation insulating film 42 and the additional insulating film 52 constitute a gate insulating film 53. Further, the gate electrode 51 is arranged on a gate insulating film 53 constituted by the element isolation insulating film 42 and the additional insulating film 52.
  • the wiring layer 70 has a structure including first to third interlayer insulating films 81 to 83 and first to third wiring parts 91 to 93, as in the first embodiment.
  • the source region 35 is formed in the center of the active layer 13, and the drain region 32 is formed in a frame shape so as to surround the source region 35. Therefore, the first to third drain wiring parts 91a to 93a are formed in a frame shape so as to surround the first to third source wiring parts 91b to 93b.
  • the p type corresponds to the first conductivity type
  • the n type corresponds to the second conductivity type.
  • the element isolation insulating film 42 and the additional insulating film 52 constituting the STI isolation section 40 are used as the gate insulating film 53, and the gate insulating film 53 can be easily thickened. Therefore, it is possible to easily apply a sufficiently high voltage to the gate electrode 51.
  • the gate insulating film 53 includes the element isolation insulating film 42 and the additional insulating film 52 even in a semiconductor device in which a p-channel type LDMOS is formed, it is different from the first embodiment. A similar effect can be obtained.
  • the additional insulating film 52 is not formed, and the gate electrode 51 is formed on the first interlayer insulating film 81. That is, in the semiconductor device of this embodiment, the element isolation insulating film 42 and the first interlayer insulating film 81 are used as the gate insulating film 53. In other words, the semiconductor device of this embodiment has a configuration in which the semiconductor device of the second embodiment is changed to a p-channel LDMOS.
  • the same effects as the second embodiment can be obtained even if the second embodiment is a semiconductor device in which a p-channel LDMOS is formed.
  • a seventh embodiment will be described. This embodiment is a combination of the fifth embodiment and the third embodiment. Other aspects are the same as those in the fifth embodiment, so explanations will be omitted here.
  • the semiconductor device of this embodiment as shown in FIG. 9, the portion of the protective insulating film 60 that overlaps with the gate electrode 51 in the normal direction is removed.
  • the semiconductor device of this embodiment has a configuration in which the semiconductor device of the third embodiment is changed to a p-channel type LDMOS.
  • the third embodiment is a semiconductor device in which a p-channel LDMOS is formed, the same effects as in the third embodiment can be obtained.
  • the semiconductor device of this embodiment in the normal direction, a portion of the body layer 34 overlapping with the gate electrode 51 is provided with an n - type layer having an impurity concentration lower than that of the body layer 34. A buried channel layer 37 is formed. That is, the semiconductor device of this embodiment has a configuration in which the semiconductor device of the fourth embodiment is changed to a p-channel type LDMOS.
  • the fourth embodiment is a semiconductor device in which a p-channel LDMOS is formed, the same effects as in the fourth embodiment can be obtained.
  • the source region 35 and the drain region 32 may be isolated by a LOCOS insulating film instead of the STI isolation section 40. Then, a laminated insulating film may be disposed on the LOCOS insulating film, and the gate insulating film 53 may be configured to include the LOCOS insulating film. Note that in the case of such a configuration, the LOCOS insulating film corresponds to the element isolation insulating film.
  • the wiring layer 70 has a three-layer wiring structure.
  • the number of layers in the wiring layer 70 can be changed as appropriate.
  • the fourth embodiment may be combined with the second and third embodiments, and the second and third embodiments may also include the buried channel layer 36.
  • the eighth embodiment may be combined with the sixth and seventh embodiments, and the sixth and seventh embodiments may also include the buried channel layer 37.

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Abstract

La présente invention concerne un à dispositif semi-conducteur comprenant : un substrat semi-conducteur (10) qui a une surface principale (10a) ; une couche de dérive (31) d'un premier type de conductivité, la couche de dérive étant formée dans une partie superficielle côté surface principale (10a) ; une région de drain (32) du premier type de conductivité, la région de drain étant formée dans une partie superficielle de la couche de dérive (31) ; une couche de corps (34) d'un second type de conductivité, la couche de corps étant formée dans la partie superficielle côté surface principale (10a) à une certaine distance de la couche de dérive (31) ; une région de source (35) du premier type de conductivité, la région de source étant formée dans une partie superficielle de la couche de corps (34) ; un film d'isolation de grille (53) qui est formé sur la couche de corps (34) ; et une électrode de grille (51) qui est disposée sur le film d'isolation de grille (53). Un film isolant d'isolation d'élément (42), qui assure l'isolation de la région de source (35) et de la région de drain (32) l'une par rapport à l'autre, est disposé entre la région de source (35) et la région de drain (32) ; un film isolant multicouche (52) est disposé sur le film isolant d'isolation d'élément (42) ; et le film isolant de grille (53) est configuré de manière à contenir le film isolant d'isolation d'élément (42) et le film isolant multicouche (52).
PCT/JP2023/033089 2022-09-12 2023-09-11 Dispositif à semi-conducteur WO2024058140A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-144676 2022-09-12
JP2022144676A JP2024039928A (ja) 2022-09-12 2022-09-12 半導体装置

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015073089A (ja) * 2013-09-06 2015-04-16 株式会社半導体エネルギー研究所 半導体装置
JP2017188585A (ja) * 2016-04-06 2017-10-12 株式会社デンソー 半導体装置およびその製造方法
JP2020021881A (ja) * 2018-08-02 2020-02-06 株式会社豊田中央研究所 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015073089A (ja) * 2013-09-06 2015-04-16 株式会社半導体エネルギー研究所 半導体装置
JP2017188585A (ja) * 2016-04-06 2017-10-12 株式会社デンソー 半導体装置およびその製造方法
JP2020021881A (ja) * 2018-08-02 2020-02-06 株式会社豊田中央研究所 半導体装置

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