WO2024055205A1 - 覆晶薄膜、其制作方法及显示装置 - Google Patents

覆晶薄膜、其制作方法及显示装置 Download PDF

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Publication number
WO2024055205A1
WO2024055205A1 PCT/CN2022/118764 CN2022118764W WO2024055205A1 WO 2024055205 A1 WO2024055205 A1 WO 2024055205A1 CN 2022118764 W CN2022118764 W CN 2022118764W WO 2024055205 A1 WO2024055205 A1 WO 2024055205A1
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WIPO (PCT)
Prior art keywords
chip
layer
base material
leads
lead
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PCT/CN2022/118764
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English (en)
French (fr)
Inventor
卢鑫泓
曲燕
董水浪
李柳青
周靖上
李国腾
李宝曼
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/118764 priority Critical patent/WO2024055205A1/zh
Priority to CN202280003168.0A priority patent/CN118043964A/zh
Publication of WO2024055205A1 publication Critical patent/WO2024055205A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a chip-on-chip film, a manufacturing method thereof, and a display device.
  • the emerging three-dimensional (3D) display technologies such as virtual reality (VR) and augmented reality (AR) have particularly higher requirements for resolution because they are near-eye displays.
  • embodiments of the present disclosure provide a chip-on-chip film, including:
  • a plurality of bonding pads located on the at least one substrate layer
  • a plurality of first leads located on the at least one substrate layer, the plurality of first leads being electrically connected to part of the pads;
  • a plurality of second leads are located on a side of each base material layer away from the layer where the plurality of pads are located, and the plurality of second leads are electrically connected to the remaining pads.
  • the plurality of first leads are located between the at least one base material layer and the layer where the plurality of pads are located.
  • the first lead includes an integrally provided first wiring portion and a first connecting portion, and the first connecting portion is connected to the bonding pad Contact electrical connection.
  • the orthographic projection of the first connection portion on the base material layer and the pad electrically connected to it are on the base material layer. 's orthographic projections roughly coincide.
  • the above-mentioned chip-on-chip film provided by embodiments of the present disclosure further includes a plurality of first transfer electrodes, and the first transfer electrodes are connected between the second lead and the bonding pad. .
  • the plurality of first transfer electrodes and the plurality of first leads are provided in the same layer and in the same material.
  • the orthographic projection of the pad on the base material layer is located on the base of the base material of the first transfer electrode electrically connected thereto. within the orthographic projection on the layer.
  • the second lead includes an integrally provided second wiring portion and a second connection portion, and the second connection portion passes through the first The transfer electrode is electrically connected to the pad.
  • the second connection portion is electrically connected to the first transfer electrode.
  • the above-mentioned chip-on-chip film provided by embodiments of the present disclosure also includes a plurality of pad structures located on a side of the layer where the plurality of second leads are located away from the layer where the plurality of pads are located, so The orthographic projection of the pad electrically connected to the second connecting portion on the base material layer substantially coincides with the pad structure.
  • the orthographic projection of the raised structure on the base material layer is located at the orthogonal projection of the second connecting portion on the base material layer. within the projection.
  • the distance of the base material layer beyond the padding structure is within 0.5 ⁇ m.
  • the above-mentioned chip-on-chip film provided by embodiments of the present disclosure further includes a plurality of second transfer electrodes, the second transfer electrodes are embedded in the base material layer, and the first transfer electrodes It is electrically connected to the second connection part through the second transfer electrode.
  • the above-mentioned chip-on-chip film provided by the embodiment of the present disclosure further includes a plurality of third transfer electrodes, the third transfer electrodes are arranged in the same layer as the first transfer electrodes, and the A third transfer electrode is connected between the first transfer electrode and the second transfer electrode.
  • the first lead is provided integrally with the bonding pad.
  • the second lead includes an integrally provided second wiring portion and a second connection portion, and the second connection portion is connected to the bonding pad Contact electrical connection.
  • the above-mentioned chip-on-chip film provided by embodiments of the present disclosure also includes a plurality of pad structures located on a side of the layer where the plurality of second leads are located away from the layer where the plurality of pads are located, so
  • the orthographic projection shape of the padding structure on the base material layer is substantially the same as the orthographic projection shape of the second lead on the base substrate, and the orthogonal projection shape of the padding structure on the base material layer is approximately the same.
  • the projection is located within the orthographic projection of the second lead on the base substrate.
  • the material of the pad structure is the same as the material of the pad.
  • the orthographic projection of the second lead on the base material layer is the same as the orthographic projection of the first lead on the base material layer. Do not overlap with each other.
  • the plurality of bonding pads are arranged in an array, and any two adjacent rows of the bonding pads are partially staggered along a preset direction.
  • embodiments of the present disclosure also provide a method for manufacturing the above-mentioned chip-on-chip film, including:
  • At least one base material layer, as well as a plurality of first leads and a plurality of bonding pads are sequentially formed on the sacrificial layer, and before forming one of the base material layers each time, a plurality of second leads are respectively formed; wherein, The plurality of first leads are electrically connected to part of the pads, and the plurality of second leads are electrically connected to the rest of the pads;
  • the sacrificial layer is removed, so that the rigid substrate and the sacrificial layer are peeled off together to obtain the chip-on-chip film.
  • multiple first leads and multiple bonding pads are formed, specifically including:
  • One patterning process is used to form multiple first leads and multiple bonding pads at the same time, or two patterning processes are used to form multiple first leads and multiple bonding pads sequentially.
  • the method further includes:
  • the base material layer and the second lead are etched so that the base material layer exposes the copper layer of the second lead.
  • the base material layer and the second lead are etched each time, so that the base material layer exposes the second lead.
  • the copper layer and before forming the plurality of first leads it also includes:
  • a second transfer electrode is formed on the exposed copper layer of the second lead.
  • a second transfer electrode is formed on the exposed copper layer of the second lead.
  • a first transfer electrode is formed, and the second transfer electrode is electrically connected to the pad corresponding to the second lead through the first transfer electrode.
  • the method further includes:
  • a third transfer electrode is formed such that the second transfer electrode is electrically connected to the pad corresponding to the second lead through the third transfer electrode, the first transfer electrode, and the second lead in sequence.
  • the method before forming the plurality of second leads for the first time, the method further includes:
  • a plurality of pad structures are formed on the sacrificial layer, and the orthographic projection of the pad structures on the rigid substrate is approximately the same as the orthographic projection of the pads electrically connected to the second leads on the rigid substrate. coincide.
  • the method before forming the plurality of second leads for the first time, the method further includes:
  • a plurality of pad structures are formed on the sacrificial layer, the orthographic projection shape of the pad structures on the base material layer is substantially the same as the orthographic projection shape of the second lead on the base substrate, and The orthographic projection of the padding structure on the base material layer is located within the orthographic projection of the second lead on the base substrate.
  • an embodiment of the present disclosure provides a display device, including the above display substrate provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of using a single layer of metal to lay out pads and leads in the related art
  • Figure 2 is a schematic structural diagram of a chip-on-chip film provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of the layer where the first lead is located and the layer where the second lead is located in the chip-on-chip film shown in Figure 1;
  • Figure 4 is a cross-sectional view along line I-I’ in Figure 1;
  • Figure 5 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • Figure 6 is a cross-sectional view along line II-II’ in Figure 5;
  • Figure 7 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view along line III-III' in Figure 7;
  • Figure 9 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • Figure 10 is a cross-sectional view along line IV-IV’ in Figure 9;
  • Figure 11 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • Figure 12 is a cross-sectional view along line V-V’ in Figure 11;
  • Figure 13 is a schematic structural diagram of the layer where the first lead is located in the chip-on-chip film shown in Figure 1;
  • Figure 14 is a schematic structural diagram of the layer where the second lead is located in the chip-on-chip film shown in Figure 1;
  • Figure 15 is a schematic structural diagram of the padding structure in the flip-chip film shown in Figure 1;
  • Figure 16 is a structural schematic diagram of the pad structure and the second lead in the flip-chip film shown in Figure 10;
  • Figure 17 is a picture of a raised structure produced by an additive method according to an embodiment of the present disclosure.
  • Figure 18 is a picture of a raised structure produced by the subtractive method provided by the embodiment of the present disclosure.
  • Figure 19 is another structural schematic diagram of the chip-on-chip film shown in Figure 4.
  • Figure 20 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • Figure 21 is a flow chart of a method for manufacturing a chip-on-chip film provided by an embodiment of the present disclosure
  • Figure 22 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 4.
  • Figure 23 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 4.
  • Figure 24 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 4.
  • Figure 25 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 4.
  • Figure 26 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 4.
  • Figure 27 is a schematic structural diagram of the layer where the second lead is located in the chip-on-chip film shown in Figure 6;
  • Figure 28 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 6;
  • Figure 29 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 6;
  • Figure 30 is a schematic structural diagram of the layer where the second transfer electrode is located in the chip-on-chip film shown in Figure 6;
  • Figure 31 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 6;
  • Figure 32 is a schematic structural diagram of the layer where the first lead and the first transfer electrode are located in the chip-on-chip film shown in Figure 6;
  • Figure 33 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 6;
  • Figure 34 is a schematic structural diagram of the layer where the pad is located in the flip-chip film shown in Figure 6;
  • Figure 35 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 6;
  • Figure 36 is a schematic structural diagram of the layer where the second lead is located in the chip-on-chip film shown in Figure 8;
  • Figure 37 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 8.
  • Figure 38 is a schematic structural diagram of the layer where the first lead and the first transfer electrode are located in the chip-on-chip film shown in Figure 8;
  • FIG39 is a schematic diagram of another structure of the flip chip film shown in FIG8 during the manufacturing process.
  • Figure 40 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 8.
  • Figure 41 is a schematic structural diagram of the layer where the pad and the second transfer electrode are located in the chip-on-chip film shown in Figure 8;
  • Figure 42 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 8.
  • Figure 43 is a schematic structural diagram of the layer where the third transfer electrode is located in the chip-on-chip film shown in Figure 8;
  • Figure 44 is another structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 8.
  • Figure 45 is a schematic structural diagram of the layer where the second lead of the first layer is located in the chip-on-chip film shown in Figure 12;
  • Figure 46 is a schematic structural diagram of the chip-on-chip film shown in Figure 12 during the production process
  • Figure 47 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 48 is a schematic structural diagram of the layer where the first transfer electrode is located in the first layer of the chip-on-chip film shown in Figure 12;
  • Figure 49 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 50 is a schematic structural diagram of the layer where the second lead of the second layer is located in the chip-on-chip film shown in Figure 12;
  • Figure 51 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 52 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 53 is a schematic structural diagram of the layer where the second layer of the first transfer electrode is located in the chip-on-chip film shown in Figure 12;
  • Figure 54 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 55 is a schematic structural diagram of the layer where the first lead and the first transfer electrode are located in the chip-on-chip film shown in Figure 12;
  • Figure 56 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 57 is a schematic structural diagram of the layer where the pad is located in the flip-chip film shown in Figure 12;
  • Figure 58 is a structural schematic diagram of the manufacturing process of the chip-on-chip film shown in Figure 12;
  • Figure 59 is another structural schematic diagram of a chip-on-chip film provided by an embodiment of the present disclosure.
  • FIG. 60 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the chip-on-chip film must be laterally expanded (that is, the length is increased). But on the other hand, the chip is limited by wafer technology, cutting efficiency, etc.
  • the maximum lateral size i.e. length
  • embodiments of the present disclosure provide a chip-on-chip film, as shown in Figures 2 to 12, including:
  • the base material layer 101 can be a flexible base made of polyimide (PI) or other materials to ensure the flexible function of the chip-on-chip film;
  • PI polyimide
  • Multiple bonding pads 102 are located on the entire base material layer 101; in some embodiments, the multiple bonding pads 102 can be made using a subtractive electroplating method that requires relatively low space requirements, and the thickness of the bonding pads 102 can be 3 ⁇ m ⁇ 10 ⁇ m, such as 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc.;
  • a plurality of first leads 103 are located on the entire base material layer 101, and are electrically connected to part of the pads 102; in some embodiments, the material of the first leads 103 can be processed by dry etching.
  • Patterned (small CD Bias) metal materials such as titanium (Ti), molybdenum (Mo), aluminum (Al), etc.; the first lead 103 can be a single-layer structure or a stacked structure, such as the first lead 103 It is a single-layer structure such as titanium metal layer and molybdenum metal layer, or a laminated structure composed of titanium metal layer/aluminum metal layer/titanium metal layer, molybdenum metal layer/aluminum metal layer/molybdenum metal layer, etc.; optionally, When the first lead 103 has a stacked structure of titanium metal layer/aluminum metal layer/titanium metal layer, in order to ensure that the resistance of the first lead 103 is as low as possible, the thickness of the titanium metal layer can be
  • the plurality of second leads 104 are located on the side of each base material layer 101 away from the layer where the multiple bonding pads 102 are located. In other words, when there are multiple base material layers 101, each base material layer 101 is away from the multiple welding pads 102. A plurality of second leads 104 are provided on one side of the layer where the pad 102 is located. Optionally, the plurality of second leads 104 are electrically connected to the remaining pads 102 (that is, the pads 102 that are not connected to the first leads 103).
  • the materials and thicknesses of the plurality of second leads 104 can be the same as those of the plurality of first leads 103; in other embodiments, the materials of the second leads 104 can be the same as those of the first leads 103.
  • the materials of the lead 102 are different.
  • the second lead 104 has a laminated structure composed of a titanium metal layer/a copper metal layer/titanium metal layer, and from an economic perspective, the thickness of the copper metal layer can be For example etc., the thickness of the titanium metal layer does not exceed
  • a plurality of bonding pads 102 and a plurality of first leads 103 electrically connected to some of the bonding pads 102 are provided on one side of the base material layer 101 and connected with the rest.
  • the plurality of second leads 104 electrically connected to the bonding pads 102 are arranged on a side of the base material layer 101 away from the layer where the plurality of bonding pads 102 are located, so that the space on both sides of the base material layer 101 can be used for wiring.
  • the technical solution of arranging multiple pads 102 and multiple leads electrically connected to them on the same layer. This disclosure increases the wiring space.
  • the number of pads 102 When the number of pads 102 is the same as that of the related technology, sufficient wiring space can be used to increase the number of single rows. The number of pads 102 reduces the number of rows of pads 102 and reduces process difficulty. In addition, when the number of rows of bonding pads 102 is the same as that of the related technology, sufficient wiring space can be used to increase the upper limit of the number of bonding pads 102, thereby increasing the number of signal lines electrically connected to the bonding pads 102 in the display panel, and further improving the display The resolution of the panel.
  • the layer where the plurality of first leads 103 is located is located on all base material layers. 101 and the layer where the plurality of pads 102 are located, so that the layer where the multiple pads 102 are located and the layer where the multiple first leads 103 are located on the entire base material layer 101 are arranged in different layers.
  • the plurality of second leads 104 are located on the side of the base material layer 101 away from the layer where the plurality of bonding pads 102 are located. It can be seen that the layer where the plurality of bonding pads 102 are located, the layer where the multiple first leads 103 are located, and the layer where the multiple second leads 104 are located. The three are arranged on different layers, thus further increasing the wiring space.
  • the first lead 103 includes an integrally provided first wiring portion 1031 and a first connecting portion 1032 .
  • a connecting portion 1032 is electrically connected to the pad 102 .
  • the first connection part 1032 can be provided on the base material layer 101 The orthographic projection of the pad 102 electrically connected thereto substantially coincides with the orthographic projection on the base material layer 101 .
  • the "roughly coincident" may coincide exactly, or there may be some deviation (for example, a deviation of ⁇ 2 ⁇ m) , therefore, the "roughly coincident" relationship between relevant features falls within the scope of protection of the present disclosure as long as the error is allowed.
  • a plurality of first transfer electrodes 105 may also be included.
  • the electrode 105 is connected between the second lead 104 and the pad 102 .
  • the plurality of first transfer electrodes 105 and the plurality of first leads 103 are arranged on the same layer and with the same material. That is to say, the same film forming process is used to form the plurality of first transfer electrodes 105 .
  • the conductive film layer of the connecting electrode 105 and the plurality of first leads 103 is then used to form a plurality of first transfer electrodes 105 and the plurality of first leads 103 through a patterning process using the same mask. That is, one patterning process corresponds to one mask (also called photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes.
  • the multiple first transfer electrodes 105 and multiple first transfer electrodes 105 are formed.
  • the first lead wires 103 are independent of each other, and the plurality of first transfer electrodes 105 and the plurality of first lead wires 103 may have the same thickness or may have different thicknesses.
  • the first transfer electrode 105 and the first lead 103 are electrically connected to different pads 102. In order to improve the overall flatness of the pad 102, the thickness of the transfer electrode 105 and the first lead 103 can be made the same.
  • the orthographic projection of the pad 102 on the base material layer 101 is located electrically connected to it.
  • the first transfer electrode 105 is within the orthographic projection on the base material layer 101 . Since the layer where the plurality of first leads 103 is located is only provided with the first leads 103 and the first transfer electrode 105 (the pads 102 corresponding to the second leads 104 are electrically connected), compared with the related art in which all the leads and In the solution where all the bonding pads 102 are arranged on the same layer, the layer where the first lead 103 is located has enough space to arrange the first transfer electrode 105.
  • the size of the first transfer electrode 105 can be larger than the size of the soldering pad 102, which facilitates the second transfer electrode 105.
  • the pads 102 corresponding to the two leads 104 are in contact and electrically connected with the first transfer electrode 105 .
  • the second lead 104 includes an integrally provided second wiring portion 1041 and a second connection portion 1042 .
  • the second connecting portion 1042 is electrically connected to the pad 102 through the first transfer electrode 105 .
  • the second connection part 1042 is electrically connected to the first transfer electrode 105 in the transfer hole penetrating the base material layer 101 ; or, as shown in FIGS.
  • the second transfer electrodes 106 are embedded in the base material layer 101, and the first transfer electrode 105 is electrically connected to the second connection part 1042 through the second transfer electrodes 106; or, as shown in Figure 7 and As shown in FIG. 8 , a plurality of third transfer electrodes 107 may also be included.
  • the third transfer electrode 107 is arranged on the same layer as the first transfer electrode 105 .
  • the third transfer electrode 107 is connected between the first transfer electrode 105 and the first transfer electrode 105 . Between the two transfer electrodes 106, the first transfer electrode 105 is electrically connected to the second connection part 1042 through the third transfer electrode 107 and the second transfer electrode 106 in sequence.
  • an electroplating process can be used to make the second transfer electrode 106 of FIG. 5 and FIG. 6 , and the transfer hole of the base material layer 101 is filled flat to ensure the flatness of the subsequent layer where the first lead 103 is located.
  • an additive electroplating process to make the second transfer electrode 106 in Figures 7 and 8 to fill the transfer holes in the base material layer 101, multiple weldings for binding can also be completed.
  • the manufacturing of the pad 102 can reduce one electroplating process, which is beneficial to increasing production capacity.
  • the material of the second transfer electrode 106 is copper or other materials with good conductivity and low resistance.
  • the orthographic projections of the multiple pad structures 108 on one side of the layer where the disk 102 is located and the pad 102 electrically connected to the second connection part 1042 on the base material layer 101 roughly coincide, that is, the orthographic projections of the two coincide exactly. Or within the error range caused by factors such as craftsmanship and measurement.
  • the transfer hole of the base material layer 101 is relatively deep, which is not conducive to realizing electrical contact between the first transfer electrode 105 and the second connection portion 1042 in the transfer hole of the base material layer 101.
  • a The padding structure 108 is used to support the second connection part 1042 to reduce the hole depth of the base material layer 101 in disguise, so that the second connection part 1042 can be electrically connected to the first transfer electrode 105 in the transfer hole of the base material layer 101. connect.
  • the orthographic projection of the transfer hole of the base material layer 101 on the base material layer 101 is located within the orthographic projection of the surface of the pad structure 108 on the side of the layer where the pad 102 is located on the base material layer 101 .
  • the distance of the base material layer 101 beyond the padding structure 108 is within 0.5 ⁇ m, which is equivalent to the base layer 101.
  • the depth of the transfer hole in the material layer 101 at the position of the pad structure 108 is within 0.5 ⁇ m, which facilitates the electrical connection of the second connection portion 1042 with the first transfer electrode 105 in the transfer hole of the base material layer 101 .
  • the original chemical solution of the base material layer 101 has leveling properties, which is helpful to ensure the flatness of the base material layer 101 when the distance of the base material layer 101 beyond the padding structure 108 is within 0.5 ⁇ m.
  • Figure 17 shows the morphology of the raised structure 108 made by the additive method
  • Figure 18 shows the morphology of the raised structure 108 made by the subtractive method.
  • the cross-section of the structure 108 is approximately an inverted trapezoid, and the surface is uneven.
  • the cross-section of the raised structure 108 is a trapezoid, and the surface is relatively flat. Since the raised structure 108 is an island, the cross-sections of the raised structure 108 in all directions are substantially the same.
  • the present disclosure may prefer a subtractive method that requires relatively low space to produce the raised structure 108 .
  • the thickness uniformity of the pad structure 108 produced by the subtractive method is good.
  • the thickness of the pad structure 108 is 5 ⁇ m to 10 ⁇ m, for example, it can be 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc.
  • the thickness of the base material layer 101 is 5.5 ⁇ m to 10.5 ⁇ m, for example, it may be 5.5 ⁇ m, 6.5 ⁇ m, 7.5 ⁇ m, 8.5 ⁇ m, 9.5 ⁇ m, 10.5 ⁇ m, etc.
  • the material of the pad structure 108 may be an insulating material, or the same conductive material as the pad 102 may be used.
  • the material of the pad 108 is the same as the material of the pad 102 , raw material costs can be saved, and because the contact area between the second lead 104 and the pad 108 is larger, the second lead 104 and the pad 102 can also be made of the same material.
  • the overall resistance of structure 108 is low.
  • the padding structure 108 can be set on the base material layer.
  • the orthographic projection on 101 is located within the orthographic projection of the second connecting part 1042 on the base material layer 101 , that is, the raised structure 108 is wrapped by the second connecting part 1042 to protect the raised structure 108 .
  • the first lead 103 and the bonding pad 102 can be placed on the same layer.
  • the first lead 103 and the bonding pad 102 are integrally provided to avoid additional film layers of the first lead 103, reduce the number of film layers, and help improve the flexibility of the chip-on-chip film.
  • the second connection portion 1042 of the second lead 104 does not need to be connected to the pad 102 through the first transfer electrode 105 , but can be directly in contact and electrically connected to the pad 102 .
  • a plurality of pad structures 108 may still be provided on a side of the layer where the plurality of second leads 104 are located away from the layer where the plurality of bonding pads 102 are located.
  • the orthographic projection shape of the raising structure 108 on the base material layer 101 and the second lead 104 on the base substrate 101 can be set. The shapes of the orthographic projections on the substrate layer 108 are approximately the same.
  • the orthographic projection of the raised structure 108 on the base material layer 101 can be located within the orthographic projection of the second lead 104 on the base substrate 101 .
  • the distance between the mask and the exposure can be adjusted so that the distance between the second lead 104 and the pad structure 108 can be adjusted.
  • the shape is the same but the size is different, specifically by controlling the distance between the mask plate and the exposure lamp during the process of making the raising structure 108 to be smaller than the distance between the mask plate and the exposure lamp during the process of making the second lead 104, so as to A raised structure 108 having the same shape as the second lead 104 but smaller size is obtained.
  • the orthographic projection of the second lead 104 on the base material layer 101 does not overlap with each other to avoid signal interference caused by coupling capacitance due to overlap between the two.
  • the first wiring portions 1031 and the second wiring portions 1041 corresponding to the electrically connected pads 102 in the same column can be arranged alternately in the row direction XX', and the odd-numbered column pads 102 correspond to the electrically connected first wiring portions.
  • the alternating arrangement of the first wiring portion 1031 and the second wiring portion 1041 is the same.
  • the even rows of pads 102 correspond to the electrically connected first wiring portion 1031 and the second wiring portion 1041.
  • the odd-numbered rows of pads 102 correspond to electrical connections.
  • the alternating arrangement of the connected first wiring portions 1031 and the second wiring portions 1041 is opposite to the alternating arrangement of the first and second wiring portions 1031 and 1041 electrically connected to the even-numbered rows of pads 102 .
  • the first wiring portion 1031 and the second wiring portion 1041 are arranged on different layers, even if the distance between their orthographic projections on the base material layer 101 is smaller than that of the first wiring portion 1031 and the second wiring portion 1041 if they are arranged on the same layer in the related art, The distance between the leads can still effectively avoid short circuits between the two. Based on this, in this disclosure, the space between the layer where the first wiring part 1031 is located and the layer where the second wiring part 1041 is located is used to lay more leads.
  • multiple pads 102 are arranged in an array, with any adjacent The two rows of pads 102 are partially staggered along the preset direction Ensure that there is a large space for disposing the first wiring part 1031 and the second wiring part 1041, and avoid the first wiring part 1031 and the second wiring part 1041 from overlapping each other.
  • the pads 102 electrically connected to the first wiring part 1031 and the pads 102 electrically connected to the second wiring part 1041 are alternately arranged in both the row direction X-X' and the column direction Y-Y'.
  • the base material layer 101 in order to block water vapor, can be covered with a layer Inorganic layer 109.
  • an anti-oxidation layer 110 can be plated on the surface of the pad 102.
  • the anti-oxidation layer 110 can be made of tin (Sn), gold (Au) and other materials to prevent oxidation.
  • the thickness of the layer 110 may be 0.1 ⁇ m to 0.5 ⁇ m, such as 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.4 ⁇ m, 0.5 ⁇ m, etc.
  • screen printing can also be used to coat the solder resist layer 111 (Soler Resin, SR) on both the front and back sides of the base material layer 101.
  • the resist layer on the base material layer 101 The solder layer 111 exposes the first bonding area (OLB lead) for bonding the chip-on-chip film to the display panel (panel), the second bonding area (ILB lead) for bonding to the chip (IC), and the flexible circuit.
  • the solder resist layer 111 below the base material layer 101 is provided on the entire surface.
  • the solder resist layer 111 on the front side can be coated first, then the chip-on-chip film is laser peeled off (LLO) from the glass substrate, and finally the solder resist layer 111 on the back side is made; in other embodiments, The chip-on-chip film can also be laser-lifted (LLO) off the glass substrate first, and then the solder resist layer 111 on both sides is made, which is not limited here.
  • embodiments of the present disclosure provide a method for manufacturing a flip-chip film. Since the principle of solving problems of this manufacturing method is similar to the principle of solving problems of the above-mentioned flip-chip film, therefore, the manufacturing method provided by the embodiments of the disclosure For implementation, please refer to the implementation of the above-mentioned chip-on-chip film provided by the embodiments of the present disclosure, and repeated details will not be described again.
  • the above-mentioned production method provided by the embodiment of the present disclosure, as shown in Figure 21, includes the following steps:
  • S2102. Form at least one base material layer, a plurality of first leads and a plurality of bonding pads in sequence on the sacrificial layer, and form a plurality of second leads respectively before forming a base material layer each time; wherein, the plurality of first leads are formed.
  • One lead is electrically connected to part of the pads, and a plurality of second leads are electrically connected to the remaining pads;
  • forming multiple first leads and multiple pads in step S2102 can be implemented in the following two ways:
  • One possible implementation method is to use a patterning process to simultaneously form multiple first leads and multiple pads, so that the multiple first leads and multiple pads are arranged on the same layer and with the same material; another possible implementation method The method is: using two patterning processes to sequentially form multiple first leads and multiple bonding pads, so that the layer where the multiple first leads are located is between the layer where the multiple bonding pads are located and the base material layer closest to the layer where the bonding pads are located.
  • step S2102 after each base material layer is formed and before forming a plurality of first leads, the following steps may also be performed:
  • the base material layer and the second lead are etched so that the base material layer exposes the copper layer of the second lead, so as to facilitate the growth of the second transfer electrode on the copper layer.
  • a second transfer electrode is formed on the exposed copper layer of the second lead to connect the second lead and the subsequently produced pad through the second transfer electrode.
  • step S2102 while forming multiple bonding pads in step S2102, the following steps may also be performed:
  • a second transfer electrode is formed on the exposed copper layer of the second lead to avoid additional production of a second transfer electrode closest to the bonding pad and save money.
  • the first transfer electrode is formed so that the second transfer electrode is electrically connected to the pad corresponding to the second lead through the first transfer electrode.
  • the third transfer electrode is formed such that the second transfer electrode is electrically connected to the pad corresponding to the third transfer electrode, the first transfer electrode and the second lead in sequence.
  • the following steps may also be performed:
  • the orthographic projection of the padding structures on the rigid substrate substantially coincides with the orthographic projection of the pads electrically connected to the second lead on the rigid substrate.
  • the padding structures are on the base material layer.
  • the orthographic projection shape is substantially the same as the orthographic projection shape of the second lead on the base substrate, and the orthographic projection of the raising structure on the base material layer is located within the orthographic projection of the second lead on the base substrate.
  • the production of the chip-on-chip film shown in Figure 19 (equivalent to the chip-on-chip film shown in Figure 4) can be completed through the following steps:
  • a sacrificial layer 113 (De-Bonding Layer, DBL) is coated on the rigid substrate 112 (such as a glass substrate).
  • the material of the sacrificial layer 113 can be a polyimide system, and the thickness can be For example etc.; then electroplating is performed on the sacrificial layer 113 to produce a plurality of pad structures 108 (as shown in Figure 15).
  • the processing method of the pad structures 108 is preferably the subtractive method to ensure the uniformity of the film thickness.
  • the thickness of the pad structures 108 is 5 ⁇ m to 10 ⁇ m, such as 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc.
  • a plurality of second leads 104 are made.
  • the second leads 104 are preferably made of metal materials that can be patterned by dry etching (CD Bias is small), such as Ti, Ti/Al /Ti, Mo, Mo/Al/Mo, etc., the thickness should consider the principle of keeping the wiring resistance as low as possible. For example, the thickness of Ti/Al/Ti can be set to wait.
  • the second lead 104 needs to wrap the padding structure 108.
  • the second lead 104 includes an integrated second lead part 1041 and a second connection part 1042.
  • the second connection part 1042 wraps the raising structure 108, that is, the raising structure 108 is on the rigid substrate 112.
  • the orthographic projection is located within the orthographic projection of the second connection portion 1042 on the rigid substrate 112 .
  • a base material layer 101 is formed on the layer where the plurality of second leads 104 are located.
  • the base material layer 101 can be a flexible substrate such as polyimide, and its thickness needs to be the same as that of the padding structure 108.
  • the thicknesses are similar.
  • the thickness of the base material layer 101 is within 0.5 ⁇ m greater than the thickness of the padding structure 108 . Since the original chemical solution of the base material layer 101 has leveling properties, the base material layer 101 is flat in areas other than the padding structure 108 .
  • an inorganic layer 109 buffer can be deposited on the base material layer 101 to isolate water vapor.
  • the fourth step is to form a transfer hole penetrating the base material layer 101 and the inorganic layer 109 at the position corresponding to the padding structure 108, and then on the inorganic layer 109 Prepare a plurality of first leads 103 and a plurality of first transfer electrodes 105.
  • the orthographic projection of the first transfer electrodes 105 on the rigid substrate 112 can substantially coincide with the orthographic projection of the second connection portion 1042 on the rigid substrate 112, that is, The orthographic projections of the two coincide exactly, or are within the error range caused by manufacturing technology, measurement and other factors.
  • the material and thickness of the layer in which the plurality of first leads 103 and the plurality of first transfer electrodes 105 are located are selected to be the same as the material and thickness of the layer in which the plurality of second leads 104 are located.
  • a plurality of bonding pads 102 are made on the layer where the plurality of first leads 103 and the plurality of first transfer electrodes 105 are located, as final bonding pads.
  • an anti-oxidation layer 110 is plated on the surface of each pad 102.
  • the anti-oxidation layer 110 can be made of Sn, Au or other materials, and the thickness of the anti-oxidation layer 110 is 0.1 ⁇ m to 0.5 ⁇ m.
  • a subtractive electroplating method with relatively low space requirements is used to make multiple bonding pads 102, and the thickness of the bonding pads 102 may be 3 ⁇ m to 10 ⁇ m.
  • the sixth step uses laser lift-off (LLO) to peel off the rigid substrate 112. Due to the existence of the sacrificial layer 113, multiple second leads 104 and multiple pad structures 108 can be Successful separation.
  • LLO laser lift-off
  • the seventh step uses screen printing to coat the solder resist layer 111 (Soler Resin, SR) on both the front and back sides of the base material layer 101, and the solder resist layer 111 on the base material layer 101 is exposed.
  • the solder resist layer 111 below the base material layer 101 is provided on the entire surface.
  • the solder resist layer 111 on the front side can be coated first, then the chip-on-chip film is laser peeled off (LLO) from the glass substrate, and finally the solder resist layer 111 on the back side is made; in other embodiments, The chip-on-chip film can also be laser-lifted (LLO) off the glass substrate first, and then the solder resist layer 111 on both sides is made, which is not limited here.
  • the chip-on-chip film shown in Figure 10 can be produced based on similar steps from the first to sixth steps above.
  • the differences are: first, the shape of the pad structure 108 in Figure 10 is the same as the shape of the second lead 104, and The orthographic projection of the pad structure 108 is located within the orthographic projection of the second lead 104; secondly, there is no need to make the first lead 103 separately in Figure 10, but the first lead 103 can be made while making the pad 102, so that the first lead 103
  • the lead 103 and the bonding pad 102 are arranged in the same layer and with the same material, and there is no need to make the first transfer electrode 105.
  • the bonding pad 102 is in contact and electrically connected to the second connection part 1042.
  • the anti-oxidation layer 110 surrounding the first lead 103 may be formed at the same time as the anti-oxidation layer 110 surrounding the pad 102 is formed.
  • the production of the chip-on-chip film shown in Figure 6 can be achieved based on the following steps:
  • a sacrificial layer 113 (De-Bonding Layer, DBL) is coated on the rigid substrate 112 (such as a glass substrate).
  • the material of the sacrificial layer 113 can be a polyimide system, and the thickness can be For example wait.
  • a plurality of second leads 104 are formed on the sacrificial layer 113.
  • the second leads 104 include a second wiring portion 1041 and a second connection portion 1042.
  • the layer of the second leads 104 The structure is a 3-layer metal structure, the middle layer must be copper metal, and the upper/lower metal material must be molybdenum (Mo), aluminum (Al), titanium (Ti), molybdenum/nickel/titanium (MTD) alloy, etc. can be used
  • Mo molybdenum
  • Al aluminum
  • Ti titanium
  • MTD molybdenum/nickel/titanium
  • the material removed by the dry etching process is preferably Ti/Cu/Ti.
  • the thickness of the copper metal layer M can be The thickness of the upper metal layer U and the lower metal layer D preferably does not exceed Subsequently, the base material layer 101 and the inorganic layer 109 are formed on the plurality of second leads 104 .
  • a transfer hole is made at the position of the second connection part 1042, and a dry etching process is used to achieve one-time transfer of the inorganic layer 109, the base material layer 101, and the upper metal layer at the position of the second connection part 1042.
  • the etching of D, in particular, the upper metal layer D must be completely removed to ensure that subsequent copper metal plating can be performed to form the second transfer electrode 106.
  • an electroplating process is used to form the second transfer electrode 106 at the transfer hole, and the deeper transfer hole is filled in to ensure that the layer of the first lead 103 that is subsequently produced is The flatness.
  • the thick film of the base material layer 101 is etched by the hard mask of the inorganic layer 109 during dry etching, another structural feature of this embodiment is in the transfer hole.
  • the second transfer electrode 106 has a slope angle close to 90°.
  • a plurality of first leads 103 and a plurality of first transfer electrodes 105 are prepared on the inorganic layer 109.
  • a plurality of first leads 103 and a plurality of first transfer electrodes 105 are prepared.
  • the material and thickness of the layer where the transfer electrode 105 is located are selected to be the same as the material and thickness of the layer where the plurality of second leads 104 are located.
  • a plurality of bonding pads 102 are made on the layer where the plurality of first leads 103 and the plurality of first transfer electrodes 105 are located as final bonding pads.
  • an anti-oxidation layer 110 is plated on the surface of each pad 102.
  • the anti-oxidation layer 110 can be made of Sn or Au or other materials, and the thickness of the anti-oxidation layer 110 is 0.1 ⁇ m to 0.5 ⁇ m.
  • a subtractive electroplating method with relatively low space requirements is used to make multiple bonding pads 102, and the thickness of the bonding pads 102 may be 3 ⁇ m to 10 ⁇ m.
  • the seventh step uses laser lift-off (LLO) to peel off the rigid substrate 112. Due to the existence of the sacrificial layer 113, multiple second leads 104 and multiple pad structures 108 can be The separation was successful, and the chip-on-chip film shown in Figure 6 was obtained.
  • LLO laser lift-off
  • the production of the chip-on-chip film shown in Figure 8 can be achieved based on the following steps:
  • a sacrificial layer 113 (De-Bonding Layer, DBL) is coated on the rigid substrate 112 (such as a glass substrate).
  • the material of the sacrificial layer 113 can be a polyimide system, and the thickness can be For example wait.
  • a plurality of second leads 104 are formed on the sacrificial layer 113.
  • the second leads 104 include a second wiring portion 1041 and a second connection portion 1042.
  • the second leads 104 can Use dry etching to pattern metal materials (CD Bias is small), such as Ti, Ti/Al/Ti, Mo, Mo/Al/Mo, etc.
  • CD Bias is small
  • the thickness should be considered to have the wiring resistance as low as possible.
  • Ti can be set The thickness of /Al/Ti is wait.
  • the base material layer 101 and the inorganic layer 109 are formed on the layer where the second lead 104 is located.
  • no transfer holes have been formed in the base material layer 101 and the inorganic layer 109.
  • the first lead 103 and the first transfer electrode 105 are formed on the inorganic layer 109 and are made of the same layer and material.
  • the material and structure of the first lead 103 can be the same as the material and structure of the second lead 104 .
  • the fourth step is to make a transfer hole penetrating the base material layer 101 and the inorganic layer 109 at the position of the second connection part 1042 , and use a dry etching process to complete the inorganic layer at the position of the second connection part 1042 at one time. 109.
  • the upper metal layer D must be completely removed to ensure that subsequent copper metal plating can be performed to form the second transfer electrode 106.
  • additive plating is used to make the second transfer electrode 106 that fills the transfer hole, and at the same time, the bonding pad 102 is generated.
  • the third transfer electrode 107 is made, and the first transfer electrode 105 and the second transfer electrode 106 are connected.
  • the sacrificial layer 113 and the rigid substrate 112 can be peeled off by laser with reference to the sixth step in the manufacturing method of the flip-chip film shown in FIG. 19. At this point, the chip-on-chip film shown in FIG. 8 is obtained.
  • the seventh step in the manufacturing method of the flip-chip film shown in FIG. 19 to form the solder resist layer 111 on the front and back sides of the flip-chip film shown in FIG. 8 , which will not be described again here.
  • the chip-on-chip film shown in FIG. 12 shows two layers of second leads 104.
  • the second lead 104 produced for the first time is marked as 104A
  • the second lead 104 produced for the second time is marked as 104A.
  • 104B the production of the chip-on-chip film shown in Figure 12 can be achieved based on the following steps:
  • a sacrificial layer 113 (De-Bonding Layer, DBL) is coated on the rigid substrate 112 (such as a glass substrate).
  • the material of the sacrificial layer 113 can be a polyimide system, and the thickness can be For example wait.
  • a plurality of second leads 104A are formed on the sacrificial layer 113 for the first time.
  • the second leads 104A of this layer include a second wiring portion 1041 and a second connection portion 1042.
  • the layer structure of the second lead 104A is a three-layer metal structure, the middle layer must be copper metal, and the upper/lower metal material must be molybdenum (Mo), aluminum (Al), titanium (Ti), molybdenum/nickel/titanium (MTD) ) alloy and other materials that can be removed by dry etching process, preferably Ti/Cu/Ti.
  • the thickness of the copper metal layer M can be The thickness of the upper metal layer U and the lower metal layer D preferably does not exceed
  • the base material layer 101 and the inorganic layer 109 are formed on the layer where the second lead 104A is located, and a transfer hole is made at the position of the second connection part 1042, and the dry etching process is used to realize the first connection at one time.
  • the upper metal layer D must be completely removed to ensure that subsequent copper metal plating can be performed to form the second transfer electrode 106.
  • an electroplating process is used to form the second transfer electrode 106 at the transfer hole, and the deeper transfer hole is filled in to ensure that the layer of the first lead 103 that is subsequently produced is The flatness.
  • the thick film of the base material layer 101 is etched by the hard mask of the inorganic layer 109 during dry etching, another structural feature of this embodiment is in the transfer hole.
  • the second transfer electrode 106 has a slope angle close to 90°.
  • a plurality of second leads 104B and transition electrodes 1042 electrically connected to the second transfer electrodes 106 are formed on the layer where the first transfer electrode 106 produced in the fourth step is located.
  • the structure and material of the second lead 104B may be the same as the structure and material of the second lead 104A, and will not be described again here.
  • the sixth step can refer to the method of the third step to sequentially form the base material layer 101 and the inorganic layer 109 on the layer where the second lead 104B is located, and form a transition that penetrates the base material layer 101 and the inorganic layer 109. hole, and the upper metal of the transition electrode 1042' at the position of the transfer hole is etched away at the same time to ensure that subsequent copper metal plating can be performed to form the second transfer electrode 106.
  • the second transfer electrode 106 with a slope angle of approximately 90° can be formed at the transfer hole by referring to the method in the third step.
  • a plurality of first leads 103 and a plurality of first transfer electrodes 105 are prepared on the second transfer electrode 106 in the seventh step.
  • a plurality of first transfer electrodes 105 are prepared.
  • the material and thickness of the layer where the lead 103 and the plurality of first transfer electrodes 105 are located are selected to be the same as the material and thickness of the layer where the plurality of second leads 104A and 104B are located.
  • a plurality of bonding pads 102 are made on the layer where the plurality of first leads 103 and the plurality of first transfer electrodes 105 are located as final bonding pads.
  • an anti-oxidation layer 110 is plated on the surface of each pad 102.
  • the anti-oxidation layer 110 can be made of Sn, Au or other materials, and the thickness of the anti-oxidation layer 110 is 0.1 ⁇ m to 0.5 ⁇ m.
  • a subtractive electroplating method with relatively low space requirements is used to make multiple bonding pads 102, and the thickness of the bonding pads 102 may be 3 ⁇ m to 10 ⁇ m.
  • LLO laser lift-off
  • FIGS. 2 to 12 show the combination of the lead arrangement methods in the chip-on-chip film shown in Figure 4.
  • each film layer in Figure 59 can refer to the production of the same film layer in the chip-on-chip film shown in Figure 4.
  • the method of manufacturing the second lead 104 in FIG. 59 can refer to the method of manufacturing the second lead 104 in the chip-on-chip film shown in FIG. 4 , and will not be described again here.
  • the patterning process involved in forming each layer structure may not only include deposition, photoresist coating, masking, exposure, development, etching, photoresist Part or all of the process, such as peeling, may also include other processes.
  • the details are subject to the graphics of the required composition formed during the actual production process, which is not limited here.
  • a post-bake process may be included after development and before etching.
  • the deposition process can be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here;
  • the mask used in the mask process can be a half tone mask (Half Tone Mask) ), single slit diffraction mask (Single Slit Mask) or gray tone mask (Gray Tone Mask), which are not limited here;
  • etching can be dry etching or wet etching, which is not limited here.
  • embodiments of the disclosure provide a display device, including the above-mentioned chip-on-chip film provided by embodiments of the disclosure. Since the principle in which the display device solves the problem is similar to the principle in which the above-mentioned flip-chip film solves the problem, the implementation of the display device can be referred to the above-mentioned embodiment of the flip-chip film, and repeated details will not be repeated.
  • the above-mentioned display device may include a chip-on-chip film 001, a display substrate 002, a driver chip IC, and a flexible circuit board FPC.
  • the display substrate 002 is electrically connected to the first binding area BA 1 of the chip-on-chip film 001
  • the flexible circuit board FPC is electrically connected to the second binding area BA 2 of the chip-on-chip film 001
  • the driver chip IC is electrically connected to the third binding area of the chip-on-chip film 001 Zone BA 3 electrical connection.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other device with A product or component that displays functionality.
  • the above-mentioned display device provided by the embodiment of the present disclosure includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, control chip and other components.
  • the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc.
  • control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additional wires, signal lines, etc.
  • control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • programmable gate arrays programmable array logic
  • Programmable logic devices etc.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above display device provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.

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Abstract

本公开提供的覆晶薄膜、其制作方法及显示装置，包括至少一个基材层；多个焊盘，位于至少一个基材层之上；多条第一引线，位于至少一个基材层之上，多条第一引线与部分焊盘电连接；多条第二引线，位于每个基材层远离多个焊盘所在层的一侧，多条第二引线与其余焊盘电连接。

Description

覆晶薄膜、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种覆晶薄膜、其制作方法及显示装置。
背景技术
随着显示技术的不断发展，用户对显示分辨率(PPI)的要求越来越高。逐渐兴起的虚拟现实(VR)和增强现实(AR)等三维(3D)显示技术，由于其是近眼显示，尤其对分辨率提出了更高的要求。
发明内容
本公开实施例提供的覆晶薄膜、其制作方法及显示装置，具体方案如下：
一方面，本公开实施例提供了一种覆晶薄膜，包括：
至少一个基材层；
多个焊盘，位于所述至少一个基材层之上；
多条第一引线，位于所述至少一个基材层之上，所述多条第一引线与部分所述焊盘电连接；
多条第二引线，位于每个所述基材层远离所述多个焊盘所在层的一侧，所述多条第二引线与其余所述焊盘电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多条第一引线位于所述至少一个基材层与所述多个焊盘所在层之间。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第一引线包括一体设置的第一走线部和第一连接部，所述第一连接部与所述焊盘接触电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第一连 接部在所述基材层上的正投影与其电连接的所述焊盘在所述基材层上的正投影大致重合。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括多个第一转接电极，所述第一转接电极连接在所述第二引线与所述焊盘之间。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个第一转接电极与所述多条第一引线同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述焊盘在所述基材层上的正投影位于与其电连接的所述第一转接电极在所述基材层上的正投影内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第二引线包括一体设置的第二走线部和第二连接部，所述第二连接部通过所述第一转接电极与所述焊盘电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第二连接部与所述第一转接电极接触电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括位于所述多条第二引线所在层远离所述多个焊盘所在层一侧的多个垫高结构，所述垫高结构与所述第二连接部电连接的所述焊盘在所述基材层上的正投影大致重合。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述垫高结构在所述基材层上的正投影位于所述第二连接部在所述基材层上的正投影内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在垂直于所述基材层的方向上，所述基材层超出所述垫高结构的距离在0.5μm以内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括多个第二转接电极，所述第二转接电极嵌入所述基材层，所述第一转接电极通过所述第二转接电极与所述第二连接部电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括多个第三转接电极，所述第三转接电极与所述第一转接电极同层设置，所述第三 转接电极连接在所述第一转接电极与所述第二转接电极之间。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第一引线与所述焊盘一体设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第二引线包括一体设置的第二走线部和第二连接部，所述第二连接部与所述焊盘接触电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，还包括位于所述多条第二引线所在层远离所述多个焊盘所在层一侧的多个垫高结构，所述垫高结构在所述基材层上的正投影形状与所述第二引线在所述衬底基板上的正投影形状大致相同，且所述垫高结构在所述基材层上的正投影位于所述第二引线在所述衬底基板上的正投影内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述垫高结构的材料与所述焊盘的材料相同。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述第二引线在所述基材层上的正投影与所述第一引线在所述基材层上的正投影互不交叠。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，所述多个焊盘呈阵列排布，任意相邻两行所述焊盘沿预设方向局部错开设置。
另一方面，本公开实施例还提供了一种上述覆晶薄膜的制作方法，包括：
提供一个刚性基板，并在所述刚性基板上形成牺牲层；
在所述牺牲层上依次形成至少一个基材层、以及多条第一引线和多个焊盘，且在每次形成一个所述基材层之前，分别形成多条第二引线；其中，所述多条第一引线与部分所述焊盘电连接，所述多条第二引线与其余所述焊盘电连接；
去除所述牺牲层，使得所述刚性基板与所述牺牲层一同剥离，获得所述覆晶薄膜。
在一些实施例中，在本公开实施例提供的上述制作方法中，形成多条第 一引线和多个焊盘，具体包括：
采用一次构图工艺同时形成多条第一引线和多个焊盘，或者，采用两次构图工艺依次形成多条第一引线和多个焊盘。
在一些实施例中，在本公开实施例提供的上述制作方法中，在每次形成一个基材层之后，且在形成多条第一引线之前，还包括：
对所述基材层和所述第二引线进行刻蚀，使得所述基材层暴露出所述第二引线的铜层。
在一些实施例中，在本公开实施例提供的上述制作方法中，在每次对所述基材层和所述第二引线进行刻蚀，使得所述基材层暴露出所述第二引线的铜层之后，且在形成多条第一引线之前，还包括：
在暴露出的所述第二引线的铜层上形成第二转接电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，在形成多个焊盘的同时，还包括：
在最后一次对所述基材层和所述第二引线进行刻蚀后，暴露出的所述第二引线的铜层上形成第二转接电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，在形成多条第一引线的同时，还包括：
形成第一转接电极，所述第二转接电极通过所述第一转接电极与所述第二引线对应的所述焊盘电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在形成多个焊盘之后，还包括：
形成第三转接电极，使得所述第二转接电极依次通过所述第三转接电极、所述第一转接电极与所述第二引线对应的所述焊盘电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在首次形成多条第二引线之前，还包括：
在所述牺牲层上形成多个垫高结构，所述垫高结构在所述刚性基板上的正投影与所述第二引线电连接的所述焊盘在所述刚性基板上的正投影大致重 合。
在一些实施例中，在本公开实施例提供的上述制作方法中，在首次形成多条第二引线之前，还包括：
在所述牺牲层上形成多个垫高结构，所述垫高结构在所述基材层上的正投影形状与所述第二引线在所述衬底基板上的正投影形状大致相同，且所述垫高结构在所述基材层上的正投影位于所述第二引线在所述衬底基板上的正投影内。
另一方面，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述显示基板。
附图说明
图1为相关技术中采用单层金属布设焊盘与引线的示意图；
图2为本公开实施例提供的覆晶薄膜的一种结构示意图；
图3为图1所示覆晶薄膜中第一引线所在层和第二引线所在层的结构示意图；
图4为图1中沿I-I’线的一种截面图；
图5为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图6为图5中沿II-II’线的一种截面图；
图7为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图8为图7中沿III-III’线的一种截面图；
图9为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图10为图9中沿IV-IV’线的一种截面图；
图11为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图12为图11中沿V-V’线的一种截面图；
图13为图1所示覆晶薄膜中第一引线所在层的结构示意图；
图14为图1所示覆晶薄膜中第二引线所在层的结构示意图；
图15为图1所示覆晶薄膜中垫高结构的结构示意图；
图16为图10所示覆晶薄膜中垫高结构与第二引线的结构示意图；
图17为本公开实施例提供的加成法制作的垫高结构的图片；
图18为本公开实施例提供的减成法制作的垫高结构的图片；
图19为图4所示覆晶薄膜的又一种结构示意图；
图20为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图21为本公开实施例提供的覆晶薄膜的制作方法的流程图；
图22为图4所示覆晶薄膜在制作过程中的一种结构示意图；
图23为图4所示覆晶薄膜在制作过程中的又一种结构示意图；
图24为图4所示覆晶薄膜在制作过程中的又一种结构示意图；
图25为图4所示覆晶薄膜在制作过程中的又一种结构示意图；
图26为图4所示覆晶薄膜在制作过程中的又一种结构示意图；
图27为图6所示覆晶薄膜中第二引线所在层的结构示意图；
图28为图6所示覆晶薄膜在制作过程中的一种结构示意图；
图29为图6所示覆晶薄膜在制作过程中的又一种结构示意图；
图30为图6所示覆晶薄膜中第二转接电极所在层的结构示意图；
图31为图6所示覆晶薄膜在制作过程中的又一种结构示意图；
图32为图6所示覆晶薄膜中第一引线和第一转接电极所在层的结构示意图；
图33为图6所示覆晶薄膜在制作过程中的又一种结构示意图；
图34为图6所示覆晶薄膜中焊盘所在层的结构示意图；
图35为图6所示覆晶薄膜在制作过程中的又一种结构示意图；
图36为图8所示覆晶薄膜中第二引线所在层的结构示意图；
图37为图8所示覆晶薄膜在制作过程中的一种结构示意图；
图38为图8所示覆晶薄膜中第一引线和第一转接电极所在层的结构示意图；
图39为图8所示覆晶薄膜在制作过程中的又一种结构示意图；
图40为图8所示覆晶薄膜在制作过程中的又一种结构示意图；
图41为图8所示覆晶薄膜中焊盘和第二转接电极所在层的结构示意图；
图42为图8所示覆晶薄膜在制作过程中的又一种结构示意图；
图43为图8所示覆晶薄膜中第三转接电极所在层的结构示意图；
图44为图8所示覆晶薄膜在制作过程中的又一种结构示意图；
图45为图12所示覆晶薄膜中第一层第二引线所在层的结构示意图；
图46为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图47为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图48为图12所示覆晶薄膜中第一层第一转接电极所在层的结构示意图；
图49为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图50为图12所示覆晶薄膜中第二层第二引线所在层的结构示意图；
图51为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图52为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图53为图12所示覆晶薄膜中第二层第一转接电极所在层的结构示意图；
图54为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图55为图12所示覆晶薄膜中第一引线和第一转接电极所在层的结构示意图；
图56为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图57为图12所示覆晶薄膜中焊盘所在层的结构示意图；
图58为图12所示覆晶薄膜在制作过程中的一种结构示意图；
图59为本公开实施例提供的覆晶薄膜的又一种结构示意图；
图60为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明 本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前随着4K、8K显示产品的普及，对应的分辨率越来越高，相应的芯片(IC)的信号数也越多。尤其是对于三维显示产品，三维效果越好，则要求的视图数越多，对应的信号线的数量会有数倍的增长，如此对芯片、覆晶薄膜(COF)、柔性电路板(FPC)等提出了更高的挑战。但受限于现在铜箔的制作加工能力，覆晶薄膜上铜走线的布线周期(Line Pitch)最小仅在18μm左右，而量产的覆晶薄膜卷带上芯片绑定工艺周期水平仅在24μm，导致目前行业内最高水平仅能达到4000通道。因此要想满足超多信号线的要求，就必须进行覆晶薄膜的横向扩大(即增大长度)。不过另一方面，芯片受到晶圆工艺、切割效率等限制，横向尺寸(即长度)最大仅能做到32mm，因此无法对应更多信号线。
覆晶薄膜绑定的芯片IC长度L公式为
Figure PCTCN2022118764-appb-000001
其中，W L＝(n-1+0.5)×P 1，Wp表示焊盘宽度，W L表示相邻焊盘的间距；m为pin数量，n为排数，P 1为布线周期(Line Pitch)，相关技术中，芯片长度L的最大值为32000μm，焊盘宽度Wp的最小值为12μm，布线周期(Line Pitch)的最小值为3.6μm，焊盘宽度Wp与焊盘间距W L(相当于焊盘周期Lead Pitch)之 和大于等于24μm。由该公式结合图1和表1可知，在覆晶薄膜的焊盘(也称为引脚pin)和引线采用同层布线的前提下，排数n相同的情况下，布线周期(Line Pitch)和焊盘周期(Lead Pitch)均随着焊盘数量增加而进一步的压缩，极容易达到当前产线的工艺极限，唯一的解决方案就是增加焊盘的排数n。而增加焊盘排数n就会增加与覆晶薄膜绑定的芯片IC的宽度，不仅会降低芯片切割效率，更会增加后续内焊盘绑定(Inner Lead Bonding，ILB)的工艺难度。
表1
Figure PCTCN2022118764-appb-000002
为了解决相关技术中存在的上述技术问题，本公开实施例提供了一种覆晶薄膜，如图2至图12所示，包括：
至少一个基材层101，可选地，基材层101可以为聚酰亚胺(PI)等材质的柔性基底，以保证覆晶薄膜的柔性功能；
多个焊盘102，位于全部基材层101之上；在一些实施例中，可采用对于空间需求相对较低的减成电镀法制作多个焊盘102，焊盘102的厚度可以为3μm～10μm，例如为3μm、4μm、5μm、6μm、7μm、8μm、9μm、10μm等；
多条第一引线103，位于全部基材层101之上，多条第一引线103与部分焊盘102电连接；在一些实施例中，第一引线103的材料包括可以用干法刻蚀进行图案化(CD Bias小)的金属材料，例如钛(Ti)、钼(Mo)、铝(Al) 等；第一引线103可以为单层结构，也可以为叠层结构，例如第一引线103为钛金属层、钼金属层等单层结构，或为由钛金属层/铝金属层/钛金属层、钼金属层/铝金属层/钼金属层等构成的叠层结构；可选地，在第一引线103为钛金属层/铝金属层/钛金属层的叠层结构的情况下，为保证第一引线103的电阻尽可能低，可以设置钛金属层的厚度为
Figure PCTCN2022118764-appb-000003
铝金属层的厚度为
Figure PCTCN2022118764-appb-000004
多条第二引线104，位于每个基材层101远离多个焊盘102所在层的一侧，换言之，在基材层101为多个的情况下，每个基材层101远离多个焊盘102所在层的一侧均设置有多条第二引线104，可选地，多条第二引线104与其余焊盘102(即未连接第一引线103的焊盘102)电连接，在一些实施例中，为简化工艺、节约原料成本，多条第二引线104的材料及厚度选择可以与多条第一引线103相同；在另一些实施例中，第二引线104的材料可以与第一引线102的材料不同，例如第二引线104具有由钛金属层/铜金属层/钛金属层构成的叠层结构，且从经济性考率，铜金属层的厚度可以为
Figure PCTCN2022118764-appb-000005
例如
Figure PCTCN2022118764-appb-000006
等，钛金属层厚度不超过
Figure PCTCN2022118764-appb-000007
在本公开实施例提供的上述覆晶薄膜中，通过将多个焊盘102、以及与部分焊盘102电连接的多条第一引线103设置在基材层101的一侧，并将与其余焊盘102电连接的多条第二引线104设置在基材层101远离多个焊盘102所在层的一侧，使得可利用基材层101双侧的空间进行布线，相较于仅在单侧同层设置多个焊盘102及其电连接的多条引线的技术方案，本公开增加了布线空间，在焊盘102数量与相关技术相同的情况下，可利用充足的布线空间增加单排焊盘102的数量，减少焊盘102的排数，降低工艺难度。另外，在焊盘102的排数与相关技术相同的情况下，可利用充足的布线空间提升焊盘102数量的上限，从而增加显示面板中与焊盘102电连接的信号线数量，进一步提高显示面板的分辨率。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图4、图6、图8、图10和图12所示，多条第一引线103所在层位于全部基材层101与多个焊盘102所在层之间，这样可以使得在全部基材层101之上设置的多个焊 盘102所在层、多条第一引线103所在层为异层设置，结合上述记载的多条第二引线104位于基材层101远离多个焊盘102所在层的一侧可知，多个焊盘102所在层、多条第一引线103所在层、以及多条第二引线104所在层三者异层设置，由此进一步增加了布线空间。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图2至图12所示，第一引线103包括一体设置的第一走线部1031和第一连接部1032，第一连接部1032与焊盘102接触电连接。可选地，为保证第一连接部1032与焊盘102之间的接触面积较大，相应的接触电阻较小，电连接效果较好，可以设置第一连接部1032在基材层101上的正投影与其电连接的焊盘102在基材层101上的正投影大致重合。需要说明的是，在本公开提供的实施例中，由于工艺条件的限制或测量等其他因素的影响，“大致重合”可能会恰好重合，也可能会有一些偏差(例如具有±2μm的偏差)，因此相关特征之间“大致重合”的关系只要满足误差允许，均属于本公开的保护范围。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图3至图8、图11和图12所示，还可以包括多个第一转接电极105，第一转接电极105连接在第二引线104与焊盘102之间。可选地，如图13所示，多个第一转接电极105与多条第一引线103同层、同材料设置，也就是说，采用同一成膜工艺形成用于制作多个第一转接电极105和多条第一引线103的导电膜层，然后利用同一掩模板通过一次构图工艺形成多个第一转接电极105和多条第一引线103。即一次构图工艺对应一道掩模板(mask，也称光罩)，根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，所形成多个第一转接电极105和多条第一引线103是相互独立的，且多个第一转接电极105和多条第一引线103可能具有相同的厚度、也可能具有不同的厚度。本公开中第一转接电极105、以及第一引线103与不同的焊盘102电连接，为了提高焊盘102的整体平坦度，可以使得转接电极105和第一引线103的厚度相同。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图2至图8、图11和图12所示，焊盘102在基材层101上的正投影位于与其电连接的第 一转接电极105在基材层101上的正投影内。由于多条第一引线103所在层仅设置有第一引线103和第一转接电极105(与第二引线104对应的焊盘102对应电连接)，因此相较于相关技术中将全部引线和全部焊盘102设置在同一层的方案，第一引线103所在层具有足够大的空间设置第一转接电极105，因此可以将第一转接电极105的尺寸大于焊盘102的尺寸，便于第二引线104对应的焊盘102与第一转接电极105接触电连接。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图2至图8所示，第二引线104包括一体设置的第二走线部1041和第二连接部1042，第二连接部1042通过第一转接电极105与焊盘102电连接。可选地，如图4所示，第二连接部1042在贯穿基材层101的转接孔内与第一转接电极105接触电连接；或者，如图5和图6所示，还可以包括多个第二转接电极106，第二转接电极106嵌入基材层101，第一转接电极105通过第二转接电极106与第二连接部1042电连接；或者，如图7和图8所示，还可以包括多个第三转接电极107，第三转接电极107与第一转接电极105同层设置，第三转接电极107连接在第一转接电极105与第二转接电极106之间，使得第一转接电极105依次通过第三转接电极107、第二转接电极106电连接至第二连接部1042。
在一些实施例中，可采用电镀工艺制作图5和图6的第二转接电极106，将基材层101的转接孔填平，以保证后续第一引线103所在层的平坦度。可选地，在采用加成法电镀工艺制作图7和图8中的第二转接电极106来填平基材层101的转接孔的同时，还可以完成起绑定作用的多个焊盘102的制作，如此相较于采用两次电镀工艺分别制作第二转接电极106和焊盘102的方案，可减少一次电镀工艺，利于提升产能。可选地，第二转接电极106的材料为铜等导电性较好、电阻较小的材料。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图4、图10、图14和图15所示，还可以包括位于多条第二引线104所在层远离多个焊盘102所在层一侧的多个垫高结构108，垫高结构108与第二连接部1042电连接的焊盘102在基材层101上的正投影大致重合，即二者的正投影恰好 重合或在因工艺制作、测量等因素造成的误差范围内。本公开中基材层101的转接孔较深，不利于实现第一转接电极105在基材层101的转接孔内与第二连接部1042接触电连接，因此，本公开中设置了用于支撑第二连接部1042的垫高结构108，以变相减小基材层101的孔深，便于第二连接部1042在基材层101的转接孔内与第一转接电极105电连接。可选地，基材层101的转接孔在基材层101上的正投影位于垫高结构108靠近焊盘102所在层一侧的表面在基材层101上的正投影内。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，在垂直于基材层101的方向Z上，基材层101超出垫高结构108的距离在0.5μm以内，相当于基材层101在垫高结构108位置处转接孔的孔深在0.5μm以内，利于第二连接部1042在基材层101的转接孔内与第一转接电极105电连接。并且，基材层101的原药液具备流平特性，在基材层101超出垫高结构108的距离在0.5μm以内的情况下，利于保证基材层101的平坦性。
示例性地，图17示出了采用加成法所制作垫高结构108的形貌，图18示出了采用减成法所制作垫高结构108的形貌，对比可见，图17中垫高结构108的截面近似为倒梯形，且表面不平整，图18中垫高结构108的截面是梯形，且表面较平整。由于垫高结构108是孤岛，因此，垫高结构108在各个方向的截面大致相同。考虑到加成法所制作倒梯形形貌的垫高结构108不利于被第二连接部1042所覆盖，本公开可优选对于空间需求相对较低的减成法来制作垫高结构108。减成法制作的垫高结构108的膜厚均一性较好，可选地，垫高结构108的厚度为5μm～10μm，例如可以为5μm、6μm、7μm、8μm、9μm、10μm等。相应地，基材层101的厚度为5.5μm～10.5μm，例如可为5.5μm、6.5μm、7.5μm、8.5μm、9.5μm、10.5μm等。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，垫高结构108的材料可以为绝缘材料，也可以采用与焊盘102相同的导电材料。在垫高结构108的材料与焊盘102的材料相同的情况下，可节约原料成本，且因第二引线104与垫高结构108的接触面积较大，还可使得第二引线104与垫高结 构108的整体电阻较小。可选地，为避免与焊盘102的材料相同的垫高结构108在后续制作基材层101的工序中被氧化，如图3和图6所示，可以设置垫高结构108在基材层101上的正投影位于第二连接部1042在基材层101上的正投影内，即通过第二连接部1042包裹垫高结构108，以实现对垫高结构108的保护。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图9和图10所示，当焊盘的总数不太多时，可以将第一引线103与焊盘102同层、同材料设置，可选地，第一引线103与焊盘102一体设置，以避免额外设置第一引线103的膜层，减少膜层数量，利于提升覆晶薄膜的柔性。在此情况下，第二引线104的第二连接部1042无需通过第一转接电极105与焊盘102转接，而是可以直接与焊盘102接触电连接。可选地，为利于焊盘102与第二连接部1042的电连接，仍可在位于多条第二引线104所在层远离多个焊盘102所在层的一侧设置多个垫高结构108。在一些实施例中，为共用掩膜板，节约掩膜板成本，如图16所示，可设置垫高结构108在基材层101上的正投影形状与第二引线104在衬底基板101上的正投影形状大致相同，同时为了保护垫高结构108，可设置垫高结构108在基材层101上的正投影位于第二引线104在衬底基板101上的正投影内。在具体实施时，在采用同一掩膜板分别制作第二引线104和垫高结构108的过程中，可通过调节掩膜板与曝光等之间的距离使得第二引线104和垫高结构108的形状相同但尺寸不同，具体通过控制在制作垫高结构108的过程中掩膜板与曝光灯之间的距离小于在制作第二引线104的过程中掩膜板与曝光等之间的距离，以获得与第二引线104形状相同但尺寸较小的垫高结构108。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图2、图5、图7、图9和图11所示，第二引线104在基材层101上的正投影与第一引线103在基材层101上的正投影互不交叠，以避免二者之间因交叠而产生耦合电容造成信号干扰。可选地，同列焊盘102对应电连接的第一走线部1031和第二走线部1041可以在行方向X-X’上交替设置，奇数列焊盘102对应电连接的 第一走线部1031和第二走线部1041的交替排列方式相同，偶数列焊盘102对应电连接的第一走线部1031和第二走线部1041的交替排列方式相同，奇数列焊盘102对应电连接的第一走线部1031和第二走线部1041的交替排列方式与偶数列焊盘102对应电连接的第一走线部1031和第二走线部1041的交替排列方式相反。应当理解的是，因第一走线部1031与第二走线部1041是异层设置的，因此即使二者在基材层101上的正投影之间的距离小于相关技术中同层设置的引线之间的距离，依然可以有效避免二者之间短接。基于此，本公开中利用第一走线部1031所在层与第二走线部1041所在层的空间布设较多的引线。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图2、图5、图7、图9和图11所示，多个焊盘102呈阵列排布，任意相邻两行焊盘102沿预设方向X局部错开设置，相较于各行焊盘102平齐设置的方案，本公开通过在预设方向X上将任意相邻两行焊盘102局部错开设置，利于保证有较大的空间设置第一走线部1031和第二走线部1041，避免第一走线部1031和第二走线部1041相互交叠。可选地，第一走线部1031电连接的焊盘102与第二走线部1041电连接的焊盘102在行方向X-X’和列方向Y-Y’上均交替设置。
在一些实施例中，在本公开实施例提供的上述覆晶薄膜中，如图4、图6、图8、图10和图12所示，为阻隔水汽，可在基材层101上覆盖一无机层109。且为防止焊盘102被氧化影响焊盘102的导电性，可在焊盘102的表面镀防氧化层110，防氧化层110可采用锡(Sn)、金(Au)等材料制作，防氧化层110的厚度可以为0.1μm～0.5μm，例如为0.1μm、0.2μm、0.3μm、0.4μm、0.5μm等。可选地，如图19和图20所示，还可采用丝网印刷方式在基材层101的正反面均涂布阻焊层111(Soler Resin，SR)，基材层101之上的阻焊层111露出覆晶薄膜与显示面板(panel)进行绑定的第一绑定区(OLB lead)、与芯片(IC)进行绑定的第二绑定区(ILB lead)、以及与柔性电路板(FPC)进行绑定的第三绑定区(FOF lead)，基材层101下方的阻焊层111整面设置。在 一些实施例中，可采用先涂布正面的阻焊层111，再将覆晶薄膜自玻璃基板上激光剥离(LLO)掉，最后制作反面的阻焊层111；在另一些实施例中，也可以先将覆晶薄膜自玻璃基板上激光剥离(LLO)掉，再制作正反两面的阻焊层111，在此不做限定。
基于同一发明构思，本公开实施例提供了一种覆晶薄膜的制作方法，由于该制作方法解决问题的原理与上述覆晶薄膜解决问题的原理相似，因此，本公开实施例提供的该制作方法的实施可以参见本公开实施例提供的上述覆晶薄膜的实施，重复之处不再赘述。
在一些实施例中，本公开实施例提供的上述制作方法，如图21所示，包括以下步骤：
S2101、提供一个刚性基板，并在刚性基板上形成牺牲层；
S2102、在牺牲层上依次形成至少一个基材层、以及多条第一引线和多个焊盘，且在每次形成一个基材层之前，分别形成多条第二引线；其中，多条第一引线与部分焊盘电连接，多条第二引线与其余焊盘电连接；
S2103、去除牺牲层，使得刚性基板与牺牲层一同剥离，获得覆晶薄膜。
在一些实施例中，在本公开实施例提供的上述制作方法中，步骤S2102中的形成多条第一引线和多个焊盘，具体可以通过以下两种方式进行实现：
其中一种可能的实现方式为：采用一次构图工艺同时形成多条第一引线和多个焊盘，使得多条第一引线和多个焊盘同层同材料设置；另一种可能的实现方式为：采用两次构图工艺依次形成多条第一引线和多个焊盘，使得多条第一引线所在层位于多个焊盘所在层与距离焊盘所在层最近的基材层之间。
在一些实施例中，在本公开实施例提供的上述制作方法中，在上述步骤S2102中，每次形成一个基材层之后，且在形成多条第一引线之前，还可以执行以下步骤：
对基材层和第二引线进行刻蚀，使得基材层暴露出第二引线的铜层，以便于在铜层上生长第二转接电极。
在一些实施例中，在本公开实施例提供的上述制作方法中，在每次对基 材层和第二引线进行刻蚀，使得基材层暴露出第二引线的铜层之后，且在形成多条第一引线之前，还可以执行以下步骤：
在暴露出的第二引线的铜层上形成第二转接电极，以通过第二转接电极连接第二引线和后续制作的焊盘。
在一些实施例中，在本公开实施例提供的上述制作方法中，在步骤S2102中形成多个焊盘的同时，还可以执行以下步骤：
在最后一次对基材层和第二引线进行刻蚀后，暴露出的第二引线的铜层上形成第二转接电极，以避免额外制作与焊盘距离最近的第二转接电极，节约一道工序。
在一些实施例中，在本公开实施例提供的上述制作方法中，在形成多条第一引线的同时，还可以形成以下步骤：
形成第一转接电极，使得第二转接电极通过第一转接电极与第二引线对应的焊盘电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在形成多个焊盘之后，还可以执行以下步骤：
形成第三转接电极，使得第二转接电极依次通过第三转接电极、第一转接电极与第二引线对应的焊盘电连接。
在一些实施例中，在本公开实施例提供的上述制作方法中，在首次形成多条第二引线之前，还可以执行以下步骤：
在牺牲层上形成多个垫高结构，垫高结构在刚性基板上的正投影与第二引线电连接的焊盘在刚性基板上的正投影大致重合，或者，垫高结构在基材层上的正投影形状与第二引线在衬底基板上的正投影形状大致相同，且垫高结构在基材层上的正投影位于第二引线在衬底基板上的正投影内。
为了更好的理解本公开实施例提供的上述制作方法，以下对本公开实施例提供的上述显示基板的制作过程进行详细说明。
在一些实施例中，可通过以下步骤完成图19所示覆晶薄膜(相当于图4所示覆晶薄膜)的制作：
第一步，如图22所示，在刚性基板112(例如玻璃基板)上涂布牺牲层113(De-Bonding Layer，DBL)，牺牲层113的材料可以为聚酰亚胺体系，厚度可以为
Figure PCTCN2022118764-appb-000008
例如
Figure PCTCN2022118764-appb-000009
Figure PCTCN2022118764-appb-000010
等；然后在牺牲层113上电镀制作多个垫高结构108(如图15所示)，垫高结构108的加工方式优选减成法以确保膜厚的均一性，垫高结构108的厚度为5μm～10μm，例如5μm、6μm、7μm、8μm、9μm、10μm等。
第二步，如图14和图23所示，制作多条第二引线104，第二引线104优选可以用干法刻蚀进行图案化(CD Bias小)的金属材料，例如Ti、Ti/Al/Ti、Mo、Mo/Al/Mo等，厚度考虑走线电阻尽可能低的原则，例如可以设置Ti/Al/Ti的厚度为
Figure PCTCN2022118764-appb-000011
等。特别的，考虑后续基材层101的高温制作工艺，第二引线104需要对垫高结构108进行包裹。可选地，本实施例中第二引线104包括一体设置的第二引线部1041和第二连接部1042，第二连接部1042包裹垫高结构108，即垫高结构108在刚性基板112上的正投影位于第二连接部1042在刚性基板112上的正投影内。
第三步，如图24所示，在多条第二引线104所在层之上形成基材层101，基材层101可以为聚酰亚胺等柔性基底，其厚度需要与垫高结构108的厚度接近，例如基材层101的厚度比垫高结构108的厚度大0.5μm以内。由于基材层101的原药液具备流平特性，因此基材层101在垫高结构108之外的区域均平坦。之后可在基材层101上面沉积一层无机层109(buffer)，以隔绝水汽。
第四步，如图13和图25所示，在基材层101和无机层109对应垫高结构108的位置形成贯穿基材层101和无机层109的转接孔，之后在无机层109上制备多条第一引线103和多个第一转接电极105，第一转接电极105在刚性基板112上的正投影可以与第二连接部1042在刚性基板112上的正投影大致重合，即二者的正投影恰好重合，或在因制作工艺、测量等因素造成的误差范围内。可选地，多条第一引线103和多个第一转接电极105所在层的材料及厚度选择与多条第二引线104所在层的材料及厚度相同。
第五步，如图2和图26所示，在多条第一引线103和多个第一转接电极105所在层上制作多个焊盘102，作为最终的绑定焊盘。随后在每个焊盘102表面镀上一层防氧化层110，防氧化层110可以采用Sn或者Au等材料制作，防氧化层110的厚度0.1μm～0.5μm。可选地，采用对空间需求相对较低的减成电镀法制作多个焊盘102，焊盘102的厚度可以为3μm～10μm。
第六步，如图4所示，用激光剥离法(Laser Lift-Off，LLO)剥离刚性基板112，由于牺牲层113的存在，因此多条第二引线104和多个垫高结构108均可成功分离。
第七步，如图19所示，采用丝网印刷方式在基材层101的正反面均涂布阻焊层111(Soler Resin，SR)，基材层101之上的阻焊层111露出覆晶薄膜与显示面板(panel)进行绑定的第一绑定区(OLB lead)、与芯片(IC)进行绑定的第二绑定区(ILB lead)、以及与柔性电路板(FPC)进行绑定的第三绑定区(FOF lead)，基材层101下方的阻焊层111整面设置。在一些实施例中，可采用先涂布正面的阻焊层111，再将覆晶薄膜自玻璃基板上激光剥离(LLO)掉，最后制作反面的阻焊层111；在另一些实施例中，也可以先将覆晶薄膜自玻璃基板上激光剥离(LLO)掉，再制作正反两面的阻焊层111，在此不做限定。
至此完成了图19所示覆晶薄膜的制作。
基于上述第一步至第六步的相似步骤可制作图10所示的覆晶薄膜，不同之处在于：其一，图10中垫高结构108的形状与第二引线104的形状相同，且垫高结构108的正投影位于第二引线104的正投影内；其二，图10中无需单独制作第一引线103，而是可以在制作焊盘102的同时制作第一引线103，使得第一引线103与焊盘102同层、同材料设置，且无需制作第一转接电极105，焊盘102与第二连接部1042接触电连接，可选地，为防止第一引线103被氧化，还可在形成包裹焊盘102的防氧化层110的同时，形成包裹第一引线103的防氧化层110。
在一些实施例中，可基于以下步骤可实现图6所示覆晶薄膜的制作：
第一步，在刚性基板112(例如玻璃基板)上涂布牺牲层113(De-Bonding Layer，DBL)，牺牲层113的材料可以为聚酰亚胺体系，厚度可以为
Figure PCTCN2022118764-appb-000012
例如
Figure PCTCN2022118764-appb-000013
等。
第二步，如图27和图28所示，在牺牲层113上形成多条第二引线104，第二引线104包括第二走线部1041和第二连接部1042，第二引线104的层结构为3层金属结构，中间层必须为铜金属，而最上层/下层金属材料需是钼(Mo)、铝(Al)、钛(Ti)、钼/镍/钛(MTD)合金等可以用干刻工艺去除的材料，优选为Ti/Cu/Ti，其中从经济性考率，铜金属层M厚度可以为
Figure PCTCN2022118764-appb-000014
上金属层U、下金属层D的厚度优选不超过
Figure PCTCN2022118764-appb-000015
随后在多条第二引线104上形成基材层101和无机层109。
第三步，如图29所示，在第二连接部1042的位置制作转接孔，利用干刻工艺一次性实现对第二连接部1042位置的无机层109、基材层101、上金属层D的刻蚀，特别的，上金属层D必须完全去除，以保证后续可以进行铜金属电镀形成第二转接电极106。通过在第二转接电极106之前制作基材层101，有效避免了基材层101的高温工艺对第二转接电极106的氧化影响。
第四步，如图30和图31所示，采用电镀工艺在转接孔处形成第二转接电极106，将较深的转接孔填平，以保证后续制作的第一引线103所在层的平坦度，特别的，由于基材层101这一厚膜在干刻中为由无机层109的硬掩模刻蚀(Hardmask Etch)，因此该实施例的另一个结构特点在于转接孔内的第二转接电极106具有接近90°的坡度角。
第五步，如图32和图33所示，在无机层109上制备多条第一引线103和多个第一转接电极105，可选地，多条第一引线103和多个第一转接电极105所在层的材料及厚度选择与多条第二引线104所在层的材料及厚度相同。
第六步，如图34和图35所示，在多条第一引线103和多个第一转接电极105所在层上制作多个焊盘102，作为最终的绑定焊盘。随后在每个焊盘102表面镀上一层防氧化层110，防氧化层110可以采用Sn或者Au等材料制 作，防氧化层110的厚度0.1μm～0.5μm。可选地，采用对空间需求相对较低的减成电镀法制作多个焊盘102，焊盘102的厚度可以为3μm～10μm。
第七步，如图6所示，用激光剥离法(Laser Lift-Off，LLO)剥离刚性基板112，由于牺牲层113的存在，因此多条第二引线104和多个垫高结构108均可成功分离,至此获得了图6所示的覆晶薄膜。
可选地，还可参考图19所示覆晶薄膜制作方法中的第七步在图6所示覆晶薄膜的正反面制作阻焊层111，在此不再赘述。
在一些实施例中，可基于以下步骤可实现图8所示覆晶薄膜的制作：
第一步，在刚性基板112(例如玻璃基板)上涂布牺牲层113(De-Bonding Layer，DBL)，牺牲层113的材料可以为聚酰亚胺体系，厚度可以为
Figure PCTCN2022118764-appb-000016
例如
Figure PCTCN2022118764-appb-000017
等。
第二步，如图36和图37所示，在牺牲层113上形成多条第二引线104，第二引线104包括第二走线部1041和第二连接部1042，第二引线104优选可以用干法刻蚀进行图案化(CD Bias小)的金属材料，例如Ti、Ti/Al/Ti、Mo、Mo/Al/Mo等，厚度考虑走线电阻尽可能低的原则，例如可以设置Ti/Al/Ti的厚度为
Figure PCTCN2022118764-appb-000018
等。
第三步，如图38和图39所示，在第二引线104所在层上形成基材层101和无机层109，此步骤中基材层101与无机层109中尚未形成转接孔。之后在无机层109上形成同层、同材料设置的第一引线103和第一转接电极105，特别的，第一引线103的材料及结构可以与第二引线104的材料及结构相同。
第四步，如图40所示，在第二连接部1042的位置制作贯穿基材层101和无机层109的转接孔，利用干刻工艺一次性实现对第二连接部1042位置的无机层109、基材层101、上金属层D的刻蚀，特别的，上金属层D必须完全去除，以保证后续可以进行铜金属电镀形成第二转接电极106。通过在第二转接电极106之前制作基材层101，有效避免了基材层101的高温工艺对第二转接电极106的氧化影响。
第五步，如图41和图42所示，采用加成法电镀，制作填平转接孔的第二转接电极106，同时生成起绑定作用的焊盘102。
第六步，如图43和图44所示，制作第三转接电极107，将第一转接电极105与第二转接电极106进行连接。
第七步，可参考图19所示覆晶薄膜制作方法中的第六步激光剥离掉牺牲层113和刚性基板112，至此获得了图8所示的覆晶薄膜。可选地，还可参考图19所示覆晶薄膜制作方法中的第七步在图8所示覆晶薄膜的正反面制作阻焊层111，在此不再赘述。
图12所示覆晶薄膜示出两层第二引线104，为便于说明，以下制作方法中将第一次制作的第二引线104标记为104A，将第二次制作的第二引线104标记为104B。具体地，可基于以下步骤实现图12所示覆晶薄膜的制作：
第一步，在刚性基板112(例如玻璃基板)上涂布牺牲层113(De-Bonding Layer，DBL)，牺牲层113的材料可以为聚酰亚胺体系，厚度可以为
Figure PCTCN2022118764-appb-000019
例如
Figure PCTCN2022118764-appb-000020
等。
第二步，如图45和图46所示，在牺牲层113上第一次形成多条第二引线104A，该层第二引线104A包括第二走线部1041和第二连接部1042，第二引线104A的层结构为3层金属结构，中间层必须为铜金属，而最上层/下层金属材料需是钼(Mo)、铝(Al)、钛(Ti)、钼/镍/钛(MTD)合金等可以用干刻工艺去除的材料，优选为Ti/Cu/Ti，其中从经济性考率，铜金属层M厚度可以为
Figure PCTCN2022118764-appb-000021
上金属层U、下金属层D的厚度优选不超过
Figure PCTCN2022118764-appb-000022
第三步，如图47所示，第二引线104A所在层上形成基材层101和无机层109，并在第二连接部1042的位置制作转接孔，利用干刻工艺一次性实现对第二连接部1042位置的无机层109、基材层101、上金属层D的刻蚀，特别的，上金属层D必须完全去除，以保证后续可以进行铜金属电镀形成第二转接电极106。通过在第二转接电极106之前制作基材层101，有效避免了基材层101的高温工艺对第二转接电极106的氧化影响。
第四步，如图48和图49所示，采用电镀工艺在转接孔处形成第二转接电极106，将较深的转接孔填平，以保证后续制作的第一引线103所在层的平坦度，特别的，由于基材层101这一厚膜在干刻中为由无机层109的硬掩模刻蚀(Hardmask Etch)，因此该实施例的另一个结构特点在于转接孔内的第二转接电极106具有接近90°的坡度角。
第五步，如图50和图51所示，在第四步制作的第一转接电极106所在层上形成多条第二引线104B、以及与第二转接电极106电连接的过渡电极1042’，第二引线104B的结构、材料可以与第二引线104A的结构、材料相同，在此不做赘述。
第六步，如图52所示，可参考第三步的方法在第二引线104B所在层上依次形成基材层101和无机层109，并形成贯穿基材层101和无机层109的转接孔，且转接孔位置的过渡电极1042’的上层金属被同时刻蚀掉，以保证后续可以进行铜金属电镀形成第二转接电极106。
第七步，如图53和图54所示，可参考第三步的方法在转接孔处形成坡度角近似90°的第二转接电极106。
第八步，如图55和图56所示，在第七步的第二转接电极106上制备多条第一引线103和多个第一转接电极105，可选地，多条第一引线103和多个第一转接电极105所在层的材料及厚度选择与多条第二引线104A、104B所在层的材料及厚度相同。
第九步，如图57和图58所示，在多条第一引线103和多个第一转接电极105所在层上制作多个焊盘102，作为最终的绑定焊盘。随后在每个焊盘102表面镀上一层防氧化层110，防氧化层110可以采用Sn或者Au等材料制作，防氧化层110的厚度0.1μm～0.5μm。可选地，采用对空间需求相对较低的减成电镀法制作多个焊盘102，焊盘102的厚度可以为3μm～10μm。
第十步，用激光剥离法(Laser Lift-Off，LLO)剥离刚性基板112，由于牺牲层113的存在，因此多条第二引线104均可成功分离,至此获得了图12所示的覆晶薄膜。
可选地，还可参考图19所示覆晶薄膜制作方法中的第七步在图12所示覆晶薄膜的正反面制作阻焊层111，在此不再赘述。
需要说明的是，以上仅以第一引线103、第二引线104共两层或三层布线进行了示例说明，在具体实施时，第一引线103、第二引线104还可以包括四层以上，且在布线为四层以上的情况下，第一引线103、第二引线104的设置方式可参见图2至图12，在图2至图12中的引线设置方案不冲突的前提下，可将图2至图12的实施方式自身或任意两者以上进行组合。例如图59示出了图4所示覆晶薄膜中的引线设置方式的自身组合，可选地，图59中各膜层的制作方法可参考图4所示覆晶薄膜中相同膜层的制作方法，例如，图59中第二引线104的制作方法可参考图4所示覆晶薄膜中第二引线104的制作方法，在此不做赘述。
另外，在本公开实施例提供的上述制作方法中，形成各层结构涉及到的构图工艺，不仅可以包括沉积、光刻胶涂覆、掩模板掩模、曝光、显影、刻蚀、光刻胶剥离等部分或全部的工艺过程，还可以包括其他工艺过程，具体以实际制作过程中形成所需构图的图形为准，在此不做限定。例如，在显影之后和刻蚀之前还可以包括后烘工艺。
其中，沉积工艺可以为化学气相沉积法、等离子体增强化学气相沉积法或物理气相沉积法，在此不做限定；掩膜工艺中所用的掩膜板可以为半色调掩膜板(Half Tone Mask)、单缝衍射掩模板(Single Slit Mask)或灰色调掩模板(Gray Tone Mask)，在此不做限定；刻蚀可以为干法刻蚀或者湿法刻蚀，在此不做限定。
基于同一发明构思，本公开实施例提供了一种显示装置，包括本公开实施例提供的上述覆晶薄膜。由于该显示装置解决问题的原理与上述覆晶薄膜解决问题的原理相似，因此，该显示装置的实施可以参见上述覆晶薄膜的实施例，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述显示装置中，如图60所示，可以包括覆晶薄膜001、显示基板002、驱动芯片IC和柔性电路板FPC，可 选地，显示基板002与覆晶薄膜001的第一绑定区BA 1电连接，柔性电路板FPC与覆晶薄膜001的第二绑定区BA 2电连接，驱动芯片IC与覆晶薄膜001的第三绑定区BA 3电连接。
在一些实施例中，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。可选地，本公开实施例提供的上述显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (30)

  1. 一种覆晶薄膜，其中，包括：
    至少一个基材层；
    多个焊盘，位于所述至少一个基材层之上；
    多条第一引线，位于所述至少一个基材层之上，所述多条第一引线与部分所述焊盘电连接；
    多条第二引线，位于每个所述基材层远离所述多个焊盘所在层的一侧，所述多条第二引线与其余所述焊盘电连接。
  2. 如权利要求1所述的覆晶薄膜，其中，所述多条第一引线位于所述至少一个基材层与所述多个焊盘所在层之间。
  3. 如权利要求2所述的覆晶薄膜，其中，所述第一引线包括一体设置的第一走线部和第一连接部，所述第一连接部与所述焊盘接触电连接。
  4. 如权利要求3所述的覆晶薄膜，其中，所述第一连接部在所述基材层上的正投影与其电连接的所述焊盘在所述基材层上的正投影大致重合。
  5. 如权利要求3或4所述的覆晶薄膜，其中，还包括多个第一转接电极，所述第一转接电极电连接在所述第二引线与所述焊盘之间。
  6. 如权利要求5所述的覆晶薄膜，其中，所述多个第一转接电极与所述多条第一引线同层、同材料设置。
  7. 如权利要求6所述的覆晶薄膜，其中，所述焊盘在所述基材层上的正投影位于与其电连接的所述第一转接电极在所述基材层上的正投影内。
  8. 如权利要求6或7所述的覆晶薄膜，其中，所述第二引线包括一体设置的第二走线部和第二连接部，所述第二连接部通过所述第一转接电极与所述焊盘电连接。
  9. 如权利要求8所述的覆晶薄膜，其中，所述第二连接部与所述第一转接电极接触电连接。
  10. 如权利要求9所述的覆晶薄膜，其中，还包括位于所述多条第二引 线所在层远离所述多个焊盘所在层一侧的多个垫高结构，所述垫高结构与所述第二连接部电连接的所述焊盘在所述基材层上的正投影大致重合。
  11. 如权利要求10所述的覆晶薄膜，其中，所述垫高结构在所述基材层上的正投影位于所述第二连接部在所述基材层上的正投影内。
  12. 如权利要求10或11所述的覆晶薄膜，其中，在垂直于所述基材层的方向上，所述基材层超出所述垫高结构的距离在0.5μm以内。
  13. 如权利要求8所述的覆晶薄膜，其中，还包括多个第二转接电极，所述第二转接电极嵌入所述基材层，所述第一转接电极通过所述第二转接电极与所述第二连接部电连接。
  14. 如权利要求13所述的覆晶薄膜，其中，还包括多个第三转接电极，所述第三转接电极与所述第一转接电极同层设置，所述第三转接电极连接在所述第一转接电极与所述第二转接电极之间。
  15. 如权利要求1所述的覆晶薄膜，其中，所述第一引线与所述焊盘一体设置。
  16. 如权利要求15所述的覆晶薄膜，其中，所述第二引线包括一体设置的第二走线部和第二连接部，所述第二连接部与所述焊盘接触电连接。
  17. 如权利要求16所述的覆晶薄膜，其中，还包括位于所述多条第二引线所在层远离所述多个焊盘所在层一侧的多个垫高结构，所述垫高结构在所述基材层上的正投影形状与所述第二引线在所述衬底基板上的正投影形状大致相同，且所述垫高结构在所述基材层上的正投影位于所述第二引线在所述衬底基板上的正投影内。
  18. 如权利要求11～13、17任一项所述的覆晶薄膜，其中，所述垫高结构的材料与所述焊盘的材料相同。
  19. 如权利要求1～18任一项所述的覆晶薄膜，其中，所述第二引线在所述基材层上的正投影与所述第一引线在所述基材层上的正投影互不交叠。
  20. 如权利要求1～19任一项所述的覆晶薄膜，其中，所述多个焊盘呈阵列排布，任意相邻两行所述焊盘沿预设方向局部错开设置。
  21. 一种如权利要求1～20任一项所述的覆晶薄膜的制作方法，其中，包括：
    提供一个刚性基板，并在所述刚性基板上形成牺牲层；
    在所述牺牲层上依次形成至少一个基材层、以及多条第一引线和多个焊盘，且在每次形成一个所述基材层之前，分别形成多条第二引线；其中，所述多条第一引线与部分所述焊盘电连接，所述多条第二引线与其余所述焊盘电连接；
    去除所述牺牲层，使得所述刚性基板与所述牺牲层一同剥离，获得所述覆晶薄膜。
  22. 如权利要求21所述的制作方法，其中，形成多条第一引线和多个焊盘，具体包括：
    采用一次构图工艺同时形成多条第一引线和多个焊盘，或者，采用两次构图工艺依次形成多条第一引线和多个焊盘。
  23. 如权利要求21或22所述的制作方法，其中，在每次形成一个基材层之后，且在形成多条第一引线之前，还包括：
    对所述基材层和所述第二引线进行刻蚀，使得所述基材层暴露出所述第二引线的铜层。
  24. 如权利要求23所述的制作方法，其中，在每次对所述基材层和所述第二引线进行刻蚀，使得所述基材层暴露出所述第二引线的铜层之后，且在形成多条第一引线之前，还包括：
    在暴露出的所述第二引线的铜层上形成第二转接电极。
  25. 如权利要求23所述的制作方法，其中，在形成多个焊盘的同时，还包括：
    在最后一次对所述基材层和所述第二引线进行刻蚀后，暴露出的所述第二引线的铜层上形成第二转接电极。
  26. 如权利要求24或25所述的制作方法，其中，在形成多条第一引线的同时，还包括：
    形成第一转接电极，所述第二转接电极通过所述第一转接电极与所述第二引线对应的所述焊盘电连接。
  27. 如权利要求26所述的制作方法，其中，在形成多个焊盘之后，还包括：
    形成第三转接电极，使得所述第二转接电极依次通过所述第三转接电极、所述第一转接电极与所述第二引线对应的所述焊盘电连接。
  28. 如权利要求21或22所述的制作方法，其中，在首次形成多条第二引线之前，还包括：
    在所述牺牲层上形成多个垫高结构，所述垫高结构在所述刚性基板上的正投影与所述第二引线电连接的所述焊盘在所述刚性基板上的正投影大致重合。
  29. 如权利要求21或22所述的制作方法，其中，在首次形成多条第二引线之前，还包括：
    在所述牺牲层上形成多个垫高结构，所述垫高结构在所述基材层上的正投影形状与所述第二引线在所述衬底基板上的正投影形状大致相同，且所述垫高结构在所述基材层上的正投影位于所述第二引线在所述衬底基板上的正投影内。
  30. 一种显示装置，其中，包括如权利要求1～20任一项所述的覆晶薄膜。
PCT/CN2022/118764 2022-09-14 2022-09-14 覆晶薄膜、其制作方法及显示装置 WO2024055205A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205142A (ja) * 2007-02-20 2008-09-04 Sumitomo Metal Mining Package Materials Co Ltd Ｃｏｆ用配線基板とその製造方法、並びに半導体装置
CN108417151A (zh) * 2018-02-02 2018-08-17 武汉华星光电半导体显示技术有限公司 显示装置及其覆晶薄膜结构
CN110111682A (zh) * 2019-04-10 2019-08-09 深圳市华星光电技术有限公司 覆晶薄膜及显示装置
CN110391273A (zh) * 2018-04-17 2019-10-29 三星显示有限公司 显示装置
CN110580855A (zh) * 2019-09-17 2019-12-17 合肥鑫晟光电科技有限公司 覆晶薄膜、覆晶薄膜基板及其制作方法、显示装置
CN113517252A (zh) * 2020-04-09 2021-10-19 南茂科技股份有限公司 薄膜覆晶封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205142A (ja) * 2007-02-20 2008-09-04 Sumitomo Metal Mining Package Materials Co Ltd Ｃｏｆ用配線基板とその製造方法、並びに半導体装置
CN108417151A (zh) * 2018-02-02 2018-08-17 武汉华星光电半导体显示技术有限公司 显示装置及其覆晶薄膜结构
CN110391273A (zh) * 2018-04-17 2019-10-29 三星显示有限公司 显示装置
CN110111682A (zh) * 2019-04-10 2019-08-09 深圳市华星光电技术有限公司 覆晶薄膜及显示装置
CN110580855A (zh) * 2019-09-17 2019-12-17 合肥鑫晟光电科技有限公司 覆晶薄膜、覆晶薄膜基板及其制作方法、显示装置
CN113517252A (zh) * 2020-04-09 2021-10-19 南茂科技股份有限公司 薄膜覆晶封装结构

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