WO2024053452A1 - マルチレベルインバータ - Google Patents

マルチレベルインバータ Download PDF

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Publication number
WO2024053452A1
WO2024053452A1 PCT/JP2023/030963 JP2023030963W WO2024053452A1 WO 2024053452 A1 WO2024053452 A1 WO 2024053452A1 JP 2023030963 W JP2023030963 W JP 2023030963W WO 2024053452 A1 WO2024053452 A1 WO 2024053452A1
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Prior art keywords
gate drivers
switching element
voltage
vector
inverter
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PCT/JP2023/030963
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English (en)
French (fr)
Japanese (ja)
Inventor
裕一 中村
アナンタ ヘガデ
朝実良 鈴木
康弘 新井
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to JP2024545577A priority Critical patent/JPWO2024053452A1/ja
Priority to EP23862991.9A priority patent/EP4586489A4/en
Priority to CN202380059840.2A priority patent/CN119731927A/zh
Priority to US19/106,080 priority patent/US20260081539A1/en
Publication of WO2024053452A1 publication Critical patent/WO2024053452A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H02M7/53876—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times

Definitions

  • the present disclosure relates to a multilevel inverter, and more particularly, to a multilevel inverter with a bootstrap circuit.
  • Patent Document 1 discloses a three-phase voltage type PWM inverter circuit using a bootstrap circuit.
  • a three-phase voltage type PWM inverter circuit includes six switching elements, six gate drive circuits, a microcomputer, a main DC power supply, and three bootstraps. It has a circuit.
  • Patent Document 1 discloses that by giving a predetermined switching pattern to each phase of a three-phase inverter, a desired voltage vector is obtained and supplied to the load, and a control voltage is supplied by a bootstrap circuit for each phase.
  • An inverter control method is disclosed.
  • the bootstrap circuit can charge a voltage vector selected during a period in which the bootstrap circuit of any phase maintains a discharged state and does not affect the output voltage at predetermined intervals. Switching control is performed to replace it with a voltage vector.
  • Patent Document 1 The inverter control method disclosed in Patent Document 1 is a technology related to two-level inverters, and cannot be applied to multi-level inverters.
  • An object of the present disclosure is to provide a multilevel inverter that can suppress voltage drop in a bootstrap circuit.
  • a multilevel inverter includes a DC power supply section, a plurality of inverter circuits, and a control device.
  • the DC power supply section has a positive electrode, a negative electrode, and an intermediate potential point.
  • the plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply section.
  • the control device controls the plurality of inverter circuits.
  • Each of the plurality of inverter circuits includes a switching circuit, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode.
  • the first switching element, the second switching element, the third switching element, and the fourth switching element are connected from the positive electrode side to the negative electrode side.
  • the element and the fourth switching element are connected in series so as to be lined up in this order.
  • the first diode is connected in antiparallel to the first switching element.
  • the second diode is connected in antiparallel to the second switching element.
  • the third diode is connected in antiparallel to the third switching element.
  • the fourth diode is connected in antiparallel to the fourth switching element.
  • the fifth diode has a cathode connected to a first connection point between the first switching element and the second switching element, and an anode connected to the intermediate potential point.
  • the sixth diode has an anode connected to a second connection point between the third switching element and the fourth switching element, and a cathode connected to the intermediate potential point.
  • the control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, and a plurality of second gate drivers. It has a bootstrap circuit, a plurality of third bootstrap circuits, a power supply section, and a control section.
  • the plurality of first gate drivers drive the first switching elements of each of the plurality of inverter circuits.
  • the plurality of second gate drivers drive the second switching elements of each of the plurality of inverter circuits.
  • the plurality of third gate drivers drive the third switching elements of each of the plurality of inverter circuits.
  • the plurality of fourth gate drivers drive the fourth switching elements of each of the plurality of inverter circuits.
  • the plurality of first bootstrap circuits correspond one-to-one to the plurality of first gate drivers and supply voltage to the corresponding first gate drivers.
  • the plurality of second bootstrap circuits correspond one-to-one to the plurality of second gate drivers and supply voltage to the corresponding second gate drivers.
  • the plurality of third bootstrap circuits correspond one-to-one to the plurality of third gate drivers and supply voltage to the corresponding third gate drivers.
  • the power supply unit supplies voltage to the plurality of fourth gate drivers.
  • the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers.
  • the control unit selects a plurality of voltage vectors adjacent to the command voltage vector from among a group of voltage vectors, each of which is determined by a combination of potential levels at a third connection point between the second switching element and the third switching element of the plurality of inverter circuits. Select the voltage vector of Each of the group of voltage vectors is determined by a combination of potential levels at the third connection point between the second switching element and the third switching element of the plurality of inverter circuits.
  • the control unit controls one first voltage vector among two first voltage vectors having a reference size and closest to the command voltage vector among the plurality of voltage vectors to the one of the first voltage vectors of the plurality of inverter circuits.
  • the control unit is configured to control a voltage vector other than the first voltage vector among the plurality of voltage vectors, a remaining first voltage vector of the two first voltage vectors, the zero vector, and the second voltage vector.
  • the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers within a predetermined control period so that the composite vector of the plurality of gate drivers matches the command voltage vector. Control the gate driver.
  • the multilevel inverter includes a DC power supply, a plurality of inverter circuits, and a control device.
  • the DC power supply section has a positive electrode, a negative electrode, and an intermediate potential point.
  • the plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply section.
  • the control device controls the plurality of inverter circuits.
  • Each of the plurality of inverter circuits includes a switching circuit, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, and a sixth diode.
  • the first switching element, the second switching element, the third switching element, and the fourth switching element are connected from the positive electrode side to the negative electrode side.
  • the element and the fourth switching element are connected in series so as to be lined up in this order.
  • the first diode is connected in antiparallel to the first switching element.
  • the second diode is connected in antiparallel to the second switching element.
  • the third diode is connected in antiparallel to the third switching element.
  • the fourth diode is connected in antiparallel to the fourth switching element.
  • the fifth diode has a cathode connected to a first connection point between the first switching element and the second switching element, and an anode connected to the intermediate potential point.
  • the sixth diode has an anode connected to a second connection point between the third switching element and the fourth switching element, and a cathode connected to the intermediate potential point.
  • the control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of first bootstrap circuits, and a plurality of second gate drivers. It has a bootstrap circuit, a plurality of third bootstrap circuits, a power supply section, and a control section.
  • the plurality of first gate drivers drive the first switching elements of each of the plurality of inverter circuits.
  • the plurality of second gate drivers drive the second switching elements of each of the plurality of inverter circuits.
  • the plurality of third gate drivers drive the third switching elements of each of the plurality of inverter circuits.
  • the plurality of fourth gate drivers drive the fourth switching elements of each of the plurality of inverter circuits.
  • the plurality of first bootstrap circuits correspond one-to-one to the plurality of first gate drivers and supply voltage to the corresponding first gate drivers.
  • the plurality of second bootstrap circuits correspond one-to-one to the plurality of second gate drivers and supply voltage to the corresponding second gate drivers.
  • the plurality of third bootstrap circuits correspond one-to-one to the plurality of third gate drivers and supply voltage to the corresponding third gate drivers.
  • the power supply unit supplies voltage to the plurality of fourth gate drivers.
  • the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers.
  • the control unit selects a plurality of voltage vectors adjacent to the command voltage vector from among a group of voltage vectors, each of which is determined by a combination of potential levels at a third connection point between the second switching element and the third switching element of the plurality of inverter circuits. Select the voltage vector of Each of the group of voltage vectors is determined by a combination of potential levels at the third connection point between the second switching element and the third switching element of the plurality of inverter circuits.
  • the control unit controls a first voltage vector having a reference size and closest to the command voltage vector among the plurality of voltage vectors to the second switching element and the third switching element of the plurality of inverter circuits. a zero vector of a combination in which the potential level of the third connection point with the negative electrode is the potential of the negative electrode, and a second voltage vector having the same direction as the first voltage vector and twice the size of the first voltage vector, Replace with The control unit controls a predetermined voltage vector so that a composite vector of voltage vectors other than the first voltage vector among the plurality of voltage vectors, the zero vector, and the second voltage vector matches the command voltage vector.
  • the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers are controlled within a control period of.
  • a multilevel inverter includes a DC power supply section, a plurality of inverter circuits, and a control device.
  • the DC power supply section has a positive electrode, a negative electrode, and an intermediate potential point.
  • the plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply section.
  • the control device controls the plurality of inverter circuits.
  • Each of the plurality of inverter circuits includes a first switching element, a second switching element, a third switching element, a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode.
  • the first diode, the second diode, the third diode, and the fourth diode are connected in antiparallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. ing.
  • the first switching element and the second switching element are connected in series such that the first switching element and the second switching element are arranged in this order from the positive electrode side to the negative electrode side.
  • a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and the output point.
  • the output point is a connection point between the first switching element and the second switching element.
  • the control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply section, and a control section. and has.
  • the plurality of first gate drivers drive the first switching elements of each of the plurality of inverter circuits.
  • the plurality of second gate drivers drive the second switching elements of each of the plurality of inverter circuits.
  • the plurality of third gate drivers drive the third switching elements of each of the plurality of inverter circuits.
  • the plurality of fourth gate drivers drive the fourth switching elements of each of the plurality of inverter circuits.
  • the plurality of bootstrap circuits correspond one-to-one to the plurality of first gate drivers, and supply voltage to the corresponding first gate drivers.
  • the power supply unit supplies voltage to the plurality of second gate drivers and the plurality of third gate drivers.
  • the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers.
  • the control unit selects a plurality of voltage vectors adjacent to the command voltage vector from among the group of voltage vectors. Each of the group of voltage vectors is determined by a combination of potential levels of the plurality of connection points in the plurality of inverter circuits.
  • the control unit controls one of two first voltage vectors having a reference size and closest to the command voltage vector among the plurality of voltage vectors to the plurality of voltage vectors in the plurality of inverter circuits.
  • the voltage vector is replaced with a zero vector of a combination in which the potential level of the connection point is the potential of the negative electrode, and a second voltage vector having the same direction as the first voltage vector and twice the size of the first voltage vector.
  • the control unit controls a predetermined voltage vector so that a composite vector of voltage vectors other than the first voltage vector among the plurality of voltage vectors, the zero vector, and the second voltage vector matches the command voltage vector.
  • the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers are controlled within a control period of.
  • the multilevel inverter includes a DC power supply, a plurality of inverter circuits, and a control device.
  • the DC power supply section has a positive electrode, a negative electrode, and an intermediate potential point.
  • the plurality of inverter circuits are connected between the positive electrode and the negative electrode of the DC power supply section.
  • the control device controls the plurality of inverter circuits.
  • Each of the plurality of inverter circuits includes a first switching element, a second switching element, a third switching element, a fourth switching element, and a first diode, a second diode, a third diode, and a fourth diode.
  • the first diode, the second diode, the third diode, and the fourth diode are connected in antiparallel to the first switching element, the second switching element, the third switching element, and the fourth switching element, respectively. ing.
  • the first switching element and the second switching element are connected in series such that the first switching element and the second switching element are arranged in this order from the positive electrode side to the negative electrode side.
  • a series circuit of the third switching element and the fourth switching element is connected between the intermediate potential point and the output point.
  • the output point is a connection point between the first switching element and the second switching element.
  • the control device includes a plurality of first gate drivers, a plurality of second gate drivers, a plurality of third gate drivers, a plurality of fourth gate drivers, a plurality of bootstrap circuits, a power supply section, and a control section. and has.
  • the plurality of first gate drivers drive the first switching elements of each of the plurality of inverter circuits.
  • the plurality of second gate drivers drive the second switching elements of each of the plurality of inverter circuits.
  • the plurality of third gate drivers drive the third switching elements of each of the plurality of inverter circuits.
  • the plurality of fourth gate drivers drive the fourth switching elements of each of the plurality of inverter circuits.
  • the plurality of bootstrap circuits correspond one-to-one to the plurality of first gate drivers, and supply voltage to the corresponding first gate drivers.
  • the power supply unit supplies voltage to the plurality of second gate drivers and the plurality of third gate drivers.
  • the control unit controls the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers.
  • the control unit selects a plurality of voltage vectors adjacent to the command voltage vector from among the group of voltage vectors. Each of the group of voltage vectors is determined by a combination of potential levels of the plurality of connection points in the plurality of inverter circuits.
  • the control unit controls each of two first voltage vectors having a reference size and closest to the command voltage vector among the plurality of voltage vectors to one of the plurality of connection points in the plurality of inverter circuits.
  • the voltage vector is replaced with a combination of zero vectors whose potential level is the potential of the negative electrode, and a second voltage vector having the same direction as the first voltage vector and twice the size of the first voltage vector.
  • the control unit controls a predetermined voltage vector so that a composite vector of voltage vectors other than the first voltage vector among the plurality of voltage vectors, the zero vector, and the second voltage vector matches the command voltage vector.
  • the plurality of first gate drivers, the plurality of second gate drivers, the plurality of third gate drivers, and the plurality of fourth gate drivers are controlled within a control period of.
  • FIG. 1 is a circuit diagram of a system including a multilevel inverter according to a first embodiment.
  • FIG. 2 is an explanatory diagram of the current path when the switching circuit is in the first switching state in the multilevel inverter same as above.
  • FIG. 3 is an explanatory diagram of a discharging path and a charging path when the switching circuit is in the first switching state in the multilevel inverter same as above.
  • FIG. 4 is an explanatory diagram of the current path when the switching circuit is in the second switching state in the above multilevel inverter.
  • FIG. 5 is an explanatory diagram of a discharging path and a charging path when the switching circuit is in the second switching state in the multilevel inverter same as above.
  • FIG. 6 is an explanatory diagram of the current path when the switching circuit is in the third switching state in the multilevel inverter same as above.
  • FIG. 7 is an explanatory diagram of the discharging path and the charging path when the switching circuit is in the third switching state in the multilevel inverter same as above.
  • FIG. 8 is an explanatory diagram of voltage command values for each phase in the multilevel inverter same as above.
  • FIG. 9 is an explanatory diagram of a group of voltage vectors regarding the multilevel inverter.
  • FIG. 10 is a more detailed explanatory diagram of a group of voltage vectors for the multilevel inverter.
  • FIG. 11 is a vector diagram for explaining the operation of the control section in the multilevel inverter.
  • FIG. 12A is an explanatory diagram of a command voltage vector and a first voltage vector regarding the multilevel inverter same as above.
  • FIG. 12B is an explanatory diagram of a command voltage vector, a zero vector, and a second voltage vector regarding the multilevel inverter same as above.
  • FIG. 13 is a time chart of the switching state of each phase of the multilevel inverter according to the comparative example.
  • FIG. 14 is a time chart of the on/off states of the first to fourth switching elements of the multilevel inverter according to the comparative example.
  • FIG. 15 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the multilevel inverter according to the first embodiment. .
  • FIG. 16 is a time chart of the on/off states of the first to fourth switching elements when the inverter circuit is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the same multilevel inverter as described above.
  • FIG. 17 is a time chart of the switching states of each phase of the multilevel inverter according to the comparative example.
  • FIG. 18 is a time chart of the on/off states of the first to fourth switching elements of the multilevel inverter according to the comparative example.
  • FIG. 19 is a time chart of the switching state of each phase when the inverter circuit of each phase is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the multilevel inverter according to the first embodiment. .
  • FIG. 20 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 21 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the multilevel inverter according to the second embodiment.
  • FIG. 22 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 21 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the multilevel inverter according to the second embodiment.
  • FIG. 22 is a time chart of the on/off states of the first to
  • FIG. 23 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the same multilevel inverter as described above.
  • FIG. 24 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 25 is a circuit diagram of a system including a multilevel inverter according to a modification.
  • FIG. 26 is a circuit diagram of a system including a multilevel inverter according to the third embodiment.
  • FIG. 27 is an explanatory diagram of a current path when the switching circuit is in the first switching state in the above multilevel inverter.
  • FIG. 28 is an explanatory diagram of the discharge path when the switching circuit is in the first switching state in the multilevel inverter same as above.
  • FIG. 29 is an explanatory diagram of the current path when the switching circuit is in the second switching state in the above multilevel inverter.
  • FIG. 30 is an explanatory diagram of the discharge path when the switching circuit is in the second switching state in the multilevel inverter same as above.
  • FIG. 31 is an explanatory diagram of the current path when the switching circuit is in the third switching state in the multilevel inverter same as above.
  • FIG. 32 is an explanatory diagram of the discharging path and the charging path when the switching circuit is in the third switching state in the multilevel inverter same as above.
  • FIG. 33 is an explanatory diagram of the discharge path when the switching circuit is in the second switching state in the multilevel inverter same as above.
  • FIG. 34 is an explanatory diagram of voltage command values for each phase in the multilevel inverter same as above.
  • FIG. 35 is an explanatory diagram of a group of voltage vectors regarding the multilevel inverter same as above.
  • FIG. 36 is a more detailed explanatory diagram of a group of voltage vectors regarding the multilevel inverter.
  • FIG. 37 is a vector diagram for explaining the operation of the control section in the multilevel inverter same as above.
  • FIG. 38A is an explanatory diagram of a command voltage vector and a first voltage vector regarding the multilevel inverter same as above.
  • FIG. 38B is an explanatory diagram of a command voltage vector, a zero vector, and a second voltage vector regarding the multilevel inverter same as above.
  • FIG. 39 is a time chart of the switching state of each phase of the multilevel inverter according to the comparative example.
  • FIG. 40 is a time chart of the on/off states of the first to fourth switching elements of the multilevel inverter according to the comparative example.
  • FIG. 41 is a time chart of the switching state of each phase when the inverter circuit of each phase is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the multilevel inverter according to the third embodiment. .
  • FIG. 42 is a time chart of the on/off states of the first to fourth switching elements when the inverter circuit is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the same multilevel inverter as described above.
  • FIG. 43 is a time chart of the switching state of each phase of the multilevel inverter according to the comparative example.
  • FIG. 44 is a time chart of the on/off states of the first to fourth switching elements of the multilevel inverter according to the comparative example.
  • FIG. 45 is a time chart of the switching state of each phase when the inverter circuit of each phase is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the multilevel inverter according to the third embodiment. .
  • FIG. 42 is a time chart of the on/off states of the first to fourth switching elements when the inverter circuit is controlled by replacing the first voltage vector with a zero vector and a second voltage vector in the multilevel inverter according to the third embodiment. .
  • FIG. 46 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 47 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the multilevel inverter according to the fourth embodiment.
  • FIG. 48 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 48 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 49 is a time chart of the switching state of each phase when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit of each phase in the same multilevel inverter as described above.
  • FIG. 50 is a time chart of the on/off states of the first to fourth switching elements when the first voltage vector is replaced with a zero vector and a second voltage vector to control the inverter circuit in the same multilevel inverter as described above.
  • FIG. 51 is a circuit diagram of a system including a multilevel inverter according to Embodiment 5.
  • FIG. 52 is a circuit diagram of a system including a multilevel inverter according to Embodiment 6.
  • FIG. 53 is a circuit diagram of a system including a multilevel inverter according to Embodiment 7.
  • FIG. 54 is a circuit diagram of a system including a multilevel inverter according to Embodiment 8.
  • the multilevel inverter 100 includes, for example, as shown in FIG. 1, a DC power supply section 3, a plurality of (for example, three) inverter circuits 1, and a control device 6.
  • the DC power supply section 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1.
  • the plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply section 3.
  • the control device 6 controls the plurality of inverter circuits 1.
  • the multilevel inverter 100 is a diode clamp type three-level, three-phase inverter.
  • each of the plurality of inverter circuits 1 has an output terminal 41.
  • an AC load RA1 is connected to a plurality of output terminals (AC terminals) 41.
  • AC load RA1 is, for example, a three-phase motor.
  • one of the plurality of inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage
  • another one is an inverter circuit 1V that outputs a V-phase voltage
  • the remaining One is an inverter circuit 1W that outputs a W-phase voltage.
  • Each of the plurality of inverter circuits 1 includes a switching circuit 10, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. Moreover, each of the plurality of inverter circuits 1 includes a fifth diode D5 and a sixth diode D6. In the multilevel inverter 100, the potential at the intermediate potential point M1 is clamped by the fifth diode D5 and the sixth diode D6 of each inverter circuit 1.
  • each switching circuit 10 the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected from the positive electrode P1 side to the negative electrode N1 side. , the third switching element Q3, and the fourth switching element Q4 are connected in series in this order.
  • the first diode D1 is connected in antiparallel to the first switching element Q1.
  • the second diode D2 is connected in antiparallel to the second switching element Q2.
  • the third diode D3 is connected in antiparallel to the third switching element Q3.
  • the fourth diode D4 is connected in antiparallel to the fourth switching element Q4.
  • the fifth diode D5 has a cathode connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2, and an anode connected to the intermediate potential point M1.
  • the sixth diode D6 has an anode connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4, and a cathode connected to the intermediate potential point M1.
  • the control device 6 includes a plurality of (for example, three) first gate drivers 61, a plurality of (for example, three) second gate drivers 62, a plurality of (for example, three) third gate drivers 63, A plurality of (for example, three) fourth gate drivers 64 are included.
  • the control device 6 also includes a plurality of (for example, three) first bootstrap circuits 71, a plurality of (for example, three) second bootstrap circuits 72, and a plurality of (for example, three) third bootstrap circuits 71, and a plurality of (for example, three) third bootstrap circuits 71. It has a strap circuit 73, a power supply section 9, and a control section 60.
  • the plurality of first gate drivers 61 drive the first switching elements Q1 of each of the plurality of inverter circuits 1.
  • the plurality of second gate drivers 62 drive the second switching elements Q2 of each of the plurality of inverter circuits 1.
  • the plurality of third gate drivers 63 drive the third switching elements Q3 of each of the plurality of inverter circuits 1.
  • the plurality of fourth gate drivers 64 drive the fourth switching elements Q4 of each of the plurality of inverter circuits 1.
  • the plurality of first bootstrap circuits 71 correspond to the plurality of first gate drivers 61 on a one-to-one basis.
  • the plurality of first bootstrap circuits 71 supply voltage to the corresponding first gate drivers 61.
  • the plurality of second bootstrap circuits 72 correspond to the plurality of second gate drivers 62 on a one-to-one basis.
  • the plurality of second bootstrap circuits 72 supply voltages to the corresponding second gate drivers 62.
  • the plurality of third bootstrap circuits 73 correspond to the plurality of third gate drivers 63 on a one-to-one basis.
  • the plurality of third bootstrap circuits 73 supply voltage to the corresponding third gate drivers 63.
  • the power supply section 9 supplies voltage to the plurality of fourth gate drivers 64.
  • the control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 , and a plurality of fourth gate drivers 64 .
  • the DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2.
  • a first capacitor C1 and a second capacitor C2 are connected in series.
  • the first end of the first capacitor C1 is connected to the first DC terminal 31
  • the second end of the first capacitor C1 is connected to the first end of the second capacitor C2
  • the first end of the first capacitor C1 is connected to the first end of the second capacitor C2.
  • the second end of the two capacitor C2 is connected to the second DC terminal 32.
  • the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1.
  • the DC power supply section 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1.
  • a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32.
  • the output voltage Vdc of the DC voltage source E1 is applied between the positive pole P1 and the negative pole N1 of the DC power supply section 3.
  • the capacitance of the second capacitor C2 is the same as that of the first capacitor C1.
  • the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" is not limited to the case where the capacitance of the second capacitor C2 completely matches the capacitance of the first capacitor C1; It is sufficient that the capacitance of C2 is within the range of 95% or more and 105% or less of the capacitance of the first capacitor C1.
  • the switching circuit 10 included in the inverter circuit 1U will be referred to as the switching circuit 10U
  • the switching circuit 10 included in the inverter circuit 1V will be referred to as the switching circuit 10V
  • the switching circuit 10 included in the inverter circuit 1W will be referred to as the switching circuit 10V
  • the included switching circuit 10 may also be referred to as a switching circuit 10W.
  • the output terminal 41 included in the inverter circuit 1U is referred to as an output terminal 41U
  • the output terminal 41 included in the inverter circuit 1V is referred to as an output terminal 41V
  • the output terminal 41 included in the inverter circuit 1W is referred to as an output terminal 41V. is sometimes referred to as the output terminal 41W.
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal.
  • the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, MOSFETs. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are as follows. These are a gate terminal, a drain terminal, and a source terminal.
  • the MOSFETs forming each of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are, for example, normally-off type n-channel MOSFETs.
  • the MOSFET is, for example, a Si-based MOSFET or a SiC-based MOSFET.
  • the control terminal of the first switching element Q1 of each switching circuit 10 is connected to the corresponding first gate driver 61 among the plurality of first gate drivers 61. Further, a control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding second gate driver 62 among the plurality of second gate drivers 62. Further, the control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding third gate driver 63 among the plurality of third gate drivers 63. Further, a control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding fourth gate driver 64 among the plurality of fourth gate drivers 64.
  • the first main terminal of the first switching element Q1 is connected to the positive electrode P1 of the DC power supply section 3, and the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2. It is connected. Furthermore, in each switching circuit 10, the second main terminal of the second switching element Q2 is connected to the first main terminal of the third switching element Q3. In each switching circuit 10, the second main terminal of the third switching element Q3 is connected to the first main terminal of the fourth switching element Q4, and the second main terminal of the fourth switching element Q4 is connected to the negative terminal of the DC power supply section 3. Connected to N1.
  • the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. Further, in the inverter circuit 1V, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. Further, in the inverter circuit 1W, the third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W.
  • the U phase of the AC load RA1 is connected to the third connection point 13 of the inverter circuit 1U via the output terminal 41U.
  • the V phase of the AC load RA1 is connected to the third connection point 13 of the inverter circuit 1V via the output terminal 41V.
  • the W phase of the AC load RA1 is connected to the third connection point 13 of the inverter circuit 1W via the output terminal 41W.
  • the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal of the first switching element Q1. (drain terminal). Furthermore, in each inverter circuit 1, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal of the second switching element Q2. Connected to the main terminal (drain terminal).
  • the anode of the third diode D3 is connected to the second main terminal (source terminal) of the third switching element Q3, and the cathode of the third diode D3 is connected to the first main terminal of the third switching element Q3. Connected to the main terminal (drain terminal).
  • the anode of the fourth diode D4 is connected to the second main terminal (source terminal) of the fourth switching element Q4, and the cathode of the fourth diode D4 is connected to the first main terminal of the fourth switching element Q4. Connected to the main terminal (drain terminal).
  • the first diode D1 may be replaced by a parasitic diode of a MOSFET that constitutes the first switching element Q1.
  • the second diode D2 may be replaced by a parasitic diode of a MOSFET that constitutes the second switching element Q2.
  • the third diode D3 may be replaced by a parasitic diode of a MOSFET that constitutes the third switching element Q3.
  • the fourth diode D4 may be replaced by a parasitic diode of a MOSFET that constitutes the fourth switching element Q4.
  • the cathode of the fifth diode D5 is connected to the first connection point 11 between the first switching element Q1 and the second switching element Q2. Further, the anode of the fifth diode D5 is connected to the intermediate potential point M1 of the DC power supply section 3.
  • the "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.
  • the intermediate potential point M1 is connected to the ground, so the potential of the intermediate potential point M1 is 0V. In this case, assuming that the voltage across the DC power supply section 3 is Vdc, the potential of the positive electrode P1 is Vdc/2, and the potential of the negative electrode N1 is -Vdc/2.
  • the cathode of the sixth diode D6 is connected to the intermediate potential point M1.
  • the anode of the sixth diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.
  • the plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1.
  • the plurality of first gate drivers 61 are connected to the control terminals of the corresponding first switching elements Q1.
  • the plurality of first gate drivers 61 drive corresponding first switching elements Q1.
  • the plurality of first gate drivers 61 are connected to the control section 60.
  • the control unit 60 outputs a plurality of first control signals S1 (see FIG. 2) corresponding one-to-one to the plurality of first gate drivers 61.
  • Each of the plurality of first gate drivers 61 controls on/off of the first switching element Q1 based on the applied first control signal S1.
  • the plurality of second gate drivers 62 correspond one-to-one to the plurality of second switching elements Q2.
  • the plurality of second gate drivers 62 are connected to the control terminals of the corresponding second switching elements Q2.
  • the plurality of second gate drivers 62 drive corresponding second switching elements Q2.
  • the plurality of second gate drivers 62 are connected to the control section 60.
  • the control unit 60 outputs a plurality of second control signals S2 (see FIG. 2) corresponding one-to-one to the plurality of second gate drivers 62.
  • Each of the plurality of second gate drivers 62 controls on/off of the second switching element Q2 based on the applied second control signal S2.
  • the plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3.
  • the plurality of third gate drivers 63 are connected to the control terminals of the corresponding third switching elements Q3.
  • the plurality of third gate drivers 63 drive corresponding third switching elements Q3.
  • the plurality of third gate drivers 63 are connected to the control section 60.
  • the control unit 60 outputs a plurality of third control signals S3 (see FIG. 2) corresponding one-to-one to the plurality of third gate drivers 63.
  • Each of the plurality of third gate drivers 63 controls on/off of the third switching element Q3 based on the applied third control signal S3.
  • the plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4.
  • the plurality of fourth gate drivers 64 are connected to the control terminals of the corresponding fourth switching elements Q4.
  • the plurality of fourth gate drivers 64 drive corresponding fourth switching elements Q4.
  • the plurality of fourth gate drivers 64 are connected to the control section 60.
  • the control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 2) corresponding one-to-one to the plurality of fourth gate drivers 64.
  • Each of the plurality of fourth gate drivers 64 controls on/off of the fourth switching element Q4 based on the applied fourth control signal S4.
  • the plurality of first bootstrap circuits 71 correspond to the plurality of first gate drivers 61 on a one-to-one basis.
  • the plurality of first bootstrap circuits 71 supply voltage to the corresponding first gate drivers 61.
  • Each of the plurality of first bootstrap circuits 71 includes a diode D17, a resistor R17, and a capacitor C17 (also referred to as a boost capacitor C17).
  • the anode of the diode D17 is connected to the positive terminal of the power supply section 9, and the cathode of the diode D17 is connected to the first end of the capacitor C17 via the resistor R17.
  • the first end of the capacitor C17 is connected to the high potential power supply terminal 61H (see FIG.
  • the first bootstrap circuit 71 supplies the first gate driver 61 with a voltage necessary to turn on the first switching element Q1 in the first gate driver 61.
  • Each of the plurality of first bootstrap circuits 71 further includes a Zener diode Z17 connected in parallel to the capacitor C17.
  • the plurality of second bootstrap circuits 72 correspond to the plurality of second gate drivers 62 on a one-to-one basis.
  • the plurality of second bootstrap circuits 72 supply voltages to the corresponding second gate drivers 62.
  • Each of the plurality of second bootstrap circuits 72 includes a diode D27, a resistor R27, and a capacitor C27 (also referred to as a boost capacitor C27).
  • the anode of the diode D27 is connected to the positive terminal of the power supply section 9, and the cathode of the diode D27 is connected to the first end of the capacitor C27 via the resistor R27.
  • the first end of the capacitor C27 is connected to the high potential power supply terminal 62H (see FIG.
  • the second bootstrap circuit 72 supplies the second gate driver 62 with a voltage necessary to turn on the second switching element Q2 in the second gate driver 62.
  • Each of the plurality of second bootstrap circuits 72 further includes a Zener diode Z27 connected in parallel to the capacitor C27.
  • the plurality of third bootstrap circuits 73 correspond to the plurality of third gate drivers 63 on a one-to-one basis.
  • the plurality of third bootstrap circuits 73 supply voltage to the corresponding third gate drivers 63.
  • Each of the plurality of third bootstrap circuits 73 includes a diode D37, a resistor R37, and a capacitor C37 (also referred to as a boost capacitor C37).
  • the anode of the diode D37 is connected to the positive terminal of the power supply section 9, and the cathode of the diode D37 is connected to the first end of the capacitor C37 via the resistor R37.
  • the first end of the capacitor C37 is connected to the high potential power supply terminal 63H (see FIG.
  • the third bootstrap circuit 73 supplies the third gate driver 63 with a voltage necessary to turn on the third switching element Q3 in the third gate driver 63.
  • Each of the plurality of third bootstrap circuits 73 further includes a Zener diode Z37 connected in parallel to the capacitor C37.
  • the power supply section 9 includes a plurality (three) of first bootstrap circuits 71, a plurality (three) of second bootstrap circuits 72, a plurality (three) of third bootstrap circuits 73, and a plurality (three) of third bootstrap circuits 73.
  • a voltage is supplied to the fourth gate driver 64.
  • the power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91.
  • the positive side terminal of the power supply unit 9 is connected to the high potential side power supply terminal 64H (see FIG. 3) of each of the plurality of fourth gate drivers 64, and the negative side terminal of the power supply unit 9 is connected to the high potential side power supply terminal 64H (see FIG. 3) of each of the plurality of fourth gate drivers 64. It is connected to the low potential side power supply terminal 64L (see FIG. 3) of each driver 64.
  • the control unit 60 controls a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 , and a plurality of fourth gate drivers 64 . Thereby, the control unit 60 controls the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4.
  • the main body that executes the control unit 60 includes a computer system.
  • a computer system includes one or more computers.
  • a computer system mainly consists of a processor and a memory as hardware.
  • the function of the control unit 60 as an execution entity in the present disclosure is realized by the processor executing a program recorded in the memory of the computer system.
  • the program may be pre-recorded in the computer system's memory, or may be provided via a telecommunications line, or may be stored in a non-temporary storage device such as a memory card, optical disk, hard disk drive (magnetic disk), etc. that can be read by the computer system. It may also be provided recorded on a digital recording medium.
  • a processor of a computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI).
  • the plurality of electronic circuits may be integrated into one chip, or may be provided in a distributed manner over a plurality of chips.
  • a plurality of chips may be integrated into one device, or may be distributed and provided in a plurality of devices.
  • the control unit 60 receives a plurality of (three) first control signals S1 (see FIG. 2) for controlling a plurality of (three) first switching elements Q1 and a plurality of (three) second switching elements Q2.
  • a plurality of (three) second control signals S2 for controlling the plurality of third switching elements Q3, and a plurality of (three) third control signals S3 (see FIG. 2) for controlling the plurality of third switching elements Q3.
  • a plurality of (three) fourth control signals S4 for controlling the plurality of (three) fourth switching elements Q4.
  • FIG. 2 only one inverter circuit 1 among the three inverter circuits 1 is illustrated, and illustration of the remaining two inverter circuits is omitted. Further, in FIG.
  • a plurality of first gate drivers 61 , a plurality of second gate drivers 62 , a plurality of third gate drivers 63 , a plurality of fourth gate drivers 64 , and a plurality of first bootstrap circuits 71 , a plurality of second bootstrap circuits 72, a plurality of third bootstrap circuits 73, and a power supply section 9 are not illustrated.
  • FIG. 3 only one inverter circuit 1 among the three inverter circuits 1 is illustrated, and illustration of the remaining two inverter circuits is omitted.
  • two first gate drivers 61, two second gate drivers 62, two third gate drivers 63, two fourth gate drivers 64, and two first bootstrap circuits 71 are shown.
  • two second bootstrap circuits 72, and two third bootstrap circuits 73 are not shown.
  • the three first control signals S1 are a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V. and a first control signal S1W that controls the first switching element Q1.
  • the three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V. and a second control signal S2W that controls the second switching element Q2.
  • the three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V. and a third control signal S3W that controls the third switching element Q3.
  • the three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V. and a fourth control signal S4W that controls the fourth switching element Q4.
  • Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4 have, for example, a potential level at a first potential level (hereinafter also referred to as low level). This is a signal that changes between a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.
  • the first potential level is, for example, 0V
  • the second potential level is a potential level higher than the gate threshold voltage of the MOSFET.
  • the first potential level is The second potential level is a potential level for turning off the switching element corresponding to the control signal, and the second potential level is a potential level for turning on the switching element corresponding to the control signal.
  • Each of the plurality of first switching elements Q1 is in an on state when the corresponding first control signal S1 is at a high level, and is in an off state when it is at a low level. Further, each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level, and turned off when the corresponding second control signal S2 is at a low level. Furthermore, each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level, and turned off when the corresponding third control signal S3 is at a low level. Further, each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level, and turned off when the corresponding fourth control signal S4 is at a low level.
  • each of the plurality of inverter circuits 1 is controlled to the first switching state, the second switching state, or the third switching state. That is, in the multilevel inverter 100, in each of the three inverter circuits 1U, 1V, and 1W, the switching state of the switching circuit 10 is one of the first switching state, the second switching state, and the third switching state. controlled by.
  • the first switching state, the second switching state, and the third switching state differ in the combinations of on/off states of the first to fourth switching elements Q1 to Q4.
  • the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other.
  • the potential level of the output voltage changes in three levels depending on the states of the first to fourth switching elements Q1 to Q4.
  • the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other. different.
  • the first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the on state, and both the third switching element Q3 and the fourth switching element Q4 are in the off state.
  • Each of the plurality of inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply section 3 when controlled to the first switching state.
  • the potential of the third connection point 13 becomes the potential level of the positive electrode P1 of the DC power supply section 3 (for example, Vdc/2).
  • the second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state, and both the second switching element Q2 and the third switching element Q3 are in the on state.
  • Each of the plurality of inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply section 3 when controlled to the second switching state.
  • the potential at the third connection point 13 becomes the potential level (for example, 0) of the intermediate potential point M1.
  • the third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the off state, and both the third switching element Q3 and the fourth switching element Q4 are in the on state.
  • Each of the plurality of inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply section 3 when controlled to the third switching state.
  • the potential at the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply section 3 (for example, ⁇ Vdc/2).
  • the capacitor C17 of the first bootstrap circuit 71 is connected to the first gate driver 61 so that the first gate driver 61 turns on the first switching element Q1. Necessary voltage is supplied. Therefore, as shown in FIG. - Discharged on the discharge path Ru1 of the capacitor C17. As a result, in the first bootstrap circuit 71, the voltage across the capacitor C17 decreases over time.
  • the capacitor C27 of the second bootstrap circuit 72 is connected to the second gate driver 62 so that the second gate driver 62 turns on the second switching element Q2. Necessary voltage is supplied. Therefore, the electric charge of the capacitor C27 of the second bootstrap circuit 72 is transmitted through the discharge path Ru2 of the capacitor C27 - the high potential side power supply terminal 62H of the second gate driver 62 - the low potential side power supply terminal 62L of the second gate driver 62 - the capacitor C27. is discharged. As a result, in the second bootstrap circuit 72, the voltage across the capacitor C27 decreases over time.
  • the voltage across the capacitor C17 is Vo1
  • the voltage across the capacitor C27 is Vo2
  • the voltage across the diode D17 is Vd1
  • the voltage across the resistor R17 is VR1
  • the second switching element Q2 When the switching circuit 10 of the inverter circuit 1 is in the first switching state, the capacitor C17 is charged by the capacitor C27 when the first condition is satisfied.
  • the first condition is Vo2>(Vo1+Vd1+VR1+Vf2).
  • a charging path Ru21 for charging the capacitor C17 by the capacitor C27 is a path of the capacitor C27, the resistor R27, the diode D17, the resistor R17, the capacitor C1, the first connection point 11, the second switching element Q2, and the capacitor C27.
  • the switching circuit 10 of the inverter circuit 1 when the switching circuit 10 of the inverter circuit 1 is in the second switching state, for example, as shown in FIG. 13-A current flows through the path of the output terminal 41 (the path indicated by the thick solid arrow), and the voltage value of the output voltage to the AC load RA1 becomes zero. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, the intermediate potential point M1 of the DC power supply section 3 - the fifth diode D5 - A current flows through the path of the second switching element Q2, the third connection point 13, and the output terminal 41 of the switching circuit 10U.
  • the switching circuit 10 of the inverter circuit 1 when the switching circuit 10 of the inverter circuit 1 is in the second switching state, for example, as shown in FIG. In some cases, a current flows through the path (the path indicated by the thick broken line arrow), and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, the output terminal 41 of the inverter circuit 1U - the third connection point - the third A current flows through the path of switching element Q3-second connection point 12-sixth diode D6 (path indicated by a thick broken line arrow), and the voltage value of the output voltage to AC load RA1 becomes zero.
  • the capacitor C27 of the second bootstrap circuit 72 is connected to the second gate driver 62 so that the second gate driver 62 turns on the second switching element Q2. Necessary voltage is supplied. Therefore, as shown in FIG. 5, the charge on the capacitor C27 of the second bootstrap circuit 72 is as follows: - Discharged on the discharge path Ru2 of the capacitor C27. Further, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C37 of the third bootstrap circuit 73 is connected to the third gate driver 63 so that the third gate driver 63 turns on the third switching element Q3. Necessary voltage is supplied.
  • the electric charge of the capacitor C37 of the third bootstrap circuit 73 is transferred to the discharge path Ru3 of the capacitor C37 - the high potential power supply terminal 63H of the third gate driver 63 - the low potential power supply terminal 63L of the third gate driver 63 - the discharge path Ru3 of the capacitor C37. is discharged.
  • the voltages across the capacitors C17, C27, and C37 are respectively Vo1, Vo2, and Vo3, the voltages across the resistors R17 and R27 are VR1 and VR2, and the second switching element Q2 and the third switching element Assuming that the voltages across the element Q3 are Vf2 and Vf3, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the capacitor C27 is charged by the capacitor C37 when the second condition is satisfied, and when the third condition is satisfied Capacitor C17 is charged by capacitor C27.
  • the second condition is Vo3>(Vo2+Vd2+VR2+Vf3).
  • the third condition is Vo2>(Vo1+Vd1+VR1+Vf2).
  • a charging path Ru32 for charging the capacitor C27 by the capacitor C37 is a path from the capacitor C37 to the resistor R37 to the diode D27 to the resistor R27 to the capacitor C27 to the third connection point 13 to the third switching element Q3 to the capacitor C37.
  • a charging path Ru21 for charging the capacitor C17 by the capacitor C27 is a path of the capacitor C27, the resistor R27, the diode D17, the resistor R17, the capacitor C17, the first connection point 11, the second switching element Q2, and the capacitor C27.
  • a charging path Ru32 for charging the capacitor C27 by the capacitor C37 is a path from the capacitor C37 to the resistor R37 to the diode D27 to the resistor R27 to the capacitor C27 to the third connection point 13 to the third switching element Q3 to the capacitor C37.
  • the switching circuit of the inverter circuit 1 when the switching circuit of the inverter circuit 1 is in the third switching state, as shown in FIG. A current flows through the 41U path, and the voltage value of the output voltage to the AC load RA1 becomes -Vdc/2. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C17 of the first bootstrap circuit 71 is charged, so the voltage of the capacitor C17 increases over time, and the capacitor C17 becomes fully charged. Become. Further, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C27 of the second bootstrap circuit 72 (see FIG. 1) is charged, so the voltage of the capacitor C27 increases over time, and the capacitor C27 is fully charged.
  • the capacitor C37 of the third bootstrap circuit 73 is connected to the third gate driver 63 so that the third gate driver 63 turns on the third switching element Q3. Necessary voltage is supplied. Therefore, the electric charge of the capacitor C37 of the third bootstrap circuit 73 is transferred to the discharge path Ru3 of the capacitor C37 - the high potential power supply terminal 63H of the third gate driver 63 - the low potential power supply terminal 63L of the third gate driver 63 - the discharge path Ru3 of the capacitor C37. is discharged. As shown in FIG.
  • the voltage across the power supply section 9 is Voo
  • the voltages across the capacitors C27 and C37 are Vo2 and Vo3
  • the voltages across the resistors R27 and R37 are VR2 and VR3, respectively
  • the third switching Assuming that the voltages across the element Q3 and the fourth switching element Q4 are Vf3 and Vf4, respectively, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the capacitor C37 is charged by the power supply section 9 when the fourth condition is satisfied.
  • the capacitor C27 is charged by the capacitor C37 when the fifth condition is satisfied.
  • the sixth condition is Voo>(Vo3+Vd3+VR3+Vf4).
  • the fifth condition is Vo3>(Vo2+Vd2+VR2+Vf3).
  • a charging path Ru93 for charging the capacitor C37 by the power supply section 9 includes the positive side terminal of the power supply section 9 - diode D37 - diode D27 - resistor R27 - capacitor C27 - third connection point 13 - third switching element Q3 - fourth switching element. Q4 - This is the path for the negative terminal of the power supply section 9.
  • a charging path Ru32 for charging the capacitor C27 by the capacitor C37 is a path from the capacitor C37 to the resistor R37 to the diode D27 to the resistor R27 to the capacitor C27 to the third connection point 13 to the third switching element Q3 to the capacitor C37.
  • the control unit 60 controls the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U based on voltage commands Vu, Vv, and Vw (see FIG. 8) regarding the output voltages of the inverter circuits 1U, 1V, and 1W, respectively.
  • Fourth control signals S1 to S4 (S1U to S4U), first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V, and first to fourth control signals S1 to S4 (S1V to S4V) of the inverter circuit 1W -Generate first to fourth control signals S1 to S4 (S1W to S4W) for fourth switching elements Q1 to Q4.
  • the voltage command Vu, the voltage command Vv, and the voltage command Vw are, for example, sinusoidal signals whose phases differ by 120 degrees, and their respective values (voltage command values) change over time. Change. Note that the length of one cycle of voltage command Vu, voltage command Vv, and voltage command Vw is the same.
  • the control unit 60 may perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on information output from the detection unit 8 that detects the state of the AC load RA1.
  • PI Proportional Integral
  • the information output from the detection unit 8 is, for example, the detection results of a plurality of current sensors that detect the output currents flowing in each of the U phase, V phase, and W phase of the AC load RA1. and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase motor.
  • the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U) will be described.
  • the operations of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W are similar to the operations of the U-phase inverter circuit 1U.
  • the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W have different phases.
  • the control unit 60 controls the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 by performing voltage vector control.
  • the control unit 60 stores a group of voltage vectors in advance.
  • Each of the group of voltage vectors is determined by a combination of potential levels at the connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1.
  • a group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase.
  • the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each having a magnitude of zero, as shown in FIG. Further, the group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each having a magnitude of (2/3) 1/2 ⁇ 2 Vdc and having different directions. Furthermore, the group of voltage vectors consists of 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, each having a magnitude of (2/3) 1/2 ⁇ Vdc, Contains V12p and V12n.
  • a group of voltage vectors consists of six voltage vectors V13, V14, V15, V16, V17, and V18, each with a magnitude of (2/3) 1/2 3 1/2 Vdc and different directions.
  • the angle between two adjacent voltage vectors among six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees.
  • the angle between two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees.
  • FIG. 9 is a vector diagram showing a group of voltage vectors on orthogonal dq coordinates.
  • a group of voltage vectors represents the first switching state, the second switching state, and the third switching state with the symbols "P", "0", and "N", respectively, and the U-phase, V-phase, and W-phase. When written in order, it can be expressed as shown in FIG.
  • the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o[000], respectively.
  • V0p[PPP] with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P", the switching state of the V-phase switching circuit 10V is "P”, and the switching state of the W-phase switching circuit This represents that the switching state of 10W is "P".
  • a voltage vector appended with "p” such as V10p includes "P" and does not include "N". This point is the same below.
  • a voltage vector with an "n” attached thereto such as V10n, includes “N” and does not include “P”. This point is the same below.
  • a voltage vector with an "o” attached such as V10o, includes “0” and does not include “P” and “N”.
  • the switching state of the switching circuit 10 is "P"
  • the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply section 3.
  • the switching state of the switching circuit 10 is "N”
  • the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply section 3.
  • the switching state of the switching circuit 10 is "0"
  • the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply section 3.
  • V1, V2, V3, V4, V5, and V6 are V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP, respectively. ] It can be expressed as "p”, "n” after the number “V”, such as V1 [PNN], V2 [PPN], V3 [NPN], V4 [NPP], V5 [NNP], V6 [PNP], Voltage vectors without any "o” include “P” and "N” as three-phase switching states.
  • the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n are V7p[P00], V7n[0NN], V8p[PP0], and V8n, respectively. [00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0].
  • V13, V14, V15, V16, V17, and V18 are V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0, respectively. ] It can be expressed as.
  • the control unit 60 converts the instantaneous value of the command voltage regarding the output voltage of each of the plurality of inverter circuits 1 into a command voltage vector V * (see FIG. 11). If the d-axis component of the command voltage vector V * on the orthogonal d-q coordinates is Vd, and the q-axis component of the command voltage vector V * on the orthogonal d-q coordinates is Vq, then the command voltage vector V * is It can be determined using equation (1).
  • the control unit 60 selects a plurality (for example, five) of voltage vectors adjacent to the command voltage vector V * from among the group of voltage vectors.
  • the plurality of voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].
  • the control unit 60 selects a first voltage vector VV1 (in the examples of FIGS. 11 and 12A, V8p[PP0] and V8n[00N]) whose size is the reference size among the plurality of voltage vectors and is closest to the command voltage vector V*. ) is the zero vector V0n[NNN] of the combination in which the potential level of the third connection point 13 between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1 is a negative potential, and the first voltage vector At least one second voltage vector VV2 (in the example of FIG. 12A, V2[PPN]) having the same direction as VV1 and a different magnitude from the first voltage vector VV1.
  • the reference size is, for example, (2/3) 1/2 ⁇ Vdc. Therefore, the plurality of voltage vectors are 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p as voltage vectors (reference vectors) whose magnitude is the reference magnitude. [0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0]. The angle between the first voltage vector VV1 closest to the command voltage vector V * and the command voltage vector V * is smaller than 30 degrees.
  • the control unit 60 controls three voltage vectors (V13[P0N] in the example of FIG. 12B) other than the first voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 12A) among the plurality of voltage vectors. , V7p[P00] and V7n[0NN]), the zero vector V0n[NNN], and at least one second voltage vector VV2 at a predetermined control period so as to match the command voltage vector V * .
  • a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 are controlled within Ts (see FIG. 15).
  • the predetermined control period Ts is, for example, two periods of the carrier signal.
  • the composite vector of the vectors at the vertices of the equilateral triangle surrounding the command voltage vector V * is , to match the command voltage vector V * . That is, in the comparative example, the first voltage vector VV1 (in the example of FIG. 12A, V8p[PP0] and V8n[00N]), the voltage vector V13[P0N], and the voltage vector V7p[P00] and V7n[0NN]. , is made to match the command voltage vector V * .
  • the control period Ts is one period of the carrier signal.
  • T0 is the allocation time of voltage vector V8p and voltage vector V8n
  • T1 is the allocation time of voltage vector V13
  • T2 is the allocation time of voltage vector V7p and voltage vector V7n with respect to the control period Ts. It has been done.
  • T0, T1, and T2 if the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector V * are Va, Vb, and Vc, the magnitude of the command voltage vector V * is V, and the angle is ⁇ , then the formula (2 ) and formula (3) are determined.
  • "j" in equation (2) is an imaginary unit.
  • voltage vector Va is voltage vector V8p[PP0] and V8n[00N]
  • voltage vector Vb is voltage vector V13[P0N]
  • voltage vector Vc is voltage vector V8p[PP0] and V8n[00N].
  • the second switching element Q2 is in the on state during the entire period within the control period Ts, and the voltage drop width of the second bootstrap circuit 72 becomes large.
  • voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ The voltage vectors are output in the following order: voltage vector V7p[P00] ⁇ voltage vector V8p[PP0] ⁇ voltage vector V8p[PP0] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ voltage vector V8n[00N].
  • the control unit 60 replaces the voltage vectors V8p[PP0] and V8p[PP0] in the comparative example with the zero vector V0n[NNN] and the second voltage vector VV2 (V2[PPN]), as shown in FIG.
  • a period in which the U-phase switching state is "N" can be generated.
  • the multilevel inverter 100 according to the first embodiment as shown in FIG. 16, both the first switching element Q1 and the second switching element Q2 are in the OFF state, and the third switching element Q3 and the fourth switching element A third switching state can occur in which both Q4 are in the on state. Therefore, the multilevel inverter 100 according to the first embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72.
  • the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.
  • voltage vector V8p[PP0] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ voltage vector The voltage vectors are output in the order of V7p[P00] ⁇ voltage vector V8p[PP0].
  • FIG. 17 as in the example of FIG.
  • the distribution time of voltage vectors V8p and V8n is T0
  • the distribution time of voltage vector V13 is T1
  • the distribution time of voltage vectors V7p and V7n is T2.
  • An example is shown below. In this case, as shown in FIG. 18, the third switching state does not occur during the entire period within the control period Ts, and the voltage drop width of the second bootstrap circuit 72 becomes large.
  • control unit 60 of the multilevel inverter 100 within two cycles of the carrier signal, for example, as shown in FIG. 19, voltage vector V2[PPN] ⁇ voltage vector V7p[P00] ⁇
  • the voltage vectors are output in the following order: voltage vector V13[P0N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ voltage vector V7p[P00] ⁇ zero vector V0n[NNN].
  • the control unit 60 replaces the voltage vectors V8p[PP0] and V8p[PP0] in the example of FIG.
  • the multilevel inverter 100 according to the first embodiment can generate the third switching state within the control period Ts, as shown in FIG. 20. Therefore, the multilevel inverter 100 according to the first embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72.
  • the control unit 60 sets the first voltage vector VV1 to the zero vector V0n[NNN] when the polarity of the command voltage corresponding to the command voltage vector V * is positive. 2 voltage vector VV2.
  • the control unit 60 converts the first voltage vector VV1 into the zero vector V0n[NNN] and the second voltage vector. Do not replace with VV2.
  • control unit 60 controls the plurality of first gate drivers so that the output voltage of each of the plurality of first bootstrap circuits 71 and the plurality of second bootstrap circuits 72 does not fall below a predetermined value. 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64.
  • the control unit 60 controls a plurality (5) of voltage vectors (for example, V8p) adjacent to the command voltage vector V * among a group (27) of voltage vectors. [PP0], V8n[00N], V13[P0N], V7p[P00], V7n[0NN]).
  • Each of the group of voltage vectors is determined by a combination of potential levels at the third connection point 13 between the second switching element Q2 and the third switching element Q3 of the plurality of inverter circuits 1.
  • the control unit 60 controls one first voltage vector VV1 among the two first voltage vectors VV1 whose size is the reference size and is closest to the command voltage vector V * among the plurality of voltage vectors to the plurality of inverter circuits 1.
  • the voltage vector VV1 is replaced with a second voltage vector VV2 that is twice as large as the voltage vector VV1.
  • the control unit 60 controls voltage vectors other than the first voltage vector VV1 among the plurality of voltage vectors, the remaining first voltage vector VV1 of the two first voltage vectors VV1, the zero vector V0n[NNN], and the second voltage vector.
  • a plurality of first gate drivers 61, a plurality of second gate drivers 62, and a plurality of third gate drivers 63 are operated within a predetermined control period Ts so that the composite vector of vector VV2 and vector VV2 matches the command voltage vector V * .
  • a plurality of fourth gate drivers 64 are controlled.
  • the multilevel inverter 100 it is possible to suppress voltage drop in the bootstrap circuit. More specifically, according to this aspect, the voltage drop in the capacitor C17 of the plurality of first bootstrap circuits 71, the capacitor C27 of the plurality of second bootstrap circuits 72, and the capacitor C37 of the plurality of third bootstrap circuits 73 is reduced. It becomes possible to suppress this.
  • the DC-DC converter 91 included in the power supply section 9 supplies voltage to the plurality of fourth gate drivers 64 and the plurality of third bootstrap circuits 73.
  • the multilevel inverter 100 according to the first embodiment can be made smaller.
  • VV1 is replaced with a zero vector (V0n[NNN]) and a second voltage vector VV2 (V2[PPN]).
  • the control unit 60 for example, as shown in the example of FIG. One first voltage vector VV1 (V8n[00N]) of ]).
  • VV1 V8n[00N]
  • the control unit 60 of the multilevel inverter 100 according to the second embodiment within two periods of the carrier signal, as shown in FIG. They are output in the following order: [P00] ⁇ voltage vector V2 [PPN] ⁇ voltage vector V2 [PPN] ⁇ voltage vector V7p [P00] ⁇ voltage vector V13 [P0N] ⁇ zero vector V0 [NNN].
  • the control unit 60 converts the voltage vectors V8n[00N], V8p[PP0], V8p[PP0], and V8n[00N] in the example of FIG. 13 into zero vectors V0n[NNN], voltage vectors V2[PPN], and voltage vectors, respectively. Since V2[PPN] is replaced with the zero vector V0n[NNN], a period in which the U-phase switching state is "N" can be generated, as shown in FIG. Thereby, the multilevel inverter 100 according to the second embodiment can generate the third switching state within the control period Ts, as shown in FIG. 22. Therefore, the multilevel inverter 100 according to the second embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72.
  • the multilevel inverter 100 has the control unit 60 select one of the first voltage vectors VV1 from the two first voltage vectors VV1 (V8n[00N], V8p[PP0]). Only (V8p[PP0]) is replaced with the zero vector V0n[NNN] and the second voltage vector VV2 (V2[PPN]).
  • the control unit 60 for example, as shown in the example of FIG. Among them, one first voltage vector VV1 (V8n [00N]) is replaced with a zero vector V0n [NNN], and the remaining one first voltage vector VV1 (V8p [PP0]) is replaced with a second voltage vector VV2 (V2 [ PPN]).
  • VV1 V8n [00N]
  • V8p [PP0] the remaining one first voltage vector
  • V2 V2 [ PPN]
  • the control unit 60 converts the voltage vectors V8p[PP0], V8n[00N], V8n[00N], and V8p[PP0] in the example of FIG. 17 into voltage vectors V2[PPN], V0n[NNN], and V0n[NNN], respectively. , V2[PPN], it is possible to generate a period in which the U-phase switching state is "N", as shown in FIG.
  • the multilevel inverter 100 according to the second embodiment can generate the third switching state within the control period Ts, as shown in FIG. 24. Therefore, the multilevel inverter 100 according to the second embodiment can suppress the voltage drop of the capacitor C27 of the second bootstrap circuit 72.
  • the control unit 60 selects the first voltage vector VV1, which has the reference size among the plurality of voltage vectors and is closest to the command voltage vector V * , to the plurality of inverter circuits 1.
  • the voltage vector VV1 is replaced with a second voltage vector VV2 that is twice as large as the voltage vector VV1.
  • the control unit 60 causes a composite vector of voltage vectors other than the first voltage vector VV1 among the plurality of voltage vectors, the zero vector Vo[NNN], and the second voltage vector VV2 to match the command voltage vector V * . Then, the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, and the plurality of fourth gate drivers 64 are controlled within a predetermined control period Ts.
  • the multilevel inverter 100 it is possible to suppress voltage drop in the bootstrap circuit. More specifically, according to this aspect, the voltage drop in the capacitor C17 of the plurality of first bootstrap circuits 71, the capacitor C27 of the plurality of second bootstrap circuits 72, and the capacitor C37 of the plurality of third bootstrap circuits 73 is reduced. It becomes possible to suppress this.
  • Embodiments 1 and 2 described above are only one of various embodiments of the present disclosure.
  • the first and second embodiments described above can be modified in various ways depending on the design, etc., as long as the objective of the present disclosure can be achieved.
  • each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4 are not limited to MOSFETs, but are, for example, IGBTs (Insulated Gate Bipolar Transistors).
  • the control terminal, the first main terminal, and the second main terminal in each of the plurality of first switching elements Q1, the plurality of second switching elements Q2, the plurality of third switching elements Q3, and the plurality of fourth switching elements Q4. are the gate terminal, collector terminal and emitter terminal, respectively.
  • control unit 60 controls the first voltage not only when the polarity of the command voltage corresponding to the command voltage vector V * is positive but also when the polarity is negative.
  • Vector VV1 may be replaced with zero vector V0n[NNN] and second voltage vector VV2.
  • each of the plurality of first bootstrap circuits 71 includes the Zener diode Z17, but may have a configuration that does not include the Zener diode Z17.
  • each of the plurality of second bootstrap circuits 72 includes the Zener diode Z27, but may have a configuration that does not include the Zener diode Z27.
  • each of the plurality of third bootstrap circuits 73 includes the Zener diode Z37, but may have a configuration in which the Zener diode Z37 is not included.
  • the multilevel inverter 100 is not limited to the configuration including one DC-DC converter 91 as shown in FIG.
  • the power supply unit 9 may have a configuration including a plurality (three) of DC-DC converters 91.
  • the plurality of DC-DC converters 91 correspond to the plurality of (three) fourth gate drivers 64 and supply voltage to the corresponding fourth gate drivers 64.
  • the anode of the diode D17 is connected to the positive side terminal of the corresponding DC-DC converter 91 among the plurality of DC-DC converters 91. It is connected.
  • the anode of the diode D27 is connected to the positive side terminal of the corresponding DC-DC converter 91 among the plurality of DC-DC converters 91.
  • the anode of the diode D37 is connected to the positive side terminal of the corresponding DC-DC converter 91 among the plurality of DC-DC converters 91.
  • the multilevel inverter 100 may be a multilevel inverter of three or more levels, and may be a five-level inverter, for example.
  • the multilevel inverter 100a includes a DC power supply section 3, a plurality of (for example, three) inverter circuits 1a, and a control device 6a.
  • the DC power supply section 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1.
  • the plurality of inverter circuits 1a are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply section 3.
  • the control device 6a controls the plurality of inverter circuits 1a.
  • the multilevel inverter 100a is a T-type three-level, three-phase inverter.
  • each of the plurality of inverter circuits 1a has an output terminal 41a.
  • an AC load RA1 is connected to a plurality of output terminals (AC terminals) 41a.
  • AC load RA1 is, for example, a three-phase motor.
  • one of the plurality of inverter circuits 1a is an inverter circuit 1Ua that outputs a U-phase voltage
  • another one is an inverter circuit 1Va that outputs a V-phase voltage
  • the remaining One is an inverter circuit 1Wa that outputs a W-phase voltage.
  • Each of the plurality of inverter circuits 1a includes a first switching element Q1a, a second switching element Q2a, a third switching element Q3a, a fourth switching element Q4a, a first diode D1a, a second diode D2a, a third diode D3a, and a third switching element Q4a. 4 diode D4a.
  • the first diode D1a, the second diode D2a, the third diode D3a, and the fourth diode D4a are connected in antiparallel to the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a, respectively. ing.
  • a first switching element Q1a and a second switching element Q2a are connected in series such that the first switching element Q1a and the second switching element Q2a are lined up in this order from the positive electrode P1 side to the negative electrode N1 side.
  • a series circuit (first circuit 11a) of the first switching element Q1a and the second switching element Q2a is connected between the positive electrode P1 and the negative electrode N1.
  • a series circuit (second circuit 12a) of a third switching element Q3a and a fourth switching element Q4a is connected between an intermediate potential point M1 and an output point.
  • the output point is a connection point 13a between the first switching element Q1a and the second switching element Q2a.
  • the second circuit 12a has a bidirectional switch including a third switching element Q3a, a fourth switching element Q4a, a third diode D3a, and a fourth diode D4a.
  • the control device 6a includes a plurality of (for example, three) first gate drivers 61a, a plurality of (for example, three) second gate drivers 62a, a plurality of (for example, three) third gate drivers 63a, A plurality of (for example, three) fourth gate drivers 64a are included.
  • the control device 6a also includes a plurality of (for example, three) bootstrap circuits 71a (hereinafter also referred to as first bootstrap circuits 71a), a plurality of (for example, three) second bootstrap circuits 72a, and a power source. It has a section 9a and a control section 60a.
  • the plurality of first gate drivers 61a drive the first switching elements Q1a of the plurality of inverter circuits 1a.
  • the plurality of second gate drivers 62a drive the second switching elements Q2a of the plurality of inverter circuits 1a.
  • the plurality of third gate drivers 63a drive the third switching elements Q3a of the plurality of inverter circuits 1a.
  • the plurality of fourth gate drivers 64a drive the fourth switching elements Q4a of the plurality of inverter circuits 1a.
  • the plurality of first bootstrap circuits 71a correspond to the plurality of first gate drivers 61a on a one-to-one basis.
  • the plurality of first bootstrap circuits 71a supply voltage to the corresponding first gate drivers 61a.
  • the plurality of second bootstrap circuits 72a correspond to the plurality of third gate drivers 63a and the plurality of fourth gate drivers 64a.
  • the plurality of second bootstrap circuits 72a supply voltages to the corresponding third gate drivers 63a and the corresponding fourth gate drivers 64a.
  • the power supply section 9a supplies voltage to the plurality of second gate drivers 62a.
  • the control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a.
  • the DC power supply unit 3 includes a first capacitor C1 and a second capacitor C2.
  • a first capacitor C1 and a second capacitor C2 are connected in series.
  • the first end of the first capacitor C1 is connected to the first DC terminal 31
  • the second end of the first capacitor C1 is connected to the first end of the second capacitor C2
  • the first end of the first capacitor C1 is connected to the first end of the second capacitor C2.
  • the second end of the two capacitor C2 is connected to the second DC terminal 32.
  • the connection point between the first capacitor C1 and the second capacitor C2 is an intermediate potential point M1.
  • the DC power supply section 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1.
  • a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32.
  • the output voltage Vdc of the DC voltage source E1 is applied between the positive pole P1 and the negative pole N1 of the DC power supply section 3.
  • the capacitance of the second capacitor C2 is the same as that of the first capacitor C1.
  • the capacitance of the second capacitor C2 is the same as the capacitance of the first capacitor C1" is not limited to the case where the capacitance of the second capacitor C2 completely matches the capacitance of the first capacitor C1; It is sufficient that the capacitance of C2 is within the range of 95% or more and 105% or less of the capacitance of the first capacitor C1.
  • the output terminal 41a included in the inverter circuit 1Ua among the plurality of output terminals 41a will be referred to as the output terminal 41Ua
  • the output terminal 41a included in the inverter circuit 1Va will be referred to as the output terminal 41Va
  • the output terminal 41a included in the inverter circuit 1Wa will be referred to as the output terminal 41Va
  • the included output terminal 41a may also be referred to as an output terminal 41Wa.
  • the first switching element Q1a, second switching element Q2a, third switching element Q3a, and fourth switching element Q4a of each inverter circuit 1a have a control terminal, a first main terminal, and a second main terminal.
  • the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a of each inverter circuit 1a are, for example, MOSFETs. Therefore, the control terminal, the first main terminal, and the second main terminal of each of the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a of each inverter circuit 1a are as follows. These are a gate terminal, a drain terminal, and a source terminal.
  • the MOSFETs forming each of the first switching element Q1a, the second switching element Q2a, the third switching element Q3a, and the fourth switching element Q4a are, for example, normally-off type n-channel MOSFETs.
  • the MOSFET is, for example, a Si-based MOSFET or a SiC-based MOSFET.
  • a control terminal of the first switching element Q1a of each inverter circuit 1a is connected to a corresponding first gate driver 61a among the plurality of first gate drivers 61a. Further, a control terminal of the second switching element Q2a of each inverter circuit 1a is connected to a corresponding second gate driver 62a among the plurality of second gate drivers 62a. Further, a control terminal of the third switching element Q3a of each inverter circuit 1a is connected to a corresponding third gate driver 63a among the plurality of third gate drivers 63a. Further, a control terminal of the fourth switching element Q4a of each inverter circuit 1a is connected to a corresponding fourth gate driver 64a among the plurality of fourth gate drivers 64a.
  • the first main terminal of the first switching element Q1a is connected to the positive electrode P1 of the DC power supply section 3, and the second main terminal of the first switching element Q1a is connected to the first main terminal of the second switching element Q2a.
  • the second main terminal of the second switching element Q2a is connected to the negative electrode N1 of the DC power supply section 3.
  • the bidirectional switch included in the second circuit 12a is a common source bidirectional switch in which the second main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a are connected to each other. It's a switch.
  • the "intermediate potential point M1" is a point at which the potential is intermediate between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.
  • the intermediate potential point M1 is connected to the ground, so the potential of the intermediate potential point M1 is 0V.
  • the potential of the positive electrode P1 is Vdc/2
  • the potential of the negative electrode N1 is -Vdc/2.
  • connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Ua.
  • a connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Va.
  • a connection point 13a between the first switching element Q1a and the second switching element Q2a is connected to the output terminal 41Wa.
  • the U phase of AC load RA1 is connected to connection point 13a of inverter circuit 1Ua via output terminal 41Ua.
  • the V phase of the AC load RA1 is connected to the connection point 13a of the inverter circuit 1Va via the output terminal 41Va.
  • the W phase of the AC load RA1 is connected to the connection point 13a of the inverter circuit 1Wa via the output terminal 41Wa.
  • the anode of the first diode D1a is connected to the second main terminal (source terminal) of the first switching element Q1a, and the cathode of the first diode D1a is connected to the first main terminal of the first switching element Q1a. (drain terminal).
  • the anode of the second diode D2a is connected to the second main terminal (source terminal) of the second switching element Q2a, and the cathode of the second diode D2a is connected to the first main terminal of the second switching element Q2a. Connected to the main terminal (drain terminal).
  • the anode of the third diode D3a is connected to the second main terminal (source terminal) of the third switching element Q3a, and the cathode of the third diode D3a is connected to the first main terminal of the third switching element Q3a. Connected to the main terminal (drain terminal).
  • the anode of the fourth diode D4a is connected to the second main terminal (source terminal) of the fourth switching element Q4a, and the cathode of the fourth diode D4a is connected to the first main terminal of the fourth switching element Q4a. Connected to the main terminal (drain terminal).
  • the first diode D1a may be replaced by a parasitic diode of a MOSFET that constitutes the first switching element Q1a.
  • the second diode D2a may be replaced by a parasitic diode of a MOSFET that constitutes the second switching element Q2a.
  • the third diode D3a may be replaced by a parasitic diode of a MOSFET that constitutes the third switching element Q3a.
  • the fourth diode D4a may be replaced by a parasitic diode of a MOSFET that constitutes the fourth switching element Q4a.
  • the plurality of first gate drivers 61a correspond one-to-one to the plurality of first switching elements Q1a.
  • the plurality of first gate drivers 61a are connected to the control terminals of the corresponding first switching elements Q1a.
  • the plurality of first gate drivers 61a drive corresponding first switching elements Q1a.
  • the plurality of first gate drivers 61a are connected to the control section 60a.
  • the control unit 60a outputs a plurality of first control signals S1 (see FIG. 27) that correspond one-to-one to the plurality of first gate drivers 61a.
  • Each of the plurality of first gate drivers 61a controls on/off of the first switching element Q1a based on the applied first control signal S1a.
  • the plurality of second gate drivers 62a correspond one-to-one to the plurality of second switching elements Q2a.
  • the plurality of second gate drivers 62a are connected to the control terminals of the corresponding second switching elements Q2a.
  • the plurality of second gate drivers 62a drive corresponding second switching elements Q2a.
  • the plurality of second gate drivers 62a are connected to the control section 60a.
  • the control unit 60a outputs a plurality of second control signals S2a (see FIG. 27) in one-to-one correspondence to the plurality of second gate drivers 62a.
  • Each of the plurality of second gate drivers 62a controls on/off of the second switching element Q2a based on the applied second control signal S2a.
  • the plurality of third gate drivers 63a correspond one-to-one to the plurality of third switching elements Q3a.
  • the plurality of third gate drivers 63a are connected to the control terminals of the corresponding third switching elements Q3a.
  • the plurality of third gate drivers 63a drive corresponding third switching elements Q3a.
  • the plurality of third gate drivers 63a are connected to the control section 60a.
  • the control unit 60a outputs a plurality of third control signals S3a (see FIG. 27) in one-to-one correspondence to the plurality of third gate drivers 63a.
  • Each of the plurality of third gate drivers 63a controls on/off of the third switching element Q3a based on the applied third control signal S3a.
  • the plurality of fourth gate drivers 64a correspond one-to-one to the plurality of fourth switching elements Q4a.
  • the plurality of fourth gate drivers 64a are connected to the control terminals of the corresponding fourth switching elements Q4a.
  • the plurality of fourth gate drivers 64a drive corresponding fourth switching elements Q4a.
  • the plurality of fourth gate drivers 64a are connected to the control section 60a.
  • the control unit 60a outputs a plurality of fourth control signals S4a (see FIG. 27) in one-to-one correspondence to the plurality of fourth gate drivers 64a.
  • Each of the plurality of fourth gate drivers 64a controls on/off of the fourth switching element Q4a based on the applied fourth control signal S4a.
  • the plurality of first bootstrap circuits 71a correspond to the plurality of first gate drivers 61a on a one-to-one basis.
  • the plurality of first bootstrap circuits 71a supply voltage to the corresponding first gate drivers 61a.
  • each of the plurality of first bootstrap circuits 71a includes a diode D11, a resistor R11, and a capacitor C11 (also referred to as a boost capacitor C11).
  • the anode of the diode D11 is connected to the positive terminal of the power supply section 9a, and the cathode of the diode D11 is connected to the first end of the capacitor C11 via the resistor R11.
  • the first end of the capacitor C11 is connected to the high potential side power supply terminal 61Ha (see FIG. 28) of the first gate driver 61a, and the second end of the capacitor C11 is connected to the low potential side power supply terminal of the first gate driver 61a. 61La (see FIG. 28).
  • the first bootstrap circuit 71a supplies the first gate driver 61a with a voltage necessary to turn on the first switching element Q1a in the first gate driver 61a.
  • Each of the plurality of first bootstrap circuits 71a further includes a Zener diode Z11 connected in parallel to the capacitor C11.
  • the plurality of second bootstrap circuits 72a correspond to the plurality of third gate drivers 63a and the plurality of fourth gate drivers 64a.
  • the plurality of second bootstrap circuits 72a supply voltages to the corresponding third gate drivers 63a and the corresponding fourth gate drivers 64a.
  • Each of the plurality of second bootstrap circuits 72a includes a diode D21, a resistor R21, and a capacitor C21 (also referred to as a boost capacitor C21).
  • the anode of the diode D21 is connected to the positive terminal of the power supply section 9a, and the cathode of the diode D21 is connected to the first end of the capacitor C21 via the resistor R21.
  • the first end of the capacitor C21 is connected to the high potential side power supply terminal 63Ha (see FIG. 28) of the third gate driver 63a and the high potential side power supply terminal 64Ha (see FIG. 28) of the fourth gate driver 64a.
  • the second end of C21 is connected to a low potential power terminal 63La (see FIG. 28) of the third gate driver 63a and a low potential power terminal 64La (see FIG. 28) of the fourth gate driver 64a.
  • the second bootstrap circuit 72a supplies the third gate driver 63a with a voltage necessary to turn on the third switching element Q3a in the third gate driver 63a, and supplies the voltage necessary to turn on the third switching element Q3a in the fourth gate driver 64a.
  • the voltage necessary to turn on the fourth gate driver 64a is supplied to the fourth gate driver 64a.
  • Each of the plurality of second bootstrap circuits 72a further includes a Zener diode Z21 connected in parallel to the capacitor C21.
  • the power supply section 9a supplies voltage to a plurality (three) of first bootstrap circuits 71a, a plurality (three) of second bootstrap circuits 72a, and a plurality (three) of second gate drivers 62a.
  • the power supply unit 9a is, for example, a DC power supply including an isolated DC-DC converter 91a.
  • the positive side terminal of the power supply unit 9a is connected to the high potential side power supply terminal 62Ha (see FIG. 28) of each of the plurality of second gate drivers 62a, and the negative side terminal of the power supply unit 9a is connected to the high potential side power supply terminal 62Ha (see FIG. 28) of each of the plurality of second gate drivers 62a. It is connected to the low potential side power supply terminal 62La (see FIG. 28) of each driver 62a.
  • the control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a. Thereby, the control unit 60a controls the plurality of first switching elements Q1a, the plurality of second switching elements Q2a, the plurality of third switching elements Q3a, and the plurality of fourth switching elements Q4a.
  • the main body that executes the control unit 60a includes a computer system.
  • a computer system includes one or more computers.
  • a computer system mainly consists of a processor and a memory as hardware. When a processor executes a program recorded in the memory of the computer system, the function of the control unit 60a as an execution entity in the present disclosure is realized.
  • the program may be pre-recorded in the computer system's memory, or may be provided via a telecommunications line, or may be stored in a non-temporary storage device such as a memory card, optical disk, hard disk drive (magnetic disk), etc. that can be read by the computer system. It may also be provided recorded on a digital recording medium.
  • a processor of a computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI).
  • the plurality of electronic circuits may be integrated into one chip, or may be provided in a distributed manner over a plurality of chips.
  • a plurality of chips may be integrated into one device, or may be distributed and provided in a plurality of devices.
  • the control unit 60a receives a plurality of (three) first control signals S1a (see FIG. 27) for controlling a plurality of (three) first switching elements Q1a and a plurality of (three) second switching elements Q2a.
  • a plurality of (three) second control signals S2a for controlling the plurality of (three) second control signals S2a (see FIG. 27)
  • a plurality of (three) third control signals S3a for controlling the plurality of third switching elements Q3a.
  • a plurality of (three) fourth control signals S4a for controlling the plurality of (three) fourth switching elements Q4a.
  • FIG. 27 only one inverter circuit 1a among the three inverter circuits 1a is illustrated, and illustration of the remaining two inverter circuits 1a is omitted. Further, in FIG. 27, a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, a plurality of fourth gate drivers 64a, and a plurality of first bootstrap circuits 71a are shown. The illustrations of the plurality of second bootstrap circuits 72a and the power supply section 9a are omitted. Further, in FIG. 28, only one inverter circuit 1a among the three inverter circuits 1a is illustrated, and illustration of the remaining two inverter circuits 1a is omitted. Further, in FIG. 28, two first gate drivers 61a, two second gate drivers 62a, two third gate drivers 63a, two fourth gate drivers 64a, and two first bootstrap circuits 71a. , and two second bootstrap circuits 72a are omitted from illustration.
  • the three first control signals S1a are a first control signal S1Ua that controls the first switching element Q1a of the inverter circuit 1Ua, a first control signal S1Va that controls the first switching element Q1a of the inverter circuit 1Va, and a first control signal S1Va that controls the first switching element Q1a of the inverter circuit 1Va. and a first control signal S1Wa that controls the first switching element Q1a.
  • the three second control signals S2a include a second control signal S2Ua that controls the second switching element Q2a of the inverter circuit 1Ua, a second control signal S2Va that controls the second switching element Q2a of the inverter circuit 1Va, and a second control signal S2Va that controls the second switching element Q2a of the inverter circuit 1Va. and a second control signal S2Wa that controls the second switching element Q2a.
  • the three third control signals S3a are a third control signal S3Ua that controls the third switching element Q3a of the inverter circuit 1Ua, a third control signal S3Va that controls the third switching element Q3a of the inverter circuit 1Va, and a third control signal S3Va that controls the third switching element Q3a of the inverter circuit 1Va. and a third control signal S3Wa that controls the third switching element Q3a.
  • the three fourth control signals S4a are a fourth control signal S4Ua that controls the fourth switching element Q4a of the inverter circuit 1Ua, a fourth control signal S4Va that controls the fourth switching element Q4a of the inverter circuit 1Va, and a fourth control signal S4Va that controls the fourth switching element Q4a of the inverter circuit 1Va. and a fourth control signal S4Wa that controls the fourth switching element Q4a.
  • Each of the plurality of first control signals S1a, the plurality of second control signals S2a, the plurality of third control signals S3a, and the plurality of fourth control signals S4a have, for example, a potential level at a first potential level (hereinafter also referred to as low level). This is a signal that changes between a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.
  • the first potential level is, for example, 0V
  • the second potential level is a potential level higher than the gate threshold voltage of the MOSFET.
  • the first potential level is The second potential level is a potential level for turning off the switching element corresponding to the control signal, and the second potential level is a potential level for turning on the switching element corresponding to the control signal.
  • Each of the plurality of first switching elements Q1a is turned on when the corresponding first control signal S1a is at a high level, and turned off when the corresponding first control signal S1a is at a low level. Further, each of the plurality of second switching elements Q2a is turned on when the corresponding second control signal S2a is at a high level, and turned off when the corresponding second control signal S2a is at a low level. Furthermore, each of the plurality of third switching elements Q3a is turned on when the corresponding third control signal S3a is at a high level, and turned off when the corresponding third control signal S3a is at a low level. Further, each of the plurality of fourth switching elements Q4a is turned on when the corresponding fourth control signal S4a is at a high level, and turned off when the corresponding fourth control signal S4a is at a low level.
  • each of the plurality of inverter circuits 1a is controlled to a first switching state, a second switching state, or a third switching state. That is, in the multilevel inverter 100a, the switching state of each of the three inverter circuits 1Ua, 1Va, and 1Wa is controlled to be one of the first switching state, the second switching state, and the third switching state. .
  • the first switching state, the second switching state, and the third switching state differ in the combinations of on/off states of the first to fourth switching elements Q1a to Q4a.
  • the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from each other. That is, in each of the plurality of inverter circuits 1a, the potential level of the output voltage changes in three levels depending on the states of the first to fourth switching elements Q1a to Q4a. Regarding the output voltages of the plurality of inverter circuits 1a, the output voltage of the U-phase inverter circuit 1Ua, the output voltage of the V-phase inverter circuit 1Va, and the output voltage of the W-phase inverter circuit 1Wa are out of phase with each other. different.
  • the first switching state is a combination in which both the first switching element Q1a and the third switching element Q3a are in the on state, and both the second switching element Q2a and the fourth switching element Q4a are in the off state.
  • Each of the plurality of inverter circuits 1a can output an output voltage at the potential level of the positive electrode P1 of the DC power supply section 3 when controlled to the first switching state.
  • the potential at the connection point 13a becomes the potential level of the positive electrode P1 of the DC power supply section 3 (for example, Vdc/2).
  • the second switching state is a combination in which both the first switching element Q1a and the second switching element Q2a are in the off state, and both the third switching element Q3a and the fourth switching element Q4a are in the on state.
  • Each of the plurality of inverter circuits 1a can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply section 3 when controlled to the second switching state.
  • the potential at the connection point 13a in the second switching state, the potential at the connection point 13a becomes the potential level (for example, 0) of the intermediate potential point M1.
  • the third switching state is a combination in which both the first switching element Q1a and the third switching element Q3a are in the off state, and both the second switching element Q2a and the fourth switching element Q4a are in the on state.
  • Each of the plurality of inverter circuits 1a can output an output voltage at the potential level of the negative electrode N1 of the DC power supply section 3 when controlled to the third switching state.
  • the potential at the connection point 13a becomes the potential level of the negative electrode N1 of the DC power supply section 3 (for example, ⁇ Vdc/2).
  • the inverter circuit 1a When the inverter circuit 1a is in the first switching state, as shown in FIG. 27, a current flows through the path from the positive electrode P1 of the DC power supply section 3 to the first switching element Q1a to the connection point 13a to the output terminal 41a (see FIG. 26). , the voltage value of the output voltage to the AC load RA1 (see FIG. 26) is Vdc/2.
  • the capacitor C11 of the first bootstrap circuit 71a is not charged from the power supply section 9a, and the capacitor C11 of the first bootstrap circuit 71a is charged to the first gate driver 61a.
  • the voltage necessary to turn on the first switching element Q1a is supplied by the first gate driver 61a. Therefore, as shown in FIG. 28, the electric charge of the capacitor C11 of the first bootstrap circuit 71a is as follows: capacitor C11 - high potential side power supply terminal 61Ha of the first gate driver 61a - low potential side power supply terminal 61La of the first gate driver 61a. - Discharged on the discharge path Ru1a of the capacitor C11. As a result, in the first bootstrap circuit 71a, the voltage across the capacitor C11 decreases over time.
  • the capacitor C21 of the second bootstrap circuit 72a is not charged from the power supply section 9a, and the capacitor C21 of the second bootstrap circuit 72a is charged to the third gate driver 63a.
  • the voltage necessary to turn on the third switching element Q3a is supplied by the third gate driver 63a. Therefore, as shown in FIG. 28, the electric charge of the capacitor C21 of the second bootstrap circuit 72a is as follows: capacitor C21 - high potential side power supply terminal 63Ha of the third gate driver 63a - low potential side power supply terminal 63La of the third gate driver 63a. - Discharged through the discharge path Ru3a of the capacitor C21. As a result, in the second bootstrap circuit 72a, the voltage across the capacitor C21 decreases over time.
  • inverter circuit 1a when the inverter circuit 1a is in the second switching state (when changing from the first switching state to the second switching state), for example, as shown in FIG. A current flows through the path of switching element Q3a - fourth switching element Q4a - connection point 13a - output terminal 41a (see FIG. 26), and the voltage value of the output voltage to AC load RA1 becomes 0.
  • the inverter circuit 1a when the inverter circuit 1a is in the second switching state, the voltage required for turning on the third switching element Q3a is applied from the capacitor C21 of the second bootstrap circuit 72a to the third gate driver 63a. Supplied. Therefore, as shown in FIG. 30, the electric charge of the capacitor C21 of the second bootstrap circuit 72a is as follows: capacitor C21 - high potential side power supply terminal 63Ha of the third gate driver 63a - low potential side power supply terminal 63La of the third gate driver 63a. - Discharged through the discharge path Ru3a of the capacitor C21.
  • the inverter circuit 1a when the inverter circuit 1a is in the second switching state, the voltage necessary for turning on the fourth switching element Q4a is applied from the capacitor C21 of the second bootstrap circuit 72a to the fourth gate driver 64a. Supplied. Therefore, the electric charge of the capacitor C21 of the second bootstrap circuit 72a is transmitted through the discharge path Ru4a of the capacitor C21 - the high potential side power supply terminal 64Ha of the fourth gate driver 64a - the low potential side power supply terminal 64La of the fourth gate driver 64a - the capacitor C21. is discharged.
  • a charging path Ru91 for charging the capacitor C11 by the power supply section 9a is a path from the positive terminal of the power supply section 9a - the diode D11 - the resistor R11 - the capacitor C11 - the connection point 13a - the second switching element Q2a - the negative terminal of the power supply section 9a. It is.
  • a charging path Ru92 for charging the capacitor C21 by the power supply section 9a is a positive terminal of the power supply section 9a - a diode D21 - a resistor R21 - a capacitor C21 - a fourth switching element Q4a - a connection point 13a - a second switching element Q2a - a power supply section 9a. This is the path of the negative terminal of .
  • inverter circuit 1a when the inverter circuit 1a is in the second switching state (when changing from the third switching state to the second switching state), for example, as shown in FIG. A current flows through the path of - fourth switching element Q4a - third switching element Q3a - intermediate potential point M1, and the voltage value of the output voltage to AC load RA1 becomes zero.
  • the inverter circuit 1a when the inverter circuit 1a is in the second switching state, it is discharged through each of the discharge paths Ru3a and Ru4a shown in FIG. 30 described above.
  • control unit 60a controls the first to fourth switching elements Q1a to Q4a of the inverter circuit 1Ua based on voltage commands Vu, Vv, and Vw (see FIG. 34) regarding the output voltages of the inverter circuits 1Ua, 1Va, and 1Wa, respectively.
  • 1 to 4th control signals S1a to S4a (S1Ua to S4Ua)
  • first to fourth control signals S1a to S4a S1Va to S4Va
  • First to fourth control signals S1a to S4a (S1Wa to S4Wa) for the first to fourth switching elements Q1a to Q4a are generated.
  • the voltage command Vu, the voltage command Vv, and the voltage command Vw are, for example, sinusoidal signals whose phases differ by 120°, and their values (voltage command values) change over time. Change. Note that the length of one cycle of voltage command Vu, voltage command Vv, and voltage command Vw is the same.
  • the control unit 60a may perform PI (Proportional Integral) control of the voltage commands Vu, Vv, and Vw based on information output from the detection unit 8 that detects the state of the AC load RA1.
  • PI Proportional Integral
  • the information output from the detection unit 8 is, for example, the detection results of a plurality of current sensors that detect the output currents flowing in each of the U phase, V phase, and W phase of the AC load RA1. and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase motor.
  • the operation of one of the three inverter circuits 1a (for example, the U-phase inverter circuit 1Ua) will be described.
  • the operations of the V-phase inverter circuit 1Va and the W-phase inverter circuit 1Wa are similar to the operations of the U-phase inverter circuit 1Ua.
  • the output voltage of the U-phase inverter circuit 1Ua, the output voltage of the V-phase inverter circuit 1Va, and the output voltage of the W-phase inverter circuit 1Wa are different in phase from each other.
  • the control unit 60a controls the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a by performing voltage vector control.
  • the control unit 60a stores a group of voltage vectors in advance.
  • Each of the group of voltage vectors is determined by a combination of potential levels at the connection point 13a between the first switching element Q1a and the second switching element Q2a of the plurality of inverter circuits 1a.
  • a group of voltage vectors is determined by the switching state of the inverter circuit 1Ua corresponding to the U phase, the switching state of the inverter circuit 1Va corresponding to the V phase, and the switching state of the inverter circuit 1Wa corresponding to the W phase.
  • the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each having a magnitude of zero, as shown in FIG. Further, the group of voltage vectors includes six voltage vectors V1, V2, V3, V4, V5, and V6, each having a magnitude of (2/3) 1/2 ⁇ 2 Vdc and having different directions. Furthermore, the group of voltage vectors consists of 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, each having a magnitude of (2/3) 1/2 ⁇ Vdc, Contains V12p and V12n.
  • a group of voltage vectors consists of six voltage vectors V13, V14, V15, V16, V17, and V18, each with a magnitude of (2/3) 1/2 3 1/2 Vdc and different directions.
  • the angle between two adjacent voltage vectors among six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees.
  • the angle between two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is 60 degrees.
  • FIG. 35 is a vector diagram showing a group of voltage vectors on orthogonal dq coordinates.
  • a group of voltage vectors represents the first switching state, the second switching state, and the third switching state with the symbols "P", "0", and "N", respectively, and the U-phase, V-phase, and W-phase. When written in order, it can be expressed as shown in FIG.
  • the three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o[000], respectively.
  • V0p[PPP] with respect to the zero vector V0p, the switching state of the U-phase inverter circuit 1Ua is "P", the switching state of the V-phase inverter circuit 1Va is "P”, and the switching state of the W-phase inverter circuit 1Ua is "P". It expresses that the switching state of 1Wa is "P".
  • a voltage vector appended with "p” such as V10p includes "P" and does not include "N". This point is the same below.
  • a voltage vector with an "n” attached thereto such as V10n, includes “N” and does not include “P”. This point is the same below.
  • a voltage vector with an "o” attached such as V10o, includes “0” and does not include “P” and “N”.
  • the switching state of the inverter circuit 1a is "P"
  • the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the positive electrode P1 of the DC power supply section 3.
  • the switching state of the inverter circuit 1a is "N”
  • the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the negative electrode N1 of the DC power supply section 3.
  • the switching state of the inverter circuit 1a is "0"
  • the potential of the connection point 13a in the inverter circuit 1a becomes the potential of the intermediate potential point M1 of the DC power supply section 3.
  • V1, V2, V3, V4, V5, and V6 are V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP, respectively. ] It can be expressed as "p”, "n” after the number “V”, such as V1 [PNN], V2 [PPN], V3 [NPN], V4 [NPP], V5 [NNP], V6 [PNP], Voltage vectors without any "o” include “P” and "N” as three-phase switching states.
  • the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n are V7p[P00], V7n[0NN], V8p[PP0], and V8n, respectively. [00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0].
  • V13, V14, V15, V16, V17, and V18 are V13[P0N], V14[0PN], V15[NP0], V16[N0P], V17[0NP], and V18[PN0, respectively. ] It can be expressed as
  • the control unit 60a converts the instantaneous value of the command voltage regarding the output voltage of each of the plurality of inverter circuits 1a into a command voltage vector V * (see FIG. 37). If the d-axis component of the command voltage vector V * on the orthogonal d-q coordinates is Vd, and the q-axis component of the command voltage vector V * on the orthogonal d-q coordinates is Vq, then the command voltage vector V * is It can be determined using equation (4).
  • the control unit 60a selects a plurality (for example, five) of voltage vectors adjacent to the command voltage vector V * from among the group of voltage vectors.
  • the plurality of voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].
  • the control unit 60a selects two first voltage vectors VV1 (in the examples of FIGS. 37 and 38A, V8p [PP0] and V8n [ 00N]), a zero vector V0n[NNN] of a combination in which the potential level of the connection point 13a of the plurality of inverter circuits 1a is a negative potential, and a first voltage vector in the same direction as the first voltage vector VV1.
  • At least one second voltage vector VV2 (in the example of FIG. 38A, V2[PPN]) having a different magnitude from VV1.
  • the reference size is, for example, (2/3) 1/2 ⁇ Vdc.
  • the plurality of voltage vectors are 12 voltage vectors V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p as voltage vectors (reference vectors) whose magnitude is the reference magnitude. [0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0].
  • the angle between the two first voltage vectors VV1 closest to the command voltage vector V * and the command voltage vector V * is smaller than 30 degrees.
  • the control unit 60a controls three voltage vectors (in the example of FIG. 38B, V13[P0N]) other than the first voltage vector VV1 (in the example of FIG. 38A, V8p[PP0] and V8n[00N]) among the plurality of voltage vectors. , V7p[P00] and V7n[0NN]), the zero vector V0n[NNN], and at least one second voltage vector VV2 at a predetermined control period so as to match the command voltage vector V * .
  • Ts see FIG. 41
  • a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a are controlled.
  • the predetermined control period Ts is, for example, two periods of the carrier signal.
  • the composite vector of the vectors at the vertices of an equilateral triangle surrounding the command voltage vector V * is Match the voltage vector V * . That is, in the comparative example, one of the two first voltage vectors VV1 (in the example of FIG. 38A, V8p[PP0] and V8n[00N]), the voltage vector V13[P0N], the voltage vector V7p[P00] and The composite vector of V7n[0NN] is made to match the command voltage vector V * .
  • the control period Ts is one period of the carrier signal.
  • voltage vector Va is voltage vector V8p[PP0] and V8n[00N]
  • voltage vector Vb is voltage vector V13[P0N]
  • voltage vector Vc is voltage vector V8p[PP0] and V8n[00N].
  • the third switching element Q3a is in the ON state during the entire period within the control period Ts, and the voltage drop width of the second bootstrap circuit 72a becomes large.
  • voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ The voltage vectors are output in the following order: voltage vector V7p[P00] ⁇ voltage vector V8p[PP0] ⁇ voltage vector V8p[PP0] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ voltage vector V8n[00N].
  • the control unit 60a replaces the voltage vectors V8p[PP0] and V8p[PP0] in the comparative example with the zero vector V0n[NNN] and the second voltage vector VV2 (V2[PPN]), as shown in FIG.
  • a period in which the U-phase switching state is "N" can be generated.
  • the multilevel inverter 100a according to the third embodiment as shown in FIG. 42, both the first switching element Q1a and the third switching element Q3a are in the off state, and the second switching element Q2a and the fourth switching element A third switching state can be generated in which both Q4a are in the on state. Therefore, the multilevel inverter 100a according to the third embodiment can suppress the voltage drop of the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.
  • the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.
  • voltage vector V8p[PP0] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ voltage vector The voltage vectors are output in the order of V7p[P00] ⁇ voltage vector V8p[PP0].
  • FIG. 43 as in the example of FIG.
  • the distribution time of voltage vectors V8p and V8n is T0
  • the distribution time of voltage vector V13 is T1
  • the distribution time of voltage vectors V7p and V7n is T2.
  • An example is shown below.
  • the third switching state does not occur during the entire period within the control period Ts, and the voltage drop width of the capacitor C11 of the first bootstrap circuit 71a and the second bootstrap circuit 72a increases. It ends up.
  • control unit 60a of the multilevel inverter 100a within two cycles of the carrier signal, for example, as shown in FIG. 45, voltage vector V2[PPN] ⁇ voltage vector V7p[P00] ⁇
  • the voltage vectors are output in the following order: voltage vector V13[P0N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ voltage vector V7p[P00] ⁇ zero vector V0n[NNN].
  • the control unit 60a replaces the voltage vectors V8p[PP0] and V8p[PP0] in the example of FIG.
  • the multilevel inverter 100a according to the third embodiment can generate the third switching state within the control period Ts, as shown in FIG. 46. Therefore, the multilevel inverter 100a according to the third embodiment can suppress the voltage drop of the capacitor C11 of the first bootstrap circuit 71a and the capacitor C21 of the second bootstrap circuit 72a.
  • the control unit 60a sets one of the two first voltage vectors VV1 to a zero vector when the polarity of the command voltage corresponding to the command voltage vector V * is positive. V0n[NNN] and the second voltage vector VV2.
  • the control unit 60a converts the first voltage vector VV1 into the zero vector V0n[NNN] and the second voltage vector. Do not replace with VV2.
  • the control unit 60a controls the plurality of first gate drivers so that the output voltages of the plurality of first bootstrap circuits 71a and the plurality of second bootstrap circuits 72a do not fall below a predetermined value.
  • 61a a plurality of second gate drivers 62a, a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a.
  • the control unit 60a controls a plurality (5) of voltage vectors (for example, V8p) adjacent to the command voltage vector V * among a group (27) of voltage vectors. [PP0], V8n[00N], V13[P0N], V7p[P00], V7n[0NN]). Each of the group of voltage vectors is determined by a combination of potential levels at the connection points 13a in the plurality of inverter circuits 1a.
  • the control unit 60a controls one first voltage vector VV1 among the two first voltage vectors VV1 whose size is the reference size and is closest to the command voltage vector V * among the plurality of voltage vectors to the plurality of inverter circuits 1a.
  • the control unit 60a controls voltage vectors other than the first voltage vector VV1 among the plurality of voltage vectors, the remaining first voltage vector VV1 of the two first voltage vectors VV1, the zero vector V0n[NNN], and the second voltage vector.
  • a plurality of first gate drivers 61a, a plurality of second gate drivers 62a, and a plurality of third gate drivers 63a are operated within a predetermined control period Ts so that the composite vector of vector VV2 and vector VV2 matches the command voltage vector V * .
  • a plurality of fourth gate drivers 64a are controlled.
  • the multilevel inverter 100a according to the third embodiment it is possible to suppress voltage drop in the bootstrap circuit. More specifically, according to the multilevel inverter 100a according to the third embodiment, it is possible to suppress the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a. becomes.
  • the DC-DC converter 91a included in the power supply section 9a includes a plurality of second gate drivers 62a, a plurality of first bootstrap circuits 71a, and a plurality of second bootstrap circuits. A voltage is supplied to 72a.
  • the multilevel inverter 100a according to the third embodiment can be made smaller.
  • the control unit 60a controls two first voltage vectors VV1 (V8n[00N] shown in FIG. 39, One first voltage vector VV1 (V8n[00N]) of V8p[PP0]) is replaced with a zero vector V0n[NNN], and the remaining one first voltage vector VV1(V8p[PP0]) is replaced with a second voltage vector Replace with VV2 (V2[PPN]).
  • VV1 V8n[00N]
  • V8p[PP0] the control unit 60a of the multilevel inverter 100a according to the fourth embodiment, within two cycles of the carrier signal, as shown in FIG.
  • the control unit 60a converts the voltage vectors V8n[00N], V8p[PP0], V8p[PP0], and V8n[00N] in the example of FIG. 39 into zero vectors V0n[NNN], voltage vectors V2[PPN], and voltage vectors, respectively. Since V2[PPN] is replaced with the zero vector V0n[NNN], a period in which the U-phase switching state is "N" can be generated, as shown in FIG.
  • the multilevel inverter 100a according to the fourth embodiment can generate the third switching state within the control period Ts, as shown in FIG. 48. Therefore, the multilevel inverter 100a according to the fourth embodiment can suppress the voltage drop of the capacitor C21 of the second bootstrap circuit 72a.
  • the control unit 60 controls the two first voltage vectors VV1 (V8n[00N], V8p[PP0]) in FIG. Among them, only one first voltage vector VV1 (V8p[PP0]) is replaced with a zero vector V0n[NNN] and a second voltage vector VV2 (V2[PPN]).
  • the control unit 60a controls the two first voltage vectors VV1 (V8n[00N], V8p[ PP0]), one first voltage vector VV1 (V8n[00N]) is replaced with a zero vector V0n[NNN], and the remaining one first voltage vector VV1 (V8p[PP0]) is replaced with a second voltage vector VV2. (V2[PPN]).
  • V2[PPN] the control unit 60a of the multilevel inverter 100a according to the fourth embodiment, within two cycles of the carrier signal, as shown in FIG.
  • the voltage vectors are output in the following order: [P00] ⁇ voltage vector V2[PPN] ⁇ voltage vector V2[PPN] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ zero vector V0n[NNN].
  • the voltage vectors V8p[PP0], V8n[00N], V8n[00N], and V8p[PP0] in the example of FIG. 43 are converted into voltage vectors V0n[NNN], V2[PPN], and V2[PPN], respectively.
  • V0n[NNN] it is possible to generate a period in which the switching state of the U phase is "N", as shown in FIG.
  • the multilevel inverter 100a according to the fourth embodiment can generate the third switching state within the control period Ts, as shown in FIG. 48. Therefore, the multilevel inverter 100a according to the fourth embodiment can suppress the voltage drop of the capacitor C21 of the second bootstrap circuit 72a.
  • the control unit 60a selects each of the two first voltage vectors VV1 whose size is the reference size and is closest to the command voltage vector V * among the plurality of voltage vectors.
  • the control unit 60a causes a composite vector of voltage vectors other than the first voltage vector VV1 among the plurality of voltage vectors, the zero vector V0 [NNN], and the second voltage vector VV2 to match the command voltage vector V * . Then, the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, the plurality of third gate drivers 63a, and the plurality of fourth gate drivers 64a are controlled within a predetermined control period Ts.
  • the multilevel inverter 100a according to the fourth embodiment it is possible to suppress voltage drop in the bootstrap circuit. More specifically, according to the multilevel inverter 100a according to the fourth embodiment, it is possible to suppress the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a. becomes.
  • the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.
  • voltage vector V8p[PP0] ⁇ voltage vector V7p[P00] ⁇ voltage vector V13[P0N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V8n[00N] ⁇ voltage vector V13[P0N] ⁇ voltage vector The voltage vectors are output in the order of V7p[P00] ⁇ voltage vector V8p[PP0].
  • FIG. 43 as in the example of FIG.
  • the distribution time of voltage vectors V8p and V8n is T0
  • the distribution time of voltage vector V13 is T1
  • the distribution time of voltage vectors V7p and V7n is T2.
  • An example is shown below. In this case, as shown in FIG. 44, the third switching state does not occur during the entire period within the control period Ts, and the voltage drop width of the second bootstrap circuit 72a becomes large.
  • control unit 60a of the multilevel inverter 100a within two cycles of the carrier signal, for example, as shown in FIG. 49, voltage vector V2[PPN] ⁇ voltage vector V7p[P00] ⁇
  • the voltage vectors are output in the following order: voltage vector V13[P0N] ⁇ voltage vector V0n[NNN] ⁇ voltage vector V0n[NNN] ⁇ voltage vector V13[P0N] ⁇ voltage vector V7p[P00] ⁇ voltage vector V2[PPN].
  • the control unit 60a replaces the voltage vectors V8p[PP0] and V8n[00N] in the example of FIG.
  • the multilevel inverter 100a according to the fourth embodiment can generate the third switching state within the control period Ts, as shown in FIG. 50. Therefore, the multilevel inverter 100a according to the fourth embodiment can suppress the voltage drop of the capacitor C21 of the second bootstrap circuit 72a.
  • Embodiment 5 A multilevel inverter 100A according to Embodiment 5 will be described with reference to FIG. 51.
  • the same components as those of the multilevel inverter 100a according to the third embodiment (see FIG. 26) are designated by the same reference numerals, and the description thereof will be omitted.
  • the multilevel inverter 100A differs from the multilevel inverter 100a in that the power supply section 9a includes a plurality (three) of DC-DC converters 91a.
  • the plurality of DC-DC converters 91a correspond to the plurality of (three) fourth gate drivers 64a and supply voltage to the corresponding fourth gate drivers 64a. Furthermore, in the multilevel inverter 100A, the plurality of DC-DC converters 91a correspond to the plurality of first bootstrap circuits 71a and are connected to the corresponding first bootstrap circuits 71a. More specifically, in each of the plurality of DC-DC converters 91a, the positive side terminal is connected to the anode of the diode D11 in the corresponding first bootstrap circuit 71a, and the negative side terminal is connected to the DC power supply section 3. is connected to the negative electrode N1 of.
  • control unit 60a performs the same voltage vector control as the control unit 60a of the multilevel inverter 100a, thereby controlling the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, and the plurality of third gate drivers.
  • a gate driver 63a and a plurality of fourth gate drivers 64a are controlled.
  • the multilevel inverter 100A suppresses the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a. becomes possible.
  • FIG. 52 A multilevel inverter 100B according to the sixth embodiment will be described with reference to FIG. 52.
  • the same components as those of the multilevel inverter 100a (see FIG. 26) according to the third embodiment are denoted by the same reference numerals, and the description thereof will be omitted.
  • a bidirectional switch including a third switching element Q3a and a fourth switching element Q4a is configured such that the first main terminals (source terminals) of the third switching element Q3a and the fourth switching element Q4a are connected to each other. It is a common drain bidirectional switch.
  • the second main terminal of fourth switching element Q4a is connected to intermediate potential point M1
  • third switching element Q3a is connected to connection point 13a.
  • the power supply section 9a includes a plurality (three) of second DC-DC converters 92 in addition to a DC-DC converter 91a (hereinafter also referred to as a first DC-DC converter 91a). Note that in FIG. 52, each of the plurality of second DC-DC converters 92 is illustrated with a symbol of a DC power supply.
  • the first DC-DC converter 91a supplies voltage to the plurality of second gate drivers 62a, the plurality of first bootstrap circuits 71a, and the plurality of second bootstrap circuits 72a.
  • the plurality of second DC-DC converters 92 correspond one-to-one to the plurality of fourth gate drivers 64a, and supply voltage to the corresponding fourth gate drivers 64a.
  • the second DC-DC converter 92 has a positive terminal connected to the high potential power supply terminal of the fourth gate driver 64a, and a negative terminal connected to the intermediate potential point M1 and the low potential power supply terminal of the fourth gate driver 64a. terminal and the second main terminal of the fourth switching element Q4a.
  • control unit 60a performs the same voltage vector control as the control unit 60a of the multilevel inverter 100a, thereby controlling the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, and the plurality of third gate drivers.
  • a gate driver 63a and a plurality of fourth gate drivers 64a are controlled.
  • the multilevel inverter 100B suppresses the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a and the capacitor C21 of the plurality of second bootstrap circuits 72a. becomes possible.
  • Embodiment 7 A multilevel inverter 100C according to Embodiment 7 will be described with reference to FIG. 53.
  • the same components as those of the multilevel inverter 100a (see FIG. 26) according to the third embodiment are given the same reference numerals, and the description thereof will be omitted.
  • the multilevel inverter 100C does not include the plurality of second bootstrap circuits 72a in the multilevel inverter 100a, and the power supply section 9a includes a DC-DC converter 91a (hereinafter also referred to as the first DC-DC converter 91a). , has a plurality (three) of second DC-DC converters 92. Note that in FIG. 53, each of the plurality of second DC-DC converters 92 is illustrated with a symbol of a DC power supply.
  • the first DC-DC converter 91a supplies voltage to the plurality of second gate drivers 62a, the plurality of first bootstrap circuits 71a, and the plurality of second bootstrap circuits 72a.
  • the plurality of second DC-DC converters 92 correspond to the plurality of third gate drivers 63a and the plurality of fourth gate drivers 64a, and supply voltage to the corresponding third gate drivers 63a and the corresponding fourth gate drivers 64a. do.
  • Each of the plurality of second DC-DC converters 92 has its positive terminal connected to the high potential power terminal of the corresponding third gate driver 63a and the high potential power terminal of the corresponding fourth gate driver 64a. .
  • each of the plurality of second DC-DC converters 92a has its negative terminal connected to the low potential side power supply terminal of the corresponding third gate driver 63a and the low potential side power supply terminal of the corresponding fourth gate driver 64a. ing.
  • control unit 60a performs the same voltage vector control as the control unit 60a of the multilevel inverter 100a, thereby controlling the plurality of first gate drivers 61a, the plurality of second gate drivers 62a, and the plurality of third gate drivers.
  • a gate driver 63a and a plurality of fourth gate drivers 64a are controlled.
  • the multilevel inverter 100C according to the seventh embodiment can suppress the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a.
  • FIG. 54 A multilevel inverter 100D according to the eighth embodiment will be described with reference to FIG. 54.
  • the same components as the multilevel inverter 100C according to the seventh embodiment are designated by the same reference numerals, and the description thereof will be omitted.
  • the first DC-DC converter 91a is not connected to the plurality of first bootstrap circuits 71a, and the positive terminal of the second DC-DC converter 92 is connected to the anode of the diode D11 of the first bootstrap circuit 71a. It is connected to the.
  • control unit 60a performs the same voltage vector control as the control unit 60a of the multilevel inverter 100a according to the third embodiment, thereby controlling the plurality of first gate drivers 61a and the plurality of second gate drivers 62a. , a plurality of third gate drivers 63a, and a plurality of fourth gate drivers 64a.
  • the multilevel inverter 100D according to the eighth embodiment can suppress the voltage drop of the capacitor C11 of the plurality of first bootstrap circuits 71a.
  • Embodiments 3 to 8 above are just one of various embodiments of the present disclosure. Embodiments 3 to 8 described above can be modified in various ways depending on the design, etc., as long as the objective of the present disclosure can be achieved.
  • each of the plurality of first switching elements Q1a, the plurality of second switching elements Q2a, the plurality of third switching elements Q3a, and the plurality of fourth switching elements Q4a are not limited to MOSFETs, but are, for example, IGBTs (Insulated Gate Bipolar Transistors).
  • the control terminal, the first main terminal, and the second main terminal in each of the plurality of first switching elements Q1a, the plurality of second switching elements Q2a, the plurality of third switching elements Q3a, and the plurality of fourth switching elements Q4a. are the gate terminal, collector terminal and emitter terminal, respectively.
  • the control unit 60a is controlled not only when the polarity of the command voltage corresponding to the command voltage vector V * is negative, but also when the polarity of the command voltage corresponding to the command voltage vector V* is negative.
  • the first voltage vector VV1 may be replaced with a zero vector V0n[NNN] and a second voltage vector VV2.
  • each of the plurality of first bootstrap circuits 71a includes the Zener diode Z11, but may have a configuration that does not include the Zener diode Z11.
  • each of the plurality of second bootstrap circuits 72a includes the Zener diode Z21, but may have a configuration that does not include the Zener diode Z21.
  • the multilevel inverter 100a may be a multilevel inverter of three or more levels, and may be a five-level inverter, for example.
  • the multilevel inverter (100) includes a DC power supply section (3), a plurality of inverter circuits (1), and a control device (6).
  • the DC power supply section (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1).
  • a plurality of inverter circuits (1) are connected between a positive electrode (P1) and a negative electrode (N1) of a DC power supply section (3).
  • a control device (6) controls a plurality of inverter circuits (1).
  • Each of the plurality of inverter circuits (1) includes a switching circuit (10), a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), It has a fifth diode (D5) and a sixth diode (D6).
  • a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected from the positive electrode (P1) side to the negative electrode (N1).
  • a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series so as to be lined up in this order on the side.
  • the first diode (D1) is connected in antiparallel to the first switching element (Q1).
  • the second diode (D2) is connected in antiparallel to the second switching element (Q2).
  • the third diode (D3) is connected in antiparallel to the third switching element (Q3).
  • the fourth diode (D4) is connected in antiparallel to the fourth switching element (Q4).
  • the fifth diode (D5) has a cathode connected to the first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and an anode connected to the intermediate potential point (M1). has been done.
  • the sixth diode (D6) has an anode connected to the second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and a cathode connected to the intermediate potential point (M1). has been done.
  • the control device (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64). , a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply section (9), and a control section (60).
  • the plurality of first gate drivers (61) drive the first switching elements (Q1) of each of the plurality of inverter circuits (1).
  • the plurality of second gate drivers (62) drive the second switching elements (Q2) of each of the plurality of inverter circuits (1).
  • the plurality of third gate drivers (63) drive each third switching element (Q3) of the plurality of inverter circuits (1).
  • the plurality of fourth gate drivers (64) drive each fourth switching element (Q4) of the plurality of inverter circuits (1).
  • the plurality of first bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61) and supply voltage to the corresponding first gate drivers (61).
  • the plurality of second bootstrap circuits (72) correspond one-to-one to the plurality of second gate drivers (62) and supply voltage to the corresponding second gate drivers (62).
  • the plurality of third bootstrap circuits (73) correspond one-to-one to the plurality of third gate drivers (63) and supply voltage to the corresponding third gate drivers (63).
  • the power supply section (9) supplies voltage to the plurality of fourth gate drivers (64).
  • the control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64).
  • the control unit (60) selects a plurality of voltage vectors adjacent to the command voltage vector (V * ) from among the group of voltage vectors.
  • Each of the group of voltage vectors is determined by a combination of potential levels at the third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1).
  • the control unit (60) selects one first voltage vector (VV1) among the two first voltage vectors (VV1) whose size is the reference size and is closest to the command voltage vector (V * ) among the plurality of voltage vectors. ) is zero in a combination in which the potential level of the third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1) is the potential of the negative electrode (N1).
  • the control unit (60) controls voltage vectors other than the first voltage vector (VV1) among the plurality of voltage vectors, the remaining first voltage vector (VV1) of the two first voltage vectors (VV1), and the zero vector (
  • the capacitors (C17) of the plurality of first bootstrap circuits (71), the capacitors (C27) of the plurality of second bootstrap circuits (72), and the plurality of third bootstrap circuits It becomes possible to suppress the voltage drop of the capacitor (C37) in (73).
  • the multilevel inverter (100) includes a DC power supply section (3), a plurality of inverter circuits (1), and a control device (6).
  • the DC power supply section (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1).
  • a plurality of inverter circuits (1) are connected between a positive electrode (P1) and a negative electrode (N1) of a DC power supply section (3).
  • a control device (6) controls a plurality of inverter circuits (1).
  • Each of the plurality of inverter circuits (1) includes a switching circuit (10), a first diode (D1), a second diode (D2), a third diode (D3), a fourth diode (D4), It has a fifth diode (D5) and a sixth diode (D6).
  • a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected from the positive electrode (P1) side to the negative electrode (N1).
  • a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) are connected in series so as to be lined up in this order on the side.
  • the first diode (D1) is connected in antiparallel to the first switching element (Q1).
  • the second diode (D2) is connected in antiparallel to the second switching element (Q2).
  • the third diode (D3) is connected in antiparallel to the third switching element (Q3).
  • the fourth diode (D4) is connected in antiparallel to the fourth switching element (Q4).
  • the fifth diode (D5) has a cathode connected to the first connection point (11) between the first switching element (Q1) and the second switching element (Q2), and an anode connected to the intermediate potential point (M1). has been done.
  • the sixth diode (D6) has an anode connected to the second connection point (12) between the third switching element (Q3) and the fourth switching element (Q4), and a cathode connected to the intermediate potential point (M1). has been done.
  • the control device (6) includes a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64). , a plurality of first bootstrap circuits (71), a plurality of second bootstrap circuits (72), a power supply section (9), and a control section (60).
  • the plurality of first gate drivers (61) drive the first switching elements (Q1) of each of the plurality of inverter circuits (1).
  • the plurality of second gate drivers (62) drive the second switching elements (Q2) of each of the plurality of inverter circuits (1).
  • the plurality of third gate drivers (63) drive each third switching element (Q3) of the plurality of inverter circuits (1).
  • the plurality of fourth gate drivers (64) drive each fourth switching element (Q4) of the plurality of inverter circuits (1).
  • the plurality of first bootstrap circuits (71) correspond one-to-one to the plurality of first gate drivers (61) and supply voltage to the corresponding first gate drivers (61).
  • the plurality of second bootstrap circuits (72) correspond one-to-one to the plurality of second gate drivers (62) and supply voltage to the corresponding second gate drivers (62).
  • the plurality of third bootstrap circuits (73) correspond one-to-one to the plurality of third gate drivers (63) and supply voltage to the corresponding third gate drivers (63).
  • the power supply section (9) supplies voltage to the plurality of fourth gate drivers (64).
  • the control unit (60) controls a plurality of first gate drivers (61), a plurality of second gate drivers (62), a plurality of third gate drivers (63), and a plurality of fourth gate drivers (64).
  • the control unit (60) selects a plurality of voltage vectors adjacent to the command voltage vector (V * ) from among the group of voltage vectors.
  • Each of the group of voltage vectors is determined by a combination of potential levels at the third connection point (13) between the second switching element (Q2) and the third switching element (Q3) of the plurality of inverter circuits (1).
  • the control unit (60) selects a first voltage vector (VV1), which has a reference size among the plurality of voltage vectors and is closest to the command voltage vector (V * ), to a second voltage vector of the plurality of inverter circuits (1).
  • the control unit (60) commands a composite vector of voltage vectors other than the first voltage vector (VV1) among the plurality of voltage vectors, the zero vector (Vo[NNN]), and the second voltage vector (VV2).
  • a plurality of first gate drivers (61), a plurality of second gate drivers (62), and a plurality of third gate drivers (63) are operated within a predetermined control period (Ts) so as to match the voltage vector (V * ). and a plurality of fourth gate drivers (64).
  • the capacitor (C17) of the plurality of first bootstrap circuits (71), the capacitor (C27) of the plurality of second bootstrap circuits (72), and the plurality of third bootstrap circuits It becomes possible to suppress the voltage drop of the capacitor (C37) in (73).
  • the control unit (60) One voltage vector (VV1) is replaced with a zero vector (V0n[NNN]) and a second voltage vector (VV2).
  • the number of times the first voltage vector (VV1) is replaced with the zero vector (V0n[NNN]) and the second voltage vector (VV2) can be reduced.
  • the control unit (60) includes a plurality of first bootstrap circuits (71) and a plurality of second bootstrap circuits (71).
  • each of the plurality of first bootstrap circuits (71) and the plurality of second bootstrap circuits (72) includes a capacitor (C17), a diode (D17), and a resistor (R17).
  • the diode (D17) is connected in series with the capacitor (C17).
  • the resistor (R17) is connected in series to the capacitor (C17).
  • the power supply section (9) includes a DC-DC converter (91).
  • the DC-DC converter (91) supplies voltage to the plurality of fourth gate drivers (64) and the plurality of third bootstrap circuits (73).
  • the multilevel inverter (100a; 100A; 100B; 100C; 100D) includes a DC power supply section (3), a plurality of inverter circuits (1a), and a control device (6a).
  • the DC power supply section (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1).
  • the plurality of inverter circuits (1a) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply section (3).
  • a control device (6a) controls a plurality of inverter circuits (1a).
  • Each of the plurality of inverter circuits (1a) includes a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a), a fourth switching element (Q4a), and a first diode (D1a). , a second diode (D2a), a third diode (D3a), and a fourth diode (D4a).
  • the first diode (D1a), the second diode (D2a), the third diode (D3a), and the fourth diode (D4a) are the first switching element (Q1a), the second switching element (Q2a), and the third switching element ( Q3a) and the fourth switching element (Q4a), respectively, in antiparallel connection.
  • the first switching element (Q1a) and the second switching element (Q2a) are switched from the positive electrode (P1) side to the negative electrode (N1) side.
  • the switching elements (Q2a) are connected in series so as to be lined up in this order.
  • a series circuit of a third switching element (Q3a) and a fourth switching element (Q4a) is connected between an intermediate potential point (M1) and an output point.
  • the output point is a connection point (13a) between the first switching element (Q1a) and the second switching element (Q2a).
  • the control device (6a) includes a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), and a plurality of fourth gate drivers (64a). , a plurality of bootstrap circuits (71a), a power supply section (9a), and a control section (60a).
  • the plurality of first gate drivers (61a) drive each first switching element (Q1a) of the plurality of inverter circuits (1a).
  • the plurality of second gate drivers (62a) drive the second switching elements (Q2a) of each of the plurality of inverter circuits (1a).
  • the plurality of third gate drivers (63a) drive each third switching element (Q3a) of the plurality of inverter circuits (1a).
  • the plurality of fourth gate drivers (64a) drive the fourth switching elements (Q4a) of each of the plurality of inverter circuits (1a).
  • the plurality of bootstrap circuits (71a) correspond one-to-one to the plurality of first gate drivers (61a), and supply voltage to the corresponding first gate drivers (61a).
  • the power supply section (9a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of third gate drivers (63a).
  • the control unit (60a) controls a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), and a plurality of fourth gate drivers (64a).
  • the control unit (60a) selects a plurality of voltage vectors adjacent to the command voltage vector (V * ) from among the group of voltage vectors. Each of the group of voltage vectors is determined by a combination of potential levels at a plurality of connection points (13a) in a plurality of inverter circuits (1a). The control unit (60a) selects one first voltage vector (VV1) among the two first voltage vectors (VV1) whose size is the reference size and is closest to the command voltage vector (V * ) among the plurality of voltage vectors.
  • VV1 is a zero vector (V0n [NNN]) and a first voltage vector (VV1) in which the potential level of the plurality of connection points (13a) in the plurality of inverter circuits (1a) is the potential of the negative electrode (N1).
  • VV2 having the same direction and twice the size of the first voltage vector (VV1) is substituted.
  • the control unit (60) controls voltage vectors other than the first voltage vector (VV1) among the plurality of voltage vectors, the remaining first voltage vector (VV1) of the two first voltage vectors (VV1), and the zero vector (
  • the bootstrap circuit (71a) it is possible to suppress a voltage drop in the bootstrap circuit (71a). More specifically, according to this aspect, it is possible to suppress the voltage drop of the capacitor (C11) of the plurality of bootstrap circuits (71a).
  • the multilevel inverter (100a; 100A; 100B; 100C; 100D) includes a DC power supply section (3), a plurality of inverter circuits (1a), and a control device (6a).
  • the DC power supply section (3) has a positive electrode (P1), a negative electrode (N1), and an intermediate potential point (M1).
  • the plurality of inverter circuits (1a) are connected between the positive electrode (P1) and the negative electrode (N1) of the DC power supply section (3).
  • a control device (6a) controls a plurality of inverter circuits (1a).
  • Each of the plurality of inverter circuits (1a) includes a first switching element (Q1a), a second switching element (Q2a), a third switching element (Q3a), a fourth switching element (Q4a), and a first diode (D1a). , a second diode (D2a), a third diode (D3a), and a fourth diode (D4a).
  • the first diode (D1a), the second diode (D2a), the third diode (D3a), and the fourth diode (D4a) are the first switching element (Q1a), the second switching element (Q2a), and the third switching element ( Q3a) and the fourth switching element (Q4a), respectively, in antiparallel connection.
  • the first switching element (Q1a) and the second switching element (Q2a) are switched from the positive electrode (P1) side to the negative electrode (N1) side.
  • the switching elements (Q2a) are connected in series so as to be lined up in this order.
  • a series circuit of a third switching element (Q3a) and a fourth switching element (Q4a) is connected between an intermediate potential point (M1) and an output point.
  • the output point is a connection point (13a) between the first switching element (Q1a) and the second switching element (Q2a).
  • the control device (6a) includes a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), and a plurality of fourth gate drivers (64a). , a plurality of bootstrap circuits (71a), a power supply section (9a), and a control section (60a).
  • the plurality of first gate drivers (61a) drive each first switching element (Q1a) of the plurality of inverter circuits (1a).
  • the plurality of second gate drivers (62a) drive the second switching elements (Q2a) of each of the plurality of inverter circuits (1a).
  • the plurality of third gate drivers (63a) drive each third switching element (Q3a) of the plurality of inverter circuits (1a).
  • the plurality of fourth gate drivers (64a) drive the fourth switching elements (Q4a) of each of the plurality of inverter circuits (1a).
  • the plurality of bootstrap circuits (71a) correspond one-to-one to the plurality of first gate drivers (61a), and supply voltage to the corresponding first gate drivers (61a).
  • the power supply section (9a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of third gate drivers (63a).
  • the control unit (60a) controls a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), a plurality of third gate drivers (63a), and a plurality of fourth gate drivers (64a).
  • the control unit (60a) selects a plurality of voltage vectors adjacent to the command voltage vector (V * ) from among the group of voltage vectors. Each of the group of voltage vectors is determined by a combination of potential levels at a plurality of connection points (13a) in a plurality of inverter circuits (1a).
  • the control unit (60a) controls each of the two first voltage vectors (VV1) whose size is the reference size and is closest to the command voltage vector (V * ) among the plurality of voltage vectors to the plurality of inverter circuits (1a).
  • the control unit (60a) commands a composite vector of voltage vectors other than the first voltage vector (VV1) among the plurality of voltage vectors, the zero vector (V0[NNN]), and the second voltage vector (VV2).
  • a plurality of first gate drivers (61a), a plurality of second gate drivers (62a), and a plurality of third gate drivers (63a) are operated within a predetermined control period (Ts) so as to match the voltage vector (V * ). and a plurality of fourth gate drivers (64a).
  • the bootstrap circuit (71a) it is possible to suppress a voltage drop in the bootstrap circuit (71a). More specifically, according to this aspect, it is possible to suppress the voltage drop of the capacitor (C11) of the plurality of bootstrap circuits (71a).
  • the control unit (60a) One voltage vector (VV1) is replaced with a zero vector (V0n[NNN]) and a second voltage vector (VV2).
  • the number of times the first voltage vector (VV1) is replaced with the zero vector (V0n[NNN]) and the second voltage vector (VV2) can be reduced.
  • the control unit (60a) includes a plurality of bootstrap circuits (71a).
  • each of the plurality of bootstrap circuits (71a) includes a capacitor (C11 ), a diode (D11), and a resistor (R11).
  • the diode (D11) is connected in series with the capacitor (C11).
  • the resistor (R11) is connected in series to the capacitor (C11).
  • the power supply section (9a) operates one DC-DC converter (91a).
  • the DC-DC converter (91a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of bootstrap circuits (71a).
  • the power supply section (9a) includes one first DC-DC converter (91a). and a plurality of second DC-DC converters (92).
  • the first DC-DC converter (91a) supplies voltage to the plurality of second gate drivers (62a) and the plurality of bootstrap circuits (71a).
  • the plurality of second DC-DC converters (92) supply voltage to the plurality of fourth gate drivers (64a).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
PCT/JP2023/030963 2022-09-09 2023-08-28 マルチレベルインバータ Ceased WO2024053452A1 (ja)

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EP23862991.9A EP4586489A4 (en) 2022-09-09 2023-08-28 MULTI-LEVEL INVERTER
CN202380059840.2A CN119731927A (zh) 2022-09-09 2023-08-28 多电平逆变器
US19/106,080 US20260081539A1 (en) 2022-09-09 2023-08-28 Multi-level inverter

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WO2024253051A1 (ja) * 2023-06-09 2024-12-12 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2025004696A1 (ja) * 2023-06-27 2025-01-02 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2025249443A1 (ja) * 2024-05-31 2025-12-04 パナソニックＩｐマネジメント株式会社 スイッチング素子駆動回路及び電力変換装置
WO2026018574A1 (ja) * 2024-07-16 2026-01-22 パナソニックＩｐマネジメント株式会社 スイッチング素子駆動回路及び電力変換装置
WO2026078955A1 (ja) * 2024-10-08 2026-04-16 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2026078954A1 (ja) * 2024-10-08 2026-04-16 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
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WO2024236980A1 (ja) * 2023-05-16 2024-11-21 パナソニックＩｐマネジメント株式会社 電力変換装置
WO2024253051A1 (ja) * 2023-06-09 2024-12-12 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2025004696A1 (ja) * 2023-06-27 2025-01-02 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2025249443A1 (ja) * 2024-05-31 2025-12-04 パナソニックＩｐマネジメント株式会社 スイッチング素子駆動回路及び電力変換装置
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WO2026078954A1 (ja) * 2024-10-08 2026-04-16 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ
WO2026078953A1 (ja) * 2024-10-08 2026-04-16 パナソニックＩｐマネジメント株式会社 マルチレベルインバータ

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US20260081539A1 (en) 2026-03-19
EP4586489A1 (en) 2025-07-16

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