WO2024053372A1 - Élément d'imagerie à semi-conducteurs et procédé de fabrication ainsi que dispositif électronique - Google Patents

Élément d'imagerie à semi-conducteurs et procédé de fabrication ainsi que dispositif électronique Download PDF

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Publication number
WO2024053372A1
WO2024053372A1 PCT/JP2023/029937 JP2023029937W WO2024053372A1 WO 2024053372 A1 WO2024053372 A1 WO 2024053372A1 JP 2023029937 W JP2023029937 W JP 2023029937W WO 2024053372 A1 WO2024053372 A1 WO 2024053372A1
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Prior art keywords
solid
state imaging
imaging device
wiring
pixel
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PCT/JP2023/029937
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English (en)
Japanese (ja)
Inventor
健士 石崎
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024053372A1 publication Critical patent/WO2024053372A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present disclosure relates to a solid-state image sensor, a manufacturing method, and an electronic device, and particularly relates to a solid-state image sensor, a manufacturing method, and an electronic device that can achieve higher image quality.
  • DRAM Dynamic Random Access Memory
  • Patent Document 1 discloses a DRAM element having a configuration in which one memory cell region having a plurality of capacitor elements is separated from a peripheral circuit region by a groove formed at the periphery of the memory cell region.
  • the present disclosure has been made in view of this situation, and is intended to make it possible to achieve higher image quality.
  • a solid-state imaging device includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel, and and an isolation section that electrically isolates the capacitors from each other.
  • a manufacturing method includes forming a three-dimensional capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; The method further includes forming an isolation portion that electrically isolates the capacitors from each other.
  • An electronic device includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
  • the solid-state imaging device includes a separation portion that electrically isolates the capacitors from each other.
  • a three-dimensional capacitor is provided between the upper wiring and the lower wiring of the wiring layer of the pixel for each of the plurality of pixels, and the capacitors of adjacent pixels are separated by the separation part. electrically isolated.
  • FIG. 2 is a circuit diagram illustrating an embodiment of a pixel included in an image sensor to which the present technology is applied.
  • FIG. 3 is a diagram illustrating a configuration example of a MIM capacitor when viewed from above.
  • FIG. 3 is a diagram illustrating a cross-sectional configuration example of a MIM capacitor. It is a figure explaining a 1st process. It is a figure explaining a 2nd process. It is a figure explaining a 3rd process. It is a figure explaining the 4th process. It is a figure explaining the 5th process. It is a figure explaining a 6th process. It is a figure explaining a 7th process. It is a figure explaining the 8th process.
  • FIG. 7 is a cross-sectional view showing a modified example of the MIM capacitor.
  • 1 is a block diagram showing a configuration example of an imaging device.
  • FIG. It is a figure which shows the example of use which uses an image sensor.
  • FIG. 1 shows a circuit diagram of the pixel 11.
  • the pixel 11 includes a photoelectric conversion section 12, a transfer transistor 13, a first FD (Floating Diffusion) section 14, a connection transistor 15, a second FD section 16, an MIM capacitor 17, a reset transistor 18, It is configured to include an amplification transistor 19 and a selection transistor 20, and outputs a pixel signal via a vertical signal line 21.
  • the pixel 11 is a LOFIC (Lateral Over Flow Integration Capacitor) pixel, which guides charges overflowing from the photoelectric conversion unit 12 in the lateral direction when it is irradiated with light strong enough to exceed the saturation capacity of the photoelectric conversion unit 12. It has a structure in which the energy is accumulated in the MIM capacitor 17.
  • the photoelectric conversion section 12 has an anode terminal grounded and a cathode terminal connected to the first FD section 14 via the transfer transistor 13.
  • the photoelectric conversion unit 12 receives light irradiated onto the light-receiving surface of the image sensor, and photoelectrically converts the light into an electric charge corresponding to the amount of light.
  • the transfer transistor 13 is arranged to connect the photoelectric conversion section 12 and the first FD section 14.
  • the transfer transistor 13 is driven according to the transfer signal TG, and transfers the charge photoelectrically converted by the photoelectric conversion section 12 to the first FD section 14.
  • the first FD section 14 accumulates charges transferred from the photoelectric conversion section 12 via the transfer transistor 13 in order to convert them into pixel signals.
  • connection transistor 15 is arranged to connect the first FD section 14 and the second FD section 16.
  • the connection transistor 15 is driven according to the connection signal FDG to turn on/off the connection between the first FD section 14 and the second FD section 16.
  • the second FD section 16 is connected to the first FD section 14 with the connection transistor 15 turned on, and accumulates charges together with the first FD section 14.
  • the MIM capacitor 17 is a capacitor with an MIM (Metal-Insulator-Metal) structure provided in the wiring layer of the image sensor, and is arranged to connect the second FD section 16 and the signal wiring MIMVDD. Then, the MIM capacitor 17 accumulates charge similarly to the second FD section 16. Furthermore, the MIM capacitor 17 has a plurality of cylindrical shapes (a shape in which a dielectric film is sandwiched between a cylindrical upper electrode and a cylindrical lower electrode, as will be explained with reference to FIGS. 2 and 3 later). It has a structure.
  • MIM Metal-Insulator-Metal
  • the reset transistor 18 is arranged to connect the second FD section 16 and the power supply wiring VDD. Then, the reset transistor 18 is driven according to the reset signal RST, and the connection transistor 15 and the reset transistor 18 are turned on, so that the data stored in the first FD section 14, the second FD section 16, and the MIM capacitor 17 is removed. The accumulated charge is discharged to the power supply wiring VDD to reset the charge.
  • the amplification transistor 19 is arranged so that the first FD section 14 is connected to the gate electrode, and the power supply wiring VDD and the selection transistor 20 are connected. Then, the amplification transistor 19 transfers the charges accumulated by the first FD section 14 or the charges accumulated by the first FD section 14, the second FD section 16, and the MIM capacitor 17 to each It is converted into a pixel signal with a level corresponding to the charge on the capacitor.
  • the selection transistor 20 is arranged to connect the amplification transistor 19 and the vertical signal line 21.
  • the selection transistor 20 is driven according to the selection signal SEL, and the pixel signal converted by the amplification transistor 19 is output to the vertical signal line 21 while the selection transistor 20 is on.
  • the connection transistor 15 when the connection transistor 15 is turned off according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is accumulated in the capacitance of only the first FD section 14. Ru. Further, when the connection transistor 15 is turned on according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is transferred to the first FD section 14, the second FD section 16, and the MIM. It is accumulated in the combined capacity of the capacitor 17. In this way, the pixel 11 having the structure in which the MIM capacitor 17 is provided can switch the capacitance for accumulating the charge transferred from the photoelectric conversion unit 12.
  • FIG. 2 shows a schematic configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2 when viewed from above. Note that the pixels 11-1 and 11-2 have the same configuration, and if there is no need to distinguish between them, they will be simply referred to as the pixel 11, and each part constituting the pixel 11 will also be referred to in the same manner.
  • the MIM capacitor 17 has a structure having a plurality of cylinder shapes, and in FIG. It represents the cylinder shape. Note that the cylinder shape of the MIM capacitor 17 is not limited to a circular shape, and may be, for example, a rectangular shape.
  • the pixel 11 is configured such that an isolation structure 31 is provided to surround the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between the isolation structures 31.
  • the MIM capacitors 17 of adjacent pixels 11 are configured to be electrically and physically isolated from each other by the isolation structure 31 and the interlayer insulating film 32. That is, as shown in the figure, the MIM capacitor 17-1 of the pixel 11-1 and the MIM capacitor 17-2 of the pixel 11-2 are separated by the separation structures 31-1 and 31-2 and the interlayer insulating film 32. There is.
  • a through electrode 33 is arranged between the pixels 11 so as to penetrate the interlayer insulating film 32. Further, as will be explained later with reference to FIG. 3, the pixel 11 is provided with a slit 34.
  • FIG. 3 shows a schematic cross-sectional configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2.
  • the MIM capacitor 17 is configured to have a three-dimensional shape between the lower wiring 41 and the upper wiring 42, and the MIM capacitor 17 and the upper wiring 42 are connected via an electrode 43.
  • the MIM capacitor 17 is arranged in the wiring layer of the pixel 11 (the wiring layer on either the sensor board side or the logic board side).
  • an insulating film 44 is provided at the lower end portion of the MIM capacitor 17, and an insulating film 45 is provided at the upper end portion of the MIM capacitor 17.
  • silicon nitride can be used for the insulating film 44 and the insulating film 45.
  • the insulating film 45 is formed so as to be partially opened by the slit 34.
  • the MIM capacitor 17 is configured such that upper electrodes 53a and 53b are provided to face both surfaces of the lower electrode 51, respectively.
  • the MIM capacitor 17 has a dielectric film 52a sandwiched between one surface of the lower electrode 51 and the upper electrode 53a, and a dielectric film 52b sandwiched between the other surface of the lower electrode 51 and the upper electrode 53b. It is composed of Further, the lower electrode 51 is connected to the lower wiring 41, and the upper electrodes 53a and 53b are connected to the upper wiring 42 via the electrode 43.
  • the lower electrode 51 is formed in a concave shape along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film 52a is formed inside the lower electrode 51. It is constructed by embedding an upper electrode 53a inside.
  • a dielectric film 52b is formed on the outside of each lower electrode 51 forming a cylinder shape, and an upper electrode 53b is formed outside the dielectric film 52b and between adjacent cylinder shapes. Constructed by being embedded.
  • titanium nitride can be used for the lower electrode 51 and the upper electrode 53
  • a high-k film for example, a ZrO/AlO/ZrO laminated film
  • An isolation structure 31 is provided around the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between adjacent isolation structures 31.
  • the isolation structure 31 is formed by filling a trench formed by penetrating the interlayer insulating film 32 by wet etching to surround the MIM capacitor 17 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32. Consisted of.
  • silicon nitride, silicon carbide, or the like SiN, SiC(N) film
  • metals e.g., Ti, Ta, W, Mo, Al, Cu, Co, Ni, Ru, etc.
  • compounds containing these metals e.g., TiN, TaN, WN, MoN
  • a through electrode 33 is provided between the MIM capacitors 17, and the lower wiring 41-3 and the upper wiring 42-3 are electrically connected by the through electrode 33.
  • tungsten can be used as the material for forming the through electrode 33.
  • the pixel 11 configured in this manner can electrically isolate the MIM capacitor 17 from other adjacent pixels 11. In other words, even if the MIM capacitors 17 are applied to a CMOS image sensor, conduction between the MIM capacitors 17 can be avoided. Further, by employing the MIM capacitor 17 having a three-dimensional structure using a cylinder shape, the pixel 11 can achieve higher capacitance than, for example, an MIM capacitor having a two-dimensional structure.
  • the image sensor having the pixels 11 can expand the dynamic range when capturing an HDR (High Dynamic Range) image, for example, and can capture a higher quality image.
  • HDR High Dynamic Range
  • a lower wiring 41 and an insulating film 44 are formed below the interlayer insulating film 32, and an insulating film 45 is formed above the interlayer insulating film 32.
  • the insulating film 45 is opened and the trench formed by wet etching to the insulating film 44 so as to penetrate the interlayer insulating film 32 is etched with SiO2 as described above.
  • the separation structure 31 is formed by embedding a material that provides a selectivity.
  • a plurality of recesses 61 for forming the cylinder shape of the MIM capacitor 17 are formed to penetrate the interlayer insulating film 32, the insulating film 44, and the insulating film 45. Ru. That is, the plurality of recesses 61 are formed such that the lower wiring 41 is exposed at the bottom surface of each recess.
  • a plurality of lower electrodes 51 are formed by depositing titanium nitride on the side and bottom surfaces of each of the plurality of recesses 61. That is, the lower electrode 51 is formed in a concave shape along the shape of the concave portion 61 .
  • the interlayer insulating film 32 is selectively etched back to remove the interlayer insulating film inside the isolation structure 31. Remove 32. That is, the interlayer insulating film 32 between the plurality of lower electrodes 51 is removed through the slit 34 so that only the interlayer insulating film 32 between adjacent interlayer insulating films 32 remains. At this time, the upper end of each lower electrode 51 is supported by the insulating film 45.
  • a dielectric film is formed on both sides of the lower electrode 51.
  • a dielectric film 52a is formed on the inside of the concave shape of the lower electrode 51
  • a dielectric film 52b is formed on the outside of the concave shape of the lower electrode 51.
  • a film of titanium nitride is formed on both sides of the lower electrode 51.
  • the upper electrode 53a is formed so as to sandwich the dielectric film 52a between it and the lower electrode 51
  • the upper electrode 53b is formed so that the dielectric film 52b is sandwiched between it and the lower electrode 51.
  • the interlayer insulating film 32 is stacked, the interlayer insulating film 32, the insulating film 44, and the insulating film 45 are penetrated between adjacent isolation structures 31.
  • the through electrode 33 is formed by filling tungsten into the trench formed until the lower wiring 41-3 is exposed. Further, an electrode 43 is formed so as to be connected to the upper electrode 53a.
  • the upper wiring 42 is formed so as to be connected to the electrode 43 and the through electrode 33, respectively, thereby forming the MIM capacitor 17 as shown in FIG. 3 described above.
  • the mechanical strength of the MIM capacitor 17 formed through the steps described above can be improved by, for example, supporting the individual lower electrodes 51 with the insulating film 45. Furthermore, when selectively etching back the interlayer insulating film 32, the isolation structure 31 can stop the etching.
  • FIG. 12 is a cross-sectional view showing an example of a modification of the MIM capacitor 17.
  • an isolation structure is created by filling a trench formed to penetrate the interlayer insulating film 32 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32.
  • a body 31 was constructed.
  • the isolation structure 31A is formed of the same material as the lower electrode 51, the upper electrode 53a, and the dielectric film 52a. That is, in the MIM capacitor 17A, the isolation structure 31A is configured by a laminated structure in which a metal forming the lower electrode 51, a dielectric forming the dielectric film 52a, and a metal forming the upper electrode 53a are stacked.
  • the separation structure 31A is formed by stacking metals.
  • the MIM capacitor 17A can form the isolation structure 31 by a portion of its outer periphery, and for example, costs can be reduced by reducing the manufacturing process.
  • the present technology is not limited to application to the MIM capacitor 17 used for switching the capacitance for accumulating charges transferred from the photoelectric conversion unit 12, but is applicable to Therefore, it may be applied to MIM capacitors used for other purposes.
  • the image sensor including the pixels 11 as described above can be used in various electronic devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or other equipment with an imaging function. Can be applied.
  • an imaging system such as a digital still camera or a digital video camera
  • a mobile phone with an imaging function or other equipment with an imaging function. Can be applied.
  • FIG. 13 is a block diagram showing a configuration example of an imaging device installed in an electronic device.
  • the imaging device 101 includes an optical system 102, an image sensor 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.
  • the optical system 102 is configured with one or more lenses, guides image light (incident light) from the subject to the image sensor 103, and forms an image on the light-receiving surface (sensor section) of the image sensor 103.
  • an image sensor including the pixels 11 described above is applied as the image sensor 103. Electrons are accumulated in the image sensor 103 for a certain period of time depending on the image formed on the light-receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to the signal processing circuit 104.
  • the signal processing circuit 104 performs various signal processing on the pixel signals output from the image sensor 103.
  • An image (image data) obtained by signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 for display, or supplied to a memory 106 for storage (recording).
  • the imaging device 101 configured in this way, by applying an imaging element including the above-described pixels 11, it is possible to capture, for example, a higher quality image.
  • FIG. 14 is a diagram showing an example of use of the above-described image sensor (imaging device).
  • the above-described image sensor can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.
  • ⁇ Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes Devices used for transportation, such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc.
  • Devices used for transportation such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc.
  • User gestures Devices used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate devices according to the gestures.
  • - Endoscopes devices that perform blood vessel imaging by receiving infrared light, etc.
  • Devices used for medical and healthcare purposes - Devices used for security, such as surveillance cameras for crime prevention and cameras for person authentication - Skin measurement devices that take pictures of the skin, and devices that take pictures of the scalp - Devices used for beauty purposes, such as microscopes for skin care.
  • - Devices used for sports such as action cameras and wearable cameras.
  • - Cameras, etc. used to monitor the condition of fields and crops. , equipment used for agricultural purposes
  • the present technology can also have the following configuration.
  • a solid-state imaging device comprising: an isolation section that electrically isolates the capacitors of the adjacent pixels.
  • the isolation section is provided for each pixel surrounding the capacitor,
  • the solid-state imaging device according to (1) above, wherein an interlayer insulating film is provided between the separation portions of each of the pixels.
  • the material is a metal or a compound containing the metal.
  • the capacitor is configured to have a plurality of cylindrical shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring.
  • the dielectric film is formed on both sides of the concave lower electrode formed along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film is formed on both sides of the concave lower electrode, and the dielectric film is formed on both sides of the concave lower electrode formed along each of the high aspect ratio concave portions constituting the cylinder shape.
  • the solid-state imaging device according to (7) above which is configured by providing an upper electrode.
  • the separation part is formed by a laminated structure in which the same materials as the upper electrode, the lower wiring, and the dielectric film that constitute the capacitor are laminated.
  • solid-state image sensor (11) forming a capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; A method for manufacturing a solid-state imaging device, comprising: forming an isolation portion that electrically isolates the capacitors of the adjacent pixels.
  • An electronic device comprising: a solid-state imaging device; and a separation section that electrically isolates the capacitors of the adjacent pixels.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un élément d'imagerie à semi-conducteurs et un procédé de fabrication, et un dispositif électronique qui permettent d'obtenir une qualité d'image supérieure. L'élément d'imagerie à semi-conducteurs comprend : une pluralité de pixels ; un condensateur qui est disposé sur chaque pixel et qui est conçu pour avoir une forme tridimensionnelle entre un câblage supérieur et un câblage inférieur d'une couche de câblage du pixel ; et une partie de séparation qui sépare électriquement les condensateurs de pixels adjacents. En outre, la partie de séparation est disposée sur chaque pixel de façon à entourer le condensateur. Un film isolant intercouche est disposé entre les parties de séparation des pixels respectifs. La présente technique peut s'appliquer à des capteurs d'image CMOS, par exemple.
PCT/JP2023/029937 2022-09-08 2023-08-21 Élément d'imagerie à semi-conducteurs et procédé de fabrication ainsi que dispositif électronique WO2024053372A1 (fr)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554788B2 (en) * 2002-06-12 2009-06-30 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device
US20120306057A1 (en) * 2011-05-30 2012-12-06 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
JP2013153103A (ja) * 2012-01-26 2013-08-08 Elpida Memory Inc 半導体装置及びその製造方法
JP2020129795A (ja) * 2019-02-11 2020-08-27 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． イメージセンサ及びその駆動方法
WO2020261817A1 (fr) * 2019-06-25 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs
US20220052086A1 (en) * 2020-08-13 2022-02-17 Samsung Electronics Co., Ltd. Image sensor
JP2022045912A (ja) * 2020-09-09 2022-03-22 三星電子株式会社 イメージセンサ

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7554788B2 (en) * 2002-06-12 2009-06-30 Samsung Electronics Co., Ltd. Capacitor for a semiconductor device
US20120306057A1 (en) * 2011-05-30 2012-12-06 Hynix Semiconductor Inc. Method for manufacturing semiconductor device
JP2013153103A (ja) * 2012-01-26 2013-08-08 Elpida Memory Inc 半導体装置及びその製造方法
JP2020129795A (ja) * 2019-02-11 2020-08-27 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． イメージセンサ及びその駆動方法
WO2020261817A1 (fr) * 2019-06-25 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et procédé de fabrication d'élément d'imagerie à semi-conducteurs
US20220052086A1 (en) * 2020-08-13 2022-02-17 Samsung Electronics Co., Ltd. Image sensor
JP2022045912A (ja) * 2020-09-09 2022-03-22 三星電子株式会社 イメージセンサ

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