WO2024053372A1 - Solid-state imaging element and manufacturing method, and electronic device - Google Patents
Solid-state imaging element and manufacturing method, and electronic device Download PDFInfo
- Publication number
- WO2024053372A1 WO2024053372A1 PCT/JP2023/029937 JP2023029937W WO2024053372A1 WO 2024053372 A1 WO2024053372 A1 WO 2024053372A1 JP 2023029937 W JP2023029937 W JP 2023029937W WO 2024053372 A1 WO2024053372 A1 WO 2024053372A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- solid
- state imaging
- imaging device
- wiring
- pixel
- Prior art date
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 91
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims description 27
- 238000000926 separation method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 description 13
- 238000012546 transfer Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 210000004204 blood vessel Anatomy 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 210000004761 scalp Anatomy 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
Definitions
- the present disclosure relates to a solid-state image sensor, a manufacturing method, and an electronic device, and particularly relates to a solid-state image sensor, a manufacturing method, and an electronic device that can achieve higher image quality.
- DRAM Dynamic Random Access Memory
- Patent Document 1 discloses a DRAM element having a configuration in which one memory cell region having a plurality of capacitor elements is separated from a peripheral circuit region by a groove formed at the periphery of the memory cell region.
- the present disclosure has been made in view of this situation, and is intended to make it possible to achieve higher image quality.
- a solid-state imaging device includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel, and and an isolation section that electrically isolates the capacitors from each other.
- a manufacturing method includes forming a three-dimensional capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; The method further includes forming an isolation portion that electrically isolates the capacitors from each other.
- An electronic device includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
- the solid-state imaging device includes a separation portion that electrically isolates the capacitors from each other.
- a three-dimensional capacitor is provided between the upper wiring and the lower wiring of the wiring layer of the pixel for each of the plurality of pixels, and the capacitors of adjacent pixels are separated by the separation part. electrically isolated.
- FIG. 2 is a circuit diagram illustrating an embodiment of a pixel included in an image sensor to which the present technology is applied.
- FIG. 3 is a diagram illustrating a configuration example of a MIM capacitor when viewed from above.
- FIG. 3 is a diagram illustrating a cross-sectional configuration example of a MIM capacitor. It is a figure explaining a 1st process. It is a figure explaining a 2nd process. It is a figure explaining a 3rd process. It is a figure explaining the 4th process. It is a figure explaining the 5th process. It is a figure explaining a 6th process. It is a figure explaining a 7th process. It is a figure explaining the 8th process.
- FIG. 7 is a cross-sectional view showing a modified example of the MIM capacitor.
- 1 is a block diagram showing a configuration example of an imaging device.
- FIG. It is a figure which shows the example of use which uses an image sensor.
- FIG. 1 shows a circuit diagram of the pixel 11.
- the pixel 11 includes a photoelectric conversion section 12, a transfer transistor 13, a first FD (Floating Diffusion) section 14, a connection transistor 15, a second FD section 16, an MIM capacitor 17, a reset transistor 18, It is configured to include an amplification transistor 19 and a selection transistor 20, and outputs a pixel signal via a vertical signal line 21.
- the pixel 11 is a LOFIC (Lateral Over Flow Integration Capacitor) pixel, which guides charges overflowing from the photoelectric conversion unit 12 in the lateral direction when it is irradiated with light strong enough to exceed the saturation capacity of the photoelectric conversion unit 12. It has a structure in which the energy is accumulated in the MIM capacitor 17.
- the photoelectric conversion section 12 has an anode terminal grounded and a cathode terminal connected to the first FD section 14 via the transfer transistor 13.
- the photoelectric conversion unit 12 receives light irradiated onto the light-receiving surface of the image sensor, and photoelectrically converts the light into an electric charge corresponding to the amount of light.
- the transfer transistor 13 is arranged to connect the photoelectric conversion section 12 and the first FD section 14.
- the transfer transistor 13 is driven according to the transfer signal TG, and transfers the charge photoelectrically converted by the photoelectric conversion section 12 to the first FD section 14.
- the first FD section 14 accumulates charges transferred from the photoelectric conversion section 12 via the transfer transistor 13 in order to convert them into pixel signals.
- connection transistor 15 is arranged to connect the first FD section 14 and the second FD section 16.
- the connection transistor 15 is driven according to the connection signal FDG to turn on/off the connection between the first FD section 14 and the second FD section 16.
- the second FD section 16 is connected to the first FD section 14 with the connection transistor 15 turned on, and accumulates charges together with the first FD section 14.
- the MIM capacitor 17 is a capacitor with an MIM (Metal-Insulator-Metal) structure provided in the wiring layer of the image sensor, and is arranged to connect the second FD section 16 and the signal wiring MIMVDD. Then, the MIM capacitor 17 accumulates charge similarly to the second FD section 16. Furthermore, the MIM capacitor 17 has a plurality of cylindrical shapes (a shape in which a dielectric film is sandwiched between a cylindrical upper electrode and a cylindrical lower electrode, as will be explained with reference to FIGS. 2 and 3 later). It has a structure.
- MIM Metal-Insulator-Metal
- the reset transistor 18 is arranged to connect the second FD section 16 and the power supply wiring VDD. Then, the reset transistor 18 is driven according to the reset signal RST, and the connection transistor 15 and the reset transistor 18 are turned on, so that the data stored in the first FD section 14, the second FD section 16, and the MIM capacitor 17 is removed. The accumulated charge is discharged to the power supply wiring VDD to reset the charge.
- the amplification transistor 19 is arranged so that the first FD section 14 is connected to the gate electrode, and the power supply wiring VDD and the selection transistor 20 are connected. Then, the amplification transistor 19 transfers the charges accumulated by the first FD section 14 or the charges accumulated by the first FD section 14, the second FD section 16, and the MIM capacitor 17 to each It is converted into a pixel signal with a level corresponding to the charge on the capacitor.
- the selection transistor 20 is arranged to connect the amplification transistor 19 and the vertical signal line 21.
- the selection transistor 20 is driven according to the selection signal SEL, and the pixel signal converted by the amplification transistor 19 is output to the vertical signal line 21 while the selection transistor 20 is on.
- the connection transistor 15 when the connection transistor 15 is turned off according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is accumulated in the capacitance of only the first FD section 14. Ru. Further, when the connection transistor 15 is turned on according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is transferred to the first FD section 14, the second FD section 16, and the MIM. It is accumulated in the combined capacity of the capacitor 17. In this way, the pixel 11 having the structure in which the MIM capacitor 17 is provided can switch the capacitance for accumulating the charge transferred from the photoelectric conversion unit 12.
- FIG. 2 shows a schematic configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2 when viewed from above. Note that the pixels 11-1 and 11-2 have the same configuration, and if there is no need to distinguish between them, they will be simply referred to as the pixel 11, and each part constituting the pixel 11 will also be referred to in the same manner.
- the MIM capacitor 17 has a structure having a plurality of cylinder shapes, and in FIG. It represents the cylinder shape. Note that the cylinder shape of the MIM capacitor 17 is not limited to a circular shape, and may be, for example, a rectangular shape.
- the pixel 11 is configured such that an isolation structure 31 is provided to surround the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between the isolation structures 31.
- the MIM capacitors 17 of adjacent pixels 11 are configured to be electrically and physically isolated from each other by the isolation structure 31 and the interlayer insulating film 32. That is, as shown in the figure, the MIM capacitor 17-1 of the pixel 11-1 and the MIM capacitor 17-2 of the pixel 11-2 are separated by the separation structures 31-1 and 31-2 and the interlayer insulating film 32. There is.
- a through electrode 33 is arranged between the pixels 11 so as to penetrate the interlayer insulating film 32. Further, as will be explained later with reference to FIG. 3, the pixel 11 is provided with a slit 34.
- FIG. 3 shows a schematic cross-sectional configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2.
- the MIM capacitor 17 is configured to have a three-dimensional shape between the lower wiring 41 and the upper wiring 42, and the MIM capacitor 17 and the upper wiring 42 are connected via an electrode 43.
- the MIM capacitor 17 is arranged in the wiring layer of the pixel 11 (the wiring layer on either the sensor board side or the logic board side).
- an insulating film 44 is provided at the lower end portion of the MIM capacitor 17, and an insulating film 45 is provided at the upper end portion of the MIM capacitor 17.
- silicon nitride can be used for the insulating film 44 and the insulating film 45.
- the insulating film 45 is formed so as to be partially opened by the slit 34.
- the MIM capacitor 17 is configured such that upper electrodes 53a and 53b are provided to face both surfaces of the lower electrode 51, respectively.
- the MIM capacitor 17 has a dielectric film 52a sandwiched between one surface of the lower electrode 51 and the upper electrode 53a, and a dielectric film 52b sandwiched between the other surface of the lower electrode 51 and the upper electrode 53b. It is composed of Further, the lower electrode 51 is connected to the lower wiring 41, and the upper electrodes 53a and 53b are connected to the upper wiring 42 via the electrode 43.
- the lower electrode 51 is formed in a concave shape along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film 52a is formed inside the lower electrode 51. It is constructed by embedding an upper electrode 53a inside.
- a dielectric film 52b is formed on the outside of each lower electrode 51 forming a cylinder shape, and an upper electrode 53b is formed outside the dielectric film 52b and between adjacent cylinder shapes. Constructed by being embedded.
- titanium nitride can be used for the lower electrode 51 and the upper electrode 53
- a high-k film for example, a ZrO/AlO/ZrO laminated film
- An isolation structure 31 is provided around the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between adjacent isolation structures 31.
- the isolation structure 31 is formed by filling a trench formed by penetrating the interlayer insulating film 32 by wet etching to surround the MIM capacitor 17 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32. Consisted of.
- silicon nitride, silicon carbide, or the like SiN, SiC(N) film
- metals e.g., Ti, Ta, W, Mo, Al, Cu, Co, Ni, Ru, etc.
- compounds containing these metals e.g., TiN, TaN, WN, MoN
- a through electrode 33 is provided between the MIM capacitors 17, and the lower wiring 41-3 and the upper wiring 42-3 are electrically connected by the through electrode 33.
- tungsten can be used as the material for forming the through electrode 33.
- the pixel 11 configured in this manner can electrically isolate the MIM capacitor 17 from other adjacent pixels 11. In other words, even if the MIM capacitors 17 are applied to a CMOS image sensor, conduction between the MIM capacitors 17 can be avoided. Further, by employing the MIM capacitor 17 having a three-dimensional structure using a cylinder shape, the pixel 11 can achieve higher capacitance than, for example, an MIM capacitor having a two-dimensional structure.
- the image sensor having the pixels 11 can expand the dynamic range when capturing an HDR (High Dynamic Range) image, for example, and can capture a higher quality image.
- HDR High Dynamic Range
- a lower wiring 41 and an insulating film 44 are formed below the interlayer insulating film 32, and an insulating film 45 is formed above the interlayer insulating film 32.
- the insulating film 45 is opened and the trench formed by wet etching to the insulating film 44 so as to penetrate the interlayer insulating film 32 is etched with SiO2 as described above.
- the separation structure 31 is formed by embedding a material that provides a selectivity.
- a plurality of recesses 61 for forming the cylinder shape of the MIM capacitor 17 are formed to penetrate the interlayer insulating film 32, the insulating film 44, and the insulating film 45. Ru. That is, the plurality of recesses 61 are formed such that the lower wiring 41 is exposed at the bottom surface of each recess.
- a plurality of lower electrodes 51 are formed by depositing titanium nitride on the side and bottom surfaces of each of the plurality of recesses 61. That is, the lower electrode 51 is formed in a concave shape along the shape of the concave portion 61 .
- the interlayer insulating film 32 is selectively etched back to remove the interlayer insulating film inside the isolation structure 31. Remove 32. That is, the interlayer insulating film 32 between the plurality of lower electrodes 51 is removed through the slit 34 so that only the interlayer insulating film 32 between adjacent interlayer insulating films 32 remains. At this time, the upper end of each lower electrode 51 is supported by the insulating film 45.
- a dielectric film is formed on both sides of the lower electrode 51.
- a dielectric film 52a is formed on the inside of the concave shape of the lower electrode 51
- a dielectric film 52b is formed on the outside of the concave shape of the lower electrode 51.
- a film of titanium nitride is formed on both sides of the lower electrode 51.
- the upper electrode 53a is formed so as to sandwich the dielectric film 52a between it and the lower electrode 51
- the upper electrode 53b is formed so that the dielectric film 52b is sandwiched between it and the lower electrode 51.
- the interlayer insulating film 32 is stacked, the interlayer insulating film 32, the insulating film 44, and the insulating film 45 are penetrated between adjacent isolation structures 31.
- the through electrode 33 is formed by filling tungsten into the trench formed until the lower wiring 41-3 is exposed. Further, an electrode 43 is formed so as to be connected to the upper electrode 53a.
- the upper wiring 42 is formed so as to be connected to the electrode 43 and the through electrode 33, respectively, thereby forming the MIM capacitor 17 as shown in FIG. 3 described above.
- the mechanical strength of the MIM capacitor 17 formed through the steps described above can be improved by, for example, supporting the individual lower electrodes 51 with the insulating film 45. Furthermore, when selectively etching back the interlayer insulating film 32, the isolation structure 31 can stop the etching.
- FIG. 12 is a cross-sectional view showing an example of a modification of the MIM capacitor 17.
- an isolation structure is created by filling a trench formed to penetrate the interlayer insulating film 32 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32.
- a body 31 was constructed.
- the isolation structure 31A is formed of the same material as the lower electrode 51, the upper electrode 53a, and the dielectric film 52a. That is, in the MIM capacitor 17A, the isolation structure 31A is configured by a laminated structure in which a metal forming the lower electrode 51, a dielectric forming the dielectric film 52a, and a metal forming the upper electrode 53a are stacked.
- the separation structure 31A is formed by stacking metals.
- the MIM capacitor 17A can form the isolation structure 31 by a portion of its outer periphery, and for example, costs can be reduced by reducing the manufacturing process.
- the present technology is not limited to application to the MIM capacitor 17 used for switching the capacitance for accumulating charges transferred from the photoelectric conversion unit 12, but is applicable to Therefore, it may be applied to MIM capacitors used for other purposes.
- the image sensor including the pixels 11 as described above can be used in various electronic devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or other equipment with an imaging function. Can be applied.
- an imaging system such as a digital still camera or a digital video camera
- a mobile phone with an imaging function or other equipment with an imaging function. Can be applied.
- FIG. 13 is a block diagram showing a configuration example of an imaging device installed in an electronic device.
- the imaging device 101 includes an optical system 102, an image sensor 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.
- the optical system 102 is configured with one or more lenses, guides image light (incident light) from the subject to the image sensor 103, and forms an image on the light-receiving surface (sensor section) of the image sensor 103.
- an image sensor including the pixels 11 described above is applied as the image sensor 103. Electrons are accumulated in the image sensor 103 for a certain period of time depending on the image formed on the light-receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to the signal processing circuit 104.
- the signal processing circuit 104 performs various signal processing on the pixel signals output from the image sensor 103.
- An image (image data) obtained by signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 for display, or supplied to a memory 106 for storage (recording).
- the imaging device 101 configured in this way, by applying an imaging element including the above-described pixels 11, it is possible to capture, for example, a higher quality image.
- FIG. 14 is a diagram showing an example of use of the above-described image sensor (imaging device).
- the above-described image sensor can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.
- ⁇ Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes Devices used for transportation, such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc.
- Devices used for transportation such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc.
- User gestures Devices used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate devices according to the gestures.
- - Endoscopes devices that perform blood vessel imaging by receiving infrared light, etc.
- Devices used for medical and healthcare purposes - Devices used for security, such as surveillance cameras for crime prevention and cameras for person authentication - Skin measurement devices that take pictures of the skin, and devices that take pictures of the scalp - Devices used for beauty purposes, such as microscopes for skin care.
- - Devices used for sports such as action cameras and wearable cameras.
- - Cameras, etc. used to monitor the condition of fields and crops. , equipment used for agricultural purposes
- the present technology can also have the following configuration.
- a solid-state imaging device comprising: an isolation section that electrically isolates the capacitors of the adjacent pixels.
- the isolation section is provided for each pixel surrounding the capacitor,
- the solid-state imaging device according to (1) above, wherein an interlayer insulating film is provided between the separation portions of each of the pixels.
- the material is a metal or a compound containing the metal.
- the capacitor is configured to have a plurality of cylindrical shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring.
- the dielectric film is formed on both sides of the concave lower electrode formed along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film is formed on both sides of the concave lower electrode, and the dielectric film is formed on both sides of the concave lower electrode formed along each of the high aspect ratio concave portions constituting the cylinder shape.
- the solid-state imaging device according to (7) above which is configured by providing an upper electrode.
- the separation part is formed by a laminated structure in which the same materials as the upper electrode, the lower wiring, and the dielectric film that constitute the capacitor are laminated.
- solid-state image sensor (11) forming a capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; A method for manufacturing a solid-state imaging device, comprising: forming an isolation portion that electrically isolates the capacitors of the adjacent pixels.
- An electronic device comprising: a solid-state imaging device; and a separation section that electrically isolates the capacitors of the adjacent pixels.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present disclosure relates to a solid-state imaging element and a manufacturing method, and an electronic device that enable a higher image quality to be achieved. The solid-state imaging element comprises: a plurality of pixels; a capacitor that is provided to each pixel and that is configured to have a three-dimensional shape between upper wiring and lower wiring of a wiring layer of the pixel; and a separating part that electrically separates the capacitors of adjacent pixels. Further, the separating part is provided to each pixel so as to surround the capacitor. An interlayer insulating film is provided between the separating parts of the respective pixels. The present technology can be applied to CMOS image sensors, for example.
Description
本開示は、固体撮像素子および製造方法、並びに、電子機器に関し、特に、より高画質化を図ることができるようにした固体撮像素子および製造方法、並びに、電子機器に関する。
The present disclosure relates to a solid-state image sensor, a manufacturing method, and an electronic device, and particularly relates to a solid-state image sensor, a manufacturing method, and an electronic device that can achieve higher image quality.
従来、DRAM(Dynamic Random Access Memory)素子の微細化に伴ってメモリセルの面積が縮小することになるため、キャパシタを立体形状に形成することによって高容量化を図る技術の開発が進められている。
Conventionally, as the size of DRAM (Dynamic Random Access Memory) elements becomes smaller, the area of memory cells shrinks, so the development of technology to increase capacitance by forming capacitors into three-dimensional shapes has been progressing. .
例えば、特許文献1には、複数のキャパシタ素子を有する1つのメモリセル領域を、そのメモリセル領域の周縁部に形成された溝部によって周辺回路領域から分離した構成のDRAM素子が開示されている。
For example, Patent Document 1 discloses a DRAM element having a configuration in which one memory cell region having a plurality of capacitor elements is separated from a peripheral circuit region by a groove formed at the periphery of the memory cell region.
ところで、上述の特許文献1に開示されているメモリセルで用いられている立体形状のキャパシタを、CMOS(Complementary Metal Oxide Semiconductor)イメージセンサに適用することによって、例えば、高画質化を図ることが検討されている。しかしながら、立体形状のキャパシタ間で電気的な分離が行われていないため、隣接する画素の立体形状のキャパシタどうしが導通してしまうことが想定され、CMOSイメージセンサに適用することは困難であった。
By the way, it is being considered, for example, to improve image quality by applying the three-dimensional capacitor used in the memory cell disclosed in Patent Document 1 mentioned above to a CMOS (Complementary Metal Oxide Semiconductor) image sensor. has been done. However, since there is no electrical isolation between the three-dimensional capacitors, it is assumed that the three-dimensional capacitors of adjacent pixels will conduct with each other, making it difficult to apply to CMOS image sensors. .
本開示は、このような状況に鑑みてなされたものであり、より高画質化を図ることができるようにするものである。
The present disclosure has been made in view of this situation, and is intended to make it possible to achieve higher image quality.
本開示の一側面の固体撮像素子は、複数の画素と、前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部とを備える。
A solid-state imaging device according to an aspect of the present disclosure includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel, and and an isolation section that electrically isolates the capacitors from each other.
本開示の一側面の製造方法は、複数の画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタを形成することと、隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部を形成することとを含む。
A manufacturing method according to one aspect of the present disclosure includes forming a three-dimensional capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; The method further includes forming an isolation portion that electrically isolates the capacitors from each other.
本開示の一側面の電子機器は、複数の画素と、前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部とを有する固体撮像素子を備える。
An electronic device according to one aspect of the present disclosure includes a plurality of pixels, a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel; The solid-state imaging device includes a separation portion that electrically isolates the capacitors from each other.
本開示の一側面においては、複数の画素ごとに、画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタが設けられ、隣接する画素のキャパシタどうしの間が分離部によって電気的に分離される。
In one aspect of the present disclosure, a three-dimensional capacitor is provided between the upper wiring and the lower wiring of the wiring layer of the pixel for each of the plurality of pixels, and the capacitors of adjacent pixels are separated by the separation part. electrically isolated.
以下、本技術を適用した具体的な実施の形態について、図面を参照しながら詳細に説明する。
Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.
<画素の構成例>
図1乃至図3を参照して、本技術を適用した撮像素子が有する画素の一実施の形態について説明する。 <Example of pixel configuration>
An embodiment of a pixel included in an image sensor to which the present technology is applied will be described with reference to FIGS. 1 to 3.
図1乃至図3を参照して、本技術を適用した撮像素子が有する画素の一実施の形態について説明する。 <Example of pixel configuration>
An embodiment of a pixel included in an image sensor to which the present technology is applied will be described with reference to FIGS. 1 to 3.
図1には、画素11の回路図が示されている。
FIG. 1 shows a circuit diagram of the pixel 11.
図1に示すように、画素11は、光電変換部12、転送トランジスタ13、第1のFD(Floating Diffusion)部14、接続トランジスタ15、第2のFD部16、MIMキャパシタ17、リセットトランジスタ18、増幅トランジスタ19、および選択トランジスタ20を備えて構成され、垂直信号線21を介して画素信号を出力する。例えば、画素11は、LOFIC(Lateral Over Flow Integration Capacitor)画素であり、光電変換部12の飽和容量を超えるほど強い光が照射された場合に、光電変換部12から溢れる電荷を横方向に導いてMIMキャパシタ17に蓄積する構造である。
As shown in FIG. 1, the pixel 11 includes a photoelectric conversion section 12, a transfer transistor 13, a first FD (Floating Diffusion) section 14, a connection transistor 15, a second FD section 16, an MIM capacitor 17, a reset transistor 18, It is configured to include an amplification transistor 19 and a selection transistor 20, and outputs a pixel signal via a vertical signal line 21. For example, the pixel 11 is a LOFIC (Lateral Over Flow Integration Capacitor) pixel, which guides charges overflowing from the photoelectric conversion unit 12 in the lateral direction when it is irradiated with light strong enough to exceed the saturation capacity of the photoelectric conversion unit 12. It has a structure in which the energy is accumulated in the MIM capacitor 17.
光電変換部12は、アノード端子が接地され、カソード端子が転送トランジスタ13を介して第1のFD部14に接続される。そして、光電変換部12は、撮像素子の受光面に照射される光を受光し、その光の光量に応じた電荷に光電変換する。
The photoelectric conversion section 12 has an anode terminal grounded and a cathode terminal connected to the first FD section 14 via the transfer transistor 13. The photoelectric conversion unit 12 receives light irradiated onto the light-receiving surface of the image sensor, and photoelectrically converts the light into an electric charge corresponding to the amount of light.
転送トランジスタ13は、光電変換部12と第1のFD部14とを接続するように配置される。そして、転送トランジスタ13は、転送信号TGに従って駆動し、光電変換部12で光電変換された電荷を第1のFD部14へ転送する。
The transfer transistor 13 is arranged to connect the photoelectric conversion section 12 and the first FD section 14. The transfer transistor 13 is driven according to the transfer signal TG, and transfers the charge photoelectrically converted by the photoelectric conversion section 12 to the first FD section 14.
第1のFD部14は、転送トランジスタ13を介して光電変換部12から転送されてくる電荷を、画素信号に変換するために蓄積する。
The first FD section 14 accumulates charges transferred from the photoelectric conversion section 12 via the transfer transistor 13 in order to convert them into pixel signals.
接続トランジスタ15は、第1のFD部14と第2のFD部16とを接続するように配置される。そして、接続トランジスタ15は、接続信号FDGに従って駆動し、第1のFD部14と第2のFD部16との接続をオン/オフする。
The connection transistor 15 is arranged to connect the first FD section 14 and the second FD section 16. The connection transistor 15 is driven according to the connection signal FDG to turn on/off the connection between the first FD section 14 and the second FD section 16.
第2のFD部16は、接続トランジスタ15がオンとなった状態で第1のFD部14に接続され、第1のFD部14とともに電荷を蓄積する。
The second FD section 16 is connected to the first FD section 14 with the connection transistor 15 turned on, and accumulates charges together with the first FD section 14.
MIMキャパシタ17は、撮像素子の配線層に設けられたMIM(Metal-Insulator-Metal)構造のキャパシタであって、第2のFD部16と信号配線MIMVDDとを接続するように配置される。そして、MIMキャパシタ17は、第2のFD部16と同様に電荷を蓄積する。また、MIMキャパシタ17は、複数のシリンダ形状(後述の図2および図3を参照して説明するように、筒形の上部電極と筒形の下部電極とで誘電膜を挟み込んだ形状)を有する構造となっている。
The MIM capacitor 17 is a capacitor with an MIM (Metal-Insulator-Metal) structure provided in the wiring layer of the image sensor, and is arranged to connect the second FD section 16 and the signal wiring MIMVDD. Then, the MIM capacitor 17 accumulates charge similarly to the second FD section 16. Furthermore, the MIM capacitor 17 has a plurality of cylindrical shapes (a shape in which a dielectric film is sandwiched between a cylindrical upper electrode and a cylindrical lower electrode, as will be explained with reference to FIGS. 2 and 3 later). It has a structure.
リセットトランジスタ18は、第2のFD部16と電源配線VDDとを接続するように配置される。そして、リセットトランジスタ18は、リセット信号RSTに従って駆動し、接続トランジスタ15およびリセットトランジスタ18がオンとなることで、第1のFD部14、第2のFD部16、およびMIMキャパシタ17に蓄積されていた電荷を電源配線VDDに排出して、電荷をリセットする。
The reset transistor 18 is arranged to connect the second FD section 16 and the power supply wiring VDD. Then, the reset transistor 18 is driven according to the reset signal RST, and the connection transistor 15 and the reset transistor 18 are turned on, so that the data stored in the first FD section 14, the second FD section 16, and the MIM capacitor 17 is removed. The accumulated charge is discharged to the power supply wiring VDD to reset the charge.
増幅トランジスタ19は、第1のFD部14がゲート電極に接続されるとともに、電源配線VDDと選択トランジスタ20とを接続するように配置される。そして、増幅トランジスタ19は、第1のFD部14によって蓄積されている電荷、または、第1のFD部14、第2のFD部16、およびMIMキャパシタ17によって蓄積されている電荷を、それぞれの容量に対する電荷に応じたレベルの画素信号に変換する。
The amplification transistor 19 is arranged so that the first FD section 14 is connected to the gate electrode, and the power supply wiring VDD and the selection transistor 20 are connected. Then, the amplification transistor 19 transfers the charges accumulated by the first FD section 14 or the charges accumulated by the first FD section 14, the second FD section 16, and the MIM capacitor 17 to each It is converted into a pixel signal with a level corresponding to the charge on the capacitor.
選択トランジスタ20は、増幅トランジスタ19と垂直信号線21とを接続するように配置される。そして、選択トランジスタ20は、選択信号SELに従って駆動し、選択トランジスタ20がオンとなっている間に、増幅トランジスタ19によって変換された画素信号が垂直信号線21に出力される。
The selection transistor 20 is arranged to connect the amplification transistor 19 and the vertical signal line 21. The selection transistor 20 is driven according to the selection signal SEL, and the pixel signal converted by the amplification transistor 19 is output to the vertical signal line 21 while the selection transistor 20 is on.
例えば、画素11では、接続信号FDGに従って接続トランジスタ15がオフとなっている場合、光電変換部12から転送トランジスタ13を介して転送される電荷は、第1のFD部14のみの容量に蓄積される。また、接続信号FDGに従って接続トランジスタ15がオンとなっている場合、光電変換部12から転送トランジスタ13を介して転送される電荷は、第1のFD部14、第2のFD部16、およびMIMキャパシタ17を合わせた容量に蓄積される。このように、MIMキャパシタ17を設けた構造の画素11は、光電変換部12から転送される電荷を蓄積するための容量を切り替えることができる。
For example, in the pixel 11, when the connection transistor 15 is turned off according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is accumulated in the capacitance of only the first FD section 14. Ru. Further, when the connection transistor 15 is turned on according to the connection signal FDG, the charge transferred from the photoelectric conversion section 12 via the transfer transistor 13 is transferred to the first FD section 14, the second FD section 16, and the MIM. It is accumulated in the combined capacity of the capacitor 17. In this way, the pixel 11 having the structure in which the MIM capacitor 17 is provided can switch the capacitance for accumulating the charge transferred from the photoelectric conversion unit 12.
図2および図3を参照して、MIMキャパシタ17の構成例について説明する。
A configuration example of the MIM capacitor 17 will be described with reference to FIGS. 2 and 3.
図2には、隣接する2つの画素11-1および11-2が有するMIMキャパシタ17-1および17-2を平面視した概略的な構成例が示されている。なお、画素11-1および11-2は、同様に構成されており、それらを区別する必要がない場合には、単に画素11と称し、画素11を構成する各部についても同様に称する。
FIG. 2 shows a schematic configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2 when viewed from above. Note that the pixels 11-1 and 11-2 have the same configuration, and if there is no need to distinguish between them, they will be simply referred to as the pixel 11, and each part constituting the pixel 11 will also be referred to in the same manner.
上述したように、MIMキャパシタ17は、複数のシリンダ形状を有する構造となっており、図2では、MIMキャパシタ17を表す破線で囲われている領域に図示されている複数の円形が、複数のシリンダ形状を表している。なお、MIMキャパシタ17のシリンダ形状は、円形の形状に限定されることなく、例えば、矩形の形状であってもよい。
As described above, the MIM capacitor 17 has a structure having a plurality of cylinder shapes, and in FIG. It represents the cylinder shape. Note that the cylinder shape of the MIM capacitor 17 is not limited to a circular shape, and may be, for example, a rectangular shape.
そして、画素11は、MIMキャパシタ17の外周を囲うように分離構造体31が設けられて構成されており、分離構造体31どうしの間には層間絶縁膜32が設けられている。これにより、隣接する画素11のMIMキャパシタ17どうしの間が、分離構造体31および層間絶縁膜32によって電気的および物理的に分離されるように構成されている。つまり、図示するように、画素11-1のMIMキャパシタ17-1と画素11-2のMIMキャパシタ17-2とは、分離構造体31-1および31-2並びに層間絶縁膜32によって分離されている。
The pixel 11 is configured such that an isolation structure 31 is provided to surround the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between the isolation structures 31. Thereby, the MIM capacitors 17 of adjacent pixels 11 are configured to be electrically and physically isolated from each other by the isolation structure 31 and the interlayer insulating film 32. That is, as shown in the figure, the MIM capacitor 17-1 of the pixel 11-1 and the MIM capacitor 17-2 of the pixel 11-2 are separated by the separation structures 31-1 and 31-2 and the interlayer insulating film 32. There is.
また、画素11どうしの間には、層間絶縁膜32を貫通するように貫通電極33が配置されている。また、後述する図3を参照して説明するように、画素11にはスリット34が設けられている。
Further, a through electrode 33 is arranged between the pixels 11 so as to penetrate the interlayer insulating film 32. Further, as will be explained later with reference to FIG. 3, the pixel 11 is provided with a slit 34.
図3には、隣接する2つの画素11-1および11-2が有するMIMキャパシタ17-1および17-2を断面視した概略的な構成例が示されている。
FIG. 3 shows a schematic cross-sectional configuration example of MIM capacitors 17-1 and 17-2 included in two adjacent pixels 11-1 and 11-2.
図3に示すように、MIMキャパシタ17は、下部配線41および上部配線42の間に立体形状となるように構成され、MIMキャパシタ17と上部配線42とが電極43を介して接続される。例えば、MIMキャパシタ17は、画素11の配線層(センサ基板側およびロジック基板側いずれかの配線層)に配置される。また、MIMキャパシタ17の下端部分には絶縁膜44が設けられており、MIMキャパシタ17の上端部分には絶縁膜45が設けられている。例えば、絶縁膜44および絶縁膜45には、窒化ケイ素を用いることができる。また、絶縁膜45は、スリット34によって部分的に開口するように形成される。
As shown in FIG. 3, the MIM capacitor 17 is configured to have a three-dimensional shape between the lower wiring 41 and the upper wiring 42, and the MIM capacitor 17 and the upper wiring 42 are connected via an electrode 43. For example, the MIM capacitor 17 is arranged in the wiring layer of the pixel 11 (the wiring layer on either the sensor board side or the logic board side). Further, an insulating film 44 is provided at the lower end portion of the MIM capacitor 17, and an insulating film 45 is provided at the upper end portion of the MIM capacitor 17. For example, silicon nitride can be used for the insulating film 44 and the insulating film 45. Further, the insulating film 45 is formed so as to be partially opened by the slit 34.
MIMキャパシタ17は、下部電極51の両面それぞれに対向するように上部電極53aおよび53bが設けられて構成される。そして、MIMキャパシタ17は、下部電極51の一方の面と上部電極53aとの間に誘電膜52aを挟み込むとともに、下部電極51の他方の面と上部電極53bとの間に誘電膜52bを挟み込むように構成される。また、下部電極51は下部配線41に接続され、上部電極53aおよび53bは電極43を介して上部配線42に接続される。
The MIM capacitor 17 is configured such that upper electrodes 53a and 53b are provided to face both surfaces of the lower electrode 51, respectively. The MIM capacitor 17 has a dielectric film 52a sandwiched between one surface of the lower electrode 51 and the upper electrode 53a, and a dielectric film 52b sandwiched between the other surface of the lower electrode 51 and the upper electrode 53b. It is composed of Further, the lower electrode 51 is connected to the lower wiring 41, and the upper electrodes 53a and 53b are connected to the upper wiring 42 via the electrode 43.
例えば、MIMキャパシタ17は、シリンダ形状を構成する個々の高アスペクト比の凹部に沿って下部電極51が凹形状に形成され、下部電極51の内側に誘電膜52aが成膜され、誘電膜52aの内側に上部電極53aが埋め込まれることによって構成される。さらに、MIMキャパシタ17は、シリンダ形状を構成する個々の下部電極51の外側に誘電膜52bが成膜され、誘電膜52bの外側であって、隣接するシリンダ形状どうしの間に、上部電極53bが埋め込まれることによって構成される。例えば、下部電極51および上部電極53には、窒化チタンを用いることができ、誘電膜52には、High-k膜(例えば、ZrO/AlO/ZrO積層膜)を用いることができる。
For example, in the MIM capacitor 17, the lower electrode 51 is formed in a concave shape along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film 52a is formed inside the lower electrode 51. It is constructed by embedding an upper electrode 53a inside. Further, in the MIM capacitor 17, a dielectric film 52b is formed on the outside of each lower electrode 51 forming a cylinder shape, and an upper electrode 53b is formed outside the dielectric film 52b and between adjacent cylinder shapes. Constructed by being embedded. For example, titanium nitride can be used for the lower electrode 51 and the upper electrode 53, and a high-k film (for example, a ZrO/AlO/ZrO laminated film) can be used for the dielectric film 52.
MIMキャパシタ17の外周には分離構造体31が設けられ、隣接する分離構造体31どうしの間に層間絶縁膜32が設けられている。
An isolation structure 31 is provided around the outer periphery of the MIM capacitor 17, and an interlayer insulating film 32 is provided between adjacent isolation structures 31.
分離構造体31は、MIMキャパシタ17を囲うように、ウェットエッチングにより層間絶縁膜32を貫通して形成されるトレンチに対して、層間絶縁膜32を構成するSiO2と選択比が取れる材質を埋め込むことによって構成される。例えば、分離構造体31を構成する材質として、窒化ケイ素や炭化ケイ素など(SiN, SiC(N)膜)を用いることができる。また、分離構造体31を構成する材質として、金属(例えば、Ti, Ta, W, Mo, Al, Cu, Co, Ni, Ruなど)を用いたり、それらの金属を含む化合物(例えば、TiN, TaN, WN, MoN)を用いたりしてもよい。
The isolation structure 31 is formed by filling a trench formed by penetrating the interlayer insulating film 32 by wet etching to surround the MIM capacitor 17 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32. Consisted of. For example, silicon nitride, silicon carbide, or the like (SiN, SiC(N) film) can be used as the material constituting the separation structure 31. In addition, as the material constituting the separation structure 31, metals (e.g., Ti, Ta, W, Mo, Al, Cu, Co, Ni, Ru, etc.) or compounds containing these metals (e.g., TiN, TaN, WN, MoN) may also be used.
MIMキャパシタ17どうしの間には貫通電極33が設けられ、貫通電極33によって下部配線41-3および上部配線42-3が電気的に接続される。例えば、貫通電極33を構成する材質としては、タングステンを用いることができる。
A through electrode 33 is provided between the MIM capacitors 17, and the lower wiring 41-3 and the upper wiring 42-3 are electrically connected by the through electrode 33. For example, tungsten can be used as the material for forming the through electrode 33.
このように構成される画素11は、隣接する他の画素11との間でMIMキャパシタ17を電気的に分離することができる。つまり、MIMキャパシタ17をCMOSイメージセンサに適用しても、MIMキャパシタ17どうしが導通することを回避することができる。また、画素11は、シリンダ形状を用いた三次元的な構造のMIMキャパシタ17を採用することで、例えば、二次元的な構造のMIMキャパシタと比較して高容量化を図ることができる。
The pixel 11 configured in this manner can electrically isolate the MIM capacitor 17 from other adjacent pixels 11. In other words, even if the MIM capacitors 17 are applied to a CMOS image sensor, conduction between the MIM capacitors 17 can be avoided. Further, by employing the MIM capacitor 17 having a three-dimensional structure using a cylinder shape, the pixel 11 can achieve higher capacitance than, for example, an MIM capacitor having a two-dimensional structure.
これにより、画素11を有する撮像素子は、例えば、HDR(High Dynamic Range)画像の撮像時におけるダイナミックレンジの拡大を図ることができ、より高画質な画像を撮像することができる。
Thereby, the image sensor having the pixels 11 can expand the dynamic range when capturing an HDR (High Dynamic Range) image, for example, and can capture a higher quality image.
<撮像素子の製造方法>
図4乃至図11を参照して、撮像素子の製造方法のうち、MIMキャパシタ17を形成する工程について説明する。 <Manufacturing method of image sensor>
With reference to FIGS. 4 to 11, the process of forming theMIM capacitor 17 in the method of manufacturing an image sensor will be described.
図4乃至図11を参照して、撮像素子の製造方法のうち、MIMキャパシタ17を形成する工程について説明する。 <Manufacturing method of image sensor>
With reference to FIGS. 4 to 11, the process of forming the
第1の工程において、図4に示すように、層間絶縁膜32の下側に下部配線41および絶縁膜44が形成され、層間絶縁膜32の上側に絶縁膜45が形成される。
In the first step, as shown in FIG. 4, a lower wiring 41 and an insulating film 44 are formed below the interlayer insulating film 32, and an insulating film 45 is formed above the interlayer insulating film 32.
第2の工程において、図5に示すように、絶縁膜45を開口し、層間絶縁膜32を貫通するように絶縁膜44までウェットエッチングにより形成されたトレンチに対して、上述したようなSiO2と選択比が取れる材質を埋め込むことによって分離構造体31が形成される。
In the second step, as shown in FIG. 5, the insulating film 45 is opened and the trench formed by wet etching to the insulating film 44 so as to penetrate the interlayer insulating film 32 is etched with SiO2 as described above. The separation structure 31 is formed by embedding a material that provides a selectivity.
第3の工程において、図6に示すように、MIMキャパシタ17のシリンダ形状を形成するための複数の凹部61が、層間絶縁膜32、絶縁膜44、および絶縁膜45を貫通するように形成される。即ち、複数の凹部61は、それぞれの底面に下部配線41が露出するように形成される。
In the third step, as shown in FIG. 6, a plurality of recesses 61 for forming the cylinder shape of the MIM capacitor 17 are formed to penetrate the interlayer insulating film 32, the insulating film 44, and the insulating film 45. Ru. That is, the plurality of recesses 61 are formed such that the lower wiring 41 is exposed at the bottom surface of each recess.
第4の工程において、図7に示すように、複数の凹部61それぞれの側面および底面に対して窒化チタンを成膜することで、複数の下部電極51が形成される。即ち、下部電極51は、凹部61の形状に沿って凹形状に形成される。
In the fourth step, as shown in FIG. 7, a plurality of lower electrodes 51 are formed by depositing titanium nitride on the side and bottom surfaces of each of the plurality of recesses 61. That is, the lower electrode 51 is formed in a concave shape along the shape of the concave portion 61 .
第5の工程において、図8に示すように、絶縁膜45に対してスリット34を加工した後、層間絶縁膜32を選択的にエッチバックして、分離構造体31よりも内側の層間絶縁膜32を除去する。即ち、隣接する層間絶縁膜32どうしの間の層間絶縁膜32だけが残るように、複数の下部電極51どうしの間の層間絶縁膜32がスリット34を介して除去される。このとき、個々の下部電極51の上端が絶縁膜45によって支持されている。
In the fifth step, as shown in FIG. 8, after forming the slits 34 in the insulating film 45, the interlayer insulating film 32 is selectively etched back to remove the interlayer insulating film inside the isolation structure 31. Remove 32. That is, the interlayer insulating film 32 between the plurality of lower electrodes 51 is removed through the slit 34 so that only the interlayer insulating film 32 between adjacent interlayer insulating films 32 remains. At this time, the upper end of each lower electrode 51 is supported by the insulating film 45.
第6の工程において、図9に示すように、下部電極51の両面に対して誘電体を成膜する。これにより、下部電極51の凹形状の内側に対して誘電膜52aが形成され、下部電極51の凹形状の外側に対して誘電膜52bが形成される。
In the sixth step, as shown in FIG. 9, a dielectric film is formed on both sides of the lower electrode 51. As a result, a dielectric film 52a is formed on the inside of the concave shape of the lower electrode 51, and a dielectric film 52b is formed on the outside of the concave shape of the lower electrode 51.
第7の工程において、図10に示すように、下部電極51の両面に対して窒化チタンを成膜する。これにより、下部電極51との間で誘電膜52aを挟み込むように上部電極53aが形成され、下部電極51との間で誘電膜52bを挟み込むように上部電極53bが形成される。
In the seventh step, as shown in FIG. 10, a film of titanium nitride is formed on both sides of the lower electrode 51. As a result, the upper electrode 53a is formed so as to sandwich the dielectric film 52a between it and the lower electrode 51, and the upper electrode 53b is formed so that the dielectric film 52b is sandwiched between it and the lower electrode 51.
第8の工程において、図11に示すように、層間絶縁膜32を積み増した後、隣接する分離構造体31どうしの間において、層間絶縁膜32、絶縁膜44、および絶縁膜45を貫通するように下部配線41-3が露出するまで形成されたトレンチに対してタングステンを埋め込むことによって、貫通電極33が形成される。また、上部電極53aに接続するように電極43を形成する。
In the eighth step, as shown in FIG. 11, after the interlayer insulating film 32 is stacked, the interlayer insulating film 32, the insulating film 44, and the insulating film 45 are penetrated between adjacent isolation structures 31. The through electrode 33 is formed by filling tungsten into the trench formed until the lower wiring 41-3 is exposed. Further, an electrode 43 is formed so as to be connected to the upper electrode 53a.
その後、電極43および貫通電極33それぞれに接続するように上部配線42を形成することで、上述の図3に示したようなMIMキャパシタ17が形成される。
Thereafter, the upper wiring 42 is formed so as to be connected to the electrode 43 and the through electrode 33, respectively, thereby forming the MIM capacitor 17 as shown in FIG. 3 described above.
以上のような工程で形成されるMIMキャパシタ17は、例えば、個々の下部電極51を絶縁膜45によって支持することで、機械的強度の向上を図ることができる。また、層間絶縁膜32を選択的にエッチバックする際に、分離構造体31によってエッチングを止めることができる。
The mechanical strength of the MIM capacitor 17 formed through the steps described above can be improved by, for example, supporting the individual lower electrodes 51 with the insulating film 45. Furthermore, when selectively etching back the interlayer insulating film 32, the isolation structure 31 can stop the etching.
<MIMキャパシタの変形例>
図12は、MIMキャパシタ17の変形例の一例を示す断面図である。 <Modified example of MIM capacitor>
FIG. 12 is a cross-sectional view showing an example of a modification of theMIM capacitor 17.
図12は、MIMキャパシタ17の変形例の一例を示す断面図である。 <Modified example of MIM capacitor>
FIG. 12 is a cross-sectional view showing an example of a modification of the
上述したように、図3に示したMIMキャパシタ17では、層間絶縁膜32を貫通するように形成されるトレンチに、層間絶縁膜32を構成するSiO2と選択比が取れる材質を埋め込むことによって分離構造体31が構成されていた。
As described above, in the MIM capacitor 17 shown in FIG. 3, an isolation structure is created by filling a trench formed to penetrate the interlayer insulating film 32 with a material that has a selectivity with SiO2 constituting the interlayer insulating film 32. A body 31 was constructed.
これに対し、図12に示すMIMキャパシタ17Aでは、分離構造体31Aは、下部電極51、上部電極53a、および誘電膜52aと同一の材質によって形成される。つまり、MIMキャパシタ17Aでは、下部電極51を形成する金属、誘電膜52aを形成する誘電体、および上部電極53aを形成する金属が積層された積層構造によって分離構造体31Aが構成されている。
On the other hand, in the MIM capacitor 17A shown in FIG. 12, the isolation structure 31A is formed of the same material as the lower electrode 51, the upper electrode 53a, and the dielectric film 52a. That is, in the MIM capacitor 17A, the isolation structure 31A is configured by a laminated structure in which a metal forming the lower electrode 51, a dielectric forming the dielectric film 52a, and a metal forming the upper electrode 53a are stacked.
これにより、分離構造体31を形成するためだけの工程が不要となり、下部電極51、上部電極53a、および誘電膜52aを形成する工程で、同時に、分離構造体31Aを形成することができる。つまり、MIMキャパシタ17Aのシリンダ形状を形成するための複数の凹部61(図6参照)と同時に、分離構造体31Aを形成するためのトレンチを形成する。そして、下部電極51、上部電極53a、および誘電膜52aを形成する際に、そのトレンチに対して、下部電極51を形成する金属、誘電膜52aを形成する誘電体、および上部電極53aを形成する金属が積層されることで分離構造体31Aが形成される。
This eliminates the need for a process solely for forming the isolation structure 31, and allows the isolation structure 31A to be formed simultaneously in the process of forming the lower electrode 51, the upper electrode 53a, and the dielectric film 52a. That is, at the same time as the plurality of recesses 61 (see FIG. 6) for forming the cylinder shape of the MIM capacitor 17A, a trench for forming the isolation structure 31A is formed. Then, when forming the lower electrode 51, the upper electrode 53a, and the dielectric film 52a, the metal forming the lower electrode 51, the dielectric forming the dielectric film 52a, and the upper electrode 53a are formed in the trench. The separation structure 31A is formed by stacking metals.
このように、MIMキャパシタ17Aは、その外周の一部分によって分離構造体31を構成することができ、例えば、製造工程を削減することでコストダウンを図ることができる。
In this way, the MIM capacitor 17A can form the isolation structure 31 by a portion of its outer periphery, and for example, costs can be reduced by reducing the manufacturing process.
なお、本技術は、上述したように、光電変換部12から転送される電荷を蓄積するための容量を切り替える用途に用いられるMIMキャパシタ17に適用するのに限定されることはなく、画素11内で、他の用途に用いられるMIMキャパシタに適用してもよい。
Note that, as described above, the present technology is not limited to application to the MIM capacitor 17 used for switching the capacitance for accumulating charges transferred from the photoelectric conversion unit 12, but is applicable to Therefore, it may be applied to MIM capacitors used for other purposes.
<電子機器の構成例>
上述したような画素11を備える撮像素子は、例えば、デジタルスチルカメラやデジタルビデオカメラなどの撮像システム、撮像機能を備えた携帯電話機、または、撮像機能を備えた他の機器といった各種の電子機器に適用することができる。 <Example of configuration of electronic equipment>
The image sensor including thepixels 11 as described above can be used in various electronic devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone with an imaging function, or other equipment with an imaging function. Can be applied.
上述したような画素11を備える撮像素子は、例えば、デジタルスチルカメラやデジタルビデオカメラなどの撮像システム、撮像機能を備えた携帯電話機、または、撮像機能を備えた他の機器といった各種の電子機器に適用することができる。 <Example of configuration of electronic equipment>
The image sensor including the
図13は、電子機器に搭載される撮像装置の構成例を示すブロック図である。
FIG. 13 is a block diagram showing a configuration example of an imaging device installed in an electronic device.
図13に示すように、撮像装置101は、光学系102、撮像素子103、信号処理回路104、モニタ105、およびメモリ106を備えて構成され、静止画像および動画像を撮像可能である。
As shown in FIG. 13, the imaging device 101 includes an optical system 102, an image sensor 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.
光学系102は、1枚または複数枚のレンズを有して構成され、被写体からの像光(入射光)を撮像素子103に導き、撮像素子103の受光面(センサ部)に結像させる。
The optical system 102 is configured with one or more lenses, guides image light (incident light) from the subject to the image sensor 103, and forms an image on the light-receiving surface (sensor section) of the image sensor 103.
撮像素子103としては、上述した画素11を備える撮像素子が適用される。撮像素子103には、光学系102を介して受光面に結像される像に応じて、一定期間、電子が蓄積される。そして、撮像素子103に蓄積された電子に応じた信号が信号処理回路104に供給される。
As the image sensor 103, an image sensor including the pixels 11 described above is applied. Electrons are accumulated in the image sensor 103 for a certain period of time depending on the image formed on the light-receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to the signal processing circuit 104.
信号処理回路104は、撮像素子103から出力された画素信号に対して各種の信号処理を施す。信号処理回路104が信号処理を施すことにより得られた画像(画像データ)は、モニタ105に供給されて表示されたり、メモリ106に供給されて記憶(記録)されたりする。
The signal processing circuit 104 performs various signal processing on the pixel signals output from the image sensor 103. An image (image data) obtained by signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 for display, or supplied to a memory 106 for storage (recording).
このように構成されている撮像装置101では、上述した画素11を備える撮像素子を適用することで、例えば、より高画質な画像を撮像することができる。
In the imaging device 101 configured in this way, by applying an imaging element including the above-described pixels 11, it is possible to capture, for example, a higher quality image.
<イメージセンサの使用例>
図14は、上述のイメージセンサ(撮像素子)を使用する使用例を示す図である。 <Example of image sensor usage>
FIG. 14 is a diagram showing an example of use of the above-described image sensor (imaging device).
図14は、上述のイメージセンサ(撮像素子)を使用する使用例を示す図である。 <Example of image sensor usage>
FIG. 14 is a diagram showing an example of use of the above-described image sensor (imaging device).
上述したイメージセンサは、例えば、以下のように、可視光や、赤外光、紫外光、X線等の光をセンシングする様々なケースに使用することができる。
The above-described image sensor can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below.
・ディジタルカメラや、カメラ機能付きの携帯機器等の、鑑賞の用に供される画像を撮影する装置
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置 ・Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes Devices used for transportation, such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc. ・User gestures Devices used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate devices according to the gestures. - Endoscopes, devices that perform blood vessel imaging by receiving infrared light, etc. - Devices used for medical and healthcare purposes - Devices used for security, such as surveillance cameras for crime prevention and cameras for person authentication - Skin measurement devices that take pictures of the skin, and devices that take pictures of the scalp - Devices used for beauty purposes, such as microscopes for skin care. - Devices used for sports, such as action cameras and wearable cameras. - Cameras, etc. used to monitor the condition of fields and crops. , equipment used for agricultural purposes
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供される装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置 ・Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes Devices used for transportation, such as in-vehicle sensors that take pictures of the rear, surroundings, and interior of the car, surveillance cameras that monitor moving vehicles and roads, and distance sensors that measure the distance between vehicles, etc. ・User gestures Devices used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate devices according to the gestures. - Endoscopes, devices that perform blood vessel imaging by receiving infrared light, etc. - Devices used for medical and healthcare purposes - Devices used for security, such as surveillance cameras for crime prevention and cameras for person authentication - Skin measurement devices that take pictures of the skin, and devices that take pictures of the scalp - Devices used for beauty purposes, such as microscopes for skin care. - Devices used for sports, such as action cameras and wearable cameras. - Cameras, etc. used to monitor the condition of fields and crops. , equipment used for agricultural purposes
<構成の組み合わせ例>
なお、本技術は以下のような構成も取ることができる。
(1)
複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を備える固体撮像素子。
(2)
前記分離部は、前記キャパシタを囲って前記画素ごとに設けられ、
それぞれの前記画素の前記分離部どうしの間には層間絶縁膜が設けられる
上記(1)に記載の固体撮像素子。
(3)
前記分離部どうしの間の前記層間絶縁膜を貫通し、前記上部配線および前記下部配線を接続する貫通電極
をさらに備える上記(2)に記載の固体撮像素子。
(4)
前記分離部は、前記層間絶縁膜と選択比が取れる材質をトレンチに埋め込むことで形成される
上記(2)または(3)に記載の固体撮像素子。
(5)
前記材質として、窒化ケイ素または炭化ケイ素が用いられる
上記(4)に記載の固体撮像素子。
(6)
前記材質として、金属、または、前記金属を含む化合物が用いられる
上記(4)に記載の固体撮像素子。
(7)
前記キャパシタは、前記上部配線に接続される筒形の上部電極と前記下部配線に接続される筒形の下部電極とで誘電膜を挟み込んだシリンダ形状を複数有して構成される
上記(1)から(6)までのいずれかに記載の固体撮像素子。
(8)
前記キャパシタは、前記シリンダ形状を構成する個々の高アスペクト比の凹部に沿って形成された凹形状の前記下部電極の両面に前記誘電膜が成膜され、それぞれの前記誘電膜を挟み込むように前記上部電極を設けることにより構成される
上記(7)に記載の固体撮像素子。
(9)
前記シリンダ形状を構成する個々の前記下部電極の上端が絶縁膜によって支持される
上記(7)または(8)に記載の固体撮像素子。
(10)
前記分離部は、前記キャパシタを構成する前記上部電極、前記下部配線、および前記誘電膜と同一の材質が積層された積層構造によって形成される
上記(7)から(9)までのいずれかに記載の固体撮像素子。
(11)
複数の画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタを形成することと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部を形成することと
を含む固体撮像素子の製造方法。
(12)
複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を有する固体撮像素子を備える電子機器。 <Example of configuration combinations>
Note that the present technology can also have the following configuration.
(1)
multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A solid-state imaging device comprising: an isolation section that electrically isolates the capacitors of the adjacent pixels.
(2)
The isolation section is provided for each pixel surrounding the capacitor,
The solid-state imaging device according to (1) above, wherein an interlayer insulating film is provided between the separation portions of each of the pixels.
(3)
The solid-state imaging device according to (2) above, further comprising a through electrode that penetrates the interlayer insulating film between the separation parts and connects the upper wiring and the lower wiring.
(4)
The solid-state imaging device according to (2) or (3), wherein the isolation portion is formed by filling a trench with a material that has a selectivity with respect to the interlayer insulating film.
(5)
The solid-state imaging device according to (4) above, wherein silicon nitride or silicon carbide is used as the material.
(6)
The solid-state imaging device according to (4) above, wherein the material is a metal or a compound containing the metal.
(7)
The capacitor is configured to have a plurality of cylindrical shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring. The solid-state imaging device according to any one of (6) to (6).
(8)
In the capacitor, the dielectric film is formed on both sides of the concave lower electrode formed along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film is formed on both sides of the concave lower electrode, and the dielectric film is formed on both sides of the concave lower electrode formed along each of the high aspect ratio concave portions constituting the cylinder shape. The solid-state imaging device according to (7) above, which is configured by providing an upper electrode.
(9)
The solid-state imaging device according to (7) or (8) above, wherein an upper end of each of the lower electrodes forming the cylinder shape is supported by an insulating film.
(10)
According to any one of (7) to (9) above, the separation part is formed by a laminated structure in which the same materials as the upper electrode, the lower wiring, and the dielectric film that constitute the capacitor are laminated. solid-state image sensor.
(11)
forming a capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A method for manufacturing a solid-state imaging device, comprising: forming an isolation portion that electrically isolates the capacitors of the adjacent pixels.
(12)
multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
An electronic device comprising: a solid-state imaging device; and a separation section that electrically isolates the capacitors of the adjacent pixels.
なお、本技術は以下のような構成も取ることができる。
(1)
複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を備える固体撮像素子。
(2)
前記分離部は、前記キャパシタを囲って前記画素ごとに設けられ、
それぞれの前記画素の前記分離部どうしの間には層間絶縁膜が設けられる
上記(1)に記載の固体撮像素子。
(3)
前記分離部どうしの間の前記層間絶縁膜を貫通し、前記上部配線および前記下部配線を接続する貫通電極
をさらに備える上記(2)に記載の固体撮像素子。
(4)
前記分離部は、前記層間絶縁膜と選択比が取れる材質をトレンチに埋め込むことで形成される
上記(2)または(3)に記載の固体撮像素子。
(5)
前記材質として、窒化ケイ素または炭化ケイ素が用いられる
上記(4)に記載の固体撮像素子。
(6)
前記材質として、金属、または、前記金属を含む化合物が用いられる
上記(4)に記載の固体撮像素子。
(7)
前記キャパシタは、前記上部配線に接続される筒形の上部電極と前記下部配線に接続される筒形の下部電極とで誘電膜を挟み込んだシリンダ形状を複数有して構成される
上記(1)から(6)までのいずれかに記載の固体撮像素子。
(8)
前記キャパシタは、前記シリンダ形状を構成する個々の高アスペクト比の凹部に沿って形成された凹形状の前記下部電極の両面に前記誘電膜が成膜され、それぞれの前記誘電膜を挟み込むように前記上部電極を設けることにより構成される
上記(7)に記載の固体撮像素子。
(9)
前記シリンダ形状を構成する個々の前記下部電極の上端が絶縁膜によって支持される
上記(7)または(8)に記載の固体撮像素子。
(10)
前記分離部は、前記キャパシタを構成する前記上部電極、前記下部配線、および前記誘電膜と同一の材質が積層された積層構造によって形成される
上記(7)から(9)までのいずれかに記載の固体撮像素子。
(11)
複数の画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタを形成することと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部を形成することと
を含む固体撮像素子の製造方法。
(12)
複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を有する固体撮像素子を備える電子機器。 <Example of configuration combinations>
Note that the present technology can also have the following configuration.
(1)
multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A solid-state imaging device comprising: an isolation section that electrically isolates the capacitors of the adjacent pixels.
(2)
The isolation section is provided for each pixel surrounding the capacitor,
The solid-state imaging device according to (1) above, wherein an interlayer insulating film is provided between the separation portions of each of the pixels.
(3)
The solid-state imaging device according to (2) above, further comprising a through electrode that penetrates the interlayer insulating film between the separation parts and connects the upper wiring and the lower wiring.
(4)
The solid-state imaging device according to (2) or (3), wherein the isolation portion is formed by filling a trench with a material that has a selectivity with respect to the interlayer insulating film.
(5)
The solid-state imaging device according to (4) above, wherein silicon nitride or silicon carbide is used as the material.
(6)
The solid-state imaging device according to (4) above, wherein the material is a metal or a compound containing the metal.
(7)
The capacitor is configured to have a plurality of cylindrical shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring. The solid-state imaging device according to any one of (6) to (6).
(8)
In the capacitor, the dielectric film is formed on both sides of the concave lower electrode formed along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film is formed on both sides of the concave lower electrode, and the dielectric film is formed on both sides of the concave lower electrode formed along each of the high aspect ratio concave portions constituting the cylinder shape. The solid-state imaging device according to (7) above, which is configured by providing an upper electrode.
(9)
The solid-state imaging device according to (7) or (8) above, wherein an upper end of each of the lower electrodes forming the cylinder shape is supported by an insulating film.
(10)
According to any one of (7) to (9) above, the separation part is formed by a laminated structure in which the same materials as the upper electrode, the lower wiring, and the dielectric film that constitute the capacitor are laminated. solid-state image sensor.
(11)
forming a capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A method for manufacturing a solid-state imaging device, comprising: forming an isolation portion that electrically isolates the capacitors of the adjacent pixels.
(12)
multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
An electronic device comprising: a solid-state imaging device; and a separation section that electrically isolates the capacitors of the adjacent pixels.
なお、本実施の形態は、上述した実施の形態に限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。また、本明細書に記載された効果はあくまで例示であって限定されるものではなく、他の効果があってもよい。
Note that this embodiment is not limited to the embodiment described above, and various changes can be made without departing from the gist of the present disclosure. Moreover, the effects described in this specification are merely examples and are not limited, and other effects may also be present.
11 画素, 12 光電変換部, 13 転送トランジスタ, 14 第1のFD部, 15 接続トランジスタ, 16 第2のFD部, 17 MIMキャパシタ, 18 リセットトランジスタ, 19 増幅トランジスタ, 20 選択トランジスタ, 21 垂直信号線, 31 分離構造体, 32 層間絶縁膜, 33 貫通電極, 34 スリット, 41 下部配線, 42 上部配線, 43 電極, 44および45 絶縁膜, 51 下部電極, 52 誘電膜, 53 上部電極
11 Pixel, 12 Photoelectric conversion section, 13 Transfer transistor, 14 First FD section, 15 Connection transistor, 16 Second FD section, 17 MIM capacitor, 18 Reset transistor, 19 Amplification transistor, 20 Selection transistor, 21 Vertical signal line , 31 Separation structure, 32 Interlayer insulating film, 33 Through electrode, 34 Slit, 41 Lower wiring, 42 Upper wiring, 43 Electrode, 44 and 45 Insulating film, 51 Lower electrode, 52 Dielectric film, 53 Upper electrode
Claims (12)
- 複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を備える固体撮像素子。 multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A solid-state imaging device comprising: an isolation section that electrically isolates the capacitors of the adjacent pixels. - 前記分離部は、前記キャパシタを囲って前記画素ごとに設けられ、
それぞれの前記画素の前記分離部どうしの間には層間絶縁膜が設けられる
請求項1に記載の固体撮像素子。 The isolation section is provided for each pixel surrounding the capacitor,
The solid-state imaging device according to claim 1, wherein an interlayer insulating film is provided between the separation portions of each of the pixels. - 前記分離部どうしの間の前記層間絶縁膜を貫通し、前記上部配線および前記下部配線を接続する貫通電極
をさらに備える請求項2に記載の固体撮像素子。 The solid-state imaging device according to claim 2, further comprising: a through electrode that penetrates the interlayer insulating film between the separation parts and connects the upper wiring and the lower wiring. - 前記分離部は、前記層間絶縁膜と選択比が取れる材質をトレンチに埋め込むことで形成される
請求項2に記載の固体撮像素子。 The solid-state imaging device according to claim 2, wherein the isolation portion is formed by filling a trench with a material that has a selectivity with respect to the interlayer insulating film. - 前記材質として、窒化ケイ素または炭化ケイ素が用いられる
請求項4に記載の固体撮像素子。 The solid-state imaging device according to claim 4, wherein silicon nitride or silicon carbide is used as the material. - 前記材質として、金属、または、前記金属を含む化合物が用いられる
請求項4に記載の固体撮像素子。 The solid-state imaging device according to claim 4, wherein the material is a metal or a compound containing the metal. - 前記キャパシタは、前記上部配線に接続される筒形の上部電極と前記下部配線に接続される筒形の下部電極とで誘電膜を挟み込んだシリンダ形状を複数有して構成される
請求項1に記載の固体撮像素子。 The capacitor is configured to have a plurality of cylindrical shapes in which a dielectric film is sandwiched between a cylindrical upper electrode connected to the upper wiring and a cylindrical lower electrode connected to the lower wiring. The solid-state imaging device described. - 前記キャパシタは、前記シリンダ形状を構成する個々の高アスペクト比の凹部に沿って形成された凹形状の前記下部電極の両面に前記誘電膜が成膜され、それぞれの前記誘電膜を挟み込むように前記上部電極を設けることにより構成される
請求項7に記載の固体撮像素子。 In the capacitor, the dielectric film is formed on both sides of the concave lower electrode formed along each high aspect ratio concave portion constituting the cylinder shape, and the dielectric film is formed on both sides of the concave lower electrode, and the dielectric film is formed on both sides of the concave lower electrode formed along each of the high aspect ratio concave portions constituting the cylinder shape. The solid-state imaging device according to claim 7, configured by providing an upper electrode. - 前記シリンダ形状を構成する個々の前記下部電極の上端が絶縁膜によって支持される
請求項7に記載の固体撮像素子。 The solid-state imaging device according to claim 7, wherein an upper end of each of the lower electrodes forming the cylinder shape is supported by an insulating film. - 前記分離部は、前記キャパシタを構成する前記上部電極、前記下部配線、および前記誘電膜と同一の材質が積層された積層構造によって形成される
請求項7に記載の固体撮像素子。 The solid-state imaging device according to claim 7, wherein the separation section is formed of a laminated structure in which the same materials as the upper electrode, the lower wiring, and the dielectric film that constitute the capacitor are laminated. - 複数の画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタを形成することと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部を形成することと
を含む固体撮像素子の製造方法。 forming a capacitor that is provided for each of a plurality of pixels and has a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
A method for manufacturing a solid-state imaging device, comprising: forming an isolation portion that electrically isolates the capacitors of the adjacent pixels. - 複数の画素と、
前記画素ごとに設けられ、前記画素の配線層の上部配線および下部配線の間に立体形状で構成されるキャパシタと、
隣接する前記画素の前記キャパシタどうしの間を電気的に分離する分離部と
を有する固体撮像素子を備える電子機器。 multiple pixels,
a capacitor provided for each pixel and configured in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixel;
An electronic device comprising: a solid-state imaging device; and a separation section that electrically isolates the capacitors of the adjacent pixels.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2022142692 | 2022-09-08 | ||
JP2022-142692 | 2022-09-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2024053372A1 true WO2024053372A1 (en) | 2024-03-14 |
Family
ID=90190988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2023/029937 WO2024053372A1 (en) | 2022-09-08 | 2023-08-21 | Solid-state imaging element and manufacturing method, and electronic device |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2024053372A1 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554788B2 (en) * | 2002-06-12 | 2009-06-30 | Samsung Electronics Co., Ltd. | Capacitor for a semiconductor device |
US20120306057A1 (en) * | 2011-05-30 | 2012-12-06 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device |
JP2013153103A (en) * | 2012-01-26 | 2013-08-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
JP2020129795A (en) * | 2019-02-11 | 2020-08-27 | 三星電子株式会社Samsung Electronics Co.,Ltd. | Image sensor and method of driving the same |
WO2020261817A1 (en) * | 2019-06-25 | 2020-12-30 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging element and method for manufacturing solid-state imaging element |
US20220052086A1 (en) * | 2020-08-13 | 2022-02-17 | Samsung Electronics Co., Ltd. | Image sensor |
JP2022045912A (en) * | 2020-09-09 | 2022-03-22 | 三星電子株式会社 | Image sensor |
-
2023
- 2023-08-21 WO PCT/JP2023/029937 patent/WO2024053372A1/en unknown
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554788B2 (en) * | 2002-06-12 | 2009-06-30 | Samsung Electronics Co., Ltd. | Capacitor for a semiconductor device |
US20120306057A1 (en) * | 2011-05-30 | 2012-12-06 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device |
JP2013153103A (en) * | 2012-01-26 | 2013-08-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
JP2020129795A (en) * | 2019-02-11 | 2020-08-27 | 三星電子株式会社Samsung Electronics Co.,Ltd. | Image sensor and method of driving the same |
WO2020261817A1 (en) * | 2019-06-25 | 2020-12-30 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state imaging element and method for manufacturing solid-state imaging element |
US20220052086A1 (en) * | 2020-08-13 | 2022-02-17 | Samsung Electronics Co., Ltd. | Image sensor |
JP2022045912A (en) * | 2020-09-09 | 2022-03-22 | 三星電子株式会社 | Image sensor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102536429B1 (en) | Imaging device, method for manufacturing the same, and electronic device | |
KR102590610B1 (en) | Imaging device and driving method, and electronic device | |
WO2017169882A1 (en) | Image pickup element, method for manufacturing image pickup element, and electronic apparatus | |
US12047700B2 (en) | Imaging element, driving method, and electronic device | |
CN209845132U (en) | Pixel circuit of solid-state high dynamic range image sensor and image sensor | |
TW201640664A (en) | Solid-state imaging device, method for manufacturing same, and electronic instrument | |
CN105934826A (en) | Solid-state image pickup element, image pickup device, and electronic apparatus | |
JP6856974B2 (en) | Solid-state image sensor and electronic equipment | |
KR20180066020A (en) | Solid-state image sensors, and electronic devices | |
JP2017183636A (en) | Solid imaging element, sensor device, and electronic apparatus | |
TW201201364A (en) | Solid-state image capturing device and electronic device | |
JP7403993B2 (en) | Solid-state imaging device and its manufacturing method, and electronic equipment | |
CN108780801B (en) | Semiconductor device, solid-state imaging element, imaging device, and electronic apparatus | |
CN107408567B (en) | Solid-state image capturing element and electronic device | |
JP6816014B2 (en) | Solid-state image sensor, manufacturing method, and electronic equipment | |
WO2024053372A1 (en) | Solid-state imaging element and manufacturing method, and electronic device | |
WO2023153300A1 (en) | Solid-state imaging element, manufacturing method, and electronic apparatus | |
WO2024162013A1 (en) | Solid-state imaging element, manufacturing method, and electronic apparatus | |
WO2024043069A1 (en) | Solid-state imaging device | |
WO2023157620A1 (en) | Solid-state imaging device and electronic apparatus | |
WO2019224936A1 (en) | Solid-state image capture device and image capture device | |
US20120080731A1 (en) | Photodetector isolation in image sensors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 23862912 Country of ref document: EP Kind code of ref document: A1 |