JP6856974B2 - Solid-state image sensor and electronic equipment - Google Patents

Description

The present disclosure relates to a solid-state image sensor and an electronic device, and more particularly to a solid-state image sensor and an electronic device whose capacity can be reduced by using a hollow region.

In a CMOS (Complementary Metal-Oxide Semiconductor) image sensor, as the pixel miniaturization progresses, the aperture area of the photodiode decreases and the sensitivity decreases. In addition, the size of the pixel transistor is reduced, and random noise is exacerbated. As a result, the S / N (Signal / Noise) ratio decreases and the image quality deteriorates.

Therefore, it is considered to improve the S / N ratio by reducing the parasitic capacitance of the FD (floating diffusion) and improving the charge-voltage conversion efficiency.

The parasitic capacitance of the FD includes the diffusion capacitance of the FD, the capacitance of the gate electrode of the amplification transistor connected to the FD via the FD wiring, the capacitance of the FD wiring, and the like. The diffusion capacity of the FD can be reduced by reducing the concentration of N-type impurities in the FD. However, in this case, there is a concern about poor contact.

Further, the capacitance of the gate electrode of the amplification transistor can be reduced by reducing the size of the amplification transistor. However, as the size of the amplification transistor decreases, the random noise worsens.

Further, the capacity of the FD wiring can be reduced to some extent by devising the wiring layout or the like. However, since the FD needs to be connected to the amplification transistor, the wiring layout is limited based on the pixel sharing method. Therefore, it is difficult to reduce the capacity of the FD wiring by devising the wiring layout.

Therefore, a method has been devised to reduce the capacitance of the FD wiring by changing the entire periphery of the wiring layer to a low dielectric constant film (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2009-231501

As a method for reducing the capacity, a method other than the method described in Patent Document 1 is desired.

The present disclosure has been made in view of such a situation, and makes it possible to reduce the capacity by using a hollow region.

The solid-state imaging device on one side of the present disclosure has a first wiring for connecting the floating diffusion and the FD wiring, and a second wiring for connecting the amplification transistor and the FD wiring, and the first wiring. The region between the second wiring and the second wiring is configured to be a plurality of hollow regions, and the FD wiring is in a direction perpendicular to the light incident surface with the floating diffusion and the amplification transistor, respectively. It is a solid-state imaging element arranged at an overlapping position.

The electronic device on one side of the present disclosure corresponds to the solid-state image sensor on the one side of the present disclosure.

In one aspect of the present disclosure, the first wiring for connecting the floating diffusion and the FD wiring and the second wiring for connecting the amplification transistor and the FD wiring are provided, and the first wiring and the first wiring are provided. The region between the two wirings is configured to be a plurality of hollow regions, and the FD wiring is arranged at a position perpendicular to the light incident surface and overlapping the floating diffusion and the amplification transistor, respectively. To.

According to one aspect of the present disclosure, the capacity can be reduced. Further, according to one aspect of the present disclosure, the hollow region can be used to reduce the capacity.

The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure which shows the structural example of the 1st Embodiment of a CMOS image sensor as a solid-state image sensor to which this disclosure is applied. It is a figure which shows the circuit structure example of the pixel which is arranged two-dimensionally in the pixel area of FIG. It is a figure which shows the 1st structural example of a CMOS image sensor. It is a figure which shows the 2nd structural example of a CMOS image sensor. It is a figure which shows the 3rd structural example of a CMOS image sensor. It is a figure which shows the 4th structural example of a CMOS image sensor. It is a figure which shows the circuit structure example of the pixel of the 2nd Embodiment of the CMOS image sensor to which this disclosure is applied. It is a figure which shows the arrangement example of each part of the 3rd Embodiment of a CMOS image sensor. FIG. 5 is a plan view of a first structural example of the pixel region of FIG. 8 as viewed from the wiring layer side. 9 is a cross-sectional view taken along the line AA and a cross-sectional view taken along the line BB'. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. 9 and FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. 9 and FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. 9 and FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. 9 and FIG. 9 is a cross-sectional view taken along the line AA'of FIG. 9 of a second structural example of the pixel region of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. 9 is a cross-sectional view taken along the line AA'of FIG. 9 of another second structural example of the pixel region of FIG. FIG. 9 is a cross-sectional view taken along the line AA'of FIG. 9 of a third structural example of the pixel region of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. It is a figure explaining the manufacturing method of the semiconductor substrate of FIG. It is a figure which shows the other structural example of the hollow region between the FD wiring and a semiconductor substrate. It is a figure explaining the 1st manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 1st manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 1st manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 2nd manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 2nd manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 2nd manufacturing method of the CMOS image sensor of FIG. It is a figure explaining the 2nd manufacturing method of the CMOS image sensor of FIG. It is a figure which shows the other structural example of the hollow region around the TSV. It is a top view explaining the arrangement of the hollow region in 4th Embodiment of a CMOS image sensor. It is a figure which shows the example of another shape of the hollow region around the FD wiring of FIG. 33. It is a top view which shows the example of the shape of the hollow region formed around the TSV. It is a block diagram which shows the structural example of the image pickup apparatus as an electronic device to which this disclosure is applied. It is a figure which shows the use example using the said CMOS image sensor.

Hereinafter, embodiments for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment: CMOS image sensor (FIGS. 1 to 6)
2. Second embodiment: CMOS image sensor (Fig. 7)
3. 3. Third Embodiment: CMOS image sensor (FIGS. 8 to 32)
4. Fourth Embodiment: CMOS image sensor (FIGS. 33 to 35)
5. Fifth Embodiment: Electronic device (FIG. 36)
6. Usage example of CMOS image sensor (Fig. 37)

<First Embodiment>
(Structure example of the first embodiment of the CMOS image sensor)
FIG. 1 is a diagram showing a configuration example of a first embodiment of a CMOS image sensor as a solid-state image sensor to which the present disclosure is applied.

The CMOS image sensor 50 includes a pixel area 51, a pixel drive line 52, a vertical signal line 53, a vertical drive unit 54, a column processing unit 55, a horizontal drive unit 56, a system control unit 57, a signal processing unit 58, and a memory unit 59. , It is formed on a semiconductor substrate (chip) such as a silicon substrate (not shown).

In the pixel region 51 of the CMOS image sensor 50, pixels having a photoelectric conversion element that generates a charge amount corresponding to the amount of incident light and accumulates it inside are two-dimensionally arranged in a matrix to perform imaging. Further, in the pixel region 51, a pixel drive line 52 is formed for each row with respect to the matrix-shaped pixels, and a vertical signal line 53 is formed for each column.

The vertical drive unit 54 is composed of a shift register, an address decoder, and the like, and drives each pixel of the pixel area 51 in units of rows. One end of the pixel drive line 52 is connected to an output end (not shown) corresponding to each line of the vertical drive unit 54. Although the specific configuration of the vertical drive unit 54 is not shown, the vertical drive unit 54 has two scanning systems, a read scanning system and a sweep scanning system.

The read-out scanning system selects each line in order so as to read the pixel signals from each pixel in order in line units, and outputs the selection signal or the like from the output end connected to the pixel drive line 52 of the selected line. As a result, the pixels in the row selected by the readout scanning system read out the electric signal of the electric charge accumulated in the photoelectric conversion element as a pixel signal and supply it to the vertical signal line 53.

The sweep-out scanning system turns on the reset signal output from the output end connected to the pixel drive line 52 of each row in order to sweep (reset) unnecessary charges from the photoelectric conversion element. By scanning by this sweep-out scanning system, a so-called electronic shutter operation is sequentially performed row by row. Here, the electronic shutter operation refers to an operation of discarding the electric charge of the photoelectric conversion element and starting a new exposure (starting the accumulation of electric charge).

The column processing unit 55 has a signal processing circuit for each column of the pixel area 51. Each signal processing circuit of the column processing unit 55 performs signal processing such as A / D conversion processing on the pixel signal output from each pixel of the selected line through the vertical signal line 53. The column processing unit 55 temporarily holds the pixel signal after signal processing.

The horizontal drive unit 56 is composed of a shift register, an address decoder, and the like, and sequentially selects the signal processing circuits of the column processing unit 55. By the selective scanning by the horizontal drive unit 56, the pixel signals signal-processed by each signal processing circuit of the column processing unit 55 are sequentially output to the signal processing unit 58.

The system control unit 57 is composed of a timing generator or the like that generates various timing signals, and controls the vertical drive unit 54, the column processing unit 55, and the horizontal drive unit 56 based on the various timing signals generated by the timing generator. To do.

The signal processing unit 58 performs various signal processing on the pixel signal output from the column processing unit 55. At this time, the signal processing unit 58 stores the intermediate result of signal processing and the like in the memory unit 59 as necessary, and refers to the signal processing unit 58 at a necessary timing. The signal processing unit 58 outputs the pixel signal after signal processing.

The memory unit 59 is composed of a DRAM (Dynamic Random Access Memory), a SRAM (Static Random Access Memory), or the like.

(Example of pixel circuit configuration)
FIG. 2 is a diagram showing a circuit configuration example of pixels two-dimensionally arranged in the pixel region 51 of FIG.

The pixel 90 includes a photodiode 91 as a photoelectric conversion element, a transfer transistor 92, an FD 93, a reset transistor 94, an amplification transistor 95, and a selection transistor 96.

The photodiode 91 generates and accumulates an electric charge according to the amount of received light. The anode terminal of the photodiode 91 is grounded, and the cathode terminal is connected to the FD 93 via the transfer transistor 92.

The gate terminal of the transfer transistor 92 is connected to a line that supplies a transfer signal among the pixel drive lines 52 formed for the pixel 90. When the transfer transistor 92 is turned on by the transfer signal, the transfer transistor 92 reads out the electric charge generated by the photodiode 91 and transfers it to the FD 93.

The FD 93 holds the charge read from the photodiode 91. The gate terminal of the reset transistor 94 is connected to a line that supplies a reset signal among the pixel drive lines 52 formed for the pixel 90. When the reset transistor 94 is turned on by the reset signal, the charge accumulated in the FD 93 is discharged to the power supply 97 having the potential VDD to reset the potential of the FD 93.

The gate terminal of the amplification transistor 95 is connected to the FD 93, and the amplification transistor 95 outputs a pixel signal corresponding to the potential of the FD 93 using the power supply 97.

The gate terminal of the selection transistor 96 is connected to a line that supplies a selection signal among the pixel drive lines 52 formed for the pixel 90. When the selection transistor 96 is turned on by the selection signal, the pixel signal output from the amplification transistor 95 is supplied to the column processing unit 55 of FIG. 1 via the vertical signal line 53.

The FD 93 may be shared among a plurality of pixels 90.

(First structural example of CMOS image sensor)
FIG. 3 is a diagram showing a first structural example of the CMOS image sensor 50.

As shown in FIG. 3, the CMOS image sensor 50 is configured by laminating a wiring layer 112 on a semiconductor substrate 111 such as a silicon substrate. The wiring layer 112 is composed of, for example, five wiring layers 121 to 125.

A photodiode 91, an FD 93, a power supply 97, and the like are formed on the semiconductor substrate 111. A transfer transistor 92 is formed between the photodiode 91 and the FD 93 on the semiconductor substrate 111, and an amplification transistor 95 is connected to the power supply 97. Further, a vertical signal line 53 is formed on the wiring layer 124.

The amplification transistor 95 is connected to the FD wiring 132 formed in the wiring layer 122 via the via 131 formed in the wiring layer 121. On the other hand, the FD 93 is connected to the FD wiring 132 via the via 131 formed in the wiring layer 121. As a result, the amplification transistor 95 and the FD 93 are connected to the via 131 via the FD wiring 132.

Further, the power supply 97 is connected to the wiring 133 formed in the wiring layer 122 via the via 131 formed in the wiring layer 121. The transfer transistor 92 is connected to the TRG wiring 134 formed in the wiring layer 122 via the via 131 formed in the wiring layer 121.

A wiring interlayer film 130 such as a SiO film is formed in a region of the wiring layers 121 to 125 where wiring or the like is not formed. However, in the example of FIG. 3, the FD wiring includes the entire area between the FD wiring 132 and the wiring 133 and the TRG wiring 134 adjacent to the FD wiring 132 formed on the wiring layer 122 other than the FD wiring 132. The area around 132 is the hollow area 135. The FD wiring 132 and the hollow region 135 are in contact with each other.

When the wiring interlayer film 130 is a SiO film, the permittivity of the hollow region (Air) 135 is 1/4 times the dielectric constant of the wiring interlayer film 130. Therefore, by forming the hollow region 135, the capacity of the FD wiring 132 is reduced to about 1/4 of the case where the hollow region 135 is not formed.

Further, since the wiring interlayer film 130 is formed in the region other than the hollow region 135 of the wiring layer 122, the mechanical strength is stronger than the case where the wiring interlayer film 130 is not formed in the entire wiring layer 122.

(Second structural example of CMOS image sensor)
FIG. 4 is a diagram showing a second structural example of the CMOS image sensor 50.

Of the configurations shown in FIG. 4, the same configurations as those in FIG. 3 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The structure of the CMOS image sensor 50 of FIG. 4 is different from the structure of FIG. 3 in that hollow regions 201 to 206 are formed instead of the hollow region 135.

In the example of FIG. 4, the area around the FD wiring 132 including the entire area between the FD wiring 132 and the wiring 133 and the TRG wiring 134 is not in contact with the FD wiring 132, the wiring 133, and the TRG wiring 134. , Hollow regions 201 to 206 are formed.

(Third structural example of CMOS image sensor)
FIG. 5 is a diagram showing a third structural example of the CMOS image sensor 50.

Of the configurations shown in FIG. 5, the same configurations as those in FIG. 3 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The structure of the CMOS image sensor 50 of FIG. 5 is different from the structure of FIG. 3 in that a hollow region 221 is formed instead of the hollow region 135.

In the example of FIG. 5, the area around the FD wiring 132 is hollow, including only the area between the FD wiring 132 and the wiring 133, not the entire area between the FD wiring 132 and the wiring 133 and the TRG wiring 134. Region 221.

That is, since the FD wiring 132 handles analog signals, it has weaker resistance to noise than wirings such as vertical signal lines 53 that handle digital signals. Therefore, it is desirable to reduce the capacitance between the noise source wiring 133 and the FD wiring 132 connected to the power supply 97. However, it may be better to maintain the capacitance between the TRG wiring 134 and the FD wiring 132.

Therefore, in the example of FIG. 5, the periphery of the FD wiring 132 including only the region between the FD wiring 132 and the wiring 133 in the region between the FD wiring 132 and the adjacent wiring 133 and the TRG wiring 134. Region is made into a hollow region 221. That is, in the region between the FD wiring 132 and the adjacent wiring 133 and the TRG wiring 134, the region other than the region between the FD wiring 132 and the TRG wiring 134 is set as the hollow region 221.

As a result, noise propagation via the capacitance between the FD wiring 132 and the noise source wiring 133 can be suppressed. In addition, the capacitance between the TRG wiring 134 and the FD wiring 132 can be maintained.

The hollow region 221 may or may not be in contact with the FD wiring 132 and the wiring 133 as shown in FIG.

(Fourth structural example of CMOS image sensor)
FIG. 6 is a diagram showing a fourth structural example of the CMOS image sensor 50.

Of the configurations shown in FIG. 6, the same configurations as those in FIG. 3 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The structure of the CMOS image sensor 50 of FIG. 6 is different from the structure of FIG. 3 in that a hollow region 241 is formed in addition to the hollow region 135.

In the example of FIG. 6, the entire region around the vertical signal line 53 is the hollow region 241.

That is, when the number of vertical signal lines 53 is large, high-speed driving can be performed, but the wiring density increases and the capacity of the vertical signal lines 53 increases. As a result, the responsiveness deteriorates, the variation of the pixel signal increases, and the image quality of the captured image deteriorates. Therefore, in the example of FIG. 6, the entire region around the vertical signal line 53 is made into a hollow region 241. Thereby, the capacitance of the vertical signal line 53 can be reduced. As a result, it is possible to suppress variations in pixel signals during high-speed driving and improve the image quality of captured images.

In the example of FIG. 6, the entire region around the vertical signal line 53 is the hollow region 241. However, even if only a part of the region around the vertical signal line 53 is the hollow region 241. Good. Further, instead of the hollow region 135, the hollow regions 201 to 206 or the hollow region 221 may be formed.

Further, the hollow region 241 may or may not be in contact with the wiring adjacent to the vertical signal line 53 as shown in FIG.

As described above, in the CMOS image sensor 50, at least a part of the region between the FD wiring 132 and each of the wiring 133 and the TRG wiring 134 is the hollow region 135 (201 to 206,221). Therefore, it is possible to reduce the capacity of the FD wiring 132 and improve the charge-voltage conversion efficiency without having to change the wiring layout.

Further, since it is not necessary to change the wiring layout, any method can be adopted as the pixel sharing method of the CMOS image sensor 50.

A low dielectric constant film may be formed instead of the wiring interlayer film 130 in the regions other than the wiring and the hollow region 135 (201 to 206,221,241) of the wiring layers 121 to 125.

<Second Embodiment>
(Example of pixel circuit configuration of the second embodiment of the CMOS image sensor)
The configuration of the second embodiment of the CMOS image sensor as a solid-state image sensor to which the present disclosure is applied is the CMOS of FIG. 1 except for the circuit configuration of the pixels two-dimensionally arranged in the pixel region 51 and the operation of the sweep-out scanning system. It is the same as the image sensor. Therefore, in the following, only the circuit configuration of the pixels and the operation of the sweep-out scanning system will be described, and the components other than the pixels of the CMOS image sensor will be described using the reference numerals of FIG.

FIG. 7 is a diagram showing an example of a pixel circuit configuration of a second embodiment of a CMOS image sensor to which the present disclosure is applied.

Of the configurations shown in FIG. 7, the same configurations as those in FIG. 2 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The circuit configuration of the pixel 300 in FIG. 7 is such that the FD 301 and 302 are provided instead of the FD 93 and the reset transistors 303 and 304 are provided instead of the reset transistor 94. Is different. The pixel 300 can switch the imaging mode to the high charge voltage conversion efficiency mode or the low charge voltage conversion efficiency mode by switching the reset transistor 304 on / off.

Specifically, in the pixel 300, the gate terminal of the amplification transistor 95 is connected to the FD 301. Further, a reset transistor 303 and a reset transistor 304 connected in series via the FD 302 are connected between the power supply 97 and the FD 301.

Different lines of the pixel drive lines 52 in the corresponding rows are connected to the gate terminals of the reset transistor 303 and the reset transistor 304, and different reset signals are supplied through the lines. The reset signal supplied to the reset transistor 303 is turned on by the sweep scanning system of the vertical drive unit 54 to sweep out unnecessary charges from the photodiode 91.

The reset signal supplied to the reset transistor 304 is always turned on by the sweep scan system when the imaging mode is the high charge voltage conversion efficiency mode. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of the FD 301 becomes the potential VDD of the power supply 97, and the capacity of the FD of the pixel 300 is only the capacity of the FD 301. Therefore, the charge-voltage conversion efficiency is high.

On the other hand, when the imaging mode is the low charge voltage conversion efficiency mode, the reset signal supplied to the reset transistor 304 is always turned off by the sweep scanning system. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of the FD 302 becomes the potential VDD of the power supply 97, and the capacity of the FD of the pixel 300 becomes the sum of the capacities of the FD 301 and the FD 302. Therefore, the charge-voltage conversion efficiency becomes low.

In the pixel 300 configured as described above, the ratio of the charge-voltage conversion efficiency between the high charge-voltage conversion efficiency mode and the low-charge-voltage conversion efficiency mode (hereinafter referred to as the mode ratio) is the capacity of the FD 301 and the capacity of the FD 301 and FD 302. It is determined by the ratio with the sum of. Further, the capacities of the FD 301 and the FD 302 contribute to the capacities of the FD wiring (not shown) connected to the FD 301 and the capacities of the FD wiring (not shown) connected to the FD 302, respectively.

Therefore, in the pixel 300, a hollow region 135 (201 to 20) is formed around the FD wiring connected to, for example, the FD 301 of the two FD wirings connected to the FD 301 and the FD 302 so that the mode ratio becomes a desired ratio. A hollow region similar to 206,221) is formed.

That is, as described above, by forming the hollow region around the FD wiring, the capacity of the FD wiring can be reduced as compared with the case where the hollow region is not formed. Therefore, the hollow region is formed so that the capacity of the FD wiring connected to the FD 301 is the capacity of the FD wiring corresponding to the capacity of the FD 301 determined based on the capacity of the FD 302 and the desired mode ratio.

The hollow region may be formed only around the FD wiring connected to the FD 302, or may be formed around the two FD wirings connected to each of the FD 301 and the FD 302. Further, the FD 301 and the FD 302 may be shared among a plurality of pixels 300.

As described above, in the second embodiment of the CMOS image sensor, two FD301 and FD302 are formed, and FD wiring is connected to each of the FD301 and FD302. Then, a hollow region is formed around at least one of the FD wirings. As a result, the capacity of the FD wiring in which the hollow region is formed is reduced as compared with the case where the hollow region is not formed, and as a result, the mode ratio can be set to a desired ratio.

On the other hand, when a hollow region is not formed around the FD wiring connected to each of the FD 301 and FD 302, the mode ratio needs to be adjusted by the wiring layout. However, when the pixel 300 is small, the degree of freedom of the wiring layout is low, and the wiring layout is limited based on the sharing method of the pixel 300, so that the adjustment by the wiring layout is difficult.

<Third Embodiment>
(Example of arrangement of each part of CMOS image sensor)
Since the configuration of the third embodiment of the CMOS image sensor as the solid-state image sensor to which the present disclosure is applied is the same as the configuration of the CMOS image sensor 50 of FIG. 1, the description thereof will be omitted. Further, in the following figures, the same reference numerals as those of the CMOS image sensor 50 are given, and the description thereof will be omitted as appropriate.

FIG. 8 is a diagram showing an arrangement example of each part of the third embodiment of the CMOS image sensor.

In the CMOS image sensor 320 of FIG. 8, the pixel region 51 is arranged on one of the two semiconductor substrates 321 and the semiconductor substrate 322 to be laminated, and the control circuit 331 and the logic circuit 332 are arranged on the other semiconductor substrate 322. Is placed. One or more wiring layers are laminated on the semiconductor substrate 321 and the semiconductor substrate 322, and the semiconductor substrate 321 and the semiconductor substrate 322 are laminated so that the wiring layers are joined to each other.

The control circuit 331 is, for example, a circuit including a vertical drive unit 54, a column processing unit 55, a horizontal drive unit 56, and a system control unit 57. The logic circuit 332 is, for example, a circuit including a signal processing unit 58 and a memory unit 59.

Here, the number of layers of the semiconductor substrate of the CMOS image sensor 320 is set to be two, but it may be one layer or three or more layers. Further, the control circuit 331 may be formed on the same semiconductor substrate 321 as the pixel region 51.

(First structural example of semiconductor substrate 321)
9 is a plan view of a first structural example of the pixel region 51 of the semiconductor substrate 321 of FIG. 8 as viewed from the wiring layer side, and FIG. 10 is a sectional view taken along the line AA and FIG. 9B. It is a sectional view. For convenience of explanation, FIG. 9 shows only the semiconductor substrate 321 and the bottom one wiring layer, and FIG. 10 shows only the semiconductor substrate 321 and the bottom two wiring layers.

As shown in FIGS. 9 and 10, in the CMOS image sensor 320, the FD 93 is shared between two horizontally adjacent pixels 90. As shown in FIG. 10, FD wiring 361 connecting the FD 93, the source of the reset transistor 94, and the gate of the amplification transistor 95 is formed in the wiring layer 351 at the bottom of the pixel region 51.

As shown in FIG. 10, the FD wiring 361 is connected to the FD 93 via the via 361A, is connected to the source of the reset transistor 94 formed on the semiconductor substrate 321 via the via 361B, and is connected to the gate and via of the amplification transistor 95. It is connected via 361C.

Further, as shown in FIG. 9, TRG wiring 362, which is one wiring constituting the pixel drive line 52, is connected to the gate of the transfer transistor 92. Further, as shown in FIG. 10, various wirings 363 are formed on the wiring layer 352 above the wiring layer 351.

As shown in FIGS. 9 and 10, in the wiring layer 351, there are a plurality of (4 in the example of FIG. 10) hollow regions between the FD wiring 361 and other wiring (not shown) in the wiring layer 351. (Air Gap) 364A is formed. Further, a plurality of (6 in the example of FIG. 10) hollow regions 364B are also formed between the FD wiring 361 and the semiconductor substrate 321 having different potentials. Further, a plurality of hollow regions 364C are also formed in the region above the FD wiring 361 of the wiring layer 352.

As described above, the hollow regions 364A to 364C are formed between the FD wiring 361 and other wiring or other electrodes such as the semiconductor substrate 321 to form the hollow region 364A to 364C between the FD wiring 361 and the other wiring or electrode. The dielectric constant of the FD wiring 361 is reduced, and the capacitance of the FD wiring 361 is reduced. As a result, the charge-voltage conversion efficiency is improved.

Further, the hollow region formed between the FD wiring 361 and the other wiring is not one hollow region but is composed of a plurality of hollow regions 364A. Therefore, even when the distance between the FD wiring 361 and the other wiring is increased in order to reduce the capacity of the FD wiring 361, the size of one hollow region can be reduced, so that the hollow region can be reduced. Can be easily formed.

In the wiring layer 351 and the wiring layer 352, wiring such as FD wiring 361, TRG wiring 362, and wiring 363, hollow regions 364A to 364C, and regions where transistors such as transfer transistors 92 are not formed are covered with an insulating film 353 such as a SiO film. Wiring interlayer film) is formed. In the third embodiment, the material of the insulating film 353 is SiO2, but of course, the material is not limited to this.

As described above, the hollow regions 364A to 364C are the insulating film 353, that is, the hollow regions 364A to 364C are supported by the insulating film 353, so that the capacity of the FD wiring 361 is increased as compared with the case where the hollow regions 364A to 364C are supported by the conductor. It can be reduced.

(Explanation of Manufacturing Method of First Structural Example of Semiconductor Substrate 321)
11 to 14 are views for explaining a method of manufacturing a semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 of FIGS. 9 and 10 are laminated.

First, in the first step of FIG. 11, transistors and the like constituting the pixel 90 such as the photodiode 91, FD93, transfer transistor 92, reset transistor 94, and amplification transistor 95 are formed on the semiconductor substrate 321. Then, the insulating film 353 is formed on the semiconductor substrate 321.

In the second step of FIG. 11, a photoresist pattern is formed by applying the photoresist 381 to a region on the insulating film 353 other than the region corresponding to the hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Will be done. Then, the insulating film 353 is etched using the photoresist pattern. As a result, the insulating film 353 in the region where the photoresist 381 is not formed, that is, the region corresponding to the hollow region 364B is removed. The size of the hollow region 364B can be controlled by changing the photoresist pattern.

In the third step of FIG. 12, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method having poor coverage. As a result, a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321 is formed. In the fourth step of FIG. 12, the FD wiring 361 and vias 361A to 361C are formed in the insulating film 353 so that the FD 93 is connected to the source of the reset transistor 94 and the gate of the amplification transistor 95 at the damascene.

In the fifth step of FIG. 13, the photoresist 381 is applied to a region on the insulating film 353 other than the region corresponding to the hollow region 364A between the FD wiring 361 and the other wiring not shown in the same wiring layer 351. By doing so, a photoresist pattern is formed. Then, the insulating film 353 is etched using the photoresist pattern. As a result, the insulating film 353 in the region where the photoresist 381 is not formed, that is, the region corresponding to the hollow region 364A is removed.

In the sixth step of FIG. 13, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method having poor coverage. As a result, the hollow region 364A is formed. In the seventh step of FIG. 14, the wiring 363 of the wiring layer 352 is formed by damascene.

In the eighth step of FIG. 14, first, the hollow above the FD wiring 361 is the same as the second step of FIG. 11 and the third step of FIG. 12 and the fifth step and the sixth step of FIG. Region 364C is formed.

Specifically, the photoresist pattern is formed by applying the photoresist 381 to a region other than the region corresponding to the hollow region 364C on the FD wiring 361 on the insulating film 353. Then, the insulating film 353 is etched using the photoresist pattern, whereby the insulating film 353 in the region corresponding to the hollow region 364C is removed. After that, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method having poor coverage.

The thickness of the insulating film 353 etched in the second step of FIG. 11, the fifth step of FIG. 13, and the eighth step of FIG. 14 (the length in the direction perpendicular to the semiconductor substrate 321), that is, hollow. The thickness of the regions 364A to 364C is, for example, thinner than a few um.

As described above, since the insulating film 353 on the hollow regions 364A to 364C is formed by a film forming method having poor coverage, the insulating film 353 is formed on the hollow regions 364A to 364C while maintaining the cavities in the hollow regions 364A to 364C. The insulating film 353 can be formed. The film quality of the insulating film 353 below the hollow regions 364A to 364C may be the same as or different from the film quality of the insulating film 353 above the hollow regions 364A to 364C.

(Second Structural Example of Semiconductor Substrate 321)
FIG. 15 is a cross-sectional view taken along the line AA'of FIG. 9 of a second structural example of the pixel region 51 of the semiconductor substrate 321 of FIG. For convenience of explanation, FIG. 15 shows only the semiconductor substrate 321 and the bottom two wiring layers.

Of the configurations shown in FIG. 15, the same configurations as those in FIG. 10 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The configuration of the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 of FIG. 15 are laminated is that the stopper film 401 is formed so as to be in contact with the FD wiring 361 and the bottom surface of the hollow region 364A. Different from.

The stopper film 401 is a film for stopping the etching of the insulating film 353 when the FD wiring 361 is formed by the damascene, and is a SiOC film or the like.

(Explanation of Manufacturing Method of Second Structural Example of Semiconductor Substrate 321)
16 to 19 are views for explaining a method of manufacturing a semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 of FIG. 15 are laminated.

First, the first to third steps of FIGS. 11 and 12 are performed to form a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in the first to sixth steps of FIGS. 16 and 18, the FD wiring 361 and the vias 361A to 361C are formed by the damascene.

That is, in the first step of FIG. 16, the insulating film 353 is formed on the semiconductor substrate 321 on which the hollow region 364B is formed and flattened.

In the second step of FIG. 16, the stopper film 401 is formed on the insulating film 353. In the third step of FIG. 17, an insulating film 353 having a predetermined thickness is formed (stacked) on the stopper film 401.

In the fourth step of FIG. 17, the region corresponding to the vias 361A to 361C of the insulating film 353 below the stopper film 401 is etched, and the region corresponding to the FD wiring 361 of the insulating film 353 above the stopper film 401 is etched. Will be done. Etching of the insulating film 353 above the stopper film 401 is stopped by the stopper film 401. That is, the bottom surface of the etching region of the insulating film 353 above the stopper film 401 is in contact with the upper surface of the stopper film 401.

In the fifth step of FIG. 18, copper (Cu) 402 is formed on the uppermost insulating film 353. In the sixth step of FIG. 18, unnecessary copper 402 above the insulating film 353 is removed, whereby FD wiring 361 and vias 361A to 361C are formed.

Next, in the seventh step of FIG. 19, the region other than the region corresponding to the hollow region 364A between the FD wiring 361 and another wiring not shown in the same wiring layer 351 on the insulating film 353 is photo-photographed. By applying the resist 381, a photoresist pattern is formed. Then, using the photoresist pattern, the insulating film 353 is etched so that the etching is stopped at the stopper film 401. As a result, the insulating film 353 in the region where the photoresist 381 is not formed, that is, the region corresponding to the hollow region 364A is removed.

After that, the sixth to eighth steps of FIGS. 13 and 14 are performed to form the hollow region 364A and the hollow region 364C.

As described above, the bottom surface of all the hollow regions 364A is in contact with the upper surface of the stopper film 401. That is, the positions of the bottom surfaces of all the hollow regions 364A in the thickness direction are the same. Therefore, the variation in the depth of the hollow region 364A (the length in the direction perpendicular to the semiconductor substrate 321) is reduced, and thus the variation in the capacity of the FD wiring 361 is reduced.

In the seventh step of FIG. 19, as shown in FIG. 20, after the etching of the insulating film 353 is stopped by the stopper film 401, further etching may be performed.

(Third structural example of semiconductor substrate 321)
FIG. 21 is a cross-sectional view taken along the line AA'of FIG. 9 of a third structural example of the pixel region 51 of the semiconductor substrate 321 of FIG. For convenience of explanation, FIG. 21 shows only the semiconductor substrate 321 and the bottom two wiring layers.

Of the configurations shown in FIG. 21, the same configurations as those in FIG. 10 are designated by the same reference numerals. Duplicate explanations will be omitted as appropriate.

The configuration of the semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 of FIG. 21 are laminated is such that the lower part of the four continuous hollow regions 364A is connected and the insulation around the upper part of the hollow region 364A. The configuration differs from that of FIG. 10 in that the film is an insulating film 421 made of a material different from that of the insulating film 353.

The material of the insulating film 421 is, for example, SiN.

(Explanation of Manufacturing Method of Third Structural Example of Semiconductor Substrate 321)
22 and 23 are views for explaining a method of manufacturing a semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 of FIG. 21 are laminated.

First, the first to third steps of FIGS. 11 and 12 are performed to form a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in the first step of FIG. 22, the insulating film 421 is formed on the insulating film 353. Then, in the insulating film 353 and the insulating film 421, the FD wiring 361 and the vias 361A to 361C are formed so as to be connected to the FD 93 by the damascene.

Next, in the second step of FIG. 22, a photoresist pattern is formed by applying the photoresist 381 to a region other than the region corresponding to the hollow region 364A on the insulating film 421.

Then, the insulating film 353 and the insulating film 421 are etched using the photoresist pattern. As a result, the insulating film 353 and the insulating film 421 in the region where the photoresist 381 is not formed, that is, the region corresponding to the hollow region 364A is removed.

In the third step of FIG. 23, isotropic etching of the insulating film 353 and the insulating film 421 is performed under the condition that the etching rate of the insulating film 353 is higher than the etching rate of the insulating film 421. As a result, only the insulating film 353 is etched, and the lower portions of the four hollow regions 364A are connected.

In the fourth step of FIG. 23, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method having poor coverage. At this time, the size of the lower part of the hollow region 364A is large, but the size of the upper part is small, so that the material of the insulating film 353 is closed before reaching the lower part. Therefore, the cavity of the hollow region 364A is maintained. After that, the seventh and eighth steps of FIG. 14 are performed to form the hollow region 364C.

As shown in FIG. 24, similarly to the hollow region 364A, an insulating film 422 may be formed around the upper portion of the hollow region 364B, and the lower portion of the hollow region 364B may be connected. Further, although not shown, the lower portion of the hollow region 364C may be connected. Further, the lower portion of each of the hollow regions 364A to 364C may be larger than the size of the upper portion, and the lower portions of the hollow regions 364A to 364C may not be connected to each other.

(First manufacturing method of CMOS image sensor)
25 to 27 show a first manufacturing method of the CMOS image sensor 320 of FIG. 8 manufactured by joining the semiconductor substrate 321 manufactured by the manufacturing methods of FIGS. 11 to 14 and the semiconductor substrate 322. It is a figure.

After the semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 are laminated is manufactured by the manufacturing method of FIGS. 11 to 14, the wiring layer 431 is further laminated. Then, in the first step of FIG. 25, the photoresist 381 is applied to the region on the insulating film 353 of the wiring layer 352 around the region where the TSV (through-silicon via) 452 other than the pixel region 51 is formed. As a result, a photoresist pattern is formed. Then, the insulating film 353 is etched using the photoresist pattern. As a result, the insulating film 353 in the region where the photoresist 381 is not formed, that is, the region around the region where the TSV452 is formed is removed.

In the second step of FIG. 25, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method having poor coverage. As a result, the hollow region 432 is formed in the region around the region where the TSV452 (connection portion) is formed.

In the third step of FIG. 26, the semiconductor substrate 321 and the semiconductor substrate 322 are joined.

Specifically, in the example of FIG. 26, four wiring layers 441 to 444 on which various wirings 440 are formed are laminated on the semiconductor substrate 322, and wirings 440 and the like of the wiring layers 441 to 444 are not formed. An insulating film 445 is formed in the region.

The wiring 440 of the uppermost wiring layer 444 is formed of, for example, aluminum (Al), and the wiring 440 of the wiring layers 441 to 443 other than the uppermost layer is formed of, for example, copper (Cu). The semiconductor substrate 321 and the semiconductor substrate 322 are joined so that the uppermost wiring layer 431 of the semiconductor substrate 321 and the uppermost wiring layer 444 of the semiconductor substrate 322 are joined.

After joining the semiconductor substrate 321 and the semiconductor substrate 322, an insulating film 451 is formed on the surface of the semiconductor substrate 321 facing the surface on which the wiring layer 351 is laminated. Further, a color filter, an on-chip lens, or the like (not shown) is formed in a region corresponding to the pixel region 51 on the surface of the semiconductor substrate 321 facing the surface on which the wiring layer 351 is laminated. Further, the semiconductor substrate 321 and the semiconductor substrate 322 after bonding are thinned, whereby the film thickness of the CMOS image sensor 320 is made to a desired film thickness.

Next, in the fourth step of FIG. 27, the region of the insulating film 451, the semiconductor substrate 321 and the insulating film 353, and the insulating film 445 in which the TSV452 is formed is etched to form the TSV452. The TSV 452 is connected to the wiring 440 of the wiring layer 444 and the wiring 363 of the wiring layer 351 to electrically connect the semiconductor substrate 321 and the semiconductor substrate 322.

(Second manufacturing method of CMOS image sensor)
28 to 31 describe a second manufacturing method of the CMOS image sensor 320 of FIG. 8 manufactured by joining the semiconductor substrate 321 manufactured by the manufacturing methods of FIGS. 11 to 14 and the semiconductor substrate 322. It is a figure.

After the semiconductor substrate 321 in which the wiring layer 351 and the wiring layer 352 are laminated is manufactured by the manufacturing method of FIGS. 11 to 14, the wiring layer 431 is further laminated. Then, in the first step of FIG. 28, the semiconductor substrate 321 and the semiconductor substrate 322 are joined so that the uppermost wiring layer 352 of the semiconductor substrate 321 and the uppermost wiring layer 442 of the semiconductor substrate 322 are joined. ..

Further, after joining the semiconductor substrate 321 and the semiconductor substrate 322, an insulating film 451 is formed on the surface of the semiconductor substrate 321 facing the surface on which the wiring layer 351 is laminated. Further, a color filter, an on-chip lens, or the like (not shown) is formed in a region corresponding to the pixel region 51 on the surface of the semiconductor substrate 321 facing the surface on which the wiring layer 351 is laminated. Further, the semiconductor substrate 321 and the semiconductor substrate 322 after bonding are thinned, whereby the film thickness of the CMOS image sensor 320 is made to a desired film thickness.

Next, in the second step of FIG. 29, the photoresist pattern is formed by applying the photoresist 381 to the region on the insulating film 451 around the region where the TSV 452 is formed other than the pixel region 51. .. Then, the semiconductor substrate 321 and the insulating film 451 and the insulating film 353 are etched using the photoresist pattern. As a result, the semiconductor substrate 321 and the insulating film 451 and the insulating film 353 are removed from the region where the photoresist 381 is not formed, that is, the region around the region where the TSV 452 is formed.

In the third step of FIG. 30, the photoresist pattern is peeled off, and the insulating film 451 is formed by a film forming method having poor coverage. As a result, a hollow region 432 penetrating the semiconductor substrate 321 is formed in a region around the region where the TSV452 is formed.

In the fourth step of FIG. 31, the region of the insulating film 451, the semiconductor substrate 321 and the insulating film 353, and the insulating film 445 in which the TSV452 is formed is etched to form the TSV452.

As shown in FIG. 32, when the insulating film 451 is formed in the third step, the insulating film 451 may be embedded in the hollow region 432 in the semiconductor substrate 321. Further, the TSV 452 may connect the wiring 440 of the wiring layer 444 and the wiring 363 of the wiring layer 351 by one via, or may be connected by two vias.

As described above, by forming the hollow region 432 around the TSV452, the capacitance between the TSV452 and the potential portion (for example, GND) of the semiconductor substrate 321 can be reduced.

In the third embodiment, the number of the hollow regions 364A to 364C and the hollow regions 432 can be any number as long as it is 1 or more. Further, the shapes of the hollow regions 364A to 364C and the hollow regions 432 may be any shape as long as the insulating film is not formed by a film forming method having poor coverage.

<Fourth Embodiment>
(Explanation of arrangement of hollow area in pixel area)
The configuration and structure of the fourth embodiment of the CMOS image sensor as a solid-state image sensor to which the present disclosure is applied are a point in which the FD93 is shared between 2 (horizontal) × 2 (vertical) pixels 90, and a hollow region. It is the same as the configuration and structure of the CMOS image sensor 320 except for the arrangement and shape of the 364A to 364C and the hollow region 432.

Therefore, in the following, only the arrangement and shape of the hollow regions 364A to 364C and the hollow regions 432 will be described. Further, in the following figures, the same ones as the CMOS image sensor 320 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

FIG. 33 illustrates the arrangement of the hollow region in the pixel region 51 according to the fourth embodiment of the CMOS image sensor. The pixel region 51 of the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 and the wiring layer 431 are laminated. Is a plan view seen from the wiring layer 431 side.

FIG. 33A shows only the semiconductor substrate 321 and the wiring layer 351, and FIG. 33B shows only the semiconductor substrate 321 and the wiring layer 431.

As shown in FIG. 33A, in the fourth embodiment of the CMOS image sensor, in the wiring layer 351, a hollow region 472 is formed between the FD wiring 361 and other wiring in the same wiring layer 351 such as the wiring 471. It is formed. As a result, the dielectric constant between the FD wiring 361 in the wiring layer 351 and the other wiring is reduced, and the capacitance of the FD wiring 361 is reduced. As a result, the charge-voltage conversion efficiency is improved.

Further, as shown in FIG. 33B, in the wiring layer 431, a hollow region 474 is formed between the vertical signal line 53 and other wiring in the same wiring layer 431 such as the wiring 473. As a result, the dielectric constant between the vertical signal line 53 in the wiring layer 431 and the other wiring is reduced, and the capacitance of the vertical signal line 53 is reduced. As a result, it is possible to prevent a delay in reading the pixel signal.

In the example of FIG. 33A, two hollow regions 472 are formed between the FD wiring 361 and the other wiring, but the number of hollow regions 472 can be any number as long as it is 1 or more. .. Similarly, the number of hollow regions 474 formed between the vertical signal line 53 and other wiring can be any number as long as it is 1 or more.

Further, in the example of FIG. 33, the shapes of the hollow region 472 and the hollow region 474 are formed to be rectangular when viewed from above the wiring layer 431 (striped shape), but the hollow region 472 and the hollow region are formed. The shape of 474 can be any shape.

(Example of the shape of the hollow region in the pixel region)
FIG. 34 is a plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 351 is laminated, which shows another example of the shape of the hollow region 472, as viewed from the wiring layer 351 side.

The shape of the hollow region 472 may be, for example, a circular shape (hole shape) when viewed from above the wiring layer 351 as shown in FIG. 34A, or a mesh as shown in FIG. 34B. (Mesh shape) may be used.

Although not shown, the shape of the hollow region 474 can be the same as that of the hollow region 472.

(Example of the shape of the hollow region outside the pixel region)
FIG. 35 is a plan view of the CMOS image sensor as viewed from above the insulating film 451 showing an example of the shape of the hollow region 432 formed around the TSV 452 outside the pixel region 51 in the fourth embodiment of the CMOS image sensor. Is.

The shape of the hollow region 432 may be, for example, a ring-shaped rectangle when viewed from above the insulating film 451 as shown in FIG. 35A, or a ring-shaped circular shape as shown in FIG. 35B. It may have a shape that becomes. Further, as shown in FIG. 35C, the shape may be a line (stripe shape).

Further, the number of hollow regions 432 formed around the TSV 452 is two in the examples of FIGS. 35A and 35C and one in the example of FIG. 35B, but the number is not limited to these and can be any number. can do.

The shapes of the hollow region 432, the hollow region 472, and the hollow region 474 are not limited to the shapes of FIGS. 34 and 35 as long as the insulating film is not formed by a film forming method having poor coverage.

Further, also in the fourth embodiment, as in the third embodiment, hollow regions may be formed in the lower portion and the upper portion of the FD wiring 361.

Further, in the third embodiment, as in the fourth embodiment, a hollow region may be formed around the vertical signal line 53. Further, in the third and fourth embodiments, the region where the hollow region is formed may be around the wiring other than the FD wiring 361 and the vertical signal line 53 whose capacity is desired to be reduced.

Further, in the third and fourth embodiments, a hollow region may be formed in the semiconductor substrate 322.

<Fifth Embodiment>
(Structure example of one embodiment of the imaging device)
FIG. 36 is a block diagram showing a configuration example of an embodiment of an imaging device as an electronic device to which the present disclosure is applied.

The image pickup device 1000 of FIG. 36 is a video camera, a digital still camera, or the like. The image pickup device 1000 includes a lens group 1001, a solid-state image pickup element 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via the bus line 1009.

The lens group 1001 captures incident light (image light) from the subject and forms an image on the image pickup surface of the solid-state image pickup device 1002. The solid-state image sensor 1002 includes the CMOS image sensor described above. The solid-state image sensor 1002 converts the amount of incident light imaged on the imaging surface by the lens group 1001 into an electric signal in pixel units and supplies it to the DSP circuit 1003 as a pixel signal.

The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state image sensor 1002, supplies the image signal after the image processing to the frame memory 1004 in frame units, and temporarily stores the image signal.

The display unit 1005 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays an image based on a frame-based pixel signal temporarily stored in the frame memory 1004.

The recording unit 1006 is composed of a DVD (Digital Versatile Disk), a flash memory, or the like, and reads and records a frame-by-frame pixel signal temporarily stored in the frame memory 1004.

The operation unit 1007 issues operation commands for various functions of the image pickup apparatus 1000 under the operation of the user. The power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007 as appropriate.

The electronic device to which this technology is applied may be any device that uses a CMOS image sensor for the image capture unit (photoelectric conversion unit), and in addition to the image pickup device 1000, a portable terminal device having an image pickup function, and a CMOS image for the image reading unit. There are copiers that use sensors.

<Example of using CMOS image sensor>
FIG. 37 is a diagram showing a usage example using the above-mentioned CMOS image sensor.

The CMOS image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as described below.

・ Devices that take images for viewing, such as digital cameras and portable devices with camera functions. ・ For safe driving such as automatic stop and recognition of the driver's condition, in front of the car Devices used for traffic, such as in-vehicle sensors that photograph the rear, surroundings, and interior of vehicles, surveillance cameras that monitor traveling vehicles and roads, and distance measurement sensors that measure distance between vehicles, etc. Equipment used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate the equipment according to the gestures ・ Endoscopes, devices that perform angiography by receiving infrared light, etc. Equipment used for medical and healthcare ・ Equipment used for security such as surveillance cameras for crime prevention and cameras for person authentication ・ Skin measuring instruments for taking pictures of the skin and taking pictures of the scalp Equipment used for beauty such as microscopes ・ Equipment used for sports such as action cameras and wearable cameras for sports applications ・ Camera etc. for monitoring the condition of fields and crops , Equipment used for agriculture

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

Further, the embodiment of the present disclosure is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present disclosure.

The present disclosure can be applied not only to a CMOS image sensor but also to a CCD (Charge Coupled Device) image sensor.

The present disclosure may have the following structure.

(1)
A solid-state image sensor configured such that at least a part of a region between the FD wiring connected to the floating diffusion and the wiring other than the FD wiring is a hollow region.
(2)
The solid-state image sensor according to (1), wherein the FD wiring and the hollow region are configured to be in contact with each other.
(3)
The solid-state image sensor according to (1), wherein the FD wiring and the hollow region are not in contact with each other.
(4)
The hollow region is configured to be a region other than the region between the FD wiring and the TRG wiring connected to the transfer transistor in the region between the FD wiring and the wiring other than the FD wiring. The solid-state imaging device according to any one of (1) to (3) above.
(5)
The solid-state image sensor according to any one of (1) to (4) above, wherein at least a part around the vertical signal line is a hollow region.
(6)
The solid-state image sensor according to any one of (1) to (5) above, wherein the FD wiring is configured to be a part of a plurality of FD wirings connected to each of the plurality of floating diffusions.
(7)
The solid-state image sensor according to (1) above, wherein the number of hollow regions is configured to be plural.
(8)
Any of the above (1) or (7) configured such that an insulating film is formed in a region other than the hollow region among the regions between the FD wiring and the wiring other than the FD wiring. The solid-state image sensor according to the description.
(9)
The solid-state imaging device according to (8), wherein the material of the insulating film formed around the upper part of the hollow region and the material of the insulating film formed around the lower part of the hollow region are different from each other. ..
(10)
The solid-state image sensor according to (9) above, wherein the size of the lower part of the hollow region is configured to be larger than the size of the upper part.
(11)
The number of the hollow regions is plural,
The solid-state image sensor according to (10) above, wherein the lower portions of the plurality of hollow regions are configured to be connected.
(12)
The above (1) or (7) to (11), wherein at least a part of the region between the FD wiring and the semiconductor substrate connected to the FD wiring is a hollow region. Solid-state image sensor.
(13)
A first semiconductor substrate on which the FD wiring, wiring other than the FD wiring, and a wiring layer on which the hollow region is formed are laminated.
A second semiconductor substrate bonded to the first semiconductor substrate and
A connection portion for electrically connecting the first semiconductor substrate and the second semiconductor substrate is provided.
The solid-state image sensor according to any one of (1) or (7) to (11), wherein a hollow region is formed around the connection portion of the wiring layer.
(14)
The solid-state imaging device according to (13), wherein the hollow region formed around the connection portion of the wiring layer is configured to penetrate the first semiconductor substrate.
(15)
An electronic device including a solid-state image sensor in which at least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region.
(16)
The first semiconductor substrate and
A second semiconductor substrate bonded to the first semiconductor substrate and
A connection portion for electrically connecting the first semiconductor substrate and the second semiconductor substrate is provided.
A solid-state image sensor in which a hollow region is formed around the connection portion of the wiring layer laminated on the first semiconductor substrate.

50 CMOS image sensor, 53 vertical signal line, 92 transfer transistor, 93 FD, 132 FD wiring, 133 wiring, 134 TRG wiring, 135, 201 to 206, 221, 241 hollow area, 301, 302 FD, 320 CMOS image sensor, 321 322 semiconductor substrate, 351 352 wiring layer, 353 insulating film, 361 FD wiring, 364A to 364C hollow area, 421 insulating film, 432 hollow area, 452 TSV, 1000 image sensor, 1002 solid-state image sensor

Claims (14)

The first wiring that connects the floating diffusion and the FD wiring,
It has a second wiring that connects the amplification transistor and the FD wiring.
The region between the first wiring and the second wiring is configured to be a plurality of hollow regions.
The FD wiring is a solid-state image sensor arranged at a position perpendicular to the light incident surface and overlapping the floating diffusion and the amplification transistor. The solid-state image sensor according to claim 1, wherein the FD wiring and the hollow region are configured to be in contact with each other. The solid-state image sensor according to claim 1, wherein the FD wiring and the hollow region are not in contact with each other. The hollow region is configured to be a region other than the region between the FD wiring and the TRG wiring connected to the transfer transistor in the region between the FD wiring and the wiring other than the FD wiring. The solid-state imaging device according to claim 1. The solid-state imaging device according to claim 1, wherein at least a part around the vertical signal line is a hollow region. The solid-state image sensor according to claim 1, wherein the FD wiring is configured to be a part of a plurality of FD wirings connected to each of the plurality of floating diffusions. The solid-state image sensor according to claim 1, wherein an insulating film is formed in a region other than the hollow region in the region between the FD wiring and the wiring other than the FD wiring. The material of the insulating film formed around the upper part of the hollow region and the material of the insulating film formed around the lower part of the hollow region are configured to be different from each other.
The solid-state image sensor according to claim 7. The size of the lower part of the hollow region was configured to be larger than the size of the upper part.
The solid-state image sensor according to claim 8. The number of the hollow regions is plural,
The lower parts of the plurality of hollow regions were configured to be connected.
The solid-state image sensor according to claim 9. The solid-state image sensor according to claim 1, wherein at least a part of a region between the FD wiring and the semiconductor substrate connected to the FD wiring is a hollow region. A first semiconductor substrate on which the FD wiring, wiring other than the FD wiring, and a wiring layer on which the hollow region is formed are laminated.
A second semiconductor substrate bonded to the first semiconductor substrate and
A connection portion for electrically connecting the first semiconductor substrate and the second semiconductor substrate is provided.
The solid-state imaging device according to claim 1, wherein a hollow region is formed around the connection portion of the wiring layer. The hollow region formed around the connection portion of the wiring layer is configured to penetrate the first semiconductor substrate.
The solid-state image sensor according to claim 12. It has a first wiring that connects the floating diffusion and the FD wiring, and a second wiring that connects the amplification transistor and the FD wiring, and the region between the first wiring and the second wiring is The FD wiring is configured to be a plurality of hollow regions, and the FD wiring includes a solid-state imaging element arranged at a position overlapping each of the floating diffusion and the amplification transistor in a direction perpendicular to the light incident surface. Electronics.

Images