JP2012191116A - Photoelectric conversion device, imaging system, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric conversion device capable of suppressing increase in capacity of a floating diffusion region.SOLUTION: There is provided a photoelectric conversion device comprising: a semiconductor substrate on which a photoelectric conversion element, a floating diffusion region, a transfer transistor, and an amplification transistor are provided; and a plurality of wiring layers including a first wiring layer and a second wiring layer. In the photoelectric conversion device, a gate electrode of the transfer transistor and the second wiring layer are connected in a stacked contact structure.

Description

  The present invention relates to a photoelectric conversion device and a manufacturing process thereof.

  CMOS photoelectric conversion devices are widely used as image sensors for digital cameras or digital video cameras. In general, a CMOS photoelectric conversion device includes a pixel region in which pixels including a photodiode (PD) are arranged in a two-dimensional array, and a peripheral circuit region that is disposed so as to surround the pixel region.

  With the recent increase in the number of pixels in digital cameras and digital video cameras, CMOS type photoelectric conversion devices are desired to have many pixels mounted on the same area, and the size of one pixel of the CMOS type photoelectric conversion device is reduced. It continues to be.

  Patent Document 1 shows a structure of a general CMOS photoelectric conversion device. In order to make it possible to increase the number of pixels, a wiring layer that electrically connects each photodiode and transistor is formed into a multilayer wiring.

  In Patent Document 2, in order to ensure sensitivity to incident light even when the pixel is reduced, two types of interlayer insulating layers are provided in the wiring portion of the pixel of the CMOS photoelectric conversion device depending on the object to be electrically connected. A configuration in which a contact structure is provided is disclosed. One of the two contact structures electrically connects the semiconductor region and the gate electrode of the amplification MOS transistor without using a wiring layer. The other is a method in which a plurality of plugs are stacked and electrically connected to an active region or gate electrode and a wiring layer.

JP 2003-204055 A JP 2008-85304 A

  Here, the circuit scale of the whole photoelectric conversion apparatus is increasing from the request | requirement from high-speed and highly functional photoelectric conversion apparatus. Further miniaturization is necessary to meet this requirement.

  In Patent Document 1, a wiring layer of two layers, a first wiring layer and a second wiring layer, a first interlayer insulating film, and a second interlayer insulating film are provided from the side closer to the semiconductor substrate. When electrical connection is made through two or more interlayer insulating films that are connected from the second wiring layer to the semiconductor substrate, first, the second via is provided by the second via disposed in the second interlayer insulating film. The wiring layer and the first wiring layer are connected. Further, the first wiring layer and the semiconductor substrate are electrically connected by a first via disposed in the first interlayer insulating film. In such a configuration, the inventors have found the following problems. In the configuration as described above, it is necessary to secure an area for forming the first wiring layer for connecting the first via and the second via, and it is difficult to miniaturize the first wiring layer. . Further, for example, in the floating diffusion portion of a CMOS type photoelectric conversion device, when the area of the opposing metal wiring is large, the capacitance between the floating diffusion portion and the metal wiring is increased. The problem of an increase in capacitance becomes more influential because the distance between the floating diffusion portion and the metal wiring is reduced as the miniaturization progresses. Such an increase in the capacity of the floating diffusion portion may cause a decrease in signal charge generated by photoelectric conversion. Furthermore, in the case where regions having different numbers of wiring layers are included, there is a possibility that a step between the regions is generated.

  Accordingly, an object of the present invention is to provide a photoelectric conversion device capable of suppressing an increase in the capacity of the floating diffusion portion. Another object of the present invention is to reduce the level difference between regions when the regions have different numbers of wiring layers.

  The photoelectric conversion device of the present invention includes a photoelectric conversion element, a floating diffusion portion, a transfer transistor that transfers charges of the photoelectric conversion element to the floating diffusion portion, and an amplification transistor that outputs a signal based on the potential of the floating diffusion portion And a plurality of wiring layers including a first wiring layer and a second wiring layer disposed on the first wiring layer. A gate electrode of the transistor and the second wiring layer are connected by a stack contact structure.

  Another photoelectric conversion device of the present invention includes a pixel region in which a plurality of pixels each including a photoelectric conversion element and a transistor are arranged, a peripheral circuit region having a transistor and having more wiring layers than the pixel region, , A plurality of interlayer insulating films including a first interlayer insulating film and a second interlayer insulating film disposed on the first interlayer insulating film, and a first wiring layer And a wiring portion disposed on the semiconductor substrate, the wiring portion including a plurality of wiring layers including a second wiring layer disposed on the first wiring layer. The portion includes the first wiring layer and a plug disposed in the first interlayer insulating film connected to the first wiring layer in the peripheral circuit region, and the second wiring layer and the first wiring layer And a plug disposed in the first interlayer insulating film connected to the second wiring layer and the second interlayer insulation. And a wiring layer disposed closest to the semiconductor substrate is the first wiring layer in the peripheral circuit region, and the first wiring layer in the pixel region. 2 wiring layers.

  The method for manufacturing a photoelectric conversion device according to the present invention includes a pixel region in which a plurality of pixels each including a photoelectric conversion element and a transistor are arranged, and a peripheral circuit region having a transistor and having more wiring layers than the pixel region. And a wiring portion having a plurality of interlayer insulating films and a plurality of wiring layers disposed on the semiconductor substrate. Forming a first interlayer insulating film on the semiconductor substrate; forming a plurality of plugs in the first interlayer insulating film; and a plurality of plugs formed in the first interlayer insulating film. After the step of forming a first wiring layer connected to the portion on the first interlayer insulating film in the peripheral circuit region and the step of forming the first wiring layer, a second interlayer insulating film is formed. Forming a part of the second interlayer insulating film; A hole exposing a part of the plurality of plugs formed in the first interlayer insulating film in the pixel region and a hole exposing a part of the first wiring layer in the peripheral circuit region; A step of forming the second interlayer insulating film; a step of forming a plug in the second interlayer insulating film by burying a conductor in a hole formed in the second interlayer insulating film; Forming a second wiring layer on the second interlayer insulating film after the step of forming the plug in the interlayer insulating film.

  With the photoelectric conversion device of the present invention, it is possible to suppress an increase in the capacity of the floating diffusion portion.

Sectional schematic diagram of the photoelectric conversion device of the first embodiment Schematic cross-sectional view of a photoelectric conversion device for explaining the first embodiment Sectional schematic diagram which shows the manufacturing process of the photoelectric conversion apparatus of 1st Embodiment. Sectional schematic diagram of the photoelectric conversion device of the second embodiment Circuit diagram and plan view of pixel of photoelectric conversion device Plane schematic diagram of photoelectric conversion device Sectional schematic diagram of the photoelectric conversion device of the third embodiment Block diagram for explaining an imaging system Another schematic plan view of a pixel of a photoelectric conversion device Sectional schematic diagram of the photoelectric conversion device of the fourth embodiment Sectional schematic diagram which shows the manufacturing process of the photoelectric conversion apparatus of 4th Embodiment. Sectional schematic diagram of the photoelectric conversion device of the fifth embodiment Photoelectric conversion device cross-sectional schematic diagram of the sixth embodiment

  The photoelectric conversion device of the present invention includes a semiconductor substrate on which a photoelectric conversion element and a transistor are arranged, a plurality of wiring layers including a first wiring layer and a second wiring layer. A connection between the semiconductor substrate and one of the plurality of wiring layers and between the gate electrode of the transistor and one of the plurality of wiring layers has a stack contact structure. By having such a structure, it is possible to suppress an increase in the capacity of the floating diffusion portion.

  In addition, the photoelectric conversion device of the present invention includes a pixel region and a peripheral circuit region on a semiconductor substrate, and a wiring portion disposed on the semiconductor substrate. The wiring portion includes a first interlayer insulating film, a first wiring layer, a second interlayer insulating film, and a second wiring layer arranged in this order from the semiconductor substrate side. Further, the wiring portion includes a plug disposed in the first interlayer insulating film for connecting the peripheral circuit region to the first wiring layer, and a second wiring layer for connecting to the second wiring layer in the pixel region. A plug disposed on the first interlayer insulating film and a plug disposed on the second interlayer insulating film; In the photoelectric conversion device of the present invention, the wiring layer arranged closest to the semiconductor substrate is the first wiring layer in the peripheral circuit region and the second wiring layer in the pixel region. By having such a structure, it is possible to suppress the step between the pixel region and the peripheral circuit region and increase the number of wiring layers in the peripheral circuit region while suppressing an increase in capacitance of the floating diffusion portion. Become.

  The photoelectric conversion device of the present invention will be described. FIG. 6 is a schematic plan view of the photoelectric conversion device of each embodiment. In FIG. 6, reference numeral 601 denotes a pixel area, and 602 denotes a peripheral circuit area. The pixel region 601 includes an effective pixel region in which pixels 611 including photoelectric conversion elements for obtaining an imaging signal are arranged in a two-dimensional array. In some embodiments, the peripheral circuit region 602 is a region other than the pixel region 601 and has more wiring layers than the pixel region 601. In FIG. 6, a peripheral circuit area 602 includes a vertical scanning circuit 612 for reading a signal from the pixel area 601, a horizontal scanning circuit 613 for processing and outputting the read signal, and the read signal. A reading circuit 614 or the like including a circuit to be processed can be provided. The readout circuit 614 is an arbitrary circuit such as an amplifier circuit, a correlated double sampling circuit, or an AD conversion circuit. The pixel region 601 and the peripheral circuit region 602 are integrated on the same semiconductor substrate. In FIG. 6, the photoelectric conversion device includes an optical black region 603 for obtaining a reference signal in which pixels that are shielded from light by a light shielding film are arranged.

  Next, a pixel circuit and a planar layout of the photoelectric conversion device are described with reference to FIGS. FIG. 5A is a circuit diagram illustrating an example of a pixel circuit of the photoelectric conversion device. The pixel 611 includes a photodiode PD that is a photoelectric conversion element, a transfer transistor TT, an amplification transistor AT, and a reset transistor RT. In FIG. 5A, a transfer transistor TT, an amplification transistor AT, and a reset transistor RT are NMOS transistors, and signal charges are electrons. In this configuration example, the photodiode PD has an anode grounded and a cathode connected to the transfer transistor TT. The amplification transistor AT is connected to a constant current circuit (not shown) and constitutes a source follower circuit. The photodiode PD has a charge storage portion of a first conductivity type (n-type in this configuration example) which is a cathode. The node FD includes a floating diffusion part (FD part). The node FD is reset to a predetermined voltage by applying a reset pulse RES to the gate of the reset transistor RT. The pixel selection state and non-selection state are controlled by the predetermined potential. Specifically, when the reset pulse RES is applied to the reset transistor RT in a state where the drain voltage VFDC of the reset transistor RT is set to the first voltage, the pixel is selected. In addition, when the reset pulse RES is applied to the reset transistor RT in a state where the drain voltage VFDC of the reset transistor RT is set to the second voltage, the pixel is in a non-selected state. The first voltage is a voltage for turning on the amplification transistor AT, and the second voltage is a voltage for turning off the amplification transistor AT. In addition, when the transfer pulse Tx is applied to the gate of the transfer transistor TT, the signal charge stored in the charge storage unit is transferred to the node FD. The voltage of the node FD changes according to the amount of charge transferred. By the selection and non-selection operations by the reset transistor RT and the transfer operation of the transfer transistor TT, a signal corresponding to the voltage of the node FD is output from the amplification transistor AT to the vertical output line VSL.

  FIG. 5B is a plan layout diagram of the pixel circuit shown in FIG. In FIG. 5B, the gate electrode GTT of the transfer transistor is disposed between the photodiode PD and the FD portion FD. A gate electrode GRT of the reset transistor is disposed between the FD portion FD and the drain 501 of the reset transistor. Here, the FD portion FD is also the drain of the transfer transistor TT and the source of the reset transistor RT as described above. The gate electrode GAT of the amplification transistor is disposed between the source 502 and the drain 503 of the amplification transistor. The gate electrode GAT of this amplification transistor is connected to the FD portion FD through a shared contact. At this time, the gate electrode GAT of the amplification transistor extends from the FD portion FD to the amplification transistor, and also serves as a wiring connecting the FD portion FD and the gate electrode GAT of the amplification transistor. In FIG. 5B, the part surrounded by a square is a contact.

  Hereinafter, the photoelectric conversion device of the present invention will be described based on such a pixel 611. Note that the circuit and planar layout of the pixel of the present invention are not limited to the configuration shown in FIG. 5, and may have a selection transistor. In the following description, “arranged above” includes not only directly above but also a configuration disposed above and above.

(First embodiment)
The photoelectric conversion apparatus of this embodiment is demonstrated using FIG. FIG. 1 is a schematic cross-sectional view showing a part of the pixel region 601 and a part of the peripheral circuit region 602. A partial cross-sectional view of the pixel region 601 in FIG. 1 corresponds to FIG. 5B, and a partial cross-sectional view of the peripheral circuit region 602 is a cross-section of an arbitrary transistor included in the peripheral circuit region 602. is there. In FIG. 1, the same components as those in FIG. 5B are denoted by the same reference numerals, and description thereof is omitted. In addition, the pixel region 601 and the peripheral circuit region 602 in FIG.

  In the pixel region 601 of FIG. 1, an element isolation 102 such as LOCOS, an n-type charge storage portion 103 constituting a photodiode, a gate electrode 104 of a transfer transistor, and an FD portion 105 are arranged. Further, the pixel region 601 is provided with a gate electrode 106 of the amplification transistor, a sidewall 107 and a source / drain 108 of the transistor in the pixel region. In the peripheral circuit region 602 in FIG. 1, for example, transistors constituting the readout circuit 614 in FIG. 6 are arranged. The transistor includes a gate electrode 109, a sidewall 110, and a source / drain 111.

  In the pixel region 601 and the peripheral circuit region 602 in FIG. 1, a wiring portion is disposed on the main surface 112 of the semiconductor substrate 101. The wiring portion includes a plurality of interlayer insulating films, a plurality of plugs, and a plurality of wiring layers in the pixel region 601 and the peripheral circuit region 602. The plurality of interlayer insulating films include at least a first interlayer insulating film 201, a second interlayer insulating film 202, and a third interlayer insulating film 203. The first interlayer insulating film 201, the second interlayer insulating film 202, and the third interlayer insulating film 203 are stacked in this order from the main surface 112 in FIG. The plurality of plugs are arranged on the plugs 204, 205, and 210 disposed on the first interlayer insulating film 201, the plugs 206 and 212 disposed on the second interlayer insulating film 202, and the third interlayer insulating film 203. 208, 214. The plurality of wiring layers include a first wiring layer disposed on the first interlayer insulating film 201, a second wiring layer disposed on the second interlayer insulating film 202, and a third interlayer insulating film. And a third wiring layer disposed on 203. Each wiring layer shows a set of wirings formed at the same height or in the same process, and has a plurality of wirings. The first wiring layer has wiring 211, the second wiring layer has wirings 207 and 213, and the third wiring layer has wirings 209 and 215. Here, 205a and 205b are used when a plurality of plugs, for example, the plug 205 are shown, and 211a and 211b are shown when a plurality of wirings, for example, the wiring 211 are shown. The same applies to other configurations.

  In the pixel region 601, the plug 204 and the plug 205 disposed on the first interlayer insulating film 201 are connected to elements disposed on the semiconductor substrate 101. The plug 205 is connected to the plug 206 disposed on the second interlayer insulating film 202, and the plug 206 connects the plug 205 and the second wiring layer 207 disposed on the second interlayer insulating film 202. A part of the second wiring layer 207 b is connected to a plug 208 b disposed on the third interlayer insulating film 203, and the plug 208 b is a third wiring layer disposed on the third interlayer insulating film 203. Are connected to some of the wirings 209b. Here, the plug 204 disposed in the first interlayer insulating film 201 has a shared contact structure that electrically connects the FD portion 105 and the gate electrode 106 of the amplification transistor without a wiring. Further, the plug 205 disposed on the first interlayer insulating film 201 and the plug 206 disposed on the second interlayer insulating film 202 have a stacked structure (stack contact structure). The plug 205 and the plug 206 electrically connect the gate electrode 104 of the transfer transistor, the source / drain 108 of the amplification transistor, and the wiring of the second wiring layer 207 disposed thereon. In other words, the connection between the gate electrode 104 of the transfer transistor, the source / drain 108 of the amplification transistor, and the wiring of the second wiring layer 207 disposed thereon has a stack contact structure.

  Next, in the peripheral circuit region 602, the plug 210 disposed on the first interlayer insulating film 201 is connected to an element disposed on the semiconductor substrate 101. The plug 210 is connected to the wiring 211 of the first wiring layer disposed on the first interlayer insulating film 201, and the wiring 211 of the first wiring layer is connected to the plug 212 disposed on the second interlayer insulating film 202. Connecting. The wiring 213 in the second wiring layer disposed on the second interlayer insulating film 202 is electrically connected to the wiring 211 in the first wiring layer through the plug 212. The wiring 213 in the second wiring layer is electrically connected to the wiring 215 in the third wiring layer disposed on the third interlayer insulating film 203 through the plug 214 disposed in the third interlayer insulating film 203. Is done. A stack contact structure is not arranged in the peripheral circuit region 602.

  Here, the first wiring layer is not disposed in the pixel region 601 but is disposed only in the peripheral circuit region 602, and is the wiring layer closest to the semiconductor substrate in the peripheral circuit region 602. With such a configuration in which the first wiring layer is not disposed in the vicinity of the FD portion 105, an increase in the capacity of the FD portion can be suppressed.

  Here, the wiring of the second wiring layer is disposed in the pixel region 601 and the peripheral circuit region 602, and in the pixel region 601 where the first wiring layer is not disposed, the wiring layer closest to the semiconductor substrate is provided. Become. That is, the height of the wiring arranged closest to the semiconductor substrate differs between the pixel region 601 and the peripheral circuit region 602. Here, the height is a height from the main surface 122 of the semiconductor substrate. Specifically, the wiring 211 disposed closest to the semiconductor substrate in the peripheral circuit region 602 is lower than the wiring 207 disposed closest to the semiconductor substrate in the pixel region at the lower surface thereof. Is located. A wiring 207 disposed closest to the semiconductor substrate 101 in the pixel region 601 and a wiring 213 disposed in the second layer from the semiconductor substrate 101 in the peripheral circuit region 602 are high from the surface 112 of the semiconductor substrate. Are equal. Therefore, it can be seen that the peripheral circuit region 602 has more wiring layers between the main surface 112 of the semiconductor substrate and the same height. With such a configuration, even in a configuration in which the peripheral circuit region 602 has a large number of wiring layers, a step difference from the pixel region 601 can be reduced, and an increase in the thickness of the interlayer insulating film in the pixel region 601 can be suppressed. It becomes possible.

  In FIG. 1, the first wiring layer is disposed on the plugs 204 and 205 in the pixel region 601 and is disposed at the same height as the plug 206. In FIG. 1, the bottom surface of the wiring 211 and the bottom surface of the plug 206 are arranged at the same height, but the bottom surfaces may not be the same height. The wiring 211 and the plug 206 are arranged at least at the same height. Further, when the plug 206 and the plug 212 arranged in the second interlayer insulating film 202 are compared, the length of the plug 212 is shorter by the amount of the first wiring layer. With such a short plug 212, the wiring 207 and the wiring 213 in the second wiring layer can be arranged at the same height.

  Next, the thinning of the interlayer insulating film of the photoelectric conversion device of this embodiment will be described with reference to FIG. 2A is a schematic cross-sectional view of the photoelectric conversion device of FIG. 1, and FIG. 2B is a schematic cross-sectional view of a photoelectric conversion device for comparison based on the configuration described in Patent Document 1. 2A and 2B, structures having the same circuit and the same number of wiring layers in the pixel region and the peripheral circuit region are compared. In FIG. 2, the same reference numerals are given to the components corresponding to those in FIG. The photoelectric conversion device 200 in FIG. 2B differs from the photoelectric conversion device 100 in FIG. 2A in particular in the structure of the wiring portion in the peripheral circuit region 602. Here, the wiring part of FIG. 2B will be described. 2B will be described using the same names as those in FIG. 2A for comparison.

  2B includes a plurality of interlayer insulating films, a plurality of plugs, and a plurality of wiring layers. The plurality of interlayer insulating films include a first interlayer insulating film 220, a second interlayer insulating film 221, a third interlayer insulating film 222, and a fourth interlayer insulating film 223 arranged in order from the semiconductor substrate 101 side. And have. The plurality of plugs include plugs 224, 225, 230 on the first interlayer insulating film 220, plugs 226, 231 on the second interlayer insulating film 221, plugs 228, 233 on the third interlayer insulating film 222, 4 has an interlayer insulating film 223 and a plug 235. The plurality of wiring layers include a first wiring layer disposed on the second interlayer insulating film 221, a second wiring layer disposed on the third interlayer insulating film 222, and a fourth interlayer insulating film. And a third wiring layer disposed on the H.223. The first wiring layer has wirings 227 and 232, the second wiring layer has wirings 229 and 234, and the third wiring layer has wirings 236.

  Plugs 224, 225, and 230 disposed on the first interlayer insulating film 220 are connected to elements of the semiconductor substrate 101. Here, the plug 225 disposed on the first interlayer insulating film 220 in the pixel region 601 is connected to the plug 226 disposed on the second interlayer insulating film 221 to form a stack contact structure. Then, the plug 230 disposed on the first interlayer insulating film 220 in the peripheral circuit region 602 is connected to the plug 231 disposed on the second interlayer insulating film 221 to form a stack contact structure. The plug 224 has a shared contact structure as in FIG. Then, the plug 226 in the pixel region 601 is connected to the wiring 227 in the first wiring layer disposed on the second interlayer insulating film 221, and the plug 231 in the peripheral circuit region 602 is on the second interlayer insulating film 221. The wiring 232 of the first wiring layer is connected. After that, a part of the wiring 227 b of the first wiring layer in the pixel region 601 is a part of the wiring 229 b of the second wiring layer disposed on the third interlayer insulating film 222 and the third interlayer insulating film 222. Are electrically connected through a plug 228b disposed in The wiring 232 in the first wiring layer in the peripheral circuit region 602 includes a wiring 234 in the second wiring layer disposed on the third interlayer insulating film 222 and a plug 233 disposed in the third interlayer insulating film 222. Electrically connected. Then, the wiring 234 of the second wiring layer in the peripheral circuit region 602 includes a wiring 236 of the third wiring layer on the fourth interlayer insulating film 223 and a plug 235 disposed on the fourth interlayer insulating film 223. Electrically connected.

  Here, the heights of the layers in the photoelectric conversion device 100 in FIG. 2A and the photoelectric conversion device 200 in FIG. 2B are compared. In the photoelectric conversion device 100, the uppermost wiring layer (the wiring 209 of the third wiring layer) in the pixel region 601 and the uppermost wiring layer (the wiring 215 of the third wiring layer) in the peripheral circuit region 602 are arranged at the same height h1. Has been. It can be seen that there is no step between the pixel region 601 and the peripheral circuit region 602. On the other hand, in the photoelectric conversion device 200, the uppermost wiring layer (wiring 229 of the second wiring layer) of the pixel region 601 is arranged at the height h2, and the uppermost wiring layer (third wiring layer) of the peripheral circuit region 602 is disposed. The wiring 236) is arranged at a height h3. Here, the interlayer insulating film is arranged with a thickness of height h1 on the photoelectric conversion element of the photoelectric conversion device 100, and the interlayer insulating film has a thickness of height h3 on the photoelectric conversion element of the photoelectric conversion device 200. It is arranged. Therefore, the interlayer insulating film disposed on the photoelectric conversion element of the photoelectric conversion device 100 is thinner than the photoelectric conversion device 200 by the difference d2. This difference d2 is the height of one plug. For example, in the 130 nm wiring process, when the height up to h3 is about 2.4 μm, d2 is about 0.30 μm, and about 10 to 20% of the height up to h3 can be reduced. Therefore, the photoelectric conversion device 100 according to the present embodiment can increase the number of wiring layers in the peripheral circuit region 602 while suppressing an increase in the thickness of the interlayer insulating film.

  In addition, when the interlayer insulating film for the wiring layer in the peripheral circuit region disposed in the pixel region in FIG. 2 is removed, the pixel region 601 and the peripheral circuit region 602 in the photoelectric conversion device 200 in FIG. A large step d1 occurs between the two. If such a level difference occurs, there is a possibility that the shape will vary depending on the level difference in subsequent processes, for example, when forming a color filter or when forming a lens. In order to suppress variation in shape, a flattening layer for flattening the level difference is required, and the flattening layer must be provided thick. However, according to the photoelectric conversion device 100 of the present embodiment, even when the interlayer insulating film in the pixel region is removed, it is possible to reduce the step difference from the peripheral circuit region. Even when the peripheral circuit region has more wiring layers than the pixel region, it is possible to reduce the level difference of one wiring layer.

  Next, an example of a method for manufacturing the photoelectric conversion device of FIG. 1 will be described with reference to FIG. 3, members corresponding to the photoelectric conversion device in FIG. 1 are denoted by the same reference numerals as those in FIG. 1 before and after processing. In FIG. 3, the description of the components denoted by the same reference numerals as those in FIG. 1 is omitted.

  First, the element isolation part 102 is formed in the semiconductor substrate 101 using a general semiconductor process. Thereafter, for example, gate electrodes 104, 106, and 109 of transistors made of polysilicon are formed. A semiconductor region (not shown) for forming the charge storage portion 103 of the photodiode and the LDD structure is formed by ion implantation. Then, sidewalls 107 and 110 are formed on the gate electrode. Thereafter, the source and drain 108 and 111 and the FD portion 105 are formed by ion implantation. A first interlayer insulating film 201 made of a silicon oxide film is formed on the element thus formed to obtain the structure shown in FIG.

  Next, a photoresist is applied onto the first interlayer insulating film 201, and the photoresist is patterned by photolithography to form a photoresist mask. The first interlayer insulating film 201 is etched using a photoresist mask to form contact holes 310, 311, 312 for the plugs shown in FIG. 1 in the first interlayer insulating film 201. When the photoresist mask is removed, the structure shown in FIG. 3B is obtained. Here, the contact hole 310 for the shared contact structure exposes the FD portion 105 and the gate electrode 106 of the amplification transistor.

  Next, a barrier metal film made of, for example, a single layer or a stacked layer of titanium or titanium nitride is formed in each of the contact holes 310, 311, 312. In addition, a film containing titanium, tantalum, silicon, tungsten, or the like can be used as the barrier metal film. Subsequently, a metal film for forming a plug made of, for example, a tungsten film is formed so as to cover the barrier metal film. Then, these films other than those buried in each contact hole are removed by CMP or etching. After the removal, plugs 204, 205, and 210 having a barrier metal 313 are formed, and the configuration shown in FIG. 3C is obtained.

  Next, a wiring layer is formed. A barrier metal film, a wiring material film containing aluminum, for example, and a barrier metal film are laminated in this order. Then, using the resist pattern formed by photolithography as a mask, these films are etched to form the wiring 211 of the first wiring layer and its barrier metal 314. A second interlayer insulating film 202 made of, for example, a silicon oxide film is formed so as to cover it, and a planarization process is performed to obtain the structure of FIG. Here, the material and the etching conditions are selected so that the etching selectivity of the barrier metal 313 and the metal film of the plug disposed on the first interlayer insulating film 201 is larger than that of the barrier metal 314 of the first wiring layer. Is desirable. This is to prevent the plug disposed in the first interlayer insulating film 201 under the first wiring layer 211 from being etched or to reduce the etching amount when forming the wiring 211 of the first wiring layer. It is.

  Next, a mask made of a photoresist pattern is formed on the second interlayer insulating film 202, the second interlayer insulating film 202 is etched, the photoresist pattern is removed, and the structure of FIG. obtain. In FIG. 3E, a via hole 315 exposing the surface of the plug 205 is formed on the plug 205 in the pixel region 601. In the peripheral circuit region 602, a via hole 316 that exposes the surface of the wiring 211 is formed on the wiring 211 of the first wiring layer. Although the via holes 315 and 316 have different depths, the wiring 211 and the plug 205 function as an etching stop layer, and thus can be simultaneously formed by etching. Then, the plug 206 and the plug 212 shown in FIG. 1 are processed through a plug formation process including a barrier metal formation process similar to the plug disposed on the first interlayer insulating film 201 shown in FIG. And form. After that, the wiring 207 and the wiring 213 in the second wiring layer shown in FIG. 1 are formed on the second interlayer insulating film 202 in the same process as the wiring 211. Then, as in the previous steps, the third interlayer insulating film 203 shown in FIG. 1 is formed, the plug 208 and the plug 214 are formed, and the wiring 209 and the wiring 215 of the third wiring layer are formed. Thus, the structure of FIG. 1 is obtained.

  Thereafter, plugs, wiring layers, and interlayer insulating films may be further formed as necessary. Although not shown in FIG. 1 and the like, a photoelectric conversion device is completed by further disposing a protective film, a color filter, and a microlens.

  According to the photoelectric conversion device of the present embodiment, it is possible to suppress an increase in the capacity of the FD unit. Further, it is possible to suppress the increase in the thickness of the interlayer insulating film, and to arrange more wiring layers in the peripheral circuit region than in the pixel region. In addition, a step between the peripheral circuit region and the pixel region can be reduced.

  In FIG. 1, a part of the wiring 207 a of the first wiring layer is arranged on the first plug 204 having the shared contact structure and the FD portion 105 so as to overlap in plan view. . A part of the wiring of the first wiring layer disposed closest to the semiconductor substrate 101 in the pixel region 601 covers the FD portion 105, so that the light shielding property of the FD portion 105 is improved, and the FD portion 105 is connected to the FD portion 105. It is possible to reduce light contamination. Here, the term “planar” refers to a planar layout when viewed from the top of the main surface 112 toward the main surface 112 in a direction perpendicular to the main surface 112 of the semiconductor substrate. With such a configuration, the light shielding property of the FD portion is improved, and the quality of the obtained image signal can be improved.

  Here, when the optical black region 603 shown in FIG. 6 includes the same number of wiring layers as the pixel region 601 including the light shielding film, the optical black region 603 has a wiring portion having the same structure as the pixel region 601 in FIG. Is possible. Further, when the optical black region 603 shown in FIG. 6 includes a wiring layer having a larger number of layers than the pixel region 601 including the light shielding film, the wiring portion having the same structure as that of the peripheral circuit region 602 in FIG. It is possible to have. In this case, it is possible to obtain an optical black region having the same configuration as the pixel in the pixel region 601 while having a light shielding film. Note that the photoelectric conversion device is not necessarily provided with the optical black region 603 illustrated in FIG.

(Second Embodiment)
In this embodiment, various damascene structures are applied to the wiring layer of the first embodiment. This embodiment will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view of the photoelectric conversion device. FIG. 4 shows a configuration corresponding to a portion between the semiconductor substrate 101 of FIG. 1 and the wiring 207 and the wiring 213 of the second wiring layer. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. By having a damascene wiring layer and a plug as in this embodiment, fine wiring (both width and thickness) can be formed. In the dual damascene structure, since the wiring layer and the plug are formed in the same process, it is possible to reduce the thickness of the interlayer insulating film by a process margin that needs to be provided for each process. For example, if the height to h3 is about 2.4 μm in the 130 nm wiring process, the margin for forming the plug is about 3%. Therefore, according to the photoelectric conversion device of the present embodiment, the thickness of the interlayer insulating film can be reduced as compared with the photoelectric conversion device of the first embodiment.

  First, in the photoelectric conversion device in FIG. 4A, the wiring 207 in the second wiring layer in the pixel region 601 and the wiring 213 in the second wiring layer in the peripheral circuit region 602 have a single damascene structure. The wiring 207 and the wiring 213 in the second wiring layer having a single damascene structure are so-called copper wirings having copper as a conductor. Copper diffusion prevention films 402 and 403 are disposed on the wiring 207 and the wiring 213. Here, the wiring 207 and the wiring 213 are formed by a single damascene method, and the upper surfaces of the wiring 207 and the wiring 213 form the same surface as the upper surface of the second interlayer insulating film 202.

  With respect to the method for manufacturing the photoelectric conversion device in FIG. 4A, portions different from the first embodiment will be described. After the plug 206 and the plug 212 are formed as in the first embodiment, an interlayer insulating film 401 is formed on the second interlayer insulating film 202. Then, wiring grooves for the first wiring layer and the fourth wiring layer are formed in the interlayer insulating film 401 by etching or the like. Next, a barrier metal film such as titanium nitride is formed so as to cover the inner wall of the wiring trench and the upper surface of the interlayer insulating film 401. Thereafter, a copper film is formed so as to fill the wiring trench in which the barrier metal film is disposed and to cover the upper surface of the interlayer insulating film 401 on which the barrier metal film is formed. The barrier metal film and the copper film formed other than the wiring trench are removed by CMP or the like to form a copper wiring. Finally, a diffusion prevention film for copper, such as a silicon nitride film, is formed so as to cover the copper wiring, and the diffusion prevention film is patterned as necessary, so that the photoelectric conversion device shown in FIG. A configuration is obtained. Thereafter, wiring layers and plugs may be formed until a desired configuration is obtained.

In the photoelectric conversion device of FIG. 4B, in addition to the configuration of FIG. 4A, the wiring 211 of the first wiring layer has a single damascene structure.
The manufacturing method in FIG. 4B is almost the same as that in FIG. Specifically, after the formation of plugs 204, 205, and 210 disposed on the first interlayer insulating film 201, an interlayer insulating film 408 is formed on the first interlayer insulating film 201. A wiring groove for the first wiring layer is formed in the interlayer insulating film 408 by etching or the like. Then, a barrier metal film such as titanium nitride is formed so as to cover the inner wall of the wiring trench and the upper surface of the interlayer insulating film 408. Thereafter, a copper film is formed so as to fill the wiring trench in which the barrier metal film is disposed and to cover the upper surface of the interlayer insulating film 408 on which the barrier metal film is formed. The barrier metal film and the copper film formed other than the wiring trench are removed by CMP or the like to form a copper wiring 211. Then, a diffusion prevention film 407 is formed over the wiring 211, and an interlayer insulation film 409 that covers the diffusion prevention film 407 and the interlayer insulation film 408 is formed. Thereafter, the plugs 206 and 212 are formed in the same manner as in the first embodiment, and the second wiring layer as shown in FIG. 4A is formed, and the photoelectric conversion device shown in FIG. 4B is obtained. .

  Next, in the photoelectric conversion device of FIG. 4C, the wiring 211 of the first wiring layer has a single damascene structure as shown in FIG. 4B. In the photoelectric conversion device in FIG. 4C, the wiring 207 and the plug 206 in the second wiring layer in FIG. 4B have a dual damascene structure. Further, the wiring 213 and the plug 212 have a dual damascene structure.

  The manufacturing method of FIG.4 (c) is as follows. First, after forming the wiring 211 and the diffusion prevention film 404 of the first wiring layer as in FIG. 4B, the interlayer insulating film 409 is formed, and the interlayer insulating film 401 is formed. Then, continuous grooves for wiring and plugs are formed at arbitrary locations in the interlayer insulating films 408, 409, and 401 by photolithography and etching. When the wiring and plug grooves are formed by etching, for example, the interlayer insulating film 409 and the interlayer insulating film 401 are formed of films made of different materials, and the etching selectivity of the interlayer insulating film 409 and the interlayer insulating film 401 is determined. It is possible to form using this. Then, a barrier metal film such as titanium nitride is formed so as to cover the inner walls of the wiring and plug grooves and to cover the upper surface of the interlayer insulating film 401. Then, a copper film is formed so as to fill the wiring and plug trenches where the barrier metal film is disposed and to cover the upper surface of the interlayer insulating film 401 on which the barrier metal film is formed. Next, the barrier metal film and the copper film formed other than the wiring and plug grooves are removed by CMP or the like, and the wiring 207 and the wiring 213 of the second wiring layer of the copper wiring of the dual damascene structure are formed. It is formed. The wirings and plugs of the second wiring layer are formed by a dual damascene method and are integrally formed. The upper surface of the wiring of the second wiring layer forms one surface with the upper surface of the interlayer insulating film. Then, diffusion prevention films 402 and 403 are formed on the first wiring layer, and the photoelectric conversion device of FIG. 4C is obtained.

  By having a damascene wiring layer and a plug as in this embodiment, fine wiring (both width and thickness) can be formed. In the dual damascene structure, since the wiring layer and the plug are formed in the same process, for example, it is not necessary to provide a process margin in the CMP process for forming the plug. Can be reduced. Therefore, according to the photoelectric conversion device of this embodiment, it is possible to suppress an increase in the capacity of the FD unit. In addition, the thickness of the interlayer insulating film can be reduced as compared with the photoelectric conversion device of the first embodiment.

  When copper wiring is applied as in this embodiment, it is preferable to use a conductor mainly composed of tungsten for the plugs 204, 205, and 210 disposed in the first interlayer insulating film 201. If a conductor composed mainly of copper is used as a plug for connection to a semiconductor substrate, the copper diffusion coefficient is large, causing copper diffusion to the semiconductor substrate, resulting in problems such as dark current. This is because there is a possibility that it will end.

(Third embodiment)
The photoelectric conversion device of this embodiment has a configuration that does not use the shared contact structure of the first embodiment. The photoelectric conversion device of this embodiment will be described with reference to FIG. FIG. 7A is a diagram corresponding to FIG. 1, and the same components are denoted by the same reference numerals and description thereof is omitted.
The photoelectric conversion device 700 illustrated in FIG. 7A does not include the shared contact structure plug 204 illustrated in FIG. is doing. Specifically, a plug 705a connected to the FD portion 105 and a plug 705b connected to the gate electrode 106 of the amplification transistor are provided in the first interlayer insulating film 201. The plug 705a is connected to the plug 706a disposed in the second interlayer insulating film 202 and is connected to the wiring 707 included in the first wiring layer. The plug 705b is connected to the plug 706b disposed in the second interlayer insulating film 202, and is connected to the wiring 707 included in the first wiring layer. That is, the FD portion 105 and the gate electrode 106 of the amplification transistor are electrically connected by the plug 705, the plug 706, and the wiring 707. In such a configuration, it is possible to arrange more wiring layers in the peripheral circuit region than in the pixel region while reducing the level difference between the peripheral circuit region and the pixel region.

  A modification of the present embodiment will be described with reference to FIG. In the photoelectric conversion device 701 in FIG. 7B, in addition to the configuration in FIG. 7A, an optical waveguide 702 is provided on the photoelectric conversion element. With such a configuration, it is possible to further improve the light collection efficiency. The optical waveguide 702 can be applied to the configurations of other embodiments.

(Application to imaging system)
FIG. 8 is a diagram illustrating a schematic configuration of a camera that is one of the imaging systems. Note that the concept of a camera includes not only a device mainly for photographing, but also a device (for example, a personal computer or a portable terminal) that is supplementarily provided with a photographing function. The camera 400 includes a solid-state image sensor 1004 typified by the photoelectric conversion device 100 described above. An optical image of the subject is formed on the imaging surface of the solid-state imaging device 1004 by the lens 1002. On the outside of the lens 1002, a barrier 1001 serving both as a protection function of the lens 1002 and a main switch can be provided. The lens 1002 can be provided with a diaphragm 1003 for adjusting the amount of light emitted therefrom. The imaging signal output from the solid-state imaging device 1004 is subjected to various corrections, clamps, and other processes by the imaging signal processing circuit 1005. An imaging signal output from the imaging signal processing circuit 1005 is analog-digital converted by an A / D converter 1006. The image data output from the A / D converter 1006 is subjected to signal processing such as correction and data compression by the signal processing unit 1007. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 operate according to the timing signal generated by the timing generation unit 1008.

  The blocks 1005 to 1008 may be formed on the same chip as the solid-state image sensor 1004. Each block of the camera 400 is controlled by the overall control / arithmetic unit 1009. In addition, the camera 400 includes a memory unit 1010 for temporarily storing image data, and a recording medium control interface unit 1011 for recording or reading an image on a recording medium. The recording medium 1012 includes a semiconductor memory or the like and can be attached and detached. The camera 400 may include an external interface (I / F) unit 1013 for communicating with an external computer or the like.

(Fourth embodiment)
Next, a fourth embodiment will be described. In the embodiments so far, the number of wiring layers is different between the pixel region and the peripheral circuit region, but in this embodiment, the number of wiring layers is equal. In the fourth embodiment, a configuration in which the stack contact structure is applied without providing the wiring of the first wiring layer at least in the vicinity of the FD portion will be described. By having such a configuration, it is possible to reduce an increase in the capacity of the FD portion, and it is possible to suppress a decrease in signal (a decrease in sensitivity).

  First, the capacity of the FD unit will be described. The FD portion is connected to the gate electrode GAT of the amplification transistor and functions as an input portion of the source follower circuit. The signal Vfd input to the source follower circuit is simply expressed as Vfd = Qfd / Cfd using the capacitance Cfd of the node FD including the FD portion and the charge Qfd stored in the node FD. Therefore, when the capacitance of the FD portion increases, the capacitance Cfd of the node FD increases and the signal Vfd decreases. Here, in the vicinity of the FD portion, the wiring of the first wiring layer only for connecting the plug disposed in the first interlayer insulating film and the plug disposed in the second interlayer insulating film is formed. In this case, the area of the wiring facing the FD portion increases. At this time, the capacitance between the FD portion and the wiring increases. In view of such a problem, in this embodiment, the stack contact structure is applied without providing the wiring of the first wiring layer at least in the vicinity of the FD portion.

  First, the planar layout of the pixel circuit of this embodiment will be described with reference to FIG. FIG. 9 shows another configuration of the planar layout diagram of the pixel circuit shown in FIG. In FIG. 9, the same components as those in FIG. In FIG. 9, the wiring 906 included in the first wiring layer is arranged. The wiring 906a is a wiring for connecting the FD portion, the gate electrode GAT of the amplification transistor, and the drain of the reset transistor. The wiring 906c is a wiring for connecting the wiring included in the second wiring layer and the gate electrode GTT of the transfer transistor. The wiring 906d is a wiring for connecting a wiring included in the second wiring layer and an arbitrary semiconductor substrate.

  Hereinafter, the photoelectric conversion device of this embodiment will be described based on such a pixel 611. Note that the circuit and planar layout of the pixel of the present invention are not limited to the structure shown in FIG. 9, and may have a selection transistor.

  The photoelectric conversion apparatus of this embodiment is demonstrated using FIG. FIG. 10 is a schematic cross-sectional view of the photoelectric conversion device based on FIG. 9 and shows a modification of the configuration shown in FIG. The description of the same configuration as that in FIGS. 7A and 9 is omitted.

  In the pixel region 601 and the peripheral circuit region 602 in FIG. 10, a wiring portion is disposed on the main surface 112 of the semiconductor substrate 101. The wiring portion includes a plurality of interlayer insulating films, a plurality of plugs, and a plurality of wiring layers in the pixel region 601 and the peripheral circuit region 602. The plurality of plugs include plugs disposed on the first interlayer insulating film 201, the second interlayer insulating film 202, and the third interlayer insulating film 203. The plugs disposed on the first interlayer insulating film 201 are plugs 904, 905, 911 and the like. The plugs disposed in the second interlayer insulating film 202 are plugs 907a, 907b, 913a, and 913b. Plugs disposed on the third interlayer insulating film 203 are plugs 909 and 915. The plurality of wiring layers include a first wiring layer disposed on the first interlayer insulating film 201, a second wiring layer disposed on the second interlayer insulating film 202, and a third interlayer insulating film. And a third wiring layer disposed on 203. The first wiring layer has wirings 906 and 912, the second wiring layer has wirings 908 and 914, and the third wiring layer has wirings 910 and 916.

  Here, FIG. 10 differs from the configuration of FIG. 7A in the connection structure between the FD portion and the gate electrode 106 of the amplification transistor, and the source / drain 111 of the transistor and the second wiring layer in the peripheral circuit region 602 are different. The connection structure with the wiring 914 is different. Specifically, in FIG. 10, the FD portion and the gate electrode 106 of the amplification transistor are connected not by the wiring of the second wiring layer but by the wiring 906b of the first wiring layer. The source / drain 111 is connected to the wiring 914b of the second wiring layer via the plugs 911b and 913b without passing through the wiring of the first wiring layer. Also in FIG. 10, a stack contact structure is formed in which the plug 904 a in the vicinity of the FD portion 105 is connected to the plug 907 a disposed in the second interlayer insulating film 202 without passing through the first wiring layer. Here, the vicinity of the FD portion 105 is a region surrounding the FD portion or a region adjacent to the FD portion 105. For example, in the case of a CMOS type photoelectric conversion device, the vicinity of the FD portion 105 is above the gate electrode GRT of the reset transistor and the gate electrode GTT of the transfer transistor in FIG. That is, the gate electrode of these transistors and the wiring for supplying a control signal to the gate electrode are connected using the stack contact structure. The FD portion is connected to the gate electrode of the amplification transistor by a shared contact or by using the wiring and the contact of the first wiring layer. In the present embodiment, an increase in capacitance can be suppressed by reducing another wiring adjacent to a wiring for connecting to the gate electrode of the transistor connected to the FD portion. With such a configuration, an increase in the capacity of the FD unit 105 can be reduced, and a decrease in signal (a decrease in sensitivity) can be suppressed.

In the case of forming the wiring of the first wiring layer only for connecting the plug disposed on the first interlayer insulating film and the plug disposed on the second interlayer insulating film, the first wiring Since it is necessary to secure an area for forming the wiring of the layer, it is difficult to advance miniaturization. Therefore, miniaturization can be facilitated by the configuration of the present embodiment.
In addition, since the wiring of the first wiring layer only for connecting the plug disposed on the first interlayer insulating film and the plug disposed on the second interlayer insulating film can be reduced, for example, the first wiring layer It is possible to shorten the area where the wirings face each other, that is, the wiring facing length. Therefore, it is possible to reduce the occurrence of defects due to a short circuit between wirings.

Further, as shown in the third embodiment, a stack contact structure may be applied even in a region that is not in the vicinity of the FD portion 105. With such a configuration, it is possible to reduce the occurrence of defects due to a reduction in height and a short circuit between wirings.
In FIG. 10, some plugs 911 b in the peripheral circuit region 602 are not connected to the wiring of the first wiring layer disposed on the first interlayer insulating film 201, and are disposed on the second interlayer insulating film 202. The stacked contact structure is directly connected to the plug 913b. In this manner, the peripheral circuit region 602 may have a configuration in which stack contact structures are mixed. In particular, it is preferable to apply the peripheral circuit region 602 around a region where an increase in capacitance is not desired, such as an amplifying unit.

  Next, an example of a method for manufacturing the photoelectric conversion device in FIG. 10 will be described with reference to FIG. The reference numerals in FIG. 11 correspond to those in FIG. 10, and the description of the components with the same reference numerals is omitted. In FIG. 11, members corresponding to the photoelectric conversion device in FIG. 10 are denoted by the same reference numerals as those in FIG. 10 before and after processing. Explanation of the same steps as those in the manufacturing method (FIG. 3) of the first embodiment is omitted.

  A semiconductor region including the element isolation portion 102, the gate electrodes 104, 106, and 109 of the transistors, the sidewalls 107 and 110, and the charge storage portion 103 of the photodiode is formed using a general semiconductor process. An insulating film 201 made of a silicon oxide film is formed on the element thus formed to obtain the configuration of FIG. As in the description of the first embodiment, the insulating film 201 that will later become the first interlayer insulating film and the first interlayer insulating film 201 are denoted by the same reference numerals for simplicity. The same applies to other interlayer insulating films.

Next, the insulating film 201 is etched to form contact holes 1110 to 1106 for the plugs shown in FIG. 10 in the insulating film 201 (FIG. 11B). Then, plugs 904a, 904b, 905a, 905b, 911a, and 911b are formed in each contact hole to obtain the configuration shown in FIG.
Next, as shown in FIG. 11D, wirings 906a, 906b, 912a, and 912b of the first wiring layer are formed. An insulating film 202 made of, for example, a silicon oxide film is formed so as to cover it, and a planarization process is performed to obtain the structure of FIG.
Next, the insulating film 202 is etched to obtain the configuration shown in FIG. In FIG. 11E, a via hole 1107 that exposes the surface of the plug 904a is formed on a part of the plugs 904a in the pixel region 601. Further, the via hole 1108 other than on the 904a is formed on the wiring 906b of the first wiring layer so as to expose the surface of the wiring 906b. In the peripheral circuit region 602, a via hole 1110 exposing the surface of the plug 911b is formed on a part of the plugs 911b. Also, the via hole 1109 other than on the 911b is formed on the wiring 212 of the first wiring layer so as to expose the surface of the wiring 212. Then, as in FIG. 11C, plugs 907a and 907b and plugs 913a and 213b are formed. Thereafter, by forming the wiring of the second wiring layer shown in FIG. 10, the third interlayer insulating film 203, the plug 909 and the plug 915, and the wiring 910 and the wiring 916 of the third wiring layer, The structure of FIG. 10 is obtained.

  Thereafter, if necessary, a plug, a wiring layer, and an interlayer insulating film are further formed, and a protective film, a color filter, and a microlens are arranged to complete the photoelectric conversion device. Further, a stacked via structure may be applied to a plug disposed on the further formed interlayer insulating film and a wiring layer disposed on the interlayer insulating film. As described above, the photoelectric conversion device of this embodiment can reduce the capacity of the FD unit. In the present embodiment, the number of wiring layers in the pixel region and the peripheral circuit region may be the same and is not limited.

(Fifth embodiment)
In the present embodiment, as in the second embodiment, various damascene structures are applied to the wiring layer of the fourth embodiment. This embodiment will be described with reference to FIG. FIG. 12 is a schematic cross-sectional view of a photoelectric conversion device. FIG. 12 shows a configuration corresponding to a portion between the semiconductor substrate 101 in FIG. 10 and the wiring 908 and the wiring 914 in the second wiring layer. 12, the same components as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. The damascene structure is the same as that of the second embodiment. By having a damascene wiring layer and a plug as in the present embodiment, it is possible to form fine wiring (both width and thickness), and to further improve the degree of freedom of wiring layout. Further, the thickness of the interlayer insulating film can be reduced as compared with the photoelectric conversion device of the fourth embodiment.

  First, in the photoelectric conversion device in FIG. 12A, the wiring 908 in the second wiring layer in the pixel region 601 in FIG. 10 and the wiring 914 in the second wiring layer in the peripheral circuit region 602 have a single damascene structure. . The wiring 1208 and the wiring 1214 in the second wiring layer having a single damascene structure have copper as a conductor and are so-called copper wirings. Copper diffusion prevention films 1202 and 1203 are disposed on the wiring 1208 and the wiring 1214.

  The manufacturing method of the photoelectric conversion device in FIG. 12A will be described with respect to differences from the fourth embodiment. Similarly to the fourth embodiment, after the plugs 907 a and 907 b and the plugs 913 a and 913 b are formed, an interlayer insulating film 1201 is formed on the second interlayer insulating film 202. Then, a wiring groove for the second wiring layer is formed in the interlayer insulating film 1201 by etching or the like. Next, a barrier metal film such as titanium nitride is formed so as to cover the inner wall of the wiring trench and the upper surface of the interlayer insulating film 1201. Thereafter, a copper film is formed so as to fill the wiring trench in which the barrier metal film is disposed and to cover the upper surface of the interlayer insulating film 1201 on which the barrier metal film is formed. The barrier metal film and the copper film formed other than the wiring trench are removed by CMP or the like to form a copper wiring. In FIG. 12, 1204a, 1204b, 1205a, and 1205b are barrier metals. Finally, a diffusion prevention film for copper such as a silicon nitride film is formed so as to cover the copper wiring, and patterning of the diffusion prevention film is performed as necessary, so that the photoelectric conversion device shown in FIG. A configuration is obtained. Thereafter, wiring layers and plugs may be formed until a desired configuration is obtained. In that case, you may form using not only single damascene but dual damascene.

  In the photoelectric conversion device in FIG. 12B, the wirings 1206 and 1212 in the first wiring layer have a single damascene structure in addition to the configuration in FIG. The manufacturing method in FIG. 12B is almost the same as that in FIGS. 12A and 4B, and the description thereof is omitted. In FIG. 12B, diffusion prevention films 1207 and 1208 are disposed on the wiring of the first wiring layer. Reference numerals 1209 and 1210 denote interlayer insulating films.

  Next, in the photoelectric conversion device of FIG. 12C, the wiring 912 of the first wiring layer has a single damascene structure as shown in FIG. In the photoelectric conversion device in FIG. 12C, the wirings 1208a and 1208b and the plugs 907a and 907b in the second wiring layer in FIG. 12B have dual damascene structures 1220 and 1221, respectively. The wirings 1214a and 1214b and the plugs 1213a and 1213b have dual damascene structures 1222 and 1223, respectively. The manufacturing method of FIG. 12C is the same as that of FIG. 12B and FIG.

  By having a damascene wiring layer and a plug as in this embodiment, fine wiring (both width and thickness) can be formed. In the dual damascene structure, since the wiring layer and the plug are formed in the same process, for example, it is not necessary to provide a process margin in the CMP process for forming the plug. Can be reduced. Therefore, according to the photoelectric conversion device of the present embodiment, the thickness of the interlayer insulating film can be further reduced as compared with the photoelectric conversion device of the first embodiment.

  When copper wiring is applied as in this embodiment, it is preferable to use a conductor mainly composed of tungsten for the plugs 904, 905, and 911 disposed in the first interlayer insulating film 201. If a conductor composed mainly of copper is used as a plug for connection to a semiconductor substrate, the copper diffusion coefficient is large, causing copper diffusion to the semiconductor substrate, resulting in problems such as dark current. This is because there is a possibility that it will end.

(Sixth embodiment)
The photoelectric conversion device of this embodiment has a configuration using a shared contact structure in the fourth embodiment. Here, the shared contact structure means that the plugs 905a and 905b disposed in the first interlayer insulating film 201 in FIG. 10 electrically connect the FD portion 105 and the gate electrode 106 of the amplification transistor without the wiring 906a. It is a structure to do. The photoelectric conversion device of this embodiment will be described with reference to FIG. FIG. 13A is a diagram corresponding to FIG. 10, and the same components are denoted by the same reference numerals and description thereof is omitted.

  The photoelectric conversion device illustrated in FIG. 13A includes a plug 1305 having a shared contact structure, and the FD portion 105 and the gate electrode 106 of the amplification transistor are connected by the plug 1305. That is, the FD portion 105 and the gate electrode 106 of the amplification transistor are electrically connected by the plug 1305. Even in such a configuration, it is possible to form a stack contact structure as in the other embodiments. Furthermore, since the intermediate wiring layer near the FD portion can be eliminated by using the shared contact structure, the capacity of the FD portion can be reduced.

  A modification of the present embodiment will be described with reference to FIG. The photoelectric conversion device in FIG. 13B has a configuration in which the number of wiring layers in the peripheral circuit region is larger than that in the pixel region in the configuration in FIG. With this configuration, it is possible to increase only the number of wiring layers in the peripheral circuit area where the scale of the circuit is remarkable, and to maintain the distance between the semiconductor substrate in the pixel region and the closest wiring, thereby improving sensitivity. Leads to. Further, a structure in which the number of wiring layers in the peripheral circuit portion is increased as described above can be realized without using a shared contact structure (not shown).

  Further, the stack contact structure is not limited to two plugs, and may have a configuration in which three or more plugs as shown in plugs 1302a, 1303a, and 1304a in FIG. 13B are directly connected. In the peripheral circuit portion, connections (1308 to 1310) via wiring and stack contact structures (1306 and 1307) may be mixed. Further, the stack contact structure includes not only plugs disposed on the first interlayer insulating film and the second interlayer insulating film but also plugs disposed on the second interlayer insulating film and the third interlayer insulating film. May be. The same applies to other embodiments.

  The present invention is not limited to a CMOS type photoelectric conversion device, but can be applied to a photoelectric conversion device having a plurality of wiring layers. Further, the plugs of the shared contact structure shown in some embodiments may be arranged in the peripheral circuit region. Furthermore, in the present invention, the vicinity of the FD portion has been described as a portion that suppresses the increase in capacitance. However, the present invention can be applied to any portion that does not require an increase in capacitance, such as the vicinity of the amplification portion in the peripheral circuit portion. is there.

  The configurations of the embodiments of the present invention described above can be changed as appropriate and can be combined. It is also clear that the photoelectric conversion devices described in the fourth to sixth embodiments can be applied to an imaging system.

DESCRIPTION OF SYMBOLS 100 Photoelectric conversion apparatus 101 Semiconductor substrate 102 Element isolation 103 Charge storage part 104,106,109 Gate electrode of MOS transistor 105 Floating diffusion part (FD part)
107, 110 Side walls 108, 111 MOS transistor source / drain 201-203 First to third interlayer insulating films 204-6, 208, 210, 212, 214 Plug 211 First wiring layer wiring 207, 213 First Second wiring layer wiring 209, 215 Third wiring layer wiring 601 Pixel region 602 Peripheral circuit region 603 Optical black region

Claims (12)

A semiconductor substrate on which a photoelectric conversion element, a floating diffusion portion, a transfer transistor that transfers charges of the photoelectric conversion element to the floating diffusion portion, and an amplification transistor that outputs a signal based on the potential of the floating diffusion portion; ,
In a photoelectric conversion device having a first wiring layer and a plurality of wiring layers including a second wiring layer disposed on the first wiring layer,
A photoelectric conversion device, wherein a gate electrode of the transfer transistor and the second wiring layer are connected in a stack contact structure. The photoelectric conversion device according to claim 1;
An image pickup system, comprising: a signal processing circuit that processes a signal output from the photoelectric conversion device. A pixel region in which a plurality of pixels including photoelectric conversion elements and transistors are arranged;
A semiconductor substrate having a transistor and a peripheral circuit region having more wiring layers than the pixel region;
A plurality of interlayer insulating films including a first interlayer insulating film and a second interlayer insulating film disposed on the first interlayer insulating film; and on the first wiring layer and the first wiring layer A wiring portion disposed on the semiconductor substrate, the wiring portion including a plurality of wiring layers including a second wiring layer disposed on
In a photoelectric conversion device having
The wiring portion includes the first wiring layer and a plug disposed in the first interlayer insulating film connected to the first wiring layer in the peripheral circuit region, and the second wiring layer A plug disposed in the first interlayer insulating film connected to the second wiring layer and a plug disposed in the second interlayer insulating film in the pixel region;
The wiring layer arranged closest to the semiconductor substrate is the first wiring layer in the peripheral circuit region, and the second wiring layer in the pixel region.   The plug disposed in the first interlayer insulating film disposed in the pixel region and the plug disposed in the second interlayer insulating film have a stack contact structure in which the plugs are stacked in contact with each other. The photoelectric conversion device according to claim 3. The transistor disposed in the pixel region includes a transfer transistor that transfers charges generated in the photoelectric conversion element, and an amplification transistor that outputs a signal based on the charges,
The wiring portion includes a plug having a shared contact structure in the first interlayer insulating film that connects a floating diffusion portion to which the transfer transistor transfers charges and a gate electrode of the amplification transistor in the pixel region. The photoelectric conversion device according to claim 4.   6. The photoelectric conversion device according to claim 5, wherein at least a part of the first wiring layer is disposed on the plug of the shared contact structure and is disposed on the floating diffusion portion. The plug disposed on the first interlayer insulating film, the plug disposed on the first interlayer insulating film, and the plug disposed on the second interlayer insulating film are formed of a barrier metal film and a conductor. And
The material of the barrier metal film includes any of titanium, tantalum, silicon, and tungsten,
The photoelectric conversion device according to claim 3, wherein the material of the conductor includes tungsten. The photoelectric conversion device according to claim 3, wherein a material of the plurality of wiring layers includes either copper or aluminum. The wiring portion has a plug disposed on the second interlayer insulating film connected to the second wiring layer in the peripheral circuit region,
4. The photoelectric conversion according to claim 3, wherein a plug disposed in the second interlayer insulating film in the pixel region is longer than a plug disposed in the second interlayer insulating film in the peripheral circuit region. apparatus. The photoelectric conversion device has an optical black region having light-shielded pixels for obtaining a reference signal,
The wiring portion of the optical black region includes the first wiring layer and a plug disposed on the first interlayer insulating film connected to the first wiring layer;
4. The photoelectric conversion device according to claim 3, wherein a wiring layer disposed closest to the semiconductor substrate in the optical black region is the first wiring layer. 5. The photoelectric conversion device according to claim 2;
An image pickup system, comprising: a signal processing circuit that processes a signal output from the photoelectric conversion device. A pixel region in which a plurality of pixels including photoelectric conversion elements and transistors are arranged;
A semiconductor substrate having a transistor and a peripheral circuit region having more wiring layers than the pixel region;
In a method of manufacturing a photoelectric conversion device having a plurality of interlayer insulating films disposed on the semiconductor substrate and a wiring portion having a plurality of wiring layers,
Forming a first interlayer insulating film on the semiconductor substrate;
Forming a plurality of plugs in the first interlayer insulating film;
Forming a first wiring layer connected to a part of the plurality of plugs formed in the first interlayer insulating film on the first interlayer insulating film in the peripheral circuit region;
A step of forming a second interlayer insulating film after the step of forming the first wiring layer;
A part of the second interlayer insulating film is removed and a hole exposing a part of the plurality of plugs formed in the first interlayer insulating film in the pixel region and the first wiring in the peripheral circuit region Forming a hole exposing a part of the layer in the second interlayer insulating film;
Forming a plug in the second interlayer insulating film by filling a conductor in a hole formed in the second interlayer insulating film;
A step of forming a second wiring layer on the second interlayer insulating film after the step of forming a plug in the second interlayer insulating film;
A process for producing a photoelectric conversion device comprising:

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