JP2011166033A - Solid-state image pickup element, method of manufacturing the same, and electronic information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup element which uses a charge-coupled device (CCD) for preventing alteration in quality and corrosion of metal-wiring layer, forming a charge detecting portion and reducing the capacity by the metal-wiring layer, without causing reduction in converting efficiency for converting signal charges into a signal voltage in the charge-detecting portion. <P>SOLUTION: The solid-state image pickup element 100 that uses a CCD includes a charge transfer portion for transferring the signal charges obtained by photo-electric conversion in a plurality of photo-electric converting regions and a charge-detecting portion for converting signal charges transferred to the signal voltage. In the solid-state image pickup element, a metal layer 7, forming the charge detecting portion and a hollow structure wherein a hollow region 16, is provided between insulating layers 11, and 12 covering the metal layer 7 are provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an electronic information device, and more specifically, a solid-state imaging device that realizes high reliability without reducing a charge-voltage conversion rate in a charge detection unit, and a manufacturing method thereof, In addition, the present invention relates to an electronic information device equipped with such a highly reliable solid-state imaging device.

  2. Description of the Related Art Conventionally, in a camera-equipped mobile phone, a digital still camera (DSC), a surveillance camera, and the like, a solid-state imaging device such as a CCD (Charge Coupled Device) image sensor (hereinafter also referred to as a CCD solid-state imaging device) is used as an imaging device. It has been.

  FIG. 8 is a diagram for explaining a conventional CCD type solid-state imaging device. FIG. 8A schematically shows the entire configuration of the CCD type solid-state imaging device, and FIG. The cross-sectional structure of the charge detection part in a CCD type solid-state image sensor is shown.

  As shown in FIG. 8A, the CCD solid-state imaging device 210 is arranged in a matrix and is provided corresponding to a plurality of light receiving portions (photoelectric conversion regions) Px for performing photoelectric conversion, and each light receiving portion row. A vertical transfer unit (vertical CCD) 211 that transfers charges generated in the photoelectric conversion area in the vertical direction, and a horizontal transfer unit (horizontal CCD) 212 that transfers signal charges from the vertical transfer unit 211 in the horizontal direction; have. The solid-state imaging device 210 is disposed on the final stage side of the horizontal transfer unit 212, detects the transferred signal charge and outputs it as a voltage signal, and is stored in the charge detection unit 213. And a charge discharging unit 214 that discharges the signal charge to the outside of the solid-state imaging device 210. Here, the light receiving unit PD is formed of a photodiode, and the charge detection unit 220 is arranged on the final stage side of the horizontal transfer unit 212, and stores a charge storage unit 213 that stores the transferred signal charge, and a detected signal. And an output unit 215 that converts the electric charge into a signal voltage and amplifies the signal voltage. Each light receiving part PD forms each pixel Px in the solid-state imaging device.

  In such a CCD type solid-state imaging device 210, the signal charge generated in the light receiving unit (photodiode) PD is transferred by the charge transfer unit (vertical CCD 211 and horizontal CCD 212), and the signal charge is transferred by the charge detection unit 220. It is converted into a signal voltage and output.

  Normally, the charge detection unit 220 has a structure called FDA (floating diffusion amplifier), and the charge storage unit and output unit in the FDA structure are configured as shown in FIG.

As shown in FIG. 8B, in the surface region of the silicon substrate 51, the detection unit N ⁺ impurity layer 55 that forms the charge storage unit 213 and the reset drain N ⁺ impurity diffusion layer 57 that forms the charge discharge unit 214. And are formed. An N ⁻ impurity layer 64a serving as a channel region constituting a reset transistor is formed between the impurity layer 55 and the impurity layer 57, and a reset gate electrode RG is formed on the N ⁻ impurity layer 64a. A polysilicon layer 58 is formed. An N ⁻ impurity layer 64 constituting a transfer channel of the horizontal CCD 212 is formed on the horizontal CCD side of the detection unit N ⁺ impurity layer 55, and a transfer gate electrode of the horizontal CCD 212 is provided on the impurity layer 64. A polysilicon layer 52 having a two-layer structure is formed.

  The transfer gate electrode OG is the final gate electrode that reads the signal charge transferred from the charge transfer unit to the charge detection unit 220, and the reset gate electrode RG is stored in the charge storage unit of the charge detection unit 220. This is a gate electrode for discharging and resetting the signal charge to the reset drain RD, and a driving voltage (power supply voltage) for driving the solid-state imaging device is applied to the reset drain RD.

FIG. 9 is a plan view for explaining the layout pattern of the impurity layer and the electrode in the vicinity of the charge detection unit 220, and FIG. 9A shows the separation pattern of the active region (impurity layer), the pattern of the gate electrode, Only the N ⁺ impurity layer pattern and the contact pattern are schematically shown. FIG. 9B shows only the isolation pattern of the active region, the arrangement pattern of the N ⁺ impurity layer, and the pattern of the metal layer.

On the silicon substrate 51 (see FIG. 9B), an N ^- impurity layer 64 serving as a channel region of the horizontal CCD 212 is formed, and is made of a first layer polysilicon as a two-layer transfer electrode constituting the horizontal CCD. First layer gate electrodes 52a and second layer gate electrodes 52b made of second layer polysilicon are alternately arranged. The end side portion of the horizontal CCD 212 of the N ⁻ impurity layer 64 is connected to an N ⁺ impurity layer (reset drain impurity layer) 57 constituting a reset drain, and the N ⁺ impurity layer 57 and the N ⁻ impurity layer 64 are connected to each other. In the connection portion, a polysilicon layer 58 constituting a reset gate is formed via an insulating film (not shown).

Further, an N ⁺ impurity layer (detection part impurity layer) 55 constituting a charge detection part is formed in a part of the N ⁻ impurity layer 64 between the reset gate RG and the final transfer gate 52c. An N ⁻ impurity layer 65 constituting a transistor (output circuit transistor) of the output unit 215 is formed so as to be close to the ⁺ impurity layer 55.

  Here, a polysilicon layer 67 serving as a gate electrode is formed on the impurity layer 65 of this transistor via an insulating film (not shown), and one end of the polysilicon layer 67 is formed on the detection unit impurity layer 55. positioned. Further, on both sides of the gate electrode of the transistor impurity layer 65, a source / drain region is formed, and a contact hole 65a is formed for connection to the upper metal wiring 57b. On the reset drain impurity layer 57, a contact hole 57a for connecting the impurity layer to the upper metal layer 59 is formed. A metal layer 54 is also formed on the transfer gate 52 constituting the horizontal CCD. However, this metal layer is formed as a light shielding film and is not used as an electrical wiring layer. is there.

  Here, the capacitance component CFD possessed by the charge detection unit is expressed as follows.

CFD = C1 + C2 + C3 + Cd + Cg + Cf
C1 is a capacitance component between the final transfer gate OG and the detection unit impurity layer (including the metal wiring 56) 55, C2 is a capacitance component between the reset gate RG and the detection unit impurity layer (including the metal wiring 56), C3 is a capacitance component between the detection unit metal wiring 56 and the reset drain wiring 59, Cd is a junction capacitance component in the detection unit impurity region and between the detection unit impurity region and the substrate, Cg is a capacitance component of the output unit transistor, Cf is a stray capacitance component of the charge detection unit itself, that is, a stray capacitance component of the conductive member constituting the charge detection unit.

  The output voltage Vout of the output unit is expressed by the following equation, where Qsig is the amount of charge input from the final transfer gate OG to the charge detection unit 220.

Vout = Qsig / CFD
From this equation, it can be seen that in order to increase the output voltage Vout, it is necessary to reduce the capacitance CFD of the charge detection unit.

  For this reason, in the conventional CCD type solid-state imaging device, a measure has been taken to remove the dielectric film on the charge detection unit and to make the capacitance component of the charge detection unit as small as possible.

  FIG. 10 is a cross-sectional view for explaining a CCD solid-state imaging device to which such a countermeasure is taken. FIG. 10A is a cross-sectional view of the structure (charge) of the Xa-Xa line in FIGS. FIG. 10B shows the Xb-Xb line cross-sectional structure of FIG. 9A and FIG. 9B (cross-sectional structure of the charge detection unit).

The cross-sectional structure shown in FIG. 10A is similar to the cross-sectional structure shown in FIG. 8B, in the surface region of the silicon substrate 51, the detection unit N ⁺ impurity layer 55 that forms the charge storage unit 213, and the charge A reset drain N ⁺ impurity diffusion layer 57 that constitutes the discharge portion 214 is formed. An N ⁻ impurity layer 64a serving as a channel region constituting a reset transistor is formed between the impurity layer 55 and the impurity layer 57, and a reset gate electrode RG is formed on the N ⁻ impurity layer 64a. A polysilicon layer 58 is formed. Further, an N ⁻ impurity layer 64 constituting a transfer channel of the horizontal CCD 212 is formed on the horizontal CCD side of the detection unit N ⁺ impurity layer 55, and a transfer gate electrode OG of the horizontal CCD 212 is formed on the impurity layer 64. A polysilicon layer 52 having a two-layer structure is formed.

The N ⁻ impurity layer 65 constituting the transistor of the output part is formed separated from the detection part N ⁺ impurity layer 55 by the field insulating film 66, and the gate electrode of the transistor is formed on the N ⁻ impurity layer 65. A polysilicon layer 67 is formed through an insulating film, and one end of the polysilicon layer 67 is located on the detection portion N ⁺ impurity layer 55.

  On the field oxide film and the impurity layer, a lower metal insulating film 53 is formed so as to cover the entire surface. On the lower metal insulating film 53, a metal layer 54 as a light shielding film is a transfer electrode of the horizontal CCD. Metal layers 56 and 59 are formed as wirings as well.

The metal layer 56 is connected to the detection portion N ⁺ impurity layer 55 and the polysilicon layer 67 of the output transistor through a contact hole formed in the lower metal insulating film 53. The metal layer 59 is connected to the transistor impurity layer 57 through a contact hole formed in the lower metal insulating film 53.

  Further, an on-chip organic material layer 61 is formed on the entire surface of the substrate via an element protection film 60 such as a silicon nitride film so as to cover these polysilicon layers 52 and 58, and an on-chip surface antireflection film 63 is formed on the surface thereof. Is formed. Here, the on-chip organic material layer 61 includes an on-chip color filter layer 62.

In this conventional solid-state imaging device 200, the region R inside the circle with a constant radius centered on the detection unit N ⁺ impurity layer 55 shown in FIGS. 9A and 9B is an on-chip organic material. The layer 61 and the on-chip surface antireflection film 63 are removed and exposed.

  Next, a method for manufacturing the solid-state imaging device shown in FIG. 10 will be described.

  FIG. 11 is a cross-sectional view showing the manufacturing method of the conventional solid-state imaging device shown in FIG. 10 in the order of steps (FIGS. (A) to (e)), and particularly shows the steps after the metal layer forming step. Yes. In addition, the element structure obtained by the process up to the formation process of the metal layer is shown in FIG.

First, as shown in FIG. 10, an N ⁻ impurity layer 64 serving as a charge transfer path, an N ⁻ impurity layer 64a serving as a channel region of a reset transistor, a detection unit N ⁺ impurity layer 55, and a reset drain N are formed on a silicon substrate 51. ^{The +} impurity layer 57 is formed by selective impurity diffusion treatment, and then a charge transfer portion 52 is formed by a two-layer polysilicon gate, and a reset gate electrode 58 for discharging the charge of the detection portion to the reset drain is formed. To do.

  Thereafter, a lower metal insulating film 53 is formed on the entire surface, and a transfer portion upper metal layer 54 as a light shielding film, a metal wiring 56 for transmitting the potential of the detection portion to the output transistor, and a reset drain metal wiring 59 are formed ( FIG. 11 (a)).

Next, a protective film 60 such as a silicon nitride film is formed on the entire surface of the underlying structure 71 up to these metals (FIG. 11B). At this time, the film formation conditions are as follows: in a low temperature plasma CVD apparatus, the temperature is 300 to 400 ° C., the pressure is 1.5 to 3.0 Torr, the high frequency RF power is 500 to 1000 W, the low frequency RF power is 100 to 700 W, and the flow rate of SiH ₄ gas is 100. The conditions of ˜200 sccm, NH ₃ gas flow rate of 200 to 1000 sccm, N ₂ gas flow rate of 10000 to 15000 sccm, and film thickness of 20 to 50 nm are used.

  Subsequently, a transparent organic material that is an on-chip layer is applied and planarized, and then an organic material layer such as the color filter 62 is formed by spin coating. Further, a transparent organic material, which is an on-chip layer, is formed to a predetermined thickness in order to adjust the height (condensing height) of the microlens from the light receiving portion. For example, although the condensing height of the microlens varies depending on the number of pixels of the solid-state imaging device, the organic material is set so that the distance from the opening surface of the light receiving unit to the bottom of the microlens is about 3.0 to 7.0 μm. Adjust by layer thickness.

Thereafter, a surface antireflection film 63 made of a material such as a silicon oxide film is also formed by low temperature plasma CVD. As the film forming conditions, the temperature is 200 to 250 ° C., the pressure is 1.5 to 3.5 Torr, the RF power is 150 to 300 W, SiH ₄ .N ₂ O.N ₂ gas is used, and the film thickness is 10 to 50 nm. Use conditions.

  The color filter layer 62 is a portion located above the charge detection portion during the photolithography process when forming the color filter because residues and the like remain in the subsequent dry etching process and are difficult to remove completely. Has been removed.

  After all these on-chip processes (color filter and microlens forming process) are completed, an etching pattern 66b (resist mask or the like) having an opening 66a is formed above the detection portion, and dry etching is performed. Then, the silicon oxide film 63 as an antireflection film, the organic material layer 61, and the silicon nitride film layer 60 as a protective film are removed by etching.

  In this etching process, since the silicon oxide film, the organic film (acrylic film), and the silicon nitride film are etched from the upper layer side, a three-step etching process is performed using a plasma etching apparatus. Specifically, although the etching process is a single process, the processing conditions are switched to an etching step suitable for each film during the single etching process.

The etching conditions of the first step for etching the silicon oxide film are as follows: pressure 500 to 2000 mtorr, RF power 750 to 1500 W, and used gas O ₂ · CHF ₃ . Etching conditions for etching the acrylic film in the second step are a pressure of 500 to 1500 mtorr, an RF power of 300 to 750 W, and a working gas O ₂ · CHF ₃ . Etching conditions for etching the silicon nitride film in the third step are a pressure of 1000 to 2000 mtorr, an RF power of 750 to 1500 W, and a working gas O ₂ · CF ₄ .

  Note that, regarding these on-chip process layers (layers formed in the on-chip process), electrode pad portions for the solid-state imaging device to exchange signals with the outside are also removed at the same time (not shown).

  A conventional CCD solid-state imaging device has the above-described structure, and is manufactured by the manufacturing method described above.

  Japanese Patent Laid-Open No. 2004-228561 prevents a decrease in detection sensitivity by preventing an increase in the capacity of the charge detection unit by not arranging a material constituting the color filter array in at least a part of the detection unit. It is disclosed.

  However, recent CCD-type solid-state imaging devices are increasingly used in harsh environments such as in-vehicle peripheral monitors, drive recorders that record the situation before and after an accident, or surveillance cameras in high-temperature and high-humidity areas. Tend to be.

  In these harsh environments, not only the solid-state imaging device itself becomes high temperature, but also all the films on the metal film as shown in FIG. In solid-state image sensors where the metal film has been removed, the moisture and high-temperature environment that the metal film in the detection unit has penetrated cause corrosion and deterioration, leading to a significant decrease in reliability such as malfunction. There is a problem that it ends up.

  Therefore, in order to cope with these harsh usage environments, as shown in FIG. 12, in the solid-state imaging device 200 shown in FIG. 11, a protective film (silicon nitride film) 60 is provided in a region R where the charge detection unit is disposed on the substrate. A solid-state imaging device 200a that employs a structure that leaves only the same has already been developed.

  FIG. 13 is a cross-sectional view showing the manufacturing method of the conventional solid-state imaging device shown in FIG. 12 in the order of steps (FIGS. (A) to (e)).

  The manufacturing method of the solid-state imaging device 200a shown in FIG. 12 has almost the same steps as the manufacturing method of the solid-state imaging device 200 shown in FIG. 11, but the manufacturing method of the solid-state imaging device 200 shown in FIG. The step of etching the film formed on the charge detection portion shown in FIG. 13E is different from that of the solid-state imaging device 200 shown in FIG.

  That is, in the manufacturing method of the solid-state imaging device 200a shown in FIG. 12, after forming the on-chip layer, the silicon oxide film and the organic film are formed from the upper layer side as in the manufacturing method of the solid-state imaging device 200 shown in FIG. (Acrylic film) The silicon nitride film is not etched, but only the silicon oxide film and the organic film (acrylic film) are etched from the upper layer side, that is, the silicon nitride film This etching step is not performed.

  Note that the steps shown in FIGS. 13A to 13D in the method for manufacturing the solid-state imaging device shown in FIG. 12 are the steps shown in FIGS. 11A to 11D in the method for manufacturing the solid-state imaging device shown in FIG. Is exactly the same.

  For the electrode pad portion, it is necessary to remove the silicon nitride film for electrical connection. Therefore, when etching the silicon nitride film, a mask patterned so as to selectively remove the silicon nitride film is used. It is necessary to devise a method such as using the silicon nitride film at the electrode pad portion or independently of the etching process of the upper silicon oxide film and the organic film (acrylic film). .

  By leaving the silicon nitride film on the charge detection portion in this way, moisture (and impurities) that has entered the package of the solid-state imaging device from the outside and the metal wiring of the solid-state imaging device are not in direct contact with each other, It is possible to prevent the deterioration and corrosion of the metal, so that problems such as malfunction can be prevented to some extent.

  However, as described above, leaving the insulating film on the metal layer that constitutes the charge detection unit causes an increase in the capacitance of the detection unit, resulting in a decrease in output of about 10% at the same incident light amount. It becomes.

  Patent Document 2 discloses a CCD output unit corresponding to a charge detection unit covered with a low dielectric constant material having a dielectric constant lower than that of a mold resin, as in the solid-state imaging device shown in FIG. Similarly to the solid-state imaging device shown in FIG. 12, the one disclosed in Patent Document 2 also causes an increase in the capacity of the detection unit by leaving an insulating film on the metal layer constituting the charge detection unit.

  In addition, there are various methods for reducing the capacity of the charge detection unit as a whole. For example, Patent Documents 3 and 4 both include a wiring layer (polysilicon) between the charge detection unit and the first stage transistor and a substrate ( A device with a reduced capacitance to the (GND potential) is disclosed.

  However, the cited documents 3 and 4 do not reduce the capacitance (floating capacitance) between the insulating film formed above the charge detection portion and the conductive layer constituting the charge detection portion.

JP-A-2-2675 JP-A-5-251676 Japanese Patent Laid-Open No. 3-116840 JP-A-11-297982

  As described above, in the conventional technique, the dielectric film on the charge detection unit is removed so that the voltage of the output signal increases, and the corrosion of the metal wiring constituting the charge detection unit is prevented, and the reliability is improved. It is contrary to manufacturing a high device, and it has been difficult to realize a solid-state imaging device that satisfies both of them.

  The present invention has been made to solve the above-described problems, and the alteration of the metal wiring layer constituting the charge detection unit can be achieved without increasing the capacity of the metal wiring layer constituting the charge detection unit. And a solid-state imaging device with high conversion efficiency that can change signal charges into signal voltages and thereby have high reliability, a method for manufacturing the same, and an electronic information device using such a solid-state imaging device The purpose is to obtain.

  The solid-state imaging device according to the present invention has been transferred to a plurality of photoelectric conversion regions provided on a semiconductor substrate, and a charge transfer unit that transfers signal charges obtained by photoelectric conversion in the plurality of photoelectric conversion regions. A solid-state imaging device having a charge detection unit that converts a signal charge into a signal voltage, and an output circuit that amplifies the signal voltage and outputs the signal voltage to the outside as a pixel signal, and a conductive layer that constitutes the charge detection unit; A hollow structure in which a hollow region is interposed between the conductive layer and the insulating layer covering the conductive layer can achieve the above object.

  According to the present invention, in the solid-state imaging device, the conductive layer forming the hollow structure is preferably a metal layer.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that the insulating layer covering the metal layer, which is the conductive layer forming the hollow structure, is composed of two protective films.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that each of the two protective films is a silicon nitride film.

  In the solid-state imaging device, the present invention has an etching resistance to the etching process as an etching stop film used in the etching process for forming the hollow region below the conductive layer forming the hollow structure. A film is preferably formed.

  According to the present invention, in the solid-state imaging device, the film having etching resistance to the etching process is preferably a silicon nitride film.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that a transparent organic material, a color filter material, and an antireflection film layer are laminated on the insulating layer forming the hollow structure so as to cover the hollow region.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that each of the transparent organic material, the color filter material, and the antireflection film layer is an on-chip material layer.

  A manufacturing method of a solid-state imaging device according to the present invention includes a plurality of photoelectric conversion regions provided on a semiconductor substrate, a charge transfer unit that transfers signal charges obtained by photoelectric conversion in the plurality of photoelectric conversion regions, and a transfer A method of manufacturing a solid-state imaging device having a charge detection unit that converts a signal charge that has been generated into a signal voltage and an output circuit that amplifies the signal voltage and outputs the signal voltage to the outside as a pixel signal, the charge detection unit Forming a conductive layer comprising: a sacrificial layer for forming a hollow region on the conductive layer, covering the conductive layer; and an insulating layer covering the sacrificial layer And a step of removing the sacrificial layer so that a hollow region is formed between the conductive layer and the insulating layer, whereby the above object is achieved.

  In the method for manufacturing a solid-state imaging device according to the present invention, the step of forming the insulating layer so as to cover the sacrificial layer includes the step of forming a first protective film so as to cover the sacrificial layer, and the first protective film. A step of selectively removing a portion located on the edge portion of the sacrificial layer to form a protective film opening, and a step of removing the sacrificial layer by exposing the sacrificial layer to an etchant through the protective film opening; And forming a second protective film on the first protective film so as to close the protective film opening.

  According to the present invention, in the method for manufacturing a solid-state imaging device, the sacrificial layer is preferably a photoresist film.

  According to the present invention, in the method for manufacturing a solid-state imaging device, in the step of selectively removing a portion of the first protective film located on the edge portion of the sacrificial layer to form a protective film opening, The selective etching of the first protective film is performed using a photoresist mask, and when removing the photoresist film as the sacrificial layer, the photoresist mask used in the selective etching of the first protective film is also removed. Is preferred.

  According to the present invention, in the method for manufacturing a solid-state imaging device, the sacrificial layer is preferably a silicon oxide film.

  The present invention provides a method for manufacturing a solid-state imaging device, wherein a film having etching resistance to etching of the sacrificial layer is formed as a base layer of the conductive layer before forming the conductive layer constituting the charge detection unit. In the etching process including the step of forming and removing the sacrificial layer, it is preferable to use a film having the etching resistance as an etching stopper layer.

  An electronic information device according to the present invention is an electronic information device including an imaging unit that captures an image of a subject, and the imaging unit is the above-described solid-state imaging device according to the present invention, thereby achieving the above object. Is done.

  Next, the operation of the present invention will be described.

  In the present invention, a protective film is formed to prevent moisture entering from the outside, but the protective film is not in contact with the metal film, so that the charge detection is performed so that the voltage of the output signal increases. It is possible to obtain a solid-state imaging device that satisfies both removal of the dielectric film on the portion and prevention of corrosion of the metal wiring constituting the charge detection portion.

  In other words, by forming a protective film on the metal layer that constitutes the charge detection unit via a cavity, it is not necessary to remove the on-chip layer (organic film) as an upper layer further, Problems such as an increase in capacitance at the charge detection unit do not occur. As a result, the charge detection part is not only covered with the protective film of the silicon nitride film but also covered with an organic film having good hygroscopicity.

  For this reason, the invaded moisture does not directly contact the protective film, but is once absorbed and contacted by the organic film or the like, and further improvement in reliability can be expected.

  In addition to organic films, color filters can be stacked on top of them, and these organic films and color filters can be formed on the charge detection section to prevent light from entering the detection section. Generation of noise components generated in the detection unit due to incidence can also be suppressed.

  As described above, according to the present invention, it is possible to prevent a decrease in output due to an increase in the capacitance of the charge detection unit, further improve the reliability compared with a highly reliable solid-state imaging device that leaves a conventional protective film, and further to the output unit. By improving the light-shielding property, it is possible to realize a high-performance solid-state imaging device with reduced output noise components.

FIG. 1 is a diagram for explaining a solid-state imaging device according to Embodiment 1 of the present invention. FIGS. 1A and 1B are layout patterns of impurity layers and electrodes in a charge detection unit of the solid-state imaging device. FIG. FIG. 2 is a cross-sectional view illustrating the CCD solid-state imaging device according to the first embodiment. FIG. 2A is a cross-sectional view taken along the line IIa-II in FIGS. FIG. 2B shows the structure of the cross section taken along the line IIb-II of FIG. 1A and FIG. 1B (cross-sectional structure of the charge detection portion). FIG. 3 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the first embodiment illustrated in FIG. 1 in order of steps (FIGS. FIG. 4 is a cross-sectional view illustrating a CCD type solid-state imaging device according to Embodiment 2 of the present invention, and shows a structure corresponding to a cross section taken along line IIa-IIa in FIGS. FIG. 5 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the second embodiment in the order of steps (FIGS. (A) to (g)). FIG. 6 is a cross-sectional view showing the contact hole forming process in the order of steps (FIGS. (A) to (d)) in the method of manufacturing the solid-state imaging device of the second embodiment. FIG. 7 is a block diagram illustrating a schematic configuration example of an electronic information device using the solid-state imaging device according to Embodiment 1 or 2 as an imaging unit as Embodiment 3 of the present invention. FIG. 8 is a diagram for explaining a conventional CCD type solid-state imaging device. FIG. 8A schematically shows the entire configuration of the CCD type solid-state imaging device, and FIG. The cross-sectional structure of the charge detection part in a CCD type solid-state image sensor is shown. FIG. 9 is a plan view for explaining the layout pattern of the impurity layer and the electrode in the charge detection section of the conventional solid-state imaging device. FIG. 9A shows the separation pattern of the active region (impurity layer) and the gate electrode. Only the pattern, the N ⁺ impurity layer pattern, and the contact pattern are schematically shown, and FIG. 9B shows only the isolation pattern of the active region, the arrangement pattern of the N ⁺ impurity layer, and the pattern of the metal layer. FIG. 10 is a cross-sectional view for explaining a CCD solid-state imaging device to which such a countermeasure is taken. FIG. 10A is a cross-sectional view of the structure (charge) of the Xa-Xa line in FIGS. 9A and 9B. FIG. 10B shows the Xb-Xb line cross-sectional structure of FIG. 9A and FIG. 9B (cross-sectional structure of the charge detection unit). FIG. 11 is a cross-sectional view showing the manufacturing method of the conventional solid-state imaging device shown in FIG. 10 in the order of steps (FIGS. (A) to (e)). FIG. 12 is a cross-sectional view illustrating another conventional CCD solid-state imaging device. FIG. 13 is a cross-sectional view showing the manufacturing method of the conventional solid-state imaging device shown in FIG. 12 in the order of steps (FIGS. (A) to (e)).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a solid-state imaging device according to Embodiment 1 of the present invention. FIGS. 1A and 1B are layout patterns of impurity layers and electrodes in a charge detection unit of the solid-state imaging device. FIG.

  In other words, FIG. 1A shows the layout of the charge detection portion of the solid-state imaging device according to the first embodiment and the impurity layer in the vicinity thereof, and the polysilicon gate (gate electrode made of polysilicon) formed on the impurity layer. Shows the layout. FIG. 1B shows the layout of the impurity layer in the solid-state imaging device of Embodiment 1 and the impurity layer in the vicinity thereof, and the layout of the metal layer formed on the impurity layer.

  FIG. 2 is a cross-sectional view illustrating the CCD solid-state imaging device according to the first embodiment. FIG. 2A is a cross-sectional view taken along the line IIa-IIa in FIG. 1A and FIG. FIG. 2B shows the structure of the section taken along the line IIb-IIb in FIGS. 1A and 1B (cross-sectional structure of the charge detection section).

On the silicon substrate 1 (see FIG. 1), an N ⁻ impurity layer 17 serving as a channel region of the horizontal CCD 2 is formed. On the N ⁻ impurity layer 17, a second layer transfer electrode constituting the horizontal CCD is formed as a second layer transfer electrode. First layer gate electrodes 2a made of single layer polysilicon and second layer gate electrodes 2b made of second layer polysilicon are alternately arranged. The end side portion of the horizontal CCD 2 of the N ⁻ impurity layer 17 is connected to the N ⁺ impurity layer (reset drain impurity layer) 8 constituting the reset drain, and the N ⁺ impurity layer 8 and the N ⁻ impurity layer 17 are connected to each other. A polysilicon layer 9 constituting a reset gate is formed on the connection portion 17a via an insulating film (not shown).

Further, an N ⁺ impurity layer (detection part impurity layer) 6 constituting a charge detection part is formed in a part of the N ⁻ impurity layer 17 between the reset gate and the final transfer gate 2c, and the N ⁺ An N ⁻ impurity layer 18 constituting a transistor (output circuit transistor) in the output section is formed so as to be close to the impurity layer 6.

  Here, a polysilicon layer 20 serving as a gate electrode is formed on the transistor impurity layer 18 via an insulating film (not shown), and one end of the polysilicon layer 20 is located on the detection unit impurity layer 6. ing. Further, both side portions of the gate electrode of the transistor impurity layer 18 serve as source / drain regions, and contact holes 18a for connection to the upper metal wiring 18b are formed. On the reset drain impurity layer 8, a contact hole 8a for connecting the impurity layer to the upper metal layer 10 is formed. Note that a metal layer 5 is also formed on the transfer gate 2 constituting the horizontal CCD, but this metal layer is formed as a light shielding film and is not used as an electrical wiring layer. is there.

Further, the N ⁻ impurity layer 18, the channel N ⁻ impurity layer 17, and the reset drain impurity layer 8 constituting the transistor of the output part are formed by being separated by a field insulating film 19.

  Further, a metal lower insulating film 3 is formed on the field oxide film and the impurity layer so as to cover the entire surface. On the metal lower insulating film 3, a metal layer 5 as a light shielding film is a transfer electrode of the horizontal CCD. Further, metal layers 7 and 10 are formed as wirings.

The metal layer 7 is connected to the detection portion N ⁺ impurity layer 6 and the polysilicon layer 20 of the output transistor through a contact hole formed in the lower metal insulating film 3. The metal layer 10 is connected to the transistor impurity layer 8 through a contact hole formed in the lower metal insulating film 3.

  Further, a lower element protective film 11 and an upper element protective film 12 are formed on the entire surface of the substrate so as to cover these polysilicon layers 5, 7 and 10, and an on-chip organic material layer 13 is further formed thereon. An on-chip surface antireflection film 15 is formed on the surface. Here, the on-chip organic material layer 13 includes an on-chip color filter layer 14.

In the solid-state imaging device 100 according to the first embodiment, the lower element protection is performed in the rectangular region Ra having a certain size centered on the detection unit N ⁺ impurity layer 6 shown in FIGS. A cavity 16 is formed below the film 11.

  Next, a manufacturing method will be described.

  FIG. 3 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the first embodiment illustrated in FIG. 1 in order of steps (FIGS.

First, an N ⁻ impurity layer 17 serving as a charge transfer path, an N ⁻ impurity layer 8 serving as a channel region of a reset transistor, a detection unit N ⁺ impurity layer 6, and a reset drain N ⁺ impurity layer 8 are selectively formed on the silicon substrate 1. Then, the charge transfer part 2 is formed by two layers of polysilicon gates, and the reset gate electrode 9 for discharging the charge of the detection part to the reset drain is formed.

  Thereafter, an under-metal insulating film (silicon oxide film) 3 is formed on the entire surface, the transfer part upper metal layer 5 as a light shielding film, a metal wiring 7 for transmitting the potential of the detection part to the output transistor, and a reset drain metal wiring 10 is formed (FIG. 3A).

  In this manner, the metal wiring 7 constituting the charge detection unit and its peripheral portion are formed on the base structure 21 obtained by sequentially forming the impurity layer, the polysilicon layer, the metal under-insulating film, and the metal layer on the substrate. A resist film 11a having a planar pattern to cover is formed (FIG. 3B).

  About the resist used here, since the lower element protective film (silicon nitride film) 11 is formed with the resist attached later, a resist having a performance excellent in heat resistance is preferable. Further, this resist shape is reflected to form a cavity 16, and the cavity edge portion of the lower element protection film (silicon nitride film) 11 is etched using a further resist mask 12a, so that the resist film 11a to be formed is formed. The shape of the resist film is not such that the side surface of the resist film is nearly vertical like a conventional resist, and it is desirable that the side surface of the resist film be inclined depending on the focus conditions during exposure and the heat treatment conditions after development.

  Subsequently, the lower element protection film 11 is formed by a plasma CVD apparatus with the resist film 11a attached.

  As film formation conditions at this time, film formation is performed by plasma CVD processing at a lower temperature than in the past. Specifically, temperature 200-300 ° C., pressure 1.5-3.0 Torr, high-frequency RF power 500-1000 W, low-frequency RF power 100-700 W, SiH 4 gas flow rate 100-200 sccm, NH 3 gas flow rate 200-1000 sccm, N 2 Under the condition of a gas flow rate of 10,000 to 15000 sccm, a silicon nitride film as the lower element protection film 11 is grown to a thickness of 10 to 50 nm (FIG. 3C).

  Thereafter, in order to remove the resist film 11 a covered with the protective film 11, a resist mask 12 a is formed in order to remove a part of the protective film 11 by etching. Here, with respect to the resist opening A of the resist mask 12a, only one place is shown in FIG. 3D, but in practice, in order to facilitate the removal of the material in the cavity in the subsequent processing, FIG. As shown in b), resist openings A are provided at several locations on the metal layer.

Then, the lower element protection film (silicon nitride film) 11 exposed in the resist opening A is etched by plasma etching to form an opening 11c (FIG. 3D). The conditions at this time are the same as the etching process of the silicon nitride film in the conventional solid-state imaging device. That is, this etching process is performed at a pressure of 1000 to 2000 mtorr, an RF power of 750 to 1500 W, and using the used gas O ₂ · CF ₄ .

Thereafter, the resist mask 12a and the resist film 11a covered with the protective film 11 are removed together by plasma treatment with O ₂ and CF ₄ and etching treatment using an organic resist peeling solution (FIG. 3E). ). Here, both SiN etching and resist peeling use O ₂ · CF ₄ as a gas to be used, but SiN etching uses CF ₄ as the main gas, and resist peeling uses O ₂ as the main gas. A main gas containing a small amount of CF ₄ is used.

  Thereafter, a silicon nitride film 12 as an upper element protection film is formed by a low temperature plasma CVD process (FIG. 3F). The film formation conditions are the same as the film formation conditions of the silicon nitride film as the lower element protection film. However, it should be noted here that the processing at the time of forming the lower element protection film 11 is important. In relation to the temperature and the processing temperature at the time of forming the upper element protective film 12, the processing temperature at the time of forming the upper element protective film is the same as the processing temperature at the time of forming the lower element protective film, or It is necessary to process at a low temperature.

  This is because the deposition process is a low-temperature deposition CVD process, and the deposited silicon nitride film contains a considerable amount of hydrogen. This is because exposure to a temperature atmosphere may cause problems such as peeling of the formed film due to the influence of the release gas and the like.

  Then, the transparent organic material 13 which is an on-chip layer is applied and planarized, and then an organic material layer such as the color filter 14 is formed by spin coating. Further, a transparent organic material 15 that is an on-chip layer is formed thereon with a predetermined thickness in order to adjust the height (condensing height) of the microlens from the light receiving portion. For example, although the condensing height of the microlens varies depending on the number of pixels of the solid-state imaging device, the organic material is set so that the distance from the opening surface of the light receiving unit to the bottom of the microlens is about 3.0 to 7.0 μm. The film thickness of the layer 13 is adjusted.

Thereafter, a surface antireflection film 15 made of a material such as a silicon oxide film is also formed by low temperature plasma CVD. The film forming conditions at this time are a temperature of 200 to 250 ° C., a pressure of 1.5 to 3.5 Torr, an RF power of 150 to 300 W, a SiH ₄ .N ₂ O.N ₂ gas, and a film thickness of 10 to 50 nm.

  Here again, similarly to the above, the processing temperature at the time of forming the silicon oxide film 15 as the antireflection film is the same as or lower than the processing temperature at the time of forming the lower element protective film 11 and the upper element protective film 12. It is necessary to perform the film forming process.

  Unlike the conventional method for manufacturing a solid-state imaging device, in the method for manufacturing a solid-state imaging device according to Embodiment 1 of the present invention, it is not necessary to remove these organic films and antireflection films on the charge detection unit. It is possible to provide a moisture-proof effect and a light-shielding effect.

  In addition, since it is necessary to remove the organic film and the antireflection film for the electrode pad part for transmitting / receiving signals to / from the outside of the solid-state image sensor, these antireflections are also provided by the resist pattern only for the electrode pad part. The film 16, the organic film 14, the upper element protection film 12, and the lower element protection film 11 need to be removed by dry etching. The processing conditions are the same as those in the conventional method for manufacturing a solid-state imaging device.

  The color filter layer 14 is a portion located above the charge detection portion during photolithography processing when forming the color filter, because residues and the like remain in the subsequent dry etching processing and are difficult to remove completely. Has been removed.

  As described above, in the first embodiment, the protective films 11 and 12 are formed on the metal layer 7 constituting the charge detection unit through the cavity, and the on-chip layer (organic film) 13 as an upper layer is further formed. It is not necessary to remove the film, and even if all of them are left, problems such as an increase in capacity in the charge detection unit do not occur. As a result, the charge detection portion is not only covered with the protective films 11 and 12 of the silicon nitride film, but is also covered with the organic film 13 having good hygroscopicity.

  For this reason, the invaded moisture does not directly contact the protective films 11 and 12, but is once absorbed and contacted by the organic film 13 and the like, and further improvement in reliability can be expected.

  Further, not only the organic film 13 but also the color filter 14 is stacked thereon to form the organic film 13 and the color filter 14 on the charge detection section, thereby preventing light from entering the detection section. It is also possible to suppress the generation of noise components generated in the detection unit due to light incidence.

(Embodiment 2)
FIG. 4 is a cross-sectional view illustrating a CCD type solid-state imaging device according to Embodiment 2 of the present invention, and shows a structure corresponding to a cross section taken along line IIa-IIa in FIGS.

  The solid-state imaging device 100a according to the second embodiment has a structure that is hardly different from the solid-state imaging device 100 according to the first embodiment, but the manufacturing method is different from the manufacturing method of the solid-state imaging device according to the first embodiment. Due to the difference in the manufacturing method, there are some structural differences from the solid-state imaging device 100 of the first embodiment.

  That is, in the method for manufacturing the solid-state imaging device according to the second embodiment, the materials used for forming the cavity 16 are different from those in the method for manufacturing the solid-state imaging device according to the first embodiment. That is, in the method for manufacturing the solid-state imaging device of the first embodiment, the resist film is used. However, in the method for manufacturing the solid-state imaging device of the second embodiment, a silicon oxide film is used. For this reason, in the solid-state imaging device according to the second embodiment, the surface of the cavity has an uneven structure reflecting the base shape. Further, the solid-state imaging device of the second embodiment is different from that of the first embodiment in that an etching stop film 4 for removing the material in the cavity is formed.

  Next, a manufacturing method will be described.

  FIG. 5 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the second embodiment in the order of steps (FIGS. (A) to (g)).

First, on a silicon substrate 1, N a charge transfer path ^- selective impurity layer 17, the detection unit N ⁺ impurity layer 6, a reset drain N ⁺ impurity layer 8 ^- the impurity layer 17, N be the channel region of the reset transistor Then, a charge transfer gate 2 is formed by a two-layer polysilicon gate, and a reset gate electrode 9 for discharging the charge of the charge detection portion to the reset drain is formed.

  Thereafter, an under-metal insulating film (interlayer insulating film under the metal) 3 is formed on the entire surface, and an etching stop film 4 is formed thereon (FIG. 5A).

Note that a silicon oxide film or a BPSG film is usually used for the interlayer insulating film under the metal. Further, here, after the formation of the interlayer insulating film under the metal, the silicon nitride film 4 as an etching stop film is formed, but since the formation of the silicon nitride film 4 is before the formation of the metal layer, Treatment at a high temperature of 400 ° C. or higher is also possible. For example, in a normal low pressure CVD (thermal CVD) apparatus, in a low pressure CVD thermal diffusion furnace, a temperature of 750 to 900 ° C., a use gas SiH ₂ Cl _2, NH ₃ and N ₂ , and a film thickness of 20 to 50 nm. A silicon nitride film is formed.

  In this state, a contact hole for connection between the metal wiring and each gate electrode or diffusion layer is formed.

  Note that in these steps, if the contact hole formation process includes taper etching for reducing the contact step, the silicon nitride film 4 becomes an obstacle to wet etching. It is necessary to perform taper processing etching.

  FIG. 6 shows steps (FIGS. (A) to (d)) for explaining a case where taper etching for reducing a contact step is performed in the contact hole formation process.

More specifically, on the silicon substrate 1, the charge transfer path to become N ^- impurity layer 17, a channel region of the reset transistor N ^- impurity layer 17a, the impurity layer, such as detector N ⁺ impurity layer 6 is formed, After the polysilicon gates 2 and 9 are formed and the under-metal insulating film 3 is formed on the entire surface (FIG. 6A), a first resist mask 41 for contact formation is formed, and the under-metal is formed by a chemical solution such as HF. The insulating film 3 is wet etched (FIG. 6B). As a result, a hole 3a having an inclined side wall is formed in the lower portion of the opening 41a of the resist mask 41 in the lower metal insulating film 3 (FIG. 6B). After removing the first resist mask 41, a silicon nitride film 4 is formed on the entire surface (FIG. 6C).

  Further, a second resist mask 42 for contact formation is formed on the silicon nitride screen 41, and contact holes 3a are formed in the silicon nitride film 41 and the lower metal insulating film 3 by dry etching (FIG. 6D). ).

  By such taper etching for reducing the contact step, the cross-sectional shape of the contact hole and the shape of the upper end corner of the contact hole can be gradually inclined.

Next, a metal layer 5 on the transfer section as a light shielding film, a metal wiring 7 for transmitting the potential of the detection section to the output transistor, and a reset drain metal wiring 10 are formed, and the metal wiring 7 constitutes a charge detection section. Connected to the N ⁺ impurity layer 6, the reset drain metal wiring 10 is connected to the N ⁺ impurity layer 8 (FIG. 5B).

  Thereafter, a sacrificial layer for forming the cavity 16 is formed. In the second embodiment, first, the silicon oxide film 33 is formed by the low temperature plasma CVD process, the metal layer 5, the metal wiring 7, and the reset drain metal wiring. 10 is formed to cover 10.

The silicon oxide film 33 is formed using SiH ₄ .N ₂ O.N ₂ gas under conditions of a temperature of 250 to 400 ° C., a pressure of 1.5 to 3.5 Torr, and an RF power of 150 to 300 W. It carries out on the conditions of 300-700 nm.

Further, a cavity forming resist pattern 34 is formed on the silicon oxide film 33, and the cavity silicon oxide film 33 is etched by plasma etching. As the etching conditions, a pressure of 150 to 400 mtorr, an RF power of 1000 to 1500 W, and a working gas CF ₄ · CHF ₃ · Ar are used. Here again, as in the first embodiment, since the silicon nitride film 11 formed on the silicon oxide film 33 later is removed, the cross-sectional shape of the cavity forming film (silicon oxide film) 33a is inclined as much as possible. It is desirable to have a shape (tapered shape depending on plasma etching conditions).

Next, a silicon nitride film 11 as a first protective film layer is formed by a low temperature plasma CVD process. The film forming conditions are as follows: temperature 250-400 ° C., pressure 1.5-3.0 Torr, high-frequency RF power 500-1000 W, low-frequency RF power 100-700 W, SiH ₄ gas flow rate 100-200 sccm, NH ₃ gas flow rate 200- The conditions are 1000 sccm, N ₂ gas flow rate of 10,000 to 15000 sccm, and film thickness of 10 to 50 nm.

  Thereafter, in order to remove the silicon oxide film 33a on the lower side of the silicon nitride film 11, a resist mask 35 for removing a part of the first protective film 11 is formed (FIG. 5E).

  Here, with respect to the opening pattern 35a of the resist mask 35, only one opening is shown in the cross-sectional view of FIG. 5B, but actually, the opening pattern 35a is shown in FIG. As shown in FIG. 1B, openings A are provided at several locations on the metal wiring.

Then, the silicon nitride film 11 as the first protective film exposed to the resist opening is removed by plasma etching. The conditions are the same as in the conventional example described above, and the conditions of pressure 1000 to 2000 mtorr, RF power 750 to 1500 W, and used gas O ₂ · CF ₄ are used.

Thereafter, the resist mask 35 is removed by O ₂ plasma treatment or organic peeling solution, and the silicon oxide film 33a inside the cavity is removed by chemical treatment (FIG. 5F). The chemical solution used at this time is desirably removed with a buffered HF solution (BHF etchant) so as to minimize damage to the metal layer.

  The BHF etchant is a mixed chemical obtained by diluting hydrogen fluoride, ammonium fluoride, and a fluorosurfactant with water. Although it has a slight etching property for an aluminum-based film as a wiring material, the etching of the aluminum film is hardly problematic because of an etching rate difference from the cavity inner film to be etched.

  Although not shown in the above description of the prior art and the embodiment, the conventional solid-state imaging device and the solid-state imaging device of the present embodiment use a three-layer structure wiring including an aluminum alloy as the wiring. Of the layers of the structure, the Al—Cu layer as an intermediate layer is etched by a BHF etchant.

  However, even if the aluminum film is etched and receded, it is considered that there is no particular problem in device operation as long as the thickness is up to 100 nm.

  Similarly to the first embodiment, the second protective film silicon nitride film 12, the on-chip organic material layer 13, the color filter layer 14, and the silicon oxide film 15 that is an antireflection film are formed, and the solid-state imaging device of the second embodiment. Complete the structure.

  Hereinafter, the features of the first and second embodiments of the present invention will be described in comparison.

  The manufacturing method of the solid-state imaging device according to the first embodiment is a manufacturing method in which an organic resist is embedded as a sacrificial layer in the cavity to be formed. The manufacturing method of the solid-state imaging device according to the second embodiment includes the cavity to be formed. In this method, a silicon oxide film is embedded as a sacrificial layer.

In Embodiment 1, using a resist as a sacrificial layer as described above makes the manufacturing method simple, but setting the processing temperature at the time of forming the protective film twice after forming the sacrificial layer as high as possible. However, although it is suitable for film formation, the heat resistance performance of the organic resist is required in that case, and the organic resist having high heat resistance is very expensive. Further, the conventional removal of the organic resist has been performed by O ₂ plasma treatment and an organic peeling liquid. However, in the first embodiment, the O ₂ plasma is very difficult to hit the resist in the cavity, and the peeling is an organic peeling liquid. There is a demerit that you must rely on.

  On the other hand, in the second embodiment, there is no concern as in the first embodiment, but there is a demerit of the recession of aluminum by the BHF treatment and an increase in the process for forming the etching stop film.

  As shown in the description of the second embodiment, when the contact taper process is performed, the contact patterning / etching process needs to be performed twice.

  In consideration of the merits and demerits as described above, it is necessary to select the manufacturing method of the first and second embodiments from the viewpoint of the manufacturing equipment to be used and the cost.

  Hereinafter, a metal wiring having a multilayer structure of three or more layers that can be used in the embodiment of the present invention will be briefly described.

  The role (purpose) and materials used for each layer are as follows.

  That is, for example, an intermediate layer of a multilayer wiring having a three-layer structure is a wiring layer body portion, and a film similar to a conventional single-layer metal wiring is used. For example, in the above embodiment, an Al—Cu layer can be used as the intermediate layer, but a pure Al layer, an Al—Si layer, or the like can also be used.

  The lower layer is formed for the purpose of preventing the main body metal (intermediate layer) of the wiring layer and the material such as silicon of the substrate that is in contact with the contact from reacting by a subsequent heat treatment or the like. The layer can be used as a lower layer (underlying metal) and is also called a barrier metal layer. For example, a TiN layer can be used as the base metal, but a Ti layer, a TiW layer, a W layer, or the like can also be used. Further, the lower barrier metal layer itself is often composed of two layers (Ti / TiN) of an extremely thin Ti layer and a TiN layer.

  Furthermore, the upper layer is provided as an antireflection film because the intermediate metal layer is an Al-based metal layer and thus becomes an optically highly reflective layer.

  In other words, when the wiring layer has a single-layer structure consisting of only the metal used as the intermediate layer of the multilayer structure, the underlying metal layer (aluminum) of this single-layer structure is formed when a subsequent metal pattern (upper metal pattern) is formed. Under the influence of reflection from the system film), a fine pattern is cut off, or in a device having a high step such as a CCD, pattern constriction occurs at the step portion. Therefore, the upper layer of the multilayer wiring having the three-layer structure is provided as an antireflection film layer in order to prevent the adverse effect of reflection from the underlying layer when the upper pattern as described above is formed.

  Furthermore, for the upper layer, the same refractory metal layer as the lower layer is often used as the upper layer because of the simplicity of the film forming process between the upper layer and the lower layer. In the present embodiment, a TiN layer can be used as the upper layer, but TiW or the like can also be used. However, since the pure Ti layer and the pure W layer are considered to have a large reflection, the use conditions may be limited.

Furthermore, although not specifically described in the first and second embodiments, a digital camera such as a digital video camera or a digital still camera using at least one of the solid-state imaging devices of the first and second embodiments as an imaging unit. An electronic information device having an image input device, such as an image input camera, a scanner, a facsimile machine, or a camera-equipped mobile phone, will be briefly described below.
(Embodiment 3)
FIG. 7 is a block diagram illustrating a schematic configuration example of an electronic information device using the solid-state imaging device according to any one of Embodiments 1 and 2 as an imaging unit as Embodiment 3 of the present invention.

  An electronic information device 90 according to Embodiment 3 of the present invention shown in FIG. 7 includes at least one of the solid-state imaging devices according to Embodiments 1 and 2 of the present invention as an imaging unit 91 that captures a subject. A memory unit 92 such as a recording medium for recording data after high-definition image data obtained by photographing by such an image pickup unit is subjected to predetermined signal processing for recording, and predetermined signal processing for displaying the image data A display unit 93 such as a liquid crystal display device that displays on a display screen such as a liquid crystal display screen, and a communication unit 94 such as a transmission / reception device that performs communication processing after performing predetermined signal processing on the image data for communication. And an image output unit 95 that prints (prints) image data and outputs (prints out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device, a method for manufacturing the same, and an electronic information device, in which the metal wiring layer constituting the charge detection unit is altered without increasing the capacity due to the metal wiring layer constituting the charge detection unit. A solid-state imaging device that can prevent corrosion and thereby convert signal charges into signal voltages with high and high reliability, a manufacturing method thereof, and an electronic information device using such a solid-state imaging device Obtainable.

1 Silicon substrate 2 Horizontal CCD
2a 1st layer gate electrode 2b 2nd layer gate electrode 3 Under metal insulating film 5, 7, 10 Metal layer 6 Detection part impurity layer 8 Reset drain impurity layer 8a, 18a Contact hole 9 Polysilicon layer 6 Detection part impurity layer 10 Upper layer Metal layer 11 Lower element protective film 12 Upper element protective film 13 On-chip organic material layer 15 On-chip surface antireflection film 14 On-chip color filter layer 16 Cavity 17 Channel N ⁻ Impurity layer 18 N ⁻ Impurity layer 18b Upper layer metal Wiring 19 Field insulating film 20 Polysilicon layer 90 Electronic information equipment 91 Imaging unit 92 Memory unit 93 Display unit 94 Communication unit 95 Image output unit 100, 100a Solid-state imaging device Ra Rectangular area

Claims (15)

A plurality of photoelectric conversion regions provided on a semiconductor substrate, a charge transfer unit that transfers signal charges obtained by photoelectric conversion in the plurality of photoelectric conversion regions, and a charge that converts the transferred signal charges into a signal voltage A solid-state imaging device having a detection unit and an output circuit that amplifies the signal voltage and outputs it as a pixel signal to the outside,
A solid-state imaging device having a hollow structure in which a hollow region is interposed between a conductive layer constituting the charge detection section and an insulating layer covering the conductive layer. The solid-state imaging device according to claim 1,
The solid-state imaging device according to claim 1, wherein the conductive layer forming the hollow structure is a metal layer. The solid-state imaging device according to claim 2,
The insulating layer that covers the metal layer, which is a conductive layer that forms the hollow structure, is a solid-state imaging device that includes two protective films. The solid-state imaging device according to claim 3,
The two-layer protective film is a solid-state imaging device, both of which are silicon nitride films. The solid-state imaging device according to claim 1,
A solid-state imaging device in which a film having an etching resistance to the etching process is formed as an etching stop film used in the etching process for forming the hollow region below the conductive layer forming the hollow structure . The solid-state imaging device according to claim 5,
The solid-state imaging device, wherein the film having etching resistance to the etching process is a silicon nitride film. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein a transparent organic material, a color filter material, and an antireflection film layer are laminated on the insulating layer forming the hollow structure so as to cover the hollow region. The solid-state imaging device according to claim 7,
The transparent organic material, the color filter material, and the antireflection film layer are each an on-chip material layer. A plurality of photoelectric conversion regions provided on a semiconductor substrate, a charge transfer unit that transfers signal charges obtained by photoelectric conversion in the plurality of photoelectric conversion regions, and a charge that converts the transferred signal charges into a signal voltage A method of manufacturing a solid-state imaging device having a detection unit and an output circuit that amplifies the signal voltage and outputs the signal voltage to the outside as a pixel signal,
Forming a conductive layer constituting the charge detection unit;
Forming a sacrificial layer for forming a hollow region on the conductive layer so as to cover the conductive layer;
Forming an insulating layer to cover the sacrificial layer;
And a step of removing the sacrificial layer so that a hollow region is formed between the conductive layer and the insulating layer. In the manufacturing method of the solid-state image sensing device according to claim 9,
Forming an insulating layer to cover the sacrificial layer,
Forming a first protective film to cover the sacrificial layer;
Selectively removing a portion of the first protective film located on the edge portion of the sacrificial layer to form a protective film opening;
Removing the sacrificial layer by exposing it to an etchant through the protective film opening;
Forming a second protective film on the first protective film so as to close the protective film opening. In the manufacturing method of the solid-state image sensing device according to claim 10,
The method for manufacturing a solid-state imaging device, wherein the sacrificial layer is a photoresist film. In the manufacturing method of the solid-state image sensing device according to claim 11,
In the step of selectively removing a portion of the first protective film located on the edge portion of the sacrificial layer to form a protective film opening, selective etching of the first protective film is performed using a photoresist mask. Done,
A method for manufacturing a solid-state imaging device, wherein the photoresist mask used in the selective etching of the first protective film is also removed when the photoresist film as the sacrificial layer is removed. In the manufacturing method of the solid-state image sensing device according to claim 10,
The method for manufacturing a solid-state imaging device, wherein the sacrificial layer is a silicon oxide film. In the manufacturing method of the solid-state image sensing device according to claim 13,
Before forming a conductive layer constituting the charge detection portion, including a step of forming a film having etching resistance to etching of the sacrificial layer as a base layer of the conductive layer,
In the etching process for removing the sacrificial layer, a method for manufacturing a solid-state imaging device, wherein the film having etching resistance is used as an etching stopper layer. An electronic information device having an imaging unit for imaging a subject,
The electronic information device, wherein the imaging unit is a solid-state imaging device according to claim 1.

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