JP2010232284A - Solid state imaging apparatus, method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image quality of a picked-up image by suppressing generation of a dark current due to stress generated by metal wirings in a peripheral region. <P>SOLUTION: Insulating films have stress relaxation layers 600 (air layer) formed in a boundary region KA positioned between an optical black pixel region BA and the peripheral region SA to relax stress generated by a plurality of metal wirings HW. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus. In particular, according to the present invention, peripheral circuit elements are provided in a peripheral region located around a pixel region where a plurality of pixels are arranged, and a multilayer wiring layer is provided above the pixel region and the peripheral region. The present invention relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device.

  Electronic devices such as digital video cameras and digital still cameras include solid-state imaging devices. For example, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor is included as a solid-state imaging device. Moreover, it has a CCD (Charge Coupled Device) type image sensor as a solid-state imaging device.

  In the solid-state imaging device, a plurality of pixels are provided in the pixel region on the imaging surface. In each of the plurality of pixels, a photoelectric conversion unit is provided so as to generate signal charges by receiving incident light and performing photoelectric conversion. For example, a photodiode is formed as the photoelectric conversion unit.

  In a solid-state imaging device such as a CMOS type image sensor, peripheral circuit elements are provided in a peripheral region located around the pixel region on the imaging surface. A multilayer wiring layer is provided above the pixel region and the peripheral region. In the multilayer wiring layer, a plurality of insulating films are laminated, and a metal wiring is provided between the plurality of insulating films. In this multilayer wiring layer, a diffusion preventing layer for preventing diffusion of the metal material constituting the metal wiring is formed (for example, see Patent Document 1).

  Further, in the above pixel region, among the plurality of pixels, an effective pixel through which incident light is transmitted to the light receiving surface is provided in the effective pixel region located in the central portion. At the same time, in the pixel region, a light-shielding pixel that shields incident light from above the light receiving surface is provided in an optical black (OPB) pixel region located in the peripheral portion of the effective pixel region. The pixel signal obtained from the light-shielded pixel is used as a black level reference signal. For example, the pixel signal obtained from the effective pixel is subjected to differential processing with the pixel signal obtained from the light-shielded pixel, and noise components due to dark current are removed (see, for example, Patent Document 2).

  In addition, in the solid-state imaging device, hydrogenation processing is performed in order to suppress generation of noise components due to dark current (see, for example, Patent Document 3 and Patent Document 4).

JP 2008-103572 A JP 2006-229799 A JP 2004-165236 A JP 2003-229556 A

  The metal wiring included in the multilayer wiring layer may be formed at different densities between the pixel region and the peripheral region. In general, the metal wiring is formed at a higher density in the peripheral region than in the pixel region. In particular, in a CMOS image sensor used in a digital single-lens reflex camera, the signal dose in the pixel area is large, and the width of the metal wiring in a portion where signal lines are bundled in the peripheral area is wide. For this reason, the metal wiring has a large density difference between the pixel region and the peripheral region.

  In the multilayer wiring layer, the metal material constituting the metal wiring has a larger stress (stress) than the insulating material constituting the insulating film. For this reason, among the plurality of pixels arranged in the pixel region, in a portion of the pixel close to the peripheral region, dark current may be noticeably generated due to stress due to the metal wiring in the peripheral region.

  In addition, in the above-described hydrogenation treatment, it may be difficult to effectively prevent the generation of noise components due to dark current because the metal wiring inhibits hydrogen permeation.

  Therefore, in the solid-state imaging device, the image quality of the captured image may deteriorate due to the generation of noise components due to dark current.

  Therefore, the present invention provides a solid-state imaging device, a manufacturing method thereof, and an electronic device that can improve the image quality of a captured image.

  In the solid-state imaging device of the present invention, a plurality of pixels that receive incident light on the light receiving surface and generate signal charges are provided in a pixel region, and a peripheral circuit element is provided in a peripheral region located around the pixel region. A semiconductor substrate, and a wiring layer in which a plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films, The insulating film is provided with a stress relieving layer for relieving stress due to the metal wiring in a portion located between the pixel region and the peripheral region.

  In the solid-state imaging device of the present invention, a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region, and a peripheral circuit element is provided in a peripheral region located around the pixel region. A semiconductor substrate provided; and a wiring layer in which a plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films. The plurality of pixels include an effective pixel formed above the light receiving surface so that the incident light is transmitted, and a light shielding pixel formed above the light receiving surface so that the incident light is blocked. The pixel region is located in a central portion of the pixel region, and is located in an effective pixel region in which the effective pixel is provided, and in the peripheral region of the effective pixel region in the pixel region. The shading picture The insulating film is provided with a stress relieving layer for relieving stress caused by the plurality of metal wirings in a portion located between the effective pixel region and the peripheral region. It has been.

  In the electronic device of the present invention, a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region, and a peripheral circuit element is provided in a peripheral region located around the pixel region. A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films. The insulating film is provided with a stress relieving layer for relieving stress due to the metal wiring at a portion located between the pixel region and the peripheral region.

  In the electronic device of the present invention, a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region, and a peripheral circuit element is provided in a peripheral region located around the pixel region. A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films. The plurality of pixels include an effective pixel formed above the light receiving surface so that the incident light is transmitted, and a light shielding pixel formed above the light receiving surface so that the incident light is blocked. The pixel region is located in a central portion of the pixel region, the effective pixel region in which the effective pixel is provided, and the pixel region is located in a peripheral portion of the effective pixel region, The shading pixel is The insulating film is provided with a stress relieving layer for relieving stress caused by the plurality of metal wirings in a portion located between the effective pixel region and the peripheral region. ing.

  In the method for manufacturing a solid-state imaging device according to the present invention, a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region of a semiconductor substrate, and are positioned around the pixel region in the semiconductor substrate. Forming a peripheral circuit element in a peripheral region, and forming a wiring layer in which a metal wiring is interposed between a plurality of stacked insulating films above the pixel region and the peripheral region; In the wiring layer forming step, a stress relaxation layer that relaxes stress due to the plurality of metal wirings is formed in a portion of the insulating film located between the pixel region and the peripheral region.

  According to the method for manufacturing a solid-state imaging device of the present invention, a plurality of pixels that receive incident light on a light receiving surface and generate a signal charge are provided in a pixel region of a semiconductor substrate, and a periphery that is positioned around the pixel region in the semiconductor substrate An element forming step of providing a peripheral circuit element in the region; and a wiring layer forming step of forming a wiring layer in which metal wiring is interposed between the plurality of stacked insulating films above the pixel region and the peripheral region. The element forming step forms, as the plurality of pixels, an effective pixel that transmits the incident light to the light receiving surface and a light-shielded pixel that blocks the incident light above the light receiving surface. In the pixel forming step, the effective pixel is formed in the effective pixel region located in the central portion of the pixel region, and the effective pixel region is surrounded by the pixel region. The light-shielding pixel is formed in an optical black pixel region located in a portion, and in the wiring layer forming step, a stress caused by the metal wiring in a portion located between the effective pixel region and the peripheral region in the insulating film. A stress relieving layer is provided to relieve stress.

  In the present invention, in the insulating film, a stress relaxation layer is formed in a portion located between the pixel region or the effective pixel region and the peripheral region to relieve stress due to the plurality of metal wirings.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device which can improve the image quality of a captured image, its manufacturing method, and an electronic device can be provided.

FIG. 1 is a configuration diagram showing a configuration of a camera 40 in Embodiment 1 according to the present invention. FIG. 2 is a diagram schematically illustrating the configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing the main part of the pixel P provided in the pixel area PA in the embodiment according to the present invention. FIG. 4 is a diagram illustrating a detailed configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating a detailed configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 7 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 8 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 9 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 10 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 11 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. FIG. 12 is a diagram illustrating a main part of the solid-state imaging device 1b according to the second embodiment of the present invention. FIG. 13 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1b in the second embodiment according to the present invention. FIG. 14 is a diagram illustrating a main part provided in each step of the method of manufacturing the solid-state imaging device 1b according to the second embodiment of the present invention. FIG. 15 is a diagram illustrating a main part of the solid-state imaging device 1c according to the third embodiment of the present invention. FIG. 16 is a diagram illustrating a main part of the solid-state imaging device 1c according to the third embodiment of the present invention. FIG. 17 is a view showing a modification of the third embodiment according to the present invention. FIG. 18 is a diagram illustrating a main part of the solid-state imaging device 1d according to the fourth embodiment of the present invention. FIG. 19 is a diagram illustrating a main part of the solid-state imaging device 1d according to the fourth embodiment of the present invention. FIG. 20 is a diagram illustrating a main part of the solid-state imaging device 1e according to the fifth embodiment of the present invention. FIG. 21 is a diagram illustrating a main part of the solid-state imaging device 1f according to the sixth embodiment of the present invention. FIG. 22 is a diagram showing a configuration of the pixel P in the embodiment according to the invention.

  Embodiments of the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. Embodiment 1 (in the case of a plurality of stress relieving layers)
2. Embodiment 2 (when the stress relaxation layer has an air gap structure)
3. Embodiment 3 (when there is a single stress relieving layer)
4). Embodiment 4 (when there is a stress relaxation layer between the effective pixel region and the OPB pixel region)
5). Embodiment 5 (when the widths of the plurality of stress relaxation layers are different from each other)
6). Embodiment 6 (when the widths of the plurality of stress relaxation layers are different from each other)
7). Other

<1. Embodiment 1>
[A] Device Configuration (1) Main Configuration of Camera FIG. 1 is a configuration diagram showing the configuration of the camera 40 in Embodiment 1 according to the present invention.

  As shown in FIG. 1, the camera 40 includes a solid-state imaging device 1, an optical system 42, a control unit 43, and a signal processing circuit 44. Each part will be described sequentially.

  The solid-state imaging device 1 receives incident light (subject image) H incident via the optical system 42 on the imaging surface PS and photoelectrically converts the signal charge to generate raw data, and then outputs raw data. Here, the solid-state imaging device 1 is driven based on a control signal output from the control unit 43.

  The optical system 42 is disposed so as to collect incident light H from an incident subject image onto the imaging surface PS of the solid-state imaging device 1.

  The control unit 43 outputs various control signals to the solid-state imaging device 1 and the signal processing circuit 44, and controls operations of the solid-state imaging device 1 and the signal processing circuit 44.

The signal processing circuit 44 is configured to generate a digital image for the subject image by performing signal processing on the data output from the solid-state imaging device 1.
(2) Main Configuration of Solid-State Imaging Device The overall configuration of the solid-state imaging device 1 will be described.

  FIG. 2 is a diagram schematically illustrating the configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. FIG. 2 is a schematic plan view of the solid-state imaging device 1.

  The solid-state imaging device 1 according to the present embodiment is a CMOS color image sensor. As shown in FIG. 2, a pixel area PA and a peripheral area SA are provided on the imaging surface PS of the substrate 101. The substrate 101 is a semiconductor substrate made of silicon, for example.

(2-1) Pixel Area The pixel area PA will be described.

  As shown in FIG. 2, the pixel area PA has a rectangular shape, and is provided with pixels P, row control lines VL, and column signal lines HL.

  In the pixel area PA, as shown in FIG. 2, a plurality of pixels P are arranged in each of the horizontal direction x and the vertical direction y. That is, the pixels P are arranged in a matrix.

  FIG. 3 is a circuit diagram showing the main part of the pixel P provided in the pixel area PA in the embodiment according to the present invention.

  As shown in FIG. 3, the pixel P provided in the pixel area PA includes a photodiode 21, a transfer transistor 22, an amplification transistor 23, a selection transistor 24, and a reset transistor 25. That is, the pixel P includes a photodiode 21 that receives incident light on the light receiving surface and generates a signal charge, and a pixel transistor that performs an operation of reading the signal charge from the photodiode 21.

  In the pixel P, the photodiode 21 generates and accumulates signal charges by receiving incident light on the light receiving surface and performing photoelectric conversion. As shown in FIG. 3, the photodiode 21 is connected to the floating diffusion FD via the transfer transistor 22, and the accumulated signal charge is transferred as an output signal by the transfer transistor 22.

  In the pixel P, as shown in FIG. 3, the transfer transistor 22 is provided so as to be interposed between the photodiode 21 and the floating diffusion FD. The transfer transistor 22 transfers the signal charge accumulated in the photodiode 21 as an output signal to the floating diffusion FD when the transfer pulse TRG is applied to the gate.

  In the pixel P, as shown in FIG. 3, the amplification transistor 23 has a gate connected to the floating diffusion FD, and is configured to amplify an output signal output via the floating diffusion FD. Here, the amplification transistor 23 is connected to the column signal line HL via the selection transistor 24. When the selection transistor 24 is turned on, the amplification transistor 23 is connected to the constant current source I connected to the column signal line HL. Configure source followers between them.

  In the pixel P, the selection transistor 24 is configured such that the selection pulse SEL is supplied to the gate, as shown in FIG. The selection transistor 24 selects a pixel from which a signal is read out in units of rows, and is turned on when a selection pulse SEL is supplied. In the ON state, as described above, the amplification transistor 23 and the constant current source I constitute a source follower, and a voltage that is linked to the voltage of the floating diffusion FD is output to the column signal line HL.

  In the pixel P, the reset transistor 25 is configured such that a reset pulse RST is supplied to the gate, as shown in FIG. Further, they are connected so as to be interposed between the power supply Vdd and the floating diffusion FD. The reset transistor 25 resets the potential of the floating diffusion FD to the potential of the power supply Vdd when the reset pulse RST is supplied to the gate.

  The pixels P are sequentially selected and driven in units of horizontal lines (pixel rows) by supplying various pulse signals from the peripheral circuits provided in the peripheral area SA via the row control lines VL.

  In the pixel area PA, the row control line VL is electrically connected to each of a plurality of pixels P arranged in the horizontal direction x in the pixel area PA, as shown in FIG. A plurality of row control lines VL are arranged in the vertical direction y so as to correspond to the plurality of pixels P arranged in the vertical direction y. That is, the row control line VL is arranged for each row of the pixels P provided in the pixel area PA.

  In the pixel area PA, the column signal line HL is electrically connected to each of a plurality of pixels P arranged in the vertical direction y in the pixel area PA, as shown in FIG. A plurality of column signal lines HL are arranged in the horizontal direction x so as to correspond to the plurality of pixels P arranged in the horizontal direction x. That is, the column signal line HL is arranged for each column of the pixels P provided in the pixel area PA.

  As shown in FIG. 2, the pixel area PA of the present embodiment includes an effective pixel area YA and an optical black pixel area BA.

  As shown in FIG. 2, the effective pixel area YA is located at the center of the pixel area PA. In the effective pixel area YA, the effective pixel YP is provided as the pixel P. Although details will be described later, among the plurality of pixels P, the effective pixel YP is formed above the light receiving surface so that incident light incident on the imaging surface PS of the substrate 101 is transmitted to the light receiving surface.

  As shown in FIG. 2, the optical black pixel area BA is located in the peripheral portion of the effective pixel area YA in the pixel area PA. In the optical black pixel area BA, a light shielding pixel BP is provided as the pixel P. Although details will be described later, the light-shielding pixel BP is formed so that incident light incident on the imaging surface PS of the substrate 101 is shielded above the light-receiving surface.

  Further, as shown in FIG. 2, the optical black pixel area BA is provided with a stress relieving layer 600 at a boundary portion located between the optical black pixel area BA and the surrounding peripheral area SA. As shown in FIG. 2, the stress relieving layer 600 is formed so as to draw a rectangle around the pixel area PA. As will be described in detail later, a multilayer wiring layer (not shown) in which metal wiring is interposed between insulating films is provided above the pixel area PA and the peripheral area SA. It is provided to relieve stress due to wiring.

(2-2) Peripheral Area The peripheral area SA will be described.

  As shown in FIG. 2, the peripheral area SA is located around the pixel area PA.

  In the peripheral area SA, a peripheral circuit for processing the signal charge generated in the pixel P is provided. Here, for example, a row scanning circuit 13, a column circuit 14, a column scanning circuit 15, an output circuit 17, and a timing control circuit 18 are provided as peripheral circuits.

  The row scanning circuit 13 includes a shift register (not shown), and is configured to selectively drive the pixels P in units of rows. Here, as shown in FIG. 2, in the row scanning circuit 13, one end of each of the plurality of row control lines VL is electrically connected, and the pixel region PA is connected to each other through each of the row control lines VL. The plurality of arranged pixels P are scanned in row units. Specifically, the row scanning circuit 13 outputs various pulse signals such as a reset pulse signal and a transfer pulse signal to each pixel P via the row control line VL to drive the pixel P.

  The column circuit 14 is configured such that one end of each of the plurality of column signal lines HL is electrically connected, and signal processing is performed on a signal read from the pixel P in units of columns. Here, the column circuit 14 includes an ADC (analog-digital conversion circuit) 400 and performs an A / D conversion operation for converting an analog signal output from the pixel P into a digital signal. Specifically, a plurality of ADCs 400 are provided in the horizontal direction x so as to correspond to the columns of the plurality of pixels P arranged in the horizontal direction x in the pixel area PA. The plurality of ADCs 400 are electrically connected to the plurality of column signal lines HL provided for each column of the pixels P, and perform an A / D conversion operation on the signals output for each column of the pixels P. To do.

  The column scanning circuit 15 includes a shift register (not shown), and is configured to select a column of the pixels P and output a digital signal from the column circuit 14 to the horizontal output line 16. As shown in FIG. 2, the column scanning circuit 15 is electrically connected to a plurality of ADCs 400 constituting the column circuit 14, and a signal read from each pixel P via the column circuit 14 is in the horizontal direction x. Are sequentially output to the horizontal output line 16.

  The output circuit 17 includes, for example, an amplifier (not shown). The digital signal output by the column scanning circuit 15 is subjected to signal processing such as amplification processing and then output to the outside as raw data.

  The timing control circuit 18 generates various timing signals and outputs them to the row scanning circuit 13, the column circuit 14, and the column scanning circuit 15, thereby performing drive control for each unit.

  The raw data obtained as described above is processed by the signal processing circuit 44 shown in FIG. 1 to generate a digital image. In the present embodiment, difference processing is performed between the data obtained from the effective pixels YP and the data obtained from the light-shielded pixels BP to generate data from which noise components due to dark current are removed. Thereafter, a digital image is generated using the data from which the noise component due to the dark current has been removed.

(3) Detailed Configuration of Solid-State Imaging Device Detailed contents of the solid-state imaging device 1 according to the present embodiment will be described.

  4 and 5 are diagrams illustrating a detailed configuration of the solid-state imaging device 1 according to the first embodiment of the present invention. Here, FIG. 4 shows a cross section of the main part of the effective pixel area YA of the pixel area PA in the solid-state imaging device 1. FIG. 5 shows a cross section of the main part of the optical black pixel area BA of the pixel area PA and the peripheral area SA in the solid-state imaging device 1. 4 and FIG. 5 show a part of the elements constituting the pixel P of the pixel area PA and the elements constituting the peripheral circuit of the peripheral area SA. That is, in the pixel area PA and the peripheral area SA, the plurality of members shown in FIGS. 2 and 3 are provided, but in FIGS. 4 and 5, some of them are illustrated, and other parts are illustrated. Is omitted.

  As shown in FIG. 4, the effective pixel YP is provided as a pixel P (see FIG. 2) in the effective pixel area YA.

  As shown in FIG. 5, in the optical black pixel area BA, a light-shielding pixel BP is provided as a pixel P (see FIG. 2). In the peripheral area SA, peripheral circuit elements SK are provided as shown in FIG.

  4 and FIG. 5, a multilayer wiring layer 500 is provided on the upper surface of the substrate 101 in each of the effective pixel area YA, the optical black pixel area BA, and the peripheral area SA. As shown in FIGS. 4 and 5, the multilayer wiring layer 500 includes insulating films 511 to 519, a contact plug CP, a metal wiring HW, and a stress relaxation layer 600. In the multilayer wiring layer 500, a plurality of insulating films 511 to 519 are laminated, and a metal wiring HW is provided between the plurality of insulating films 511 to 519.

  Each part will be described sequentially.

(3-1) Effective Pixel In the effective pixel YP, as shown in FIG. 4, the photodiode 21 and the transfer transistor 22 are provided on the substrate 101 as part of the elements constituting the effective pixel YP. .

  In the effective pixel YP, the photodiode 21 is formed above the light receiving surface JS so that incident light is transmitted. Specifically, as shown in FIG. 4, insulating films 511 to 519 constituting the multilayer wiring layer 500 are stacked above the light receiving surface JS in the photodiode 21, and the insulating films 511 to 519 are It is made of an insulating material that transmits light.

  In the effective pixel YP, the transfer transistor 22 is provided on the substrate 101 adjacent to the photodiode 21 as shown in FIG.

(3-2) Light-shielding pixel In the light-shielding pixel BP, as shown in FIG. 5, the photodiode 21 and the transfer transistor 22 are part of the elements constituting the light-shielding pixel BP, as in the effective pixel YP. It is provided on the substrate 101.

  In the light shielding pixel BP, the photodiode 21 is formed above the light receiving surface JS so that incident light is shielded. Specifically, as shown in FIG. 5, in addition to the insulating films 511 to 519 constituting the multilayer wiring layer 500, a metal wiring HW is laminated above the light receiving surface JS in the photodiode 21. The metal wiring HW is formed of a metal material that blocks light.

  In the light-shielding pixel BP, the transfer transistor 22 is provided on the substrate 101 adjacent to the photodiode 21 as shown in FIG.

(3-3) Peripheral Circuit Element In the peripheral circuit element SK, as shown in FIG. 5, a transistor 311 and a capacitor 312 are provided on the substrate 101 as a part of the peripheral circuit element SK. For example, the transistor 311 and the capacitor 312 are provided on the substrate 101 as semiconductor elements constituting the column circuit 14.

(3-4) Multilayer Wiring Layer In the multilayer wiring layer 500, the insulating films 511 to 519 cover the effective pixel YP, the light shielding pixel BP, and the peripheral circuit element SK as shown in FIGS. Is formed.

  Among the plurality of insulating films 511 to 519, as shown in FIGS. 4 and 5, the first insulating film 511 is provided with each element of the effective pixel YP, the light shielding pixel BP, and the peripheral circuit element SK on the substrate 101. The upper surface is covered.

  In the plurality of insulating films 511 to 519, the second insulating film 512 is laminated on the upper surface of the first insulating film 511 as shown in FIGS.

  In the plurality of insulating films 511 to 519, the third insulating film 513 is stacked on the upper surface of the second insulating film 512 as shown in FIGS. The third insulating film 513 is formed so as to planarize the surface of the substrate 101 provided with the second insulating film 512. In the third insulating film 513, a plurality of contact plugs CP are provided so as to penetrate the first and second insulating films 511 and 512 together with the third insulating film 513. A metal wiring HW is provided on the upper surface of the third insulating film 513.

  In the plurality of insulating films 511 to 519, the fourth insulating film 514 is laminated on the upper surface of the third insulating film 513 as shown in FIGS. The fourth insulating film 514 is provided so as to cover the metal wiring HW provided on the upper surface of the third insulating film 513.

  In the plurality of insulating films 511 to 519, the fifth insulating film 515 is stacked on the upper surface of the fourth insulating film 514 as shown in FIGS. 4 and 5. The fifth insulating film 515 is formed so as to planarize the surface of the substrate 101 provided with the fourth insulating film 514. In the fifth insulating film 515, a plurality of contact plugs CP are provided so as to penetrate the fourth insulating film 514 together with the fifth insulating film 515. A metal wiring HW is provided on the upper surface of the fifth insulating film 515.

  In the plurality of insulating films 511 to 519, the sixth insulating film 516 is laminated on the upper surface of the fifth insulating film 515 as shown in FIGS. The sixth insulating film 516 is provided so as to cover the metal wiring HW provided on the upper surface of the fifth insulating film 515.

  In the plurality of insulating films 511 to 519, the seventh insulating film 517 is laminated on the upper surface of the sixth insulating film 516 as shown in FIGS. The seventh insulating film 517 is formed so as to planarize the surface of the substrate 101 provided with the sixth insulating film 516. In the seventh insulating film 517, a plurality of contact plugs CP are provided so as to penetrate the sixth insulating film 516 together with the seventh insulating film 517. A metal wiring HW is provided on the upper surface of the seventh insulating film 517.

  In the plurality of insulating films 511 to 519, the eighth insulating film 518 is stacked on the upper surface of the seventh insulating film 517 as shown in FIGS. The eighth insulating film 518 is provided so as to cover the metal wiring HW provided on the upper surface of the seventh insulating film 517.

  Among the plurality of insulating films 511 to 519, the ninth insulating film 519 is laminated on the upper surface of the eighth insulating film 518 as shown in FIGS. The ninth insulating film 519 is formed so as to planarize the surface of the substrate 101 provided with the eighth insulating film 518.

  In the multilayer wiring layer 500, as shown in FIGS. 4 and 5, the contact plug CP is provided above the effective pixel YP, the light shielding pixel BP, or the peripheral circuit element SK, and is electrically connected to each element. It is formed to do. Here, the contact plug CP is embedded in a contact hole CH formed so as to penetrate any of the insulating films 511 to 519 constituting the multilayer wiring layer 500.

  Specifically, as shown in FIGS. 4 and 5, the contact plug CP is formed so as to penetrate the first to third insulating films 511 to 513, and the effective pixel YP, the light shielding pixel BP, or A portion connected to the peripheral circuit element SK is included.

  Further, as shown in FIGS. 4 and 5, the contact plug CP is formed so as to penetrate the fourth and fifth insulating films 514 and 515, and penetrates the first to third insulating films 511 to 513. The lower-layer contact plug CP includes a portion that is electrically connected via the metal wiring HW.

  Further, as shown in FIGS. 4 and 5, the contact plug CP is formed so as to penetrate the sixth and seventh insulating films 516 and 517, and penetrates the fourth and fifth insulating films 514 and 515. The lower-layer contact plug CP includes a portion that is electrically connected via the metal wiring HW.

  As shown in FIGS. 4 and 5, the contact plug CP is provided with a barrier metal BM on the bottom surface and side surfaces.

  In the multilayer wiring layer 500, the metal wiring HW is formed so as to be interposed between any of the plurality of insulating films 511 to 519 as shown in FIGS. 4 and 5, and electrically connected to the contact plug CP. It is connected.

  Specifically, as shown in FIGS. 4 and 5, the metal wiring HW is provided on the third insulating film 513 and covered with the fourth insulating film 514. The metal wiring HW on the third insulating film 513 includes a contact plug CP that penetrates the first to third insulating films 511 to 513 and a contact plug CP that penetrates the fourth and fifth insulating films 514 and 515. And includes a portion for electrically connecting the two. Although not shown, in a portion where the light-shielding pixel BP and the peripheral circuit element SK are electrically connected, for example, a metal wiring HW provided on the third insulating film 513 extends between both elements. The two are electrically connected.

  Further, as shown in FIGS. 4 and 5, the metal wiring HW is provided on the fifth insulating film 515 and covered with the sixth insulating film 516. The metal wiring HW on the fifth insulating film 515 includes contact plugs CP that penetrate the fourth and fifth insulating films 514 and 515, and contact plugs CP that penetrate the sixth and seventh insulating films 516 and 517. And includes a portion for electrically connecting the two.

  Further, as shown in FIGS. 4 and 5, the metal wiring HW is provided on the seventh insulating film 517 and is covered with the eighth insulating film 518. The metal wiring HW on the seventh insulating film 517 includes a portion that is electrically connected to a contact plug CP that penetrates the sixth and seventh insulating films 516 and 517.

  As shown in FIGS. 4 and 5, each metal wiring HW is provided with a barrier metal BM on the upper surface and the lower surface.

  In the present embodiment, a plurality of metal wirings HW are provided so as to include a portion having a higher density in the peripheral area SA than in the pixel area PA including the effective pixel area YA and the optical black pixel area BA. ing. For example, the density of the metal wiring HW in the pixel area PA including the effective pixel area YA and the optical black pixel area BA is 10% to 40%. On the other hand, the density of the metal wiring HW in the peripheral region SA is, for example, 10% to 80%.

  In the multilayer wiring layer 500, as shown in FIG. 5, the stress relaxation layer 600 is provided in a portion of the plurality of insulating films 511 to 519 located between the optical black pixel area BA and the peripheral area SA. The stress alleviating layer 600 includes, for example, an air layer, and alleviates stress propagating to the optical black pixel area BA by the metal wiring HW provided in the peripheral area SA in the plurality of metal wirings HW.

  In the present embodiment, the stress relaxation layer 600 includes a first stress relaxation layer 601, a second stress relaxation layer 602, and a third stress relaxation layer 603, as shown in FIG.

  The first stress relaxation layer 601 is an air layer, and is provided so as to penetrate the fourth insulating film 514 as shown in FIG. In other words, the first stress relaxation layer 601 is provided so as to have the same height as the metal wiring HW provided on the third insulating film 513 in the plurality of metal wirings HW. The first stress relieving layer 601 is a boundary region between the pixel region PA including the effective pixel region YA and the optical black pixel region BA and the peripheral region SA, where the metal wiring HW and the contact plug CP are not provided. KA is provided. The first stress relaxation layer 601 is formed so as to draw a rectangle around the pixel area PA, as shown as the stress relaxation layer 600 in FIG.

  Similar to the first stress relaxation layer 601, the second stress relaxation layer 602 is an air layer and is provided so as to penetrate the sixth insulating film 516 as shown in FIG. That is, the second stress relaxation layer 602 is provided so as to have the same height as the metal wiring HW provided on the fifth insulating film 515 in the plurality of metal wirings HW. Similar to the first stress relaxation layer 601, the second stress relaxation layer 602 is provided in the boundary region KA. The second stress relieving layer 602 is formed to draw a rectangle around the pixel area PA, as shown as the stress relieving layer 600 in FIG.

  The third stress relieving layer 603 is an air layer, similar to the first and second stress relieving layers 601 and 602, and is provided so as to penetrate the eighth insulating film 518 as shown in FIG. It has been. That is, the third stress relaxation layer 603 is provided in the plurality of metal wirings HW so as to have the same height as the metal wiring HW provided on the seventh insulating film 517. The third stress relieving layer 603 is provided in the boundary region KA similarly to the first and second stress relieving layers 601 and 602. The third stress relieving layer 603 is formed to draw a rectangle around the pixel area PA, as shown as the stress relieving layer 600 in FIG.

[B] Manufacturing Method The main part of the manufacturing method for manufacturing the solid-state imaging device 1 will be described.

  FIGS. 6 to 11 are diagrams showing the main part provided in each step of the method of manufacturing the solid-state imaging device 1 in the first embodiment according to the present invention. Here, FIGS. 6 to 11 show cross sections of main parts of the optical black pixel area BA and the peripheral area SA, as in FIG. The effective pixel area YA is not shown because it is formed through the same process as the optical black pixel area BA.

(1) Formation of Elements and First to Third Insulating Films First, as shown in FIG. 6, on the upper surface of the substrate 101, the elements including the light-shielding pixels BP and the peripheral circuit elements SK, and the first to third insulating films are formed. Films 511 to 513 are provided on the substrate 101.

  Here, in the optical black pixel area BA, as shown in FIG. 6, the photodiode 21 and the transfer transistor 22 are provided on the substrate 101 as a part of the semiconductor elements constituting the pixel P (see FIG. 2).

  In addition, in the pixel area PA, the members shown in FIGS. 2 and 3 are provided, but the illustration is omitted here. Also in the effective pixel area YA (see FIG. 4), the photodiode 21 and the transfer transistor 22 are provided on the substrate 101 as part of the semiconductor element constituting the pixel P in the same manner as in the optical black pixel area BA. .

  In the peripheral region SA, the transistor 311 and the capacitor 312 are provided as part of the peripheral circuit element SK. In addition, in the peripheral area SA, the members shown in FIGS. 2 and 3 are provided, but the illustration is omitted here.

  Then, as shown in FIG. 6, a first insulating film 511 is provided.

Here, the first insulating film 511 is formed on the substrate 101 so as to cover the entire top surface where each element is formed as described above. For example, the first insulating film 511 is formed so as to be a SiO ₂ film having a film thickness of several tens of nm.

  Then, as shown in FIG. 6, a second insulating film 512 is provided.

  Here, the second insulating film 512 is provided so as to cover the entire top surface of the first insulating film 511 and be stacked over the first insulating film 511.

  In the present embodiment, the second insulating film 512 is formed so that the second insulating film 512 functions as an etching stopper layer in an etching process for the third insulating film 513 described later. That is, the second insulating film 512 is formed so that the etching selectivity with the third insulating film 513 is increased.

  For example, the second insulating film 512 is formed so as to be an LP-SiN film and have a film thickness of several tens of nm. That is, the second insulating film 512 is formed by depositing silicon nitride by a low pressure CVD method.

  Then, as shown in FIG. 6, a third insulating film 513 is formed.

  Here, the third insulating film 513 is formed so as to cover the upper surface of the second insulating film 512.

For example, an insulating material such as SiO ₂ is formed by plasma CVD so that the film thickness becomes 500 nm. Then, a third insulating film 513 is formed by performing a planarization process on the surface. For example, the surface is planarized by performing a CMP (Chemical Mechanical Polishing) process.

(2) Formation of Contact Hole CH in Third Insulating Film 513 Next, a contact hole CH is formed in the third insulating film 513 as shown in FIG.

  Here, a contact hole CH is formed in a portion of the third insulating film 513 where the contact plug CP (see FIG. 5) is to be formed.

  Specifically, after a photoresist mask (not shown) is formed by photolithography, an anisotropic dry etching process is performed on the third insulating film 513 using the photoresist mask, so that a contact hole is obtained. CH is formed. Thereby, the contact hole CH is formed so that the side surface of the contact hole CH is along the direction z perpendicular to the surface of the substrate 101.

In the present embodiment, the dry etching process is performed so that the second insulating film 512 positioned below the third insulating film 513 functions as an etching stopper layer. That is, the above-described dry etching process is performed so that a sufficient etching selectivity can be ensured between the SiN film as the second insulating film 512 and the SiO ₂ film as the third insulating film 513.

(3) Formation of Contact Hole CH in First and Second Insulating Films 511 and 512 Next, as shown in FIG. 8, contact hole CH is formed in each of first insulating film 511 and second insulating film 512. Form.

  Here, the contact holes CH are formed in the first and second insulating films 511 and 512 so that the contact holes CH formed in the third insulating film 513 extend downward.

  Specifically, the contact hole CH is formed by performing anisotropic dry etching processing on the first and second insulating films 511 and 512 in the same manner as described above. As a result, the surfaces of the electrodes and diffusion layers constituting the lower layer elements are exposed, and contact holes CH are formed.

  In the present embodiment, a sufficient etching selectivity can be ensured between an electrode (polysilicon or the like) or a diffusion layer (Si) constituting a lower element and the first and second insulating films 511 and 512. As described above, the dry etching process is performed.

  Thereafter, a hydrogenation process is performed.

(4) Formation of Contact Plug CP Next, as shown in FIG. 9, a contact plug CP is formed in the contact hole CH.

  Here, after forming the barrier metal BM so as to cover the bottom and side surfaces of the contact hole CH, a contact plug CP is formed by embedding a metal material in the contact hole CH. For example, the contact plug CP is formed using tungsten. Thereby, the contact plug CP is formed so as to be electrically connected to each element.

(5) Formation of Metal Wiring HW and Fourth Insulating Film 514 Next, as shown in FIG. 10, the metal wiring HW and the fourth insulating film 514 are formed.

  Here, the metal wiring HW is formed on the third insulating film 513 so as to be electrically connected to the contact plug CP penetrating the first to third insulating films 511 to 513. In the present embodiment, the metal wiring HW is formed so that the barrier metal BM is interposed between the upper surface and the lower surface of the metal wiring HW. For example, the metal wiring HW is formed using aluminum.

Then, a fourth insulating film 514 is formed so as to cover the metal wiring HW provided on the upper surface of the third insulating film 513.
For example, an insulating material such as SiO ₂ is formed by a plasma CVD method so that the film thickness becomes 500 nm, and the fourth insulating film 514 is formed.

(6) Formation of First Stress Relieving Layer 601 Next, as shown in FIG. 11, a first stress relieving layer 601 is formed.

  Here, as shown in FIG. 11, the first stress relaxation layer 601 is provided between the optical black pixel area BA and the peripheral area SA in the boundary area KA where the metal wiring HW and the contact plug CP are not formed. Provide.

  In the present embodiment, the first stress relaxation layer 601 is provided as an air layer by removing a part of the fourth insulating film 514.

  Specifically, after a photoresist film (not shown) is formed on the fourth insulating film 514, the photoresist film is patterned by a photolithography technique to form a resist mask (not shown). Here, a resist mask (not shown) is formed so that the surface of the fourth insulating film 514 where the first stress relaxation layer 601 is provided is exposed and the surface of the other part is covered. Then, anisotropic etching treatment is performed on the fourth insulating film 514 using this resist mask, and a part of the fourth insulating film 514 is removed, whereby the first stress relaxation layer 601 is formed. Form.

  For example, the first stress relaxation layer 601 is formed so that the width of the first stress relaxation layer 601 is, for example, 100 nm.

(7) Formation of other members Next, other members are formed as shown in FIG.

  Here, as illustrated in FIG. 5, the fifth insulating film 515 is formed so as to planarize the surface of the substrate 101 over which the fourth insulating film 514 is provided. For example, the fifth insulating film 515 is formed in the same manner as the third insulating film 513.

  Then, in the same manner as described above, the contact plug CP and the metal wiring HW are formed. Thereafter, a sixth insulating film 516 is formed in the same manner as the fourth insulating film 514. Then, in the same manner as in the case of the first stress relaxation layer 601, the second insulating layer 602 is provided as an air layer by removing a part of the sixth insulating film 516.

  In addition, a seventh insulating film 517 is formed so as to planarize the surface of the substrate 101 over which the sixth insulating film 516 is provided. For example, the seventh insulating film 517 is formed in the same manner as the third and fifth insulating films 513 and 515.

  Then, in the same manner as described above, the contact plug CP and the metal wiring HW are formed. Here, the metal wiring HW is formed to extend in the plane direction so as to block incident light directed to the light receiving surface JS of the photodiode 21 provided in the optical black pixel area BA. Thereafter, an eighth insulating film 518 is formed in the same manner as the fourth and sixth insulating films 514 and 516. Then, as in the case of the first and second stress relieving layers 601 and 602, a part of the eighth insulating film 518 is removed to provide a third stress relieving layer 602 as an air layer.

  Next, a ninth insulating film 519 is formed so as to planarize the surface of the substrate 101 provided with the eighth insulating film 518. For example, the ninth insulating film 519 is formed in the same manner as the third and fifth insulating films 513 and 515.

  Then, after forming each part, a hydrogenation process is implemented.

  By doing so, the solid-state imaging device 1 is completed.

[C] Summary As described above, in the multilayer wiring layer 500, the first to third stress relieving layers 601 to 603 are provided in the portion located between the optical black pixel area BA and the peripheral area SA. It is provided as a layer 600. The stress relaxation layer 600 includes an air layer and absorbs and relaxes stress caused by the metal wiring HW.

  As described above, in the multilayer wiring layer 500, the metal material forming the metal wiring HW has a greater stress (stress) than the insulating material forming each of the insulating films 511 to 519. For this reason, the generation of dark current may be noticeable due to the stress caused by the metal wiring HW. However, in this embodiment, the stress relaxation layer 600 absorbs and relaxes the stress caused by the metal wiring HW. For this reason, generation | occurrence | production of a dark current can be suppressed.

  Further, as described above, when the hydrogenation process is performed, it is difficult to effectively prevent the generation of noise components due to dark current because the metal wiring HW may inhibit hydrogen permeation. There are cases. However, in this embodiment, since the stress relaxation layer 600 includes an air layer, hydrogen is easily supplied to the substrate 101 via this air layer. Therefore, in this embodiment, the hydrogenation process can be effectively performed on the substrate 101.

<2. Second Embodiment>
[A] Device Configuration FIG. 12 is a diagram illustrating a main part of the solid-state imaging device 1b according to the second embodiment of the present invention. FIG. 12 shows a cross section of the same portion as in FIG.

  As shown in FIG. 12, in the present embodiment, the solid-state imaging device 1b is different from the first embodiment in the stress relaxation layer 600b. Except for this point, the present embodiment is the same as the first embodiment. For this reason, description is abbreviate | omitted about the overlapping part.

  As shown in FIG. 12, the stress relaxation layer 600b of the present embodiment is provided in the boundary region KA as in the first embodiment. Further, as shown in FIG. 12, the stress relaxation layer 600b includes a first stress relaxation layer 601b, a second stress relaxation layer 602b, and a third stress relaxation layer 603b.

  However, in the present embodiment, the first to third stress relaxation layers 601b, 602b, and 603b are different from the first embodiment, as shown in FIG. 12, the “air gap” in which the metal layer 611 sandwiches the air layer 612. Structure ".

[B] Manufacturing Method The main part of the manufacturing method for manufacturing the solid-state imaging device 1b will be described.

  FIG. 13 and FIG. 14 are diagrams showing the main part provided in each step of the method of manufacturing the solid-state imaging device 1b in the second embodiment according to the present invention. Here, FIG. 13 and FIG. 14 show cross sections of the main parts of the optical black pixel area BA and the peripheral area SA, as in FIG.

(1) Formation of Metal Wiring HW and Metal Layer 611 First, as shown in FIG. 13, the metal wiring HW and the metal layer 611 are formed.

  Here, prior to the formation of the metal wiring HW and the metal layer 611, the contact plug CP is formed in the contact hole CH as shown in FIG. 9, as in the first embodiment.

  Thereafter, as shown in FIG. 13, a metal wiring HW is formed on the third insulating film 513 so as to be electrically connected to the contact plug CP penetrating the first to third insulating films 511 to 513. To do.

  Along with this, a metal layer 611 is formed on the third insulating film 513 as shown in FIG. Here, the metal layer 611 is formed on the third insulating film 513 so that the plurality of metal layers 611 face each other across the air layer 612. For example, the metal layer 611 is formed so that the width of the air layer 612 between the plurality of metal layers 611 is 100 nm. For example, like the metal wiring HW, the metal layer 611 is formed using aluminum.

  Note that when the metal film provided over the third insulating film 513 is patterned into the metal wiring HW, the metal film may be patterned into the metal layer 611. That is, both the metal wiring HW and the metal layer 611 may be formed at the same time by performing the same pattern processing (such as photolithography) on the same metal film.

(2) Formation of Fourth Insulating Film 514 Next, as shown in FIG. 14, a fourth insulating film 514 is formed.

Here, the fourth insulating film 514 is formed so as to cover the metal wiring HW provided on the upper surface of the third insulating film 513. For example, the fourth insulating film 514 is formed by forming an insulating material such as SiO ₂ with a thickness of 500 nm by a plasma CVD method.

  At this time, the insulating material forming the fourth insulating film 514 is not embedded between the plurality of metal layers 611. For this reason, since the state in which the air layer 612 is sandwiched between the plurality of metal layers 611 is maintained, the first stress relaxation layer 601b is formed with the “air gap structure”.

(3) Formation of other members Next, other members are formed as shown in FIG.

  Here, as illustrated in FIG. 12, the fifth insulating film 515 is formed so as to planarize the surface of the substrate 101 over which the fourth insulating film 514 is provided. For example, the fifth insulating film 515 is formed in the same manner as the third insulating film 513.

  Then, after forming the contact plug CP, the metal wiring HW, the second stress relaxation layer 601b, and the sixth insulating film 516 are formed. The second stress relaxation layer 601b is formed through the same process as that of the first stress relaxation layer 601a.

  Then, a seventh insulating film 517 is formed so as to planarize the surface of the substrate 101 over which the sixth insulating film 516 is provided. For example, the seventh insulating film 517 is formed in the same manner as the third and fifth insulating films 513 and 515.

  In the same manner as described above, after forming the contact plug CP, the metal wiring HW, the third stress relaxation layer 601c, and the eighth insulating film 518 are formed. The third stress relieving layer 601c is formed through the same process as that of the first and second stress relieving layers 601a and 601b.

  Next, a ninth insulating film 519 is formed so as to planarize the surface of the substrate 101 provided with the eighth insulating film 518. For example, the ninth insulating film 519 is formed in the same manner as the third and fifth insulating films 513 and 515.

  Then, after forming each part, a hydrogenation process is implemented.

  By doing so, the solid-state imaging device 1b is completed.

[C] Summary As described above, in the multilayer wiring layer 500, the first to third stress relief layers 601b to 603b are provided in the boundary area KA between the optical black pixel area BA and the peripheral area SA. It is provided as a layer 600b. The stress relieving layer 600b includes an air layer 612 and absorbs and relieves stress due to the metal wiring HW. For this reason, this embodiment can suppress generation | occurrence | production of a dark current similarly to the case of Embodiment 1. FIG.

  In this embodiment, since the stress relaxation layer 600b includes the air layer 612, hydrogen is easily supplied to the substrate 101 via the air layer 612. Therefore, in the present embodiment, as in the case of the first embodiment, the hydrogenation treatment can be effectively performed on the substrate 101.

<3. Embodiment 3>
[A] Device Configuration, etc. FIG. 15 is a diagram illustrating a main part of the solid-state imaging device 1c in the third embodiment of the present invention. FIG. 15 shows a cross section of the same part as in FIG.

  As shown in FIG. 15, in the present embodiment, the solid-state imaging device 1c is different from the first embodiment in the stress relaxation layer 600c. Except for this point, the present embodiment is the same as the first embodiment. For this reason, description is abbreviate | omitted about the overlapping part.

  As shown in FIG. 15, the stress relieving layer 600c according to the present embodiment is provided in the boundary region KA including the air layer as in the first embodiment.

  However, the stress relieving layer 600 c is formed so as to penetrate the third insulating film 513 to the sixth insulating film 516.

  The stress relaxation layer 600c is formed by performing anisotropic etching on the third insulating film 513 to the sixth insulating film 516 and removing a part thereof.

  Although the illustration of the planar structure of the stress relaxation layer 600c is omitted, the stress relaxation layer 600c is formed so as to draw a rectangle around the pixel region PA as shown as the stress relaxation layer 600 in FIG. Has been.

  FIG. 16 is a diagram illustrating a main part of the solid-state imaging device 1c according to the third embodiment of the present invention. FIG. 16 is different from FIG. 15 in the solid-state imaging device 1c in which the light-shielding pixel BP provided in the optical black pixel area BA and the peripheral circuit element SK provided in the peripheral area SA are electrically connected. Is shown.

  Although not shown in the first embodiment, a portion where the light shielding pixel BP and the peripheral circuit element SK are electrically connected is, for example, a metal wiring HW provided on the third insulating film 513 between the two elements. And is electrically connected to each other.

  However, in the present embodiment, the stress relaxation layer 600c penetrates the third to sixth insulating films 513 to 516 (see FIG. 15) and integrally surrounds the periphery of the optical black pixel area BA. It is formed (see FIG. 2). For this reason, in the present embodiment, the light shielding pixel BP and the peripheral circuit element SK are not electrically connected by providing the metal wiring HW on the third insulating film 513.

  In the present embodiment, as shown in FIG. 16, the metal wiring HW is extended on the seventh insulating film 517 above the stress relaxation layer 600c to electrically connect both the light-shielding pixel BP and the peripheral circuit element SK. Connected.

  For example, as shown in FIG. 2, between the pixel area PA and the peripheral area SA, the pixel P in the pixel area PA and the column circuit 14 are electrically connected via the column signal line HL (metal wiring HW). The portion to be connected to is configured as shown in FIG.

  As in the case of the first embodiment, for example, the light shielding pixel BP and the peripheral circuit element SK may be electrically connected by the metal wiring HW provided on the third insulating film 513. .

  FIG. 17 is a view showing a modification of the third embodiment according to the present invention. FIG. 17 shows an example in which the light-shielding pixel BP and the peripheral circuit element SK are electrically connected by, for example, the metal wiring HW provided on the third insulating film 513, as in the case of the first embodiment. ing.

  As shown in FIG. 17, between the pixel area PA and the peripheral area SA, a portion where the pixel P of the pixel area PA and the column circuit 14 are electrically connected via the column signal line HL is stressed. The relaxation layer 600d may not be provided.

  For example, as shown in FIG. 17, at the lower end portion of the pixel area PA, a stress relaxation layer 600d is formed so as to draw a broken line in a portion where the column signal line HL (metal wiring HW) is along the vertical direction y. May be.

[B] Summary As described above, in the multilayer wiring layer 500, the stress relaxation layer 600d is provided in the boundary area KA between the optical black pixel area BA and the peripheral area SA. The stress relaxation layer 600d includes an air layer 612, and absorbs and relaxes stress caused by the metal wiring HW. For this reason, this embodiment can suppress generation | occurrence | production of a dark current similarly to the case of Embodiment 1. FIG.

  In the present embodiment, since the stress relaxation layer 600d includes an air layer, hydrogen is easily supplied to the substrate 101 via the air layer. Therefore, in the present embodiment, as in the case of the first embodiment, the hydrogenation treatment can be effectively performed on the substrate 101.

  In this embodiment, since the single stress relaxation layer 600d is formed, the number of steps can be reduced as compared with the above-described embodiment. For this reason, this embodiment can further improve manufacturing efficiency.

<4. Embodiment 4>
[A] Device Configuration, etc. FIGS. 18 and 19 are diagrams showing a main part of a solid-state imaging device 1d in Embodiment 4 according to the present invention. Here, FIG. 18 is a schematic plan view of the solid-state imaging device 1d, similarly to FIG. FIG. 19 shows a cross section of a portion where the effective pixel area YA and the optical black pixel area BA are provided in the solid-state imaging device 1d.

  As shown in FIGS. 18 and 19, in the present embodiment, the solid-state imaging device 1d is different from the first embodiment in the position where the stress relaxation layer 600d is provided. Except for this point, the present embodiment is the same as the first embodiment. For this reason, description is abbreviate | omitted about the overlapping part.

  As shown in FIG. 18, the stress relaxation layer 600d is formed so as to draw a rectangle inside the pixel area PA, unlike the case of the first embodiment.

  Here, as shown in FIG. 19, the stress relieving layer 600d is provided in the boundary region KAd located between the effective pixel region YA and the optical black pixel region BA in the pixel region PA. The stress relieving layer 600d includes an air layer, for example, and is provided so as to relieve stress due to the metal wiring HW constituting the multilayer wiring layer 500.

  In the present embodiment, as shown in FIG. 19, the stress relaxation layer 600d includes a first stress relaxation layer 601d, a second stress relaxation layer 602d, and a third stress relaxation layer 603d.

  As shown in FIG. 19, the first stress relieving layer 601d is an air layer, and is provided so as to penetrate the fourth insulating film 514 as in the case of the first embodiment.

  As shown in FIG. 19, the second stress relaxation layer 602 d is an air layer and is provided so as to penetrate the sixth insulating film 516 as in the case of the first embodiment.

  As shown in FIG. 19, the third stress relieving layer 603d is an air layer, and is provided so as to penetrate the eighth insulating film 518, as in the case of the first embodiment.

[B] Summary As described above, in the multilayer wiring layer 500, the first to third stress relieving layers 601d to 603d are placed in the portions located between the effective pixel area YA and the optical black pixel area BA. It is provided as a relaxation layer 600d. The stress relaxation layer 600d includes an air layer and absorbs and relaxes stress caused by the metal wiring HW. For this reason, this embodiment can suppress generation | occurrence | production of a dark current similarly to the case of Embodiment 1. FIG.

  In the present embodiment, since the stress relaxation layer 600d includes an air layer, hydrogen is easily supplied to the substrate 101 via the air layer. Therefore, in the present embodiment, as in the case of the first embodiment, the hydrogenation treatment can be effectively performed on the substrate 101.

<5. Embodiment 5>
[A] Device Configuration, etc. FIG. 20 is a diagram illustrating a main part of the solid-state imaging device 1e according to the fifth embodiment of the present invention. FIG. 20 shows a cross section of the same portion as in FIG.

  As shown in FIG. 20, in the present embodiment, the solid-state imaging device 1 e is different from the first embodiment in the stress relaxation layer 600 e. Except for this point, the present embodiment is the same as the first embodiment. For this reason, description is abbreviate | omitted about the overlapping part.

  As shown in FIG. 20, the stress relaxation layer 600e of this embodiment includes an air layer and is provided in the boundary region KA, as in the first embodiment. In addition, as shown in FIG. 20, the stress relaxation layer 600e includes a first stress relaxation layer 601e, a second stress relaxation layer 602e, and a third stress relaxation layer 603e.

  However, in the present embodiment, the first to third stress relaxation layers 601e, 602e, and 603e include portions having a width different from that in the first embodiment, as shown in FIG.

  Among the plurality of metal wirings HW, the first metal wiring HW1e and the second metal wiring are disposed above the pixel vicinity region adjacent to the pixel region PA (optical black pixel region BA in FIG. 20) in the peripheral region SA. An HW2e and a third metal wiring HW3e are provided.

  Here, as shown in FIG. 20, the first metal wiring HW1e is formed on the third insulating film 513 so as to be narrower than the second metal wiring HW2e.

  Further, as shown in FIG. 20, the second metal wiring HW2e is provided above the first metal wiring HW1e and on the fifth insulating film 515. The second metal wiring HW2e is formed to be narrower than the third metal wiring HW3e.

  Further, as shown in FIG. 20, the third metal wiring HW3e is provided above the second metal wiring HW2e and on the seventh insulating film 517. The third metal wiring HW3e is formed to be wider than the first and second metal wirings HW1e and HW2e.

  That is, the first to third metal wirings HW1e, HW2e, and HW3e are formed so as to increase in width in this order.

  As shown in FIG. 20, the first to third stress relaxation layers 601e, 602e, and 603e each have a width corresponding to the widths of the first to third metal wirings HW1e, HW2e, and HW3e. Is formed.

  Specifically, as shown in FIG. 20, the first stress relaxation layer 601e is formed on the third insulating film 513 so as to be narrower than the second stress relaxation layer 602e. .

  Further, as shown in FIG. 20, the second stress relaxation layer 602e is formed on the fifth insulating film 515 so as to be narrower than the third stress relaxation layer 603e.

  Further, as shown in FIG. 20, the third stress relieving layer 603e is formed to be wider than the first and second stress relieving layers 602e and 603e.

  That is, the first to third stress relaxation layers 601e, 602e, and 603e are formed so as to increase in width in this order.

[B] Summary As described above, in the multilayer wiring layer 500, the first to third stress relieving layers 601e to 603e are stressed in the portion located between the effective pixel area YA and the optical black pixel area BA. The relaxation layer 600e is provided. The stress relieving layer 600e includes an air layer and absorbs and relieves stress due to the metal wiring HW. For this reason, this embodiment can suppress generation | occurrence | production of a dark current similarly to the case of Embodiment 1. FIG.

  In the present embodiment, the first to third stress relaxations are performed so as to correspond to the widths of the first to third metal wirings HW1e, HW2e, and HW3e provided in the vicinity of the pixel area PA in the peripheral area SA. The widths of the layers 601e, 602e, and 603e are formed. For this reason, said effect can be show | played more effectively.

  In the above description, the first to third stress relaxation layers 601e, 602e, and 603e are provided one by one, but a plurality may be provided. In this case, it is preferable to increase the number of first to third stress relaxation layers 601e, 602e, and 603e so as to correspond to the widths of the first to third metal wirings HW1e, HW2e, and HW3e. .

<6. Embodiment 6>
[A] Device Configuration, etc. FIG. 21 is a diagram illustrating a main part of the solid-state imaging device 1f according to the sixth embodiment of the present invention. FIG. 21 shows a cross section of the same portion as in FIG.

  As shown in FIG. 21, in the present embodiment, the solid-state imaging device 1 f is different from the first embodiment in the stress relaxation layer 600 f. Except for this point, the present embodiment is the same as the first embodiment. For this reason, description is abbreviate | omitted about the overlapping part.

  As shown in FIG. 21, the stress relieving layer 600f of this embodiment includes an air layer and is provided in the boundary region KA, as in the first embodiment. Further, as shown in FIG. 21, the stress relaxation layer 600f includes a first stress relaxation layer 601f, a second stress relaxation layer 602f, and a third stress relaxation layer 603f.

  However, in the present embodiment, the first to third stress relaxation layers 601f, 602f, and 603f are different in width from those in the first embodiment, as shown in FIG.

  Among the plurality of metal wirings HW, the first metal wiring HW1f and the second metal wiring are disposed above the pixel vicinity region adjacent to the pixel region PA (optical black pixel region BA in FIG. 21) in the peripheral region SA. HW2f and third metal wiring HW3f are provided.

  Here, the first metal wiring HW1f is formed on the third insulating film 513 as shown in FIG. Further, as shown in FIG. 21, the second metal wiring HW2f is provided above the first metal wiring HW1e and on the fifth insulating film 515. Further, as shown in FIG. 21, the third metal wiring HW3f is provided above the second metal wiring HW2f and on the seventh insulating film 517.

  The first to third metal wirings HW1f, HW2f, and HW3f are formed to have the same width.

  As shown in FIG. 21, the first to third stress relieving layers 601f, 602f, and 603f are formed so that the widths thereof are increased according to the respective heights.

  Specifically, as shown in FIG. 21, the first stress relaxation layer 601f is formed on the third insulating film 513 so as to be wider than the second stress relaxation layer 602f. .

  Further, as shown in FIG. 21, the second stress relaxation layer 602f is formed on the fifth insulating film 515 so as to be wider than the third stress relaxation layer 603f.

  Further, as shown in FIG. 21, the third stress relaxation layer 603f is formed to be narrower than the first and second stress relaxation layers 602f and 603f.

  That is, the first to third stress relieving layers 601f, 602f, and 603f are formed so as to be narrower in this order.

[B] Summary As described above, in the multilayer wiring layer 500, the first to third stress relieving layers 601f to 603f are stressed in the portion located between the effective pixel area YA and the optical black pixel area BA. The relaxing layer 600f is provided. The stress relaxation layer 600f includes an air layer and absorbs and relaxes stress caused by the metal wiring HW. For this reason, this embodiment can suppress generation | occurrence | production of a dark current similarly to the case of Embodiment 1. FIG.

  In general, the stress on the metal wiring HW is greater in a portion closer to the surface of the substrate 101 (a portion having a lower height) than in a portion farther (a portion having a higher height). However, in the present embodiment, the first to third stress relaxation layers 601f, 602f, and 603f are formed so that the widths thereof are increased according to the respective heights. For this reason, said effect can be show | played more effectively.

  In the above description, the first to third stress relaxation layers 601e, 602e, and 603e are provided one by one, but a plurality may be provided. In this case, it is preferable to adjust the number of first to third stress relaxation layers 601e, 602e, and 603e so as to correspond to the height positions of the first to third metal wirings HW1e, HW2e, and HW3e. It is.

<7. Other>
In carrying out the present invention, the present invention is not limited to the above-described embodiment, and various modifications can be employed.

  In the above embodiment, the case where the stress relieving layer includes an air layer has been described, but the present invention is not limited to this. In carrying out the present invention, the stress relieving layer may be a layer other than the air layer. In this case, the stress alleviating layer only needs to have a lower stress than the insulating film and the metal wiring constituting the multilayer wiring layer. For example, the stress relieving layer may be formed as a layer using a reflow glass material or a porous Low-K film.

  In the above embodiment, the case where the stress relaxation layer is provided so as to entirely surround the periphery of the pixel region (or effective pixel region) has been described, but the present invention is not limited to this. In carrying out the present invention, a stress relaxation layer may be provided in a part of the periphery of the pixel region (or effective pixel region). In this case, for example, it is preferable to provide a stress relaxation layer in a portion where the column circuit is provided in the peripheral region. This portion is greatly restricted in terms of layout, but since many fine metal wirings are arranged, the stress of the metal wiring is large, and thus the effect of installing a stress relaxation layer is great. In addition to this, it is preferable to provide a stress relieving layer in a portion (pixel power source, DAC circuit, load MOS, etc.) where metal wirings are installed at high density.

  In implementing the present invention, for example, the four pixels P may be configured as common pixels.

  FIG. 22 is a diagram showing a configuration of the pixel P in the embodiment according to the invention.

  As shown in FIG. 22, for example, a common pixel may be configured by combining four pixels P. In this case, two light receiving surfaces JS of the photodiode 21 are arranged in the horizontal direction x and the vertical direction y. A floating diffusion FD is provided at the center of all the four pixels P. A transfer transistor 22 is provided between the light receiving surfaces JS of the four pixels P and the floating diffusion FD. The pixel transistors other than the transfer transistor 22 are provided so as to be commonly used in the four pixels P.

  Specifically, each transfer transistor 22 has a source electrically connected to each photodiode 21, and a drain electrically connected to the source of one reset transistor 25. The floating diffusion FD is electrically connected to one amplification transistor 23. The source of the amplification transistor 23 is electrically connected to the drain of one address transistor 24. Each of the reset transistor 25 and the amplification transistor 23 is configured such that a power supply voltage is applied to the drain. In the selection transistor 24, the source is electrically connected to the vertical signal line.

  In each transfer transistor 22, a row transfer signal is applied to the gate. In the reset transistor 25, a row reset signal is applied to the gate. In the address transistor 24, a row selection signal is applied to the gate. In this way, by applying each signal, the signal charge readout operation is sequentially executed for each pixel P.

  Then, as shown in FIG. 22, a stress relaxation layer 600g is provided in the boundary area KA located between the pixel area PA and the peripheral area SA. The stress relaxation layer 600g includes an air layer and absorbs and relaxes stress caused by the metal wiring HW. For this reason, generation of dark current can be suppressed as in the case of the first embodiment. In this embodiment, since the stress relaxation layer 600g includes an air layer, hydrogen is easily supplied to the substrate 101 through the air layer. Therefore, as in the case of the first embodiment, the hydrogenation process can be effectively performed on the substrate. In particular, by providing the stress relaxation layer 600g near the amplification transistor 23, this effect can be made obvious.

  In the above embodiment, the case of applying to a CMOS image sensor has been described, but the present invention is not limited to this. For example, it can be applied to a CCD image sensor.

  In the practice of the present invention, the metal wiring may be formed using a metal material such as copper, and a diffusion prevention layer for preventing diffusion of the metal material such as copper is provided between the insulating films. It may be formed.

  In the above embodiment, the case where the optical black area is provided in the pixel area has been described, but the present invention is not limited to this. The present invention can be applied even when an optical black region is not provided in the pixel region.

  In the above embodiment, the case where the present invention is applied to the camera 40 has been described. However, the present invention is not limited to this. The present invention may be applied to other electronic devices including a solid-state imaging device such as a scanner or a copy machine.

  In the above embodiment, the solid-state imaging devices 1, 1b, 1c, 1d, 1e, and 1f correspond to the solid-state imaging device of the present invention. In the above embodiment, the light receiving surface JS corresponds to the light receiving surface of the present invention. In the above embodiment, the pixel P corresponds to the pixel of the present invention. In the above embodiment, the pixel area PA corresponds to the pixel area of the present invention. In the above embodiment, the peripheral area SA corresponds to the peripheral area of the present invention. In the above embodiment, the peripheral circuit element SK corresponds to the peripheral circuit element of the present invention. In the above embodiment, the substrate 101 corresponds to the semiconductor substrate of the present invention. In the above embodiment, the insulating films 511 to 519 correspond to the insulating film of the present invention. In the above embodiment, the metal wiring HW corresponds to the metal wiring of the present invention. In the above embodiment, the multilayer wiring layer 500 corresponds to the wiring layer of the present invention. In the above embodiment, the stress relief layers 600, 600b, 600c, 600d, 600e, 600f, and 600g correspond to the stress relief layers of the present invention. In the above embodiment, the effective pixel YP corresponds to the effective pixel of the present invention. In the above embodiment, the light shielding pixel BP corresponds to the light shielding pixel of the present invention. In the above embodiment, the effective pixel area YA corresponds to the effective pixel area of the present invention. In the above embodiment, the optical black pixel area BA corresponds to the optical black pixel area of the present invention. In the above embodiment, the first metal wires HW1e and HW1f correspond to the first metal wires of the present invention. In the above embodiment, the second metal wirings HW2e and HW2f correspond to the second metal wiring of the present invention. In the above embodiment, the first stress relaxation layers 601, 601a, 601b, 601d, 601e, and 601f correspond to the first stress relaxation layers of the present invention. In the above embodiment, the second stress relaxation layers 602, 602a, 602b, 602d, 602e, and 602f correspond to the second stress relaxation layers of the present invention. In the above embodiment, the column circuit 14 corresponds to the column circuit of the present invention. In the above embodiment, the camera 40 corresponds to the electronic apparatus of the present invention.

  1, 1b, 1c, 1d, 1e, 1f: solid-state imaging device, 13: row scanning circuit, 14: column circuit, 15: column scanning circuit, 16: horizontal output line, 17: output circuit, 18: timing control circuit, 21: photodiode, 22: transfer transistor, 23: amplification transistor, 24: selection transistor, 25: reset transistor, 40: camera, 42: optical system, 43: control unit, 44: signal processing circuit, 101: substrate, 311 : Transistor, 312: capacitor, 400: ADC, 500: multilayer wiring layer, 511: first insulating film, 512: second insulating film, 513: third insulating film, 514: fourth insulating film, 515 : Fifth insulating film, 516: sixth insulating film, 517: seventh insulating film, 518: eighth insulating film, 519: ninth insulating film, 600, 600b, 600c, 00d, 600e, 600f, 600g: stress relaxation layer, 601, 601a, 601b, 601d, 601e, 601f: first stress relaxation layer, 602, 602a, 602b, 602d, 602e, 602f: second stress relaxation layer, 603, 603a, 603b, 603d, 603e, 603f: third stress relieving layer, 611: metal layer, 612: air layer, BA: optical black pixel region, BM: barrier metal, BP: light shielding pixel, CH: contact hole CP: contact plug, FD: floating diffusion, HL: column signal line, HW: metal wiring, HW1e, HW1f: first metal wiring, HW2e, HW2f: second metal wiring, HW3e, HW3f: third metal Wiring, JS: light receiving surface, KA, KAd: boundary region v, : Pixel, PA: pixel regions, PS: imaging surface, SA: peripheral region, SK: peripheral circuit elements, VL: row control lines, YA: effective pixel regions, YP: effective pixels

Claims (18)

A plurality of pixels in the pixel region that receive incident light on the light receiving surface and generate signal charges, and a semiconductor substrate in which peripheral circuit elements are provided in a peripheral region located around the pixel region;
A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films, and a wiring layer is provided.
The solid-state imaging device, wherein the insulating film is provided with a stress relieving layer that relieves stress due to the metal wiring in a portion located between the pixel region and the peripheral region. The stress relieving layer includes an air layer,
The solid-state imaging device according to claim 1. The plurality of pixels are:
An effective pixel formed above the light receiving surface so that the incident light is transmitted;
A light shielding pixel formed above the light receiving surface so that the incident light is shielded, and
The pixel region is
An effective pixel region located in a central portion of the pixel region and provided with the effective pixels;
An optical black pixel region located in a peripheral portion of the effective pixel region in the pixel region and provided with the light-shielding pixel;
The insulating film is provided with the stress relieving layer in a portion located between the optical black pixel region and the peripheral region.
The solid-state imaging device according to claim 2. A plurality of the metal wirings are provided so as to have a higher density in the peripheral region than the pixel region,
The stress relieving layer relieves stress propagating to the pixel region by the metal wiring provided in the peripheral region in the plurality of metal wirings.
The solid-state imaging device according to claim 3. The plurality of metal wirings are:
A first metal wiring disposed at a first height above a pixel vicinity region adjacent to the pixel region in the peripheral region;
At least a second metal wiring disposed at a second height different from the first height above the pixel proximity region;
The stress relieving layer is
A first stress relieving layer disposed at the first height;
And at least a second stress relieving layer disposed at the second height,
The width of the first metal wiring is formed wider than the width of the second metal wiring;
A width of the first stress relieving layer is formed wider than a width of the second stress relieving layer;
The solid-state imaging device according to claim 4. The first stress relieving layer is provided in a larger number than the second stress relieving layer.
The solid-state imaging device according to claim 5. The plurality of metal wirings are:
A first metal wiring disposed at a first height above the pixel vicinity region adjacent to the pixel region in the peripheral region;
And at least a second metal wiring disposed at a second height higher than the first height above the pixel proximity region;
The stress relieving layer is
A first stress relieving layer disposed at the first height;
And at least a second stress relieving layer disposed at the second height,
A width of the first stress relieving layer is formed wider than a width of the second stress relieving layer;
The solid-state imaging device according to claim 4. The first stress relieving layer is provided in a larger number than the second stress relieving layer.
The solid-state imaging device according to claim 7. The peripheral circuit element includes a column circuit,
The stress relieving layer is formed so as to be interposed between at least the portion where the column circuit is formed in the peripheral region and the pixel region.
The solid-state imaging device according to claim 4. A plurality of pixels that receive incident light on the light receiving surface and generate signal charges are provided in the pixel region, and a semiconductor substrate in which a peripheral circuit element is provided in a peripheral region located around the pixel region;
A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films, and a wiring layer is provided.
The plurality of pixels are:
An effective pixel formed above the light receiving surface so that the incident light is transmitted;
A light shielding pixel formed above the light receiving surface so that the incident light is shielded, and
The pixel region is
An effective pixel region located in a central portion of the pixel region and provided with the effective pixels;
An optical black pixel region located in a peripheral portion of the effective pixel region in the pixel region and provided with the light-shielding pixel;
The solid-state imaging device, wherein the insulating film is provided with a stress relieving layer that relieves stress due to the plurality of metal wirings in a portion located between the effective pixel region and the peripheral region. The stress relieving layer is provided in a portion located between the effective pixel region and the optical black pixel region.
The solid-state imaging device according to claim 10. The stress relieving layer includes an air layer,
The solid-state imaging device according to claim 11. A plurality of pixels that receive incident light on the light receiving surface and generate signal charges are provided in the pixel region, and a semiconductor substrate in which a peripheral circuit element is provided in a peripheral region located around the pixel region;
A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films, and a wiring layer is provided.
The electronic device is provided with a stress relieving layer for relieving stress due to the metal wiring in a portion located between the pixel region and the peripheral region. A plurality of pixels that receive incident light on the light receiving surface and generate signal charges are provided in the pixel region, and a semiconductor substrate in which a peripheral circuit element is provided in a peripheral region located around the pixel region;
A plurality of insulating films are stacked above the pixel region and the peripheral region, and a metal wiring is provided between the plurality of insulating films, and a wiring layer is provided.
The plurality of pixels are:
An effective pixel formed above the light receiving surface so that the incident light is transmitted;
A light shielding pixel formed above the light receiving surface so that the incident light is shielded, and
The pixel region is
An effective pixel region located in a central portion of the pixel region and provided with the effective pixels;
An optical black pixel region located in a peripheral portion of the effective pixel region in the pixel region and provided with the light-shielding pixel;
The electronic device is provided with a stress relieving layer for relieving stress caused by the plurality of metal wirings in a portion located between the effective pixel region and the peripheral region. Element formation in which a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region of a semiconductor substrate, and a peripheral circuit element is provided in a peripheral region located around the pixel region in the semiconductor substrate Process,
A wiring layer forming step of forming a wiring layer in which metal wiring is interposed between a plurality of laminated insulating films above the pixel region and the peripheral region, and
In the wiring layer forming step, in the insulating film, a stress relieving layer that relieves stress due to the plurality of metal wirings is formed in a portion located between the pixel region and the peripheral region.
Manufacturing method of solid-state imaging device. A hydrogenation treatment step of performing a hydrogenation treatment on the semiconductor substrate on which the wiring layer is formed;
In the wiring layer forming step, the stress relaxation layer is formed so as to include an air layer,
In the hydrogenation treatment step, the hydrogenation treatment is performed on the semiconductor substrate via the stress relaxation layer including the air layer.
The manufacturing method of the solid-state imaging device of Claim 15. An element forming step in which a plurality of pixels that receive incident light on a light receiving surface and generate signal charges are provided in a pixel region of a semiconductor substrate, and a peripheral circuit element is provided in a peripheral region located around the pixel region in the semiconductor substrate; ,
A wiring layer forming step of forming a wiring layer in which metal wiring is interposed between a plurality of laminated insulating films above the pixel region and the peripheral region, and
The element forming step includes
A pixel forming step of forming, as the plurality of pixels, an effective pixel through which the incident light is transmitted to the light receiving surface and a light shielding pixel in which the incident light is shielded above the light receiving surface; Forming the effective pixel in the effective pixel region located in the central portion of the pixel region, and forming the light-shielded pixel in the optical black pixel region located in the peripheral portion of the effective pixel region in the pixel region,
In the wiring layer forming step, a stress relieving layer that relieves stress due to the metal wiring is provided in a portion located between the effective pixel region and the peripheral region in the insulating film.
Manufacturing method of solid-state imaging device. A hydrogenation treatment step of performing a hydrogenation treatment on the semiconductor substrate on which the wiring layer is formed;
In the wiring layer forming step, the stress relaxation layer is formed so as to include an air layer,
In the hydrogenation treatment step, the hydrogenation treatment is performed on the semiconductor substrate via the stress relaxation layer including the air layer.
The manufacturing method of the solid-state imaging device of Claim 17.

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