WO2024051066A1 - 半导体基底结构及器件 - Google Patents

半导体基底结构及器件 Download PDF

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Publication number
WO2024051066A1
WO2024051066A1 PCT/CN2023/072523 CN2023072523W WO2024051066A1 WO 2024051066 A1 WO2024051066 A1 WO 2024051066A1 CN 2023072523 W CN2023072523 W CN 2023072523W WO 2024051066 A1 WO2024051066 A1 WO 2024051066A1
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Prior art keywords
substrate
insulating layer
base structure
semiconductor base
vertical
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PCT/CN2023/072523
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English (en)
French (fr)
Inventor
武震宇
王栎皓
苏泳全
刘艺晨
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中国科学院上海微系统与信息技术研究所
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Publication of WO2024051066A1 publication Critical patent/WO2024051066A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]

Definitions

  • the invention belongs to the field of semiconductor technology and relates to a semiconductor base structure and a device.
  • the silicon on insulator (SOI) substrate has an intermediate insulating layer, which can provide an electrical isolation layer in the IC integrated circuit, reduce the leakage current of the device, It is widely used as a functional substrate to strengthen the irradiation characteristics of devices, provide an etching stop layer in the MEMS process, and increase process uniformity.
  • the existing conventional SOI substrate only contains a horizontal insulating layer and cannot conduct electrical conduction in the vertical direction.
  • TSV through silicon via
  • the existing through silicon via technology is mostly realized by etching deep holes on the substrate and electroplating metal filling.
  • Such through silicon via substrates are only suitable for low-temperature processes below 500°C.
  • electrical packaging substrate it is not compatible with front-end high-temperature processes above 700°C.
  • the purpose of the present invention is to provide a semiconductor substrate structure and device to solve the problem of limitations of substrate application in the prior art.
  • the present invention provides a semiconductor base structure, which includes:
  • a substrate the substrate includes a first side and an opposite second side;
  • Conductive pillars the conductive pillars penetrate from the first side of the substrate to the second side of the substrate;
  • a lateral insulating layer, the lateral insulating layer is located in the substrate and is arranged at intervals or continuously along the lateral direction of the substrate;
  • the vertical insulation layer is located in the substrate, arranged at vertical intervals along the substrate, penetrating from the first side of the substrate to the second side of the substrate and Located on the periphery of the conductive pillar, there is a gap between the vertical insulating layer and the lateral insulating layer.
  • the material of the conductive pillar includes one or a combination of monocrystalline silicon, polycrystalline silicon, silicon dioxide, and silicon nitride;
  • the resistivity of the conductive pillar is less than 5 ⁇ 10 -3 ⁇ cm.
  • the material of the substrate includes one or a combination of monocrystalline silicon, polycrystalline silicon, silicon carbide, diamond, and III-V semiconductors; the thickness of the substrate includes 100 ⁇ m to 800 ⁇ m.
  • the angle between the horizontal insulating layer and the vertical insulating layer includes 30° to 150°.
  • the cross-sectional shape of the conductive pillar includes one or a combination of circular, elliptical, arcuate and polygonal shapes;
  • the cross-sectional shape of the transverse insulating layer includes circular, elliptical, arcuate shape. and polygon;
  • the cross-sectional shape of the vertical insulation layer includes one or a combination of circle, ellipse, arc and polygon.
  • the material of the lateral insulating layer includes one or a combination of oxide, nitride, carbide and polymer; the material of the vertical insulating layer includes oxide, nitride, carbide and polymer.
  • the oxide includes silicon oxide
  • the nitride includes silicon nitride
  • the carbide includes silicon carbide.
  • the applicable process temperature for the semiconductor base structure includes 25°C to 1200°C.
  • the lateral insulating layer is composed of a combination of an insulating dielectric shell and a cavity.
  • the present invention also provides a semiconductor device, which includes any one of the above-mentioned semiconductor base structures.
  • the semiconductor device includes one or a combination of MEMS devices or integrated circuit devices.
  • the semiconductor base structure of the present invention includes the substrate, the conductive pillar, the lateral insulating layer and the vertical insulating layer.
  • the conductive pillars can be positioned above and below the substrate.
  • the lateral insulating layer can achieve isolation of component structures located on the upper and lower surfaces of the substrate, and the vertical insulating layer can electrically insulate the conductive pillars from the substrate.
  • the semiconductor base structure of the present invention can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, and is suitable for high-temperature processes. It can be used as the base structure of integrated circuit devices, such as CMOS, to realize interconnection between component structures in the circuit. Isolate and reduce the parasitic capacitance between transistors or leads, and enhance the radiation resistance of the device; it can also be used in the design of MEMS devices to realize the electrical extraction of the device, simplify the packaging structure of the device, and enhance the arraying capability of the device; it can also be used for example, CMOS-MEMS monolithic integrated devices improve device integration, reduce crosstalk between IC circuits and MEMS devices, and improve substrate utilization.
  • FIG. 1 shows a schematic structural diagram of a semiconductor base structure provided in Embodiment 1 of the present invention.
  • FIG. 2 shows a partial top view of the semiconductor substrate structure in FIG. 1 .
  • FIG. 3 shows another partial top structural schematic diagram of the semiconductor base structure in FIG. 1 .
  • FIG. 4 shows a schematic structural diagram of a semiconductor base structure provided in Embodiment 2 of the present invention.
  • FIG. 5 shows a schematic structural diagram of an integrated circuit device provided in Embodiment 3 of the present invention.
  • FIG. 6 shows a schematic structural diagram of the MEMS device provided in Embodiment 4 of the present invention.
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • an element is referred to as being “mounted on” or “disposed on” another element, it can be directly on the other element or indirectly on the other element.
  • a component is said to be “connected to” another component component, which may be directly connected to another component or indirectly connected to the other component.
  • illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
  • this embodiment provides a semiconductor base structure, which includes a substrate 100 , a lateral insulating layer 101 , a conductive pillar 102 and a vertical insulating layer 103 .
  • the substrate 100 includes a first side and an opposite second side; the conductive pillar 102 penetrates from the first side of the substrate 100 to the second side of the substrate 100 to expose the conductive pillar 102 . Opposite ends of the pillar 102, so that vertical electrical conduction between the upper and lower surfaces of the substrate 100 can be achieved through the conductive pillar 102; the lateral insulating layer 101 is located in the substrate 100, along the lateral direction of the substrate 100 The spaced arrangement is as shown in Figure 2, or the continuous arrangement along the lateral direction of the substrate 100 is as shown in Figure 3.
  • the lateral insulating layer 101 can be used to isolate the component structures on the upper and lower surfaces of the substrate 100, and can Define the distance from the lateral insulating layer 101 to the upper and lower surfaces of the substrate 100; the vertical insulating layer 103 is located in the substrate 100, arranged at vertical intervals along the substrate 100, from the The first surface of the substrate 100 penetrates to the second surface of the substrate 100 and surrounds the periphery of the conductive pillar 102.
  • the vertical insulating layer 103 can realize the connection between the conductive pillar 102 and the substrate.
  • the semiconductor base structure has good mechanical properties and electrical properties.
  • the material of the substrate 100 may include one or a combination of monocrystalline silicon, polycrystalline silicon, silicon carbide, diamond, and III-V semiconductors.
  • the material of the substrate 100 can be selected according to needs.
  • the substrate 100 can be a single-layer substrate, such as a single-crystal silicon substrate, a polycrystalline silicon substrate, a silicon carbide substrate, a diamond substrate, and III.
  • the substrate 100 is a composite laminated substrate, that is, it is composed of a stack combination of two or more different material layers, wherein the thickness of the substrate 100 is preferably 100 ⁇ m to 800 ⁇ m, such as 100 ⁇ m, 200 ⁇ m, 400 ⁇ m, 600 ⁇ m, 800 ⁇ m, etc., which can be selected according to needs.
  • the specific material and structure of the substrate 100 are not excessively limited here.
  • the material of the lateral insulating layer 101 may include one of oxide, nitride, carbide and polymer. or a combination thereof; the material of the vertical insulating layer 103 may include one or a combination of oxides, nitrides, carbides, and polymers; wherein the oxide may include silicon oxide, and the nitride may include nitride. Silicon and carbide may include silicon carbide.
  • the material of the lateral insulating layer 101 may be the same as or different from the material of the vertical insulating layer 103, which is not excessively limited here.
  • the specific types, sizes, distribution and morphology of the horizontal insulating layer 101 and the vertical insulating layer 103 can be selected according to needs, and are not overly limited here.
  • the angle between the lateral insulating layer 101 and the vertical insulating layer 103 includes 30° to 150°.
  • the lateral insulating layer 101 is arranged along the horizontal direction of the substrate 100, and the vertical insulating layer 103 is arranged vertically to the lateral insulating layer 101, so that the There is a vertical angle between the lateral insulating layer 101 and the vertical insulating layer 103, but it is not limited to this.
  • the included angle between the lateral insulating layer 101 and the vertical insulating layer 103 can also be For example, 30°, 45°, 60°, 135°, 150°, etc., in order to provide a flexible 3D interconnection semiconductor substrate, regarding the angle between the lateral insulating layer 101 and the vertical insulating layer 103
  • the value of is not excessively restricted here.
  • the material of the conductive pillar 102 may include one or a combination of monocrystalline silicon, polycrystalline silicon, silicon dioxide, and silicon nitride; wherein the resistivity of the conductive pillar 102 is less than 5 ⁇ 10 -3 ⁇ . ⁇ cm.
  • the material of the conductive pillar 102 is selected to be doped with a silicon-based material, thereby providing the conductive pillar 102 with a smaller resistivity for electrical connection, wherein the resistivity of the conductive pillar 102 is preferably less than 5 ⁇ 10 -3 ⁇ cm, such as 4.5 ⁇ 10 -3 ⁇ cm, 2 ⁇ 10 -3 ⁇ cm, 1 ⁇ 10 -3 ⁇ cm, etc.
  • the material of the conductive pillar 102 is selected to be doped with silicon instead of metal, such as copper metal, which can enable the semiconductor base structure to have a larger temperature adaptation range on the basis of satisfying the electrical connection, thereby enabling the
  • the semiconductor base structure is suitable for high-temperature environments, such as processing processes above 700°C in semiconductor processes, such as processing environments of 700°C, 800°C, 900°C, 1000°C, 1200°C, etc. Of course, the semiconductor base structure can also be applied to normal temperatures. Or low temperature environment, such as 25°C, 100°C, 200°C, 400°C, 500°C, 600°C, etc.
  • the cross-sectional shape of the conductive pillar 102 may include one or a combination of circular, elliptical, arcuate and polygonal shapes; the cross-sectional shape of the lateral insulating layer 101 may include circular, elliptical , one or a combination of arcs and polygons; the cross-sectional shape of the vertical insulation layer 103 may include one or a combination of circles, ellipses, arcs and polygons.
  • the cross-sectional shape of the conductive pillar 102 can be circular, elliptical, arc, triangle, quadrilateral, hexagonal, etc. as needed; similarly, the lateral insulating layer
  • the cross-sectional shape of the vertical insulating layer 101 may include circles, ovals, arcs, triangles, quadrilaterals, hexagons, etc.; the cross-sectional shape of the vertical insulating layer 103 may also include circles, ellipses, arcs, Triangles, quadrilaterals, hexagons, etc. can be selected according to needs, and there are no excessive restrictions here.
  • the semiconductor base structure in this embodiment can provide the substrate 100 through the lateral insulating layer 101
  • the isolation layer in the lateral direction reduces the leakage current of the device, strengthens the radiation characteristics of the device, and can be used as an etching stop layer to ensure the uniformity of etching; through the conductive pillar 102 and the vertical insulating layer 103 While implementing vertical electrical interconnection, the applicable temperature range of the semiconductor base structure can be expanded, especially for high-temperature processes; the lateral insulating layer 101 and the vertical insulating layer 103 arranged at intervals can also make the semiconductor base structure
  • the structure has good mechanical properties and electrical properties.
  • this embodiment provides a semiconductor base structure.
  • the lateral insulating layer 101 in the semiconductor base structure is composed of an insulating dielectric shell 1011 and a cavity 1012 .
  • the materials and structures of the substrate 100, the conductive pillars 102 and the vertical insulating layer 103 in the semiconductor base structure can be referred to the first embodiment, and will not be described again here.
  • the material of the insulating dielectric shell 1011 may be the same as the lateral insulating layer in Embodiment 1, such as one or a combination of oxide and silicon nitride.
  • the oxide may include silicon oxide, aluminum oxide, etc. , one or a combination of titanium oxide, hafnium oxide, etc.
  • the cavity 1012 can be a vacuum sealed cavity, and the vacuum degree of the cavity 1012 can be set as needed.
  • the cavity 1012 can also be a sealed cavity only, or an open cavity, where Don't be overly restrictive.
  • the specific size, distribution and morphology of the insulating dielectric shell 1011 and the cavity 1012 can be selected according to needs, and are not overly limited here.
  • this embodiment can make the semiconductor base structure have a good heat dissipation channel through the arrangement of the cavity 1012, and can be applied to devices such as integrated circuits, such as CMOS and MEMS, to expand the Application scope of the semiconductor base structure.
  • devices such as integrated circuits, such as CMOS and MEMS, to expand the Application scope of the semiconductor base structure.
  • this embodiment provides a semiconductor device that adopts the semiconductor base structure in Embodiment 1.
  • the semiconductor device includes the semiconductor base structure, an integrated circuit element 110 located on the first side of the substrate 100, such as CMOS, and a rewiring layer 113 located on the second side of the substrate 100. and an electrical lead-out electrode 114 electrically connected to the rewiring layer 113 to perform vertical electrical conduction through the semiconductor base structure.
  • the types of device elements provided on the semiconductor base structure are not limited to this. They can be passive elements, such as resistors, capacitors, etc., of course, they can also be active elements, such as MEMS elements, or a combination of integrated circuit elements and MEMS elements. Combination etc.
  • the position of the rewiring layer 113 is not limited to this.
  • the rewiring layer 113 can also be disposed on the first side of the semiconductor base structure or on both opposite sides of the semiconductor base structure. There is no limitation here. , which can be set as needed.
  • this embodiment provides a semiconductor device that adopts the semiconductor base structure having a cavity 1012 in Embodiment 2.
  • the semiconductor device includes the semiconductor base structure, a first MEMS element 111 and a second MEMS element 112 located on the first side of the substrate 100, and a rewiring located on the second side of the substrate 100.
  • the layer 113 and the electrical lead-out electrode 114 electrically connected to the rewiring layer 113 enable vertical electrical conduction through the semiconductor base structure.
  • the types of device elements provided on the semiconductor base structure are not limited to this. They can be passive elements, such as resistors, capacitors, etc., of course, they can also be active elements, such as integrated circuit elements, or integrated circuit elements and MEMS elements. combinations, etc.
  • the position of the rewiring layer 113 is not limited to this.
  • the rewiring layer 113 can also be disposed on the first side of the semiconductor base structure or on both opposite sides of the semiconductor base structure. There is no limitation here. , which can be set as needed.
  • the semiconductor base structure of the present invention includes the substrate, the conductive pillar, the lateral insulating layer and the vertical insulating layer.
  • the conductive pillar located on the substrate can be realized.
  • Vertical electrical conduction of the upper and lower surfaces can be achieved through the lateral insulating layer to achieve isolation of component structures located on the upper and lower surfaces of the substrate, and the vertical insulating layer can be used to electrically insulate the conductive pillars from the substrate.
  • the semiconductor base structure of the present invention can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, and is suitable for high-temperature processes. It can be used as the base structure of integrated circuit devices, such as CMOS, to realize interconnection between component structures in the circuit. Isolate and reduce the parasitic capacitance between transistors or leads, and enhance the radiation resistance of the device; it can also be used in the design of MEMS devices to realize the electrical extraction of the device, simplify the packaging structure of the device, and enhance the arraying capability of the device; it can also be used for example, CMOS-MEMS monolithic integrated devices improve device integration, reduce crosstalk between IC circuits and MEMS devices, and improve substrate utilization.

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Abstract

本发明提供一种半导体基底结构及器件，包括衬底、导电柱、横向绝缘层和竖向绝缘层，通过导电柱可以实现垂直电学导通，通过横向绝缘层及竖向绝缘层可实现电学绝缘；本发明的半导体基底结构可实现3D互联，具有工艺兼容性强、设计灵活、适于高温工艺等优点，可作为集成电路器件的基底结构，以实现电路元件结构间的隔离、减少晶体管间或引线间的寄生电容，增强器件的抗辐照能力；也可用于MEMS器件的设计，实现器件的电学引出，简化器件的封装结构，增强器件的阵列化能力；亦可用于例如CMOS-MEMS单片集成器件，提高器件集成度、减少IC电路和MEMS器件之间的串扰，提高衬底利用率。

Description

半导体基底结构及器件 技术领域
本发明属于半导体技术领域，涉及一种半导体基底结构及器件。
背景技术
在半导体领域中，通常采用单晶硅材料作为衬底，并基于该单晶硅衬底制备各种半导体器件。但是，单晶硅衬底也有一些技术局限性，因此，绝缘体上硅(Silicon on Insulator,SOI)衬底因具有中间绝缘层，可在IC集成电路中提供电隔离层、减少器件的漏电流、加固器件辐照特性，以及在MEMS工艺中，可提供刻蚀停止层，增加工艺均一性等被作为一种功能型衬底广泛使用。但是，现有的常规的SOI衬底只包含水平绝缘层，不能进行垂直方向的电学导通。
随着半导体器件集成度的提升，越来越多的半导体器件需要进行垂直电互联，也就是需要将位于衬底正反两面的元件或结构经过衬底本身进行电学互联。现有进行垂直电互联的做法通常为采用硅通孔(Through Silicon Vias,TSV)衬底来实现。但是，现有的硅通孔技术，大多通过在衬底上刻蚀深孔与电镀金属填充的方式来实现，这样的硅通孔衬底，一是只适用于500℃以下的低温工艺，大多用作电学封装衬底，不能兼容700℃以上的前道高温工艺；二是只含垂直绝缘与导通结构，不具有SOI衬底的优势。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种半导体基底结构及器件，用于解决现有技术中衬底应用局限性的问题。
为实现上述目的及其他相关目的，本发明提供一种半导体基底结构，所述半导体基底结构包括：
衬底，所述衬底包括第一面及相对的第二面；
导电柱，所述导电柱自所述衬底的第一面贯穿至所述衬底的第二面；
横向绝缘层，所述横向绝缘层位于所述衬底中，沿所述衬底的横向间隔排布或连续排布；
竖向绝缘层，所述竖向绝缘层位于所述衬底中，沿所述衬底的竖向间隔排布，自所述衬底的第一面贯穿至所述衬底的第二面并位于所述导电柱的外围，且所述竖向绝缘层与所述横向绝缘层之间具有间距。
可选地，所述导电柱的材料包括单晶硅、多晶硅、二氧化硅、氮化硅中的一种或组合； 所述导电柱的电阻率小于5×10-3Ω·cm。
可选地，所述衬底的材料包括单晶硅、多晶硅、碳化硅、金刚石及Ⅲ-Ⅴ族半导体中的一种或组合；所述衬底的厚度包括100μm～800μm。
可选地，所述横向绝缘层与所述竖向绝缘层之间的夹角包括30°～150°。
可选地，所述导电柱的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合；所述横向绝缘层的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合；所述竖向绝缘层的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合。
可选地，所述横向绝缘层的材料包括氧化物、氮化物、碳化物及聚合物中的一种或组合；所述竖向绝缘层的材料包括氧化物、氮化物、碳化物及聚合物中的一种或组合；其中，所述氧化物包括氧化硅、氮化物包括氮化硅、碳化物包括碳化硅。
可选地，所述半导体基底结构所适用的工艺温度包括25℃～1200℃。
可选地，在任一上述的半导体基底结构中所述横向绝缘层由绝缘介质壳体和空腔组合构成。
本发明还提供一种半导体器件，所述半导体器件包括任一上述的半导体基底结构。
可选地，所述半导体器件包括MEMS器件或集成电路器件中的一种或组合。
如上所述，本发明的所述半导体基底结构包括所述衬底、所述导电柱、所述横向绝缘层和所述竖向绝缘层，通过所述导电柱可以实现位于所述衬底的上下表面的垂直电学导通，通过所述横向绝缘层可以实现位于所述衬底上下表面的元件结构的隔离，通过所述竖向绝缘层可以将所述导电柱与所述衬底电学绝缘。
本发明的所述半导体基底结构，可实现3D互联，具有工艺兼容性强、设计灵活、适于高温工艺等优点，可作为集成电路器件的基底结构，如CMOS，以实现电路中元件结构间的隔离、减少晶体管间或引线间的寄生电容，增强器件的抗辐照能力；也可用于MEMS器件的设计，实现器件的电学引出，简化器件的封装结构，增强器件的阵列化能力；亦可用于例如CMOS-MEMS单片集成器件，提高器件集成度、减少IC电路和MEMS器件之间的串扰，提高衬底利用率。
附图说明
图1显示为本发明实施例一中提供的半导体基底结构的结构示意图。
图2显示为图1中半导体基底结构的一种局部俯视结构示意图。
图3显示为图1中半导体基底结构的另一种局部俯视结构示意图。
图4显示为本发明实施例二中提供的半导体基底结构的结构示意图。
图5显示为本发明实施例三中提供的集成电路器件的结构示意图。
图6显示为本发明实施例四中提供的MEMS器件的结构示意图。
元件标号说明
100            衬底
101            横向绝缘层
1011           绝缘介质壳体
1012           空腔
102            导电柱
103            竖向绝缘层
110            集成电路元件
111            第一MEMS元件
112            第二MEMS元件
113            重新布线层
114            电学引出电极
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。其中，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元 件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
此处可能使用诸如“介于……之间”，该表达表示包括两端点值，以及可能使用诸如“多个”，该表达表示两个或两个以上，除非另有明确具体的限定。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，其组件布局型态也可能更为复杂。
实施例一
参阅图1，本实施例提供一种半导体基底结构，所述半导体基底结构包括衬底100、横向绝缘层101、导电柱102及竖向绝缘层103。
其中，所述衬底100包括第一面及相对的第二面；所述导电柱102自所述衬底100的第一面贯穿至所述衬底100的第二面，以显露所述导电柱102的相对两端，从而通过所述导电柱102可实现所述衬底100上下表面垂直电学导通；所述横向绝缘层101位于所述衬底100中，沿所述衬底100的横向间隔排布如图2所示，或沿所述衬底100的横向连续排布如图3所示，通过所述横向绝缘层101可用于隔离所述衬底100上下表面的元件结构，并可定义所述横向绝缘层101至所述衬底100的上下表面的距离；所述竖向绝缘层103位于所述衬底100中，沿所述衬底100的竖向间隔排布，自所述衬底100的第一面贯穿至所述衬底100的第二面，并环绕于所述导电柱102的外围，通过所述竖向绝缘层103可实现所述导电柱102与所述衬底100间的电学绝缘，且所述竖向绝缘层103与所述横向绝缘层101之间具有间距，即所述横向绝缘层101与所述竖向绝缘层103相互独立无接触设置，从而可使得所述半导体基底结构具有良好的力学性能及电学性能。
作为示例，所述衬底100的材料可包括如单晶硅、多晶硅、碳化硅、金刚石及Ⅲ-Ⅴ族半导体中的一种或组合。
具体的，所述衬底100的材质可根据需要进行选择，如所述衬底100可为单层衬底，如单晶硅衬底、多晶硅衬底、碳化硅衬底、金刚石衬底及Ⅲ-Ⅴ族半导体衬底中的任一种，或所述衬底100为复合叠层衬底，即由两种或更多种不同材质层堆叠组合构成，其中，优选所述衬底100的厚度为100μm～800μm，如100μm、200μm、400μm、600μm、800μm等，具体可根据需要进行选择，关于所述衬底100的具体材质及结构，此处不作过分限制。
作为示例，所述横向绝缘层101的材料可包括氧化物、氮化物、碳化物及聚合物中的一 种或组合；所述竖向绝缘层103的材料可包括氧化物、氮化物、碳化物及聚合物中的一种或组合；其中，所述氧化物可包括氧化硅、氮化物可包括氮化硅、碳化物可包括碳化硅。
具体的，所述横向绝缘层101的材料可与所述竖向绝缘层103的材料选择相同或不同，此处不作过分限制。所述横向绝缘层101与所述竖向绝缘层103的具体种类、尺寸、分布及形貌均可根据需要进行选择，此处不作过分限定。
作为示例，所述横向绝缘层101与所述竖向绝缘层103之间的夹角包括30°～150°。
具体的，为缩短传输路径、降低损耗，优选所述横向绝缘层101沿所述衬底100的水平方向设置，且所述竖向绝缘层103与所述横向绝缘层101垂直设置，以使得所述横向绝缘层101与所述竖向绝缘层103之间具有垂直夹角，但并非局限于此，根据需要，所述横向绝缘层101与所述竖向绝缘层103之间的夹角也可为如30°、45°、60°、135°、150°等，以便于提供可灵活变化的3D互联的半导体基底，关于所述横向绝缘层101与所述竖向绝缘层103之间夹角的取值此处不作过分限制。
作为示例，所述导电柱102的材料可包括如单晶硅、多晶硅、二氧化硅、氮化硅中的一种或组合；其中，所述导电柱102的电阻率小于5×10-3Ω·cm。
具体的，所述导电柱102的材质选择掺杂硅基材质，从而可提供电阻率较小的以便进行电性连接的所述导电柱102，其中，所述导电柱102的电阻率优选小于5×10-3Ω·cm，如4.5×10-3Ω·cm、2×10-3Ω·cm、1×10-3Ω·cm等。所述导电柱102的材质选择掺杂硅基而非金属，如铜金属，其可在满足电性连接的基础上，使得所述半导体基底结构具有较大的温度适应范围，从而可使得所述半导体基底结构适用于高温环境，如半导体工艺中700℃以上的加工工艺，如加工环境为700℃、800℃、900℃、1000℃、1200℃等，当然所述半导体基底结构也可适用于常温或低温环境，如25℃、100℃、200℃、400℃、500℃、600℃等。
作为示例，所述导电柱102的横截面的形状可包括圆形、椭圆形、弧形和多边形中的一种或组合；所述横向绝缘层101的横截面的形状可包括圆形、椭圆形、弧形和多边形中的一种或组合；所述竖向绝缘层103的横截面的形状可包括圆形、椭圆形、弧形和多边形中的一种或组合。
具体的，如图2及图3，根据需要所述导电柱102的横截面的形状可为圆形、椭圆形、弧形、三角形、四边形、六边形等；同理，所述横向绝缘层101的横截面的形状可包括圆形、椭圆形、弧形、三角形、四边形、六边形等；所述竖向绝缘层103的横截面的形状也可可包括圆形、椭圆形、弧形、三角形、四边形、六边形等，具体可根据需要进行选择，此处不作过分限制。本实施例中的所述半导体基底结构通过所述横向绝缘层101可提供所述衬底100 在横向上的隔离层、减少器件的漏电流、加固器件辐照特性，且可作为刻蚀停止层应用，以保障刻蚀的均一性；通过所述导电柱102及所述竖向绝缘层103可在实行垂直电互联的同时，扩大所述半导体基底结构的适用温区范围，尤其是高温工艺；间隔设置的所述横向绝缘层101与所述竖向绝缘层103还可使得所述半导体基底结构具有良好的力学性能及电学性能。
实施例二
参阅图4，本实施例提供一种半导体基底结构，与实施例一的不同之处主要在于：该半导体基底结构中所述横向绝缘层101由绝缘介质壳体1011和空腔1012组合构成。本实施例中，所述半导体基底结构中的衬底100、导电柱102及竖向绝缘层103的材质、结构等均可参阅实施例一，此处不作赘述。
其中，所述绝缘介质壳体1011的材质可同实施例一中的所述横向绝缘层，如氧化物及氮化硅中的一种或组合，所述氧化物可包括如氧化硅、氧化铝、氧化钛、氧化铪中的一种或组合等。所述空腔1012可为真空密封空腔，所述空腔1012的真空度可根据需要进行设置，当然所述空腔1012也可仅为密封空腔，或为开口式的空腔，此处不作过分限定。关于所述绝缘介质壳体1011和所述空腔1012的具体尺寸、分布及形貌均可根据需要进行选择，此处不作过分限定。
本实施例在实施例一的基础上通过所述空腔1012的设置，可使得所述半导体基底结构具有良好的散热通道，且可适用于如集成电路，如CMOS以及MEMS等器件中，以扩大所述半导体基底结构的应用范围。
实施例三
参阅图5，本实施例提供一种半导体器件，所述半导体器件采用实施例一中的所述半导体基底结构。其中，所述半导体器件包括所述半导体基底结构，以及位于所述衬底100的第一面的集成电路元件110，如CMOS等，以及位于所述衬底100的第二面的重新布线层113及与所述重新布线层113电连接的电学引出电极114，以通过所述半导体基底结构进行垂直方向的电学导通。
关于所述半导体基底结构上设置的器件元件的种类并非局限于此，其可为无源元件，如电阻、电容等，当然也可为有源元件如MEMS元件，或集成电路元件与MEMS元件的组合等。所述重新布线层113的位置也并非局限于此，如所述重新布线层113也可设置于所述半导体基底结构的第一面或同时位于所述半导体基底结构的相对两面，此处不作限定，可根据需要进行设置。
实施例四
参阅图6，本实施例提供一种半导体器件，所述半导体器件采用实施例二中的具有空腔1012的所述半导体基底结构。其中，所述半导体器件包括所述半导体基底结构，位于所述衬底100的第一面的第一MEMS元件111、第二MEMS元件112，以及位于所述衬底100的第二面的重新布线层113及与所述重新布线层113电连接的电学引出电极114，以通过所述半导体基底结构进行垂直方向的电学导通。
关于所述半导体基底结构上设置的器件元件的种类并非局限于此，其可为无源元件，如电阻、电容等，当然也可为有源元件如集成电路元件，或集成电路元件与MEMS元件的组合等。所述重新布线层113的位置也并非局限于此，如所述重新布线层113也可设置于所述半导体基底结构的第一面或同时位于所述半导体基底结构的相对两面，此处不作限定，可根据需要进行设置。
综上所述，本发明的所述半导体基底结构包括所述衬底、所述导电柱、所述横向绝缘层和所述竖向绝缘层，通过所述导电柱可以实现位于所述衬底的上下表面的垂直电学导通，通过所述横向绝缘层可以实现位于所述衬底上下表面的元件结构的隔离，通过所述竖向绝缘层可以将所述导电柱与所述衬底电学绝缘。
本发明的所述半导体基底结构，可实现3D互联，具有工艺兼容性强、设计灵活、适于高温工艺等优点，可作为集成电路器件的基底结构，如CMOS，以实现电路中元件结构间的隔离、减少晶体管间或引线间的寄生电容，增强器件的抗辐照能力；也可用于MEMS器件的设计，实现器件的电学引出，简化器件的封装结构，增强器件的阵列化能力；亦可用于例如CMOS-MEMS单片集成器件，提高器件集成度、减少IC电路和MEMS器件之间的串扰，提高衬底利用率。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种半导体基底结构，其特征在于，所述半导体基底结构包括：
    衬底，所述衬底包括第一面及相对的第二面；
    导电柱，所述导电柱自所述衬底的第一面贯穿至所述衬底的第二面；
    横向绝缘层，所述横向绝缘层位于所述衬底中，沿所述衬底的横向间隔排布或连续排布；
    竖向绝缘层，所述竖向绝缘层位于所述衬底中，沿所述衬底的竖向间隔排布，自所述衬底的第一面贯穿至所述衬底的第二面并位于所述导电柱的外围，且所述竖向绝缘层与所述横向绝缘层之间具有间距。
  2. 根据权利要求1所述的半导体基底结构，其特征在于：所述导电柱的材料包括单晶硅、多晶硅、二氧化硅、氮化硅中的一种或组合；所述导电柱的电阻率小于5×10-3Ω·cm。
  3. 根据权利要求1所述的半导体基底结构，其特征在于：所述衬底的材料包括单晶硅、多晶硅、碳化硅、金刚石及Ⅲ-Ⅴ族半导体中的一种或组合；所述衬底的厚度包括100μm～800μm。
  4. 根据权利要求1所述的半导体基底结构，其特征在于：所述横向绝缘层与所述竖向绝缘层之间的夹角包括30°～150°。
  5. 根据权利要求1所述的半导体基底结构，其特征在于：所述导电柱的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合；所述横向绝缘层的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合；所述竖向绝缘层的横截面的形状包括圆形、椭圆形、弧形和多边形中的一种或组合。
  6. 根据权利要求1所述的半导体基底结构，其特征在于：所述横向绝缘层的材料包括氧化物、氮化物、碳化物及聚合物中的一种或组合；所述竖向绝缘层的材料包括氧化物、氮化物、碳化物及聚合物中的一种或组合；其中，所述氧化物包括氧化硅、氮化物包括氮化硅、碳化物包括碳化硅。
  7. 根据权利要求1所述的半导体基底结构，其特征在于：所述半导体基底结构所适用的工艺温度包括25℃～1200℃。
  8. 根据权利要求1～7中任一所述的半导体基底结构，其特征在于：所述横向绝缘层由绝缘介质壳体和空腔组合构成。
  9. 一种半导体器件，其特征在于：所述半导体器件包括权利要求1～8中任一所述半导体基底结构。
  10. 根据权利要求9所述的半导体器件，其特征在于：所述半导体器件包括MEMS器件或集成电路器件中的一种或组合。
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