TWI809551B - 具有散熱單元的半導體元件及其製備方法 - Google Patents

具有散熱單元的半導體元件及其製備方法 Download PDF

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TWI809551B
TWI809551B TW110141131A TW110141131A TWI809551B TW I809551 B TWI809551 B TW I809551B TW 110141131 A TW110141131 A TW 110141131A TW 110141131 A TW110141131 A TW 110141131A TW I809551 B TWI809551 B TW I809551B
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bonding layer
semiconductor
grain structure
layer
semiconductor device
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TW110141131A
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TW202230658A (zh
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施信益
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南亞科技股份有限公司
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    • H01L2225/06589—Thermal management, e.g. cooling
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Abstract

本揭露提供一種具有散熱單元的半導體元件及該半導體元件的製備方法。該半導體元件具有一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構。該載體結構包括一載體基底以及多個半導體貫穿通孔，該載體基底設置在該中介接合層上，該等半導體貫穿通孔設置在該載體基底中以及在該中介接合層上，以進行導熱。

Description

具有散熱單元的半導體元件及其製備方法
本申請案主張2021年1月26日申請之美國正式申請案第17/158,337號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露關於一種半導體元件以及該半導體元件的製備方法。特別是有關於一種具有散熱單元的半導體元件，以及具有該散熱單元的該半導體元件之製備方法。
半導體元件使用在不同的電子應用，例如個人電腦、手機、數位相機，或其他電子設備。半導體元件的尺寸逐漸地變小，以符合計算能力所逐漸增加的需求。然而，在尺寸變小的製程期間，增加不同的問題，且如此的問題在數量與複雜度上持續增加。因此，仍然持續著在達到改善品質、良率、效能與可靠度以及降低複雜度方面的挑戰。
上文之「先前技術」說明僅提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件，具有一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構。該載體結構包括一載體基底，設置在該中介接合層上；以及多個半導體貫穿通孔，設置在該載體基底中以及在該中介接合層以進行導熱。
在一些實施例中，該載體結構包括一接合層，設置在該載體基底與該中介接合層之間；以及一導電板，設置在該載體結構的該接合層中並接觸該載體結構的該等半導體貫穿通孔。
在一些實施例中，該晶粒堆疊包括一第一晶粒結構，設置在該中介接合層的下方；以及一第二晶粒結構，設置在該第一晶粒結構下方。
在一些實施例中，該第一晶粒結構與該第二晶粒結構為記憶體晶粒。
在一些實施例中，該第一晶粒結構為一記憶體晶粒，而該第二晶粒結構為一邏輯晶粒。
在一些實施例中，該載體結構之該等半導體貫穿通孔的各上表面與該載體結構的一上表面大致為共面。
在一些實施例中，該載體結構之該等半導體貫穿通孔的各上表面被該載體基底所覆蓋。
在一些實施例中，該第一晶粒結構包括一第一基底，設置在該中介接合層的相反處；一第一介電層，設置在該第一基底與該中介接合層之間；一第一接合層，設置在該第一基底與該第二晶粒結構之間；多個第一互連層，設置在該第一介電層中；該第一晶粒結構的多個半導體貫穿通孔，沿著該第一晶粒結構的該第一基底與該第一接合層設置，並電性 連接該等第一互連層與該第二晶粒結構。該第二晶粒結構包括一第二基底，設置在該第一晶粒結構之該第一接合層的相反處；一第二介電層，設置在該第二基底與該第一晶粒結構的該第一接合層之間；該第二晶粒結構的一第一接合層，設置在該第二基底下方；多個第二互連層，設置在該第二介電層中並電性連接到該第一晶粒結構的該等半導體貫穿通孔；以及該第二晶粒結構的多個半導體貫穿通孔，沿著該第二晶粒結構的該第二基底與該第一接合層而設置，並電性連接到該等第二互連層。
在一些實施例中，該半導體元件還包括多個焊料接頭(solder joints)，電性連接到該第二晶粒結構的該等半導體貫穿通孔。
在一些實施例中，該第一晶粒結構包括一第二接合層，設置在該第一晶粒結構的該第一接合層與該第二介電層之間；以及多個焊墊層(pad layer)，設置在該第二接合層中並電性連接該等第二互連層以及該第一晶粒結構的該等半導體貫穿通孔。
在一些實施例中，該等焊墊層的各寬度大於該第一晶粒結構之該等半導體貫穿通孔的各寬度。
在一些實施例中，該半導體元件還包括多個第一虛擬半導體貫穿通孔，沿著該第一晶粒結構、該第二晶粒結構以及該中介接合層設置。
在一些實施例中，該半導體元件還包括多個第一虛擬半導體貫穿通孔，沿著該第一晶粒結構、該第二晶粒結構以及該中介接合層設置，延伸到該載體結構的該接合層，並熱接觸該導電板。
在一些實施例中，該半導體元件還包括多個第二虛擬半導體貫穿通孔，沿著該中介接合層與該第一介電層設置，並延伸到該第一基 底。
在一些實施例中，該等第一虛擬半導體貫穿通孔的各寬度大於該等第二虛擬半導體貫穿通孔的各寬度。
在一些實施例中，該半導體元件還包括多個第三虛擬半導體貫穿通孔，沿著該第一晶粒結構設置並延伸到該第二晶粒結構。
在一些實施例中，該等第二半導體貫穿通孔大致均勻分布在該第一晶粒結構中。
在一些實施例中，該半導體元件還包括一熱界面層，設置在該中介接合層與該載體結構的該接合層之間，其中該熱界面層(thermal interface layer)包含充滿一可撓性材料的一碳材料。
在一些實施例中，該載體結構包括一接合層，設置在該載體基底與該中介接合層之間；以及多個導電鰭片，設置在該載體結構的該接合層中並與該載體結構的該等半導體貫穿通孔接觸。
本揭露之另一實施例提供一種半導體元件的製備方法，包括提供一載體基底；形成多個半導體貫穿通孔載該載體基底中以進行導熱；形成一接合層在該載體基板上；提供一第一晶粒結構，該第一晶粒結構包括多個半導體貫穿通孔；形成一中介接合層在該第一晶粒結構上；經由該中介接合層將該第一晶粒結構接合到該載體結構的該接合層上；以及將一第二晶粒結構接合到該第一晶粒結構上。該載體基底、該等半導體貫穿通孔以及該接合層一起配置成一載體結構。該第二晶粒結構與該第一晶粒結構藉由該等半導體貫穿通孔而電性耦接。
由於本揭露該半導體元件的設計，在該半導體元件操作期間所累積的熱可經由該等導電板以及該等半導體貫穿通孔而導熱到周圍。 意即，可改善該半導體元件的導熱能力。因此，可改善該半導體元件的效能。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:製備方法
1A:半導體元件
1B:半導體元件
1C:半導體元件
1D:半導體元件
1E:半導體元件
1F:半導體元件
1G:半導體元件
1H:半導體元件
1I:半導體元件
1J:半導體元件
1K:半導體元件
1L:半導體元件
1M:半導體元件
1N:半導體元件
100:第一晶粒結構
101:第一基底
103:第一介電層
105:第一互連層
107:第一接合層
109:半導體貫穿通孔
111:焊墊層
113:第二接合層
200:第二晶粒結構
201:第二基底
203:第二介電層
205:第二互連層
207:第一接合層
209:半導體貫穿通孔
211:焊墊層
213:第二接合層
300:第三晶粒結構
309:半導體貫穿通孔
311:焊墊層
313:第二接合層
400:第四晶粒結構
409:半導體貫穿通孔
500:載體結構
501:載體基底
501TS:上表面
503:通孔開孔
505:半導體貫穿通孔
505TS:上表面
507:導電板
509:接合層
511:導電鰭片
601:中介接合層
603:焊料接頭
605:第一虛擬半導體貫穿通孔
607:第二虛擬半導體貫穿通孔
609:第三虛擬半導體貫穿通孔
611:熱界面層
613:覆蓋層
615:第一虛擬導電層
617:第二虛擬導電層
AL:黏著層
BL:阻障層
FL:填充層
HDU:散熱單元
IL:絕緣層
S11:步驟
S13:步驟
S15:步驟
SL:晶種層
W1:寬度
W2:寬度
W3:寬度
W4:寬度
W5:寬度
W6:寬度
W7:寬度
Z:方向
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號指相同的元件。
圖1是流程示意圖，例示本揭露一實施例之半導體元件的製備方法。
圖2及圖3是剖視示意圖，例示本揭露一實施例之製備半導體元件的一部分流程。
圖4是放大剖視示意圖，例示本揭露一實施例之一中間半導體元件。
圖5及圖6是放大剖視示意圖，例示本揭露一實施例之各中間半導體元件。
圖7到圖15是剖視示意圖，例示本揭露一實施例之製備半導體元件的一部分流程。
圖16到圖20是剖視示意圖，例示本揭露一些實施例之各半導體元件。
圖21及圖22是剖視示意圖，例示本揭露另一實施例之製備半導體元 件的一流程。
圖23到圖26是剖視示意圖，例示本揭露另一實施例之製備半導體元件的一流程。
圖27及圖28是剖視示意圖，例示本揭露另一實施例之製備半導體元件的一流程。
圖29是剖視示意圖，例示本揭露另一實施例之半導體元件。
圖30及圖31是剖視示意圖，例示本揭露另一實施例之製備半導體元件的一流程。
圖32到圖34是剖視示意圖，例示本揭露另一實施例之各半導體元件。
以下描述了組件和配置的具體範例，以簡化本揭露之實施例。當然，這些實施例僅用以例示，並非意圖限制本揭露之範圍。舉例而言，在敘述中第一部件形成於第二部件之上，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不會直接接觸的實施例。另外，本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚，除非內文中特別說明，其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取 向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
應當理解，當形成一個部件在另一個部件之上(on)、與另一個部件相連(connected to)、及/或與另一個部件耦合(coupled to)，其可能包含形成這些部件直接接觸的實施例，並且也可能包含形成額外的部件介於這些部件之間，使得這些部件不會直接接觸的實施例。
應當理解，儘管這裡可以使用術語第一，第二，第三等來描述各種元件、部件、區域、層或區段(sections)，但是這些元件、部件、區域、層或區段不受這些術語的限制。相反，這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此，在不脫離本發明進步性構思的教導的情況下，下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。
除非內容中另有所指，否則當代表定向(orientation)、布局(layout)、位置(location)、形狀(shapes)、尺寸(sizes)、數量(amounts)，或其他量測(measures)時，則如在本文中所使用的例如「同樣的(same)」、「相等的(equal)」、「平坦的(planar)」，或是「共面的(coplanar)」等術語(terms)並非必要意指一精確地完全相同的定向、布局、位置、形狀、尺寸、數量，或其他量測，但其意指在可接受的差異內，包含差不多完全相同的定向、布局、位置、形狀、尺寸、數量，或其他量測，而舉例來說，所述可接受的差異可因為製造流程(manufacturing processes)而發生。術語「大致地(substantially)」可被使用在本文中，以表現出此意思。舉例來說，如大致地相同的(substantially the same)、大 致地相等的(substantially equal)，或是大致地平坦的(substantially planar)，為精確地相同的、相等的，或是平坦的，或者是其可為在可接受的差異內的相同的、相等的，或是平坦的，而舉例來說，所述可接受的差異可因為製造流程而發生。
在本揭露中，一半導體元件通常意指可藉由利用半導體特性(semiconductor characteristics)運行的一元件，而一光電元件(electro-optic device)、一發光顯示元件(light-emitting display device)、一半導體線路(semiconductor circuit)以及一電子元件(electronic device)，均包括在半導體元件的範疇中。
應當理解，在本揭露的描述中，上方(above)(或之上(up))對應Z方向箭頭的該方向，而下方(below)(或之下(down))對應Z方向箭頭的相對方向。
應當理解，在本揭露的描述中，一元件(或一特徵)沿著方向Z位在最高垂直位面(level)的一表面，表示成該元件(或該特徵)的一上表面。一元件(或一特徵)沿著方向Z位在最低垂直位面(level)的一表面，表示成該元件(或該特徵)的一下表面。
圖1是流程示意圖，例示本揭露一實施例之半導體元件1A的製備方法10。圖2及圖3是剖視示意圖，例示本揭露一實施例之製備半導體元件1A的一部分流程。圖4是放大剖視示意圖，例示本揭露一實施例之一中間半導體元件。圖5及圖6是放大剖視示意圖，例示本揭露一實施例之各中間半導體元件。圖7到圖15是剖視示意圖，例示本揭露一實施例之製備半導體元件1A的一部分流程。
請參考圖1到圖8，在步驟S11，可提供一載體結構500，而 載體結構500包括一散熱單元HDU。
請參考圖2，可提供一載體基底501，且多個通孔開孔503可形成在載體基底501中。舉例來說，載體基底501可包含矽、鍺、矽鍺、矽碳、矽鍺碳、鎵、砷化鎵、砷化銦、磷化銦(indium phosphorus)或其他IV-IV、III-V或II-VII族半導體材料。
請參考圖2，該等通孔開孔503的各內側壁可稍微呈錐形，例如介於大約85度到大約88度之間，並且平滑以用於如之後將說明的共形及無孔洞材料填充。該等通孔開孔503的各錐形內側壁亦可改善在該等通孔開孔503內之多個金屬離子的擴散，並可減少填充該等通孔開孔503的時間。此外，該等通孔開孔503的各平滑內側壁可有利於減少應力集中。在一些實施例中，該等通孔開孔503的各寬度可介於大約1μm到大約22μm之間，或是介於5μm到15μm之間。在一些實施例中，該等通孔開孔503的各深度可介於大約20μm到大約160μm之間，或是介於大約50μm到大約130μm之間。
舉例來說，該等通孔開孔503的製作技術可包含雷射鑽孔(laser drilling)、噴粉微加工(powder blast micromaching)、深反應離子蝕刻(deep reactive ion etching)或是使用氫氧化物的濕蝕刻，該氫氧化物例如氫氧化鉀(potassium hydroxide)、氫氧化鈉(sodium hydroxide)、氫氧化銣(rubidium hydroxid)、氫氧化銨(ammonium hydroxide)或是四甲基氫氧化銨(tetra methyl ammonium hydroxide)。
請參考圖3，可形成多個半導體貫穿通孔505以完全填滿該等通孔開孔503。通常，該等半導體貫穿通孔505的製作技術可包含襯墊沉積(liner deposition)以及導電材料填充(conductive material filling)。可 執行一平坦化製程，例如化學機械研磨，以提供一大致平坦表面給接下來的處理步驟。在一些實施例中，該等半導體貫穿通孔505的各側壁可大致呈錐形，例如介於大約85度到大約88度之間。在一些實施例中，該等半導體貫穿通孔505的各寬度可介於大約1μm到大約22μm之間，或是介於大約5μm到大約15μm之間。在一些實施例中，該等半導體貫穿通孔505的各深度可介於大約20μm到大約160μm之間，或是介於50μm到大約130μm之間。
為了便於描述，所以僅描述一個半導體貫穿通孔505。請參考圖4，半導體貫穿通孔505可包括一填充層FL、一晶種層SL、一黏著層AL、一阻障層BL以及一絕緣層IL。絕緣層IL可共形形成在通孔開孔503中，並可具有一U形剖面輪廓。在一些實施例中，舉例來說，絕緣層IL可包含氧化矽、氮化矽、氮氧化矽或四乙氧基矽烷(tetra-ethyl ortho-silicate)。絕緣層IL可具有一厚度，介於大約50nm到大約200nm之間。或者是，在一些實施例中，舉例來說，絕緣層IL可包含聚對二甲苯(parylene)、環氧樹脂(epoxy)或聚對茬(poly(p-xylene))。絕緣層IL可具有一厚度，介於大約1μm到大約5μm之間。絕緣層IL可確保填充層FL在載體基底501中電性絕緣。
請參考圖4，阻障層BL可共形形成在絕緣層IL上，並可具有一U形剖面輪廓。舉例來說，阻障層BL可包含鉭、氮化鉭、鈦、氮化鈦、錸、硼化鎳或氮化鉭/鉭之雙層。阻擋層BL可抑制填充層FL的導電材料擴散進入到二絕緣層IL中。阻障層BL的製作技術可包含一沉積製程，例如物理氣相沉積、原子層沉積、化學氣相沉積或噴濺。
請參考圖4，黏著層AL可共形形成在阻障層BL上，並可具 有一U形剖面輪廓。舉例來說，黏著層AL可包含鈦、鉭、鈦鎢或氮化錳。黏著層AL可改善晶種層SL與阻障層BL之間的一黏性。黏著層AL可分別具有一厚度，介於大約5nm到大約50nm之間。二黏著層AL的製作技術可包含一沉積製程，例如物理氣相沉積、原子層沉積、化學氣相沉積或噴濺。
請參考圖4，晶種層SL可共形形成在黏著層AL上，並可具有一U形剖面輪廓。晶種層SL可具有一厚度，介於大約10nm到大約40nm之間。舉例來說，晶種層SL可包含銅或釕。晶種層SL的製作技術可包含一沉積製程，例如物理氣相沉積、原子層沉積、化學氣相沉積或噴濺。在藉由一電鍍製程形成填充層FL期間，晶種層SL可降低通孔開孔503的電阻率(resistivity)。
請參考圖4，填充層FL可形成在晶種層SL上，並完全填滿通孔開孔503。舉例來說，填充層FL可為銅。填充層FL的製作技術可包含使用一鍍覆溶液(plating solution)的一電鍍製程。鍍覆溶液可包括硫酸銅(copper sulfate)、甲烷磺酸銅(copper methane sulfonate)、葡萄糖酸鹽銅(copper gluconate)、氨基磺酸鹽銅(copper sulfamate)、硝酸銅(copper nitrate)、磷酸銅(copper phosphate)或氯化銅(copper chloride)。鍍覆溶液的pH值可介於大約2到大約6之間，或是介於大約3到大約5之間。電鍍製程的製程溫度可維持在大約40℃到大約75℃之間，或是在大約50℃到大約70℃之間。
在一些實施例中，電鍍溶液可包括加速劑(accelerators)、抑制劑(suppressors)和均勻劑(levelers)。加速劑可包括一極性硫、氧或氮功能群，以幫助提升沉積率，並可促進密集成核。加速劑可以一低濃度程 度存在，舉例來說，該低濃度程度介於大約0到大約200ppm之間。抑製劑是降低鍍覆速率的添加劑，且通常以更高的濃度存在於電鍍槽(plating bath)中，例如在約5ppm和約1000ppm之間。抑制劑可為具有高分子量(molecular weight)的聚合界面活性劑(polymeric surfactant)，例如聚乙二醇(polyethylene glycol)。
抑制劑可藉由吸附在表面以及形成一阻障層的銅離子以減慢沉積率。因為其大尺寸與低擴散率，抑制劑不太可能到達通孔開孔503的下部。因此，大部分的抑制效果可發生在通孔開孔503的下部處，以幫助減少填充材料(例如銅)的過載並避免通孔開孔503關閉(closing)。
均勻劑可用於改善填充效能，降低表面粗糙度，並避免在通孔開孔503之上部處的銅沉積。均勻劑可以一小濃度存在，舉例來說，該小濃度介於大約1ppm到大約100ppm之間。舉例來說，均勻劑可為3-mercapto-1-propanesulfonate、(3-sulfopropyl)disulfide或是3,3-thiobis(1-propanesulfonate)。
應當理解，在本揭露中，術語「部位(part)」或「區段(segment)」可與術語「部分(portion)」交叉使用。
在一些實施例中，在填充層FL形成之後，可執行一退火製程(annealing process)。退火製程可減少在接下來之半導體製程期間的抽銅(copper-pumping)的不利影響、改善填充層FL與絕緣層IL之間的黏性，以及穩定填充層FL的微結構。
或者是，請參考圖5，多個覆蓋層613可共形形成在通孔開孔503的上部上，並形成在載體基底501的上表面上。絕緣層IL可共形形成在該等覆蓋層613上以及在該等通孔開孔503中。可形成填充層FL以完 全填滿該等通孔開孔503。應當理解，為了清楚，在圖5中並未顯示阻障層BL、黏著層AL以及晶種層SL。
該等覆蓋層613的製作技術可包含一沉積製程，例如一原子層沉積方法，其精確控制原子層沉積方法之一第一前驅物的數量。舉例來說，該等覆蓋層613可包含氧化鋁、氧化鉿、氧化鋯、氧化鈦、氮化鈦、氮化鎢、氮化矽或氧化矽。
在一些實施例中，當該等覆蓋層613包含氧化鋁時，該原子層沉積方法的該第一前驅物可為三甲基鋁(trimethylaluminum)，而該原子層沉積方法的該第二前驅物可為水或臭氧。
在一些實施例中，當該等覆蓋層613包含氧化鉿時，則該原子層沉積方法的該第一前驅物可為四氯化鉿(hafnium tetrachloride)、三級丁氧化鉿(hafnium tert-butoxide)、二甲基醯胺鉿(hafnium dimethylamide)、甲基乙基醯胺鉿(hafnium ethylmethylamide)、二乙基醯胺鉿(hafnium diethylamide)或甲氧基-三級丁氧化鉿(hafnium methoxy-t-butoxide)，而該原子層沉積方法的該第二前驅物可為水或臭氧。
在一些實施例中，當該等覆蓋層613包含氧化鋯時，則該原子層沉積方法的該第一前驅物可為四氯化鋯(zirconium tetrachloride)，而該原子層沉積方法的該第二前驅物可為水或臭氧。
在一些實施例中，當該等覆蓋層613包含氧化鈦時，則該原子層沉積方法的該第一前驅物可為四氯化鈦(titanium tetrachloride)、鈦酸四乙酯(tetraethyl titanate)、或異丙醇鈦(titanium isopropoxide)，而該原子層沉積方法的該第二前驅物可為水或臭氧。
在一些實施例中，當該等覆蓋層613包含氮化鈦時，則該 原子層沉積方法的該第一前驅物可為四氯化鈦(titanium tetrachloride)及氨水(ammonia)。
在一些實施例中，當該等覆蓋層613包含氮化鎢時，則該原子層沉積方法的該第一前驅物可為六氟化鎢(tungsten hexafluoride)及氨水(ammonia)。
在一些實施例中，當該等覆蓋層613包含氮化矽時，則該原子層沉積方法的該第一前驅物可為矽烯(silylene)、氯、氨水和四氫化二氮(dinitrogen tetrahydride)。
在一些實施例中，當該等覆蓋層613包含氧化矽時，則該原子層沉積方法的該第一前驅物可為矽四異氰酸酯(silicon tetraisocyanate)或CH3OSi(NCO)3，而該原子層沉積方法的該第二前驅物可為氫或臭氧。
由於該等覆蓋層613的存在，所以可降低填充層FL之填充材料在通孔開孔503之各側壁上的沉積率。因此，填充層FL之填充材料在通孔開孔503之各側壁上的沉積率以及填充層FL之填充材料在通孔開孔503之下表面上的沉積率可變得相互接近。結果，可填滿通孔開孔503而不會有任何空孔(void)形成在通孔開孔503之下表面附近。
請參考圖6，可執行一平坦化製程，例如化學機械研磨，以移除多餘材料，提供一大致平坦表面給接下來的處理步驟，並同時形成半導體貫穿通孔505。
請參考圖7，多個導電板507形成在載體基底501上並可相互分隔開。每一個導電板507可連接到其中兩個或更多個半導體貫穿通孔505。舉例來說，該等導電板507包含鎢、鈷、鋯、鉭、鈦、鋁、釕、 銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物或其組合。該等導電板507以及該等半導體貫穿通孔505一起配置成散熱單元HDU。
在一些實施例中，僅一個導電板507可形成在載體基底501上，並可連接到所有的半導體貫穿通孔505。
請參考圖8，一接合層509可形成在載體基底501上並覆蓋該等導電板507。可執行一平坦化製程，例如化學機械研磨，以提供一大致平坦表面給接下來的處理步驟。在一些實施例中，舉例來說，接合層509可包含一非有機材料，選自未摻雜矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、氧化氮化矽及其組合。在一些實施例中，舉例來說，接合層509可包含一聚合物層，例如一環氧樹脂(epoxy)、聚烯亞胺(polyimide)、苯並環丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazole)或類似物。接合層509的製作技術可包含一沉積製程，例如化學氣相沉積、電漿加強氣相沉積、蒸鍍或旋轉塗佈。
請參考圖8，載體基底501、散熱單元HDU以及接合層509一起配置成載體結構500。載體結構500可用於與其他晶粒(或其他晶圓)接合，以形成用於進一步接合程序的一中間堆疊結構。
請參考圖1及圖19到圖13，在步驟S13，一第一晶粒結構100可接合到載體結構500上。
請參考圖9，可提供一第一基底101。第一基底101可包含與載體基底501相同的材料，但並不以此為限。在一些實施例中，舉例來說，第一基底101可包含矽、鍺、矽鍺、矽碳、矽鍺碳、鎵、砷化鎵、砷化銦、磷化銦(indium phosphorus)或其他IV-IV、III-V或II-VII族半導體 材料。多個半導體貫穿通孔109可形成在第一基底101中，且其製作技術可類似於如圖2到圖6描述之該等半導體貫穿通孔505的一程序。
請參考圖9，一第一介電層103可形成在第一基底101上。在一些實施例中，第一介電層103可為一堆疊層結構。第一介電層103可包括複數個第一隔離子層。每一個第一隔離子層可具有一厚度，介於大約0.5μm到大約3.0μm之間。舉例來說，複數個第一隔離子層可包含氧化矽、硼磷矽酸鹽玻璃(borophosphosilicate glass)、未摻雜矽酸鹽玻璃(undoped silicate glass)、氟矽酸鹽玻璃(fluorinated silicate glass)、低介電常數的介電材料、類似物或其組合。複數個第一隔離子層可包含不同材料，但並不以此為限。低介電常數的介電材料可具有一介電常數，其小於3.0或甚至小於2.0。在一些實施例中，低介電常數的介電材料可具有一介電常數，其小於2.0。第一介電層103的製作技術可包含多個沉積製程，例如化學氣相沉積、電漿加強化學氣相沉積、蒸鍍或旋轉塗佈。在該等沉積製程之後，可分別對應執行多個平坦化製程，以移除多餘材料並提供一大致平坦表面給接下來的處理步驟。在第一介電層103形成期間，可形成多個主動元件以及該等第一互連層105。
舉例來說，該等主動元件(圖未示)可為雙極性接面電晶體(bipolar junction transistors)、金屬氧化物半導體場效電晶體、二極體、快閃記憶體、動態隨機存取記憶體、靜態隨機存取記憶體、可抹除可程式唯讀記憶體(erasable programmable read-only memories)、影像感測器、微機電系統、主動元件或被動元件。該等主動元件與該等半導體貫穿通孔109可電性耦接。
請參考圖9，多個第一互連層105可形成在第一介電層103 中。每一個第一互連層105可包括多個導電線、導電通孔、導電接觸點或是著陸墊。舉例來說，該等第一互連層105可包含鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭鎂)、金屬氮化物(例如氮化鈦)、過渡金屬鋁化物或其組合。該等第一互連層105與該等主動元件可電性耦接。
請參考圖9，一中介接合層601可形成在第一介電層103上。中介接合層601可包含與接合層509相同的材料，但並不以此為限。在一些實施例中，舉例來說，中介接合層601可包含一非有機材料，選自未摻雜矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、氧化氮化矽及其組合。在一些實施例中，舉例來說，中介接合層601可包含一聚合物層，例如一環氧樹脂(epoxy)、聚烯亞胺(polyimide)、苯並環丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazole)或類似物。中介接合層601的製作技術可包含一沉積製程，例如化學氣相沉積、電漿加強氣相沉積、蒸鍍或旋轉塗佈。
請參考圖10，在圖9中所描述的中間半導體元件可相反置放並接合到載體基底501上。在一些實施例中，中介接合層601可接合到載體結構500的接合層509上。在接合之後，第一介電層103可設置在中介接合層601上，且第一基底101可設置在第一介電層103上。應當理解，在該等第一互連層105與散熱單元HDU之間並無建立電性連接。
在一些實施例中，舉例來說，當接合層509與中介接合層601包含氧化矽或氮化矽時，接合層509與中介接合層601之間的接合可基於親水性接合(hydrophilic bonding)機制。在接合之前，親水性表面的修改可應用於接合層509與中介接合層601。在一些實施例中，當接合層509 與中介接合層601包含聚合黏著劑時，例如苯並環丁烯(benzocyclobutenes)與聚苯并噁唑(polybenzoxazole)，則接合可根據熱壓接合(thermo-compression bonding)。
請參考圖11，可執行一平坦化製程，例如化學機械研磨，以暴露該等半導體貫穿通孔109的上表面。
請參考圖12，可執行一蝕刻製程以凹陷第一基底101的上表面。在蝕刻製程期間，第一基底101對該等半導體貫穿通孔109的蝕刻率可介於大約100：1到大約1.05：1之間、介於大約15：1到大約2：1之間，或是介於大約10：1到大約2：1之間。在蝕刻製程之後，該等半導體貫穿通孔109的各上部可從第一基底101的上表面突伸。
請參考圖13，一第一接合層107可形成在第一基底101上。第一接合層107可包含與中介接合層601相同的材料，但並不以此為限。在一些實施例中，舉例來說，第一接合層107可包含一非有機材料，選自未摻雜矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、氧化氮化矽及其組合。在一些實施例中，舉例來說，第一接合層107可包含一聚合物層，例如一環氧樹脂(epoxy)、聚烯亞胺(polyimide)、苯並環丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazole)或類似物。第一接合層107的製作技術可包含一沉積製程，例如化學氣相沉積、電漿加強氣相沉積、蒸鍍或旋轉塗佈。可執行一平坦化製程，例如化學機械研磨，以移除第一接合層107的一些部分並暴露該等半導體貫穿通孔109的上表面。
請參考圖13，第一基底101、第一介電層103、該等第一互連層105、第一接合層107以及該等半導體貫穿通孔109一起配置成第一晶粒結構100。該等暴露的半導體貫穿通孔109則可用於進一步與其他晶粒 結構接合並電性連接到其他晶粒結構。
請參考圖1、圖14及圖15，在步驟S15，一第二晶粒結構200可接合到第一晶粒結構100上，一第三晶粒結構300可接合到第二晶粒結構200上，一第四晶粒結構400可接合到第三晶粒結構300上，且多個焊料接頭(solder joints)603可形成在第四晶粒結構400上。
請參考圖14，在一些實施例中，第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400可具有類似於第一晶粒結構100的結構。舉例來說，第二晶粒結構200一可具有一第二基底201、一第二介電層203、多個第二互連層205、一第一接合層207以及多個半導體貫穿通孔209。第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400具有類似於第一晶粒結構100之元件編號的元件，可具有相同或類似的架構，並可包含相同或類似的材料。第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400的製作技術可類似於在圖9到圖13所描述之第一晶粒結構100的一程序。
請參考圖14，第二晶粒結構200可接合到第一晶粒結構100，並可經由第一晶粒結構100的該等半導體貫穿通孔109而電性耦接到第一晶粒結構100。第三晶粒結構300可接合到第二晶粒結構200，並可經由第二晶粒結構200的該等半導體貫穿通孔209而電性耦接到第二晶粒結構200。第四晶粒結構400可接合到第三晶粒結構300，並可經由第三晶粒結構300的該等半導體貫穿通孔309而電性耦接到第三晶粒結構300。
該等半導體貫穿通孔109、209、309、409可縮減該等晶粒結構100、200、300、400之間的互連長度。因此，可降低半導體元件1A的反射雜訊、串擾雜訊(crosstalk noise)、同步切換雜訊(simultaneous switching noise)、電磁干擾以及延遲(latency)。此外，當寄生電容正比於互連長度時，因為降低的寄生電容所以亦可降低在半導體元件1A中的總功耗。
該等晶粒結構100、200、300、400之間的接合可為混合接合，舉例來說，包括介電質對介電直接合、金屬對金屬接合或是金屬對介電質接合或金屬對黏著劑接合。該介電質對介電質接合可源自於該接合層與該介電層之間的接合。該金屬對金屬接合可源自於該等半導體貫穿通孔與該等互連層之間的接合。該金屬對介電質接合或是金屬對黏著劑接合可源自於該等互連層與該接合層之間的接合。
在一些實施例中，舉例來說，用於接合晶粒結構100、200、300、400的接合方法可包括熱壓接合、鈍化罩蓋層輔助接合(passivation-capping-layer assisted bonding)或表面活化接合(urface activated bonding)。該等接合方法的製程壓力可介於大約100MPa到大約150MPa之間。該等接合方法的製程溫度可介於大約室溫到大約400℃之間。在一些實施例中，濕式清洗以及氣相/蒸氣相熱處理的表面處理可用於降低該等接合方法的製程溫度或是縮短接合方法的時間損耗。在一些實施例中，在晶粒結構100、200、300、400的接合之後，可執行一退火製程，以加強介電質對介電質接合，並產生金屬對金屬接合的熱膨脹，以便進一步改善接合品質。
第一晶粒結構100、第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400可一起配置成一晶粒堆疊。在一些實施例中，第一晶粒結構100、第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400可全部為記憶體晶粒。在一些實施例中，第一晶粒結構100可為一邏 輯晶粒，且第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400可為記憶體晶粒。應當理解，該等晶粒結構的數量僅用於說明。該等晶粒結構的數量可大於或想於四個。舉例來說，該等晶粒結構的數量可為兩個(例如第一晶粒結構以及第二晶粒結構)。舉例來說，該等晶粒結構的數量可為五個(例如第一晶粒結構到第五晶粒結構)。
請參考圖14，該等焊料接頭603可形成在第四晶粒結構400的第一接合層407上，並可電性耦接到第四晶粒結構400的該等半導體貫穿通孔409。該等焊料接頭603可包含一材料，例如錫或其他適合的材料，例如銀或銅。在該等焊料接頭603為錫焊料接頭的一實施例中，該等焊料接頭603的製作技術可包含初始經由蒸鍍、電鍍、印刷(printing)、焊料轉移(solder transfer)或植球(ball placement)而形成一層錫到一厚度，大約10μm到大約100μm之間。一旦該層錫已經形成在第四晶粒結構400的第一接合層407上，則可執行一回焊製程(reflow process)以將該焊料接頭603成形為期望的形狀。
請參考圖15，如圖14所描述的中間半導體元件可上下顛倒置放。可執行一薄化製程以縮減載體基底501的厚度以及該等半導體貫穿通孔505的厚度。該薄化製程可為一蝕刻製程、一化學研磨製程或一拋光製程。在該薄化製程之後，可暴露該等半導體貫穿通孔505的各上表面。該等半導體貫穿通孔505的各上表面505TS可大致與載體基底501的上表面501TS為共面。該等半導體貫穿通孔505的各暴露上表面可有利於導熱。
按照慣例，在該等晶粒結構之間的接合之後，一載體結構可從一晶粒結構剝離。反之，在本揭露的一些實施例中，在晶粒結構100、200、300、400之間的接合之後，載體結構500可接合到第一晶粒結 構100。此外，由於散熱單元HDU的存在，所以在半導體元件1A的操作期間所累積的熱可經由該等導電板507與該等半導體貫穿通孔505而導熱到周圍(ambient)。意即，可改善半導體元件1A的導熱能力。
圖16到圖20是剖視示意圖，例示本揭露一些實施例之各半導體元件1B、1C、1D、1E、1F。
請參考圖16，半導體元件1B可具有類似於如圖15所描述的一結構。在圖16中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。載體基底501的厚度可縮減到一垂直位面，該垂直位面在該等半導體貫穿通孔505的上表面505TS上。意即，該等半導體貫穿通孔505可維持被載體基底501所覆蓋。該等被覆蓋的半導體貫穿通孔505可避免該等半導體貫穿通孔505氧化。
請參考圖17，半導體元件1C可具有類似於如圖15所描述的一結構。在圖17中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。可藉由一蝕刻製程縮減載體基底501的厚度，並可縮減到一垂直位面，該垂直位面低於該等半導體貫穿通孔505的上表面505TS。因此，該等半導體貫穿通孔505的各上部可從載體基底501的上表面501TS突伸。該等半導體貫穿通孔505的該等暴露部分可具有較大的表面積，以接觸周圍。因此，可提升該等半導體貫穿通孔505的導熱效率。
請參考圖18，半導體元件1D可具有類似於如圖15所描述的一結構。在圖18中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。
半導體元件1D可包括多個第一虛擬導電層615以及多個第 二虛擬導電層617。該等第一虛擬導電層615可設置在接合層509中，並可大致與接合層509及中介接合層601之間的界面為共面。該等第二虛擬導電層617可設置在中介接合層601中，並可大致與接合層509及中介接合層601之間的界面為共面。該等第一虛擬導電層615可垂直對準該等第二虛擬導電層617，並可接觸該等第二虛擬導電層617。舉例來說，該等第一虛擬導電層615與該等第二虛擬導電層617可包含鎢、鈷、鋯、鉭、鈦、鋁、釕或銅。該等第一虛擬導電層615與該等第二虛擬導電層617可藉由提供金屬對金屬接合而改善接合層509與中介接合層601之間的接合品質。
應當理解，將一元件表示成「虛擬(dummy)元件」，其意指當該半導體元件在操作時，沒有外部電壓或電流施加到該元件。
請參考圖19，半導體元件1E可具有類似於如圖15所描述的一結構。在圖19中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。
半導體元件1E可包括一熱界面層611，設置在中介接合層601與接合層509之間。在一些實施例中，熱界面層611可包含充滿一可撓性材料的一碳材料，例如一聚合物基質(polymer matrix)。舉例來說，熱界面層611可包括一般垂直定向石墨及多個奈米碳管，其充滿一含氟聚合物橡膠基質(fluoropolymer rubber matrix)。該等奈米碳管的深寬比可介於大約1：1到大約1：100之間。舉另一個例子，熱界面層611可包括石墨碳(graphitic carbon)。再舉另一個例子，熱界面層611可包括熱解石墨片(pyrolytic graphite sheet)。在一些實施例中，熱界面層611的一熱阻在一厚度處可小於0.2℃ cm2/Watt，該厚度介於大約250μm到大約450μm之 間。熱界面層611可對半導體元件1E提供額外的散熱能力。
請參考圖20，半導體元件1F可具有類似於如圖15所描述的一結構。在圖20中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。
半導體元件1F可包括多個導電鰭片511，以取代該等導電板507(如圖15所示)。該等導電鰭片511可設置在接合層509中，並可相互分隔開。每一個導電鰭片511可接觸相對應的其中一個半導體貫穿通孔505。該等導電鰭片511的各寬度W1可大於該等半導體貫穿通孔505的各寬度W2。該等導電鰭片511的總表面積可大於該等導電板507的總表面積，該等導電鰭片511可對半導體元件1F提供額外的散熱能力。
圖21及圖22是剖視示意圖，例示本揭露另一實施例之製備半導體元件1G的一流程。
請參考圖21，一中間半導體元件可以類似於如圖2到圖13所描述的一程序進行製造。多個焊墊層111可形成在第一接合層107上。該等焊墊層111的各寬度W3可大於該等半導體貫穿通孔109的各寬度W4。舉例來說，該等焊墊層111可包含鎢、鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物、金屬氮化物、過渡金屬鋁化物或其組合。該等焊墊層111的較大寬度可增加對第一晶粒結構100與第二晶粒結構200之間的接合之容差裕度(tolerance window)。換言之，可降低第一晶粒結構100與該等第二互連層205之間的對準需求。
請參考圖21，一第二接合層113可形成在第一接合層107上，並可覆蓋該等焊墊層111。在一些實施例中，舉例來說，第二接合層113可包含一非有機材料，選自未摻雜矽酸鹽玻璃、氮化矽、氮氧化矽、 氧化矽、氧化氮化矽及其組合。在一些實施例中，舉例來說，第二接合層113可包含一聚合物層，例如一環氧樹脂(epoxy)、聚烯亞胺(polyimide)、苯並環丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazole)或類似物。第二接合層113的製作技術可包含一沉積製程，例如化學氣相沉積、電漿加強氣相沉積、蒸鍍或旋轉塗佈。可執行一平坦化製程，例如化學機械研磨，以暴露該等焊墊層111的各上表面。
請參考圖22，其他元件的製作技術可包含類似於如圖14及圖15所描述的一程序。第二晶粒結構200的該等焊墊層211以及第三晶粒結構300的該等焊墊層311可具有類似於第一晶粒結構100的該等焊墊層111之結構。第二晶粒結構200的第二接合層213以及第三晶粒結構300的第二接合層313可具有類似於第一晶粒結構100的第二接合層113的結構。
圖23到圖26是剖視示意圖，例示本揭露另一實施例之製備半導體元件1H的一流程。
請參考圖23，一中間半導體元件可以類似於如圖2到圖19所描述的一程序所製造。應當理解，該等半導體貫穿通孔109並未形成在目前階段中的第一基底101中。
請參考圖24，如圖23所描述的中間半導體元件可上下顛倒置放並接合到接合層509上。
請參考圖25，在第一基底101上使用一蝕刻製程、一化學研磨製程以及一拋光製程而執行一薄化製程，以縮減第一基底101的一厚度。接下來，該等半導體貫穿通孔109可形成在第一基底101中，並可接觸該等第一互連層105。第一接合層107可以類似於如圖11到圖13所描述的一程序而形成在第一基底101。
請參考圖26，第二晶粒結構200、第三晶粒結構300、第四晶粒結構400的第一接合層407以及該等焊料接頭603的製作技術可包含類似於圖14及圖15所描述的一程序。應當理解，在該等半導體貫穿通孔209、該等半導體貫穿通孔309以及該等半導體貫穿通孔409可分別形成在晶粒結構200、300、400接合之前或者是可形成在晶粒結構200、300、400接合之前。
圖27及圖28是剖視示意圖，例示本揭露另一實施例之製備半導體元件1I的一流程。
請參考圖27，一中間半導體元件可以類似於如圖2到圖14所描述的一程序所製造。在一些實施例中，多個第一虛擬半導體貫穿通孔605可沿著第四晶粒結構400、第三晶粒結構300、第二晶粒結構200、第一晶粒結構100以及中介接合層601而形成。在晶粒結構100、200、300、400接合之後，可形成該等第一虛擬半導體貫穿通孔605。在一些實施例中，多個導電特徵可形成在晶粒結構100、200、300、400中。在晶粒結構100、200、300、400接合之後，該等導電特徵可垂直對準以配置成該等第一虛擬半導體貫穿通孔605。該等第一虛擬半導體貫穿通孔605可包含與該等半導體貫穿通孔505相同材料，但並不以此為限。
請參考圖28，如圖27所描述的中間半導體元件可反向設置。可執行一平坦製程，例如化學機械研磨，以暴露該等半導體貫穿通孔505。累積在晶粒結構100、200、300、400中的熱可經由該等第一虛擬半導體貫穿通孔605而導熱到載體結構500。
圖29是剖視示意圖，例示本揭露另一實施例之半導體元件1J。
請參考圖29，半導體元件1J可具有類似於如圖28所描述的一結構。在圖29中相同或類似於圖28中的元件已標示成類似的元件編號，並已省略其重複描述。該等第一虛擬半導體貫穿通孔605可接觸該等導電板507。累積在晶粒結構100、200、300、400中的熱可經由該等該等第一虛擬半導體貫穿通孔605而導熱到載體結構500的散熱單元HDU。
圖30及圖31是剖視示意圖，例示本揭露另一實施例之製備半導體元件1K的一流程。
請參考圖30，一中間半導體元件可以類似於如圖2到圖9所描述的一程序所製造。多個第二虛擬半導體貫穿通孔607可沿著中介接合層601與第一介電層103所形成，並延伸到第一基底101。在一些實施例中，該等第二虛擬半導體貫穿通孔607可沿著中介接合層601而形成並延伸到第一介電層103。該等第二虛擬半導體貫穿通孔607可包含與該等半導體貫穿通孔109相同的材料，但並不以此為限。在一些實施例中，該等第二虛擬半導體貫穿通孔607大致均勻分布在第一晶粒結構100中。
請參考圖31，其他元件的製作技術可包含類似於如圖10到圖15所描述的一程序。累積在第一晶粒結構100中的熱可經由該等第二虛擬半導體貫穿通孔607而導熱到載體結構500。
圖32到圖34是剖視示意圖，例示本揭露另一實施例之各半導體元件1L、1M、1N。
請參考圖32，半導體元件1L可具有類似於如圖15所描述的一結構。在圖32中相同或類似於圖15中的元件已標示成類似的元件編號，並已省略其重複描述。半導體元件1L可包括該等第一虛擬半導體貫穿通孔605以及該等第二虛擬半導體貫穿通孔607．該等第一虛擬半導體貫 穿通孔605可沿著中介接合層601、第一晶粒結構100、第二晶粒結構200、第三晶粒結構300以及第四晶粒結構400而設置。該等第二虛擬半導體貫穿通孔607可沿著中介接合層601與第一介電層103而設置，並延伸到第一基底101。意即，該等第一虛擬半導體貫穿通孔605的各深度可大於該等第二虛擬半導體貫穿通孔607的各深度。該等第一虛擬半導體貫穿通孔605的各寬度W5可大於或等於該等第二虛擬半導體貫穿通孔607的各寬度W6。
請參考圖33，半導體元件1M可具有類似於如圖32所描述的一結構。在圖33中相同或類似於圖32中的元件已標示成類似的元件編號，並已省略其重複描述。半導體元件1M還包括多個第三虛擬半導體貫穿通孔609。該等第三虛擬半導體貫穿通孔609可沿著第一晶粒結構100與第二介電層203而設置，並延伸到第二基底201。該等第三虛擬半導體貫穿通孔的各深度可大於該等第二虛擬半導體貫穿通孔607的各深度。該等第一虛擬半導體貫穿通孔605的各寬度W5可大於或等於該等第三虛擬半導體貫穿通孔609的各寬度W7。
請參考圖34，半導體元件1N可具有類似於如圖33所描述的一結構。在圖34中相同或類似於圖33中的元件已標示成類似的元件編號，並已省略其重複描述。該等第一虛擬半導體貫穿通孔605、該等第二虛擬半導體貫穿通孔607以及該等第三虛擬半導體貫穿通孔609可接觸該等導電板507以用於更有效地導熱。
本揭露之一實施例提供一種半導體元件，具有一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構，包括一載體基底，設置在該中介接合層上；以及多個半導體貫穿通孔，設置在該載體 基底中以及在該中介接合層以進行導熱。
本揭露之另一實施例提供一種半導體元件的製備方法，包括提供一載體基底；形成多個半導體貫穿通孔載該載體基底中以進行導熱；形成一接合層在該載體基板上；提供一第一晶粒結構，該第一晶粒結構包括多個半導體貫穿通孔；形成一中介接合層在該第一晶粒結構上；經由該中介接合層將該第一晶粒結構接合到該載體結構的該接合層上；以及將一第二晶粒結構接合到該第一晶粒結構上。該載體基底、該等半導體貫穿通孔以及該接合層一起配置成一載體結構。該第二晶粒結構與該第一晶粒結構藉由該等半導體貫穿通孔而電性耦接。
由於本揭露該半導體元件的設計，在半導體元件1A操作期間所累積的熱可經由該等導電板507以及該等半導體貫穿通孔505(例如散熱單元HDU)而導熱到周圍。意即，可改善半導體元件1A的導熱能力。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟包含於本申請案之申請專利範圍內。
1A:半導體元件
100:第一晶粒結構
101:第一基底
103:第一介電層
105:第一互連層
107:第一接合層
109:半導體貫穿通孔
200:第二晶粒結構
201:第二基底
203:第二介電層
205:第二互連層
207:第一接合層
209:半導體貫穿通孔
300:第三晶粒結
309:半導體貫穿通孔
400:第四晶粒結構
409:半導體貫穿通孔
500:載體結構
501:載體基底
501TS:上表面
505:半導體貫穿通孔
505TS:上表面
507:導電板
509:接合層
601:中介接合層
603:焊料接頭
HDU:散熱單元
Z:方向

Claims (16)

  1. 一種半導體元件，包括：一晶粒堆疊；一中介接合層，設置在該晶粒堆疊上；以及一載體結構，包括：一載體基底，設置在該中介接合層上；以及多個半導體貫穿通孔，設置在該載體基底中以及在該中介接合層以進行導熱，其中該等半導體貫穿通孔與該晶粒堆疊相互電隔離；其中該載體結構包括：一接合層，設置在該載體基底與該中介接合層之間；以及一導電板，設置在該載體結構的該接合層中並電性耦接該載體結構的該等半導體貫穿通孔，其中該導電板與該晶粒堆疊相互電隔離；其中該晶粒堆疊包括：一第一晶粒結構，設置在該中介接合層的下方；以及一第二晶粒結構，設置在該第一晶粒結構下方；其中該第一晶粒結構包括：一第一基底，設置在該中介接合層的相反處；一第一介電層，設置在該第一基底與該中介接合層之間；一第一接合層，設置在該第一基底與該第二晶粒結構之間；多個第一互連層，設置在該第一介電層中； 該第一晶粒結構的多個半導體貫穿通孔，沿著該第一晶粒結構的該第一基底與該第一接合層設置，並電性連接該等第一互連層與該第二晶粒結構；其中該第二晶粒結構包括：一第二基底，設置在該第一晶粒結構之該第一接合層的相反處；一第二介電層，設置在該第二基底與該第一晶粒結構的該第一接合層之間；該第二晶粒結構的一第一接合層，設置在該第二基底下方；多個第二互連層，設置在該第二介電層中並電性連接到該第一晶粒結構的該等半導體貫穿通孔；以及該第二晶粒結構的多個半導體貫穿通孔，沿著該第二晶粒結構的該第二基底與該第一接合層而設置，並電性連接到該等第二互連層。
  2. 如請求項1所述之半導體元件，其中該第一晶粒結構與該第二晶粒結構為記憶體晶粒。
  3. 如請求項1所述之半導體元件，其中該第一晶粒結構為一記憶體晶粒，而該第二晶粒結構為一邏輯晶粒。
  4. 如請求項1所述之半導體元件，其中該載體結構之該等半導體貫穿通孔的各上表面與該載體結構的一上表面大致為共面。
  5. 如請求項1所述之半導體元件，其中該載體結構之該等半導體貫穿通孔的各上表面被該載體基底所覆蓋。
  6. 如請求項1所述之半導體元件，還包括多個焊料接頭，電性連接到該第二晶粒結構的該等半導體貫穿通孔。
  7. 如請求項1所述之半導體元件，其中該第一晶粒結構包括：一第二接合層，設置在該第一晶粒結構的該第一接合層與該第二介電層之間；以及多個焊墊層，設置在該第二接合層中並電性連接該等第二互連層以及該第一晶粒結構的該等半導體貫穿通孔。
  8. 如請求項7所述之半導體元件，其中該等焊墊層的各寬度大於該第一晶粒結構之該等半導體貫穿通孔的各寬度。
  9. 如請求項1所述之半導體元件，還包括多個第一虛擬半導體貫穿通孔，沿著該第一晶粒結構、該第二晶粒結構以及該中介接合層設置。
  10. 如請求項1所述之半導體元件，還包括多個第一虛擬半導體貫穿通孔，沿著該第一晶粒結構、該第二晶粒結構以及該中介接合層設置，延伸到該載體結構的該接合層，並熱接觸該導電板。
  11. 如請求項8所述之半導體元件，還包括多個第二虛擬半導體貫穿通 孔，沿著該中介接合層與該第一介電層設置，並延伸到該第一基底。
  12. 如請求項10所述之半導體元件，其中該等第一虛擬半導體貫穿通孔的各寬度大於該等第二虛擬半導體貫穿通孔的各寬度。
  13. 如請求項10所述之半導體元件，還包括多個第三虛擬半導體貫穿通孔，沿著該第一晶粒結構設置並延伸到該第二晶粒結構。
  14. 如請求項10所述之半導體元件，其中該等第二半導體貫穿通孔大致均勻分布在該第一晶粒結構中。
  15. 如請求項1所述之半導體元件，還包括一熱界面層，設置在該中介接合層與該載體結構的該接合層之間，其中該熱界面層包含充滿一可撓性材料的一碳材料。
  16. 如請求項1所述之半導體元件，其中該載體結構包括：一接合層，設置在該載體基底與該中介接合層之間；以及多個導電鰭片，設置在該載體結構的該接合層中並與該載體結構的該等半導體貫穿通孔接觸。
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