CN114792666A - 半导体元件及其制备方法 - Google Patents

半导体元件及其制备方法 Download PDF

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Publication number
CN114792666A
CN114792666A CN202111429871.1A CN202111429871A CN114792666A CN 114792666 A CN114792666 A CN 114792666A CN 202111429871 A CN202111429871 A CN 202111429871A CN 114792666 A CN114792666 A CN 114792666A
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semiconductor
bonding layer
layer
die structure
die
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施信益
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Nanya Technology Corp
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Nanya Technology Corp
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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Abstract

本公开提供一种具有散热单元的半导体元件及该半导体元件的制备方法。该半导体元件具有一晶粒堆叠；一中介接合层，设置在该晶粒堆叠上；以及一载体结构。该载体结构包括一载体基底以及多个半导体贯穿通孔，该载体基底设置在该中介接合层上，所述半导体贯穿通孔设置在该载体基底中以及在该中介接合层上，以进行导热。

Description

半导体元件及其制备方法
技术领域
本申请案主张2021年1月26日申请的美国正式申请案第17/158,337号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开关于一种半导体元件以及该半导体元件的制备方法。特别是有关于一种具有散热单元的半导体元件，以及具有该散热单元的该半导体元件的制备方法。
背景技术
半导体元件使用在不同的电子应用，例如个人电脑、手机、数码相机，或其他电子设备。半导体元件的尺寸逐渐地变小，以符合计算能力所逐渐增加的需求。然而，在尺寸变小的制程期间，增加不同的问题，且如此的问题在数量与复杂度上持续增加。因此，仍然持续着在达到改善品质、良率、效能与可靠度以及降低复杂度方面的挑战。
上文的「先前技术」说明仅提供背景技术，并未承认上文的「先前技术」说明揭示本公开的标的，不构成本公开的先前技术，且上文的「先前技术」的任何说明均不应作为本案的任一部分。
发明内容
本公开的一实施例提供一种半导体元件，具有一晶粒堆叠；一中介接合层，设置在该晶粒堆叠上；以及一载体结构。该载体结构包括一载体基底，设置在该中介接合层上；以及多个半导体贯穿通孔，设置在该载体基底中以及在该中介接合层以进行导热。
在一些实施例中，该载体结构包括一接合层，设置在该载体基底与该中介接合层之间；以及一导电板，设置在该载体结构的该接合层中并接触该载体结构的所述半导体贯穿通孔。
在一些实施例中，该晶粒堆叠包括一第一晶粒结构，设置在该中介接合层的下方；以及一第二晶粒结构，设置在该第一晶粒结构下方。
在一些实施例中，该第一晶粒结构与该第二晶粒结构为存储器晶粒。
在一些实施例中，该第一晶粒结构为一存储器晶粒，而该第二晶粒结构为一逻辑晶粒。
在一些实施例中，该载体结构的所述半导体贯穿通孔的各上表面与该载体结构的一上表面大致为共面。
在一些实施例中，该载体结构的所述半导体贯穿通孔的各上表面被该载体基底所覆盖。
在一些实施例中，该第一晶粒结构包括一第一基底，设置在该中介接合层的相反处；一第一介电层，设置在该第一基底与该中介接合层之间；一第一接合层，设置在该第一基底与该第二晶粒结构之间；多个第一互连层，设置在该第一介电层中；该第一晶粒结构的多个半导体贯穿通孔，沿着该第一晶粒结构的该第一基底与该第一接合层设置，并电性连接所述第一互连层与该第二晶粒结构。该第二晶粒结构包括一第二基底，设置在该第一晶粒结构的该第一接合层的相反处；一第二介电层，设置在该第二基底与该第一晶粒结构的该第一接合层之间；该第二晶粒结构的一第一接合层，设置在该第二基底下方；多个第二互连层，设置在该第二介电层中并电性连接到该第一晶粒结构的所述半导体贯穿通孔；以及该第二晶粒结构的多个半导体贯穿通孔，沿着该第二晶粒结构的该第二基底与该第一接合层而设置，并电性连接到所述第二互连层。
在一些实施例中，该半导体元件还包括多个焊料接头(solder joints)，电性连接到该第二晶粒结构的所述半导体贯穿通孔。
在一些实施例中，该第一晶粒结构包括一第二接合层，设置在该第一晶粒结构的该第一接合层与该第二介电层之间；以及多个焊垫层(pad layer)，设置在该第二接合层中并电性连接所述第二互连层以及该第一晶粒结构的所述半导体贯穿通孔。
在一些实施例中，所述焊垫层的各宽度大于该第一晶粒结构的所述半导体贯穿通孔的各宽度。
在一些实施例中，该半导体元件还包括多个第一虚拟半导体贯穿通孔，沿着该第一晶粒结构、该第二晶粒结构以及该中介接合层设置。
在一些实施例中，该半导体元件还包括多个第一虚拟半导体贯穿通孔，沿着该第一晶粒结构、该第二晶粒结构以及该中介接合层设置，延伸到该载体结构的该接合层，并热接触该导电板。
在一些实施例中，该半导体元件还包括多个第二虚拟半导体贯穿通孔，沿着该中介接合层与该第一介电层设置，并延伸到该第一基底。
在一些实施例中，所述第一虚拟半导体贯穿通孔的各宽度大于所述第二虚拟半导体贯穿通孔的各宽度。
在一些实施例中，该半导体元件还包括多个第三虚拟半导体贯穿通孔，沿着该第一晶粒结构设置并延伸到该第二晶粒结构。
在一些实施例中，所述第二虚拟半导体贯穿通孔大致均匀分布在该第一晶粒结构中。
在一些实施例中，该半导体元件还包括一热界面层，设置在该中介接合层与该载体结构的该接合层之间，其中该热界面层(thermal interface layer)包含充满一可挠性材料的一碳材料。
在一些实施例中，该载体结构包括一接合层，设置在该载体基底与该中介接合层之间；以及多个导电鳍片，设置在该载体结构的该接合层中并与该载体结构的所述半导体贯穿通孔接触。
本公开的另一实施例提供一种半导体元件的制备方法，包括提供一载体基底；形成多个半导体贯穿通孔载该载体基底中以进行导热；形成一接合层在该载体机体上；提供一第一晶粒结构，该第一晶粒结构包括多个半导体贯穿通孔；形成一中介接合层在该第一晶粒结构上；经由该中介接合层将该第一晶粒结构接合到该载体结构的该接合层上；以及将一第二晶粒结构接合到该第一晶粒结构上。该载体基底、所述半导体贯穿通孔以及该接合层一起配置成一载体结构。该第二晶粒结构与该第二晶粒结构借由所述半导体贯穿通孔而电性耦接。
由于本公开该半导体元件的设计，在该半导体元件操作期间所累积的热可经由所述导电板以及所述半导体贯穿通孔而导热到周围。意即，可改善该半导体元件的导热能力。因此，可改善该半导体元件的效能。
上文已相当广泛地概述本公开的技术特征及优点，而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中具有通常知识者应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中具有通常知识者亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考量图式时，可得以更全面了解本申请案的揭示内容，图式中相同的元件符号指相同的元件。
图1是流程示意图，例示本公开一实施例的半导体元件的制备方法。
图2及图3是剖视示意图，例示本公开一实施例的制备半导体元件的一部分流程。
图4是放大剖视示意图，例示本公开一实施例的一中间半导体元件。
图5及图6是放大剖视示意图，例示本公开一实施例的各中间半导体元件。
图7到图15是剖视示意图，例示本公开一实施例的制备半导体元件的一部分流程。
图16到图20是剖视示意图，例示本公开一些实施例的各半导体元件。
图21及图22是剖视示意图，例示本公开另一实施例的制备半导体元件的一流程。
图23到图26是剖视示意图，例示本公开另一实施例的制备半导体元件的一流程。
图27及图28是剖视示意图，例示本公开另一实施例的制备半导体元件的一流程。
图29是剖视示意图，例示本公开另一实施例的半导体元件。
图30及图31是剖视示意图，例示本公开另一实施例的制备半导体元件的一流程。
图32到图34是剖视示意图，例示本公开另一实施例的各半导体元件。
其中，附图标记说明如下：
10：制备方法
1A：半导体元件
1B：半导体元件
1C：半导体元件
1D：半导体元件
1E：半导体元件
1F：半导体元件
1G：半导体元件
1H：半导体元件
1I：半导体元件
1J：半导体元件
1K：半导体元件
1L：半导体元件
1M：半导体元件
1N：半导体元件
100：第一晶粒结构
101：第一基底
103：第一介电层
105：第一互连结构
107：第一接合层
109：半导体贯穿通孔
111：焊垫层
113：第二接合层
200：第二晶粒结构
201：第二基底
203：第二介电层
205：第二互连结构
207：第一接合层
209：半导体贯穿通孔
211：焊垫层
213：第二接合层
300：第三晶粒结
309：半导体贯穿通孔
311：焊垫层
313：第二接合层
400：第四晶粒结构
409：半导体贯穿通孔
500：载体结构
501：载体基底
501TS：上表面
503：通孔开孔
505：半导体贯穿通孔
505TS：上表面
507：导电板
509：接合层
511：导电鳍片
601：中介接合层
603：焊料接头
605：第一虚拟半导体贯穿通孔
607：第二虚拟半导体贯穿通孔
609：第三虚拟半导体贯穿通孔
611：热界面层
613：覆盖层
615：第一虚拟导电层
617：第二虚拟导电层
AL：粘着层
BL：阻障层
FL：填充层
HDU：散热单元
IL：绝缘层
S11：步骤
S13：步骤
S15：步骤
SL：晶种层
W1：宽度
W2：宽度
W3：宽度
W4：宽度
W5：宽度
W6：宽度
W7：宽度
Z：方向
具体实施方式
以下描述了组件和配置的具体范例，以简化本公开的实施例。当然，这些实施例仅用以例示，并非意图限制本公开的范围。举例而言，在叙述中第一部件形成于第二部件之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不会直接接触的实施例。另外，本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚，除非内文中特别说明，其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外，为易于说明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所绘示的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
应当理解，当形成一个部件在另一个部件之上(on)、与另一个部件相连(connected to)、及/或与另一个部件耦合(coupled to)，其可能包含形成这些部件直接接触的实施例，并且也可能包含形成额外的部件介于这些部件之间，使得这些部件不会直接接触的实施例。
应当理解，尽管这里可以使用术语第一，第二，第三等来描述各种元件、部件、区域、层或区段(sections)，但是这些元件、部件、区域、层或区段不受这些术语的限制。相反，这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此，在不脱离本发明进步性构思的教导的情况下，下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
除非内容中另有所指，否则当代表定向(orientation)、布局(layout)、位置(location)、形状(shapes)、尺寸(sizes)、数量(amounts)，或其他量测(measures)时，则如在本文中所使用的例如「同样的(same)」、「相等的(equal)」、「平坦的(planar)」，或是「共面的(coplanar)」等术语(terms)并非必要意指一精确地完全相同的定向、布局、位置、形状、尺寸、数量，或其他量测，但其意指在可接受的差异内，包含差不多完全相同的定向、布局、位置、形状、尺寸、数量，或其他量测，而举例来说，所述可接受的差异可因为制造流程(manufacturing processes)而发生。术语「大致地(substantially)」可被使用在本文中，以表现出此意思。举例来说，如大致地相同的(substantially the same)、大致地相等的(substantially equal)，或是大致地平坦的(substantially planar)，为精确地相同的、相等的，或是平坦的，或者是其可为在可接受的差异内的相同的、相等的，或是平坦的，而举例来说，所述可接受的差异可因为制造流程而发生。
在本公开中，一半导体元件通常意指可借由利用半导体特性(semiconductorcharacteristics)运行的一元件，而一光电元件(electro-optic device)、一发光显示元件(light-emitting display device)、一半导体线路(semiconductor circuit)以及一电子元件(electronic device)，均包括在半导体元件的范畴中。
应当理解，在本公开的描述中，上方(above)(或之上(up))对应Z方向箭头的该方向，而下方(below)(或之下(down))对应Z方向箭头的相对方向。
应当理解，在本公开的描述中，一元件(或一特征)沿着方向Z位在最高垂直位面(level)的一表面，表示成该元件(或该特征)的一上表面。一元件(或一特征)沿着方向Z位在最低垂直位面(level)的一表面，表示成该元件(或该特征)的一下表面。
图1是流程示意图，例示本公开一实施例的半导体元件1A的制备方法10。图2及图3是剖视示意图，例示本公开一实施例的制备半导体元件1A的一部分流程。图4是放大剖视示意图，例示本公开一实施例的一中间半导体元件。图5及图6是放大剖视示意图，例示本公开一实施例的各中间半导体元件。图7到图15是剖视示意图，例示本公开一实施例的制备半导体元件1A的一部分流程。
请参考图1到图8，在步骤S11，可提供一载体结构500，而载体结构500包括一散热单元HDU。
请参考图2，可提供一载体基底501，且多个通孔开孔503可形成在载体基底501中。举例来说，载体基底501可包含硅、锗、硅锗、硅碳、硅锗碳、镓、砷化镓、砷化铟、磷化铟(indium phosphorus)或其他IV-IV、III-V或II-VII族半导体材料。
请参考图2，所述通孔开孔503的各内侧壁可稍微呈锥形，例如介于大约85度到大约88度之间，并且平滑以用于如之后将说明的共形及无孔洞材料填充。所述通孔开孔503的各锥形内侧壁亦可改善在所述通孔开孔503内的多个金属离子的扩散，并可减少填充所述通孔开孔503的时间。此外，所述通孔开孔503的各平滑内侧壁可有利于减少应力集中。在一些实施例中，所述通孔开孔503的各宽度可介于大约1μm到大约22μm之间，或是介于5μm到15μm之间。在一些实施例中，所述通孔开孔503的各深度可介于大约20μm到大约160μm之间，或是介于大约50μm到大约130μm之间。
举例来说，所述通孔开孔503的制作技术可包含激光钻孔(laser drilling)、喷粉微加工(powder blast micromaching)、深反应离子蚀刻(deep reactive ion etching)或是使用氢氧化物的湿蚀刻，该氢氧化物例如氢氧化钾(potassium hydroxide)、氢氧化钠(sodium hydroxide)、氢氧化铷(rubidium hydroxid)、氢氧化铵(ammonium hydroxide)或是四甲基氢氧化铵(tetra methyl ammonium hydroxide)。
请参考图3，可形成多个半导体贯穿通孔505以完全填满所述通孔开孔503。通常，所述半导体贯穿通孔505的制作技术可包含衬垫沉积(liner deposition)以及导电材料填充(conductive material filling)。可执行一平坦化制程，例如化学机械研磨，以提供一大致平坦表面给接下来的处理步骤。在一些实施例中，所述半导体贯穿通孔505的各侧壁可大致呈锥形，例如介于大约85度到大约88度之间。在一些实施例中，所述半导体贯穿通孔505的各宽度可介于大约1μm到大约22μm之间，或是介于大约5μm到大约15μm之间。在一些实施例中，所述半导体贯穿通孔505的各深度可介于大约20μm到大约160μm之间，或是介于50μm到大约130μm之间。
为了便于描述，所以仅描述一个半导体贯穿通孔505。请参考图4，半导体贯穿通孔505可包括一填充层FL、一晶种层SL、一粘着层AL、一阻障层BL以及一绝缘层IL。绝缘层IL可共形形成在通孔开孔503中，并可具有一U形剖面轮廓。在一些实施例中，举例来说，绝缘层IL可包含氧化硅、氮化硅、氮氧化硅或四乙氧基硅烷(tetra-ethyl ortho-silicate)。绝缘层IL可具有一厚度，介于大约50nm到大约200nm之间。或者是，在一些实施例中，举例来说，绝缘层IL可包含聚对二甲苯(parylene)、环氧树脂(epoxy)或聚对茬(poly(p-xylene))。绝缘层IL可具有一厚度，介于大约1μm到大约5μm之间。绝缘层IL可确保填充层FL在载体基底501中电性绝缘。
请参考图4，阻障层BL可共形形成在绝缘层IL上，并可具有一U形剖面轮廓。举例来说，阻障层BL可包含钽、氮化钽、钛、氮化钛、铼、硼化镍或氮化钽/钽的双层。阻挡层BL可抑制填充层FL的导电材料扩散进入到二绝缘层IL中。阻障层BL的制作技术可包含一沉积制程，例如物理气相沉积、原子层沉积、化学气相沉积或喷溅。
请参考图4，粘着层AL可共形形成在阻障层BL上，并可具有一U形剖面轮廓。举例来说，粘着层AL可包含钛、钽、钛钨或氮化锰。粘着层AL可改善晶种层SL与阻障层BL之间的一粘性。粘着层AL可分别具有一厚度，介于大约5nm到大约50nm之间。二粘着层AL的制作技术可包含一沉积制程，例如物理气相沉积、原子层沉积、化学气相沉积或喷溅。
请参考图4，晶种层SL可共形形成在粘着层AL上，并可具有一U形剖面轮廓。晶种层SL可具有一厚度，介于大约10nm到大约40nm之间。举例来说，晶种层SL可包含铜或钌。晶种层SL的制作技术可包含一沉积制程，例如物理气相沉积、原子层沉积、化学气相沉积或喷溅。在借由一电镀制程形成填充层FL期间，晶种层SL可降低通孔开孔503的电阻率(resistivity)。
请参考图4，填充层FL可形成在晶种层SL上，并完全填满通孔开孔503。举例来说，填充层FL可为铜。填充层FL的制作技术可包含使用一镀覆溶液(plating solution)的一电镀制程。镀覆溶液可包括硫酸铜(copper sulfate)、甲烷磺酸铜(copper methanesulfonate)、葡萄糖酸盐铜(copper gluconate)、氨基磺酸盐铜(copper sulfamate)、硝酸铜(copper nitrate)、磷酸铜(copper phosphate)或氯化铜(copper chloride)。镀覆溶液的pH值可介于大约2到大约6之间，或是介于大约3到大约5之间。电镀制程的制程温度可维持在大约40℃到大约75℃之间，或是在大约50℃到大约70℃之间。
在一些实施例中，电镀溶液可包括加速剂(accelerators)、抑制剂(suppressors)和均匀剂(levelers)。加速剂可包括一极性硫、氧或氮功能群，以帮助提升沉积率，并可促进密集成核。加速剂可以一低浓度程度存在，举例来说，该低浓度程度介于大约0到大约200ppm之间。抑制剂是降低镀覆速率的添加剂，且通常以更高的浓度存在于电镀槽(plating bath)中，例如在约5ppm和约1000ppm之间。抑制剂可为具有高分子量(molecularweight)的聚合界面活性剂(polymeric surfactant)，例如聚乙二醇(polyethyleneglycol)。
抑制剂可借由吸附在表面以及形成一阻障层的铜离子以减慢沉积率。因为其大尺寸与低扩散率，抑制剂不太可能到达通孔开孔503的下部。因此，大部分的抑制效果可发生在通孔开孔503的下部处，以帮助减少填充材料(例如铜)的过载并避免通孔开孔503关闭(closing)。
均匀剂可用于改善填充效能，降低表面粗糙度，并避免在通孔开孔503的上部处的铜沉积。均匀剂可以一小浓度存在，举例来说，该小浓度介于大约1ppm到大约100ppm之间。举例来说，均匀剂可为3-mercapto-1-propanesulfonate、(3-sulfopropyl)disulfide或是3,3-thiobis(1-propanesulfonate)。
应当理解，在本公开中，术语「部位(part)」或「区段(segment)」可与术语「部分(portion)」交叉使用。
在一些实施例中，在填充层FL形成之后，可执行一退火制程(annealingprocess)。退火制程可减少在接下来的半导体制程期间的抽铜(copper-pumping)的不利影响、改善填充层FL与绝缘层IL之间的粘性，以及稳定填充层FL的微结构。
或者是，请参考图5，多个覆盖层613可共形形成在通孔开孔503的上部上，并形成在载体基底501的上表面上。绝缘层IL可共形形成在所述覆盖层613上以及在所述通孔开孔503中。可形成填充层FL以完全填满所述通孔开孔503。应当理解，为了清楚，在图5中并未显示阻障层BL、粘着层AL以及晶种层SL。
所述覆盖层613的制作技术可包含一沉积制程，例如一原子层沉积方法，其精确控制原子层沉积方法的一第一前驱物的数量。举例来说，所述覆盖层613可包含氧化铝、氧化铪、氧化锆、氧化钛、氮化钛、氮化钨、氮化硅或氧化硅。
在一些实施例中，当所述覆盖层613包含氧化铝时，该原子层沉积方法的该第一前驱物可为三甲基铝(trimethylaluminum)，而该原子层沉积方法的该第二前驱物可为水或臭氧。
在一些实施例中，当所述覆盖层613包含氧化铪时，则该原子层沉积方法的该第一前驱物可为四氯化铪(hafnium tetrachloride)、三级丁氧化铪(hafnium tert-butoxide)、二甲基酰胺铪(hafnium dimethylamide)、甲基乙基酰胺铪(hafniumethylmethylamide)、二乙基酰胺铪(hafnium diethylamide)或甲氧基-三级丁氧化铪(hafnium methoxy-t-butoxide)，而该原子层沉积方法的该第二前驱物可为水或臭氧。
在一些实施例中，当所述覆盖层613包含氧化锆时，则该原子层沉积方法的该第一前驱物可为四氯化锆(zirconium tetrachloride)，而该原子层沉积方法的该第二前驱物可为水或臭氧。
在一些实施例中，当所述覆盖层613包含氧化钛时，则该原子层沉积方法的该第一前驱物可为四氯化钛(titanium tetrachloride)、钛酸四乙酯(tetraethyl titanate)、或异丙醇钛(titanium isopropoxide)，而该原子层沉积方法的该第二前驱物可为水或臭氧。
在一些实施例中，当所述覆盖层613包含氮化钛时，则该原子层沉积方法的该第一前驱物可为四氯化钛(titanium tetrachloride)及氨水(ammonia)。
在一些实施例中，当所述覆盖层613包含氮化钨时，则该原子层沉积方法的该第一前驱物可为六氟化钨(tungsten hexafluoride)及氨水(ammonia)。
在一些实施例中，当所述覆盖层613包含氮化硅时，则该原子层沉积方法的该第一前驱物可为硅烯(silylene)、氯、氨水和四氢化二氮(dinitrogen tetrahydride)。
在一些实施例中，当所述覆盖层613包含氧化硅时，则该原子层沉积方法的该第一前驱物可为硅四异氰酸酯(silicon tetraisocyanate)或CH3OSi(NCO)3，而该原子层沉积方法的该第二前驱物可为氢或臭氧。
由于所述覆盖层613的存在，所以可降低填充层FL的填充材料在通孔开孔503的各侧壁上的沉积率。因此，填充层FL的填充材料在通孔开孔503的各侧壁上的沉积率以及填充层FL的填充材料在通孔开孔503的下表面上的沉积率可变得相互接近。结果，可填满通孔开孔503而不会有任何空孔(void)形成在通孔开孔503的下表面附近。
请参考图6，可执行一平坦化制程，例如化学机械研磨，以移除多余材料，提供一大致平坦表面给接下来的处理步骤，并同时形成半导体贯穿通孔505。
请参考图7，多个导电板507形成在载体基底501上并可相互分隔开。每一个导电板507可连接到其中两个或更多个半导体贯穿通孔505。举例来说，所述导电板507包含钨、钴、锆、钽、钛、铝、钌、铜、金属碳化物(例如碳化钽、碳化钛、碳化钽镁)、金属氮化物(例如氮化钛)、过渡金属铝化物或其组合。所述导电板507以及所述半导体贯穿通孔507一起配置成散热单元HDU。
在一些实施例中，仅一个导电板507可形成在载体基底501上，并可连接到所有的半导体贯穿通孔505。
请参考图8，一接合层509可形成在载体基底501上并覆盖所述导电板507。可执行一平坦化制程，例如化学机械研磨，以提供一大致平坦表面给接下来的处理步骤。在一些实施例中，举例来说，接合层509可包含一非有机材料，选自未掺杂硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅、氧化氮化硅及其组合。在一些实施例中，举例来说，接合层509可包含一聚合物层，例如一环氧树脂(epoxy)、聚烯亚胺(polyimide)、苯并环丁烯(benzocyclobutene)、聚苯并恶唑(polybenzoxazole)或类似物。接合层509的制作技术可包含一沉积制程，例如化学气相沉积、等离子体加强气相沉积、蒸镀或旋转涂布。
请参考图8，载体基底501、散热单元HDU以及接合层509一起配置成载体结构500。载体结构500可用于与其他晶粒(或其他晶圆)接合，以形成用于进一步接合程序的一中间堆叠结构。
请参考图1及图19到图13，在步骤S13，一第一晶粒结构100可接合到载体结构500上。
请参考图9，可提供一第一基底101。第一基底101可包含与载体基底501相同的材料，但并不以此为限。在一些实施例中，举例来说，第一基底101可包含硅、锗、硅锗、硅碳、硅锗碳、镓、砷化镓、砷化铟、磷化铟(indium phosphorus)或其他IV-IV、III-V或II-VII族半导体材料。多个半导体贯穿通孔109可形成在第一基底101中，且其制作技术可类似于如图2到图6描述的所述半导体贯穿通孔505的一程序。
请参考图9，一第一介电层103可形成在第一基底101上。在一些实施例中，第一介电层103可为一堆叠层结构。第一介电层103可包括多个第一隔离子层。每一个第一隔离子层可具有一厚度，介于大约0.5μm到大约3.0μm之间。举例来说，多个第一隔离子层可包含氧化硅、硼磷硅酸盐玻璃(borophosphosilicate glass)、未掺杂硅酸盐玻璃(undopedsilicate glass)、氟硅酸盐玻璃(fluorinated silicate glass)、低介电常数的介电材料、类似物或其组合。多个第一隔离子层可包含不同材料，但并不以此为限。低介电常数的介电材料可具有一介电常数，其小于3.0或甚至小于2.0。在一些实施例中，低介电常数的介电材料可具有一介电常数，其小于2.0。第一介电层103的制作技术可包含多个沉积制程，例如化学气相沉积、等离子体加强化学气相沉积、蒸镀或旋转涂布。在所述沉积制程之后，可分别对应执行多个平坦化制程，以移除多余材料并提供一大致平坦表面给接下来的处理步骤。在第一介电层103形成期间，可形成多个主动元件以及所述第一互连结构105。
举例来说，所述主动元件(图未示)可为双极性接面晶体管(bipolar junctiontransistors)、金属氧化物半导体场效晶体管、二极管、快闪存储器、动态随机存取存储器、静态随机存取存储器、可抹除可编程只读存储器(erasable programmable read-onlymemories)、影像感测器、微机电系统、主动元件或被动元件。所述主动元件与所述半导体贯穿通孔109可电性耦接。
请参考图9，多个第一互连结构105可形成在第一介电层103中。每一个第一互连结构105可包括多个导电线、导电通孔、导电接触点或是着陆垫。举例来说，所述第一互连结构105可包含钨、钴、锆、钽、钛、铝、钌、铜、金属碳化物(例如碳化钽、碳化钛、碳化钽镁)、金属氮化物(例如氮化钛)、过渡金属铝化物或其组合。所述第一互连结构105与所述主动元件可电性耦接。
请参考图9，一中介接合层601可形成在第一介电层103上。中介接合层601可包含与接合层509相同的材料，但并不以此为限。在一些实施例中，举例来说，中介接合层601可包含一非有机材料，选自未掺杂硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅、氧化氮化硅及其组合。在一些实施例中，举例来说，中介接合层601可包含一聚合物层，例如一环氧树脂(epoxy)、聚烯亚胺(polyimide)、苯并环丁烯(benzocyclobutene)、聚苯并恶唑(polybenzoxazole)或类似物。中介接合层601的制作技术可包含一沉积制程，例如化学气相沉积、等离子体加强气相沉积、蒸镀或旋转涂布。
请参考图10，在图9中所描述的中间半导体元件可相反置放并接合到载体基底501上。在一些实施例中，中介接合层601可接合到载体结构500的接合层509上。在接合之后，第一介电层103可设置在中介接合层601上，且第一基底101可设置在第一介电层103上。应当理解，在所述第一互连结构105与散热单元HDU之间并无建立电性连接。
在一些实施例中，举例来说，当接合层509与中介接合层601包含氧化硅或氮化硅时，接合层509与中介接合层601之间的接合可基于亲水性接合(hydrophilic bonding)机制。在接合之前，亲水性表面的修改可应用于接合层509与中介接合层601。在一些实施例中，当接合层509与中介接合层601包含聚合粘着剂时，例如苯并环丁烯(benzocyclobutenes)与聚苯并恶唑(polybenzoxazole)，则接合可根据热压接合(thermo-compression bonding)。
请参考图11，可执行一平坦化制程，例如化学机械研磨，以暴露所述半导体贯穿通孔109的上表面。
请参考图12，可执行一蚀刻制程以凹陷第一基底101的上表面。在蚀刻制程期间，第一基底101对所述半导体贯穿通孔109的蚀刻率可介于大约100：1到大约1.05：1之间、介于大约15：1到大约2：1之间，或是介于大约10：1到大约2：1之间。在蚀刻制程之后，所述半导体贯穿通孔109的各上部可从第一基底101的上表面突伸。
请参考图13，一第一接合层107可形成在第一基底101上。第一接合层107可包含与中介接合层601相同的材料，但并不以此为限。在一些实施例中，举例来说，第一接合层107可包含一非有机材料，选自未掺杂硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅、氧化氮化硅及其组合。在一些实施例中，举例来说，第一接合层107可包含一聚合物层，例如一环氧树脂(epoxy)、聚烯亚胺(polyimide)、苯并环丁烯(benzocyclobutene)、聚苯并恶唑(polybenzoxazole)或类似物。第一接合层107的制作技术可包含一沉积制程，例如化学气相沉积、等离子体加强气相沉积、蒸镀或旋转涂布。可执行一平坦化制程，例如化学机械研磨，以移除第一接合层107的一些部分并暴露所述半导体贯穿通孔109的上表面。
请参考图13，第一基底101、第一介电层103、所述第一互连结构105、第一接合层107以及所述半导体贯穿通孔109一起配置成第一晶粒结构100。所述暴露的半导体贯穿通孔109则可用于进一步与其他晶粒结构接合并电性连接到其他晶粒结构。
请参考图1、图14及图15，在步骤S15，一第二晶粒结构200可接合到第一晶粒结构100上，一第三晶粒结构300可接合到第二晶粒结构200上，一第四晶粒结构400可接合到第三晶粒结构300上，且多个焊料接头(solder joints)603可形成在第四晶粒结构400上。
请参考图14，在一些实施例中，第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400可具有类似于第一晶粒结构100的结构。举例来说，第二晶粒结构200一可具有一第二基底201、一第二介电层203、多个第二互连结构205、一第一接合层207以及多个半导体贯穿通孔209。第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400具有类似于第一晶粒结构100的元件编号的元件，可具有相同或类似的架构，并可包含相同或类似的材料。第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400的制作技术可类似于在图9到图13所描述的第一晶粒结构100的一程序。
请参考图14，第二晶粒结构200可接合到第一晶粒结构100，并可经由第一晶粒结构100的所述半导体贯穿通孔109而电性耦接到第一晶粒结构100。第三晶粒结构300可接合到第二晶粒结构200，并可经由第二晶粒结构200的所述半导体贯穿通孔209而电性耦接到第二晶粒结构200。第四晶粒结构400可接合到第三晶粒结构300，并可经由第三晶粒结构300的所述半导体贯穿通孔309而电性耦接到第三晶粒结构300。
所述半导体贯穿通孔109、209、309、409可缩减所述晶粒结构100、200、300、400之间的互连长度。因此，可降低半导体元件1A的反射噪声、串扰噪声(crosstalk noise)、同步切换噪声(simultaneous switching noise)、电磁干扰以及延迟(latency)。此外，当寄生电容正比于互连长度时，因为降低的寄生电容所以亦可降低在半导体元件1A中的总功耗。
所述晶粒结构100、200、300、400之间的接合可为混合接合，举例来说，包括介电质对介电直接合、金属对金属接合或是金属对介电质接合或金属对粘着剂接合。该介电质对介电质接合可源自于该接合层与该介电层之间的接合。该金属对金属接合可源自于所述半导体贯穿通孔与所述互连层之间的接合。该金属对介电质接合或是金属对粘着剂接合可源自于所述互连层与该接合层之间的接合。
在一些实施例中，举例来说，用于接合晶粒结构100、200、300、400的接合方法可包括热压接合、钝化罩盖层辅助接合(passivation-capping-layer assisted bonding)或表面活化接合(urface activated bonding)。所述接合方法的制程压力可介于大约100MPa到大约150MPa之间。所述接合方法的制程温度可介于大约室温到大约400℃之间。在一些实施例中，湿式清洗以及气相/蒸汽相热处理的表面处理可用于降低所述接合方法的制程温度或是缩短接合方法的时间损耗。在一些实施例中，在晶粒结构100、200、300、400的接合之后，可执行一退火制程，以加强介电质对介电质接合，并产生金属对金属接合的热膨胀，以便进一步改善接合品质。
第一晶粒结构100、第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400可一起配置成一晶粒堆叠。在一些实施例中，第一晶粒结构100、第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400可全部为存储器晶粒。在一些实施例中，第一晶粒结构100可为一逻辑晶粒，且第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400可为存储器晶粒。应当理解，所述晶粒结构的数量仅用于说明。所述晶粒结构的数量可大于或小于四个。举例来说，所述晶粒结构的数量可为两个(例如第一晶粒结构以及第二晶粒结构)。举例来说，所述晶粒结构的数量可为五个(例如第一晶粒结构到第五晶粒结构)。
请参考图14，所述焊料接头603可形成在第四晶粒结构400的第一接合层407上，并可电性耦接到第四晶粒结构400的所述半导体贯穿通孔409。所述焊料接头603可包含一材料，例如锡或其他适合的材料，例如银或铜。在所述焊料接头603为锡焊料接头的一实施例中，所述焊料接头603的制作技术可包含初始经由蒸镀、电镀、印刷(printing)、焊料转移(solder transfer)或植球(ball placement)而形成一层锡到一厚度，大约10μm到大约100μm之间。一旦该层锡已经形成在第四晶粒结构400的第一接合层407上，则可执行一回焊制程(reflow process)以将该焊料接头603成形为期望的形状。
请参考图15，如图14所描述的中间半导体元件可上下颠倒置放。可执行一薄化制程以缩减载体基底501的厚度以及所述半导体贯穿通孔505的厚度。该薄化制程可为一蚀刻制程、一化学研磨制程或一抛光制程。在该薄化制程之后，可暴露所述半导体贯穿通孔505的各上表面。所述半导体贯穿通孔505的各上表面505TS可大致与载体基底501的上表面501TS为共面。所述半导体贯穿通孔505的各暴露上表面可有利于导热。
按照惯例，在所述晶粒结构之间的接合之后，一载体结构可从一晶粒结构剥离。反之，在本公开的一些实施例中，在晶粒结构100、200、300、400之间的接合之后，载体结构500可接合到第一晶粒结构100。此外，由于散热单元HDU的存在，所以在半导体元件1A的操作期间所累积的热可经由所述导电板507与所述半导体贯穿通孔505而导热到周围(ambient)。意即，可改善半导体元件1A的导热能力。
图16到图20是剖视示意图，例示本公开一些实施例的各半导体元件1B、1C、1D、1E、1F。
请参考图16，半导体元件1B可具有类似于如图15所描述的一结构。在图16中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。载体基底501的厚度可缩减到一垂直位面，该垂直位面在所述半导体贯穿通孔505的上表面505TS上。意即，所述半导体贯穿通孔505可维持被载体基底501所覆盖。所述被覆盖的半导体贯穿通孔505可避免所述半导体贯穿通孔505氧化。
请参考图17，半导体元件1C可具有类似于如图15所描述的一结构。在图17中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。可借由一蚀刻制程缩减载体基底501的厚度，并可缩减到一垂直位面，该垂直位面低于所述半导体贯穿通孔505的上表面505TS。因此，所述半导体贯穿通孔505的各上部可从载体基底501的上表面501TS突伸。所述半导体贯穿通孔505的所述暴露部分可具有较大的表面积，以接触周围。因此，可提升所述半导体贯穿通孔505的导热效率。
请参考图18，半导体元件1D可具有类似于如图15所描述的一结构。在图18中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。
半导体元件1D可包括多个第一虚拟导电层615以及多个第二虚拟导电层617。所述第一虚拟导电层615可设置在接合层509中，并可大致与接合层509及中介接合层601之间的界面为共面。所述第二虚拟导电层617可设置在中介接合层601中，并可大致与接合层509及中介接合层601之间的界面为共面。所述第一虚拟导电层615可垂直对准所述第二虚拟导电层617，并可接触所述第二虚拟导电层617。举例来说，所述第一虚拟导电层615与所述第二虚拟导电层617可包含钨、钴、锆、钽、钛、铝、钌或铜。所述第一虚拟导电层615与所述第二虚拟导电层617可借由提供金属对金属接合而改善接合层509与中介接合层601之间的接合品质。
应当理解，将一元件表示成「虚拟(dummy)元件」，其意指当该半导体元件在操作时，没有外部电压或电流施加到该元件。
请参考图19，半导体元件1E可具有类似于如图15所描述的一结构。在图19中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。
半导体元件1E可包括一热界面层611，设置在中介接合层601与接合层509之间。在一些实施例中，热界面层611可包含充满一可挠性材料的一碳材料，例如一聚合物基质(polymer matrix)。举例来说，热界面层611可包括一般垂直定向石墨及多个纳米碳管，其充满一含氟聚合物橡胶基质(fluoropolymer rubber matrix)。所述纳米碳管的深宽比可介于大约1：1到大约1：100之间。举另一个例子，热界面层611可包括石墨碳(graphiticcarbon)。再举另一个例子，热界面层611可包括热解石墨片(pyrolytic graphite sheet)。在一些实施例中，热界面层611的一热阻在一厚度处可小于0.2℃cm2/Watt，该厚度介于大约250μm到大约450μm之间。热界面层611可对半导体元件1E提供额外的散热能力。
请参考图20，半导体元件1F可具有类似于如图15所描述的一结构。在图20中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。
半导体元件1F可包括多个导电鳍片511，以取代所述导电板507(如图15所示)。所述导电鳍片511可设置在接合层509中，并可相互分隔开。每一个导电鳍片511可接触相对应的其中一个半导体贯穿通孔505。所述导电鳍片511的各宽度W1可大于所述半导体贯穿通孔505的各宽度W2。所述导电鳍片511的总表面积可大于所述导电板507的总表面积，所述导电鳍片511可对半导体元件1F提供额外的散热能力。
图21及图22是剖视示意图，例示本公开另一实施例的制备半导体元件1G的一流程。
请参考图21，一中间半导体元件可以类似于如图2到图13所描述的一程序进行制造。多个焊垫层111可形成在第一接合层107上。所述焊垫层111的各宽度W3可大于所述半导体贯穿通孔109的各宽度W4。举例来说，所述焊垫层111可包含钨、钴、锆、钽、钛、铝、钌、铜、金属碳化物、金属氮化物、过渡金属铝化物或其组合。所述焊垫层111的较大宽度可增加对第一晶粒结构100与第二晶粒结构200之间的接合的容差裕度(tolerance window)。换言之，可降低第一晶粒结构100与所述第二互连层205之间的对准需求。
请参考图21，一第二接合层113可形成在第一接合层107上，并可覆盖所述焊垫层111。在一些实施例中，举例来说，第二接合层113可包含一非有机材料，选自未掺杂硅酸盐玻璃、氮化硅、氮氧化硅、氧化硅、氧化氮化硅及其组合。在一些实施例中，举例来说，第二接合层113可包含一聚合物层，例如一环氧树脂(epoxy)、聚烯亚胺(polyimide)、苯并环丁烯(benzocyclobutene)、聚苯并恶唑(polybenzoxazole)或类似物。第二接合层113的制作技术可包含一沉积制程，例如化学气相沉积、等离子体加强气相沉积、蒸镀或旋转涂布。可执行一平坦化制程，例如化学机械研磨，以暴露所述焊垫层111的各上表面。
请参考图22，其他元件的制作技术可包含类似于如图14及图15所描述的一程序。第二晶粒结构200的所述焊垫层211以及第三晶粒结构300的所述焊垫层311可具有类似于第一晶粒结构100的所述焊垫层111的结构。第二晶粒结构200的第二接合层213以及第三晶粒结构300的第二接合层313可具有类似于第一晶粒结构100的第二接合层113的结构。
图23到图26是剖视示意图，例示本公开另一实施例的制备半导体元件1H的一流程。
请参考图23，一中间半导体元件可以类似于如图2到图19所描述的一程序所制造。应当理解，所述半导体贯穿通孔109并未形成在目前阶段中的第一基底101中。
请参考图24，如图23所描述的中间半导体元件可上下颠倒置放并接合到接合层509上。
请参考图25，在第一基底101上使用一蚀刻制程、一化学研磨制程以及一抛光制程而执行一薄化制程，以缩减第一基底101的一厚度。接下来，所述半导体贯穿通孔109可形成在第一基底101中，并可接触所述第一互连层105。第一接合层107可以类似于如图11到图13所描述的一程序而形成在第一基底101。
请参考图26，第二晶粒结构200、第三晶粒结构300、第四晶粒结构400的第一接合层407以及所述焊料接头603的制作技术可包含类似于图14及图15所描述的一程序。应当理解，在所述半导体贯穿通孔209、所述半导体贯穿通孔309以及所述半导体贯穿通孔409可分别形成在晶粒结构200、300、400接合之前或者是可形成在晶粒结构200、300、400接合之前。
图27及图28是剖视示意图，例示本公开另一实施例的制备半导体元件1I的一流程。
请参考图27，一中间半导体元件可以类似于如图2到图14所描述的一程序所制造。在一些实施例中，多个第一虚拟半导体贯穿通孔605可沿着第四晶粒结构400、第三晶粒结构300、第二晶粒结构200、第一晶粒结构100以及中介接合层601而形成。在晶粒结构100、200、300、400接合之后，可形成所述第一虚拟半导体贯穿通孔605。在一些实施例中，多个导电特征可形成在晶粒结构100、200、300、400中。在晶粒结构100、200、300、400接合之后，所述导电特征可垂直对准以配置成所述第一虚拟半导体贯穿通孔605。所述第一虚拟半导体贯穿通孔605可包含与所述半导体贯穿通孔505相同材料，但并不以此为限。
请参考图28，如图27所描述的中间半导体元件可反向设置。可执行一平坦制程，例如化学机械研磨，以暴露所述半导体贯穿通孔505。累积在晶粒结构100、200、300、400中的热可经由所述第一虚拟半导体贯穿通孔605而导热到载体结构500。
图29是剖视示意图，例示本公开另一实施例的半导体元件1J。
请参考图29，半导体元件1J可具有类似于如图28所描述的一结构。在图29中相同或类似于图28中的元件已标示成类似的元件编号，并已省略其重复描述。所述第一虚拟半导体贯穿通孔605可接触所述导电板507。累积在晶粒结构100、200、300、400中的热可经由所述第一虚拟半导体贯穿通孔605而导热到载体结构500的散热单元HDU。
图30及图31是剖视示意图，例示本公开另一实施例的制备半导体元件1K的一流程。
请参考图30，一中间半导体元件可以类似于如图2到图9所描述的一程序所制造。多个第二虚拟半导体贯穿通孔607可沿着中介接合层601与第一介电层103所形成，并延伸到第一基底101。在一些实施例中，所述第二虚拟半导体贯穿通孔607可沿着中介接合层601而形成并延伸到第一介电层103。所述第二虚拟半导体贯穿通孔607可包含与所述半导体贯穿通孔109相同的材料，但并不以此为限。在一些实施例中，所述第二虚拟半导体贯穿通孔607大致均匀分布在第一晶粒结构100中。
请参考图31，其他元件的制作技术可包含类似于如图10到图15所描述的一程序。累积在第一晶粒结构100中的热可经由所述第二虚拟半导体贯穿通孔607而导热到载体结构500。
图32到图34是剖视示意图，例示本公开另一实施例的各半导体元件1L、1M、1N。
请参考图32，半导体元件1L可具有类似于如图15所描述的一结构。在图32中相同或类似于图15中的元件已标示成类似的元件编号，并已省略其重复描述。半导体元件1L可包括所述第一虚拟半导体贯穿通孔605以及所述第二虚拟半导体贯穿通孔607·所述第一虚拟半导体贯穿通孔605可沿着中介接合层601、第一晶粒结构100、第二晶粒结构200、第三晶粒结构300以及第四晶粒结构400而设置。所述第二虚拟半导体贯穿通孔607可沿着中介接合层601与第一介电层103而设置，并延伸到第一基底101。意即，所述第一虚拟半导体贯穿通孔605的各深度可大于所述第二虚拟半导体贯穿通孔607的各深度。所述第一虚拟半导体贯穿通孔605的各宽度W5可大于或等于所述第二虚拟半导体贯穿通孔607的各宽度W6。
请参考图33，半导体元件1M可具有类似于如图32所描述的一结构。在图33中相同或类似于图32中的元件已标示成类似的元件编号，并已省略其重复描述。半导体元件1M还包括多个第三虚拟半导体贯穿通孔609。所述第三虚拟半导体贯穿通孔609可沿着第一晶粒结构100与第二介电层203而设置，并延伸到第二基底201。所述第三虚拟半导体贯穿通孔的各深度可大于所述第二虚拟半导体贯穿通孔607的各深度。所述第一虚拟半导体贯穿通孔605的各宽度W5可大于或等于所述第三虚拟半导体贯穿通孔609的各宽度W7。
请参考图34，半导体元件1N可具有类似于如图33所描述的一结构。在图34中相同或类似于图33中的元件已标示成类似的元件编号，并已省略其重复描述。所述第一虚拟半导体贯穿通孔605、所述第二虚拟半导体贯穿通孔607以及所述第三虚拟半导体贯穿通孔609可接触所述导电板507以用于更有效地导热。
本公开的一实施例提供一种半导体元件，具有一晶粒堆叠；一中介接合层，设置在该晶粒堆叠上；以及一载体结构，包括一载体基底，设置在该中介接合层上；以及多个半导体贯穿通孔，设置在该载体基底中以及在该中介接合层以进行导热。
本公开的另一实施例提供一种半导体元件的制备方法，包括提供一载体基底；形成多个半导体贯穿通孔载该载体基底中以进行导热；形成一接合层在该载体机体上；提供一第一晶粒结构，该第一晶粒结构包括多个半导体贯穿通孔；形成一中介接合层在该第一晶粒结构上；经由该中介接合层将该第一晶粒结构接合到该载体结构的该接合层上；以及将一第二晶粒结构接合到该第一晶粒结构上。该载体基底、所述半导体贯穿通孔以及该接合层一起配置成一载体结构。该第二晶粒结构与该第二晶粒结构借由所述半导体贯穿通孔而电性耦接。
由于本公开该半导体元件的设计，在半导体元件1A操作期间所累积的热可经由所述导电板507以及所述半导体贯穿通孔505(例如散热单元HDU)而导热到周围。意即，可改善半导体元件1A的导热能力。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请案的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的揭示内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，此等制程、机械、制造、物质组成物、手段、方法、或步骤包含于本申请案的权利要求内。

Claims (20)

1.一种半导体元件，包括：
一晶粒堆叠；
一中介接合层，设置在该晶粒堆叠上；以及
一载体结构，包括：
一载体基底，设置在该中介接合层上；以及
多个半导体贯穿通孔，设置在该载体基底中以及在该中介接合层以进行导热。
2.如权利要求1所述的半导体元件，其中该载体结构包括：
一接合层，设置在该载体基底与该中介接合层之间；以及
一导电板，设置在该载体结构的该接合层中并接触该载体结构的所述半导体贯穿通孔。
3.如权利要求2所述的半导体元件，其中该晶粒堆叠包括：
一第一晶粒结构，设置在该中介接合层的下方；以及
一第二晶粒结构，设置在该第一晶粒结构下方。
4.如权利要求3所述的半导体元件，其中该第一晶粒结构与该第二晶粒结构为存储器晶粒。
5.如权利要求3所述的半导体元件，其中该第一晶粒结构为一存储器晶粒，而该第二晶粒结构为一逻辑晶粒。
6.如权利要求3所述的半导体元件，其中该载体结构的所述半导体贯穿通孔的各上表面与该载体结构的一上表面大致为共面。
7.如权利要求3所述的半导体元件，其中该载体结构的所述半导体贯穿通孔的各上表面被该载体基底所覆盖。
8.如权利要求3所述的半导体元件，其中该第一晶粒结构包括：
一第一基底，设置在该中介接合层的相反处；
一第一介电层，设置在该第一基底与该中介接合层之间；
一第一接合层，设置在该第一基底与该第二晶粒结构之间；
多个第一互连层，设置在该第一介电层中；
该第一晶粒结构的多个半导体贯穿通孔，沿着该第一晶粒结构的该第一基底与该第一接合层设置，并电性连接所述第一互连层与该第二晶粒结构；
其中该第二晶粒结构包括：
一第二基底，设置在该第一晶粒结构的该第一接合层的相反处；
一第二介电层，设置在该第二基底与该第一晶粒结构的该第一接合层之间；
该第二晶粒结构的一第一接合层，设置在该第二基底下方；
多个第二互连层，设置在该第二介电层中并电性连接到该第一晶粒结构的所述半导体贯穿通孔；以及
该第二晶粒结构的多个半导体贯穿通孔，沿着该第二晶粒结构的该第二基底与该第一接合层而设置，并电性连接到所述第二互连层。
9.如权利要求8所述的半导体元件，还包括多个焊料接头，电性连接到该第二晶粒结构的所述半导体贯穿通孔。
10.如权利要求8所述的半导体元件，其中该第一晶粒结构包括：
一第二接合层，设置在该第一晶粒结构的该第一接合层与该第二介电层之间；以及
多个焊垫层，设置在该第二接合层中并电性连接所述第二互连层以及该第一晶粒结构的所述半导体贯穿通孔。
11.如权利要求10所述的半导体元件，其中所述焊垫层的各宽度大于该第一晶粒结构的所述半导体贯穿通孔的各宽度。
12.如权利要求8所述的半导体元件，还包括多个第一虚拟半导体贯穿通孔，沿着该第一晶粒结构、该第二晶粒结构以及该中介接合层设置。
13.如权利要求8所述的半导体元件，还包括多个第一虚拟半导体贯穿通孔，沿着该第一晶粒结构、该第二晶粒结构以及该中介接合层设置，延伸到该载体结构的该接合层，并热接触该导电板。
14.如权利要求12所述的半导体元件，还包括多个第二虚拟半导体贯穿通孔，沿着该中介接合层与该第一介电层设置，并延伸到该第一基底。
15.如权利要求14所述的半导体元件，其中所述第一虚拟半导体贯穿通孔的各宽度大于所述第二虚拟半导体贯穿通孔的各宽度。
16.如权利要求14所述的半导体元件，还包括多个第三虚拟半导体贯穿通孔，沿着该第一晶粒结构设置并延伸到该第二晶粒结构。
17.如权利要求14所述的半导体元件，其中所述第二虚拟半导体贯穿通孔大致均匀分布在该第一晶粒结构中。
18.如权利要求8所述的半导体元件，还包括一热界面层，设置在该中介接合层与该载体结构的该接合层之间，其中该热界面层包含充满一可挠性材料的一碳材料。
19.如权利要求1所述的半导体元件，其中该载体结构包括：
一接合层，设置在该载体基底与该中介接合层之间；以及
多个导电鳍片，设置在该载体结构的该接合层中并与该载体结构的所述半导体贯穿通孔接触。
20.一种半导体元件的制备方法，包括：
提供一载体基底；
形成多个半导体贯穿通孔载该载体基底中以进行导热；
形成一接合层在该载体机体上，其中该载体基底、所述半导体贯穿通孔以及该接合层一起配置成一载体结构；
提供一第一晶粒结构，该第一晶粒结构包括多个半导体贯穿通孔；
形成一中介接合层在该第一晶粒结构上；
经由该中介接合层将该第一晶粒结构接合到该载体结构的该接合层上；以及
将一第二晶粒结构接合到该第一晶粒结构上，其中该第二晶粒结构与该第二晶粒结构借由所述半导体贯穿通孔而电性耦接。
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