CN113921463A - 半导体元件及其制备方法 - Google Patents
半导体元件及其制备方法 Download PDFInfo
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- CN113921463A CN113921463A CN202110598012.9A CN202110598012A CN113921463A CN 113921463 A CN113921463 A CN 113921463A CN 202110598012 A CN202110598012 A CN 202110598012A CN 113921463 A CN113921463 A CN 113921463A
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Abstract
本公开提供一种半导体元件及该半导体元件的制备方法。该半导体元件包括一第一晶粒、一第一导电特征、一第二晶粒、一第一遮罩层、一导电填充层、多个绝缘层以及多个保护层;该第一导电特征位在该第一晶粒中;该第二晶粒位在该第一晶粒上;该第一遮罩层位在该第二晶粒上;所述导电填充层位在沿着该第一遮罩层与该第二晶粒处,并延伸到第一晶粒,且接触该第一导电特征;所述绝缘层位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第二晶粒之间;所述保护层位在该导电填充层与该第一遮罩层之间,并覆盖所述绝缘层的各上部。
Description
技术领域
本申请案主张2020年7月10日申请的美国正式申请案第16/926,281号的优先权及益处,该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种半导体元件以及该半导体元件的制备方法。特别是涉及一种具有多个保护层以降低金属对硅的泄漏的半导体元件以及具有所述保护层的该半导体元件的制备方法。
背景技术
半导体元件是使用在不同的电子应用,例如个人电脑、手机、数码相机,或其他电子设备。半导体元件的尺寸是逐渐地变小,以符合计算能力所逐渐增加的需求。然而,在尺寸变小的制程期间,是增加不同的问题,且如此的问题在数量与复杂度上持续增加。因此,仍然持续着在达到改善品质、良率、效能与可靠度以及降低复杂度方面的挑战。
上文的“先前技术”说明仅是提供背景技术,并未承认上文的“先前技术”说明揭示本公开的标的,不构成本公开的先前技术,且上文的“先前技术”的任何说明均不应作为本案的任一部分。
发明内容
本公开的一实施例提供一种半导体元件,包括一第一晶粒;一第一导电特征,位在该第一晶粒中;一第二晶粒,位在该第一晶粒上;一第一遮罩层,位在该第二晶粒上;一导电填充层,位在沿着该第一遮罩层以及该第二晶粒处,延伸到该第一晶粒并接触该第一导电特征;多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第二晶粒之间;以及多个保护层,位在该导电填充层与该第一遮罩层之间,并覆盖所述绝缘层的上部。
在本公开的一些实施例中,所述绝缘层的最高点位在一垂直位面,是齐平于该第一遮罩层的一下表面的一垂直位面。
在本公开的一些实施例中,在该第一遮罩层与所述保护层之间的多个界面是呈锥形。
在本公开的一些实施例中,在该第一遮罩层的一上表面与位在该第一遮罩层与所述保护层之间的所述界面之间的一角度,是介于大约120度到大约135度之间。
在本公开的一些实施例中,位在所述保护层与该导电填充层之间的多个界面是大致呈垂直。
在本公开的一些实施例中,该导电填充层是由多晶硅、钨、铜、纳米碳管或焊料合金所制,所述绝缘层是由氧化硅、氮化硅、氮氧化硅、四乙基硅酸盐(tetra-ethyl ortho-silicate)、聚对二甲苯(parylene)、环氧树脂(epoxy)或聚对二甲苯(poly(p-xylene))所制。
在本公开的一些实施例中,该半导体元件还包括一阻障层,位在所述绝缘层与该导电填充层之间,其中该阻障层是由钽、氮化钽、钛、氮化钛、铼、硼化镍或氮化钽/钽双层所制。
在本公开的一些实施例中,该半导体元件还包括一粘着层,位在该阻障层与该导电填充层之间,其中该粘着层由钛、钽、钛钨或氮化锰所制。
在本公开的一些实施例中,该半导体元件还包括一晶种层,位在该粘着层与该导电填充层之间,其中该晶种层具有一厚度,是介于大约10nm到大约40nm之间。
在本公开的一些实施例中,该导电填充层的一宽度是介于大约1μm到大约22μm之间。
在本公开的一些实施例中,该导电填充层的一深度介于大约20μm到大约160μm之间。
在本公开的一些实施例中,该导电填充层的一深宽比是介于大约1:2到大约1:35之间。
在本公开的一些实施例中,位在该第一遮罩层与所述保护层之间的所述界面是大致呈垂直。
本公开的另一实施例提供一种半导体元件,包括一第一晶粒;一第一导电特征,位在该第一晶粒中;一第一遮罩层,位在该第一晶粒上;一导电填充层,位在沿着该第一遮罩层处,延伸到该第一晶粒并接触该第一导电特征;多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第一遮罩层之间;以及多个保护层,位在该导电填充层与所述绝缘层之间;其中所述保护层的最低点是位在一垂直位面,该垂直位面是较低于在该第一遮罩层的一下表面的一垂直位面。
在本公开的一些实施例中,在该第一遮罩层与所述绝缘层之间的多个界面是呈锥形。
在本公开的一些实施例中,位在该导电填充层与所述保护层之间的多个界面是大致呈垂直。
本公开的另一实施例提供一种半导体元件的制备方法,包括执行一接合制程以接合一第二晶粒到一第一晶粒上;形成一第一遮罩层在该第二晶粒上;形成一第一开口以穿过该第一遮罩层以及该第二晶粒,并延伸到该第一晶粒;形成多个绝缘层在该第一开口的多个侧壁上;形成多个保护层以覆盖所述绝缘层的上部;以及形成一导电填充层在该第一开口中。
在本公开的一些实施例中,该半导体元件的制备方法还包括:在形成所述绝缘层在该第一开口的所述侧壁上的步骤之前,执行一蚀刻制程以扩展在该第一遮罩层中的该第一开口的一步骤。
在本公开的一些实施例中,该蚀刻制程具有该第一遮罩层对该第二晶粒的一基底的一蚀刻率,其是介于大约100:1到大约1.05:1。
在本公开的一些实施例中,所述保护层是由氧化铝、氧化铪、氧化锆、氧化钛、氮化钛、氮化钨、氮化硅或氧化硅所制。
由于本公开该半导体元件的设计,所述保护层可提供额外的保护,以降低金属对硅的泄漏。此外,由于所述保护层的几何形状,该导电填充层的形成是无须任何孔洞(void)。总而言之,其是可改善半导体元件的制造良率。
上文已相当广泛地概述本公开的技术特征及优点,而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中具有通常知识者应了解,可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中具有通常知识者亦应了解,这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考量图式时,可得以更全面了解本申请案的揭示内容,图式中相同的元件符号是指相同的元件。
图1为依据本公开一实施例的一种半导体元件的剖视示意图。
图2到图6为依据本公开一些实施例的各半导体元件的剖视示意图。
图7为依据本公开一实施例中一种半导体元件的制备方法的流程示意图。
图8到图21为依据本公开一实施例中制备该半导体元件的一流程的剖视示意图。
图22到图24为依据本公开一实施例中制备一半导体元件的一流程的剖视示意图。
图25到图28为依据本公开一实施例中制备一半导体元件的一流程的剖视示意图。
图29到图31为依据本公开一实施例中制备一半导体元件的一流程的剖视示意图。
其中,附图标记说明如下:
1A:半导体元件
1B:半导体元件
1C:半导体元件
1D:半导体元件
1E:半导体元件
1F:半导体元件
10:方法
100:第一晶粒
101:第一基底
103:第一介电层
105:第一钝化层
107:第一装置元件
109:第一导电特征
111:第一虚拟导电特征
200:第二晶粒
201:第二基底
201BS:下表面
203:第二介电层
205:第二钝化层
207:第二装置元件
211:第二虚拟导电特征
301:第一遮罩层
301BS:下表面
301TS:上表面
401:导电填充层
403:绝缘层
403B:下区段
403C:覆盖区段
403S:侧区段
403T:上区段
403TP:最高点
405:阻障层
407:粘着层
409:晶种层
501:保护层
501BP:最低点
501S:侧壁
601:第一开口
603:第一导电材料
D1:深度
IF01:界面
IF03:界面
IF07:界面
IF09:界面
S11:步骤
S13:步骤
S15:步骤
S17:步骤
S19:步骤
S21:步骤
S23:步骤
T1:厚度
W1:宽度
Z:方向
α:角度
具体实施方式
以下描述了组件和配置的具体范例,以简化本公开的实施例。当然,这些实施例仅用以例示,并非意图限制本公开的范围。举例而言,在叙述中第一部件形成于第二部件之上,可能包含形成第一和第二部件直接接触的实施例,也可能包含额外的部件形成于第一和第二部件之间,使得第一和第二部件不会直接接触的实施例。另外,本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚,除非内文中特别说明,其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所绘示的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
应当理解,当形成一个部件在另一个部件之上(on)、与另一个部件相连(connected to)、及/或与另一个部件耦接(coupled to),其可能包含形成这些部件直接接触的实施例,并且也可能包含形成额外的部件介于这些部件之间,使得这些部件不会直接接触的实施例。
应当理解,尽管这里可以使用术语第一,第二,第三等来描述各种元件、部件、区域、层或区段(sections),但是这些元件、部件、区域、层或区段不受这些术语的限制。相反,这些术语仅用于将一个元件、组件、区域、层或区段与另一个区域、层或区段所区分开。因此,在不脱离本发明进步性构思的教导的情况下,下列所讨论的第一元件、组件、区域、层或区段可以被称为第二元件、组件、区域、层或区段。
除非内容中另有所指,否则当代表定向(orientation)、布局(layout)、位置(location)、形状(shapes)、尺寸(sizes)、数量(amounts),或其他量测(measures)时,则如在本文中所使用的例如“同样的(same)”、“相等的(equal)”、“平坦的(planar)”,或是“共面的(coplanar)”等术语(terms)并非必要意指一精确地完全相同的定向、布局、位置、形状、尺寸、数量,或其他量测,但其意指在可接受的差异内,是包含差不多完全相同的定向、布局、位置、形状、尺寸、数量,或其他量测,而举例来说,所述可接受的差异是可因为制造流程(manufacturing processes)而发生。术语“大致地(substantially)”是可被使用在本文中,以表现出此意思。举例来说,如大致地相同的(substantially the same)、大致地相等的(substantially equal),或是大致地平坦的(substantially planar),是为精确地相同的、相等的,或是平坦的,或者是其是可为在可接受的差异内的相同的、相等的,或是平坦的,而举例来说,所述可接受的差异是可因为制造流程而发生。
应当理解,术语“大约(about)”修饰成分(ingredient)、部件的一数量(quantity),或是本公开的反应物(reactant),其是表示可发生的数值数量上的变异(variation),举例来说,其是经由典型的测量以及液体处理程序(liquid handlingprocedures),而该液体处理程序用于制造浓缩(concentrates)或溶液(solutions)。再者,变异的发生可源自于应用在制造组成成分(compositions)或实施所述方法或其类似方式在测量程序中的非故意错误(inadvertent error)、在制造中的差异(differences)、来源(source)、或成分的纯度(purity)。在一方面,术语“大约(about)”意指报告数值的10%以内。在另一方面,术语“大约(about)”意指报告数值的5%以内。在再另一方面,术语“大约(about)”意指报告数值的10、9、8、7、6、5、4、3、2或1%以内。
在本公开中,一半导体元件通常意指可通过利用半导体特性(semiconductorcharacteristics)运行的一元件,而一光电元件(electro-optic device)、一发光显示元件(light-emitting display device)、一半导体电路(semiconductor circuit)以及一电子元件(electronic device),是均包括在半导体元件的范畴中。
应当理解,在本公开的描述中,上方(above)(或之上(up))是对应Z方向箭头的该方向,而下方(below)(或之下(down))是对应Z方向箭头的相对方向。
图1为依据本公开一实施例的一种半导体元件1A的剖视示意图。
请参考图1,半导体元件1A可包括一第一晶粒100、一第二晶粒200、一第一遮罩层301、一导电填充层401、多个绝缘层403、一阻障层405、一粘着层407、一晶种层409以及多个保护层501。
请参考图1,第一晶粒100可包括一第一基底101、一第一介电层103、一第一钝化层105、多个第一装置元件107、一第一导电特征109以及多个第一虚拟导电特征111。
请参考图1,举例来说,第一基底101可由下列材料所制:硅、锗、硅锗、硅碳、硅锗碳、镓、砷化镓、砷化铟、磷化铟或其他IV-IV族、III-V族或II-VI族半导体材料。在一些实施例中,基底101可包括一有机半导体或一层式的半导体,例如硅/硅锗、绝缘体上覆硅或绝缘体上覆硅锗。当基底101由绝缘体上覆硅所制时,基底101可包括一上半导体层、一下半导体层以及一埋入隔离层,上半导体层与下半导体层是由硅所制,而埋入隔离层是可将上半导体层与下半导体层分隔开。举例来说,埋入隔离层可包含一晶体硅或一非晶硅氧化物、氮化物或其组合。
请参考图1,第一介电层103可设置在第一基底101上。在一些实施例中,第一介电层106可为一堆迭层结构。第一介电层103可包括多个第一隔离子层。每一隔离子层可具有一厚度,介于大约0.5μm到大约3.0μm之间。举例来说,多个隔离子层可由下列材料所制:氧化硅、硼磷硅酸盐玻璃(borophosphosilicate glass)、未掺杂硅酸盐玻璃(undopedsilicate glass)、氟硅酸盐玻璃(fluorinated silicate glass)、低介电常数介电材料、类似物或其组合。多个第一隔离子层可由不同材料所制,但并不以此为限。低介电常数介电材料可具有一介电常数,是小于3.0,或甚至小于2.5。在一些实施例中,低介电常数介电材料可具有一介电常数,是小于2.0。
请参考图1,第一钝化层105可设置在第一介电层103上。在一些实施例中,第一钝化层105可为一多层结构,是包括一层氧化硅以及一层氮化硅。
请参考图1,所述第一装置元件107可设置在第一介电层103的一下部中。在一些实施例中,所述第一装置元件107可设置在第一基底101上(为了清楚,在图1中仅显示三个第一装置元件107)。举例来说,所述第一装置元件107可为双极接面晶体管(bipolarjunction transistors)、金属氧化物半导体场效晶体管、二极管、快闪存储器、动态随机存取存储器、静态随机存取存储器、电可抹除可编程只读存储器(electrically erasableprogrammable read-only memories)、影像感测器、微机电系统(micro-electro-mechanical systems)、主动元件或被动元件。
请参考图1,第一导电特征109可设置在第一介电层103中。在所述的实施例中,第一导电特征109可为一导电线。应当理解,例如导电线、导电通孔、导电接触点、着陆垫的其他导电特征,是亦设置在第一介电层103中,但为了清楚,在图1中并未显示。举例来说,第一导电特征109可由铝、铜、钛、类似物或其组合所制。第一导电特征109与所述第一装置元件107可电性耦接。
请参考图1,所述第一虚拟导电特征111可设置在第一钝化层105中。所述第一虚拟导电特征111的上表面可大致与第一钝化层105的上表面为共面。举例来说,所述第一虚拟导电特征111可由铝、铜、钛、类似物或其组合所制。
应当理解,当成一“虚拟(dummy)”元件的一元件,是指当半导体元件在操作时,没有外部电压或电流施加到该元件。
请参考图1,第二晶粒200可设置在第一晶粒100上。在一些实施例中,第一晶粒100与第二晶粒200可提供不同功能。举例来说,第一晶粒100可提供一逻辑功能,且第二晶粒200可提供一存储器功能。在一些实施例中,第一晶粒100与第二晶粒200可提供相同功能。
请参考图1,在一些实施例中,第二晶粒200可具有一结构,是类似于第一晶粒100的结构,但是以一上下颠倒的方式置放。尤其是,第二晶粒200可包括一第二基底201、一第二介电层203、一第二钝化层205、多个第二装置元件207、多个第二导电特征(图未示)以及多个第二虚拟导电特征211。
请参考图1,第二钝化层205可设置在第一钝化层105上。第二介电层203可设置在第二钝化层205上。第二基底201可设置在第二介电层203上。所述第二装置元件207可设置在第二介电层203中,并邻近第二基底201设置。所述第二导电特征(为了清楚,图1中未显示)可设置在第二介电层203中。所述第二虚拟导电特征211可设置在第二钝化层205中,并可接触所述第一虚拟导电特征111。所述第二虚拟导电特征211与所述第一虚拟导电特征111可促进在第一晶粒100与第二晶粒200之间的一接合制程,并可改善在第二晶粒200与第一晶粒100之间的接合强度。
请参考图1,第一遮罩层301可设置在第二基底201上。在一些实施例中,举例来说,第一遮罩层301可由下列材料所制:氧化硅、氮化硅、氮氧化硅、氧化氮化硅或类似物。在一些实施例中,相较于第二晶粒200的第二基底201,第一遮罩层301可由具有一较高蚀刻率的一材料所制。举例来说,第一遮罩层301对第二基底201的一蚀刻率可介于大约100:1到大约1.05:1之间。举另一个例子,第一遮罩层301对第二基底201的蚀刻率可介于大约20:1到大约10:1之间。
应当理解,在本公开中,氮氧化硅表示一物质(substance),其是包含硅、氮以及氧,且氧的一比率大于氮的一比率。氧化氮化硅(Silicon nitride oxide)表示一物质,其是包含硅、氧以及氮,且氮的一比率大于氧的一比率。
请参考图1,导电填充层401可设置来沿着第一遮罩层301、第二基底201、第二介电层203、第二钝化层205以及第一钝化层105,延伸到第一介电层103并接触第一导电特征109。导电填充层401与第一导电特征109是电性耦接。导电填充层401的上表面可大致与第一遮罩层301的上表面301TS为共面。
在一些实施例中,导电填充层401可具有一宽度W1,是介于大约1μm到大约22μm之间。尤其是,导电填充层401的宽度W1可介于大约5μm到大约15μm之间。在一些实施例中,导电填充层401可具有一深度D1,是介于大约20μm到大约160μm之间。尤其是,导电填充层401的深度D1可介于大约50μm到大约130μm之间。在一些实施例中,导电填充层401可具有一深宽比,是介于大约1:2到大约1:35之间。尤其是,导电填充层401的深宽比可介于大约1:10到大约1:25之间。举例来说,导电填充层401可由多晶硅、钨、铜、纳米碳管(carbon nanotube)或焊料合金所制。
请参考图1,晶种层409可设置在导电填充层401的各侧壁与下表面上。晶种层409的各上表面可大致与导电填充层401的上表面为共面。晶种层409可具有一厚度,是介于大约10nm到大约40nm之间。举例来说,晶种层409可由铜所制。在形成导电填充层401期间,晶种层409可降低一开口的一电阻率(resistivity)。
请参考图1,粘着层407可设置在晶种层409的各侧壁与下表面上。粘着层407的各上表面可大致与导电填充层401的上表面为共面。举例来说,粘着层407可由钛、钽、钛钨或氮化锰(manganese nitride)所制。粘着层407可改善晶种层409与阻障层405之间的粘性。
请参考图1,阻障层405可设置在粘着层407的各侧壁与下表面上。阻障层405的各上表面可大致与导电填充层401的上表面为共面。举例来说,阻障层405可由下列材料所制:钽、氮化钽、钛、氮化钛、铼(rhenium)、硼化镍或氮化钽/钽双层(tantalum nitride/tantalum bilayer)。阻障层405可抑制导电填充层401的导电材料扩散进入第二介电层203、第二基底201、第二钝化层205、第一钝化层105或第一介电层103。
请参考图1,所述绝缘层403可形成在阻障层405的所述侧壁上。为了便于描述,仅描述一个绝缘层403。绝缘层403设置在第一遮罩层301的下表面301BS下方的部分,是可表示成绝缘层403的侧区段403S。
请参考图1,侧区段403S可设置在导电填充层401与第二晶粒200之间,以及设置在导电填充层401与第一钝化层105之间。在一些实施例中,侧区段403S可设置在导电填充层401与第一介电层103之间。侧区段403S的下端可接触第一导电特征109。在一些实施例中,所述绝缘层403的最高点403TP可位在一垂直位面,该垂直位面是齐平于第一遮罩层301的下表面301BS。在一些实施例中,绝缘层403的最高点403TP可位在一垂直位面,该垂直位面是较低于第一遮罩层301的下表面301BS,并位在第二基底201的下表面201BS上方。
在一些实施例中,相较于第一遮罩层301,所述绝缘层403可由具有一较高蚀刻率的一材料所制。举例来说,所述绝缘层406对第一遮罩层301的一蚀刻率可介于大约100:1到大约1.05:1之间。举另外一个例子,所述绝缘层403对第一遮罩层301的蚀刻率可介于大约20:1到大约10:1之间。在一些实施例中,举例来说,所述绝缘层403可由氧化硅、氮化硅、氮氧化硅或四乙基硅酸盐(tetra-ethyl ortho-silicate)所制。所述绝缘层403可具有一厚度,是介于大约50nm到大约200nm之间。在一些实施例中,举例来说,所述绝缘层403可由聚对二甲苯(parylene)、环氧树脂(epoxy)或聚对二甲苯(poly(p-xylene))所制。所述绝缘层403可具有一厚度,是介于大约1μm到大约5μm之间。所述绝缘层403可确保导电填充层401在第二晶粒200与第一钝化层105中被电性绝缘。
导电填充层401可缩减第一晶粒100与第二晶粒200之间的内连接长度。因此,可降低半导体元件1A的反射噪声(reflection noise)、串音噪声(crosstalk noise)、同步切换噪声(simultaneous switching noise)、电磁干扰(electromagnetic interference)以及延迟(latency)。此外,当寄生电容正比于内连接长度时,因为寄生电容的减少,所以亦可降低在半导体元件1A中的总功耗。
请参考图1,所述保护层501可设置在阻障层405与第一遮罩层301之间,以及设置在阻障层405与所述绝缘层403的侧区段403S之间。所述保护层501可覆盖测区段403S的上部。所述保护层501的最低点501BP可位在一垂直位面,该垂直位面是较低于所述绝缘层403的最高点403TP的垂直位面。所述保护层501的上表面可大致与第一遮罩层301的上表面301TS为共面。
请参考图1,位在第一遮罩层301与所述保护层501之间的多个界面IF01可呈锥形(tapered)。在第一遮罩层301的上表面301TS与位在第一遮罩层301与所述保护层501之间的所述界面IF01之间的角度α,是可介于大约120度到大约135度之间。位在所述保护层501与阻障层405之间的多个界面IF03是大致呈垂直。
举例来说,所述保护层501可由下列材料所制:氧化铝、氧化铪、氧化锆、氧化钛、氮化钛、氮化钨、氮化硅或氧化硅。
没有本公开的所述保护层501存在,则在所述绝缘层403形成期间可能会损伤所述绝缘层403,且接下来在导电填充层401形成期间可能会产生一金属对硅的泄漏。所以,可能会影响到半导体元件1A的效能/良率。反之,在所述的实施例中,所述保护层501可形成一阻障,以避免在导电填充层401形成期间,导电填充层401的金属扩散进入第二晶粒200或第一晶粒100。因此,可改善半导体元件1A的效能/可靠度。
图2到图6为依据本公开一些实施例的各半导体元件1B、1C、1D、1E、1F的剖视示意图。
请参考图2,在半导体元件1B中,绝缘层403还包括一上区段403T,其是为绝缘层403设置在第一遮罩层301的下表面301BS上方的部分。上区段403T可设置在保护层501与第一遮罩层301之间。在所述上区段403T与第一遮罩层301之间的多个界面IF07可呈锥形。在所述上区段403T与所述保护层501之间的多个界面IF09可呈锥形。在一些实施例中,所述保护层501与阻障层405之间的所述界面IF03可大致呈垂直。在一些实施例中,所述保护层501与阻障层405之间的所述界面IF03可呈锥形。
请参考图3,在半导体元件1C中,在第一遮罩层301与所述保护层501之间的所述界面IF01可大致呈垂直。在所述保护层501与阻障层405之间的所述界面IF03可大致呈垂直。
请参考图4,在半导体元件1D中,在所述上区段403T与第一遮罩层301间的所述界面IF07可大致呈垂直。在所述上区段403T与所述保护层501之间的所述界面IF09可大致呈垂直。所述保护层501的一厚度T1可沿着方向Z并朝向第二晶粒200而逐渐缩减。
请参考图5,在半导体元件1E中,第一介电层103可设置在第一钝化层105上。第一基底101可设置在第一介电层103上。第一遮罩层301可设置在第一基底101上。导电填充层401可设置来沿着第一遮罩层301以及第一基底101,延伸到第一介电层103并接触第一导电特征109。所述绝缘层403可设置在第一遮罩层301与所述保护层501之间,以及设置在第一晶粒100与所述保护层501之间。在所述上区段403T与第一遮罩层301之间的所述界面IF07可呈锥形。在所述上区段403T与所述保护层501之间的所述界面IF09可呈锥形。在一些实施例中,在所述保护层501与阻障层405之间的所述界面IF03可大致呈垂直。
请参考图6,在半导体元件1F中,所述绝缘层403的最高点403TP可位在一垂直位面,该垂直位面是齐平于第一遮罩层301的下表面301BS。所述保护层501可覆盖所述侧区段403S的上部。位在第一遮罩层301与所述保护层501之间的所述界面IF01可呈锥形。位在所述保护层501与阻障层405之间的所述界面IF03可大致呈垂直。
应当理解,“正在形成(forming)”、“已经形成(formed)”以及“形成(form)”的术语,可表示并包括任何产生(creating)、构建(building)、图案化(patterning)、植入(implanting)或沉积(depositing)一元件(element)、一掺杂物(dopant)或一材料的方法。形成方法的例子可包括原子层沉积(atomic layer deposition)、化学气相沉积(chemicalvapor deposition)、物理气相沉积(physical vapor deposition)、喷溅(sputtering)、旋转涂布(spin coating)、扩散(diffusing)、沉积(depositing)、生长(growing)、植入(implantation)、微影(photolithography)、干蚀刻以及湿蚀刻,但并不以此为限。
图7为依据本公开一实施例中一种半导体元件1A的制备方法10的流程示意图。图8到图21为依据本公开一实施例中制备该半导体元件1A的一流程的剖视示意图。
请参考图7到图10,在步骤S11,一第二晶粒200可接合到一第一晶粒100上。
请参考图8及图9,可分开提供一第一晶粒100与一第二晶粒200。第一晶粒100可包括一第一基底101、一第一介电层103、一第一钝化层105、多个第一装置元件107、一第一导电特征109以及多个第一虚拟导电特征111。第一介电层103可形成在第一基底101上。所述第一装置元件107与第一导电特征109可形成在第一介电层103中。第一钝化层105可形成在所述第一装置元件107上。所述第一虚拟导电特征111可形成在第一钝化层105中。第二晶粒200可具有类似于第一晶粒100的结构,但是以上下颠倒的方式设置。第二晶粒200可经由一接合制程而接合到第一晶粒100上。接合制程可包括一热处理,执行热处理以达到在第二晶粒200与第一晶粒100的所述元件之间的一混合接合(hybrid bonding)。混合接合可包括一介电质与介电质(dielectric-to-dielectric)接合以及金属与金属(metal-to-metal)接合。介电质与介电质接合可源自于第二晶粒200的一第二钝化层205与第一晶粒100的第一钝化层105之间的接合。金属与金属接合可源自于第一晶粒100的所述第一虚拟导电特征111与第二晶粒200的所述第二虚拟导电特征211之间的接合。接合制程的一温度可介于大约300℃到大约450℃之间。
请参考图10,一薄化制程可执行在第二晶粒200的一第二基底201上,薄化制程是使用一蚀刻制程、一化学研磨制程或一抛光制程,以缩减第二基底201的一厚度。
请参考图7以及图11,在步骤S13,一第一遮罩层301可形成在第二晶粒200上。
请参考图11,举例来说,第一遮罩层301可由下列材料所制:氧化硅、氮化硅、氮氧化硅、氧化氮化硅或其他适合的材料。
请参考图7及图12,在步骤S15,一第一开口601是形成来沿着第一遮罩层301以及第二晶粒200,并延伸到第一晶粒100。
请参考图12,第一开口601可通过执行一微影制程以及多个蚀刻制程以依序移除第一遮罩层301、第二晶粒200、第一钝化层105以及第一介电层103所形成。第一导电特征109可经由第一开口601而暴露。
请参考图7及图13,在步骤S17,可执行一蚀刻制程,以扩展在第一遮罩层301中的第一开口601。
请参考图13,第一遮罩层301对第二晶粒的第二基底201的一蚀刻率可介于大约100:1到1.05:1之间。在一些实施例中,蚀刻制程可为一湿蚀刻制程,其是使用一湿蚀刻溶液(wet etch solution)。湿蚀刻溶液可为一氢氟酸(hydrofluoride)溶液,其是具有6:1的缓冲氧化物蚀刻剂(buffer oxide etchant),且包含7%质量百分比(w/w)的氢氟酸(hydrofluoric acid)、34%质量百分比(w/w)的氟化铵(ammonium fluoride)以及59%质量百分比(w/w)的水。在一些实施例中,蚀刻制程可为一干蚀刻制程,其是使用气体,是选自由二氟甲烷(CH2F2)、三氯甲烷(CHF3)、八氟环丁烷(C4F8)所组成的群组。在蚀刻制程之后,在第一遮罩层301中的第一开口301的宽度可以加宽,在第二晶粒200或第一晶粒100中的第一开口601的宽度可以不变。所以,在蚀刻制程之后,在第一遮罩层301中的第一开口601的所述侧壁可呈锥形。在第一遮罩层301中的加宽的第一开口601可促进所述保护层501的形成,其将于后叙述。
请参考图7、图14以及图15,在步骤S19,多个绝缘层403可形成在第一开口601中。
请参考图14,一绝缘层403可沉积在第一开口601中,以及在第一遮罩层301的上表面301TS上。绝缘层403形成在第一导电特征109上的部分可表示成下区段403B。绝缘层403形成在第一遮罩层301的下表面301BS下方与第一开口601的各侧壁上的部份,是可表示成所述侧区段403S。绝缘层403形成在第一遮罩层301的下表面301BS上方与在第一遮罩层301的上表面301TS下方的部分,可表示成上区段403T。绝缘层403形成在第一遮罩层301的上表面301TS上的部分,可表示成覆盖区段403C。
请参考图15,可执行一猛击蚀刻(punch etch)制程以移除下区段403B、所述覆盖区段403C以及所述上区段403T。在猛击蚀刻制程之后,绝缘层403可分隔成多个部分。所述绝缘层403的最高点403TP可位在一垂直位面,该垂直位面齐平于第一遮罩层301的下表面301BS。猛击蚀刻制程的所述绝缘层403的蚀刻率,可较快于猛击蚀刻制程的第一遮罩层301的蚀刻率,以避免硅/硬遮罩层界面损伤。
在一些实施例中,猛击蚀刻制程可过度凹陷绝缘层403。所述绝缘层403的最高点403TP可位在一垂直位面,该垂直位面位在第一遮罩层301的下表面301BS下方。在此情况下,在接下来一导电填充层401的形成期间,可能会发生一金属对硅的泄漏。
请参考图7及图16,在步骤S21,可形成多个保护层501以覆盖所述绝缘层403的上部。
请参考图16,所述保护层501可通过一沉积制程所形成,沉积制程是例如一原子层沉积法,其是精确控制原子层沉积法的一第一前驱物(first precursor)的数量。举例来说,所述保护层501可由下列材料所制:氧化铝、氧化铪、氧化锆、氧化钛、氮化钛、氮化钨、氮化硅或氧化硅。
在一些实施例中,当所述保护层501由氧化铝所制时,原子层沉积法的第一前驱物可为三甲基铝(trimethylaluminum),且原子层沉积法的一第二前驱物可为水或臭氧(ozone)。
在一些实施例中,当所述保护层501由氧化铪所制时,原子层沉积法的第一前驱物可为四氯化铪(hafnium tetrachloride)、三级丁氧化铪(hafnium tert-butoxide)、二甲苯胺化铪(hafnium dimethylamide)、乙基甲基酰胺化铪(hafnium ethylmethylamide)、乙胺基化铪(hafnium diethylamide)或甲氧基叔丁醇化铪(hafnium methoxy-t-butoxide),而原子层沉积法的第二前驱物可为水或臭氧。
在一些实施例中,当所述保护层501由氧化锆所制时,原子层沉积法的第一前驱物可为四氯化锆(zirconium tetrachloride),且原子层沉积法的第二前驱物可为水或臭氧。
在一些实施例中,当所述保护层501由氧化钛所制时,原子层沉积法的第一前驱物可为四氯化钛(titanium tetrachloride)、钛酸四乙酯(tetraethyl titanate)或异丙醇钛(Titanium isopropoxide),且原子层沉积法的第二前驱物可为水或臭氧。
在一些实施例中,当所述保护层501由氮化钛所制时,原子层沉积法的第一前驱物可为四氯化钛或氨水。
在一些实施例中,当所述保护层501由氮化钨所制时,原子层沉积法的第一前驱物可为六氟化钨(tungsten hexafluoride)或氨水。
在一些实施例中,当所述保护层501由氮化硅所制时,原子层沉积法的第一前驱物可为硅烯(silylene)、氯(chlorine)、氨水及/或四氢化二氮(dinitrogen tetrahydride)。
在一些实施例中,当所述保护层501由氧化硅所制时,原子层沉积法的第一前驱物可为四氯化硅(silicon tetraisocyanate)或CH3OSi(NCO)3,且原子层沉积法的第二前驱物可为氢或臭氧。
由于在第一遮罩层301中的第一开口601的各锥形侧壁,所以所述保护层501的各侧壁501S可大致呈垂直。在接下来的半导体制程期间,所述保护层501可提供额外的保护给第一遮罩层301以及第二晶粒200。因此,可避免在导电填充层401形成时的金属对硅的泄漏。因此,可改善半导体元件1A的效能/良率。
请参考图7及图17到图21,在步骤S23,一阻障层405、一粘着层407、一晶种层409以及一导电填充层401可形成在第一开口601中。
请参考图17,阻障层405可共形地形成在所述保护层501上以及在第一开口601中。阻障层405可覆盖所述保护层501、所述绝缘层403以及第一导电特征109的上表面。
请参考图18到图19,粘着层407可共形地形成在阻障层405上。晶种层409可共形地形成在粘着层407上。
请参考图20,一层第一导电材料603可沉积在如图19所述的中间半导体元件上,并完全填满第一开口601。该层第一导电材料603可通过原子层沉积、化学气相沉积或其他共形的沉积法进行沉积。由于所述保护层501的存在,可降低在第一开口601的各侧壁上的第一导电材料603的沉积率。因此,在第一开口601的各侧壁上的第一导电材料603的沉积率以及在第一开口601的下表面上的第一导电材料603的沉积率可变得相互接近。因此,可填满第一开口601,而无须形成在邻近第一开口601的下表面处的任何孔洞(void)。可改善半导体元件1A的良率。
请参考图21,可执行一平坦化制程,例如化学机械研磨,直到第一遮罩层301的上表面301TS暴露为止,以移除多余材料,提供一大致平坦表面给接下来的处理步骤,且同时形成导电填充层401在第一开口601中。
图22到图24为依据本公开一实施例中制备一半导体元件1B的一流程的剖视示意图。
请参考图22,可制造如图14所述的一中间半导体元件。所述保护层501可形成在绝缘层403上,而无须先前执行一猛击蚀刻制程在绝缘层403上。意即,所述保护层501可形成来覆盖所述覆盖区段403C、所述上区段403T以及所述侧区段403S的上部。
请参考图23,在形成所述保护层501之后,一猛击蚀刻制程可执行在如图22所述的中间半导体元件上。可移除下区段403B。由于所述保护层501的存在,所以可避免在猛击蚀刻制程期间的绝缘层403的过度凹陷以及在形成导电填充层401期间的金属对硅的泄漏。请参考图24,其他元件是可以类似于如图17到图21所述的程序所形成。
图25到图28为依据本公开一实施例中制备一半导体元件1C的一流程的剖视示意图。
请参考图25,可制造如图12所述的一中间半导体元件。绝缘层403可形成在第一开口601中,而无须先前扩展在第一遮罩层301中的第一开口601。第一开口601的整个侧壁可大致为垂直。
请参考图26,一猛击蚀刻制程可以类似于如图15所示的一程序执行。请参考图27,所述保护层501可以类似于如图16所述的一程序所形成,以覆盖所述绝缘层403的上部。请参考图28,其他元件是可以类似于如图17到图21所述的程序所形成。
图29到图31为依据本公开一实施例中制备一半导体元件1F的一流程的剖视示意图。
请参考图29,可提供一第一晶粒100。第一晶粒100可包括一第一基底101、一第一介电层103、一第一钝化层105、多个第一装置元件107以及一第一导电特征109,第一介电层103形成在第一基底101上,第一钝化层105形成在第一介电层103上,所述第一装置元件107形成在第一介电层103中,第一导电特征109形成在第一介电层103中。
请参考图30,第一晶粒100可以一上下颠倒的方式置放。第一基底101的厚度可通过一蚀刻制程、一化学研磨制程或一抛光制程进行薄化。一第一遮罩层301以及一第一开口601可以类似于如图11及图12所述的一程序所形成。请参考图31,其他元件是可以类似于如图13到图21所述的程序所形成。
本公开的一实施例提供一种半导体元件,包括一第一晶粒;一第一导电特征,位在该第一晶粒中;一第二晶粒,位在该第一晶粒上;一第一遮罩层,位在该第二晶粒上;一导电填充层,位在沿着该第一遮罩层以及该第二晶粒处,延伸到该第一晶粒并接触该第一导电特征;多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第二晶粒之间;以及多个保护层,位在该导电填充层与该第一遮罩层之间,并覆盖所述绝缘层的上部。
本公开的另一实施例提供一种半导体元件,包括一第一晶粒;一第一导电特征,位在该第一晶粒中;一第一遮罩层,位在该第一晶粒上;一导电填充层,位在沿着该第一遮罩层处,延伸到该第一晶粒并接触该第一导电特征;多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第一遮罩层之间;以及多个保护层,位在该导电填充层与所述绝缘层之间;其中所述保护层的最低点是位在一垂直位面,该垂直位面是较低于在该第一遮罩层的一下表面的一垂直位面。
本公开的另一实施例提供一种半导体元件的制备方法,包括执行一接合制程以接合一第二晶粒到一第一晶粒上;形成一第一遮罩层在该第二晶粒上;形成一第一开口以穿过该第一遮罩层以及该第二晶粒,并延伸到该第一晶粒;形成多个绝缘层在该第一开口的多个侧壁上;形成多个保护层以覆盖所述绝缘层的上部;以及形成一导电填充层在该第一开口中。
由于本公开该半导体元件的设计,所述保护层501可提供额外的保护,以降低金属对硅的泄漏。此外,由于所述保护层501的几何形状,导电填充层401的形成是无须任何孔洞(void)。总而言之,其是可改善半导体元件1A的制造良率。
虽然已详述本公开及其优点,然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如,可用不同的方法实施上述的许多制程,并且以其他制程或其组合替代上述的许多制程。
再者,本申请案的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的揭示内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此,此等制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请案的权利要求内。
Claims (20)
1.一种半导体元件,包括:
一第一晶粒;
一第一导电特征,位在该第一晶粒中;
一第二晶粒,位在该第一晶粒上;
一第一遮罩层,位在该第二晶粒上;
一导电填充层,位在沿着该第一遮罩层以及该第二晶粒处,延伸到该第一晶粒并接触该第一导电特征;
多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第二晶粒之间;以及
多个保护层,位在该导电填充层与该第一遮罩层之间,并覆盖所述绝缘层的上部。
2.如权利要求1所述的半导体元件,其中,所述绝缘层的最高点位在一垂直位面,是齐平于该第一遮罩层的一下表面的一垂直位面。
3.如权利要求2所述的半导体元件,其中,在该第一遮罩层与所述保护层之间的多个界面是呈锥形。
4.如权利要求3所述的半导体元件,其中,在该第一遮罩层的一上表面与位在该第一遮罩层与所述保护层之间的所述界面之间的一角度,是介于大约120度到大约135度之间。
5.如权利要求4所述的半导体元件,其中,位在所述保护层与该导电填充层之间的多个界面是大致呈垂直。
6.如权利要求5所述的半导体元件,其中,该导电填充层是由多晶硅、钨、铜、纳米碳管或焊料合金所制,所述绝缘层是由氧化硅、氮化硅、氮氧化硅、四乙基硅酸盐、聚对二甲苯、环氧树脂或聚对二甲苯所制。
7.如权利要求6所述的半导体元件,还包括一阻障层,位在所述绝缘层与该导电填充层之间,其中该阻障层是由钽、氮化钽、钛、氮化钛、铼、硼化镍或氮化钽/钽双层所制。
8.如权利要求7所述的半导体元件,还包括一粘着层,位在该阻障层与该导电填充层之间,其中该粘着层由钛、钽、钛钨或氮化锰所制。
9.如权利要求8所述的半导体元件,还包括一晶种层,位在该粘着层与该导电填充层之间,其中该晶种层具有一厚度,是介于大约10nm到大约40nm之间。
10.如权利要求6所述的半导体元件,其中,该导电填充层的一宽度是介于大约1μm到大约22μm之间。
11.如权利要求6所述的半导体元件,其中,该导电填充层的一深度介于大约20μm到大约160μm之间。
12.如权利要求6所述的半导体元件,其中,该导电填充层的一深宽比是介于大约1:2到大约1:35之间。
13.如权利要求3所述的半导体元件,其中,位在该第一遮罩层与所述保护层之间的所述界面是大致呈垂直。
14.一种半导体元件,包括:
一第一晶粒;
一第一导电特征,位在该第一晶粒中;
一第一遮罩层,位在该第一晶粒上;
一导电填充层,位在沿着该第一遮罩层处,延伸到该第一晶粒并接触该第一导电特征;
多个绝缘层,位在该导电填充层与该第一晶粒之间,以及位在该导电填充层与该第一遮罩层之间;以及
多个保护层,位在该导电填充层与所述绝缘层之间;
其中所述保护层的最低点是位在一垂直位面,该垂直位面是较低于在该第一遮罩层的一下表面的一垂直位面。
15.如权利要求14所述的半导体元件,其中,在该第一遮罩层与所述绝缘层之间的多个界面是呈锥形。
16.如权利要求15所述的半导体元件,其中,位在该导电填充层与所述保护层之间的多个界面是大致呈垂直。
17.一种半导体元件的制备方法,包括:
执行一接合制程以接合一第二晶粒到一第一晶粒上;
形成一第一遮罩层在该第二晶粒上;
形成一第一开口以穿过该第一遮罩层以及该第二晶粒,并延伸到该第一晶粒;
形成多个绝缘层在该第一开口的多个侧壁上;
形成多个保护层以覆盖所述绝缘层的上部;以及
形成一导电填充层在该第一开口中。
18.如权利要求17所述的半导体元件的制备方法,还包括:在形成所述绝缘层在该第一开口的所述侧壁上的步骤之前,执行一蚀刻制程以扩展在该第一遮罩层中的该第一开口的一步骤。
19.如权利要求18所述的半导体元件的制备方法,其中,该蚀刻制程具有该第一遮罩层对该第二晶粒的一基底的一蚀刻率,其是介于大约100:1到大约1.05:1。
20.如权利要求19所述的半导体元件的制备方法,其中,所述保护层是由氧化铝、氧化铪、氧化锆、氧化钛、氮化钛、氮化钨、氮化硅或氧化硅所制。
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