TW202013610A - 直通矽穿孔上方的大型金屬襯墊 - Google Patents

直通矽穿孔上方的大型金屬襯墊 Download PDF

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TW202013610A
TW202013610A TW108120529A TW108120529A TW202013610A TW 202013610 A TW202013610 A TW 202013610A TW 108120529 A TW108120529 A TW 108120529A TW 108120529 A TW108120529 A TW 108120529A TW 202013610 A TW202013610 A TW 202013610A
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Taiwan
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substrate
bonding surface
contact pad
metal contact
bonding
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TW108120529A
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English (en)
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桂蓮 高
李奉燮
蓋烏斯 吉爾曼 方騰二世
賽普里恩 艾米卡 烏佐
蘿拉 威爾 麥卡雷米
貝高森 哈巴
拉杰詡 卡特卡
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美商英帆薩斯邦德科技有限公司
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Publication of TW202013610A publication Critical patent/TW202013610A/zh

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Abstract

包括製程步驟之代表性技術及裝置可用於降低接合的微電子基板由於接合界面處之金屬膨脹而造成分層之可能性。舉例而言，當接觸襯墊定位在一個或兩個基板中之TSV上方時可使用具有較大直徑或表面積（例如，對於此應用來說過大）之金屬襯墊。

Description

直通矽穿孔上方的大型金屬襯墊
以下描述關於積體電路（IC）。更特定而言，以下描述關於製造IC晶粒及晶圓。優先權要求及相關申請案之交叉參考
本申請案主張2019年6月12日申請之美國非臨時申請案第16/439,622號及2019年5月10日申請之美國臨時申請案第62/846,081號以及2018年6月13日申請之美國臨時申請案第62/684,505號的權益，前述申請案以全文引用之方式併入本文中。
微電子元件常常包含諸如矽或砷化鎵之半導體材料的薄平板，通常稱為半導體晶圓。晶圓可經形成為包括晶圓表面上及/或部分嵌入晶圓內之多個整合式晶片或晶粒。從晶圓分離之晶粒通常作為個別預封裝單元提供。在一些封裝設計中，晶粒經安裝至基板或晶片載體，該基板或晶片載體又安裝在諸如印刷電路板（printed circuit board；PCB）之電路面板上。舉例而言，許多晶粒經設置於適合於表面黏著的封裝中。
經封裝半導體晶粒亦可以「堆疊」配置來提供，例其中一個封裝設置於例如電路板或其他載體上，且另一封裝經安裝在第一封裝之頂部上。這些配置可允許多個不同晶粒或裝置經安裝於電路板上之單個覆蓋面積內，且可藉由在封裝之間設置較短互連來進一步促成高速操作。通常，此互連距離可僅略大於晶粒自身之厚度。對於將在晶粒封裝之堆疊內達成的互連，用於機械及電性連接之互連結構可設置於每一晶粒封裝（除了最高封裝以外）之兩側（例如，面）上。
另外，晶粒或晶圓可以三維配置堆疊作為各種微電子封裝方案之部分。此可包括在較大基底晶粒、裝置、晶圓、基板等等上堆疊一或多個晶粒、裝置及/或晶圓之層，以垂直或水平配置堆疊多個晶粒或晶圓，以及兩者之各種組合。
晶粒或晶圓可使用各種接合技術（包括直接介電質接合、非黏著性技術（諸如ZiBond®）或混合接合技術（諸如DBI®），二者均購自英帆薩斯邦德科技有限公司（Invensas Bonding Technologies, Inc.）（前Ziptronix公司）、Xperi公司）以堆疊配置來接合。接合包括當兩個製備表面接合在一起時在環境條件下發生的自發性過程（參見例如美國專利第6,864,585號及第7,485,968號，這些專利全文併入本文中）。
接合晶粒或晶圓之各別配合表面常常包括嵌入式導電互連結構（其可為金屬）等等。在一些實例中，接合表面經配置且對準使得來自各別表面之導電互連結構在接合期間結合。結合的互連結構在堆疊晶粒或晶圓之間形成連續導電互連（用於信號、功率等）。
對於實施堆疊式晶粒及晶圓配置可存在多種挑戰。當使用直接接合或混合接合技術來接合堆疊晶粒時，通常需要待接合之晶粒的表面極平坦、光滑且潔淨。舉例而言，這些表面一般應具有極低的表面拓樸變化（亦即，奈米尺度變化），使得這些表面可緊密配合以形成持久接合。
可形成雙側晶粒並準備進行堆疊及接合，其中晶粒之兩側將諸如利用多個晶粒對晶粒或晶粒對晶圓應用而接合至其他基板或晶粒。製備晶粒之兩側包括：對兩個表面進行表面處理以符合介電質粗糙度規格及金屬層（例如銅等）凹陷規格。舉例而言，接合表面處的導電互連結構可輕微凹陷，略低於接合表面之絕緣材料。可藉由裝置或應用之尺寸公差、規格或實體限制來判定低於接合表面之凹陷量。可使用化學機械拋光（chemical mechanical polishing；CMP）製程等等來製備混合表面以與另一晶粒、晶圓或其他基板接合。
一般而言，當含有介電層及一或多個金屬特徵（例如，嵌入式導電互連結構）之組合的直接接合表面接合在一起時，介電質表面首先在較低溫度下接合，且特徵之金屬隨後膨脹，因為金屬在退火期間經加熱。金屬之膨脹可使得來自兩個接合表面之金屬結合成統一的導電結構（金屬至金屬接合）。當基板及金屬在退火期間經加熱時，金屬之熱膨脹係數（coefficient of thermal expansion；CTE）相比於基板之CTE通常指示在特定溫度下（例如，~300C）金屬比基板膨脹要多得多。舉例而言，銅之CTE為16.7，而熔融矽石之CTE為0.55，且矽之CTE為2.56。
在一些狀況下，金屬相對於基板之較大膨脹對於堆疊晶粒或晶圓之直接接合可能成問題。若金屬襯墊定位在直通矽穿孔（through-silicon via；TSV）上方，則TSV金屬之膨脹可能會促使襯墊金屬之膨脹。在一些狀況下，組合的金屬膨脹可能會引起接合表面之局域化分層，因為膨脹的金屬會升至高於接合表面。舉例而言，膨脹金屬可將堆疊晶粒之接合的介電質表面分離。
揭示代表性技術及裝置，這些代表性技術及裝置包括：製備用於接合，諸如在無黏著劑之情況下用於直接接合之各種微電子裝置的製程步驟。在各種具體實例中，技術可用於降低歸因於金屬膨脹而造成分層之可能性，尤其當TSV或TSV上方之接合襯墊在一個或兩個裝置之接合表面處呈現待接合時。舉例而言，在一個具體實例中，可當接觸襯墊定位在TSV上方時使用具有較大直徑或表面積（例如，對於該應用來說過大）之金屬襯墊。舉例而言，可基於襯墊之材料、其厚度及在處理期間之預期凹陷選擇接觸襯墊，包括接觸襯墊之大小（例如，表面積、直徑等）或接觸襯墊之尺寸過大的量。
當使用諸如CMP之表面製備製程來製備基板之接合表面時，接合表面上之金屬襯墊可相對於介電質凹陷，此歸因於襯墊之材料相對於介電質之材料較軟。較大直徑金屬襯墊相較於較小直徑襯墊可在更大程度上凹陷（例如，較深凹陷）。在接觸襯墊定位在TSV上方之一具體實例中，較深凹陷可補償襯墊及TSV之組合的金屬膨脹，從而允許用於金屬膨脹的較多空間，此可縮減或消除當金屬膨脹時可能原本會發生之分層。
在各種實施中，實例製程包括將第一直通矽穿孔（TSV）嵌入至具有第一接合表面之第一基板中，其中第一TSV垂直於第一接合表面（亦即，在具有類似水平定向之接合表面的水平定向之基板內為垂直的）。該製程可包括基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）估計當加熱至預選溫度時第一TSV之材料將膨脹之量。該製程包括基於該估計或基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）在第一接合表面處形成第一金屬接觸襯墊且耦接至第一TSV。
第一金屬接觸襯墊安置於第一接合表面處（且可直接安置在第一TSV上方），並在第一接合表面下方部分地延伸至第一基板中，從而將第一金屬接觸襯墊電耦接至第一TSV。在具體實例中，該製程包括基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）平坦化第一接合表面以具有預定最大表面差異以用於直接接合，且平坦化第一金屬接觸襯墊以相對於第一接合表面具有預定凹陷。
在各個實例中，選擇或形成接觸襯墊包含選擇第一金屬接觸襯墊之直徑或表面積。舉例而言，第一金屬接觸襯墊可經選擇或形成為具有相比於類似應用的典型的直徑、表面積之過大的直徑、過大的表面積等等。在一具體實例中，該製程包括：基於該預測判定第一金屬接觸襯墊相對於第一接合表面之所要凹陷，以允許第一TSV之材料及第一金屬接觸襯墊之材料的膨脹；及選擇第一金屬接觸襯墊以具有當第一金屬接觸襯墊經平坦化時有可能產生所要凹陷之周邊形狀。此可包括預測由於該平坦化而有可能在第一金屬接觸襯墊之表面中發生之凹陷之量。在另一具體實例中，該製程包括基於該判定在第一金屬接觸襯墊之表面中形成所要凹陷（在接合之前）。
在各種具體實例中，該製程包括藉由選擇第一金屬接觸襯墊而縮減或消除接合的微電子構件之分層。在一替代實施中，該製程包括基於第一TSV之材料的體積及第一TSV之材料的熱膨脹係數（CTE）直接圍繞第一金屬接觸襯墊使第一接合表面之材料凹陷或侵蝕該材料以允許第一TSV之材料及第一金屬接觸襯墊之材料的膨脹。
另外或替代地，該第一基板之背側亦可經處理以用於接合。預選材料之一或多個絕緣層可沉積於該第一基板之背側上以在該第一基板之背側將直接接合時提供應力緩解。
此外，第一TSV以及第一基板內之其他TSV可用於導向或傳遞第一基板內之熱及/或將熱自第一基板導向或傳遞掉。在一些實施中，熱傳遞TSV可部分地或全部延伸通過第一基板之厚度，且可包括導熱障壁層。在此類實例中，替代地，傾向於隔熱的通常圍繞TSV使用之障壁層可由導熱層替換。在各種實施中，一些TSV可用於信號傳遞及熱傳遞。
在一具體實例中，一種微電子組件包含第一基板，該第一基板包括具有平面化表面形貌之第一接合表面，該平面化表面形貌具有第一預定的最大表面差異。第一直通矽穿孔（TSV）經嵌入至第一基板中，且第一金屬接觸襯墊安置於第一接合表面處並電耦接至第一TSV。舉例而言，第一接觸墊可安置於第一TSV上方。可基於當加熱至預選溫度時第一TSV之材料將膨脹之量之估計及/或基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）選擇或形成第一金屬接觸襯墊。預定凹陷安置於第一金屬接觸襯墊之表面中，具有等於或大於當加熱至預選溫度時第一TSV之材料之膨脹的量及第一金屬接觸襯墊之材料之膨脹的量之體積。
在一實施中，第一金屬接觸襯墊定位在第一TSV上方，且第一金屬接觸襯墊相比於用於類似應用之典型襯墊具有過大的直徑或過大的表面積。
參考電性構件及電子構件及變化之載體論述各種實施及配置。雖然提及了具體構件（亦即，晶粒、晶圓、積體電路（IC）晶片晶粒、基板等），但此不意欲為限制性的，且為了易於論述且方便說明。參考晶圓、晶粒、基板等等論述之技術及裝置適用於任何類型或數目之電性構件、電路（例如，積體電路（IC）、混合電路、ASIC、記憶體裝置、處理器等）、構件群組、封裝式構件、結構（例如，晶圓、面板、板、PCB等）等等，其可經耦接以彼此介接，與外部電路、系統、載體等等介接。這些不同構件、電路、群組、封裝、結構等等中之每一者可一般被稱作「微電子構件」。為簡單起見，除非另外指定，否則接合至另一構件之構件將在本文中被稱作「晶粒」。
此概述並不意欲給出完整描述。在下文使用複數個實例來更詳細地解釋實施。儘管在此處且在下文論述各種實施及實例，但其他實施及實例可藉由組合個別實施及實例之特徵及元件來成為可能。
概述
參看圖1A（展示橫截面剖面圖）及圖1B（展示俯視圖），圖案化金屬及氧化物層經頻繁設置於晶粒、晶圓或其他基板（下文中「晶粒102」）上作為混合接合或DBI®表層。代表性裝置晶粒102可使用各種技術形成，以包括基底基板104及一或多個絕緣或介電層106。基底基板104可包含矽、鍺、玻璃、石英、介電質表面、直接或間接能隙半導體材料或層或另一合適材料。絕緣層106沉積或形成於基板104上方，且可包含無機介電材料層，諸如氧化物、氮化物、氮氧化物、碳氧化物、碳化物、碳氮化物、金剛石、類金剛石材料、玻璃、陶瓷、玻璃陶瓷等等。
裝置晶圓102之接合表面108可包括導電特徵110（諸如跡線、襯墊及互連結構），其嵌入於絕緣層106中且經配置以使得來自相對裝置之各別接合表面108之導電特徵110可視需要在接合期間配合並接合。接合的導電特徵110可形成堆疊裝置之間的連續導電互連（用於信號、功率等）。
鑲嵌製程（等等）可用以在絕緣層106中形成嵌入式導電特徵110。導電特徵110可包含金屬（例如，銅等）或其他導電材料或材料之組合，且包括結構、跡線、襯墊、圖案等等。在一些實例中，障壁層可在沉積導電特徵110之材料之前經沉積在用於導電特徵110之空腔中，使得障壁層安置於導電特徵110與絕緣層106之間。該障壁層可包含例如鉭或另一導電材料，以防止或縮減導電特徵110之材料擴散至絕緣層106中。在形成導電特徵110之後，裝置晶圓102（包括絕緣層106及導電特徵110）之經暴露表面可經平坦化（例如，經由CMP）以形成平坦的接合表面108。
形成接合表面108包括修整表面108以符合介電質粗糙度規格及金屬層（例如銅等）凹陷規格，以製備用於直接接合之表面108。換言之，接合表面108經形成為儘可能平坦及光滑的，且具有極小表面拓樸變化。各種習知製程（諸如化學機械拋光（CMP）、乾式或濕式蝕刻等）可用於實現低表面粗糙度。此製程提供產生可靠接合之平坦且光滑的表面108。
在雙側晶粒102之狀況下，具有經製備接合表面108的圖案化金屬及絕緣層106可設置於晶粒102之兩側上。絕緣層106典型地為高度平坦的（通常為nm級粗糙度），其中金屬層（例如，嵌入式導電特徵）在接合表面108處或正好凹陷至該接合表面下方。在絕緣層106之表面108下方凹陷的量典型地藉由尺寸公差、規格或實體限制判定。常常使用化學機械拋光（CMP）步驟及/或其他製備步驟來製備接合表面108以便與另一晶粒、晶圓或其他基板直接接合。
一些嵌入式導電特徵或互連結構可包含在經製備表面108下方部分地延伸至介電質基板106中之金屬襯墊110或導電跡線112。舉例而言，一些圖案化金屬（例如，銅）特徵110或112可為約0.5至2微米厚。這些特徵110或112之金屬可在金屬在退火期間經加熱時膨脹。其他導電互連結構可包含金屬（例如，銅）直通矽穿孔（TSV）114等等，其垂直於接合表面108延伸，部分或充分地延伸通過基板102並且包括較大數量的金屬。舉例而言，TSV 114可取決於基板102之厚度而延伸約50微米。TSV 114之金屬亦可在經加熱時膨脹。襯墊110及/或跡線112可或可不電耦接至TSV 114，如圖1A中所展示。
參看圖2，晶粒102可直接接合，例如不黏著至具有金屬襯墊110、跡線112及/或TSV 114之其他晶粒102。若金屬襯墊110定位在TSV 114上方（電耦接至TSV 114），則TSV 114金屬之膨脹可促使襯墊110金屬之膨脹。在一些狀況下，組合的金屬膨脹可引起接合表面在TSV 114（或TSV 114/襯墊110組合）之位置處的局域化分層202，因為膨脹的金屬會上升至高於接合表面108。舉例而言，膨脹金屬可將堆疊晶粒102之接合的介電質表面108分離。 例示性具體實例
參看圖3A、圖3B及圖4，在各種具體實例中，技術可用於降低由於金屬膨脹而造成分層之可能性。舉例而言，在一個具體實例中，具有較大直徑或表面積（例如，對於該應用尺寸過大）之金屬襯墊302當定位在TSV 114上方時可用於代替接觸襯墊110。舉例而言，襯墊302之直徑可大於晶粒102之表面108處之其他接觸襯墊110之直徑，使得襯墊302將比不定位在TSV 114上方之其他接觸襯墊110具有更深的凹陷以用於給定CMP製程。類似於接觸襯墊110，接觸襯墊302可嵌入於介電層106中，在接合表面106下方部分地延伸至介電層106中，並且電耦接至TSV 114。舉例而言，可基於襯墊302之材料、其厚度及在CMP處理期間之預期凹陷來選擇金屬襯墊302之尺寸過大的量。
如圖3A（展示橫截面剖面圖）及圖3B（展示俯視圖）中所展示，安置於TSV 114上方之襯墊302可比安置在晶粒102之接合表面108處之其他地方（例如，不安置於TSV 114上方）之其他襯墊110大出預選的量（就面積、直徑等而言）。在一具體實例中，藉由基於TSV 114之材料的體積及TSV 114之材料的熱膨脹係數（coefficient of thermal expansion；CTE）來估計在TSV 114之材料在加熱至預選溫度（~300°）時將膨脹之量及基於接觸襯墊302之材料之體積及接觸襯墊之材料之CTE來預測在接觸襯墊302之材料加熱至預選溫度時將膨脹之量選擇或形成襯墊302。
接觸襯墊302連同介電層106之接合表面108一起平坦化，包括基於估計及預測TSV 114材料及接觸襯墊302材料在預選溫度下之膨脹來使接觸襯墊302凹陷以具有相對於接合表面108之預定凹陷的深度（或量）。
參看圖4，在製備接合表面108（例如，藉由CMP）之後，晶粒102可直接接合，例如不黏著至具有金屬襯墊110及/或302、跡線112及/或TSV 114之其他晶粒102。當金屬襯墊302定位在TSV 114上方並且凹陷預定或可預測的量時，凹陷在不分層之情況下為材料膨脹提供空間。TSV 114材料及襯墊302材料會在經加熱退火期間膨脹。相對晶粒102之配合接觸襯墊302（或在一些實例中為302及110）接合以形成單一導電互連。然而，組合的金屬膨脹不會引起接合表面之分層，此係由於膨脹的金屬不超過接觸襯墊302（或在一些實例中為302及110）中之凹陷形成的體積。舉例而言，若凹陷的體積足夠，則膨脹金屬不會將堆疊晶粒102之接合的介電質表面108分離，如圖4中所展示。
參看圖5及圖6，說明TSV 114上方之接觸襯墊110及302之細節。展示晶粒102之一部分，首先接觸襯墊110在TSV 114上方（圖5）且接著接觸襯墊302在TSV 114上方（圖6）。當使用諸如CMP之表面製備製程來製備晶粒102之接合表面108時，接合表面108上之金屬襯墊110或302可傾向於相對於介電質106變得凹陷，此係由於接觸襯墊110或302（其可包含例如銅）相對於介電質106（其可包含例如氧化物）的柔軟度。
在各種具體實例中，直徑或表面積A2大於接觸襯墊110之較小直徑或表面積A1（圖5及圖6處展示，其中A2＞A1）之接觸襯墊302在類似CMP製程期間的凹陷程度「d2」（例如，較深凹陷）可大於較小直徑襯墊110之凹陷「d1」。較深凹陷「d2」可補償襯墊302及TSV 114之組合的金屬膨脹，從而允許用於金屬膨脹的較多空間，且該較深凹陷可縮減或消除分層。在一些具體實例中，接觸襯墊302可有意地凹陷至所要深度「d2」，且在其他具體實例中，可由於產生自藉由CMP（或其他處理）之表面108製備的可預測凹陷「d2」而基於襯墊302之大小（直徑及/或表面積）、材料組成等選擇接觸襯墊302。
在各種具體實例中，可基於以下各者預測金屬襯墊110或302之凹陷的量（例如，d1、d2等）：所使用之表面製備技術（例如，所使用之化學組合、拋光設備之速度等）、介電層106以及金屬襯墊110及302之材料、金屬襯墊110及302之間隔或密度，以及金屬襯墊110及302之大小（例如，面積或直徑）。在具體實例中，可基於TSV 114及金屬襯墊110或302組合之凹陷預測及預期的金屬膨脹來選擇金屬襯墊110及302之面積或直徑（例如，針對特定金屬厚度），以避免接合晶粒102的分層。舉例而言，可在TSV 114上方使用大小較大的襯墊302，且可在介電質106上方使用大小較小的襯墊110（以避免這些襯墊110之過多凹陷）。此技術可引起縮減或消除分層，以及引起接合表面108上之介電質106及金屬結構（110、302、112及/或114）之可靠機械耦接以及接合金屬結構（110、302、112及/或114）的可靠電性連續性。
在一個具體實例中，選擇性地蝕刻金屬襯墊110、302（經由酸性蝕刻、電漿氧化等）以提供所要凹陷深度（以容納預測金屬膨脹）。在另一具體實例中，襯墊110、302或對應的TSV 114可經選擇、形成或處理以具有不均勻的頂表面作為膨脹緩衝區。舉例而言，參看圖7，襯墊302（或在一些狀況下為TSV 114）之頂表面可形成或經選擇性地蝕刻為圓形、半球形、凸形、凹形、不規則或其他方式不平坦以允許用於材料膨脹之空間。
如在圖7之A處所展示，接觸襯墊302之頂表面或接合表面經選擇、形成或處理以具有不均勻的表面。如在B處所展示，在由於經加熱退火之材料膨脹之後，襯墊302接觸並接合。然而，在具有由襯墊302之不均勻的頂表面提供之用於膨脹之充足空間之情況下，材料不會超過所提供之空間，且因此不發生接合晶粒102之分層。
另外或替代地，如圖8中所展示，圍繞金屬襯墊110或302之介電質106可形成或經塑形以允許用於襯墊110或302（及TSV 114）之金屬膨脹的空間。在一個實例中，CMP製程可用於塑形金屬襯墊302周圍之介電質106之表面108，或在其他實例中，可使用其他製程，使得襯墊302周圍之介電質106包括為金屬膨脹提供空間之凹陷802或其他間隙。
在一具體實例中，當製備接合表面108時，介電質106可凹陷（例如，運用CMP）。在該具體實例中，金屬襯墊110或302及介電質106可同時凹陷（但以不同速率）。舉例而言，該製程可在使金屬襯墊110或302凹陷時在介電質106中的金屬襯墊110或302之邊緣周圍形成侵蝕802。
在各種具體實例中，襯墊110或302及/或TSV 114包含銅、銅合金等等。在另一具體實例中，襯墊110或302及/或TSV 114之材料可變化以控制金屬膨脹及可能的所得分層。舉例而言，在一些具體實例中，襯墊110或302及/或TSV 114可包含可能具有較低CTE之不同導電材料。在一些具體實例中，TSV 114可包含與接觸襯墊110或302不同之導電材料（具有較低CTE）。舉例而言，TSV 114可包含鎢、合金等等。
在其他具體實例中，TSV 114之材料的體積可變化以控制金屬膨脹及產生分層之可能性。舉例而言，在一些具體實例中，具有預選材料體積（例如，較小材料體積）之TSV 114可在設計規格允許時用於控制分層。TSV 114之體積之預選可基於（適當時，TSV 114及接觸襯墊110或302之）預測之材料膨脹。
在一替代具體實例中，金屬接觸襯墊110或302可自TSV 114偏移或重新定位，而非直接定位在TSV 114上方。舉例而言，金屬襯墊110或302可定位成使得其未直接在TSV 114上方，並且視需要藉由金屬跡線112耦接至TSV 114。若接觸襯墊110或302自TSV 114偏移，則可形成空腔以允許TSV 114在z方向上膨脹而不影響接合界面。可使得該空腔敞開或該空腔可填充有諸如柔性材料之材料。
替代地，TSV 114之頂表面可經配置以在接合表面108處暴露並且用作接觸襯墊。這些配置可避免組合金屬襯墊110或302之膨脹與TSV 114之膨脹，且因此最小化或消除分層。 在另一具體實例中，TSV 114可形成使得TSV 114部分地（而非完全）延伸通過基板102之厚度，在接合表面108下方終止。間隙或凹陷可設置在TSV 114上方之接合表面108中，以允許用於TSV 114之金屬膨脹的空間，且不引起分層。舉例而言，該間隙可藉由蝕刻介電層106形成。該間隙可或可不暴露TSV 114。可使用TSV 114之膨脹之預測基於TSV 114之特定金屬的體積將該間隙調諧例如至TSV 114之體積。 額外具體實例
圖9至圖13說明根據各種具體實例之背側晶粒102處理之實例。在一些實施中，在晶粒102經堆疊且在無黏著劑之情況下直接接合的情況下，當晶粒102之背側902經製備用於直接接合時，該背側902可接收與頂側接合表面108不同之製備。代替在晶粒102之背側902上形成介電層106，背側902可以不同方式製備以縮減製程步驟、縮減製造成本或用於其他原因。
在一個實施中，背側902經製備使得TSV 114之後端被暴露，以作為接合至導電襯墊、互連件或其他導電接合表面之接觸表面使用。該製備可包括在內襯/障壁層904完好之情況下薄化並選擇性地蝕刻基底基板104以暴露TSV 114、沉積一或多個絕緣材料層，以及平坦化（例如經由CMP）背側902以顯露TSV 114。然而，在一些狀況下，TSV 114之材料在經加熱退火期間之膨脹可使得絕緣材料及/或基板104變形並上升至高於平坦化表面。
在一具體實例中，如圖9至圖13中所展示，一或多個材料層可沉積於背側902上以覆蓋突起的區域，因此新表面可經重新平坦化以用於良好的介電質至介電質接合。多層結構之另一重要功能在於平衡晶粒102之前側與背側之間的應力以最小化接合之前的晶粒翹曲。經平衡的晶粒102更易於接合且較不易於接合空隙。添加的材料層可經平坦化並以其他方式製備成晶粒102之背側902上之接合表面。
如圖9所展示，TSV 114橫向於晶粒102之接合表面108安置於晶粒102內。TSV 114可在選擇性蝕刻基底基板104之後延伸超出基底基板104之表面。擴散障壁及氧化物內襯904環繞TSV 114以防止TSV 114之金屬（例如，銅）擴散至基底基板104之材料（例如，矽）中。在一具體實例中，如圖9所展示，另一擴散障壁906沉積於晶粒102之背側之表面上。在一實例中，擴散障壁906包含介電質，諸如氮化物等等。
在各種具體實例中，可具有不同殘餘應力特性之一或多個無機介電層接著經沉積至晶粒102之背側902上以使得能夠適當顯露TSV 114並且平衡晶粒102之裝置側（前側）上的應力以在單體化（singulation）之後最小化晶粒翹曲。舉例而言，包含諸如氧化物之第一低溫介電質之第一層908可沉積於包括擴散層906之背側902上方。
在一些具體實例中，包含諸如第二氧化物之第二低溫介電質之第二層910可沉積於包括第一層908之背側902上方。第二氧化物層910可具有與第一層908類似或不同的殘餘應力特性（例如，第一層908可具有壓縮性且第二層910可具有拉伸性，或反之亦然，或層908及910兩者均可具有具備類似或不同值之壓縮性或拉伸性）。在各種實施中，第一層908及第二910層包含類似或相同材料（呈不同厚度）。在其他實施中，第一層908及第二910層包含不同材料。在替代實施中，額外介電層亦可沉積於第一層908及第二層910上方。
如圖10所展示，背側902經平坦化（例如經由CMP），包括一或多個應力層908及910經平坦化以形成平坦、平滑的接合表面用於直接接合。可使第二層910之一部分在背側902上以輔助減輕損壞，諸如氧化物環效應。另外，第二層910之剩餘部分可基於第二層910之殘餘應力特性來輔助翹曲控制。
在另一具體實例中，如圖11至圖12中所展示，接觸襯墊1204可耦接至晶粒102之背側902上之TSV 114。如圖11所展示，在沉積在一些實施中亦包含接合層之第一介電層（例如低溫氧化物應力層908）之後，TSV 114藉由諸如CMP之製程經充分暴露並平坦化。第二介電層910（其可包含氧化物）可沉積於第一層908上方並經平坦化。兩個氧化物層（908及910）之間無需障壁或黏著層。在平坦化之後，背側902經圖案化並敞開（例如，蝕刻等）以用於沉積導電襯墊。如圖11中所展示，氧化物層908及910中之開口1102之直徑可大於TSV 114之直徑。
在一具體實例中，用於接觸襯墊1204之開口1102延伸通過第二層910並部分地（10 nm至1000 nm）延伸通過第一層908。障壁/黏著層1202（包含鈦/氮化鈦、鉭/氮化鉭等）可沉積至開口1102中（且可覆蓋開口1102之整個表面），如圖12所展示。銅（或類似物）沉積/電鍍（例如，鑲嵌製程）填充開口1102，該開口經平坦化（例如經由CMP）以移除多餘銅並將所得接觸襯墊1204凹陷設定至指定深度。背側902表面經製備以用於在此時接合。
在一替代具體實例中，雙鑲嵌製程可用於形成接觸襯墊1204，如圖13中所展示。在具體實例中，在將第二介電層910（其可包含氧化物）沉積至第一層908（不具有障壁或黏著層）上之後，所得背側902表面經圖案化兩次以在雙鑲嵌製程中形成用於接觸襯墊1204之唯一開口1302。首先，直徑小於TSV 114之直徑的小開口經部分地蝕刻穿過層908，接著小開口上方之大開口（直徑大於TSV 114之直徑）經圖案化並蝕刻，從而使得小開口延伸至TSV 114且大開口部分地延伸通過層910。舉例而言，在一些狀況下，設計規則指示穿孔層之存在。
第二介電層910（頂部層）之厚度及接觸襯墊1204之厚度可經調整以最小化薄晶粒翹曲，並達成所要退火溫度。在其他具體實例中，替代技術可用於縮減或消除由於金屬特徵膨脹造成之分層，且保持在本發明之範圍內。
圖14至圖16展示關於圖9至圖13形成之晶粒102（及類似結構）之實例堆疊配置，其具有前側108及背側902互連性。舉例而言，在圖14，展示實例「前側至背側」晶粒102堆疊配置。此配置將第一晶粒102之前側接合表面108接合至第二晶粒102之背側902接合表面，包括將第一晶粒102之接觸襯墊110或302接合至第二晶粒102之接觸襯墊1204。在如上文所論述之一實例中，第二晶粒102之接觸襯墊1204在接合界面1402下方穿入至第二晶粒102之第二介電層910及第一介電層908中。
在圖15，展示實例「背側對背側」晶粒102堆疊配置。此配置將第一晶粒102之背側902接合表面接合至第二晶粒102之背側902接合表面，包括將第一晶粒102之接觸襯墊1204接合至第二晶粒102之接觸襯墊1204。在如上文所論述之一實例中，第一及第二晶粒102之接觸襯墊1204在接合界面1402下方穿入至第一及第二晶粒102之第二介電層910及第一介電層908中。
在圖16，展示實例「前側對前側」晶粒102堆疊配置。此配置在接合界面1402處將第一晶粒102之前側接合表面108接合至第二晶粒102之前側接合表面108，包括將第一晶粒102之接觸襯墊110或302接合至第二晶粒102之接觸襯墊110或302。在所展示之實例中，接觸襯墊110或302電耦接至各別晶粒102之TSV 114。
在各種具體實例中，如圖17所說明，一組堆疊晶粒102之TSV 114中之一或多者除了電信號之外或代替電信號亦可用於傳導熱量。舉例而言，在一些狀況下，將散熱片（或其他熱傳遞裝置）附接至一組堆疊晶粒102中之晶粒102以減輕由晶粒102生成的熱量可為不可行的或不可能的。在此類狀況下，可尋找其他技術以視需要傳遞熱量。
在具體實例中，如圖17所展示，TSV 114（包括部分地或完全延伸通過晶粒102之TSV）之各種組態可用於將熱量自晶粒102傳導掉（或自晶粒102之熱生成部分傳導掉）。一個晶粒102之TSV 114接合第二晶粒102之TSV 114、接觸襯墊110及302、跡線112等等一起使用以完成自一個晶粒102至另一晶粒102之熱傳遞等等。第一晶粒102之TSV 114可直接接合（例如，DBI）至第二晶粒102之TSV 114、接觸襯墊110及302、跡線112等等，以用於高效能導熱性。
在一實施中，TSV 114、接觸襯墊110及302、跡線112等等中之一些為電性浮置或「虛設」結構，其可用於熱傳遞。這些結構可視需要將熱量自高功率晶粒102傳導離開至另一晶粒102或基板。虛設接觸襯墊110或302可耦接至最末穿孔或中間穿孔熱TSV 114以用於熱傳導。
在具體實例中，環繞TSV 114且可限熱的或為熱障壁之擴散障壁/氧化物內襯層904可由具有一定導熱性之不同材料的擴散障壁/氧化物內襯（諸如金屬或合金障壁等等）替換。 實例製程
圖18說明代表性製程1800，其用於製備各種微電子構件（諸如晶粒102）同時降低或消除由於嵌入式結構在接合表面處之金屬膨脹造成的分層之可能性，這些微電子構件用於接合，諸如用於在不具有黏著劑之情況下直接接合。舉例而言，接合表面處之直通矽穿孔（TSV）可引起分層，尤其當耦接至接觸襯墊時，此係因為TSV及接觸襯墊之材料在經加熱退火期間膨脹。該製程參考圖1至圖18。
描述製程之次序並不意欲被解釋為限制，且可按任何次序組合製程中之任何數目個所描述製程區塊以實施製程或替代性製程。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自製程刪除個別區塊。此外，在不脫離本文中所描述之主題之範圍的情況下，製程可以任何合適之硬體、軟體、韌體或其組合實施。在替代實施中，其他技術可以各種組合包括於製程中，且保持在本發明之範圍內。
在一實施中，晶粒、晶圓或其他基板（「基板」）使用各種技術形成以包括基底基板及一或多個介電層。在該實施中，在區塊1802處，製程1800包括將第一直通矽穿孔（TSV）（諸如TSV 114）嵌入至具有第一接合表面（諸如接合表面108）之第一基板（諸如晶粒102）中，第一TSV垂直於第一接合表面。
在實施中，在區塊1804處，該製程包括基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）在第一接合表面處形成第一金屬接觸襯墊（諸如接觸襯墊302）且電耦接至第一TSV。在一具體實例中，第一金屬接觸襯墊在第一接合表面下方部分地延伸至第一基板中。
在區塊1806處，該製程包括基於第一TSV之材料之體積及第一TSV之材料之熱膨脹係數（CTE）平坦化第一接合表面以具有預定最大表面差異以用於直接接合，且平坦化第一金屬接觸襯墊以相對於第一接合表面具有預定凹陷。在一實施中，該製程包括基於第一金屬接觸襯墊之材料之體積及第一金屬接觸襯墊之材料之CTE預測第一金屬接觸襯墊之材料在加熱至預選溫度時將膨脹之量及基於該估計以及該預測判定第一金屬接觸襯墊之大小。在一個實施中，該製程包括選擇第一金屬接觸襯墊之直徑或表面積。
在一實施中，該製程包括將第一金屬接觸襯墊電耦接至第一TSV。
在一實施中，該製程包括：基於該估計及該預測判定第一金屬接觸襯墊相對於第一接合表面之所要凹陷，以允許第一TSV之材料及第一金屬接觸襯墊之材料的膨脹；及選擇第一金屬接觸襯墊以具有當第一金屬接觸襯墊經平坦化時有可能產生所要凹陷之周邊形狀。
在另一實施中，該製程包括基於該預測判定第一金屬接觸襯墊相對於第一接合表面之所要凹陷，以允許第一TSV之材料及第一金屬接觸襯墊之材料的膨脹；及在第一金屬接觸襯墊之表面中形成所要凹陷。
在另一實施中，該製程包括選擇第一金屬接觸襯墊以具有相比於類似應用的典型直徑或表面積的過大的直徑或過大的表面積。
在一另外實施中，該製程包括預測由於平坦化而有可能在第一金屬接觸襯墊之表面中發生的凹陷之量。
在另一實施中，該製程包括基於該估計直接圍繞第一金屬接觸襯墊使第一接合表面之材料凹陷或侵蝕該材料，以允許第一TSV之材料及第一金屬接觸襯墊之材料膨脹。
在一實施中，該製程包括藉由使第一金屬接觸襯墊相對於第一TSV之位置偏移使得第一金屬接觸襯墊不直接安置在第一TSV上方來縮減或消除接合的微電子構件之分層。在另一實施中，該製程包括在第一TSV上方之第一接合表面中形成凹陷，以允許第一TSV之材料的膨脹。在另一實施中，該製程包括基於該估計調諧第一接合表面中之凹陷之量。
在一實施中，該製程包括藉由將第一TSV延伸至第一接合表面及將第一TSV之頂表面用作第一接合表面處之接觸襯墊來縮減或消除接合的微電子構件之分層。
在各種具體實例中，相較於本文中所描述之製程步驟，可修改或消除一些製程步驟。
本文中所描述之技術、構件及裝置不限於圖1至圖18之說明，且可在不脫離本發明之範圍的情況下應用於包括其他電構件之其他設計、類型、配置及構造。在一些狀況下，額外或替代構件、技術、序列或製程可用於實施本文中所描述之技術。此外，構件及/或技術可以各種組合配置及/或組合，同時產生類似或大致相同之結果。 結論
儘管已以特定針對於結構特徵及/或方法動作之語言描述本發明之實施，但應理解，實施不一定限於所描述的特定特徵或動作。確切而言，將具體特徵及動作揭示為實施實例裝置及技術之代表性形式。
102:裝置晶粒/基板 104:基底基板 106:一或多個絕緣或介電層 108:接合表面 110:導電特徵 112:導電跡線 114:直通矽穿孔（TSV） 202:局域化分層 302:接觸襯墊 802:侵蝕 902:背側 904:內襯/障壁層 906:擴散層 908:第一層/低溫氧化物應力層 910:第二層/第二氧化物層 1102:開口 1202:障壁/黏著層 1204:接觸襯墊 1302:開口 1402:接合界面 1800:製程 1802:區塊 1804:區塊 1806:區塊 A1:直徑或表面積 A2:直徑或表面積 d1:凹陷 d2:凹陷
參看隨附圖式闡述詳細描述。在這些圖中，參考數字之最左側數位識別首次出現該參考數字之圖。在不同圖中使用相同參考數字指示類似或相同物件。
對此論述，在圖中所說明之裝置及系統展示為具有大量構件。如本文中所描述，裝置及/或系統之各種實施可包括更少構件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施可包括額外構件或所描述構件之各種組合，且保持在本發明之範圍內。
圖1A展示具有接合襯墊及TSV之實例基板的橫截面。
圖1B展示圖1A之實例基板的俯視圖。
圖2展示具有接合襯墊及TSV之兩個實例接合基板及實例所得分層之橫截面。
圖3A展示根據一具體實例之具有定位在TSV上方之較大接合襯墊之實例基板的橫截面。
圖3B展示根據一具體實例之圖3A之實例基板的俯視圖。
圖4展示根據一具體實例之具有定位在TSV上方之較大接合襯墊之兩個實例接合基板的橫截面。
圖5展示具有定位在TSV上方之接合襯墊之實例基板的橫截面，其說明接合襯墊之實例凹陷。
圖6展示根據一具體實例之具有定位在TSV上方之較大接合襯墊之實例基板的橫截面，其說明接合襯墊之實例凹陷。
圖7展示根據一具體實例之兩個實例接合基板的橫截面，該兩個實例接合基板具有接合襯墊，這些接合襯墊在退火前後具有非平坦接合表面。
圖8展示根據一具體實例之實例基板的橫截面，其中接合襯墊定位在TSV上方，且其中接合襯墊周圍存在介電質之侵蝕或凹陷。
圖9至圖13展示根據一具體實例之具有定位在TSV上方之接合襯墊之實例基板的橫截面，其說明基板之實例背側製程。
圖14展示根據一具體實例之具有TSV及接合襯墊之兩個前側背側接合之實例接合基板的橫截面。
圖15展示根據一具體實例之具有TSV及接合襯墊之兩個背側接合之實例接合基板的橫截面。
圖16展示根據一具體實例之具有TSV及接合襯墊之兩個前側接合之實例接合基板的橫截面。
圖17展示根據各種具體實例之用於晶粒之熱量管理的實例TSV之圖。
圖18為根據一具體實例之文本流程圖，其說明形成微電子組件以縮減或消除接合基板之分層的實例製程。
102:裝置晶粒/基板
104:基底基板
106:一或多個絕緣或介電層
108:接合表面
110:導電特徵
112:導電跡線
114:直通矽穿孔(TSV)

Claims (20)

  1. 一種形成微電子組件之方法，其包含： 在具有第一接合表面之第一基板中設置第一直通矽穿孔（TSV），該第一直通矽穿孔垂直於該第一接合表面； 形成在該第一接合表面處或自該第一接合表面稍微凹陷之第一金屬接觸襯墊，該第一金屬接觸襯墊電耦接至該第一直通矽穿孔，該第一金屬接觸襯墊在該第一接合表面下方部分地延伸至該第一基板中並在自該第一接合表面貫穿該第一基板之方向上與該第一直通矽穿孔對準；及 平坦化該第一接合表面以具有預定最大表面差異以用於直接接合且調整該第一金屬接觸襯墊相對於該第一接合表面之凹陷，以補償該直通矽穿孔及該第一金屬接觸襯墊相對於該第一接合表面之熱膨脹。
  2. 如請求項1所述之形成微電子組件之方法，其進一步包含形成在該第一接合表面處或稍微凹陷至該第一接合表面之第二金屬接觸襯墊，該第二金屬接觸襯墊不與該直通矽穿孔在自該第一表面貫穿該第一基板之方向上對準，其中該第一金屬接觸襯墊比該第二金屬接觸襯墊相對於該第一接合表面凹陷得多。
  3. 如請求項2所述之形成微電子組件之方法，其中該第一金屬接觸襯墊在該第一接合表面處之表面積大於該第二金屬接觸襯墊。
  4. 如請求項1所述之形成微電子組件之方法，其進一步包含自與該第一接合表面相對之表面暴露該第一直通矽穿孔。
  5. 如請求項1所述之形成微電子組件之方法，其進一步包含處理與該第一接合表面相對之該表面以提供第二接合表面。
  6. 如請求項1所述之形成微電子組件之方法，其進一步包含： 提供第二基板； 將該第一基板之該第一接合表面直接接合至該第二基板而無需中介黏著劑。
  7. 如請求項4所述之形成微電子組件之方法，其中該第二基板進一步包含至少部分地延伸通過該第二基板之導電穿孔。
  8. 如請求項1所述之形成微電子組件之方法，其進一步包含加熱接合的所述第一基板及第二基板以在該第一金屬接觸襯墊與該第二基板上之電性特徵之間設置電性路徑。
  9. 一種形成微電子組件之方法，其包含： 形成設置於具有第一接合表面之第一基板內之第一直通矽穿孔，該第一直通矽穿孔在垂直於該第一接合表面之方向上延伸至該第一基板中； 形成在該第一接合表面處或自該第一接合表面稍微凹陷之第一金屬接觸襯墊及第二金屬接觸襯墊，該第一金屬接觸襯墊在該第一接合表面下方部分地延伸至該第一基板中並在自該第一接合表面貫穿該第一基板之前述方向上與該第一直通矽穿孔對準，該第二金屬接觸襯墊在該第一接合表面處或自該第一接合表面稍微凹陷，該第二金屬接觸襯墊在該第一接合表面下方部分地延伸至該第一基板中且不與該第一直通矽穿孔在自該第一接合表面貫穿該第一基板之前述方向上對準；及 平坦化該第一接合表面以具有預定最大表面差異以用於直接接合並調整該第一金屬接觸襯墊及該第二金屬接觸襯墊相對於該第一接合表面之凹陷，使得該第一金屬接觸襯墊之凹陷補償該直通矽穿孔及第一金屬接觸襯墊相對於該第一接合表面之熱膨脹。
  10. 如請求項9所述之形成微電子組件之方法，其中該第一金屬接觸襯墊具有大於該第二金屬接觸襯墊之表面積。
  11. 如請求項9所述之形成微電子組件之方法，其進一步包含處理該第一基板之與該第一接合表面相對之側以形成第二接合表面。
  12. 如請求項11所述之形成微電子組件之方法，其中該處理包含薄化該第一基板及沉積一或多個層以平衡由該第一表面在該第一基板中引起之應力。
  13. 如請求項12所述之形成微電子組件之方法，其中薄化該第一基板暴露了該第一直通矽穿孔，且該一或多個層形成於該直通矽穿孔上方，該方法進一步包含圖案化該一或多個層以在該第一直通矽穿孔上方形成開口。
  14. 如請求項13所述之形成微電子組件之方法，其進一步包含將障壁層沉積至先前該開口之經暴露表面上，且將導電材料沉積在該障壁層上及該開口內。
  15. 如請求項11所述之形成微電子組件之方法，其進一步包含使用直接介電質至介電質、非黏著性接合技術在該第一基板之該第一接合表面處而將該第一基板直接接合至第二基板。
  16. 如請求項15所述之形成微電子組件之方法，其進一步包含經由該第一直通矽穿孔及嵌入該第二基板內且在該第二基板之接合表面處暴露之一或多個導電結構將熱自該第一基板傳遞至該第二基板。
  17. 一種微電子組件，其包含： 第一直通矽穿孔，其設置於具有第一接合表面之第一基板內，該第一直通矽穿孔在垂直於該第一接合表面之方向上延伸至該第一基板中；及 在該第一接合表面處或自該第一接合表面稍微凹陷之第一金屬接觸襯墊及第二金屬接觸襯墊，該第一金屬接觸襯墊在該第一接合表面下方部分地延伸至該第一基板中且在自該第一接合表面貫穿該第一基板之前述方向上與該第一直通矽穿孔對準，該第二金屬接觸襯墊在該第一接合表面處或自該第一接合表面稍微凹陷，該第二金屬接觸襯墊在該第一接合表面下方部分地延伸至該第一基板中且不與該第一直通矽穿孔在自該第一接合表面貫穿該第一基板之前述方向上對準，該第一金屬接觸襯墊具有大於該第二金屬接觸襯墊之表面積。
  18. 如請求項17所述之微電子組件，其中該第一基板在與該第一接合表面相對之一側上包括第二接合表面。
  19. 如請求項17所述之微電子組件，其中該第一基板包括應力平衡層以補償由該第一表面在該第一基板中引起之應力。
  20. 如請求項17所述之微電子組件，其中該第一基板使用直接介電質至介電質、非黏著性接合技術在該第一基板之該第一接合表面處直接接合至第二基板。
TW108120529A 2018-06-13 2019-06-13 直通矽穿孔上方的大型金屬襯墊 TW202013610A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11574891B2 (en) 2021-01-26 2023-02-07 Nanya Technology Corporation Semiconductor device with heat dissipation unit and method for fabricating the same
TWI815726B (zh) * 2022-11-11 2023-09-11 力晶積成電子製造股份有限公司 半導體結構的製造方法

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11176450B2 (en) 2017-08-03 2021-11-16 Xcelsis Corporation Three dimensional circuit implementing machine trained network
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
EP3807927A4 (en) * 2018-06-13 2022-02-23 Invensas Bonding Technologies, Inc. TSV AS A HIDEPAD
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10937755B2 (en) * 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
JP7118785B2 (ja) 2018-07-12 2022-08-16 キオクシア株式会社 半導体装置
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR102674029B1 (ko) * 2018-10-26 2024-06-13 삼성전자주식회사 테스트 패드를 포함하는 반도체 패키지
US10707151B2 (en) * 2018-11-20 2020-07-07 Nanya Technology Corporation Through silicon via structure and method for manufacturing the same
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210098412A1 (en) * 2019-09-26 2021-04-01 Invensas Bonding Technologies, Inc. Direct gang bonding methods and structures
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US20210265253A1 (en) 2020-02-25 2021-08-26 Tokyo Electron Limited Split substrate interposer with integrated passive device
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11107775B1 (en) * 2020-03-31 2021-08-31 Nanya Technology Corporation Semiconductor device with electrically floating contacts between signal-transmitting contacts
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US20210335660A1 (en) * 2020-04-24 2021-10-28 Nanya Technology Corporation Semiconductor structure having void between bonded wafers and manufacturing method tehreof
WO2021236361A1 (en) * 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11233088B2 (en) * 2020-06-12 2022-01-25 Omnivision Technologies, Inc. Metal routing in image sensor using hybrid bonding
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
KR20220033619A (ko) * 2020-09-08 2022-03-17 삼성전자주식회사 반도체 패키지
KR20220042765A (ko) 2020-09-28 2022-04-05 삼성전자주식회사 비휘발성 메모리 장치, 이를 포함하는 시스템, 및 이의 제조 방법
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
JP2024501016A (ja) * 2020-12-28 2024-01-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 基板貫通ビアを有する構造体及びそれを形成する方法
CN117751436A (zh) * 2021-08-02 2024-03-22 华为技术有限公司 芯片堆叠结构及其制作方法、芯片封装结构、电子设备
US20230058897A1 (en) * 2021-08-17 2023-02-23 International Business Machines Corporation Thermal conduction layer
KR20230055839A (ko) 2021-10-19 2023-04-26 한국과학기술원 적층 패드 구조의 패드 패턴층들을 포함하는 반도체 장치 및 그 제조 방법
WO2023129901A1 (en) * 2021-12-27 2023-07-06 Adeia Semiconductor Bonding Technologies Inc. Directly bonded frame wafers
CN115966512A (zh) * 2022-12-14 2023-04-14 湖北江城芯片中试服务有限公司 半导体结构及其制作方法以及封装系统

Family Cites Families (410)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1489643A1 (de) * 1964-07-22 1969-08-21 Atomenergi Ab Brennstoffelement fuer einen wassergekuehlten Kernreaktor
JPS6130059A (ja) 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
KR900008647B1 (ko) 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US4904328A (en) 1987-09-08 1990-02-27 Gencorp Inc. Bonding of FRP parts
US4784970A (en) 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
JPH0272642A (ja) 1988-09-07 1990-03-12 Nec Corp 基板の接続構造および接続方法
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5489804A (en) 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
JP3190057B2 (ja) 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
JP2729413B2 (ja) 1991-02-14 1998-03-18 三菱電機株式会社 半導体装置
JP2910334B2 (ja) 1991-07-22 1999-06-23 富士電機株式会社 接合方法
JPH05198739A (ja) 1991-09-10 1993-08-06 Mitsubishi Electric Corp 積層型半導体装置およびその製造方法
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5236118A (en) 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
JPH0682753B2 (ja) 1992-09-28 1994-10-19 株式会社東芝 半導体装置の製造方法
US5503704A (en) 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
EP0610709B1 (de) 1993-02-11 1998-06-10 Siemens Aktiengesellschaft Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
US5516727A (en) 1993-04-19 1996-05-14 International Business Machines Corporation Method for encapsulating light emitting diodes
JPH0766093A (ja) 1993-08-23 1995-03-10 Sumitomo Sitix Corp 半導体ウエーハの貼り合わせ方法およびその装置
JP2560625B2 (ja) 1993-10-29 1996-12-04 日本電気株式会社 半導体装置およびその製造方法
JPH07193294A (ja) 1993-11-01 1995-07-28 Matsushita Electric Ind Co Ltd 電子部品およびその製造方法
US5501003A (en) 1993-12-15 1996-03-26 Bel Fuse Inc. Method of assembling electronic packages for surface mount applications
US5442235A (en) 1993-12-23 1995-08-15 Motorola Inc. Semiconductor device having an improved metal interconnect structure
US5413952A (en) 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
JP3294934B2 (ja) 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JPH07283382A (ja) 1994-04-12 1995-10-27 Sony Corp シリコン基板のはり合わせ方法
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
JPH08125121A (ja) 1994-08-29 1996-05-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3171366B2 (ja) 1994-09-05 2001-05-28 三菱マテリアル株式会社 シリコン半導体ウェーハ及びその製造方法
DE4433330C2 (de) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
JPH08186235A (ja) 1994-12-16 1996-07-16 Texas Instr Inc <Ti> 半導体装置の製造方法
JP2679681B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置、半導体装置用パッケージ及びその製造方法
US5610431A (en) 1995-05-12 1997-03-11 The Charles Stark Draper Laboratory, Inc. Covers for micromechanical sensors and other semiconductor devices
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JP3490198B2 (ja) 1995-10-25 2004-01-26 松下電器産業株式会社 半導体装置とその製造方法
JP3979687B2 (ja) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法
KR100438256B1 (ko) 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
DK0808815T3 (da) 1996-05-14 2001-11-26 Degussa Fremgangsmåde til fremstilling af trimethylhydroquinon
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3383811B2 (ja) 1996-10-28 2003-03-10 松下電器産業株式会社 半導体チップモジュール及びその製造方法
US5888631A (en) 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US5821692A (en) 1996-11-26 1998-10-13 Motorola, Inc. Organic electroluminescent device hermetic encapsulation package
WO1998028788A1 (en) 1996-12-24 1998-07-02 Nitto Denko Corporation Manufacture of semiconductor device
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JPH10223636A (ja) 1997-02-12 1998-08-21 Nec Yamagata Ltd 半導体集積回路装置の製造方法
JP4026882B2 (ja) 1997-02-24 2007-12-26 三洋電機株式会社 半導体装置
US5929512A (en) 1997-03-18 1999-07-27 Jacobs; Richard L. Urethane encapsulated integrated circuits and compositions therefor
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
AU7147798A (en) 1997-04-23 1998-11-13 Advanced Chemical Systems International, Inc. Planarization compositions for cmp of interlayer dielectrics
JP4032454B2 (ja) 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JPH11186120A (ja) 1997-12-24 1999-07-09 Canon Inc 同種あるいは異種材料基板間の密着接合法
US6137063A (en) 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
EP0951068A1 (en) 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6147000A (en) 1998-08-11 2000-11-14 Advanced Micro Devices, Inc. Method for forming low dielectric passivation of copper interconnects
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
JP2000100679A (ja) 1998-09-22 2000-04-07 Canon Inc 薄片化による基板間微小領域固相接合法及び素子構造
SG99289A1 (en) 1998-10-23 2003-10-27 Ibm Chemical-mechanical planarization of metallurgy
US6515343B1 (en) 1998-11-19 2003-02-04 Quicklogic Corporation Metal-to-metal antifuse with non-conductive diffusion barrier
US6409904B1 (en) 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US6123825A (en) 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
US6232150B1 (en) 1998-12-03 2001-05-15 The Regents Of The University Of Michigan Process for making microstructures and microstructures made thereby
JP3918350B2 (ja) 1999-03-05 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
US6348709B1 (en) 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6259160B1 (en) 1999-04-21 2001-07-10 Advanced Micro Devices, Inc. Apparatus and method of encapsulated copper (Cu) Interconnect formation
JP2000311982A (ja) 1999-04-26 2000-11-07 Toshiba Corp 半導体装置と半導体モジュールおよびそれらの製造方法
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
KR100333384B1 (ko) 1999-06-28 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조방법
US6218203B1 (en) 1999-06-28 2001-04-17 Advantest Corp. Method of producing a contact structure
JP3619395B2 (ja) 1999-07-30 2005-02-09 京セラ株式会社 半導体素子内蔵配線基板およびその製造方法
US6756253B1 (en) 1999-08-27 2004-06-29 Micron Technology, Inc. Method for fabricating a semiconductor component with external contact polymer support layer
US6583515B1 (en) 1999-09-03 2003-06-24 Texas Instruments Incorporated Ball grid array package for enhanced stress tolerance
US6593645B2 (en) 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6333120B1 (en) 1999-10-27 2001-12-25 International Business Machines Corporation Method for controlling the texture and microstructure of plated copper and plated structure
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
AU2001247109A1 (en) 2000-04-27 2001-11-12 Nutool, Inc. Conductive structure for use in multi-level metallization and process
JP4123682B2 (ja) 2000-05-16 2008-07-23 セイコーエプソン株式会社 半導体装置及びその製造方法
US6326698B1 (en) 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices
JP4322402B2 (ja) 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
CN1222195C (zh) 2000-07-24 2005-10-05 Tdk株式会社 发光元件
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
US6483044B1 (en) 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6583460B1 (en) 2000-08-29 2003-06-24 Micron Technology, Inc. Method of forming a metal to polysilicon contact in oxygen environment
JP2002110799A (ja) 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
US6600224B1 (en) 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6552436B2 (en) 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
JP3705159B2 (ja) 2001-06-11 2005-10-12 株式会社デンソー 半導体装置の製造方法
DE10131627B4 (de) 2001-06-29 2006-08-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
JP2003023071A (ja) 2001-07-05 2003-01-24 Sony Corp 半導体装置製造方法および半導体装置
US6847527B2 (en) 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6667225B2 (en) 2001-12-17 2003-12-23 Intel Corporation Wafer-bonding using solder and method of making the same
US20030113947A1 (en) 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding
US6660564B2 (en) 2002-01-25 2003-12-09 Sony Corporation Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6624003B1 (en) 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6720212B2 (en) 2002-03-14 2004-04-13 Infineon Technologies Ag Method of eliminating back-end rerouting in ball grid array packaging
US6627814B1 (en) 2002-03-22 2003-09-30 David H. Stark Hermetically sealed micro-device package with window
US6642081B1 (en) 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
JP3918935B2 (ja) 2002-12-20 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
JP3981026B2 (ja) 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7135780B2 (en) 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI275168B (en) 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
US20040262772A1 (en) 2003-06-30 2004-12-30 Shriram Ramanathan Methods for bonding wafers using a metal interlayer
JP2005086089A (ja) 2003-09-10 2005-03-31 Seiko Epson Corp ３次元デバイスの製造方法
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
JP2005135988A (ja) 2003-10-28 2005-05-26 Toshiba Corp 半導体装置の製造方法
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US6927498B2 (en) 2003-11-19 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad for flip chip package
US7842948B2 (en) 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
KR100618855B1 (ko) 2004-08-02 2006-09-01 삼성전자주식회사 금속 콘택 구조체 형성방법 및 이를 이용한 상변화 메모리제조방법
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060076634A1 (en) 2004-09-27 2006-04-13 Lauren Palmateer Method and system for packaging MEMS devices with incorporated getter
GB0505680D0 (en) 2005-03-22 2005-04-27 Cambridge Display Tech Ltd Apparatus and method for increased device lifetime in an organic electro-luminescent device
US7998335B2 (en) 2005-06-13 2011-08-16 Cabot Microelectronics Corporation Controlled electrochemical polishing method
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
US20070145367A1 (en) 2005-12-27 2007-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit structure
US7348648B2 (en) 2006-03-13 2008-03-25 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature
TWI299552B (en) 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure
US7972683B2 (en) 2006-03-28 2011-07-05 Innovative Micro Technology Wafer bonding material with embedded conductive particles
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
KR100825648B1 (ko) 2006-11-29 2008-04-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US9343330B2 (en) 2006-12-06 2016-05-17 Cabot Microelectronics Corporation Compositions for polishing aluminum/copper and titanium in damascene structures
US7812459B2 (en) 2006-12-19 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuits with protection layers
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US8134235B2 (en) 2007-04-23 2012-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional semiconductor device
KR101494591B1 (ko) 2007-10-30 2015-02-23 삼성전자주식회사 칩 적층 패키지
US8435421B2 (en) 2007-11-27 2013-05-07 Cabot Microelectronics Corporation Metal-passivating CMP compositions and methods
DE102008007001B4 (de) 2008-01-31 2016-09-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Vergrößern des Widerstandsverhaltens gegenüber Elektromigration in einer Verbindungsstruktur eines Halbleiterbauelements durch Bilden einer Legierung
US20090200668A1 (en) 2008-02-07 2009-08-13 International Business Machines Corporation Interconnect structure with high leakage resistance
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR100945800B1 (ko) 2008-12-09 2010-03-05 김영혜 이종 접합 웨이퍼 제조방법
IT1392793B1 (it) 2008-12-30 2012-03-23 St Microelectronics Srl Condensatore integrato con piatto a spessore non-uniforme
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
KR101049083B1 (ko) 2009-04-10 2011-07-15 (주)실리콘화일 3차원 구조를 갖는 이미지 센서의 단위 화소 및 그 제조방법
CN202758883U (zh) 2009-05-26 2013-02-27 拉姆伯斯公司 堆叠的半导体器件组件
US8101517B2 (en) 2009-09-29 2012-01-24 Infineon Technologies Ag Semiconductor device and method for making same
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
WO2011108436A1 (ja) 2010-03-01 2011-09-09 国立大学法人大阪大学 半導体装置及び半導体装置用接合材
US9018768B2 (en) 2010-06-28 2015-04-28 Samsung Electronics Co., Ltd. Integrated circuit having through silicon via structure with minimized deterioration
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
CN104011848A (zh) 2010-07-30 2014-08-27 昆山智拓达电子科技有限公司 一种硅通孔互连结构及其制造方法
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
JP2012174988A (ja) 2011-02-23 2012-09-10 Sony Corp 接合電極、接合電極の製造方法、半導体装置、及び、半導体装置の製造方法
KR101780423B1 (ko) 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
TWI467695B (zh) 2011-03-24 2015-01-01 Sony Corp 半導體裝置及其製造方法
WO2012133760A1 (ja) 2011-03-30 2012-10-04 ボンドテック株式会社 電子部品実装方法、電子部品実装システムおよび基板
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
KR102378636B1 (ko) 2011-05-24 2022-03-25 소니그룹주식회사 반도체 장치
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
JP6031765B2 (ja) 2011-07-05 2016-11-24 ソニー株式会社 半導体装置、電子機器、及び、半導体装置の製造方法
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
US8692246B2 (en) 2011-09-15 2014-04-08 International Business Machines Corporation Leakage measurement structure having through silicon vias
US8742591B2 (en) 2011-12-21 2014-06-03 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US20130256913A1 (en) 2012-03-30 2013-10-03 Bryan Black Die stacking with coupled electrical interconnects to align proximity interconnects
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
JP2013243333A (ja) 2012-04-24 2013-12-05 Tadatomo Suga チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
US9412725B2 (en) 2012-04-27 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US9048283B2 (en) * 2012-06-05 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding systems and methods for semiconductor wafers
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US8772946B2 (en) 2012-06-08 2014-07-08 Invensas Corporation Reduced stress TSV and interposer structures
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20140175614A1 (en) 2012-12-20 2014-06-26 Industrial Technology Research Institute Wafer stacking structure and method of manufacturing the same
DE102012224310A1 (de) 2012-12-21 2014-06-26 Tesa Se Gettermaterial enthaltendes Klebeband
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8916448B2 (en) 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9082644B2 (en) 2013-01-18 2015-07-14 Infineon Technologies Ag Method of manufacturing and testing a chip package
TWI518991B (zh) 2013-02-08 2016-01-21 Sj Antenna Design Integrated antenna and integrated circuit components of the shielding module
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
WO2014131152A1 (en) 2013-02-26 2014-09-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including alternating stepped semiconductor die stacks
US9331032B2 (en) 2013-03-06 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding and apparatus for performing the same
US9105485B2 (en) 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9040385B2 (en) 2013-07-24 2015-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
JP6330151B2 (ja) 2013-09-17 2018-05-30 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
JP6212720B2 (ja) 2013-09-20 2017-10-18 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
FR3011679B1 (fr) 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
KR102104061B1 (ko) 2013-11-15 2020-04-23 삼성전자 주식회사 금속 패턴 및 압전 패턴을 포함하는 반도체 소자
US9059333B1 (en) 2013-12-04 2015-06-16 International Business Machines Corporation Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
TWI538156B (zh) 2014-01-07 2016-06-11 甯樹樑 晶片間無微接觸點之晶圓級晶片堆疊結構及其製造方法
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US9343433B2 (en) 2014-01-28 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stacked dies and methods of forming the same
US9425155B2 (en) 2014-02-25 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding process and structure
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9391109B2 (en) 2014-03-28 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Uniform-size bonding patterns
US9343369B2 (en) * 2014-05-19 2016-05-17 Qualcomm Incorporated Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
KR102274775B1 (ko) 2014-11-13 2021-07-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
CN111883501A (zh) 2015-05-18 2020-11-03 索尼公司 半导体装置和成像装置
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN105140144A (zh) 2015-09-02 2015-12-09 武汉新芯集成电路制造有限公司 一种介质加压热退火混合键合方法
KR102468773B1 (ko) 2015-10-19 2022-11-22 삼성전자주식회사 반도체 소자
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9893028B2 (en) 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same
US9881882B2 (en) 2016-01-06 2018-01-30 Mediatek Inc. Semiconductor package with three-dimensional antenna
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
JP6448848B2 (ja) 2016-03-11 2019-01-09 ボンドテック株式会社 基板接合方法
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US10354975B2 (en) 2016-05-16 2019-07-16 Raytheon Company Barrier layer for interconnects in 3D integrated device
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US9892961B1 (en) 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11176450B2 (en) 2017-08-03 2021-11-16 Xcelsis Corporation Three dimensional circuit implementing machine trained network
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
JP2018064758A (ja) * 2016-10-19 2018-04-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置、製造方法、および電子機器
CN106571334B (zh) 2016-10-26 2020-11-10 上海集成电路研发中心有限公司 一种硅片间的混合键合方法
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
WO2018125673A2 (en) 2016-12-28 2018-07-05 Invensas Bonding Technologies, Inc Processing stacked substrates
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
CN106653720A (zh) 2016-12-30 2017-05-10 武汉新芯集成电路制造有限公司 一种混合键合结构及混合键合方法
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
CN106920795B (zh) 2017-03-08 2019-03-12 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
CN106920797B (zh) 2017-03-08 2018-10-12 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
JP2018163970A (ja) 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10312275B2 (en) 2017-04-25 2019-06-04 Semiconductor Components Industries, Llc Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
CN107665829B (zh) 2017-08-24 2019-12-17 长江存储科技有限责任公司 晶圆混合键合中提高金属引线制程安全性的方法
CN107731668B (zh) 2017-08-31 2018-11-13 长江存储科技有限责任公司 3d nand混合键合工艺中补偿晶圆应力的方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
CN107993928B (zh) 2017-11-20 2020-05-12 长江存储科技有限责任公司 一种抑制晶圆混合键合中铜电迁移的方法
CN107993927A (zh) 2017-11-20 2018-05-04 长江存储科技有限责任公司 提高晶圆混合键合强度的方法
US11152417B2 (en) 2017-11-21 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Anchor structures and methods for uniform wafer planarization and bonding
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
JP6967980B2 (ja) 2018-01-23 2021-11-17 東京エレクトロン株式会社 接合方法、および接合装置
TWI823598B (zh) 2018-01-23 2023-11-21 日商東京威力科創股份有限公司 接合系統及接合方法
US11127738B2 (en) 2018-02-09 2021-09-21 Xcelsis Corporation Back biasing of FD-SOI circuit blocks
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US10403577B1 (en) 2018-05-03 2019-09-03 Invensas Corporation Dielets on flexible and stretchable packaging for microelectronics
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10629592B2 (en) * 2018-05-25 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Through silicon via design for stacking integrated circuits
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
CN112514059B (zh) 2018-06-12 2024-05-24 隔热半导体粘合技术公司 堆叠微电子部件的层间连接
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
EP3807927A4 (en) 2018-06-13 2022-02-23 Invensas Bonding Technologies, Inc. TSV AS A HIDEPAD
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US20200035641A1 (en) 2018-07-26 2020-01-30 Invensas Bonding Technologies, Inc. Post cmp processing for hybrid bonding
WO2020034063A1 (en) 2018-08-13 2020-02-20 Yangtze Memory Technologies Co., Ltd. Bonding contacts having capping layer and method for forming the same
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
CN111211133B (zh) 2018-09-10 2021-03-30 长江存储科技有限责任公司 使用梳状路由结构以减少金属线装载的存储器件
WO2020051737A1 (en) 2018-09-10 2020-03-19 Yangtze Memory Technologies Co., Ltd. Memory device using comb-like routing structure for reduced metal line loading
CN111415941B (zh) 2018-09-20 2021-07-30 长江存储科技有限责任公司 多堆叠层三维存储器件
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
WO2020107452A1 (en) 2018-11-30 2020-06-04 Yangtze Memory Technologies Co., Ltd. Bonded memory device and fabrication methods thereof
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
WO2020140212A1 (en) 2019-01-02 2020-07-09 Yangtze Memory Technologies Co., Ltd. Plasma activation treatment for wafer bonding
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210098412A1 (en) 2019-09-26 2021-04-01 Invensas Bonding Technologies, Inc. Direct gang bonding methods and structures
US20210118864A1 (en) 2019-10-21 2021-04-22 Invensas Corporation Non-Volatile Dynamic Random Access Memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
KR20220120631A (ko) 2019-12-23 2022-08-30 인벤사스 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
KR20230097121A (ko) 2020-10-29 2023-06-30 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 방법 및 구조체
WO2022094579A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
JP2024501016A (ja) 2020-12-28 2024-01-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 基板貫通ビアを有する構造体及びそれを形成する方法
WO2022147430A1 (en) 2020-12-28 2022-07-07 Invensas Bonding Technologies, Inc. Structures with through-substrate vias and methods for forming the same
US20220208723A1 (en) 2020-12-30 2022-06-30 Invensas Bonding Technologies, Inc. Directly bonded structures
KR20230126736A (ko) 2020-12-30 2023-08-30 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 전도성 특징부를 갖는 구조 및 그 형성방법
US20220285303A1 (en) 2021-03-03 2022-09-08 Invensas Bonding Technologies, Inc. Contact structures for direct bonding
JP2024515032A (ja) 2021-03-31 2024-04-04 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 担体の直接接合及び剥離
EP4315411A1 (en) 2021-03-31 2024-02-07 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
JP2024515033A (ja) 2021-03-31 2024-04-04 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 担体の直接ボンディング及び剥離
KR20240028356A (ko) 2021-06-30 2024-03-05 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 결합층에서 라우팅 구조체를 갖는 소자
US20230019869A1 (en) 2021-07-16 2023-01-19 Invensas Bonding Technologies, Inc. Optically occlusive protective element for bonded structures
WO2023014616A1 (en) 2021-08-02 2023-02-09 Invensas Bonding Technologies, Inc. Protective semiconductor elements for bonded structures
WO2023034738A1 (en) 2021-09-01 2023-03-09 Adeia Semiconductor Technologies Llc Stacked structure with interposer
US20230067677A1 (en) 2021-09-01 2023-03-02 Invensas Bonding Technologies, Inc. Sequences and equipment for direct bonding
WO2023044308A1 (en) 2021-09-14 2023-03-23 Adeia Semiconductor Bonding Technologies Inc. Method of bonding thin substrates
WO2023049812A1 (en) 2021-09-24 2023-03-30 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with active interposer
US20230122531A1 (en) 2021-10-18 2023-04-20 Invensas Llc Reduced parasitic capacitance in bonded structures
US20230123423A1 (en) 2021-10-19 2023-04-20 Adeia Semiconductor Bonding Technologies Inc Stacked inductors in multi-die stacking
WO2023070033A1 (en) 2021-10-22 2023-04-27 Adeia Semiconductor Technologies Llc Radio frequency device packages
WO2023076842A1 (en) 2021-10-25 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Power distribution for stacked electronic devices
US20230125395A1 (en) 2021-10-27 2023-04-27 Adeia Semiconductor Bonding Technologies Inc. Stacked structures with capacitive coupling connections
US20230140107A1 (en) 2021-10-28 2023-05-04 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
US20230142680A1 (en) 2021-10-28 2023-05-11 Adeia Semiconductor Bonding Technologies Inc. Stacked electronic devices
KR20240091148A (ko) 2021-10-28 2024-06-21 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 확산 베리어 및 그 형성 방법
KR20240094026A (ko) 2021-11-05 2024-06-24 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 멀티-채널 디바이스 스태킹
WO2023091430A1 (en) 2021-11-17 2023-05-25 Adeia Semiconductor Bonding Technologies Inc. Thermal bypass for stacked dies
WO2023091485A1 (en) 2021-11-18 2023-05-25 Adeia Semiconductor Bonding Technologies Inc. Fluid cooling for die stacks
US20230187264A1 (en) 2021-12-13 2023-06-15 Adeia Semiconductor Technologies Llc Methods for bonding semiconductor elements
US20230187317A1 (en) 2021-12-13 2023-06-15 Adeia Semiconductor Bonding Technologies Inc. Interconnect structures
US20230197453A1 (en) 2021-12-17 2023-06-22 Adeia Semiconductor Bonding Technologies Inc. Structure with conductive feature for direct bonding and method of forming same
WO2023122513A1 (en) 2021-12-20 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Direct bonding and debonding of elements
WO2023122510A1 (en) 2021-12-20 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Thermoelectric cooling in microelectronics
WO2023122509A1 (en) 2021-12-20 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Thermoelectric cooling for die packages
WO2023122559A1 (en) 2021-12-22 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Low stress direct hybrid bonding
WO2023122687A1 (en) 2021-12-23 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Apparatuses and methods for die bond control
WO2023122732A1 (en) 2021-12-23 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Direct bonding on package substrates
WO2023122771A1 (en) 2021-12-23 2023-06-29 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with interconnect assemblies
WO2023129901A1 (en) 2021-12-27 2023-07-06 Adeia Semiconductor Bonding Technologies Inc. Directly bonded frame wafers
WO2023147502A1 (en) 2022-01-31 2023-08-03 Adeia Semiconductor Bonding Technologies Inc. Heat dissipating system for electronic devices
US20230268300A1 (en) 2022-02-24 2023-08-24 Adeia Semiconductor Bonding Technologies Inc. Bonded structures

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11574891B2 (en) 2021-01-26 2023-02-07 Nanya Technology Corporation Semiconductor device with heat dissipation unit and method for fabricating the same
TWI809551B (zh) * 2021-01-26 2023-07-21 南亞科技股份有限公司 具有散熱單元的半導體元件及其製備方法
US11728316B2 (en) 2021-01-26 2023-08-15 Nanya Technology Corporation Method for fabricating semiconductor device with heat dissipation features
TWI815726B (zh) * 2022-11-11 2023-09-11 力晶積成電子製造股份有限公司 半導體結構的製造方法

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