WO2023279720A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023279720A1
WO2023279720A1 PCT/CN2022/076466 CN2022076466W WO2023279720A1 WO 2023279720 A1 WO2023279720 A1 WO 2023279720A1 CN 2022076466 W CN2022076466 W CN 2022076466W WO 2023279720 A1 WO2023279720 A1 WO 2023279720A1
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chip
layer
sidewall
tsv
substrate
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PCT/CN2022/076466
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP22836480.8A priority Critical patent/EP4207262A4/en
Priority to US17/662,737 priority patent/US11569149B1/en
Publication of WO2023279720A1 publication Critical patent/WO2023279720A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof.
  • the TSV (Through Silicon Via) process is a high-density packaging technology that is gradually replacing the current relatively mature wire bonding technology and is considered to be the fourth-generation packaging technology.
  • the through-silicon via technology realizes the vertical electrical interconnection of the through-silicon via by filling conductive substances such as copper, tungsten, and polysilicon, which can transmit signals from one side of the chip to the other side of the chip, and realize multi-layer through the combination of chip stacking technology. 3D integration of chips. Through-silicon via technology can effectively shorten the length of interconnection lines between chips and reduce signal delay through vertical interconnection, thereby improving the signal transmission performance and operating frequency of electronic systems, increasing broadband and realizing miniaturization of device integration. It is a future semiconductor technology. important direction of development.
  • the TSV process mainly includes deep silicon etching to form micropores, deposition of insulating layer/barrier layer/seed layer, deep hole filling, chemical mechanical polishing, thinning, Pad (pad) preparation and redistribution line preparation and other process technologies.
  • the traditional TSV process is to process TSVs on the front of the chip, and form an electrical connection with the metal interconnection on the front of the chip, and finally thin the semiconductor chip to realize the electrode extraction of the TSV on the back of the chip.
  • the TSV is only located in one of the chips.
  • additional conductive structures such as: solder balls, conductive bumps, etc.
  • Chip electrical connection, structure and manufacturing process are more complicated.
  • the present application provides a method for preparing a semiconductor structure, comprising the following steps:
  • a stacked structure includes a first chip and a second chip, the second chip is face-to-face bonded on the first chip, and both the first chip and the second chip include a substrate , a dielectric layer on the substrate and a metal layer in the dielectric layer;
  • the through-silicon via includes a first portion and a second portion communicated with the first portion, the first portion penetrates the substrate of the second chip, and
  • the sidewall of the first part is a vertical sidewall;
  • the second part penetrates through the metal layer of the second chip, and penetrates at least part of the metal layer in the first chip, and the second part the sidewall of the part is an inclined sidewall, and the width of the bottom of the second part is smaller than the width of the top of the second part;
  • a conductive layer is formed in the TSV, and the conductive layer is electrically connected to the metal layer penetrating through the first chip and the second chip.
  • the first chip and the second chip both include pads, and the pads are located on the side of the metal layer away from the substrate; the through-silicon vias also penetrate through the The pads in the first chip and the pads in the second chip.
  • the forming an insulating layer on the sidewall of the first portion includes:
  • the insulating material layer on the sidewall and bottom of the second part is removed by dry etching process, and the insulating material layer remaining on the sidewall of the first part is the insulating layer.
  • the inclination angle of the sidewall of the second portion relative to the surface of the substrate is 60°-80°.
  • the depth of the TSV is 50 ⁇ m ⁇ 100 ⁇ m, and the width of the TSV is 2 ⁇ m ⁇ 10 ⁇ m.
  • Described providing laminated structure comprises:
  • through-silicon vias in the stacked structure includes:
  • the first chip and the second chip are etched by an etching process to form the through-silicon vias.
  • the second chip is bonded to the first chip via a bonding layer; the through-silicon vias also penetrate through the bonding layer.
  • the forming a conductive layer in the TSV includes:
  • a filled conductive layer is formed on the surface of the metal barrier layer, and the filled conductive layer fills up the TSV.
  • the present application also provides a semiconductor structure, comprising:
  • a stacked structure includes a first chip and a second chip, the second chip is face-to-face bonded on the first chip, the first chip and the second chip both include a substrate, a dielectric layer on the substrate and a metal layer within the dielectric layer;
  • the through-silicon via includes a first portion and a second portion connected to the first portion, the first portion penetrates through the substrate of the second chip, and the sidewall of the first portion is a vertical side wall; the second part penetrates the metal layer of the second chip, and penetrates at least part of the metal layer in the first chip, the side wall of the second part is an inclined side wall, and the width of the bottom of the second portion is less than the width of the top of the second portion;
  • the conductive layer is located in the TSV and fills the TSV, the conductive layer is electrically connected to the metal layer penetrating through the first chip and the second chip.
  • the first chip and the second chip both include pads, and the pads are located on the side of the metal layer away from the substrate; the through-silicon vias also penetrate through the The pads in the first chip and the pads in the second chip.
  • the inclination angle of the sidewall of the second portion relative to the surface of the substrate is 60°-80°.
  • the depth of the TSV is 50 ⁇ m-100 ⁇ m, and the width of the TSV is 2 ⁇ m-10 ⁇ m
  • it is characterized in that it further includes a bonding layer, the bonding layer is located between the first chip and the second chip, and is connected to the dielectric layer and the first chip of the first chip.
  • the dielectric layers of the second chip are in contact.
  • the conductive layer includes:
  • a metal barrier layer located on the surface of the insulating layer, the sidewall and the bottom of the second part;
  • the filling conductive layer is located on the surface of the metal barrier layer and fills up the through-silicon hole.
  • the metal barrier layer includes a tantalum layer; the insulating layer includes a pad oxide layer.
  • the manufacturing method of the semiconductor structure in this application forms through-silicon vias through the second chip and part of the first chip, and forms a conductive layer in the through-silicon vias, so that the first chip and the second chip can be realized without additional conductive structures.
  • the electrical connection between the inner metal layers can simplify the semiconductor structure and process steps; at the same time, because the sidewalls of the second part are inclined sidewalls, it is convenient to form an insulating layer only on the sidewalls of the first part, simplifying the process steps, cut costs.
  • the semiconductor structure in this application uses the through-silicon vias that penetrate the second chip and part of the first chip, and the conductive layer located in the through-silicon holes, so that the first chip and each layer of metal in the second chip can be realized without additional conductive structures.
  • the electrical connection between layers can simplify the semiconductor structure and process steps; at the same time, because the sidewalls of the second part are inclined sidewalls, it is convenient to form an insulating layer only on the sidewalls of the first part, simplifying process steps and reducing costs.
  • 1 is a schematic cross-sectional view of a semiconductor structure
  • FIG. 2 is a flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application
  • step S1 is a schematic cross-sectional view of the structure obtained in step S1 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
  • step S2 is a schematic cross-sectional view of the structure obtained in step S2 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
  • FIG. 5 is a flow chart of step S3 in the method for preparing a semiconductor structure provided in an embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of the structure obtained in step S301 in the method for preparing a semiconductor structure provided in an embodiment of the present application;
  • step S302 is a schematic cross-sectional view of the structure obtained in step S302 in the method for preparing a semiconductor structure provided in an embodiment of the present application, and is also a schematic cross-sectional view of the structure obtained in step S3;
  • step S4 is a schematic cross-sectional view of the structure obtained in step S4 in the method for preparing a semiconductor structure provided in an embodiment of the present application, and is also a schematic structural view of the semiconductor structure provided in another embodiment of the present application;
  • FIG. 9 is a flowchart of step S4 in the method for manufacturing a semiconductor structure provided in an embodiment of the present application.
  • First chip 111. Substrate; 112. Dielectric layer; 113. Metal layer; 114. Pad; 12. Second chip; 13. Through silicon vias; 131. First part; 132. Second part; 14 , insulating layer; 15, conductive layer; 16, bonding layer; 17, solder ball; 401, insulating material layer;
  • first or second may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be referred to as These terms are limited. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section.
  • a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention;
  • the first chip is referred to as the second chip, and similarly, the second chip may be referred to as the first chip; the first chip and the second chip are different chips.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the invention should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • the conventional semiconductor structure includes a laminated structure, a through-silicon via 13 ′, an insulating layer 14 ′, and a conductive layer 15 ′.
  • the laminated structure includes a first chip 11' and a second chip 12', and the second chip 12' is face-to-face bonded on the first chip 11' via a bonding layer 16', and the first chip 11' and the second chip 12 'both include a substrate 111', a dielectric layer 112' located on the substrate 111', and a metal layer 113' located in the dielectric layer 112'.
  • the TSV 13' penetrates through the substrate 111' of the second chip 12' and the dielectric layer 112' of the second chip 12'.
  • the insulating layer 14' is located on the sidewall of the first portion 131'.
  • the conductive layer 15' is located in the TSV 13' and fills the TSV 13'.
  • the conductive layer 15' is electrically connected to the metal layer 113' penetrating through the first chip 11' and the second chip 12'.
  • the TSV 13' is only located in the second chip 12', so additional solder balls 17' are needed to establish metal interconnection, and the manufacturing process is complicated.
  • the present application provides a method for preparing a semiconductor structure, including the following steps:
  • S1 Provide a stacked structure;
  • the stacked structure includes a first chip and a second chip, the second chip is face-to-face bonded on the first chip, and both the first chip and the second chip include a substrate and a dielectric layer on the substrate and a metal layer located in the dielectric layer;
  • S2 Form a through-silicon via in the stacked structure;
  • the through-silicon via includes a first part and a second part connected to the first part, the first part penetrates the substrate of the second chip, and the sidewall of the first part is vertical Sidewall;
  • the second part runs through the metal layer of the second chip and at least part of the metal layer in the first chip, the sidewall of the second part is an inclined sidewall, and the width of the bottom of the second part is smaller than that of the top of the second part width;
  • the manufacturing method of the semiconductor structure provided by this application forms the through-silicon via through the second chip and part of the first chip, and forms a conductive layer in the through-silicon via, so that the first chip and the second chip can be realized without additional conductive structures.
  • the electrical connection between the inner metal layers can simplify the semiconductor structure and reduce the process steps; at the same time, because the side wall of the second part is an inclined side wall, it is convenient to form an insulating layer only on the side wall of the first part, simplifying the process steps , reduce cost; in addition, the second chip is face-to-face bonded to the first chip, so that the resulting structure also has high precision, the formed stacked structure occupies a small volume, and I/O (Input/Output, input/output) density is high , Short interconnect lines and small lead parasitic parameters.
  • the bonding of the first chip and the second chip can be realized by using a wafer-level packaging process, such as WOW (wafer on wafer) or COW (chip on wafer), or chip scale package (CSP, chip scale package ) process to realize the bonding of the first chip and the second chip.
  • a wafer-level packaging process such as WOW (wafer on wafer) or COW (chip on wafer), or chip scale package (CSP, chip scale package ) process to realize the bonding of the first chip and the second chip.
  • the inclination angle of the sidewall of the second part relative to the surface of the substrate may be 60°-80°, such as 60°, 65°, 70°, 75° or 80°, etc.; in the preparation method provided in some embodiments, the depth of the TSV can be 50 ⁇ m to 100 ⁇ m, such as 50 ⁇ m, 65 ⁇ m, 80 ⁇ m or 100 ⁇ m, etc.; in the preparation method provided in some embodiments, the TSV The width of the semiconductor structure can be 2 ⁇ m to 10 ⁇ m, such as 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, 8 ⁇ m or 10 ⁇ m, etc.; The depth of the TSV and the specific size of the width of the TSV are not limited.
  • a stacked structure is provided; the stacked structure includes a first chip 11 and a second chip 12, and the second chip 12 is face-to-face bonded on the first chip 11, and the second chip 12 is bonded face-to-face.
  • Both the first chip 11 and the second chip 12 include a substrate 111 , a dielectric layer 112 on the substrate 111 , and a metal layer 113 in the dielectric layer 112 .
  • step S1 may include the following steps:
  • a second chip 12 is provided, and the second chip 12 is face-to-face bonded to the first chip 11 .
  • the substrate 111 may include but not limited to a silicon substrate, a silicon nitride substrate or a silicon oxynitride substrate, etc.; the dielectric layer 112 may include but not limited to a silicon dioxide layer or a silicon nitride layer , the application does not limit the materials of the substrate 111 and the dielectric layer 112 .
  • the dielectric layer 112 may be located on the front side of the substrate 111 .
  • the so-called “face-to-face” means that after the second chip 12 is bonded on the first chip 11, the dielectric layer 112 in the second chip 12 is bonded to the dielectric layer 112 in the first chip 11; that is, as shown in FIG. 3 , it may be that the first chip 11 is face-up, and the second chip 12 is bonded on the first chip 11 face-down.
  • the first chip 11 and the second chip 12 can both include pads 114, and the pads 114 are located on the side of the metal layer 113 away from the substrate 111; , the TSVs 13 also penetrate through the pads 114 in the first chip 11 and the pads 114 in the second chip 12 .
  • a through hole (not shown) may be reserved in the metal layer 113 and the bonding pad 114, and the through hole corresponds to the subsequently formed TSV 13, and after the TSV 13 is formed, it will become a Part of the through hole 13.
  • the method for preparing the semiconductor structure can reserve through holes in the metal layer 113 and the pad 114, and when forming the dielectric layer 112 covering the metal layer 113 and the pad 114, the reserved through hole will be It is filled with a dielectric layer 112, so that in the subsequent process of forming through-silicon vias 13, the etching step after etching the substrate 111 is to etch the dielectric layer 112, and there will be no alternate etching of the dielectric layer 112 and the metal layer 113 or In the case of the pad 114, the process steps can be simplified and the production efficiency can be improved.
  • the pad 114 may include but not limited to a copper pad, and this application does not limit the material of the pad 114 .
  • a through-silicon via 13 is formed in the laminated structure;
  • the through-silicon via 13 includes a first part 131 and a second part 132 connected to the first part 131, the first part 131 penetrates the substrate 111 of the second chip 12, and the sidewall of the first part 131 is a vertical sidewall;
  • the second part 132 penetrates the metal layer 113 of the second chip 12, and penetrates at least part of the first chip 11
  • the sidewall of the second portion 132 is an inclined sidewall, and the width of the bottom of the second portion 132 is smaller than the width of the top of the second portion 132 .
  • step S2 may include the following steps:
  • the first chip 11 and the second chip 12 are etched by an etching process to form TSVs 13 .
  • the second chip 12 can be bonded to the first chip 11 via the bonding layer 16 ;
  • the bonding layer 16 may include but not limited to an aluminum/copper composite layer, and the application does not limit the material and structure of the bonding layer 16 .
  • the traditional aluminum wire has become a bottleneck restricting the stability of the system performance.
  • copper has better thermal conductivity and electrical conductivity, and the coefficient of electric thermal expansion is lower.
  • the step of etching the first chip 11 and the second chip 12 by an etching process to form the through-silicon via 13 may include etching the first chip 11 and the second chip 13 by using a dry etching process. chip 12 to form TSVs 13 .
  • the step of etching the first chip 11 and the second chip 12 by using the dry etching process to form the through-silicon vias 13 it may further include etching the stack by using the wet etching process. structure to widen the width of the TSV 13 to ensure that the pads 114 in the first chip 11 and the second chip 12 are fully exposed.
  • step S3 referring to S3 in FIG. 2 and FIGS. 5 to 7 , an insulating layer 14 is formed on the sidewall of the first portion 131 .
  • step S3 may include the following steps:
  • S301 Form an insulating material layer 401 on the sidewall and bottom of the TSV 13, as shown in FIG. 6 ;
  • the sidewall of the second part is an inclined sidewall
  • the insulating material layer located on the sidewall and bottom of the second part can be directly removed, so that only the sidewall of the first part
  • An insulating layer is formed so that the resulting structure can directly form an electrical connection between the metal layers in the first chip and the second chip through the conductive layer in the through-silicon via, without additional solder balls or wiring, which simplifies the process steps and reduces cost.
  • the insulating material layer 401 may include but not limited to an oxide layer, and the present application does not limit the structure and material of the insulating material layer 401 .
  • step S302 referring to S302 in FIG. 5 and FIG. 7 , the insulating material layer 401 on the sidewall and bottom of the second part 132 is removed, and the insulating material layer 401 remaining on the sidewall of the first part 131 is the insulating layer 14 .
  • the insulating material layer 401 located on the sidewall and bottom of the second portion 132 may be removed by but not limited to a dry etching process.
  • the stacked structure may be etched by a wet etching process to widen the width of the through-silicon via 13 and ensure the pads in the first chip 11 and the second chip 12 114 fully exposed.
  • step S4 please refer to S4 in FIG. 2 and FIGS. connect.
  • step S4 may include the following steps:
  • S402 Form a filling conductive layer 15 on the surface of the metal barrier layer, and the filling conductive layer 15 fills the TSV 13 .
  • the present application also provides a semiconductor structure, including a stacked structure, through-silicon vias 13, an insulating layer 14, and a conductive layer 15; wherein, the stacked structure includes a first chip 11 and a second chip 12; wherein , the second chip 12 is face-to-face bonded on the first chip 11, the first chip 11 and the second chip 12 both include a substrate 111, a dielectric layer 112 on the substrate 111 and a metal layer 113 in the dielectric layer 112;
  • the TSV 13 includes a first portion 131 and a second portion 132 connected to the first portion 131; wherein, the first portion 131 penetrates the substrate 111 of the second chip 12, and the sidewall of the first portion 131 is a vertical sidewall;
  • the second part 132 penetrates the metal layer 113 of the second chip 12, and penetrates at least part of the metal layer 113 in the first chip 11.
  • the sidewall of the second part 132 is an inclined sidewall, and the width of the bottom of the second part 132 is smaller than that of the second part.
  • the width of the top of part 132; the insulating layer 14 is located on the sidewall of the first part 131; the conductive layer 15 is located in the through-silicon via 13 and fills the through-silicon via 13, and the conductive layer 15 penetrates through the first chip 11 and the second chip 12
  • the metal layer 113 is electrically connected.
  • each layer in the first chip and the second chip can be realized without additional conductive structures.
  • the electrical connection between the metal layers can simplify the semiconductor structure and reduce the process steps; at the same time, because the sidewall of the second part is an inclined sidewall, it is convenient to form an insulating layer only on the sidewall of the first part, simplifying the process steps and reducing the cost .
  • the substrate 111 may include but not limited to a silicon substrate, a sapphire substrate, a silicon nitride substrate or a silicon oxynitride substrate, etc.; the dielectric layer 112 may include but not limited to a silicon dioxide layer or For the silicon nitride layer, the present application does not limit the materials of the substrate 111 and the dielectric layer 112 .
  • both the first chip 11 and the second chip 12 may include pads 114 ; specifically, the pads 114 may be located on the side of the metal layer 113 away from the substrate 111 .
  • the pad 114 may include but not limited to a copper pad, and the application does not limit the material of the pad 114 .
  • the TSVs 13 also penetrate through the pads 114 in the first chip 11 and the pads 114 in the second chip 12 .
  • the inclination angle of the sidewall of the second part relative to the substrate surface may be 60°-80°, such as 60°, 65°, 70°, 75° or 80°, etc.; in the semiconductor structure provided in some embodiments, the depth of the through-silicon via can be 50 ⁇ m to 100 ⁇ m, such as 50 ⁇ m, 65 ⁇ m, 80 ⁇ m, or 100 ⁇ m; in the semiconductor structure provided in some embodiments, the through-silicon via The width can be 2 ⁇ m to 10 ⁇ m, such as 2 ⁇ m, 4 ⁇ m, 6 ⁇ m, 8 ⁇ m or 10 ⁇ m, etc.; the semiconductor structure provided by this application has an inclination angle of the sidewall of the second part compared to the substrate surface, the depth of the through-silicon hole and The specific size of the width of the TSV is not limited.
  • the semiconductor structure may further include a bonding layer 16; specifically, the bonding layer 16 is located between the first chip 11 and the second chip 12, and is connected to the first chip 11.
  • the dielectric layer 112 is in contact with the dielectric layer 112 of the second chip 12 .
  • the bonding layer 16 may include but not limited to an aluminum/copper composite layer, and the application does not limit the material and structure of the bonding layer 16 .
  • the traditional aluminum wire has become a bottleneck restricting the stability of the system performance.
  • copper has better thermal conductivity and electrical conductivity, and the coefficient of electric thermal expansion is lower.
  • the conductive layer 15 may include a metal barrier layer and a filled conductive layer; wherein, the metal barrier layer is located on the surface of the insulating layer, the sidewall and the bottom of the second part; the filled conductive layer is located on the surface of the metal barrier layer, And fill the TSVs 13 .
  • the barrier metal layer may include, but not limited to, a tantalum layer, a barrier metal layer of other materials or a laminated structure thereof, and the present application does not limit the material and form of the barrier metal layer.
  • the insulating layer 14 may include but not limited to a pad oxide layer.
  • the pad oxide layer may include but not limited to a silicon dioxide layer or other oxide layers, and the present application does not limit the structure and material of the pad oxide layer.

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Abstract

本申请涉及一种半导体结构及其制备方法，包括提供叠层结构，包括第一芯片及第二芯片；于所述叠层结构内形成硅通孔，包括第一部分及与所述第一部分相连通的第二部分，第一部分的侧壁为竖直侧壁，第二部分的侧壁为倾斜侧壁；于所述第一部分的侧壁上形成绝缘层；于所述硅通孔内形成导电层。本申请提供的半导体结构及其制备方法通过形成贯穿第二芯片及部分第一芯片的硅通孔，并于硅通孔内形成导电层，无需额外的导电结构即可实现第一芯片与第二芯片内各层金属层之间的电连接，可以简化半导体结构及工艺步骤；同时，由于第二部分的侧壁为倾斜侧壁，便于仅仅于第一部分的侧壁上形成绝缘层，简化工艺步骤，降低成本。

Description

半导体结构及其制备方法
相关申请的交叉引用
本申请要求于2021年07月09日提交中国专利局、申请号为202110779490.X、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
TSV(Through Silicon Via，硅通孔技术)工艺是一项高密度封装技术，正在逐渐取代目前工艺比较成熟的引线键合技术，被认为是第四代封装技术。硅通孔技术通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连，可以将信号从芯片的一面传导至芯片的另一面，并通过结合芯片堆叠技术，实现多层芯片的三维集成。硅通孔技术可以通过垂直互连有效缩短芯片间互连线的长度，减小信号延迟，从而提高电子系统的信号传输性能和工作频率，增加宽带和实现器件集成的小型化，是未来半导体技术发展的重要方向。
TSV工艺主要包括深硅刻蚀形成微孔，绝缘层/阻挡层/种子层的沉积，深孔填充，化学机械抛光，减薄、Pad(焊盘)的制备及再分布线制备等工艺技 术。其中，传统的TSV工艺是在芯片正面加工TSV，并于芯片正面的金属互连形成电连接，最后再减薄所述半导体芯片，实现TSV在芯片背面的电极引出。
然而，采用传统的TSV工艺，TSV仅位于其中一个芯片内，当两个或多个芯片键合在一起时，需要额外的导电结构(譬如：焊球、导电凸块等等)将相邻的芯片电连接，结构及制造工艺比较复杂。
发明内容
基于此，有必要针对上述背景技术中的问题提供一种无需额外的焊球即可实现金属互连的半导体结构及其制备方法。
为了实现上述目的，一方面，本申请提供了一种半导体结构的制备方法，包括如下步骤：
提供叠层结构；所述叠层结构包括第一芯片及第二芯片，所述第二芯片面对面键合于所述第一芯片上，所述第一芯片及所述第二芯片均包括衬底、位于所述衬底上的介质层及位于所述介质层内的金属层；
于所述叠层结构内形成硅通孔；所述硅通孔包括第一部分及与所述第一部分相连通的第二部分，所述第一部分贯穿所述第二芯片的所述衬底，且所述第一部分的侧壁为竖直侧壁；所述第二部分贯穿所述第二芯片的所述金属层，并贯穿至少部分所述第一芯片中的所述金属层，所述第二部分的侧壁为倾斜侧壁，且所述第二部分底部的宽度小于所述第二部分顶部的宽度；
于所述第一部分的侧壁上形成绝缘层；
于所述硅通孔内形成导电层，所述导电层与所述第一芯片及所述第二芯片内贯穿的所述金属层电连接。
在其中一个实施例中，所述第一芯片及所述第二芯片还均包括焊盘，所述焊盘位于所述金属层远离所述衬底的一侧；所述硅通孔还贯穿所述第一芯片中的所述焊盘及所述第二芯片中的所述焊盘。
在其中一个实施例中，所述于所述第一部分的侧壁上形成绝缘层包括：
于所述硅通孔的侧壁及底部形成绝缘材料层；
采用干法刻蚀工艺去除位于所述第二部分侧壁及底部的所述绝缘材料层，保留于所述第一部分侧壁的所述绝缘材料层即为所述绝缘层。
在其中一个实施例中，所述第二部分的侧壁相较于所述衬底表面的倾斜角度为60°～80°。
在其中一个实施例中，所述硅通孔的深度为50μm～100μm，所述硅通孔的宽度为2μm～10μm。
在其中一个实施例中，
所述提供叠层结构包括：
提供所述第一芯片；
提供所述第二芯片，将所述第二芯片面对面键合于所述第一芯片上；
所述于所述叠层结构内形成硅通孔包括：
采用刻蚀工艺刻蚀所述第一芯片及所述第二芯片，以形成所述硅通孔。
在其中一个实施例中，所述第二芯片经由键合层键合于所述第一芯片上；所述硅通孔还贯穿所述键合层。
在其中一个实施例中，所述于所述硅通孔内形成导电层包括：
于所述绝缘层的表面、所述第二部分的侧壁及底部形成金属阻挡层；
于所述金属阻挡层的表面形成填充导电层，所述填充导电层填满所述硅 通孔。
本申请还提供了一种半导体结构，包括：
叠层结构，所述叠层结构包括第一芯片及第二芯片，所述第二芯片面对面键合于所述第一芯片上，所述第一芯片及所述第二芯片均包括衬底、位于所述衬底上的介质层及位于所述介质层内的金属层；
硅通孔，所述硅通孔包括第一部分及与所述第一部分相连通的第二部分，所述第一部分贯穿所述第二芯片的所述衬底，且所述第一部分的侧壁为竖直侧壁；所述第二部分贯穿所述第二芯片的金属层，并贯穿至少部分所述第一芯片中的金属层，所述第二部分的侧壁为倾斜侧壁，且所述第二部分底部的宽度小于所述第二部分顶部的宽度；
绝缘层，位于所述第一部分的侧壁；
导电层，位于所述硅通孔内，且填满所述硅通孔，所述导电层与所述第一芯片及所述第二芯片内贯穿的所述金属层电连接。
在其中一个实施例中，所述第一芯片及所述第二芯片还均包括焊盘，所述焊盘位于所述金属层远离所述衬底的一侧；所述硅通孔还贯穿所述第一芯片中的所述焊盘及所述第二芯片中的所述焊盘。
在其中一个实施例中，其特征在于，所述第二部分的侧壁相较于所述衬底表面的倾斜角度为60°～80°。
在其中一个实施例中，其特征在于，所述硅通孔的深度为50μm～100μm，所述硅通孔的宽度为2μm～10μm
在其中一个实施例中，其特征在于，还包括键合层，所述键合层位于所述第一芯片与所述第二芯片之间，并与所述第一芯片的所述介质层及所述第二芯片的所述介质层相接触。
在其中一个实施例中，所述导电层包括：
金属阻挡层，位于所述绝缘层的表面、所述第二部分的侧壁及底部；
填充导电层，位于所述金属阻挡层的表面，并填满所述硅通孔。
在其中一个实施例中，所述金属阻挡层包括钽层；所述绝缘层包括垫氧化层。
本申请中的半导体结构的制备方法通过形成贯穿第二芯片及部分第一芯片的硅通孔，并于硅通孔内形成导电层，无需额外的导电结构即可实现第一芯片与第二芯片内各层金属层之间的电连接，可以简化半导体结构及工艺步骤；同时，由于第二部分的侧壁为倾斜侧壁，便于仅仅于第一部分的侧壁上形成绝缘层，简化工艺步骤，降低成本。
本申请中的半导体结构通过贯穿第二芯片及部分第一芯片的硅通孔，以及位于硅通孔内的导电层，无需额外的导电结构即可实现第一芯片与第二芯片内各层金属层之间的电连接，可以简化半导体结构及工艺步骤；同时，由于第二部分的侧壁为倾斜侧壁，便于仅仅于第一部分的侧壁上形成绝缘层，简化工艺步骤，降低成本。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种半导体结构的截面示意图；
图2为本申请一实施例中提供的半导体结构的制备方法的流程图；
图3为本申请一实施例中提供的半导体结构的制备方法中，步骤S1所得结构的截面示意图；
图4为本申请一实施例中提供的半导体结构的制备方法中，步骤S2所得结构的截面示意图；
图5为本申请一实施例中提供的半导体结构的制备方法中，步骤S3的流程图；
图6为本申请一实施例中提供的半导体结构的制备方法中，步骤S301所得结构的截面示意图；
图7为本申请一实施例中提供的半导体结构的制备方法中，步骤S302所得结构的截面示意图，亦为步骤S3所得结构的截面示意图；
图8为本申请一实施例中提供的半导体结构的制备方法中，步骤S4所得结构的截面示意图，亦为本申请另一实施例中提供的半导体结构的结构示意图；
图9为本申请一实施例中提供的半导体结构的制备方法中，步骤S4的流程图。
附图标记说明：
11、第一芯片；111、衬底；112、介质层；113、金属层；114、焊盘；12、第二芯片；13、硅通孔、131、第一部分；132、第二部分；14、绝缘层；15、导电层；16、键合层；17、焊球；401、绝缘材料层；
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来 实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一或第二描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一芯片称为第二芯片，且类似地，可以将第二芯片称为第一芯片；第一芯片与第二芯片为不同的芯片。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包 括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
一种传统的半导体结构如图1所示，传统的半导体结构包括叠层结构、硅通孔13＇、绝缘层14＇及导电层15＇。其中，叠层结构包括第一芯片11＇及第二芯片12＇，第二芯片12＇经由键合层16＇面对面键合于第一芯片11＇上，第一芯片11＇及第二芯片12＇均包括衬底111＇、位于衬底111＇上的介质层112＇及位于介质层112＇内的金属层113＇。硅通孔13＇贯穿第二芯片12＇的衬底111＇及第二芯片12＇的介质层112＇。绝缘层14＇位于第一部分131＇的侧壁。导电层15＇位于硅通孔13＇内，且填满硅通孔13＇，导电层15＇与第一芯片11＇及第二芯片12＇内贯穿的金属层113＇电连接。然而，如图1所示，传统的半导体结构中，硅通孔13＇仅位于第二芯片12＇内，因 此需要额外的焊球17＇以建立金属互连，制造工艺复杂。
请参阅图2，本申请提供一种半导体结构的制备方法，包括如下步骤：
S1：提供叠层结构；叠层结构包括第一芯片及第二芯片，第二芯片面对面键合于第一芯片上，第一芯片及第二芯片均包括衬底、位于衬底上的介质层及位于介质层内的金属层；
S2：于叠层结构内形成硅通孔；硅通孔包括第一部分及与第一部分相连通的第二部分，第一部分贯穿第二芯片的衬底，且所述第一部分的侧壁为竖直侧壁；第二部分贯穿第二芯片的金属层，并贯穿至少部分第一芯片中的金属层，第二部分的侧壁为倾斜侧壁，且第二部分底部的宽度小于第二部分顶部的宽度；
S3：于第一部分的侧壁上形成绝缘层；
S4：于硅通孔内形成导电层，导电层与第一芯片及第二芯片内贯穿的金属层电连接。
本申请提供的半导体结构的制备方法通过形成贯穿第二芯片及部分第一芯片的硅通孔，并于硅通孔内形成导电层，无需额外的导电结构即可实现第一芯片与第二芯片内各层金属层之间的电连接，可以简化半导体结构，减少工艺步骤；同时，由于第二部分的侧壁为倾斜侧壁，便于仅仅于第一部分的侧壁上形成绝缘层，简化工艺步骤，降低成本；此外，通过第二芯片面对面键合于第一芯片上，使得所得结构还具有精度高、形成的叠层结构占用体积小、I/O(Input/Output，输入/输出)密度高、互连线短及引线寄生参数小等优点。
可选的，可以采用晶圆级封装工艺实现第一芯片与第二芯片的键合，比如WOW(wafer on wafer)或COW(chip on wafer)，也可以采用芯片级封装 (CSP，chip scale package)工艺实现第一芯片与第二芯片的键合。
可选的，在一些实施例提供的制备方法中，第二部分的侧壁相较于衬底表面的倾斜角度可以为60°～80°，譬如60°、65°、70°、75°或80°等等；在一些实施例提供的制备方法中，硅通孔的深度可以为50μm～100μm，譬如50μm、65μm、80μm或100μm等等；在一些实施例提供的制备方法中，硅通孔的宽度可以为2μm～10μm，譬如2μm、4μm、6μm、8μm或10μm等等；本申请提供的半导体结构的制备方法对于第二部分的侧壁相较于衬底表面的倾斜角度、硅通孔的深度及硅通孔的宽度的具体大小并不做限定。
在步骤S1中，请参阅图2中的S1及图3，提供叠层结构；叠层结构包括第一芯片11及第二芯片12，第二芯片12面对面键合于第一芯片11上，第一芯片11及第二芯片12均包括衬底111、位于衬底111上的介质层112及位于介质层112内的金属层113。
请继续参阅图3，在其中一个实施例中，步骤S1可以包括如下步骤：
提供所述第一芯片11；
提供第二芯片12，将第二芯片12面对面键合于第一芯片11上。
在其中一个实施例中，衬底111可以包括但不仅限于硅衬底、氮化硅衬底或氮氧化硅衬底等等；介质层112可以包括但不仅限于二氧化硅层或氮化硅层，本申请对于衬底111及介质层112的材质并不做限定。
具体的，介质层112可以位于衬底111的正面。所谓“面对面”是指第二芯片12键合于第一芯片11上之后，第二芯片12中的介质层112与第一芯片11中的介质层112键合在一起；即如图3所示，可以为第一芯片11正面朝上，第二芯片12正面朝下键合在第一芯片11上。
请继续参阅图3，在其中一个实施例中，第一芯片11及第二芯片12还可以均包括焊盘114，焊盘114位于金属层113远离衬底111的一侧；在上述实施例中，硅通孔13还贯穿第一芯片11中的焊盘114及第二芯片12中的焊盘114。
在其中一个实施例中，金属层113及焊盘114内可以预留有通孔(未标示出)，通孔与后续形成的硅通孔13相对应，在硅通孔13形成后会成为硅通孔13的一部分。
上述实施例提供的半导体结构的制备方法通过在金属层113及焊盘114内可以预留有通孔，在形成覆盖金属层113及焊盘114的介质层112时，预留的通孔内会填充为介质层112，这样在后续形成硅通孔13的过程中，刻蚀衬底111后的刻蚀步骤均为刻蚀介质层112，不会存在交替刻蚀介质层112与金属层113或焊盘114的情况，可以简化工艺步骤，提高生产效率。
可选的，焊盘114可以包括但不仅限于铜焊盘，本申请对于焊盘114的材质并不做限定。
在步骤S2中，请参阅图2中的S2及图4，于叠层结构内形成硅通孔13；硅通孔13包括第一部分131及与第一部分131相连通的第二部分132，第一部分131贯穿第二芯片12的衬底111，且所述第一部分131的侧壁为竖直侧壁；第二部分132贯穿第二芯片12的金属层113，并贯穿至少部分第一芯片11中的金属层113，第二部分132的侧壁为倾斜侧壁，且第二部分132底部的宽度小于第二部分132顶部的宽度。
请继续参阅图4，在其中一个实施例中，步骤S2可以包括如下步骤：
采用刻蚀工艺刻蚀第一芯片11及第二芯片12，以形成硅通孔13。
请继续参阅图4，在其中一个实施例中，第二芯片12可以经由键合层16 键合于第一芯片11上；上述实施例中，硅通孔13还可以贯穿键合层16。
在其中一个实施例中，键合层16可以包括但不仅限于铝/铜复合层，本申请对于键合层16的材质及结构并不做限定。
由于工作环境维持在高温状态，传统铝线成为限制系统性能稳定的制约瓶颈。相较铝金属而言，铜具有更好的导热性和导电性，且电热膨胀系数更低，然而半导体很难采用铜线键合；上述实施例提供的半导体结构的制备方法通过铝/铜复合层作为键合层16，铝金属能够提供良好的结合性，同时铜金属则能够提供优异的电气、机械和热学性能。
在其中一个实施例中，采用刻蚀工艺刻蚀第一芯片11及第二芯片12，以形成硅通孔13的步骤，可以包括采用干法刻蚀工艺，刻蚀第一芯片11及第二芯片12，以形成硅通孔13。
在其中一个实施例中，在采用干法刻蚀工艺，刻蚀第一芯片11及第二芯片12，以形成硅通孔13的步骤之后，还可以包括采用湿法刻蚀工艺刻蚀叠层结构，以拓宽硅通孔13的宽度，确保第一芯片11及第二芯片12中的焊盘114充分暴露。
在步骤S3中，请参阅图2中的S3及图5至图7，于第一部分131的侧壁上形成绝缘层14。
如图5所示，在其中一个实施例中，步骤S3可以包括如下步骤：
S301：于硅通孔13的侧壁及底部形成绝缘材料层401，如图6所示；
S302：去除位于第二部分132侧壁及底部的绝缘材料层401，保留于第一部分131侧壁的绝缘材料层401即为绝缘层14，如图7所示。
上述实施例提供的半导体结构的制备方法，由于第二部分的侧壁为倾斜侧壁，位于第二部分侧壁及底部的绝缘材料层能够被直接地去除，以仅仅于 第一部分的侧壁上形成绝缘层，使得所得结构能够通过位于硅通孔内的导电层直接在第一芯片与第二芯片内各层金属层之间形成电连接，无需额外的焊球或者布线，简化工艺步骤，降低成本。
在其中一个实施例中，绝缘材料层401可以包括但不仅限于氧化物层，本申请对于绝缘材料层401的结构和材质并不做限定。
在步骤S302中，请参阅图5中的S302及图7，去除位于第二部分132侧壁及底部的绝缘材料层401，保留于第一部分131侧壁的绝缘材料层401即为绝缘层14。
在其中一个实施例中，可以采用但不仅限于干法刻蚀工艺去除位于第二部分132侧壁及底部的绝缘材料层401。
在其中一个实施例中，还可以在步骤S302之后，再采用湿法刻蚀工艺刻蚀叠层结构，以拓宽硅通孔13的宽度，确保第一芯片11及第二芯片12中的焊盘114充分暴露。
在步骤S4中，请参阅图2中的S4及图8至图9，于硅通孔13内形成导电层15，导电层15与第一芯片11及第二芯片12内贯穿的金属层113电连接。
如图9所示，在其中一个实施例中，步骤S4可以包括如下步骤：
S401：于绝缘层14的表面、第二部分132的侧壁及底部形成金属阻挡层；
S402：于金属阻挡层的表面形成填充导电层15，填充导电层15填满硅通孔13。
应该理解的是，虽然图2、5、9的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图2、5、9中的至少一部分步骤可以包括多个步 骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请继续参阅图8，本申请还提供一种半导体结构，包括叠层结构、硅通孔13、绝缘层14及导电层15；其中，叠层结构包括第一芯片11及第二芯片12；其中，第二芯片12面对面键合于第一芯片11上，第一芯片11及第二芯片12均包括衬底111、位于衬底111上的介质层112及位于介质层112内的金属层113；硅通孔13包括第一部分131及与第一部分131相连通的第二部分132；其中，第一部分131贯穿第二芯片12的衬底111，且第一部分131的侧壁为竖直侧壁；第二部分132贯穿第二芯片12的金属层113，并贯穿至少部分第一芯片11中的金属层113，第二部分132的侧壁为倾斜侧壁，且第二部分132底部的宽度小于第二部分132顶部的宽度；绝缘层14位于第一部分131的侧壁；导电层15位于硅通孔13内，且填满硅通孔13，导电层15与第一芯片11及第二芯片12内贯穿的金属层113电连接。
本申请中的半导体结构，通过贯穿第二芯片及部分第一芯片的硅通孔，以及位于硅通孔内的导电层，无需额外的导电结构即可实现第一芯片与第二芯片内各层金属层之间的电连接，可以简化半导体结构，减少工艺步骤；同时，由于第二部分的侧壁为倾斜侧壁，便于仅仅于第一部分的侧壁上形成绝缘层，简化工艺步骤，降低成本。
在其中一个实施例中，衬底111可以包括但不仅限于硅衬底、蓝宝石衬底、氮化硅衬底或氮氧化硅衬底等等；介质层112可以包括但不仅限于二氧化硅层或氮化硅层，本申请对于衬底111及介质层112的材质并不做限定。
请继续参阅图8，在其中一个实施例中，第一芯片11及第二芯片12还可以均包括焊盘114；具体的，焊盘114可以位于金属层113远离衬底111的一侧。焊盘114可以包括但不仅限于铜焊盘，本申请对于焊盘114的材质并不做限定。
在上述实施例的基础上，硅通孔13还贯穿第一芯片11中的焊盘114及第二芯片12中的焊盘114。
可选的，在一些实施例提供的半导体结构中，第二部分的侧壁相较于衬底表面的倾斜角度可以为60°～80°，譬如60°、65°、70°、75°或80°等等；在一些实施例提供的半导体结构中，硅通孔的深度可以为50μm～100μm，譬如50μm、65μm、80μm或100μm等等；在一些实施例提供的半导体结构中，硅通孔的宽度可以为2μm～10μm，譬如2μm、4μm、6μm、8μm或10μm等等；本申请提供的半导体结构对于第二部分的侧壁相较于衬底表面的倾斜角度、硅通孔的深度及硅通孔的宽度的具体大小并不做限定。
请继续参阅图8，在其中一个实施例中，半导体结构还可以包括键合层16；具体的，键合层16位于第一芯片11与第二芯片12之间，并与第一芯片11的介质层112及第二芯片12的介质层112相接触。键合层16可以包括但不仅限于铝/铜复合层，本申请对于键合层16的材质及结构并不做限定。
由于工作环境维持在高温状态，传统铝线成为限制系统性能稳定的制约瓶颈。相较铝金属而言，铜具有更好的导热性和导电性，且电热膨胀系数更低，然而半导体很难采用铜线键合；上述实施例提供的半导体结构的制备方法通过铝/铜复合层作为键合层16，铝金属能够提供良好的结合性，同时铜金属则能够提供优异的电气、机械和热学性能。
在其中一个实施例中，导电层15可以包括金属阻挡层及填充导电层；其中，金属阻挡层位于绝缘层的表面、第二部分的侧壁及底部；填充导电层位于金属阻挡层的表面，并填满硅通孔13。
在其中一个实施例中，金属阻挡层可以包括但不仅限于钽层、其他材质的金属阻挡层或其叠层结构，本申请对于金属阻挡层的材质和形式均不做限定。
在其中一个实施例中，绝缘层14可以包括但不仅限于垫氧化层。
具体的，在一些实施例中，垫氧化层可以包括但不仅限于二氧化硅层或其他氧化物层，本申请对于垫氧化层的结构和材质并不做限定。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供叠层结构；所述叠层结构包括第一芯片及第二芯片，所述第二芯片面对面键合于所述第一芯片上，所述第一芯片及所述第二芯片均包括衬底、位于所述衬底上的介质层及位于所述介质层内的金属层；
    于所述叠层结构内形成硅通孔；所述硅通孔包括第一部分及与所述第一部分相连通的第二部分，所述第一部分贯穿所述第二芯片的所述衬底，且所述第一部分的侧壁为竖直侧壁；所述第二部分贯穿所述第二芯片的所述金属层，并贯穿至少部分所述第一芯片中的所述金属层，所述第二部分的侧壁为倾斜侧壁，且所述第二部分底部的宽度小于所述第二部分顶部的宽度；
    于所述第一部分的侧壁上形成绝缘层；
    于所述硅通孔内形成导电层，所述导电层与所述第一芯片及所述第二芯片内贯穿的所述金属层电连接。
  2. 根据权利要求1所述的制备方法，其中，所述第一芯片及所述第二芯片还均包括焊盘，所述焊盘位于所述金属层远离所述衬底的一侧；所述硅通孔还贯穿所述第一芯片中的所述焊盘及所述第二芯片中的所述焊盘。
  3. 根据权利要求1所述的制备方法，其中，所述于所述第一部分的侧壁上形成绝缘层包括：
    于所述硅通孔的侧壁及底部形成绝缘材料层；
    采用干法刻蚀工艺去除位于所述第二部分侧壁及底部的所述绝缘材料层，保留于所述第一部分侧壁的所述绝缘材料层即为所述绝缘层。
  4. 根据权利要求1所述的制备方法，其中，所述第二部分的侧壁相较于所述衬底表面的倾斜角度为60°～80°。
  5. 根据权利要求1所述的制备方法，其中，所述硅通孔的深度为50μm～100μm，所述硅通孔的宽度为2μm～10μm。
  6. 根据权利要求1所述的制备方法，其中，所述提供叠层结构包括：
    提供所述第一芯片；
    提供所述第二芯片，将所述第二芯片面对面键合于所述第一芯片上；
    所述于所述叠层结构内形成硅通孔包括：
    采用刻蚀工艺刻蚀所述第一芯片及所述第二芯片，以形成所述硅通孔。
  7. 根据权利要求6所述的制备方法，其中，所述第二芯片经由键合层键合于所述第一芯片上；所述硅通孔还贯穿所述键合层。
  8. 根据权利要求1至7中任一项所述的制备方法，其中，所述于所述硅通孔内形成导电层包括：
    于所述绝缘层的表面、所述第二部分的侧壁及底部形成金属阻挡层；
    于所述金属阻挡层的表面形成填充导电层，所述填充导电层填满所述硅通孔。
  9. 一种半导体结构，包括：
    叠层结构，所述叠层结构包括第一芯片及第二芯片，所述第二芯片面对面键合于所述第一芯片上，所述第一芯片及所述第二芯片均包括衬底、位于所述衬底上的介质层及位于所述介质层内的金属层；
    硅通孔，所述硅通孔包括第一部分及与所述第一部分相连通的第二部分，所述第一部分贯穿所述第二芯片的所述衬底，且所述第一部分的侧壁为竖直侧壁；所述第二部分贯穿所述第二芯片的金属层，并贯穿至少部分所述第一芯片中的金属层，所述第二部分的侧壁为倾斜侧壁，且所述第二部分底部的 宽度小于所述第二部分顶部的宽度；
    绝缘层，位于所述第一部分的侧壁；
    导电层，位于所述硅通孔内，且填满所述硅通孔，所述导电层与所述第一芯片及所述第二芯片内贯穿的所述金属层电连接。
  10. 根据权利要求9所述的半导体结构，其中，所述第一芯片及所述第二芯片还均包括焊盘，所述焊盘位于所述金属层远离所述衬底的一侧；所述硅通孔还贯穿所述第一芯片中的所述焊盘及所述第二芯片中的所述焊盘。
  11. 根据权利要求9所述的半导体结构，其中，所述第二部分的侧壁相较于所述衬底表面的倾斜角度为60°～80°。
  12. 根据权利要求10所述的半导体结构，其中，所述硅通孔的深度为50μm～100μm，所述硅通孔的宽度为2μm～10μm。
  13. 根据权利要求9所述的半导体结构，其中，还包括键合层，所述键合层位于所述第一芯片与所述第二芯片之间，并与所述第一芯片的所述介质层及所述第二芯片的所述介质层相接触。
  14. 根据权利要求9至13中任一项所述的半导体结构，其中，所述导电层包括：
    金属阻挡层，位于所述绝缘层的表面、所述第二部分的侧壁及底部；
    填充导电层，位于所述金属阻挡层的表面，并填满所述硅通孔。
  15. 根据权利要求14所述的半导体结构，其中，所述金属阻挡层包括钽层；所述绝缘层包括垫氧化层。
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