WO2024050911A1 - 半导体结构及其形成方法、存储器 - Google Patents

半导体结构及其形成方法、存储器 Download PDF

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Publication number
WO2024050911A1
WO2024050911A1 PCT/CN2022/124200 CN2022124200W WO2024050911A1 WO 2024050911 A1 WO2024050911 A1 WO 2024050911A1 CN 2022124200 W CN2022124200 W CN 2022124200W WO 2024050911 A1 WO2024050911 A1 WO 2024050911A1
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Prior art keywords
chip
chip unit
substrate
chipset
carrier board
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PCT/CN2022/124200
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English (en)
French (fr)
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吕开敏
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长鑫存储技术有限公司
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Priority to EP22945114.1A priority Critical patent/EP4358134A1/en
Priority to US18/527,739 priority patent/US20240105706A1/en
Publication of WO2024050911A1 publication Critical patent/WO2024050911A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H—ELECTRICITY
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    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor structure, a method of forming the same, and a memory.
  • Memory is widely used in mobile devices such as mobile phones and tablet computers due to its advantages such as small size, high degree of integration, and fast transmission speed. In order to increase the storage capacity of the memory, it is usually necessary to stack multiple chip units together.
  • an insulating layer needs to be laid on the surface and periphery of each chip unit. After the insulating layer is formed, the surface of the insulating layer needs to be ground by grinding to expose the surface of the chip unit at the top. However, the surface of the chip unit is easily damaged during the grinding process, thereby affecting the appearance of the product.
  • the present disclosure provides a semiconductor structure, a method for forming the same, and a memory, which can reduce the probability of uneven grinding, avoid scratches on the surface of the top chip during the grinding process, and improve the appearance of the product.
  • a method for forming a semiconductor structure including:
  • a chipset is formed on one side of the carrier board.
  • the chipset includes a plurality of chip units stacked in a direction perpendicular to the carrier board. Each of the chip units is close to the side of the carrier board.
  • the orthographic projection of the chip unit on the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board;
  • a grinding process is performed to expose a predetermined surface of the chip unit farthest from the carrier board to the outside of the insulating dielectric layer.
  • each chipset is spaced apart, and the insulating dielectric layer fills the gaps between the chipsets.
  • the group includes a bottom chip unit and a top chip unit. In a direction parallel to the carrier board, there is a first spacing between adjacent bottom chip units, and there is a second spacing between adjacent top chip units. , the width of the second interval is smaller than the width of the first interval.
  • the bottom chip unit in a direction parallel to the carrier board, has a first width, the top chip unit has a second width, and the second width is greater than the Describe the first width.
  • performing a grinding process to expose a predetermined surface of the chip unit farthest from the carrier board to the outside of the insulating dielectric layer includes:
  • the chip unit includes a substrate and a circuit module formed on a surface of the substrate, and a surface of the top chip unit on which the circuit module is formed faces the carrier board. .
  • the forming method further includes:
  • a logic chip is formed between the chipset and the carrier board, and the orthographic projection of the chipset on the carrier board is within the orthographic projection of the logic chip on the carrier board.
  • the forming method further includes:
  • the carrier board After performing the cutting process, the carrier board is removed, and a surface of the logic chip facing away from the chipset is electrically connected to a substrate.
  • the forming method further includes:
  • a cutting process is performed in the first interval and the second interval between each of the chip groups to separate each of the chip groups.
  • the insulating dielectric layer remains in the first interval.
  • a semiconductor structure including:
  • a chipset is provided on one side of the substrate and includes a plurality of chip units stacked in a direction perpendicular to the substrate, with each chip unit close to the side of the substrate in each of the chip units.
  • the orthographic projection on the substrate is within the orthographic projection of the chip unit farthest from the substrate on the substrate;
  • An insulating layer covers the outer periphery of the chipset, and a predetermined surface of the chip unit farthest from the substrate is exposed outside the insulating layer.
  • the chipset includes a bottom chip unit and a top chip unit, and the insulating layer located on a side wall of the top chip unit in a direction parallel to the substrate The thickness is no greater than the thickness of the insulating layer located on the sidewall of the bottom chip unit.
  • the bottom chip unit in a direction parallel to the substrate, has a first width, the top chip unit has a second width, and the second width is greater than the First width.
  • the chip unit includes a substrate and a circuit module formed on a surface of the substrate, and a surface of the top chip unit on which the circuit module is formed faces the substrate.
  • the semiconductor structure further includes:
  • a logic chip is disposed between the substrate and the chipset, and the orthographic projection of the chipset on the substrate is within the orthographic projection of the logic chip on the substrate.
  • a memory including the semiconductor structure described in any one of the above.
  • the semiconductor structure, method of forming the same, and memory of the present disclosure on the one hand, stack multiple chip units in the vertical direction, which helps to increase the storage capacity.
  • the orthographic projection of each chip unit on the carrier board on the side of the chip unit close to the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board, thereby increasing the size of the top chip.
  • the probability of uneven grinding caused by different surface hardness can reduce the probability of scratches or cracks on the surface of the top chip unit during the grinding process and improve the appearance of the product.
  • the structure formed after grinding exposes the predetermined surface of the top chip unit, the heat exchange between the chip unit and the outside world can be increased. During the working process of the chip unit, the heat dissipation efficiency can be improved and the power consumption can be reduced.
  • Figure 1 is a schematic diagram of a method of forming a semiconductor structure in an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure
  • Figure 3 is a top view of a semiconductor structure in an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a conductive unit in the disclosed embodiment
  • FIG. 5 is a schematic diagram after step S130 is completed in the disclosed embodiment
  • Figure 6 is a schematic diagram of the grinding area in the disclosed embodiment
  • Figure 7 is a schematic diagram of a conductive structure in a disclosed embodiment
  • FIG. 8 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings represent the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 shows a schematic diagram of the method for forming a semiconductor structure of the present disclosure.
  • the formation method may include steps S110 to S140, wherein:
  • Step S110 provide a carrier board
  • Step S120 Form a chipset on one side of the carrier board.
  • the chipset includes a plurality of chip units stacked in a direction perpendicular to the carrier board. The side of each chip unit close to the carrier board The orthographic projection of each of the chip units on the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board;
  • Step S130 forming an insulating dielectric layer covering the chipset
  • Step S140 Perform a grinding process to expose the predetermined surface of the chip unit farthest from the carrier board to the outside of the insulating dielectric layer.
  • the method of forming a semiconductor structure of the present disclosure stacks multiple chip units 21 in a vertical direction, which helps to increase storage capacity.
  • the orthographic projection of each chip unit 21 on the side of the carrier board 100 among the chip units 21 on the carrier board 100 is within the orthographic projection of the chip unit 21 farthest from the carrier board 100 on the carrier board 100 , thereby increasing the area of the top chip unit 211, and reducing the thickness of the insulating layer 4 located on the periphery of the top chip unit 211 while the overall size of the semiconductor structure remains unchanged, thereby reducing the thickness of the insulating dielectric layer 3 during the grinding process.
  • the structure formed after grinding exposes the predetermined surface of the top chip unit 211, the heat exchange between the chip unit 21 and the outside world can be increased. During the operation of the chip unit 21, the heat dissipation efficiency can be improved and the power consumption can be reduced.
  • step S110 a carrier board is provided.
  • Figure 2 shows a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
  • the carrier board 100 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular, and its material can be It is a semiconductor material.
  • the material may be silicon, but is not limited to silicon or other semiconductor materials.
  • the shape and material of the carrier 100 are not specifically limited here.
  • a chipset is formed on one side of the carrier board.
  • the chipset includes a plurality of chip units stacked in a direction perpendicular to the carrier board.
  • Each of the chip units The orthographic projection of each chip unit on the carrier board close to the side of the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board.
  • the chipset 2 may be formed on one side of the carrier board 100 , and the chipset 2 may include a plurality of chip units 21 .
  • the chipset 2 can be used in an integrated circuit.
  • it can be a dynamic random access memory (DRAM, Dynamic Random Access Memory) or a static random access memory (static random access memory, SRAM). It can also be used for The core component in dynamic random access memory (DRAM, Dynamic Random Access Memory) or static random access memory (static random access memory, SRAM).
  • multiple chip units 21 may be stacked in a direction vertical to the carrier board 100 to form a chipset 2 , for example.
  • the number of chip units 21 in the chipset 2 can be 2, 3, 4, 5, 6 or 7. Of course, it can also be other numbers, which are not specifically limited here.
  • each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21 and thus facilitates the integration of multiple different chip units 21
  • the data in the chip unit 21 is transmitted to the same chip unit 21, so that the electrical signals in each chip unit 21 in the chipset 2 can be simultaneously transmitted to the substrate through the same chip unit 21, so as to facilitate the connection between each chip unit 21 and the substrate. external circuit connection to achieve signal transmission.
  • each chip unit 21 in the chipset 2 may be spaced apart in a direction perpendicular to the carrier board 100 .
  • each chip unit 21 may be equally spaced in a direction perpendicular to the carrier board 100 .
  • two adjacent chip units 21 may be spaced apart by a preset distance.
  • the spacing between the chip units 21 may not be completely equal.
  • the spacing between at least two chip units 21 among the plurality of chip units 21 is not equal to the spacing between other two adjacent chip units 21 . .
  • the preset distance may be 10um-150um.
  • the preset distance may be 10um, 40um, 70um, 100um, 130um or 150um.
  • the preset distance may also be other values. I won’t list them all here.
  • the chip unit 21 may have a sheet-like structure, and its shape may be rectangular, circular, elliptical or irregular, which is not specifically limited here.
  • the thickness of each chip unit 21 may be the same or different, and is not specifically limited here.
  • the thickness of the chip unit 21 can be 40um-80um.
  • it can be 40um, 50um, 60um, 70um or 80um.
  • it can also be other thicknesses, which are not listed here.
  • each chip unit 21 in the chipset 2 may have the same thickness.
  • the thickness of each chip unit 21 may be 50 ⁇ m, or the thickness of each chip unit 21 may be 50 ⁇ m. 60um, or the thickness of each chip unit 21 can be 70um; of course, each chip unit 21 can also have other thicknesses, which are not listed here.
  • the chip unit 21 may include a substrate and a circuit module.
  • the circuit module may be disposed on the surface of the substrate. At least part of the chip units 21 of each chip unit 21 has a circuit module in the substrate.
  • the surface of the chip unit 21 may be disposed toward the carrier board 100 , and its surface without circuit modules may be disposed toward the side of each chip unit 21 away from the carrier board 100 .
  • the substrate of the chip unit 21 farthest from the carrier board 100 has a circuit module.
  • the surface may be positioned towards the carrier plate 100 .
  • the substrate may be a wafer.
  • the orthographic projection of each chip unit 21 on the side close to the carrier board 100 among the chip units 21 in the chipset 2 on the carrier board 100 is the one farthest from the carrier board 100 .
  • the chip unit 21 is within the orthographic projection on the carrier 100 .
  • the chip unit 21 farthest from the carrier board 100 can be defined as the top chip unit 211
  • the chip unit 21 located between the top chip unit 211 and the carrier board 100 is the bottom chip unit 212 .
  • the bottom chip unit 212 The number can be one or multiple, and there is no special limit here.
  • the bottom chip unit 212 may have a first width
  • the top chip unit 211 may have a second width
  • the second width may be greater than the first width. That is, in the chipset 2 , the area of the top chip unit 211 is larger than the area of any other chip unit 21 in the chipset 2 .
  • each chip unit 21 located between the top chip unit 211 and the carrier board 100 may be equal or unequal. That is, the areas of each chip unit 21 in the bottom chip unit 212 may be equal or unequal, and are not specifically limited here.
  • an insulating filling layer 7 may be provided between adjacent chip units 21 , and the adjacent chip units 21 may be insulated and isolated by the insulating filling layer 7 to avoid occurrence of occurrences between the chip units 21 .
  • the material of the insulating filling layer 7 can be insulating glue or encapsulating glue, which can isolate external water and oxygen through the insulating filling layer 7 and prevent external water and oxygen from entering the inside of the chip unit 21 , thereby preventing external water and oxygen from entering the chip unit 21 . Preventing water and oxygen from corroding the internal structure of the chip unit 21 can extend the service life of the chip unit 21 .
  • the insulating filling layer 7 can fill the gap between adjacent chip units 21 , and the gap between two adjacent chip units 21 can be supported by the insulating filling layer 7 , while , it can also balance the stress between two adjacent chip units 21, reduce the warpage of each chip unit 21, and thereby improve the product yield.
  • FIG. 3 shows a top view of a semiconductor structure in an embodiment of the present disclosure.
  • the number of chipsets 2 can be multiple, and multiple chipsets 2 can be formed on the same side of the carrier board 100 , the orthographic projection of each chipset 2 on the carrier board 100 can be located in the array area.
  • each chipset 2 can be distributed at intervals, and can be distributed in an array in the array area of the carrier 100 .
  • adjacent chip units 21 in the same chipset 2 are all electrically connected.
  • adjacent chip units 21 can be electrically connected through conductive units 51 . connection, and a plurality of conductive units 51 distributed at intervals can be arranged between adjacent chip units 21. In the direction perpendicular to the carrier board 100, the conductive units 51 located in different chip units 21 can be connected to each other, thereby forming Conductive Structure 5.
  • step S130 an insulating dielectric layer covering the chipset is formed.
  • chemical vapor deposition, physical vapor deposition or atomic layer deposition can be used to simultaneously form the insulating dielectric layer 3 on the side walls and top of the chipset 2.
  • the insulating dielectric layer can also be formed by other methods. Layer 3 will not be listed one by one here.
  • the material of the insulating dielectric layer 3 can be an insulating material, and the chipset 2 can be insulated and isolated through the insulating dielectric layer 3 to avoid coupling or short circuit between the chipset 2 and other surrounding structures, thereby improving product yield.
  • the insulating dielectric layer 3 can fill the gaps between the chipsets 2, thereby preventing coupling or interference between adjacent chipsets 2. Short circuit can improve product yield.
  • the width of the second interval may be less than the width of the first interval.
  • the width of the first spacer may be greater than or equal to 200 micrometers, and the width of the second spacer may be greater than or equal to 50 micrometers and less than or equal to 100 micrometers.
  • step S140 grinding is performed to expose the predetermined surface of the chip unit farthest from the carrier board to the outside of the insulating dielectric layer.
  • a grinding process can be used to grind the insulating dielectric layer 3.
  • the ground insulating dielectric layer 3 can expose the predetermined surface of the top chip unit 211, so as to increase the heat exchange between the chipset 2 and the outside world.
  • the insulating dielectric layer 3 can be polished. Improve heat dissipation efficiency and reduce power consumption.
  • the thickness of the insulating dielectric layer 3 located on the periphery of the top chip unit 211 is larger when the overall size of the semiconductor structure remains unchanged. Small, thereby reducing the proportion of the insulating dielectric layer 3 during the grinding process, which can reduce the probability of uneven grinding due to the different surface hardness of the insulating dielectric layer 3 and the chip unit 21, and can reduce the friction of the top chip unit 211 during the grinding process. The probability of scratches or cracks on the surface, thereby improving the appearance of the product.
  • the ratio of the width of the top chip unit 211 to the thickness of the insulating dielectric layer 3 located on the side walls of the top chip unit 211 may be 5 to 20,
  • the ratio of the width of the top chip unit 211 to the thickness of the insulating dielectric layer 3 located on the sidewall of the top chip unit 211 is 5, 10, 15 or 20.
  • it can also be other ratios, which will not be discussed here. Give examples one by one.
  • the thickness of the insulating dielectric layer 3 located on the sidewall of the top chip unit 211 may be greater than or equal to 50 microns and less than or equal to 100 microns.
  • the thickness of the insulating dielectric layer 3 located on the side walls of the top chip unit 211 may be 50 microns, 60 microns, 70 microns, 80 microns, 90 microns or 100 microns.
  • the thickness of the insulating dielectric layer 3 located on the side walls of the top chip unit 211 The thickness of the insulating dielectric layer 3 above can also be other, which will not be listed here.
  • each chip unit 21 between the top chip unit 211 and the carrier board 100 can be aligned at both ends, that is, each chip unit 21 in the bottom chip unit 212 can be aligned.
  • the two ends are aligned, and the thickness of the insulating dielectric layer 3 located on the periphery of each chip unit 21 in the bottom chip unit 212 can be equal, and the thickness of the insulating dielectric layer 3 located on the periphery of each chip unit 21 in the bottom chip unit 212 can be greater than The thickness of the chip unit 21 located at the outer periphery of the top chip unit 211.
  • the insulating dielectric layer 3 is only thinned in the thickness direction and is not processed in the direction parallel to the carrier board 100 .
  • the finally formed insulating dielectric layer 3 can fill the gaps between the chip sets 2 in the direction parallel to the carrier board 100 .
  • the insulating dielectric layer 3 and the substrate of each top chip unit 211 in each chipset 2 can be polished at the same time, and the distance carrier board 100 in each chipset 2 can be exposed at the same time through the same polishing process.
  • the farthest chip unit 21 is away from the surface of the carrier board 100 .
  • performing a grinding process to expose the predetermined surface of the chip unit 21 farthest from the carrier board 100 to the outside of the insulating dielectric layer 3 may include:
  • Step S210 grinding and removing the insulating dielectric layer 3 of the first target thickness to expose the top surface of the top chip unit 211 .
  • the first target thickness of the insulating dielectric layer 3 may be removed through a grinding process, and the first target thickness may be equal to the thickness of the insulating dielectric layer 3 covering the surface of the top chip unit 211 . After grinding and removing the insulating dielectric layer 3 of the first target thickness, the top surface of the top chip unit 211 can be exposed, that is, the surface of the substrate of the top chip unit 211 away from the circuit module can be exposed.
  • the first target thickness can be 100um-150um.
  • the first target thickness can be 100um, 110um, 120um, 130um, 140um or 150um.
  • the first target thickness can also be other thicknesses, which will not be discussed here. Give examples one by one.
  • Step S220 continue to grind and remove the top chip unit 211 and the insulating dielectric layer 3 with a second target thickness to expose the predetermined surface of the top chip unit 211, wherein the second target thickness is not greater than the desired thickness. Describe the first target thickness.
  • the top chip unit 211 and the insulating dielectric layer 3 can be continuously polished, and the surface of the substrate in the top chip unit 211 away from the circuit module can be thinned to reduce the thickness of the chipset 2 and further increase the size of the chip.
  • the heat dissipation efficiency of Group 2 during operation can further reduce power consumption.
  • the top chip unit 211 and the insulating dielectric layer 3 of the second target thickness may be removed.
  • the second target thickness may be smaller than the thickness of the substrate of the top chip unit 211 , and the second target thickness may not be larger than the thickness of the substrate of the top chip unit 211 .
  • a target thickness for example, the second target thickness can be 100nm ⁇ 140nm, for example, the second target thickness can be 100nm, 110nm, 120nm, 130nm or 140nm.
  • the second target thickness can also be other thicknesses, here No more listing them one by one.
  • grinding equipment can be used to grind the insulating dielectric layer 3 located on the surface of the top chip unit 211 and the substrate of the top chip unit 211 at the same time.
  • the grinding area is shown in the dotted box in Figure 6.
  • the proportion of the insulating dielectric layer 3 during the grinding process is small.
  • the hardness of the insulating dielectric layer 3 can be matched with the substrate. Grinding with a grinding head can reduce the probability of scratches or cracks on the surface of the top chip unit 211 during the grinding process, which helps to improve the appearance of the product.
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • Step S160 Form a logic chip 6 between the chipset 2 and the carrier board 100.
  • the orthographic projection of the chipset 2 on the carrier board 100 is equal to the orthographic projection of the logic chip 6 on the carrier board 100. within the orthographic projection.
  • the logic chip 6 can be formed between the carrier board 100 and the chipset 2 , and the logic chip 6 can be bonded to the carrier board 100 through insulating adhesive 200 .
  • the material of the insulating adhesive 200 can be non-conductive adhesive, UV adhesive, etc.
  • the logic chip 6 has a conductive structure 5 on the surface of the side facing away from the chipset 2 . That is, each chip unit 21 in each chipset 2 can be electrically connected to the logic chip 6 , so that the signals in each chip unit 21 in each chipset 2 can be interconnected with the substrate through the logic chip 6 .
  • the orthographic projection of chipset 2 on carrier board 100 may be within the orthographic projection of logic chip 6 on carrier board 100 . That is, the area of the logic chip 6 may be larger than the area of each chip unit 21 located between the top chip unit 211 and the carrier 100 , and simultaneously larger than the area of the top chip unit 211 .
  • each of the plurality of chipsets 2 can be electrically connected to the logic chip 6 .
  • one logic chip 6 may be formed between the carrier board 100 and each chipset 2 , or a plurality of logic chips 6 spaced apart in a direction parallel to the carrier board 100 may be formed, which is not particularly limited here. .
  • each chip unit 21 in each chipset 2 that is closest to the carrier board 100 can be electrically connected to the same logic chip 6 .
  • each logic chip 6 can be electrically connected to at least one chipset 2 , and different logic chips 6 can be electrically connected to at least one chipset 2 .
  • Chip 6 is connected to a different chipset 2.
  • the conductive structure 5 can also extend from the inside of the chipset 2 into the logic chip 6 , so that the chipset 2 and the logic chip 6 can be electrically connected through the conductive structure 5 .
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • Step S170 After the grinding process, perform a cutting process in the first interval and the second interval between the chipsets 2 to separate the chipsets 2.
  • each chipset 2 can be separated at the first interval and the second interval between adjacent chipsets 2, and after separation, the insulating dielectric layer 3 is retained on the outer periphery of each chipset 2.
  • the insulating dielectric layer 3 on the outer periphery of each separated chip set 2 is defined as an insulating layer 4 .
  • At least part of the insulating dielectric layer 3 may remain in the first interval, that is, at least part of the insulating layer 4 may remain on the sidewall of the bottom chip unit 212 .
  • the method for forming a semiconductor structure of the present disclosure may further include:
  • step S180 after performing the cutting process, the carrier board 100 is removed, and the surface of the logic chip 6 away from the chipset 2 is electrically connected to a substrate 1 .
  • the substrate 1 may include an array area and a peripheral area.
  • the array area and the peripheral area may be adjacently distributed.
  • the peripheral area may surround the periphery of the array area.
  • the array area may be used to form external circuits connected to the chipset 2, and the peripheral area may be used to form other external circuits. circuit.
  • the array area can be a circular area, a rectangular area or an irregular pattern area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area can be an annular area, and can surround the outer periphery of the array area. It can be a circular annular area, a rectangular annular area, or other shaped annular areas, which are not listed here.
  • each chipset 2 , each insulating filling layer 7 , the insulating layer 4 , and the logic chip 6 may be formed on a carrier board 100 and the conductive structure 5. Then the carrier board 100 and the insulating adhesive 200 bonding the carrier board 100 and the logic chip 6 can be removed, and then the conductive structure 5 located on the side surface of the logic chip 6 away from the chipset 2 is exposed. out, as shown in Figure 7.
  • the logic chip 6 can be bonded in the array area of the substrate 1 through the adhesive layer 8 . It should be noted that when the logic chip 6 is bonded to the substrate 1 through the adhesive layer 8, each conductive structure 5 located on the side surface of the logic chip 6 away from the chipset 2 can be connected to the external circuit in the substrate 1 connections to facilitate signal transmission through external circuits. Since each chip unit 21 in the chipset 2 is electrically connected together, and the chip unit 21 closest to the substrate 1 is electrically connected to the logic chip 6 , the chip unit 21 in the chipset 2 can be connected to the logic chip 6 through the chip unit 21 closest to the substrate 1 . The data signals of each chip unit 21 are transmitted to the logic chip 6, and then the data signals are transmitted to the external circuit in the substrate 1 through the logic chip 6.
  • the embodiment of the present disclosure also provides a semiconductor structure.
  • the semiconductor structure can be formed by the method of forming a semiconductor structure in any of the above embodiments. As shown in Figure 8, the semiconductor structure includes a substrate 1, a chipset 2 and an insulating layer. 4, among which:
  • the chipset 2 is provided on one side of the substrate 1 and includes a plurality of chip units 21 stacked in a direction perpendicular to the substrate 1. Among the chip units 21, the chip units 21 on the side close to the substrate 1 are located on the substrate 1. The orthographic projection is within the orthographic projection of the chip unit 21 farthest from the substrate 1 on the substrate 1;
  • the insulating layer 4 covers the outer periphery of the chipset 2 , and the predetermined surface of the chip unit 21 farthest from the substrate 1 is exposed outside the insulating layer 4 .
  • the semiconductor structure of the present disclosure stacks multiple chip units 21 in the vertical direction, which helps to increase the storage capacity.
  • the orthographic projection of each chip unit 21 on the substrate 1 on the side of the chip unit 21 close to the substrate 1 is within the orthographic projection of the chip unit 21 farthest from the substrate 1 on the substrate 1, further increasing
  • the area of the top chip unit 211 is reduced, and the thickness of the insulating layer 4 located on the periphery of the top chip unit 211 is reduced while the overall size of the semiconductor structure remains unchanged, which helps to dissipate heat; on the other hand, since the insulating layer 4 is exposed
  • the predetermined surface of the top chip unit 211 can further increase the heat exchange between the chip unit 21 and the outside world. During the operation of the chip unit 21, the heat dissipation efficiency can be improved and the power consumption can be reduced.
  • the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but is not limited to silicon or For other semiconductor materials, the shape and material of the substrate 1 are not particularly limited here.
  • the substrate 1 may include an array area and a peripheral area.
  • the array area and the peripheral area may be adjacently distributed.
  • the peripheral area may surround the periphery of the array area.
  • the array area may be used to form external circuits connected to the chipset 2, and the peripheral area may be used to form other external circuits. circuit.
  • the array area can be a circular area, a rectangular area or an irregular pattern area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area can be an annular area, and can surround the outer periphery of the array area. It can be a circular annular area, a rectangular annular area, or other shaped annular areas, which are not listed here.
  • the chipset 2 can be formed on one side of the substrate 1 and can be electrically connected to an external circuit in the substrate 1 to facilitate signal transmission.
  • the chipset 2 can be disposed in the array area of the substrate 1 .
  • the chipset 2 may include a plurality of chip units 21 .
  • the chipset 2 can be used in an integrated circuit.
  • it can be a dynamic random access memory (DRAM, Dynamic Random Access Memory) or a static random access memory (static random access memory, SRAM). It can also be used for The core component in dynamic random access memory (DRAM, Dynamic Random Access Memory) or static random access memory (static random access memory, SRAM).
  • multiple chip units 21 can be stacked in a direction perpendicular to the substrate 1 to form a chipset 2.
  • the number of chip units 21 in the chipset 2 may be 2, 3, 4, 5, 6 or 7. Of course, it may also be other numbers, which are not specifically limited here.
  • each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21 and thus facilitates the integration of multiple different chip units 21
  • the data in the chip unit 21 is transmitted to the same chip unit 21, so that the electrical signals in each chip unit 21 in the chipset 2 can be simultaneously transmitted to the substrate 1 through the same chip unit 21, so as to facilitate the connection between each chip unit 21 and an external connection. Circuit connection to achieve signal transmission.
  • each chip unit 21 in the chipset 2 may be spaced apart in a direction perpendicular to the substrate 1 .
  • each chip unit 21 may be equally spaced in a direction perpendicular to the substrate 1 .
  • two adjacent chip units 21 may be spaced apart by a preset distance.
  • the spacing between the chip units 21 may not be completely equal.
  • the spacing between at least two chip units 21 among the plurality of chip units 21 is not equal to the spacing between other two adjacent chip units 21 . .
  • the preset distance may be 10um-150um.
  • the preset distance may be 10um, 40um, 70um, 100um, 130um or 150um.
  • the preset distance may also be other values. I won’t list them all here.
  • the chip unit 21 may have a sheet-like structure, and its shape may be rectangular, circular, elliptical or irregular, which is not specifically limited here.
  • the thickness of each chip unit 21 may be the same or different, and is not specifically limited here.
  • the thickness of the chip unit 21 can be 40um-80um.
  • it can be 40um, 50um, 60um, 70um or 80um.
  • it can also be other thicknesses, which are not listed here.
  • each chip unit 21 in the chipset 2 may have the same thickness.
  • the thickness of each chip unit 21 may be 50 ⁇ m, or the thickness of each chip unit 21 may be 50 ⁇ m. 60um, or the thickness of each chip unit 21 can be 70um; of course, each chip unit 21 can also have other thicknesses, which are not listed here.
  • the chip unit 21 may include a substrate and a circuit module.
  • the circuit module may be disposed on the surface of the substrate. At least part of the chip units 21 of each chip unit 21 has a circuit module in the substrate.
  • the surface of the chip unit 21 may be disposed toward the substrate 1 , and the surface without the circuit module may be oriented toward the side of each chip unit 21 away from the substrate 1 .
  • the surface of the substrate of the chip unit 21 farthest from the substrate 1 may be oriented toward the surface with the circuit module.
  • the substrate may be a wafer.
  • the orthographic projection of each chip unit 21 on the side close to the substrate 1 among the chip units 21 in the chipset 2 on the substrate 1 is the chip unit 21 farthest from the substrate 1 within the orthographic projection on substrate 1.
  • the chip unit 21 farthest from the substrate 1 can be defined as the top chip unit 211
  • the chip unit 21 located between the top chip unit 211 and the substrate 1 can be defined as the bottom chip unit 212.
  • the bottom chip unit 212 may have a first width
  • the top chip unit 211 may have a second width
  • the second width may be greater than the first width. That is, in the chipset 2 , the area of the top chip unit 211 is larger than the area of any other chip unit 21 in the chipset 2 .
  • each chip unit 21 located between the top chip unit 211 and the substrate 1 may be equal or unequal. That is, the areas of each chip unit 21 in the bottom chip unit 212 may be They may or may not be equal, and there is no special limitation here.
  • an insulating filling layer 7 may be provided between adjacent chip units 21 , and the adjacent chip units 21 may be insulated and isolated by the insulating filling layer 7 to avoid occurrence of occurrences between the chip units 21 .
  • the material of the insulating filling layer 7 can be insulating glue or encapsulating glue, which can isolate external water and oxygen through the insulating filling layer 7 and prevent external water and oxygen from entering the inside of the chip unit 21 , thereby preventing external water and oxygen from entering the chip unit 21 . Preventing water and oxygen from corroding the internal structure of the chip unit 21 can extend the service life of the chip unit 21 .
  • the insulating filling layer 7 can fill the gap between adjacent chip units 21 , and the gap between two adjacent chip units 21 can be supported by the insulating filling layer 7 , while , it can also balance the stress between two adjacent chip units 21, reduce the warpage of each chip unit 21, and thereby improve the product yield.
  • the number of chipsets 2 can be multiple. Multiple chipsets 2 can be formed on the same side of the substrate 1 .
  • the orthographic projection of each chipset 2 on the substrate 1 can be located in the array area. For example, each chipset 2 can be distributed at intervals, and can be distributed in an array in the array area of the substrate 1 .
  • adjacent chip units 21 in the same chipset 2 are electrically connected.
  • adjacent chip units 21 can be electrically connected through conductive units 51 . connection, and a plurality of conductive units 51 distributed at intervals can be arranged between adjacent chip units 21. In the direction perpendicular to the substrate 1, the conductive units 51 located in different chip units 21 can be connected to each other, thereby forming a conductive Structure 5.
  • the insulating layer 4 can be formed on the sidewall of the chipset 2 by means of chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the insulating layer 4 can also be formed by other means, which are not repeated here. List one.
  • the material of the insulating layer 4 can be an insulating material, and the chipset 2 can be insulated and isolated through the insulating layer 4 to avoid coupling or short circuit between the chipset 2 and other surrounding structures, thereby improving product yield.
  • each chipset 2 when multiple chipsets 2 are formed on one side of the substrate 1, the side walls of each chipset 2 can be provided with an insulating layer 4, thereby preventing coupling or short circuit between adjacent chipsets 2. Can improve product yield.
  • the ratio of the width of the top chip unit 211 to the thickness of the insulating layer 4 located on the sidewall of the top chip unit 211 may be 5 ⁇ 20, for example In other words, the ratio of the width of the top chip unit 211 to the thickness of the insulating layer 4 located on the side wall of the top chip unit 211 is 5, 10, 15 or 20. Of course, it can also be other ratios, and no examples are given here. Lift.
  • the thickness of the insulating layer 4 located on the sidewalls of the top chip unit 211 is no greater than that located on the bottom
  • the thickness of the insulating layer 4 located on the sidewall of the top chip unit 211 may be greater than or equal to 50 microns and less than or equal to 100 microns. Compared with 200 microns in the prior art, the thickness of the insulating layer 4 located on the top chip unit 211 in the present disclosure The thickness of the insulating layer 4 on the side wall of 211 is greatly reduced.
  • the thickness of the insulating layer 4 located on the side walls of the top chip unit 211 may be 50 microns, 60 microns, 70 microns, 80 microns, 90 microns or 100 microns.
  • the thickness of the insulating layer 4 located on the side walls of the top chip unit 211 The thickness of the insulating layer 4 can also be other, which will not be listed here.
  • each chip unit 21 between the top chip unit 211 and the substrate 1 can be aligned at both ends, that is, each chip unit 21 in the bottom chip unit 212 can be aligned at both ends. Aligned, and the thickness of the insulating layer 4 located around the periphery of each chip unit 21 in the bottom chip unit 212 can be equal, and the thickness of the insulating layer 4 located around the periphery of each chip unit 21 in the bottom chip unit 212 can be greater than that located at the top chip unit 211 The thickness of the chip unit 21 on the periphery.
  • the semiconductor structure of the present disclosure may also include a logic chip 6.
  • the logic chip 6 may be formed between the substrate 1 and the chipset 2, and may be formed by bonding.
  • Layer 8 bonds the logic chip 6 to the substrate 1.
  • the material of the adhesive layer 8 can be non-conductive glue, UV glue, etc.
  • the side surface of the logic chip 6 facing away from the chipset 2 has a conductive structure 5, that is, each Each chip unit 21 in the chipset 2 can be electrically connected to the logic chip 6 , so that the signals in each chip unit 21 in the chipset 2 are subsequently interconnected with the substrate 1 through the logic chip 6 .
  • the logic chip 6 can be electrically connected to the chip unit 21 in the chipset 2 that is closest to the substrate 1, because each chip unit 21 in the chipset 2 is electrically connected to each other and is far from the substrate 1. 1
  • the nearest chip unit 21 is electrically connected to the logic chip 6, and the data signals of each chip unit 21 in the chipset 2 can be transmitted to the logic chip 6 through the chip unit 21 closest to the substrate 1, and then the logic chip 6 The data signal is transmitted to the external circuit in the substrate 1.
  • the orthographic projection of the chipset 2 on the substrate 1 may be within the orthographic projection of the logic chip 6 on the substrate 1 . That is, the area of the logic chip 6 may be larger than the area of each chip unit 21 located between the top chip unit 211 and the substrate 1 , and simultaneously larger than the area of the top chip unit 211 .
  • each of the plurality of chipsets 2 can be electrically connected to the logic chip 6 .
  • one logic chip 6 may be formed between the substrate 1 and each chipset 2 , or a plurality of logic chips 6 spaced apart in a direction parallel to the substrate 1 may be formed, which is not specifically limited here.
  • each chip unit 21 in each chipset 2 that is closest to the substrate 1 can be electrically connected to the same logic chip 6 .
  • each logic chip 6 When a plurality of logic chips 6 are formed between the substrate 1 and each chipset 2 and are spaced apart in a direction parallel to the substrate 1, each logic chip 6 can be electrically connected to at least one chipset 2, and different logic chips 6 The connected chipset 2 is different.
  • the conductive structure 5 can also extend from the inside of the chipset 2 into the logic chip 6 , so that the chipset 2 and the logic chip 6 can be electrically connected through the conductive structure 5 .
  • Embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments.
  • a memory which may include the semiconductor structure in any of the above embodiments.
  • the specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method of forming the semiconductor structure. , which will not be described again here.
  • the memory can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • other storage devices may also be used, which are not listed here.

Abstract

本公开是关于半导体技术领域，涉及一种半导体结构及其形成方法、存储器，本公开的形成方法包括：提供载板；在载板的一侧形成芯片组，芯片组包括多个沿垂直于载板的方向堆叠的芯片单元，各芯片单元中靠近载板的一侧的各芯片单元在载板上的正投影在距离载板最远的芯片单元在载板上的正投影之内；形成覆盖芯片组的绝缘介质层；进行研磨处理，以将距离载板最远的芯片单元的预定表面暴露于绝缘介质层外。本公开的形成方法可减小出现研磨不均的概率，避免在研磨过程中顶部芯片的表面产生划痕，改善产品外观。 (图1)

Description

半导体结构及其形成方法、存储器
交叉引用
本公开要求于2022年9月5日提交的申请号为202211080235.7名称为“半导体结构及其形成方法、存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体结构及其形成方法、存储器。
背景技术
存储器因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。为了提高存储器的存储容量，通常需要将多个芯片单元叠加在一起。
在将芯片单元叠加完成后，需要在各芯片单元的表面及外周布设绝缘层，在形成绝缘层后，需通过研磨的方式对绝缘层的表面进行研磨，进而露出位于顶部的芯片单元的表面，然而，在研磨过程中易对芯片单元的表面造成损伤，进而影响产品外观。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种半导体结构及其形成方法、存储器，可减小出现研磨不均的概率，避免在研磨过程中顶部芯片的表面产生划痕，改善产品外观。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供载板；
在所述载板的一侧形成芯片组，所述芯片组包括多个沿垂直于所述载板的方向堆叠的芯片单元，各所述芯片单元中靠近所述载板的一侧的各所述芯片单元在所述载板上的正投影在距离所述载板最远的所述芯片单元在所述载板上的正投影之内；
形成覆盖所述芯片组的绝缘介质层；
进行研磨处理，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外。
在本公开的一种示例性实施例中，所述芯片组的数量为多个，各所述芯片组间 隔分布，所述绝缘介质层填满各所述芯片组之间的间隙，所述芯片组包括底部芯片单元和顶部芯片单元，在平行于所述载板的方向上，相邻的所述底部芯片单元之间具有第一间隔，相邻的所述顶部芯片单元之间具有第二间隔，所述第二间隔的宽度小于所述第一间隔的宽度。
在本公开的一种示例性实施例中，在平行于所述载板的方向上，所述底部芯片单元具有第一宽度，所述顶部芯片单元具有第二宽度，所述第二宽度大于所述第一宽度。
在本公开的一种示例性实施例中，所述进行研磨处理，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外，包括：
研磨去掉第一目标厚度的所述绝缘介质层，以露出所述顶部芯片单元的顶表面；
继续研磨去掉第二目标厚度的所述顶部芯片单元与所述绝缘介质层，以露出所述顶部芯片单元的所述预定表面，其中，所述第二目标厚度不大于所述第一目标厚度。
在本公开的一种示例性实施例中，所述芯片单元包括衬底及形成于所述衬底表面的电路模块，所述顶部芯片单元中形成有所述电路模块的表面朝向所述载板。
在本公开的一种示例性实施例中，所述形成方法还包括：
在所述芯片组与所述载板之间形成逻辑芯片，所述芯片组在所述载板上的正投影在所述逻辑芯片在所述载板上的正投影之内。
在本公开的一种示例性实施例中，所述形成方法还包括：
在执行所述切割处理后，去除所述载板，并将所述逻辑芯片背离所述芯片组的表面与一基板电连接。
在本公开的一种示例性实施例中，所述形成方法还包括：
在所述研磨处理后，在各所述芯片组之间的所述第一间隔和所述第二间隔中执行切割处理，以分离各所述芯片组。
在本公开的一种示例性实施例中，在执行所述切割处理的过程中，所述第一间隔中至少保留部分所述绝缘介质层。
根据本公开的一个方面，提供一种半导体结构，包括：
基板；
芯片组，设于所述基板的一侧，且包括多个沿垂直于所述基板的方向堆叠的芯片单元，各所述芯片单元中靠近所述基板的一侧的各所述芯片单元在所述基板上的正投影在距离所述基板最远的所述芯片单元在所述基板上的正投影之内；
绝缘层，包覆于所述芯片组的外周，且距离所述基板最远的所述芯片单元的预定表面暴露于所述绝缘层外。
在本公开的一种示例性实施例中，所述芯片组包括底部芯片单元和顶部芯片单元，在平行于所述基板的方向上，位于所述顶部芯片单元的侧壁上的所述绝缘层的 厚度不大于位于所述底部芯片单元的侧壁上的所述绝缘层的厚度。
在本公开的一种示例性实施例中，在平行于所述基板的方向上，所述底部芯片单元具有第一宽度，所述顶部芯片单元具有第二宽度，所述第二宽度大于所述第一宽度。
在本公开的一种示例性实施例中，所述芯片单元包括衬底及形成于所述衬底表面的电路模块，所述顶部芯片单元中形成有所述电路模块的表面朝向所述基板。
在本公开的一种示例性实施例中，所述半导体结构还包括：
逻辑芯片，设于所述基板与所述芯片组之间，所述芯片组在所述衬底上的正投影在所述逻辑芯片在所述衬底上的正投影之内。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述的半导体结构。
本公开的半导体结构及其形成方法、存储器，一方面，将多个芯片单元沿竖直方向堆叠设置，有助于提高存储容量。另一方面，由于芯片单元中靠近载板的一侧的各芯片单元在载板上的正投影在距离载板最远的芯片单元在载板上的正投影之内，进而增大了顶部芯片单元的面积，在半导体结构整体尺寸不变的情况下，减小了位于顶部芯片单元外周的绝缘层的厚度，进而减小研磨过程中绝缘介质层的占比，降低由于绝缘介质层与芯片单元表面硬度不同而导致研磨不均的概率，可降低在研磨过程中顶部芯片单元的表面产生划痕或裂纹的概率，改善产品外观。再一方面，由于经过研磨后形成的结构露出了顶部芯片单元的预定表面，可增加芯片单元与外界的热交换，在芯片单元工作过程中，可提高散热效率，降低功耗。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施方式中半导体结构的形成方法的示意图；
图2为本公开一实施方式中半导体结构的示意图；
图3为本公开一实施方式中半导体结构的俯视图；
图4为公开实施方式中导电单元的示意图；
图5为公开实施方式中完成步骤S130后的示意图；
图6为公开实施方式中研磨区域的示意图；
图7为公开实施方式中导电结构的示意图；
图8为本公开一实施方式中半导体结构的示意图。
附图标记说明：
1、基板；2、芯片组；21、芯片单元；211、顶部芯片单元；212、底部芯片单元；3、绝缘介质层；4、绝缘层；5、导电结构；51、导电单元；6、逻辑芯片；7、绝缘填充层；8、粘接层；100、载板；200、绝缘粘胶。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本公开实施方式提供了一种半导体结构的形成方法，图1示出了本公开的半导体结构的形成方法的示意图，参见图1所示，该形成方法可包括步骤S110-步骤S140，其中：
步骤S110，提供载板；
步骤S120，在所述载板的一侧形成芯片组，所述芯片组包括多个沿垂直于所述载板的方向堆叠的芯片单元，各所述芯片单元中靠近所述载板的一侧的各所述芯片单元在所述载板上的正投影在距离所述载板最远的所述芯片单元在所述载板上的正投影之内；
步骤S130，形成覆盖所述芯片组的绝缘介质层；
步骤S140，进行研磨处理，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外。
本公开的半导体结构的形成方法，一方面，将多个芯片单元21沿竖直方向堆叠设置，有助于提高存储容量。另一方面，由于芯片单元21中靠近载板100的一侧的各芯片单元21在载板100上的正投影在距离载板100最远的芯片单元21在载板100 上的正投影之内，进而增大了顶部芯片单元211的面积，在半导体结构整体尺寸不变的情况下，减小了位于顶部芯片单元211外周的绝缘层4的厚度，进而减小研磨过程中绝缘介质层3的占比，降低由于绝缘介质层3与芯片单元21表面硬度不同而导致研磨不均的概率，可降低在研磨过程中顶部芯片单元211的表面产生划痕或裂纹的概率，改善产品外观。再一方面，由于经过研磨后形成的结构露出了顶部芯片单元211的预定表面，可增加芯片单元21与外界的热交换，在芯片单元21工作过程中，可提高散热效率，降低功耗。
下面对本公开的半导体结构的形成方法的各步骤及其细节进行详细说明：
如图1所示，在步骤S110中，提供载板。
图2示出了本公开一实施方式中半导体结构的示意图，参见图2所示，载板100可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可为硅，但是不限于硅或其他半导体材料，在此不对载板100的形状及材料做特殊限定。
如图1所示，在步骤S120中，在所述载板的一侧形成芯片组，所述芯片组包括多个沿垂直于所述载板的方向堆叠的芯片单元，各所述芯片单元中靠近所述载板的一侧的各所述芯片单元在所述载板上的正投影在距离所述载板最远的所述芯片单元在所述载板上的正投影之内。
继续参见图2所示，芯片组2可形成于载板100一侧，芯片组2可包括多个芯片单元21。该芯片组2可用于集成电路中，举例而言，其可以是动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random access memory，SRAM)，也可以是用于动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random access memory，SRAM)中的核心部件。在本公开的一些实施例中，为了在保证存储容量的同时减小DRAM或SRAM尺寸，可将多个芯片单元21沿垂直与载板100的方向堆叠设置，以形成芯片组2，举例而言，芯片组2中芯片单元21的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，芯片组2中的各芯片单元21之间均可电性连接，有助于多个芯片单元21中的数据互相传输，进而便于将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，便于后续通过同一个芯片单元21将芯片组2中的各芯片单元21中的电信号同时传递至基板中，以便于将各芯片单元21与基板中的外接电路连接，进而实现信号传输。
在本公开的一些实施方式中，芯片组2中的各芯片单元21均可沿垂直于载板100的方向间隔分布。举例而言，各芯片单元21可沿垂直于载板100的方向等间距间隔分布，例如，相邻两个芯片单元21之间可间隔开预设距离。当然，各芯片单元21之间的间距也可不完全相等，例如，多个芯片单元21中至少有两个芯片单元21 之间的间距与其他的相邻两个芯片单元21之间的间距不相等。
在本公开的一些实施方式中，预设距离可为10um～150um，举例而言，预设距离可为10um、40um、70um、100um、130um或150um，当然，预设距离还可以是其他数值，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可呈片状结构，其形状可以是矩形、圆形、椭圆形或不规则图形，在此不做特殊限定。各芯片单元21的厚度可以相同，也可以不同，在此不做特殊限定。举例而言，芯片单元21的厚度可以是40um～80um，举例而言，其可以是40um、50um、60um、70um或80um，当然，也可以是其他厚度，在此不再一一列举。
在本公开的一些实施方式中，芯片组2中的各芯片单元21可具有相同的厚度，举例而言，各芯片单元21的厚度均可为50um，或者，各芯片单元21的厚度均可为60um，又或者，各芯片单元21的厚度均可为70um；当然，各芯片单元21也均可为其他厚度，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可包括衬底及电路模块，电路模块可设于衬底的表面，各芯片单元21中至少部分芯片单元21的衬底中具有电路模块的表面可朝向载板100设置，其未设置电路模块的表面可朝向各芯片单元21远离载板100的一侧，例如，距离载板100最远的芯片单元21的衬底中具有电路模块的表面可朝向载板100设置。举例而言，衬底可为晶圆。
在本公开的一种示例性实施方式中，芯片组2中的各芯片单元21中靠近载板100的一侧的各芯片单元21在载板100上的正投影在距离载板100最远的芯片单元21在载板100上的正投影之内。为了便于区分，可将距离载板100最远的芯片单元21定义为顶部芯片单元211，将位于顶部芯片单元211与载板100之间的芯片单元21即为底部芯片单元212，底部芯片单元212的数量可以是一个，也可以是多个，在此不做特殊限定。在平行于载板100的方向上，底部芯片单元212可具有第一宽度，顶部芯片单元211可具有第二宽度，第二宽度可大于第一宽度。即，在芯片组2中，顶部芯片单元211的面积大于芯片组2中其他任一一芯片单元21的面积。
需要说明的是，芯片组2中，位于顶部芯片单元211与载板100之间的各芯片单元21的面积可以相等，也可以不相等。即，底部芯片单元212中的各芯片单元21的面积可以相等，也可以不相等，在此不做特殊限定。
在本公开的一些实施方式中，相邻的芯片单元21之间可设置有绝缘填充层7，可通过绝缘填充层7对相邻的芯片单元21进行绝缘隔离，避免各芯片单元21之间发生信号串扰或耦合。
在本公开的一种示例性实施方式中，绝缘填充层7的材料可为绝缘胶或封装胶，可通过绝缘填充层7隔绝外界水、氧，防止外界水、氧进入芯片单元21内部，进而避免水、氧侵蚀芯片单元21的内部结构，可延长芯片单元21的使用寿命。
在本公开的一些实施方式中，绝缘填充层7可填满相邻的芯片单元21之间的间隙，可通过绝缘填充层7对相邻的两个芯片单元21之间的空隙进行支撑，同时，还可平衡相邻两个芯片单元21之间的应力，可减小各芯片单元21的翘曲，进而提高产品良率。
图3示出了本公开一实施方式中半导体结构的俯视图，参见图2及图3所示，芯片组2的数量可为多个，多个芯片组2均可形成于载板100的同一侧，各芯片组2在载板100上的正投影均可位于阵列区内。举例而言，各芯片组2可间隔分布，并可呈阵列分布于载板100的阵列区内。
在本公开的一些实施方式中，参见图4所示，同一芯片组2中相邻的芯片单元21之间均电连接，举例而言，相邻的芯片单元21之间可通过导电单元51电连接，且相邻的芯片单元21之间可布设多个间隔分布的导电单元51，在垂直于载板100的方向上，位于不同的芯片单元21中的各导电单元51可相互连接，进而形成导电结构5。
需要说明的是，参见图2所示，当相邻的芯片单元21之间形成有绝缘填充层7时，导电结构5可贯穿各绝缘填充层7。
如图1所示，在步骤S130中，形成覆盖所述芯片组的绝缘介质层。
参见图3及图5所示，可采用化学气相沉积、物理气相沉积或原子层沉积等方式在芯片组2的侧壁及顶部同时形成绝缘介质层3，当然，也可通过其他方式形成绝缘介质层3，在此不再一一列举。绝缘介质层3的材料可为绝缘材料，可通过绝缘介质层3对芯片组2进行绝缘隔离，以避免芯片组2与周围其他结构之间产生耦合或短路，可提高产品良率。
需要说明的是，当载板100的一侧形成有多个芯片组2时，绝缘介质层3可填满各芯片组2之间的间隙，进而避免相邻的芯片组2之间产生耦合或短路，可提高产品良率。
在本公开的一种示例性实施方式中，在平行于载板100的方向上，相邻的底部芯片单元212之间可具有第一间隔，同时，相邻的顶部芯片单元211之间可具有第二间隔，第二间隔的宽度可小于第一间隔的宽度。例如，第一间隔的宽度可大于或等于200微米，第二间隔的宽度可大于或等于50微米，小于或等于100微米。
如图1所示，在步骤S140中，进行研磨，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外。
可采用研磨工艺对绝缘介质层3进行研磨，研磨后的绝缘介质层3可露出顶部芯片单元211的预定表面，以便于增加芯片组2与外界的热交换，在芯片单元21工作过程中，可提高散热效率，降低功耗。
在研磨过程中，由于芯片组2中的顶部芯片单元211的面积大于其他芯片单元21的面积，在半导体结构整体尺寸不变的情况下，位于顶部芯片单元211外周的绝 缘介质层3的厚度较小，进而使得研磨过程中绝缘介质层3的占比减小，可降低由于绝缘介质层3与芯片单元21表面硬度不同而导致研磨不均的概率，可降低在研磨过程中顶部芯片单元211的表面产生划痕或裂纹的概率，进而改善产品外观。
在本公开的一些实施方式中，在平行于载板100的方向上，顶部芯片单元211的宽度与位于顶部芯片单元211的侧壁上的绝缘介质层3的厚度的比值可为5～20，举例而言，顶部芯片单元211的宽度与位于顶部芯片单元211的侧壁上的绝缘介质层3的厚度的比值为5、10、15或20，当然，也可以是其他比值，在此不再一一例举。
在本公开的一些实施方式中，位于顶部芯片单元211的侧壁上的绝缘介质层3的厚度可大于或等于50微米，小于或等于100微米。举例而言，位于顶部芯片单元211的侧壁上的绝缘介质层3的厚度可为50微米、60微米、70微米、80微米、90微米或100微米，当然，位于顶部芯片单元211的侧壁上的绝缘介质层3的厚度还可为其他，在此不再一一列举。
需要说明的是，在垂直于载板100的方向上，顶部芯片单元211与载板100之间的各芯片单元21均可两端对齐，即，底部芯片单元212中的各芯片单元21均可两端对齐，且位于底部芯片单元212中的各芯片单元21外周的绝缘介质层3的厚度均可相等，且位于底部芯片单元212中的各芯片单元21外周的绝缘介质层3的厚度可大于位于顶部芯片单元211外周的芯片单元21的厚度。
需要说明的是，由于在对绝缘介质层3进行研磨的过程中，只在绝缘介质层3的厚度方向上进行了减薄，未在平行于载板100的方向上进行处理，当芯片组2的数量为多个时，最终形成的绝缘介质层3在平行于载板100的方向上可填满各芯片组2之间的间隙。且在研磨过程中，可同时对绝缘介质层3及各芯片组2中的各顶部芯片单元211的衬底进行研磨，进而可通过同一次研磨工艺，同时露出各芯片组2中距离载板100最远的芯片单元21背离载板100的表面。
在本公开的一些实施方式中，进行研磨处理，以将距离载板100最远的芯片单元21的预定表面暴露于绝缘介质层3外(即，步骤S140)可包括：
步骤S210，研磨去掉第一目标厚度的所述绝缘介质层3，以露出所述顶部芯片单元211的顶表面。
可通过研磨工艺去除第一目标厚度的绝缘介质层3，第一目标厚度可等于绝缘介质层3覆盖在顶部芯片单元211表面的厚度。在研磨去除第一目标厚度的绝缘介质层3后，可露出顶部芯片单元211的顶表面，即，可露出顶部芯片单元211的衬底中远离电路模块的表面。
举例而言，第一目标厚度可为100um～150um，例如，第一目标厚度可为100um、110um、120um、130um、140um或150um，当然，第一目标厚度也可为其他厚度，在此不再一一例举。
步骤S220，继续研磨去掉第二目标厚度的所述顶部芯片单元211与所述绝缘介质层3，以露出所述顶部芯片单元211的所述预定表面，其中，所述第二目标厚度不大于所述第一目标厚度。
可对顶部芯片单元211及绝缘介质层3继续进行研磨，进而对顶部芯片单元211中的衬底中背离电路模块的表面进行减薄处理，以便于减小芯片组2的厚度，进一步增大芯片组2在工作过程中的散热效率，进而进一步降低功耗。
举例而言，在研磨过程中，可去掉第二目标厚度的顶部芯片单元211及绝缘介质层3，第二目标厚度可小于顶部芯片单元211的衬底的厚度，且第二目标厚度不大于第一目标厚度，举例而言，第二目标厚度可为100nm～140nm，例如，第二目标厚度可为100nm、110nm、120nm、130nm或140nm，当然，第二目标厚度也可为其他厚度，在此不再一一列举。
在本公开的一些实施方式中，可采用研磨设备对位于顶部芯片单元211表面的绝缘介质层3及顶部芯片单元211的衬底同时进行研磨，其研磨的区域如图6中虚线框所示，在此过程中，由于位于顶部芯片单元211外周的绝缘介质层3的厚度较小，进而使得研磨过程中绝缘介质层3的占比较小，在研磨过程中，可使用与衬底的硬度较匹配的研磨头进行研磨，可降低在研磨过程中顶部芯片单元211的表面产生划痕或裂纹的概率，有助于改善产品外观。
在本公开的一种实例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S160，在所述芯片组2与所述载板100之间形成逻辑芯片6，所述芯片组2在所述载板100上的正投影在所述逻辑芯片6在所述载板100上的正投影之内。
逻辑芯片6可形成于载板100与芯片组2之间，可通过绝缘粘胶200将逻辑芯片6粘接在载板100上，绝缘粘胶200的材料可为非导电胶、UV胶等。参见图7所示，逻辑芯片6背离芯片组2的一侧表面上具有导电结构5。即各芯片组2中的各芯片单元21均可与逻辑芯片6电连接，以便于后续通过逻辑芯片6将各芯片组2中的各芯片单元21中的信号与基板进行互连。
在本公开的一些实施方式中，芯片组2在载板100上的正投影可在逻辑芯片6在载板100上的正投影之内。即，逻辑芯片6的面积可大于位于顶部芯片单元211与载板100之间的各芯片单元21的面积，同时大于顶部芯片单元211的面积。
当芯片组2的数量为多个时，多个芯片组2均可与逻辑芯片6电连接。需要说明的是，载板100与各芯片组2之间可形成有一个逻辑芯片6，也可形成有多个沿平行于载板100的方向间隔分布的逻辑芯片6，在此不做特殊限定。当载板100与各芯片组2之间形成有一个逻辑芯片6时，各芯片组2中距离载板100最近的各芯片单元21可与同一逻辑芯片6电连接。当载板100与各芯片组2之间形成有多个沿平行于载板100的方向间隔分布的逻辑芯片6时，每个逻辑芯片6可至少与一个芯片组2电连接，且不同的逻辑芯片6连接的芯片组2不同。
在本公开的一种示例性实施方式中，导电结构5还可由芯片组2的内部延伸至逻辑芯片6中，进而使得芯片组2与逻辑芯片6之间可通过导电结构5实现电连接。
在本公开的一种示例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S170，在所述研磨处理后，在各所述芯片组2之间的所述第一间隔和所述第二间隔中执行切割处理，以分离各所述芯片组2。
在对绝缘介质层3及顶部芯片单元211进行研磨处理后，可对相邻的芯片组2进行切割，以将各芯片组2分离。举例而言，可在相邻的芯片组2之间的第一间隔和第二间隔处对各芯片组2进行分离，且在分离后各芯片组2的外周均保留有绝缘介质层3，可将分离后的各芯片组2的外周的绝缘介质层3定义为绝缘层4。
需要说明的是，在执行切割处理的过程中，第一间隔中可至少保留部分绝缘介质层3，即，底部芯片单元212的侧壁上可至少保留部分绝缘层4。
在本公开的一种示例性实施方式中，参见图8所示，本公开的半导体结构的形成方法还可包括：
步骤S180，在执行所述切割处理后，去除所述载板100，并将所述逻辑芯片6背离所述芯片组2的表面与一基板1电连接。
基板1可包括阵列区及外围区，阵列区与外围区可邻接分布，外围区可环绕于阵列区的外周，阵列区可用于形成与芯片组2连接的外接电路，外围区可用于形成其他外接电路。举例而言，阵列区可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区可为环形区域，并可环绕于阵列区的外周，其可以是圆环区域、矩形环区域或其他形状的环形区域，在此不再一一列举。
在本公开的一种示例性实施方式中，在将逻辑芯片6与基板1连接之前，可先在一载板100上形成各芯片组2、各绝缘填充层7、绝缘层4、逻辑芯片6及导电结构5，随后可去除载板100及将载板100与逻辑芯片6粘接在一起的绝缘粘胶200，进而将位于逻辑芯片6背离芯片组2的一侧表面上的导电结构5暴露出来，如图7所示。
在本公开的一些实施方式中，参见图8所示，可通过粘接层8将逻辑芯片6粘接在基板1的阵列区内。需要说明的是，在通过粘接层8将逻辑芯片6粘接在基板1上时，可使位于逻辑芯片6背离芯片组2的一侧表面上的各导电结构5与基板1中的外接电路连接，以便于通过外接电路进行信号传输。由于芯片组2中的各芯片单元21之间均电连接在一起，且距离基板1最近的芯片单元21与逻辑芯片6电连接，进而可通过距离基板1最近的芯片单元21将芯片组2中的各芯片单元21的数据信号均传输至逻辑芯片6，再通过逻辑芯片6将数据信号传输至基板1中的外接电路中。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体结构的形成方 法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式，还提供了一种半导体结构，该半导体结构可由上述任一实施方式中的半导体结构的形成方法形成，如图8所示，该半导体结构包括基板1、芯片组2及绝缘层4，其中：
芯片组2，设于基板1的一侧，且包括多个沿垂直于基板1的方向堆叠的芯片单元21，各芯片单元21中靠近基板1的一侧的各芯片单元21在基板1上的正投影在距离基板1最远的芯片单元21在基板1上的正投影之内；
绝缘层4，包覆于芯片组2的外周，且距离基板1最远的芯片单元21的预定表面暴露于绝缘层4外。
本公开的半导体结构，一方面，将多个芯片单元21沿竖直方向堆叠设置，有助于提高存储容量。另一方面，由于芯片单元21中靠近基板1的一侧的各芯片单元21在基板1上的正投影在距离基板1最远的芯片单元21在基板1上的正投影之内，进而增大了顶部芯片单元211的面积，在半导体结构整体尺寸不变的情况下，减小了位于顶部芯片单元211外周的绝缘层4的厚度，有助于散热；再一方面，由于绝缘层4露出了顶部芯片单元211的预定表面，可进一步增加芯片单元21与外界的热交换，在芯片单元21工作过程中，可提高散热效率，降低功耗。
下面对本公开的半导体结构的各部分的具体细节进行详细说明：
参见图8所示，基板1可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可为硅，但是不限于硅或其他半导体材料，在此不对基板1的形状及材料做特殊限定。
基板1可包括阵列区及外围区，阵列区与外围区可邻接分布，外围区可环绕于阵列区的外周，阵列区可用于形成与芯片组2连接的外接电路，外围区可用于形成其他外接电路。举例而言，阵列区可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区可为环形区域，并可环绕于阵列区的外周，其可以是圆环区域、矩形环区域或其他形状的环形区域，在此不再一一列举。
继续参见图8所示，芯片组2可形成于基板1一侧，并可与基板1中的外接电路电连接，以便于实现信号传输。例如，芯片组2可设于基板1的阵列区内。芯片组2可包括多个芯片单元21。该芯片组2可用于集成电路中，举例而言，其可以是动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random access memory，SRAM)，也可以是用于动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random  access memory，SRAM)中的核心部件。在本公开的一些实施例中，为了在保证存储容量的同时减小DRAM或SRAM尺寸，可将多个芯片单元21沿垂直与基板1的方向堆叠设置，以形成芯片组2，举例而言，芯片组2中芯片单元21的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，芯片组2中的各芯片单元21之间均可电性连接，有助于多个芯片单元21中的数据互相传输，进而便于将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，便于后续通过同一个芯片单元21将芯片组2中的各芯片单元21中的电信号同时传递至基板1中，以便于将各芯片单元21与外接电路连接，进而实现信号传输。
在本公开的一些实施方式中，芯片组2中的各芯片单元21均可沿垂直于基板1的方向间隔分布。举例而言，各芯片单元21可沿垂直于基板1的方向等间距间隔分布，例如，相邻两个芯片单元21之间可间隔开预设距离。当然，各芯片单元21之间的间距也可不完全相等，例如，多个芯片单元21中至少有两个芯片单元21之间的间距与其他的相邻两个芯片单元21之间的间距不相等。
在本公开的一些实施方式中，预设距离可为10um～150um，举例而言，预设距离可为10um、40um、70um、100um、130um或150um，当然，预设距离还可以是其他数值，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可呈片状结构，其形状可以是矩形、圆形、椭圆形或不规则图形，在此不做特殊限定。各芯片单元21的厚度可以相同，也可以不同，在此不做特殊限定。举例而言，芯片单元21的厚度可以是40um～80um，举例而言，其可以是40um、50um、60um、70um或80um，当然，也可以是其他厚度，在此不再一一列举。
在本公开的一些实施方式中，芯片组2中的各芯片单元21可具有相同的厚度，举例而言，各芯片单元21的厚度均可为50um，或者，各芯片单元21的厚度均可为60um，又或者，各芯片单元21的厚度均可为70um；当然，各芯片单元21也均可为其他厚度，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可包括衬底及电路模块，电路模块可设于衬底的表面，各芯片单元21中至少部分芯片单元21的衬底中具有电路模块的表面可朝向基板1设置，其未设置电路模块的表面可朝向各芯片单元21远离基板1的一侧，例如，距离基板1最远的芯片单元21的衬底中具有电路模块的表面可朝向基板1设置。举例而言，衬底可为晶圆。
在本公开的一种示例性实施方式中，芯片组2中的各芯片单元21中靠近基板1的一侧的各芯片单元21在基板1上的正投影在距离基板1最远的芯片单元21在基板1上的正投影之内。为了便于区分，可将距离基板1最远的芯片单元21定义为顶 部芯片单元211，将位于顶部芯片单元211与基板1之间的芯片单元21即为底部芯片单元212。在平行于基板1的方向上，底部芯片单元212可具有第一宽度，顶部芯片单元211可具有第二宽度，第二宽度可大于第一宽度。即，在芯片组2中，顶部芯片单元211的面积大于芯片组2中其他任一一芯片单元21的面积。
需要说明的是，芯片组2中，位于顶部芯片单元211与基板1之间的各芯片单元21的面积可以相等，也可以不相等，即，底部芯片单元212中的各芯片单元21的面积可以相等，也可以不相等，在此不做特殊限定。
在本公开的一些实施方式中，相邻的芯片单元21之间可设置有绝缘填充层7，可通过绝缘填充层7对相邻的芯片单元21进行绝缘隔离，避免各芯片单元21之间发生信号串扰或耦合。
在本公开的一种示例性实施方式中，绝缘填充层7的材料可为绝缘胶或封装胶，可通过绝缘填充层7隔绝外界水、氧，防止外界水、氧进入芯片单元21内部，进而避免水、氧侵蚀芯片单元21的内部结构，可延长芯片单元21的使用寿命。
在本公开的一些实施方式中，绝缘填充层7可填满相邻的芯片单元21之间的间隙，可通过绝缘填充层7对相邻的两个芯片单元21之间的空隙进行支撑，同时，还可平衡相邻两个芯片单元21之间的应力，可减小各芯片单元21的翘曲，进而提高产品良率。
芯片组2的数量可为多个，多个芯片组2均可形成于基板1的同一侧，各芯片组2在基板1上的正投影均可位于阵列区内。举例而言，各芯片组2可间隔分布，并可呈阵列分布于基板1的阵列区内。
在本公开的一些实施方式中，参见图4所示，同一芯片组2中相邻的芯片单元21之间均电连接，举例而言，相邻的芯片单元21之间可通过导电单元51电连接，且相邻的芯片单元21之间可布设多个间隔分布的导电单元51，在垂直于基板1的方向上，位于不同的芯片单元21中的各导电单元51可相互连接，进而形成导电结构5。
需要说明的是，参见图8所示，当相邻的芯片单元21之间形成有绝缘填充层7时，导电结构5可贯穿各绝缘填充层7。
参见图8所示，可采用化学气相沉积、物理气相沉积或原子层沉积等方式在芯片组2的侧壁形成绝缘层4，当然，也可通过其他方式形成绝缘层4，在此不再一一列举。绝缘层4的材料可为绝缘材料，可通过绝缘层4对芯片组2进行绝缘隔离，以避免芯片组2与周围其他结构之间产生耦合或短路，可提高产品良率。
需要说明的是，当基板1的一侧形成有多个芯片组2时，各芯片组2的侧壁均可设有绝缘层4，进而避免相邻的芯片组2之间产生耦合或短路，可提高产品良率。
在本公开的一些实施方式中，在平行于基板1的方向上，顶部芯片单元211的宽度与位于顶部芯片单元211的侧壁上的绝缘层4的厚度的比值可为5～20，举例而 言，顶部芯片单元211的宽度与位于顶部芯片单元211的侧壁上的绝缘层4的厚度的比值为5、10、15或20，当然，也可以是其他比值，在此不再一一例举。
在本公开的一些实施方式中，在本公开的一种示例性实施方式中，在平行于所述基板的方向上，位于顶部芯片单元211的侧壁上的绝缘层4的厚度不大于位于底部芯片单元212的侧壁上的绝缘层4的厚度。举例而言，位于顶部芯片单元211的侧壁上的绝缘层4的厚度可大于或等于50微米，小于或等于100微米，相比于现有技术中的200微米，本公开中位于顶部芯片单元211侧壁上的绝缘层4的厚度大大减小。举例而言，位于顶部芯片单元211的侧壁上的绝缘层4的厚度可为50微米、60微米、70微米、80微米、90微米或100微米，当然，位于顶部芯片单元211的侧壁上的绝缘层4的厚度还可为其他，在此不再一一列举。
需要说明的是，在垂直于基板1的方向上，顶部芯片单元211与基板1之间的各芯片单元21均可两端对齐，即，底部芯片单元212中的各芯片单元21均可两端对齐，且位于底部芯片单元212中的各芯片单元21外周的绝缘层4的厚度均可相等，且位于底部芯片单元212中的各芯片单元21外周的绝缘层4的厚度可大于位于顶部芯片单元211外周的芯片单元21的厚度。
在本公开的一些实施方式中，本公开的半导体结构还可包括逻辑芯片6，继续参见图7及图8所示，逻辑芯片6可形成于基板1与芯片组2之间，可通过粘接层8将逻辑芯片6粘接在基板1上，粘接层8的材料可为非导电胶、UV胶等，逻辑芯片6背离所述芯片组2的一侧表面上具有导电结构5，即各芯片组2中的各芯片单元21均可与逻辑芯片6电连接，以便后续通过逻辑芯片6将各芯片组2中的各芯片单元21中的信号与基板1进行互连。
在本公开的一些实施方式中，逻辑芯片6可与芯片组2中距离基板1最近的芯片单元21电连接，由于芯片组2中的各芯片单元21之间均电连接在一起，且距离基板1最近的芯片单元21与逻辑芯片6电连接，进而可通过距离基板1最近的芯片单元21将芯片组2中的各芯片单元21的数据信号均传输至逻辑芯片6，再通过逻辑芯片6将数据信号传输至基板1中的外接电路中。
在本公开的一些实施方式中，芯片组2在基板1上的正投影可在逻辑芯片6在基板1上的正投影之内。即，逻辑芯片6的面积可大于位于顶部芯片单元211与基板1之间的各芯片单元21的面积，同时大于顶部芯片单元211的面积。
当芯片组2的数量为多个时，多个芯片组2均可与逻辑芯片6电连接。需要说明的是，基板1与各芯片组2之间可形成有一个逻辑芯片6，也可形成有多个沿平行于基板1的方向间隔分布的逻辑芯片6，在此不做特殊限定。当基板1与各芯片组2之间形成有一个逻辑芯片6时，各芯片组2中距离基板1最近的各芯片单元21可与同一逻辑芯片6电连接。当基板1与各芯片组2之间形成有多个沿平行于基板1的方向间隔分布的逻辑芯片6时，每个逻辑芯片6可至少与一个芯片组2电连接， 且不同的逻辑芯片6连接的芯片组2不同。
在本公开的一种示例性实施方式中，导电结构5还可由芯片组2的内部延伸至逻辑芯片6中，进而使得芯片组2与逻辑芯片6之间可通过导电结构5实现电连接。
本公开实施方式还提供一种存储器，该存储器可包括上述任一实施方式中的半导体结构，其具体细节、形成工艺以及有益效果已经在对应的半导体结构及半导体结构的形成方法中进行了详细说明，此处不再赘述。
举例而言，该存储器可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。当然，还可以是其它存储装置，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种半导体结构的形成方法，其中，包括：
    提供载板；
    在所述载板的一侧形成芯片组，所述芯片组包括多个沿垂直于所述载板的方向堆叠的芯片单元，各所述芯片单元中靠近所述载板的一侧的各所述芯片单元在所述载板上的正投影在距离所述载板最远的所述芯片单元在所述载板上的正投影之内；
    形成覆盖所述芯片组的绝缘介质层；
    进行研磨处理，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外。
  2. 根据权利要求1所述的形成方法，其中，所述芯片组的数量为多个，各所述芯片组间隔分布，所述绝缘介质层填满各所述芯片组之间的间隙，所述芯片组包括底部芯片单元和顶部芯片单元，在平行于所述载板的方向上，相邻的所述底部芯片单元之间具有第一间隔，相邻的所述顶部芯片单元之间具有第二间隔，所述第二间隔的宽度小于所述第一间隔的宽度。
  3. 根据权利要求2所述的形成方法，其中，在平行于所述载板的方向上，所述底部芯片单元具有第一宽度，所述顶部芯片单元具有第二宽度，所述第二宽度大于所述第一宽度。
  4. 根据权利要求3所述的形成方法，其中，所述进行研磨处理，以将距离所述载板最远的所述芯片单元的预定表面暴露于所述绝缘介质层外，包括：
    研磨去掉第一目标厚度的所述绝缘介质层，以露出所述顶部芯片单元的顶表面；
    继续研磨去掉第二目标厚度的所述顶部芯片单元与所述绝缘介质层，以露出所述顶部芯片单元的所述预定表面，其中，所述第二目标厚度不大于所述第一目标厚度。
  5. 根据权利要求2所述的形成方法，其中，所述芯片单元包括衬底及形成于所述衬底表面的电路模块，所述顶部芯片单元中形成有所述电路模块的表面朝向所述载板。
  6. 根据权利要求2-5任一项所述的形成方法，其中，所述形成方法还包括：
    在所述芯片组与所述载板之间形成逻辑芯片，所述芯片组在所述载板上的正投影在所述逻辑芯片在所述载板上的正投影之内。
  7. 根据权利要求6所述的形成方法，其中，所述形成方法还包括：
    在所述研磨处理后，在各所述芯片组之间的所述第一间隔和所述第二间隔中执行切割处理，以分离各所述芯片组。
  8. 根据权利要求7所述的形成方法，其中，在执行所述切割处理的过程中，所述第一间隔中至少保留部分所述绝缘介质层。
  9. 根据权利要求7所述的形成方法，其中，所述形成方法还包括：
    在执行所述切割处理后，去除所述载板，并将所述逻辑芯片背离所述芯片组的表面与一基板电连接。
  10. 一种半导体结构，其中，包括：
    基板；
    芯片组，设于所述基板的一侧，且包括多个沿垂直于所述基板的方向堆叠的芯片单元，各所述芯片单元中靠近所述基板的一侧的各所述芯片单元在所述基板上的正投影在距离所述基板最远的所述芯片单元在所述基板上的正投影之内；
    绝缘层，包覆于所述芯片组的外周，且距离所述基板最远的所述芯片单元的预定表面暴露于所述绝缘层外。
  11. 根据权利要求10所述的半导体结构，其中，所述芯片组包括底部芯片单元和顶部芯片单元，在平行于所述基板的方向上，位于所述顶部芯片单元的侧壁上的所述绝缘层的厚度不大于位于所述底部芯片单元的侧壁上的所述绝缘层的厚度。
  12. 根据权利要求11所述的半导体结构，其中，在平行于所述基板的方向上，所述底部芯片单元具有第一宽度，所述顶部芯片单元具有第二宽度，所述第二宽度大于所述第一宽度。
  13. 根据权利要求11所述的半导体结构，其中，所述芯片单元包括衬底及形成于所述衬底表面的电路模块，所述顶部芯片单元中形成有所述电路模块的表面朝向所述基板。
  14. 根据权利要求10-13任一项所述的半导体结构，其中，所述半导体结构还包括：
    逻辑芯片，设于所述基板与所述芯片组之间，所述芯片组在所述衬底上的正投影在所述逻辑芯片在所述衬底上的正投影之内。
  15. 一种存储器，其中，包括权利要求10-14任一项所述的半导体结构。
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