WO2024047487A1 - 記憶装置 - Google Patents

記憶装置 Download PDF

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Publication number
WO2024047487A1
WO2024047487A1 PCT/IB2023/058422 IB2023058422W WO2024047487A1 WO 2024047487 A1 WO2024047487 A1 WO 2024047487A1 IB 2023058422 W IB2023058422 W IB 2023058422W WO 2024047487 A1 WO2024047487 A1 WO 2024047487A1
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Prior art keywords
insulator
conductor
oxide
oxide semiconductor
transistor
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PCT/IB2023/058422
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
國武寛司
松嵜隆徳
Original Assignee
株式会社半導体エネルギー研究所
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Priority to JP2024543597A priority Critical patent/JPWO2024047487A1/ja
Priority to CN202380062673.7A priority patent/CN119856581A/zh
Priority to KR1020257007363A priority patent/KR20250060217A/ko
Publication of WO2024047487A1 publication Critical patent/WO2024047487A1/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
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    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/033—Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs

Definitions

  • One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one embodiment of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer and a module.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits, imaging devices, electronic devices, and the like can be said to include semiconductor devices.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
  • a CPU is an assembly of semiconductor elements, including a semiconductor integrated circuit (including at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.
  • a technology that constructs a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention.
  • the transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.
  • Patent Document 1 discloses a CPU with low power consumption that takes advantage of the low leakage current of a transistor using an oxide semiconductor.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by applying the characteristic that a transistor using an oxide semiconductor has a small leakage current.
  • Patent Document 3 and Non-Patent Document 1 a plurality of memory cells are provided in an overlapping manner by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film. discloses a technique for increasing the density of integrated circuits.
  • Patent Document 4 discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.
  • JP2012-257187A JP2011-151383A International Publication No. 2021/053473 JP2013-211537A
  • An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.
  • one of the challenges is to provide a storage device with high operating speed.
  • one of the challenges is to provide a storage device having good electrical characteristics.
  • one of the challenges is to provide a storage device with good reliability.
  • one of the challenges is to provide a storage device with a large on-state current.
  • one of the challenges is to provide a storage device with low power consumption.
  • one of the challenges is to provide a new storage device.
  • one of the objectives is to provide a method for manufacturing a new storage device.
  • One embodiment of the present invention provides a memory device including a first conductor, a memory cell on the first conductor, a first insulator on the first conductor, and a second insulator. It is.
  • the memory cell includes a capacitor and a transistor on the capacitor.
  • the capacitive element includes a second conductor, a third insulator on the second conductor, and a third conductor on the third insulator.
  • the first insulator is provided with a first opening that reaches the first conductor. At least a portion of the second conductor, at least a portion of the third insulator, and at least a portion of the third conductor are arranged in the first opening.
  • a second insulator is disposed on the second conductor, the third insulator, and the third conductor.
  • the transistor includes a third conductor, a fourth conductor on a second insulator, an oxide semiconductor, a fourth insulator, and a fifth conductor.
  • the second insulator and the fourth conductor are provided with a second opening that reaches the third conductor. At least a portion of the oxide semiconductor is disposed in the second opening.
  • the oxide semiconductor includes at least a region in contact with the top surface of the third conductor in the second opening, a region in contact with the side surface of the fourth conductor in the second opening, and a region in contact with the top surface of the fourth conductor in the second opening. It has a region that touches a part of it.
  • the fourth insulator is disposed on the oxide semiconductor so that at least a portion thereof is located in the second opening.
  • the fifth conductor is disposed on the fourth insulator such that at least a portion thereof is located in the second opening.
  • the oxide semiconductor has a stacked structure of a first oxide semiconductor and a second oxide semiconductor over the first oxide semiconductor.
  • the first oxide semiconductor and the second oxide semiconductor have a thickness at a portion where the top surface of the fourth conductor is the formation surface and a side surface of the second insulator. It is preferable that the ratio of the film thickness of the portion serving as the formation surface is different.
  • the second opening has a region that overlaps with the first opening.
  • the channel length of the transistor is preferably smaller than the channel width of the transistor.
  • the third insulator preferably includes a material that can have ferroelectricity.
  • the third insulator preferably includes first zirconium oxide, aluminum oxide on the first zirconium oxide, and second zirconium oxide on the aluminum oxide.
  • each of the first oxide semiconductor and the second oxide semiconductor preferably contains one or more of In, Ga, and Zn.
  • the first insulator includes a laminate
  • the laminate includes a first layer
  • the first layer includes:
  • the second layer contains silicon and nitrogen
  • the second layer contains silicon and oxygen.
  • a fifth insulator is provided between the side surface of the first insulator in the first opening and the second conductor, and the fifth insulator is made of silicon and nitrogen. It is preferable to have the following.
  • the fifth conductor is provided to extend in the first direction
  • the fourth conductor is provided to extend in the second direction
  • the fifth conductor is provided to extend in the second direction. It is preferable that the fourth conductor is orthogonal to the fourth conductor.
  • the above memory device preferably has a plurality of layers including memory cells, and the plurality of layers are preferably stacked.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a storage device with high operating speed can be provided.
  • a highly reliable storage device can be provided.
  • a memory device with less variation in the electrical characteristics of transistors can be provided.
  • a storage device with good electrical characteristics can be provided.
  • a storage device with a large on-state current can be provided.
  • a storage device with low power consumption can be provided.
  • new storage devices can be provided.
  • a method for manufacturing a new storage device can be provided.
  • FIG. 1A is a plan view showing an example of a storage device.
  • FIG. 1B and FIG. 1C are cross-sectional views showing an example of a storage device.
  • FIG. 1D is a circuit diagram for explaining an example of the configuration of a storage device.
  • 2A and 2B are plan views showing an example of a storage device.
  • 3A to 3D are cross-sectional views showing an example of a storage device.
  • 4A to 4D are cross-sectional views showing an example of a storage device.
  • FIG. 5A is a cross-sectional view showing an example of a storage device.
  • FIG. 5B is a cross-sectional view showing an example of a storage device.
  • 6A to 6D are cross-sectional views showing an example of a storage device.
  • FIG. 1A is a plan view showing an example of a storage device.
  • FIG. 1B and FIG. 1C are cross-sectional views showing an example of a storage device.
  • FIG. 1D is a
  • FIG. 7A is a plan view showing an example of a storage device.
  • 7B and 7C are cross-sectional views showing an example of a storage device.
  • 8A to 8C are cross-sectional views showing an example of a storage device.
  • 9A to 9D are cross-sectional views showing an example of a storage device.
  • 10A and 10B are cross-sectional views showing an example of a storage device.
  • FIG. 11A is a plan view showing an example of a storage device.
  • 11B and 11C are cross-sectional views showing an example of a storage device.
  • FIG. 12A is a plan view showing an example of a method for manufacturing a storage device.
  • 12B and 12C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 13A is a plan view showing an example of a method for manufacturing a storage device.
  • 13B and 13C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 14A is a plan view showing an example of a method for manufacturing a storage device.
  • 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 15A is a plan view showing an example of a method for manufacturing a storage device.
  • 15B and 15C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 16A is a plan view showing an example of a method for manufacturing a storage device.
  • FIG. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 17A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 18A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 19A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • 20A is a plan view showing an example of a method for manufacturing a storage device.
  • 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 21A is a plan view showing an example of a method for manufacturing a storage device.
  • 21B and 21C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 22A is a plan view illustrating an example of a method for manufacturing a storage device.
  • 22B and 22C are cross-sectional views illustrating an example of a method for manufacturing a memory device.
  • FIG. 23A is a plan view showing an example of a storage device.
  • FIG. 23B is a cross-sectional view showing an example of a storage device.
  • FIG. 24A is a plan view showing an example of a storage device.
  • FIG. 24B is a cross-sectional view showing an example of a storage device.
  • FIG. 25A is a plan view showing an example of a storage device.
  • FIG. 25B is a cross-sectional view showing an example of a storage device.
  • 26A to 26C are planar layouts showing an example of a storage device.
  • 27A to 27C are plan layouts showing an example of a storage device.
  • 28A to 28E are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
  • 29A to 29D are cross-sectional views of metal oxides according to one embodiment of the present invention.
  • FIG. 30A to 30D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
  • 31A to 31C are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
  • FIG. 32 is a block diagram illustrating a configuration example of a storage device.
  • FIG. 33A is a schematic diagram illustrating a configuration example of a storage device.
  • FIG. 33B is a circuit diagram illustrating a configuration example of a storage device.
  • 34A and 34B are schematic diagrams illustrating a configuration example of a storage device.
  • FIG. 35 is a circuit diagram illustrating a configuration example of a storage device.
  • 36A and 36B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • FIGS. 41A and 41B are cross-sectional views illustrating transistors included in the manufactured sample.
  • FIG. 42 shows the Id-Vg characteristics of the transistor.
  • the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.
  • the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.
  • a layer or a resist mask may be unintentionally reduced due to a process such as etching, but this may not be reflected in the diagram for ease of understanding.
  • the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated explanations thereof may be omitted.
  • the hatching pattern may be the same and no particular reference numeral may be attached.
  • ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by replacing “first” with “second” or “third” as appropriate. Furthermore, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.
  • X and Y are connected means that X and Y are electrically connected.
  • X and Y refers to an object between X and Y (an element such as a switch, transistor, or diode, or a circuit including the element and wiring).
  • a connection that allows transmission of electrical signals between X and Y when Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • "X and Y are directly connected” means that electrical signals are transmitted between X and Y via wiring (or electrodes), etc., without going through the above object.
  • direct connection refers to a connection that can be viewed as the same circuit diagram when expressed as an equivalent circuit.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode). A current can be passed between the source and the drain through the formation region.
  • a channel formation region refers to a region through which current mainly flows.
  • the function of the source or drain may be swapped if transistors with different polarities are used, or if the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably.
  • impurity of a semiconductor refers to, for example, something other than the main components constituting the semiconductor.
  • an element having a concentration of less than 0.1 atomic % can be considered an impurity.
  • the inclusion of impurities may cause, for example, an increase in the defect level density of the semiconductor, a decrease in crystallinity, and the like.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and the oxide semiconductor.
  • transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • oxynitride refers to a composition containing more oxygen than nitrogen.
  • examples of the oxynitride include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.
  • the nitrided oxide has a composition containing more nitrogen than oxygen.
  • examples of the nitride oxide include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
  • the term “insulator” can be translated as an insulating film or an insulating layer. Further, the term “conductor” can be translated as a conductive film or a conductive layer. Further, the term “semiconductor” can be translated as a semiconductor film or a semiconductor layer.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included.
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included.
  • substantially perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Voltage refers to a potential difference from a reference potential.
  • the reference potential is a ground potential (earth potential)
  • “voltage” can be translated into “potential.” Note that the ground potential does not necessarily mean 0V.
  • potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, etc., the potential output from circuits, etc. also change.
  • the heights match refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • a reference surface for example, a flat surface such as a substrate surface
  • the surface of a single layer or a plurality of layers may be exposed by performing a planarization process (typically a CMP (Chemical Mechanical Polishing) process).
  • CMP Chemical Mechanical Polishing
  • the surfaces to be subjected to CMP processing have the same height from the reference surface.
  • the heights of the plurality of layers may differ depending on the processing apparatus, processing method, or material of the surface to be processed during CMP processing.
  • the heights match In this specification, this case is also treated as "the heights match.”
  • the height of the top surface of the first layer and the height of the second layer are Even if the difference from the height of the top surface of the layer is 20 nm or less, it is also said that the heights match.
  • the ends coincide means that at least a portion of the outlines of the stacked layers overlap in plan view. For example, this includes a case where the upper layer and the lower layer are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours do not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. "Concordance”.
  • match includes both a complete match and a general match.
  • normally-on characteristics refer to a state in which a channel exists and current flows through the transistor even without applying a potential to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
  • a memory device that is one embodiment of the present invention includes memory cells. Further, the memory cell includes a transistor and a capacitor.
  • FIGS. 1A to 1C are a plan view and a cross-sectional view of a memory device including a transistor 200 and a capacitor 100.
  • FIG. 1A is a plan view of the storage device.
  • FIGS. 1B and 1C are cross-sectional views of the storage device.
  • FIG. 1B is a sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A. Note that in the plan view of FIG. 1A, some elements are omitted for clarity.
  • arrows indicating the X direction, Y direction, and Z direction may be attached.
  • the "X direction” refers to the direction along the X axis, and the forward direction and reverse direction may not be distinguished unless explicitly stated.
  • the X direction, the Y direction, and the Z direction are directions that intersect with each other.
  • the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.
  • one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction” or a “first direction.”
  • the other one may be called a "second direction” or a “second direction”.
  • the remaining one may be referred to as a "third direction” or "third direction.”
  • the memory device shown in FIGS. 1A to 1C includes an insulator 140 on a substrate (not shown), a conductor 110 on the insulator 140, a memory cell 150 on the conductor 110, and an insulator on the conductor 110. It has a body 180, an insulator 280, and an insulator 283 on the memory cell 150. Insulator 140, insulator 180, insulator 280, and insulator 283 function as interlayer films.
  • the conductor 110 functions as a wiring.
  • the memory cell 150 includes a capacitive element 100 on a conductor 110 and a transistor 200 on the capacitive element 100.
  • the capacitive element 100 includes a conductor 115 on the conductor 110, an insulator 130 on the conductor 115, and a conductor 120 on the insulator 130.
  • the conductor 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductor 115 functions as the other of a pair of electrodes (sometimes called a lower electrode)
  • the insulator 130 functions as a dielectric. functions as In other words, the capacitive element 100 constitutes an MIM (Metal-Insulator-Metal) capacitor.
  • the insulator 180 is provided with an opening 190 that reaches the conductor 110. At least a portion of the conductor 115 is disposed in the opening 190. Note that the conductor 115 has a region in contact with the top surface of the conductor 110 at the opening 190, a region in contact with the side surface of the insulator 180 in the opening 190, and a region in contact with at least a part of the top surface of the insulator 180. have The insulator 130 is arranged such that at least a portion thereof is located in the opening 190. The conductor 120 is arranged such that at least a portion thereof is located in the opening 190. Note that the conductor 120 is preferably provided so as to fill the opening 190, as shown in FIGS. 1B and 1C.
  • FIG. 2A is a plan view showing an excerpt of the conductor 110, the conductor 115, the conductor 120, and the opening 190. Note that the opening 190 provided in the insulator 180 is shown by a broken line. As shown in FIG. 2A, the conductor 115 has an opening 190 in a region overlapping with the conductor 110. As shown in FIG.
  • the capacitive element 100 has a structure in which the upper electrode and the lower electrode face each other with a dielectric interposed not only on the bottom surface but also on the side surface of the opening 190, and the capacitance per unit area can be increased. can. Therefore, as the depth of the opening 190 is increased, the capacitance of the capacitive element 100 can be increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, the read operation of the storage device can be stabilized. Further, it is possible to promote miniaturization or higher integration of storage devices.
  • the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. At this time, the opening 190 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • a conductor 115 and an insulator 130 are laminated along the side wall of the opening 190 and the top surface of the conductor 110. Further, a conductor 120 is provided on the insulator 130 so as to fill the opening 190.
  • the capacitive element 100 having such a configuration may be called a trench-type capacitor or a trench capacitor.
  • An insulator 280 is placed on the capacitive element 100. That is, the insulator 280 is placed on the conductor 115, the insulator 130, and the conductor 120. In other words, the conductor 120 is placed under the insulator 280.
  • the transistor 200 includes a conductor 120, a conductor 240 over an insulator 280, an oxide semiconductor 230, an insulator 250 over the oxide semiconductor 230, and a conductor 260 over the insulator 250.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulator 250 functions as a gate insulator
  • the conductor 120 functions as one of a source electrode and a drain electrode
  • the conductor 240 functions as a source electrode and a drain electrode. functions as the other of the source electrode and the drain electrode.
  • the insulator 280 and the conductor 240 are provided with an opening 290 that reaches the conductor 120. At least a portion of the oxide semiconductor 230 is arranged in the opening 290. Note that the oxide semiconductor 230 has a region in contact with the top surface of the conductor 120 at the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a part of the top surface of the conductor 240. has. Insulator 250 is arranged such that at least a portion thereof is located in opening 290 . The conductor 260 is arranged so that at least a portion thereof is located in the opening 290. Note that the conductor 260 is preferably provided so as to fill the opening 290, as shown in FIGS. 1B and 1C.
  • FIG. 2B is a plan view showing an excerpt of the conductor 120, the oxide semiconductor 230, the conductor 240, the conductor 260, and the opening 290. Note that openings 290 provided in the insulator 280 and the conductor 240 are shown by broken lines. As shown in FIG. 2B, the conductor 240 has an opening 290 in a region overlapping with the conductor 120. Further, it is preferable that the conductor 240 is not provided inside the opening 290. In other words, the conductor 240 preferably does not have a region in contact with the side surface of the insulator 280 on the opening 290 side.
  • the oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 in the opening 290 and a region in contact with a part of the upper surface of the conductor 240. In this way, since the oxide semiconductor 230 is in contact with not only the side surface but also the top surface of the conductor 240, the area in which the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the transistor 200 is provided so as to overlap the capacitive element 100. Further, the opening 290 in which a part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which a part of the structure of the capacitor 100 is provided.
  • the conductor 120 has a function as one of the source electrode and drain electrode of the transistor 200 and a function as an upper electrode of the capacitor 100, the transistor 200 and the capacitor 100 share a part of the structure. I will do it.
  • the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in plan view. As a result, the area occupied by the memory cells 150 can be reduced, so the memory cells 150 can be arranged with high density and the storage capacity of the memory device can be increased. In other words, the storage device can be highly integrated.
  • FIG. 1D A circuit diagram of the memory device shown in this embodiment is shown in FIG. 1D.
  • the configuration shown in FIGS. 1A to 1C functions as a memory cell of a storage device.
  • the memory cell includes a transistor Tr and a capacitive element C.
  • the transistor Tr corresponds to the transistor 200
  • the capacitive element C corresponds to the capacitive element 100.
  • One of the source and drain of the transistor Tr is connected to one of the pair of electrodes of the capacitive element C.
  • the other of the source and drain of the transistor Tr is connected to the wiring BL.
  • the gate of the transistor Tr is connected to the wiring WL.
  • the other of the pair of electrodes of the capacitive element C is connected to the wiring PL.
  • the wiring BL corresponds to the conductor 240
  • the wiring WL corresponds to the conductor 260
  • the wiring PL corresponds to the conductor 110.
  • the conductor 260 is preferably provided to extend in the Y direction
  • the conductor 240 is preferably provided to extend in the X direction.
  • the wiring BL and the wiring WL are provided to intersect with each other. By intersecting the wiring BL and the wiring WL, the area of the region where the wiring BL and the wiring WL overlap becomes smaller, and the parasitic capacitance generated between the wiring BL and the wiring WL can be reduced. Further, in FIG.
  • the wiring PL (conductor 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring PL may be provided parallel to the wiring WL (conductor 260) or may be provided parallel to the wiring BL (conductor 240).
  • Capacitive element 100 includes a conductor 115, an insulator 130, and a conductor 120. Furthermore, a conductor 110 is provided below the conductor 115 . The conductor 115 has a region in contact with the conductor 110.
  • the conductor 110 is provided on the insulator 140.
  • the conductor 110 functions as a wiring PL, and can be provided in a planar shape, for example.
  • the conductor 110 the conductors described in the section [Conductor] described below can be used in a single layer or a laminated structure.
  • a highly conductive material such as tungsten can be used as the conductor 110. By using such a conductive material with high conductivity, the conductivity of the conductor 110 can be improved and the conductor 110 can sufficiently function as the wiring PL.
  • the conductor 110 is made of a single layer or a laminated layer of a conductive material that is difficult to oxidize, or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion.
  • titanium nitride or indium tin oxide added with silicon may be used.
  • a structure in which titanium nitride is laminated on tungsten may be used.
  • a structure may be used in which tungsten is laminated on a first titanium nitride, and a second titanium nitride is laminated on the tungsten.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a conductive material that is difficult to oxidize a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • titanium nitride or tantalum nitride can be used.
  • tantalum nitride a structure in which tantalum nitride is laminated on titanium nitride may be used.
  • the insulator 130 is provided on the conductor 115.
  • the insulator 130 is provided so as to be in contact with the top and side surfaces of the conductor 115. That is, it is preferable that the insulator 130 has a structure that covers the side end portions of the conductor 115. This can prevent short-circuiting between the conductor 115 and the conductor 120.
  • a structure may be adopted in which the side end portion of the insulator 130 and the side end portion of the conductor 115 match.
  • the insulator 130 and the conductor 115 can be formed using the same mask, and the manufacturing process of the memory device can be simplified.
  • the insulator 130 it is preferable to use a material with a high dielectric constant, a so-called high-k material, described in the section [Insulator] described below.
  • a high-k material as the insulator 130, the insulator 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently secured.
  • the insulator 130 is used by laminating insulating layers made of a high-k material, and is made of a material having a high dielectric constant (high-k) and a material having a dielectric strength higher than that of the high-k material.
  • a laminated structure is used.
  • the insulator 130 an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used.
  • an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used.
  • an insulator having a relatively high dielectric strength, such as aluminum oxide the dielectric strength is improved and electrostatic breakdown of the capacitive element 100 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulator 130.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • element J1 here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.
  • hafnium oxide examples include added materials.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set as appropriate.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 may be set to 1:1 or around 1:1.
  • element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Added materials, etc.
  • the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set as appropriate.
  • the ratio of the number of atoms of zirconium to the number of atoms of element J2 may be set to 1:1 or around 1:1.
  • lead titanate PbTiO x
  • barium strontium titanate BST
  • strontium titanate PZT
  • strontium bismuthate tantalate SBT
  • Piezoelectric ceramics having a perovskite structure such as bismuth ferrite (BFO) and barium titanate, may also be used.
  • examples of materials that can have ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen.
  • the element M1 is one or more selected from aluminum, gallium, indium, and the like.
  • the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate.
  • a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • materials that can have ferroelectricity include materials in which element M3 is added to the metal nitride described above.
  • the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
  • examples of materials that can have ferroelectricity include perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ alumina structure.
  • metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto.
  • a metal oxynitride obtained by adding nitrogen to the above-mentioned metal oxide, or a metal nitride obtained by adding oxygen to the above-mentioned metal nitride, etc. may be used.
  • the material that can have ferroelectricity for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used.
  • the insulator 130 can have a laminated structure made of a plurality of materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above may change not only due to film formation conditions but also due to various processes, so in this specification, only materials that exhibit ferroelectricity will be referred to. It is not only called a ferroelectric material, but also a material that can have ferroelectric properties.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even when processed into a thin film of several nanometers.
  • the film thickness of the insulator 130 can be set to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).
  • the film thickness is preferably 8 nm or more and 12 nm or less.
  • a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
  • a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area.
  • the area (occupied area) of the ferroelectric layer in plan view is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less, it can have ferroelectricity.
  • the thickness is 10000 nm 2 or less, or 1000 nm 2 or less, it may have ferroelectricity.
  • a ferroelectric material is an insulator, and has the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be formed using a capacitive element using this material as a dielectric (hereinafter sometimes referred to as a ferroelectric capacitor).
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like.
  • a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitive element 100, the storage device described in this embodiment functions as a ferroelectric memory.
  • ferroelectricity is said to be developed when oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. Furthermore, the expression of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to exhibit ferroelectricity, the insulator 130 needs to contain crystals. In particular, it is preferable for the insulator 130 to include a crystal having a rectangular crystal structure because ferroelectricity is exhibited. Note that the crystal structure of the crystal contained in the insulator 130 may be one or more selected from cubic, tetragonal, rectangular, monoclinic, and hexagonal. good. Further, the insulator 130 may have an amorphous structure. At this time, the insulator 130 may have a composite structure having an amorphous structure and a crystal structure.
  • the conductor 120 is provided in contact with a part of the upper surface of the insulator 130. Further, as shown in FIG. 2A, the side end portion of the conductor 120 is preferably located inside the side end portion of the conductor 115 in both the X direction and the Y direction. Note that in a structure in which the insulator 130 covers the side end portion of the conductor 115, the side end portion of the conductor 120 may be located outside the side end portion of the conductor 115.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a conductive material that is difficult to oxidize a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • titanium nitride or tantalum nitride can be used.
  • a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, titanium nitride is in contact with the insulator 130 and tantalum nitride is in contact with the oxide semiconductor 230.
  • the conductor 120 may have a structure in which tungsten is laminated on titanium nitride, for example.
  • the conductor 120 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section [Conductor] described below.
  • a conductive material containing oxygen as the conductor 120, conductivity can be maintained even if the conductor 120 absorbs oxygen.
  • an insulator containing oxygen such as zirconium oxide is used as the insulator 130, the conductor 120 is suitable because it can maintain conductivity.
  • the conductor 120 for example, a single layer or a stack of indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin oxide (also referred to as ITO), indium tin oxide added with silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), etc. It can be used indium tin
  • the conductor 120 may have a laminated structure of three or more layers, in which conductors containing a metal element different from the conductor are laminated so as to sandwich a conductor containing a highly conductive material.
  • highly conductive materials include conductive materials containing tungsten, copper, or aluminum as a main component.
  • a conductor sandwiching a conductor containing a highly conductive material a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or a conductive material that contains oxygen may be used. is preferred.
  • tungsten is used as a highly conductive material
  • titanium nitride is used as a conductive material that is difficult to oxidize, or a conductive material that has the function of suppressing oxygen diffusion
  • titanium is used as a conductive material containing oxygen.
  • silicon-doped indium tin oxide can be used.
  • the conductor 120 has a structure in which titanium nitride, tungsten on titanium nitride, and indium tin oxide added with silicon on tungsten are stacked.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. At this time, the insulator 180 includes at least silicon and oxygen.
  • the insulator 180 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 180 may have a laminated structure.
  • the insulator 180 may have a stacked structure of an insulator 180a and an insulator 180b on the insulator 180a.
  • the insulator 180b it is preferable to use an insulating material that is applicable to the insulator 180 described above.
  • the insulator 180a it is preferable to use an insulator that has barrier properties against oxygen and is described in the section [Insulator] described below. Oxygen contained in the insulator 180b may oxidize the conductor 110, resulting in increased resistance. By providing the insulator 180a between the insulator 180b and the conductor 110, it is possible to prevent the conductor 110 from being oxidized and increasing its resistance.
  • impurities such as hydrogen When impurities such as hydrogen are mixed into the insulator 130, leakage current generated between the upper electrode and the lower electrode may increase. Furthermore, when a material that can have ferroelectricity is used as the insulator 130, impurities such as hydrogen may be mixed into the material that can have ferroelectricity, which may reduce the crystallinity of the material that can have ferroelectricity. There is a risk of deterioration. Therefore, it is preferable to prevent impurities such as hydrogen from entering the insulator 130.
  • the insulator 180a it is preferable to use an insulator having barrier properties against hydrogen, which is described in the section [Insulator] described later. Thereby, hydrogen can be suppressed from diffusing into the insulator 130 from below the insulator 180a via the insulator 180b and the conductor 115. Silicon nitride and silicon nitride oxide can be suitably used for the insulator 180a because they each release less impurities (for example, water and hydrogen) from themselves and are less permeable to oxygen and hydrogen. At this time, the insulator 180a includes at least silicon and nitrogen.
  • the insulator 180a it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 180a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 180a.
  • FIGS. 3A and 3B show a structure in which the insulator 180 has a two-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 180 may have a laminated structure of three or more layers.
  • an insulator may be provided between the conductor 115 and the insulator 130 and the insulator 180b in addition to the insulator 180a and the insulator 180b.
  • an insulator applicable to the insulator 180a can be used. This can suppress hydrogen from diffusing into the insulator 130 via the insulator 180b.
  • the insulator 185 is provided so as to be in contact with the side surface of the insulator 180 in the opening 190. That is, the insulator 185 is preferably provided between the side surface of the insulator 180 in the opening 190 and the conductor 115.
  • the insulator 185 it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described below. This can suppress hydrogen from diffusing from outside the capacitive element 100 through the insulator 180 into the insulator 130 located in the opening 190.
  • silicon nitride or silicon nitride oxide can be used as the insulator 185.
  • the insulator 185 includes at least silicon and nitrogen.
  • the insulator 185 it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With such a configuration, hydrogen in the insulator 130 can be captured or fixed, and the hydrogen concentration in the insulator 130 can be reduced.
  • the insulator 185 magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 185.
  • the insulator 185 is provided so as to be in contact with the side surface of the insulator 180a in the opening 190 and the side surface of the insulator 180b in the opening 190, but the present invention is not limited to this. It's not something you can do.
  • the insulator 185 may be provided so as to be in contact with a part of the upper surface of the insulator 180a and the side surface of the insulator 180b at the opening 190.
  • the conductor 120 is located inside the conductor 115 via the insulator 130, but the present invention is not limited to this.
  • the conductor 120 may be located outside the conductor 115 with the insulator 130 in between.
  • the insulator 130 is disposed on the outer side surface of the conductor 115 in addition to a region in contact with the inside of the recess of the conductor 115 and a region in contact with the upper surface of the conductor 115. It is preferable to have an area located at .
  • the conductor 120 is provided so as to fill the recessed portion of the conductor 115 with the insulator 130 interposed therebetween. Furthermore, the conductor 120 has a region that faces a part of the outer side surface of the conductor 115 with the insulator 130 in between.
  • the capacitance per unit area can be increased.
  • an insulator 135 may be provided between the outer side surface of the conductor 115 and the insulators 130 and 180.
  • an insulator 182 may be provided on the conductor 120 and the insulator 130. Further, it is preferable that the insulator 182 is subjected to a planarization treatment so that the upper surface of the conductor 120 is exposed. By performing planarization treatment on the insulator 182, the transistor 200 can be suitably formed over the capacitor 100.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator applicable to the insulator 180 can be used as the insulator 182 .
  • the insulator 180 may be omitted.
  • the storage device shown in FIGS. 4C and 4D differs from the storage device shown in FIGS. 4A and 4B in that the insulator 180b is not provided. By not providing the insulator 180b, the manufacturing process of the memory device can be simplified.
  • the transistor 200 includes a conductor 120, a conductor 240 on an insulator 280, an upper surface of the conductor 120 exposed in an opening 290, and an insulator 280 in the opening 290. , the side surface of the conductor 240 in the opening 290, and the oxide semiconductor 230 provided in contact with at least a portion of the top surface of the conductor 240; and the insulator 250 provided in contact with the top surface of the oxide semiconductor 230. and a conductor 260 provided in contact with the upper surface of the insulator 250.
  • the bottom of the opening 290 is the top surface of the conductor 120
  • the sidewalls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
  • the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 110. At this time, the opening 290 has a cylindrical shape. With such a configuration, it is possible to miniaturize or highly integrate the memory device.
  • the opening 290 is circular in plan view, but the present invention is not limited to this.
  • the opening 290 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • the maximum width of the opening 290 may be calculated as appropriate depending on the shape of the top of the opening 290.
  • the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
  • the portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided to cover the oxide semiconductor 230, and a recessed portion of the insulator 250 that reflects the shape of the opening 290 is formed. A conductor 260 is provided so as to be buried therein.
  • FIG. 5A an enlarged view of the oxide semiconductor 230 and its vicinity in FIG. 1B is shown in FIG. 5A. Further, a cross-sectional view in the XY plane including the conductor 240 is shown in FIG. 5B.
  • the oxide semiconductor 230 includes a region 230i, and a region 230na and a region 230nb provided to sandwich the region 230i.
  • the region 230na is a region of the oxide semiconductor 230 that is in contact with the conductor 120. At least a portion of the region 230na functions as one of a source region and a drain region of the transistor 200.
  • the region 230nb is a region of the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb functions as the other of the source region and the drain region of the transistor 200.
  • the conductor 240 is in contact with the entire outer periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 200 can be formed over the entire outer periphery of a portion of the oxide semiconductor 230 that is formed in the same layer as the conductor 240.
  • the region 230i is a region of the oxide semiconductor 230 between the region 230na and the region 230nb. At least a portion of the region 230i functions as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 between the conductor 120 and the conductor 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or a region near the region.
  • the channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • FIG. 5A shows the channel length L of the transistor 200 with a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 120 are in contact with each other and the end of the region where the oxide semiconductor 230 and the conductor 240 are in contact in a cross-sectional view.
  • the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the thickness of the insulator 280. Therefore, the channel length of the transistor 200 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell 150 can be improved, so that a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the area occupied by the transistor 200 can be reduced compared to a planar transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane. This allows the storage device to be highly integrated, thereby increasing the storage capacity per unit area.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically. Therefore, the side surface of the conductor 260 provided at the center faces the side surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. That is, in plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region.
  • the channel width of the transistor 200 is determined by the length of the outer circumference of the oxide semiconductor 230. In other words, the channel width of the transistor 200 can be said to be determined by the maximum width of the opening 290 (the diameter if the opening 290 is circular in plan view).
  • the maximum width D of the opening 290 is indicated by a two-dot chain double-headed arrow.
  • the channel width W of the transistor 200 is indicated by a double-dashed dashed arrow.
  • the maximum width D of the opening 290 is set by the exposure limit of the photolithography. Further, the maximum width D of the opening 290 is set by the respective film thicknesses of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D ⁇ ".
  • the channel length L of the transistor 200 is preferably smaller than at least the channel width W of the transistor 200.
  • the channel length L of the transistor 200 according to one embodiment of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W of the transistor 200. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor 230, the insulator 250, and the conductor 260 are provided concentrically. Accordingly, the distance between the conductor 260 and the oxide semiconductor 230 becomes approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
  • a channel formation region of a transistor using an oxide semiconductor for a semiconductor layer preferably has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or a metal element than the source and drain regions.
  • hydrogen near oxygen vacancies may form defects in which hydrogen is present in oxygen vacancies (hereinafter sometimes referred to as V O H), and generate electrons that become carriers.
  • V O H oxygen vacancies
  • V OH are also preferably reduced.
  • the channel formation region of the transistor is a high resistance region with low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.
  • the source region and drain region of a transistor using an oxide semiconductor for the semiconductor layer have more oxygen vacancies, more V O H, or a higher concentration of impurities such as hydrogen, nitrogen, and metal elements than the channel formation region.
  • the opening 290 is provided so that the side wall of the opening 290 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the sidewalls of opening 290 may be tapered.
  • FIGS. 6A and 6B has a configuration in which the side wall of the opening 290 is tapered. Note that FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 6A and 6B.
  • the angle between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • a tapered shape refers to a shape in which at least a part of the side surface of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, there is a region where the angle between the inclined side surface and the substrate surface (hereinafter sometimes referred to as a taper angle) is less than 90 degrees.
  • the side surfaces of the structure and the substrate surface do not necessarily have to be completely flat, and may be substantially planar with minute curvatures or substantially planar with minute irregularities.
  • the shape of the opening 290 shown in FIGS. 6A and 6B is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big.
  • the maximum diameter of the opening 290 may be calculated based on the upper base surface of the truncated cone shape.
  • the channel length can be set by the thickness of the insulator 280 and the angle ⁇ 1 between the side surface of the insulator 280 and the top surface of the conductor 120 in the opening 290. Further, the length of the outer periphery of the oxide semiconductor 230 in a plan view may be determined, for example, at a region facing the conductor 240 or at a position half the thickness of the insulator 280. Note that the length of the circumference at an arbitrary position (depth) of the opening 290 may be used as the channel width of the transistor 200, if necessary. For example, the length of the circumference at the bottom of the opening 290 may be set as the channel width, or the length of the circumference at the top of the opening 290 may be set as the channel width.
  • FIGS. 6A and 6B show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 are flush with each other
  • the present invention is not limited to this.
  • the side surface of the conductor 240 at the opening 290 and the side surface of the insulator 280 at the opening 290 may be discontinuous.
  • the slope of the side surface of the conductor 240 at the opening 290 and the slope of the side surface of the insulator 280 at the opening 290 may be different from each other.
  • the angle between the side surface of the conductor 240 in the opening 290 and the top surface of the conductor 120 is preferably smaller than the angle ⁇ 1.
  • the bottom of the conductor 260 located in the opening 290 has a flat area.
  • the maximum width of the opening 290 (diameter if the opening 290 is circular in plan view), the thickness of the insulator 280 (corresponding to the depth of the opening 290), and the film of the oxide semiconductor 230
  • the bottom of the conductor 260 located in the opening 290 may not have a flat area.
  • the bottom of the conductor 260 located in the opening 290 may have a needle-like shape.
  • FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 6C and 6D.
  • the term acicular refers to a shape that becomes thinner toward the tip (closer to the bottom of the conductor 260 located in the opening 290).
  • the needle-like tip may have an acute angle or may have a downwardly convex curved shape.
  • a shape having an acute angle at the tip may be referred to as a V-shape.
  • a region of the conductor 260 located in the opening 290 that faces the oxide semiconductor 230 with the insulator 250 in between functions as a gate electrode. Therefore, the conductor 260 that fills the opening 290 and has a needle-like bottom shape may be referred to as a needle-shaped gate. Furthermore, as shown in FIGS. 6A and 6B, even if the conductor 260 has a flat bottom region, it may be called a needle-shaped gate.
  • the opening 190 is provided so that the side wall of the opening 190 is perpendicular to the top surface of the conductor 110, but the present invention is not limited to this.
  • the sidewalls of opening 190 may be tapered.
  • the angle between the side surface of the insulator 180 in the opening 190 and the top surface of the conductor 110 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • the bottom of the conductor 120 located in the opening 190 has a flat region.
  • the maximum width of the opening 190 (diameter if the opening 190 is circular in plan view), the thickness of the insulator 180 (corresponding to the depth of the opening 190), and the thickness of the conductor 115 , the film thickness of the insulator 130, etc., the bottom of the conductor 120 located in the opening 190 may not have a flat region.
  • the bottom of the conductor 120 located in the opening 190 may have a needle-like shape.
  • FIG. 1A can be referred to for a plan view of the storage device shown in FIGS. 6C and 6D.
  • the angle ⁇ 1 and the angle ⁇ 2 match or approximately match.
  • the angle ⁇ 1 and the angle ⁇ 2 may be different depending on the materials used for the insulator 180 and the insulator 280, the method for forming the opening 190 and the opening 290, and the like.
  • the angle ⁇ 1 may be larger than the angle ⁇ 2, or may be smaller than the angle ⁇ 2.
  • one of the angle ⁇ 1 and the angle ⁇ 2 may be 90 degrees or a value close to 90 degrees.
  • a value in the vicinity of a certain numerical value A refers to a value of 0.9 ⁇ A or more and 1.1 ⁇ A or less.
  • the side wall of the opening 290 may have an inverted tapered shape.
  • the angle between the side surface of the insulator 280 in the opening 290 and the top surface of the conductor 120 may be larger than 90 degrees.
  • the inverted tapered shape is a shape that has a side portion or an upper portion that protrudes from the bottom portion in a direction parallel to the substrate.
  • the shape of the opening 290 is a truncated cone shape.
  • the opening 290 is circular in plan view, and trapezoidal in cross-section.
  • the area of the truncated cone-shaped upper base (for example, the opening provided in the conductor 240) is larger than the area of the truncated conical lower base (the upper surface of the conductor 120 exposed in the opening 290). big. With such a structure, the area in which the oxide semiconductor 230 and the conductor 120 are in contact can be increased.
  • the side walls of the opening 190 may have an inverted tapered shape.
  • FIGS. 1B and 1C a portion of the oxide semiconductor 230 is located outside the opening 290, that is, on the conductor 240.
  • FIG. 1B shows a configuration in which the oxide semiconductor 230 is divided in the X direction
  • the present invention is not limited to this.
  • the oxide semiconductor 230 may be provided extending in the X direction.
  • the oxide semiconductor 230 is divided in the Y direction (see FIG. 7C).
  • FIG. 1C shows a configuration in which the side end portion of the oxide semiconductor 230 is located inside the side end portion of the conductor 240.
  • the present invention is not limited to this.
  • a structure may be adopted in which the side edges of the oxide semiconductor 230 and the side edges of the conductor 240 coincide in the Y direction.
  • a structure may be employed in which the side end portion of the oxide semiconductor 230 is located outside the side end portion of the conductor 240.
  • the band gap of the metal oxide used as the oxide semiconductor 230 is preferably 2 eV or more, more preferably 2.5 eV or more.
  • a metal oxide with a large band gap as the oxide semiconductor 230 off-state current of the transistor can be reduced.
  • a transistor with a small off-state current in a memory cell it is possible to retain stored contents for a long period of time. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced.
  • the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec.
  • the refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
  • oxide semiconductor 230 a metal oxide described in the section [Metal oxide] described below can be used in a single layer or in a stacked layer.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS Inductively Coupled Plasma-Mass Spectrometry
  • ICP-AES Inductively Coupled Plasma-Atomi c Emission Spectrometry
  • analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • a sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide.
  • the composition of the formed metal oxide may be different from the composition of the sputtering target.
  • the content of zinc in the metal oxide after formation may be reduced to about 50% compared to the sputtering target.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), and polycrystalline oxide semiconductors. Examples include semiconductors, single crystal oxide semiconductors, and the like.
  • CAAC-OS c-axis aligned crystalline oxide semiconductor
  • nc-OS nanocrystalline oxide semiconductor
  • polycrystalline oxide semiconductors examples include semiconductors, single crystal oxide semiconductors, and the like.
  • the CAAC-OS has a plurality of layered crystal regions, and the c-axis is oriented in the normal direction of the surface on which it is formed.
  • the oxide semiconductor 230 preferably has a layered crystal that is approximately parallel to the sidewall of the opening 290, particularly the sidewall of the insulator 280. With this structure, the layered crystal of the oxide semiconductor 230 is formed approximately parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.
  • CAAC-OS is a metal oxide that has a highly crystalline, dense structure and has few impurities and defects (for example, oxygen vacancies).
  • heat treatment at a temperature that does not polycrystallize the metal oxide (e.g., 400°C or higher and 600°C or lower) allows CAAC-OS to have a more highly crystalline and dense structure. It can be done. In this way, by further increasing the density of the CAAC-OS, it is possible to further reduce diffusion of impurities or oxygen in the CAAC-OS.
  • CAAC-OS it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Therefore, the metal oxide with CAAC-OS has stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.
  • the oxide semiconductor 230 Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode can be suppressed. As a result, even if heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, so that the transistor 200 is stable against high temperatures (so-called thermal budget) during the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 can be determined by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). n) can be analyzed. Alternatively, analysis may be performed by combining two or more of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 may have a stacked structure of a plurality of oxide layers having different chemical compositions. For example, a structure may be adopted in which a plurality of metal oxides selected from the metal oxides described in the section [Metal oxides] described below are laminated as appropriate.
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b over the oxide semiconductor 230a.
  • the conductivity of the material used for the oxide semiconductor 230a is preferably different from the conductivity of the material used for the oxide semiconductor 230b.
  • a material with higher conductivity than the oxide semiconductor 230b can be used for the oxide semiconductor 230a.
  • a material with high conductivity for the oxide semiconductor 230a that is in contact with the conductor 120 and the conductor 240 that function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 120 and the oxide semiconductor 230 can be reduced.
  • the contact resistance between the conductor 240 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.
  • the threshold voltage of the transistor shifts, and the drain current (hereinafter referred to as (also referred to as cut-off current) may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current is sometimes referred to as normally off.
  • the oxide semiconductor 230 As described above, by forming the oxide semiconductor 230 into a stacked structure and using a material with higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a normally-off transistor with a large on-current can be obtained. . Therefore, it is possible to provide a storage device that has both low power consumption and high performance.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than the carrier concentration of the oxide semiconductor 230b.
  • the conductivity increases, and the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the transistor can have a large on-current.
  • the carrier concentration of the oxide semiconductor 230b By lowering the carrier concentration of the oxide semiconductor 230b, the conductivity is lowered, and a normally-off transistor can be obtained.
  • a material having higher conductivity than the oxide semiconductor 230b is used for the oxide semiconductor 230a; however, one embodiment of the present invention is not limited to this.
  • a material having lower conductivity than the oxide semiconductor 230b may be used for the oxide semiconductor 230a.
  • the carrier concentration of the oxide semiconductor 230a can be lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used for the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used for the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b. Accordingly, the contact resistance between the oxide semiconductor 230 and the conductor 120 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with high on-state current can be obtained. Further, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor 200 can be a normally-off transistor.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide
  • one embodiment of the present invention is not limited to this.
  • the first metal oxide may have a larger band gap than the second metal oxide.
  • the bandgap of the first metal oxide used for the oxide semiconductor 230a can be smaller than the bandgap of the second metal oxide used for the oxide semiconductor 230b.
  • the composition of the first metal oxide is different from the composition of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxide
  • the first metal oxide used for the oxide semiconductor 230a can be an In-Zn oxide
  • the second metal oxide used for the oxide semiconductor 230b can be an In-M-Zn oxide
  • the first metal oxide can be an In-Zn oxide
  • the second metal oxide can be an In-Ga-Zn oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the content rates of elements other than element M may be different.
  • the film thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer constituting the oxide semiconductor 230 may be determined so that the thickness of the oxide semiconductor 230 falls within the above range.
  • the thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 120 and the contact resistance between the oxide semiconductor 230a and the conductor 240 are within required ranges.
  • the thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor is within a required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.
  • the thickness of the oxide semiconductor 230a and the oxide semiconductor 230b is the same at the portion where the upper surface of the conductor 240 is the formation surface, and at the side surface of the conductor 240 and the side surface of the insulator 280.
  • the ratio to the film thickness of the portion to be formed may be different. Note that details will be explained in ⁇ Example 1 of manufacturing method of storage device> described later.
  • FIGS. 8A and 8B show a structure in which the oxide semiconductor 230 has a two-layer stacked structure of an oxide semiconductor 230a and an oxide semiconductor 230b, the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of three or more layers.
  • the on-state current of the transistor 200 can be increased, and a highly reliable transistor structure with little variation can be achieved.
  • the insulators described in the section [Insulator] described below can be used in a single layer or in a laminated manner.
  • silicon oxide or silicon oxynitride can be used as the insulator 250. Silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250 a material with a high dielectric constant described in the section [Insulator] described below, a so-called high-k material, may be used.
  • hafnium oxide or aluminum oxide may be used.
  • the film thickness of the insulator 250 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less.
  • the insulator 250 only needs to have a region with the thickness described above at least in part.
  • the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. This can suppress impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 230.
  • a portion of the insulator 250 is located outside the opening 290, that is, above the conductor 240 and the insulator 280. At this time, it is preferable that the insulator 250 cover the side edges of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented. Further, it is preferable that the insulator 250 covers the side end portions of the conductor 240. This can prevent short-circuiting between the conductor 260 and the conductor 240.
  • the insulator 250 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure.
  • the insulator 250 may have a laminated structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. .
  • the insulator 250b it is preferable to use a material with a low dielectric constant described in the section [Insulator] described below.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250b contains at least oxygen and silicon. With such a configuration, the parasitic capacitance generated between the conductor 260 and the conductor 240 can be reduced. Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.
  • the insulator 250a it is preferable to use an insulator having barrier properties against oxygen as described in the section [Insulator] described below.
  • the insulator 250a has a region in contact with the oxide semiconductor 230. Since the insulator 250a has barrier properties against oxygen, desorption of oxygen from the oxide semiconductor 230 can be suppressed when heat treatment or the like is performed. Therefore, formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. Thereby, the electrical characteristics of the transistor 200 can be improved and reliability can be improved.
  • aluminum oxide may be used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.
  • the insulator 250c it is preferable to use an insulator having barrier properties against hydrogen as described in the section [Insulator] described below. Thereby, diffusion of impurities contained in the conductor 260 into the oxide semiconductor 230 can be suppressed. Silicon nitride has high hydrogen barrier properties and is therefore suitable as the insulator 250c. In this case, the insulator 250c includes at least nitrogen and silicon.
  • the insulator 250c may further have barrier properties against oxygen. Insulator 250c is provided between insulator 250b and conductor 260. Therefore, oxygen contained in the insulator 250b can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Further, a decrease in the amount of oxygen supplied to the region 230i can be suppressed.
  • an insulator may be provided between the insulator 250b and the insulator 250c.
  • the insulator it is preferable to use an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] described below.
  • the insulator hydrogen contained in the oxide semiconductor 230 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • hafnium oxide may be used as the insulator.
  • the insulator contains at least oxygen and hafnium.
  • the insulator may have an amorphous structure.
  • the film thicknesses of the insulators 250a to 250c are preferably thin, and preferably within the above-mentioned range.
  • the film thicknesses of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • FIGS. 8A and 8B show a configuration in which the insulator 250 has a three-layer stacked structure of insulators 250a to 250c, the present invention is not limited to this.
  • the insulator 250 may have a laminated structure of two layers or four or more layers. At this time, each layer included in the insulator 250 may be appropriately selected from the insulators 250a to 250c and an insulator having a function of capturing or fixing hydrogen.
  • the conductor 260 the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 260.
  • the conductor 260 it is preferable to use a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or the like.
  • the conductive material include a conductive material containing nitrogen (eg, titanium nitride or tantalum nitride), a conductive material containing oxygen (eg, ruthenium oxide, etc.), and the like. Thereby, it is possible to suppress the conductivity of the conductor 260 from decreasing.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a stacked structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • FIGS. 8A and 8B show a configuration in which the conductor 260 has a two-layer stacked structure of a conductor 260a and a conductor 260b, the present invention is not limited to this.
  • the conductor 260 may have a laminated structure of three or more layers.
  • the conductor 260 is provided to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductor 260, and a portion of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • a portion of the conductor 260 is located outside the opening 290, that is, above the conductor 240 and the insulator 280.
  • the side end portion of the conductor 260 is preferably located inside the side end portion of the oxide semiconductor 230. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the side end portion of the conductor 260 may coincide with the side end portion of the oxide semiconductor 230, or may be located outside the side end portion of the oxide semiconductor 230.
  • the conductor 120 may be provided as described in the section of [Capacitive element 100].
  • FIGS. 1B and 1C show a configuration in which the upper surface of the conductor 120 is flat
  • the present invention is not limited to this.
  • a configuration may be adopted in which a recessed portion overlapping the opening 290 is formed on the upper surface of the conductor 120.
  • the conductors described in the section [Conductor] described below can be used in a single layer or in a laminated manner.
  • a highly conductive material such as tungsten can be used as the conductor 240.
  • the conductor 240 is also preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion.
  • titanium nitride or tantalum nitride can be used. With such a structure, excessive oxidation of the conductor 240 by the oxide semiconductor 230 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used.
  • a layer containing tungsten in this way, the conductivity of the conductor 240 can be improved and the conductor 240 can function sufficiently as the wiring BL.
  • the conductor 240 has a structure in which a first conductor and a second conductor are laminated
  • the first conductor is formed using a conductive material with high conductivity
  • the second conductor is formed using a conductive material with high conductivity.
  • the conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the conductor 240 in contact with the insulator 250, it is possible to suppress oxygen in the insulator 250 from diffusing into the first conductor of the conductor 240.
  • tungsten may be used as the first conductor of the conductor 240
  • indium tin oxide added with silicon may be used as the second conductor of the conductor 240.
  • the oxide semiconductor 230 and the conductor 120 come into contact, a metal compound or an oxygen vacancy is formed, and the resistance of the region 230na of the oxide semiconductor 230 is reduced.
  • the contact resistance between the oxide semiconductor 230 and the conductor 120 can be reduced.
  • the oxide semiconductor 230 and the conductor 240 are in contact with each other, the resistance of the region 230nb of the oxide semiconductor 230 is reduced. Therefore, contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the dielectric constant is low. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant which is described in the section [Insulator] described later, can be used in a single layer or a laminated form. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 140 and the insulator 280 is reduced. Thereby, impurities such as water and hydrogen can be prevented from entering the channel formation region of the oxide semiconductor 230.
  • the insulator 280 disposed near the channel formation region it is preferable to use an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen).
  • excess oxygen an insulator containing oxygen that is released by heating
  • an insulator having a function of capturing or fixing hydrogen which is described in the section [Insulator] described later, may be used. With such a structure, hydrogen in the oxide semiconductor 230 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • the insulator 280 magnesium oxide, aluminum oxide, or the like can be used.
  • the insulator 280 is shown as a single layer in FIGS. 1B and 1C, the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the insulator 280 may have a laminated structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b. .
  • the insulator 280b preferably has a region containing more oxygen than at least one of the insulators 280a and 280c. In particular, it is preferable that the insulator 280b has a region with a higher oxygen content than each of the insulators 280a and 280c. By increasing the oxygen content of the insulator 280b, an i-type region can be easily formed in a region of the oxide semiconductor 230 that is in contact with the insulator 280b and in the vicinity thereof.
  • the insulator 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, so that oxygen can be supplied to the oxide semiconductor 230.
  • oxygen vacancies and V O H in the oxide semiconductor 230 can be reduced, and good electrical characteristics can be achieved. A highly reliable transistor can be obtained.
  • oxygen can be supplied to the insulator 280b by performing heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen.
  • oxygen may be supplied by forming an oxide film on the upper surface of the insulator 280b in an oxygen atmosphere by a sputtering method. After that, the oxide film may be removed.
  • the insulator 280b is preferably formed by a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a film forming method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • oxygen vacancies in the channel formation region and V OH have a particularly large influence on the electrical characteristics and reliability.
  • insulator having barrier properties against oxygen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c.
  • oxygen contained in the insulator 280b can be prevented from diffusing to the substrate side via the insulator 280a and to the insulator 250 side via the insulator 280c due to heating.
  • oxygen contained in the insulator 280b can be confined. Thereby, oxygen can be effectively supplied to the oxide semiconductor 230.
  • the conductor 120 and the conductor 240 may be oxidized by the oxygen contained in the insulator 280b, resulting in increased resistance.
  • the insulator 280a between the insulator 280b and the conductor 120 it is possible to prevent the conductor 120 from being oxidized and increasing its resistance.
  • the insulator 280c between the insulator 280b and the conductor 240 it is possible to suppress the conductor 240 from being oxidized and increasing its resistance.
  • the amount of oxygen supplied from the insulator 280b to the oxide semiconductor 230 increases, and oxygen vacancies in the oxide semiconductor 230 can be reduced.
  • the amount of oxygen supplied to the region of the oxide semiconductor 230 in contact with the insulator 280a and the region in contact with the insulator 280c is smaller than that in the region in contact with the insulator 280b. Therefore, a region of the oxide semiconductor 230 in contact with the insulator 280a and a region in contact with the insulator 280c may have low resistance. That is, by adjusting the film thickness of the insulator 280a, the range of the region 230na that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulator 280c, the range of the region 230nb functioning as the other of the source region and the drain region can be controlled.
  • the source region and the drain region can be controlled by the film thicknesses of the insulator 280a and the insulator 280c, so the film thicknesses of the insulator 280a and the insulator 280c can be adjusted according to the characteristics required for the transistor 200. You can set it as appropriate.
  • the thickness of the insulator 280c and the thickness of the insulator 280a may be approximately the same.
  • the thickness of the insulator 280c may be smaller than the thickness of the insulator 280a.
  • FIGS. 9C and 9D show a configuration in which an insulator 280c is provided on a flattened insulator 280b
  • the present invention is not limited to this.
  • the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased. Further, the insulator 280a, the insulator 280b, and the insulator 280c can be continuously formed without being exposed to the atmospheric environment.
  • the film By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to prevent impurities or moisture from adhering to the insulators 280a to 280c.
  • the vicinity of the interface between the insulator 280b and the insulator 280c can be kept clean.
  • an insulator having barrier properties against hydrogen as described in the section [Insulator] described later for each of the insulator 280a and the insulator 280c.
  • hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 280a or the insulator 280c.
  • a silicon nitride film and a silicon nitride oxide film are suitable for the insulator 280a and the insulator 280c because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. It can be used for.
  • the insulator 280a and the insulator 280c may be made of the same material or different materials.
  • the insulator 280a it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later.
  • a structure suppresses hydrogen from diffusing into the oxide semiconductor 230 from below the insulator 280a, and further captures or fixes hydrogen in the oxide semiconductor 230 to reduce the hydrogen concentration in the oxide semiconductor 230. Can be reduced. Further, it is possible to suppress hydrogen from diffusing into the insulator 130 from above the insulator 280a, and further capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130.
  • the insulator 280a magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used.
  • insulator 280a a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 280a.
  • an insulator having a function of capturing or fixing hydrogen may be used as the insulator 280c.
  • the film thickness of the insulator 280a is preferably smaller than the film thickness of the insulator 280b. Further, the thickness of the insulator 280c is preferably smaller than the thickness of the insulator 280b.
  • the thickness of the insulator 280a and the insulator 280c is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and even more preferably 3 nm or more and 5 nm or less.
  • the thickness of the insulator 280b is preferably 3 nm or more and 30 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 7 nm or more and 15 nm or less.
  • each of the insulator 280a and the insulator 280c includes at least silicon and nitrogen.
  • the insulator 280b includes at least silicon and oxygen.
  • FIGS. 9A to 9D show a structure in which the insulator 280 has a three-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulator 280 may have a laminated structure of two layers or four or more layers.
  • the insulator 283 it is preferable to use an insulator that has barrier properties against hydrogen and is described in the section [Insulator] described later. Thereby, hydrogen can be suppressed from diffusing into the oxide semiconductor 230 from outside the transistor through the insulator 250.
  • a silicon nitride film and a silicon nitride oxide film are suitable for use as the insulator 283 because they release little impurity (for example, water and hydrogen) from themselves and are difficult for oxygen and hydrogen to pass through. can.
  • the insulator 283 it is preferable to use an insulator that has a function of capturing or fixing hydrogen, which is described in the section [Insulator] described later. With this structure, hydrogen is prevented from diffusing into the oxide semiconductor 230 from above the insulator 283, and hydrogen in the oxide semiconductor 230 is captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor 230. Can be reduced.
  • magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Further, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 283.
  • FIGS. 1B and 1C show a structure in which the upper surface of the conductor 120 and the lower surface of the oxide semiconductor 230 are in contact with each other, the present invention is not limited to this.
  • a conductor may be provided between the conductor 120 and the oxide semiconductor 230.
  • a configuration may be adopted in which a conductor 125 is provided between the conductor 120 and the oxide semiconductor 230.
  • the conductor 125 it is preferable to use an oxygen-containing conductive material described in the "Conductor" section below.
  • a conductive material containing oxygen as the conductor 125, conductivity can be maintained even if the conductor 125 absorbs oxygen. Furthermore, diffusion of oxygen in the oxide semiconductor 230 into the conductor 120 can be suppressed.
  • the conductor 125 for example, indium tin oxide, silicon-added indium tin oxide, indium zinc oxide, or the like can be used in a single layer or in a stacked layer.
  • FIGS. 1B and 1C show a configuration in which the conductor 240 is provided on an insulator 280. Further, a configuration is shown in which a region of the insulator 250 that does not overlap with the conductor 240 has a region in contact with the upper surface of the insulator 280. Note that the present invention is not limited to this.
  • the conductor 240 may be embedded in an insulator 281.
  • the height of the top surface of the conductor 240 preferably matches the height of the top surface of the insulator 281.
  • FIG. 11A is a plan view of the storage device shown in FIGS. 11B and 11C.
  • the insulator 281 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant described in the section [Insulator] described later can be used in a single layer or a laminated form.
  • an insulating substrate for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulator region inside the semiconductor substrate described above such as an SOI (Silicon On Insulator) substrate.
  • the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • substrates containing metal nitrides, substrates containing metal oxides, and the like there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.
  • high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, and oxides containing aluminum and hafnium.
  • examples include nitride, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, and nitride containing silicon and hafnium.
  • materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and resins such as acrylic. Can be mentioned.
  • inorganic insulating materials having a low dielectric constant include, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen. Further, for example, silicon oxide having pores may be used. Note that these silicon oxides may contain nitrogen.
  • insulators having the function of suppressing permeation of impurities and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, Insulators including neodymium, hafnium, or tantalum can be used in single layers or in stacks.
  • insulators that have the function of suppressing the permeation of impurities and oxygen include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc.
  • Metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • an insulator such as a gate insulator that is in contact with the semiconductor layer or an insulator provided near the semiconductor layer is an insulator that has a region containing excess oxygen.
  • oxygen vacancies in the semiconductor layer can be reduced by providing a structure in which an insulator having a region containing excess oxygen is in contact with the semiconductor layer or in the vicinity of the semiconductor layer.
  • insulators that can easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • Insulators with barrier properties against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, and indium gallium. Examples include zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulators having barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to be an insulator that has a barrier property against one or both of oxygen and hydrogen.
  • examples of the insulator having the function of capturing or fixing hydrogen include an oxide containing magnesium, or an oxide containing one or both of aluminum and hafnium. Moreover, it is more preferable that these oxides have an amorphous structure. In an oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may capture or fix hydrogen. Note that these metal oxides preferably have an amorphous structure, but a crystalline region may be formed in part.
  • barrier insulating film refers to an insulating film having barrier properties.
  • barrier property refers to the property that the corresponding substance is difficult to diffuse (also referred to as the property that the corresponding substance is difficult to permeate, the property that the corresponding substance has low permeability, or the ability to suppress the diffusion of the corresponding substance). do.
  • the function of capturing or fixing a corresponding substance can be referred to as barrier property.
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities described as corresponding substances refer to impurities in the channel forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, oxidation Refers to at least one of nitrogen molecules ( N2O , NO, NO2, etc.), copper atoms, etc.
  • oxygen refers to at least one of, for example, an oxygen atom or an oxygen molecule.
  • the barrier property against oxygen refers to the property that at least one of oxygen atoms, oxygen molecules, etc. is difficult to diffuse.
  • Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the following, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • nitrides containing tantalum nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, etc.
  • a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen is preferable.
  • conductive materials containing oxygen indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium Examples include zinc oxide and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen is sometimes referred to as an oxide conductive film.
  • conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a plurality of conductive layers formed of the above materials may be stacked and used.
  • a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • the conductor that functions as the gate electrode has a stacked structure that combines a material containing the aforementioned metal element and a conductive material containing oxygen. It is preferable. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode.
  • a conductive material containing the aforementioned metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • one or more of the added indium tin oxides may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include atomic vacancies, point defects such as foreign atoms, line defects such as dislocations, planar defects such as crystal grain boundaries, and volume defects such as voids.
  • factors for the generation of lattice defects include a deviation in the ratio of the number of atoms of constituent elements (excess or deficiency of constituent atoms), impurities, and the like.
  • the metal oxide used for the semiconductor layer of the transistor preferably has few lattice defects.
  • the channel forming region in the metal oxide has a reduced carrier concentration and is made i-type (intrinsic) or substantially i-type.
  • the type of lattice defects that are likely to exist in a metal oxide and the amount of lattice defects that exist vary depending on the structure of the metal oxide, the method of forming a metal oxide film, etc.
  • the structure of metal oxides can be divided into single crystal structure and other structures (non-single crystal structure).
  • non-single crystal structures include a CAAC structure, a polycrystalline structure, a nc structure, an amorphous-like (a-like) structure, and an amorphous structure.
  • the a-like structure has a structure between an nc structure and an amorphous structure. Note that the classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have cavities or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. Further, a metal oxide having an a-like structure has a higher hydrogen concentration than a metal oxide having an nc structure and a metal oxide having a CAAC structure. Therefore, lattice defects are likely to be generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a highly crystalline metal oxide for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using the metal oxide in a transistor, a transistor with good electrical characteristics can be realized. Furthermore, a highly reliable transistor can be realized.
  • a metal oxide that increases the on-state current of the transistor for the channel formation region of the transistor.
  • the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). At this time, the c-axis of the crystal is oriented in the direction in which a plurality of layers are stacked.
  • metal oxides having such crystals include single-crystal oxide semiconductors, CAAC-OS, and the like.
  • the c-axis of the crystal is oriented in the normal direction to the surface on which the metal oxide is formed or the film surface.
  • the plurality of layers are arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. That is, the multiple layers extend in the channel length direction.
  • the three-layered crystal structure described above has the following structure.
  • the first layer has an octahedral atomic coordination structure of oxygen in which the metal of the first layer is located at the center.
  • the second layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the second layer exists at the center.
  • the third layer has a trigonal bipyramidal or tetrahedral atomic coordination structure of oxygen in which the metal of the third layer exists at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first to third layers is preferably composed of one metal element or a plurality of metal elements having the same valence and oxygen.
  • the valence of one or more metal elements forming the first layer is the same as the valence of one or more metal elements forming the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of one or more metal elements forming the first layer is different from the valence of one or more metal elements forming the third layer.
  • the crystallinity of the metal oxide can be improved and the carrier mobility of the metal oxide can be increased. Therefore, by using the metal oxide in a channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable.
  • the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification, etc. may include semimetal elements.
  • Examples of the metal oxide semiconductor of one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), Indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (also written as Al-Zn oxide, AZO), indium aluminum zinc oxide (also written as In-Al-Zn oxide, IAZO), indium tin zinc oxide (In -Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In -Ga-Sn-Zn oxide (also referred to as IGZTO), indium gallium aluminum zinc oxide (In-G
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements.
  • the metal oxide may contain one or more metal elements having a large periodic number in the periodic table of elements. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large periodic number in the periodic table of elements, it may be possible to increase the field effect mobility of the transistor. Examples of metal elements with large period numbers in the periodic table of elements include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. . Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • an In-Ga-Zn oxide may be used as an example of the metal oxide.
  • the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method, it is easy to form a metal oxide having the above-described layered crystal structure.
  • Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.
  • a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy
  • PEALD plasma enhanced ALD
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has advantages such as being able to form an excellent film and being able to form a film at a low temperature. Further, the PEALD method may be preferable because it can form a film at a lower temperature by using plasma. Note that some precursors used in the ALD method include elements such as carbon or chlorine. For this reason, a film formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that these elements can be quantified using XPS or secondary ion mass spectrometry (SIMS).
  • the method for forming a metal oxide film of one embodiment of the present invention uses an ALD method
  • one or both of the conditions of high substrate temperature during film formation and the implementation of impurity removal treatment may be applied.
  • the amount of carbon and chlorine contained in the film may be smaller than when ALD is used without applying these.
  • the ALD method is a film-forming method in which a film is formed by a reaction on the surface of an object, unlike a film-forming method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as sputtering or CVD, which have a high film formation rate.
  • a method may be used in which a first metal oxide is formed into a film using a sputtering method, and a second metal oxide is formed into a film using an ALD method on the first metal oxide.
  • the second metal oxide may grow crystals using the crystal part as a nucleus.
  • the composition of the resulting film can be controlled by the amount of raw material gas introduced.
  • the amount of raw material gas introduced it is possible to form a film of any composition by adjusting the amount of raw material gas introduced, the number of times it is introduced (also called the number of pulses), the time required for one pulse (also called pulse time), etc. can.
  • the ALD method by changing the raw material gas during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation can be shortened by eliminating the time required for transport and pressure adjustment. can. Therefore, it may be possible to increase the productivity of the storage device.
  • transistor with metal oxide a transistor using an oxide semiconductor for a semiconductor layer is sometimes referred to as an OS transistor, and a transistor using silicon for a semiconductor layer is sometimes referred to as an Si transistor.
  • a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • Si transistors As transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors.
  • SCE short channel effect
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it can have good electrical characteristics even if the OS transistor is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have superior effects compared to Si transistors, such as lower off-state current and the ability to manufacture transistors with shorter channel lengths.
  • the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms /cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 3 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 1 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, still more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , even more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be referred to as a semiconductor layer including a channel formation region of a transistor.
  • Semiconductor materials that can be used for the semiconductor layer are not limited to the metal oxides mentioned above.
  • a semiconductor material having a band gap semiconductor material that is not a zero-gap semiconductor may be used as the semiconductor layer.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of single element semiconductors that can be used as semiconductor materials include silicon and germanium.
  • Examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • Boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • Boron arsenide that can be used in the semiconductor layer preferably contains crystals with a cubic crystal structure.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride as a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • a chalcogenide is a compound containing chalcogen.
  • chalcogen is a general term for elements belonging to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as a semiconductor layer include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), Tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically Examples include HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • Example 1 of manufacturing method of storage device a method for manufacturing the storage device shown in FIGS. 1A to 1C, which is one embodiment of the present invention, will be described with reference to FIGS. 12A to 22C.
  • a in each figure indicates a plan view.
  • B in each figure is a sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure.
  • C in each figure is a sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure.
  • some elements are omitted for clarity of the figure.
  • an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor is used by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the film can be formed using a method such as the following.
  • sputtering methods include an RF sputtering method that uses a high frequency power source as a sputtering power source, a DC sputtering method that uses a DC power source, and a pulsed DC sputtering method that changes the voltage applied to the electrode in a pulsed manner.
  • the RF sputtering method is mainly used when forming an insulating film
  • the DC sputtering method is mainly used when forming a metal conductive film.
  • the pulsed DC sputtering method is mainly used when forming a film of a compound such as an oxide, nitride, or carbide by a reactive sputtering method.
  • the CVD method can be classified into a plasma CVD (PECVD) method that uses plasma, a thermal CVD (TCVD) method that uses heat, a photo CVD (Photo CVD) method that uses light, etc. Furthermore, depending on the raw material gas used, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
  • PECVD plasma CVD
  • TCVD thermal CVD
  • Photo CVD Photo CVD
  • MCVD metal CVD
  • MOCVD metal organic CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a memory device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the memory device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of memory devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.
  • the ALD method a thermal ALD method in which a reaction between a precursor and a reactant is performed using only thermal energy, a PEALD method in which a plasma-excited reactant is used, etc. can be used.
  • the CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.
  • a film of any composition can be formed by changing the flow rate ratio of source gases.
  • the flow rate ratio of source gases by changing the flow rate ratio of source gases during film formation, it is possible to form a film whose composition changes continuously.
  • the time required for film formation is reduced because it does not require time for transport or pressure adjustment. can do. Therefore, it may be possible to increase the productivity of the storage device.
  • a film of any composition can be formed by introducing a plurality of different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles for each precursor.
  • the type of oxidizing agent may be changed depending on each precursor. For example, when introducing at least a first precursor and a second precursor, ozone (O 3 ) is used as an oxidizing agent for the first precursor, and oxygen (O 3 ) is used as an oxidizing agent for the second precursor. O 2 ) may also be used.
  • heat treatment may be performed before forming the film.
  • the heat treatment may be performed under reduced pressure to form the film continuously without exposure to the atmosphere. By performing such treatment, it is possible to remove moisture and hydrogen adsorbed on the surface on which the film is formed, and further reduce the moisture concentration and hydrogen concentration in the structure, which is the surface on which the film is formed.
  • the temperature of the heat treatment is preferably 100°C or more and 400°C or less.
  • a substrate (not shown) is prepared, and an insulator 140 is formed on the substrate (see FIGS. 12A to 12C).
  • an insulator 140 any of the above-mentioned insulating materials may be used as appropriate.
  • the insulator 140 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductor 110 is formed on the insulator 140.
  • the above-mentioned conductive material may be used as appropriate.
  • the conductor 110 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film of tungsten and titanium nitride may be formed in this order using a CVD method.
  • the conductor 110 may be processed into a shape that extends in the X direction or the Y direction.
  • the conductor 110 may be processed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication. By performing this processing, the side end portions of the conductor 110 are covered with an insulator 130 that will be formed later.
  • a resist mask is formed by removing or leaving the exposed area using a developer.
  • a conductor, semiconductor, insulator, or the like can be processed into a desired shape.
  • a resist mask may be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by performing dry etching treatment such as ashing, wet etching treatment, wet etching treatment after dry etching treatment, or dry etching treatment after wet etching treatment.
  • a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used as the dry etching device.
  • a capacitively coupled plasma etching apparatus having parallel plate electrodes may have a configuration in which a high frequency voltage is applied to one electrode of the parallel plate electrodes.
  • a configuration may be adopted in which a plurality of different high frequency voltages are applied to one electrode of a parallel plate type electrode.
  • a configuration may be adopted in which a high frequency voltage of the same frequency is applied to each of the parallel plate type electrodes.
  • a configuration may be adopted in which high frequency voltages having different frequencies are applied to each of the parallel plate type electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • the dry etching device having a high-density plasma source for example, an inductively coupled plasma (ICP) etching device or the like can be used.
  • ICP inductively coupled plasma
  • an insulator 180 is formed on the conductor 110 (see FIGS. 12A to 12C).
  • the insulating material described above may be used as appropriate for the insulator 180.
  • the insulator 180 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 180 is preferably subjected to CMP treatment after film formation to flatten the upper surface. Note that there are cases where it is not necessary to perform CMP processing. At this time, the upper surface of the insulator 180 has an upwardly convex curved shape. By not performing planarization treatment, manufacturing costs can be lowered and production yields can be increased.
  • the film thickness of the insulator 180 corresponds to the capacitance of the capacitive element 100
  • the film thickness of the insulator 180 may be appropriately set according to the design value of the capacitance of the capacitive element 100.
  • the hydrogen concentration in the insulator 180 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas.
  • the opening 190 may be formed using a lithography method.
  • the shape of the opening 190 is circular in plan view, it is not limited to this.
  • the shape of the opening 190 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
  • the side wall of the opening 190 is preferably perpendicular to the top surface of the conductor 110. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Note that the side wall of the opening 190 may have a tapered shape. By tapering the side wall of the opening 190, the coverage of a conductive film, which will be described later as a conductor 115, can be improved, and defects such as holes can be reduced.
  • the maximum width (diameter if the opening 190 is circular in plan view) of the opening 190 is minute.
  • the maximum width of the opening 190 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening 190 has a large aspect ratio, it is preferable to process a part of the insulator 180 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing.
  • a conductive film that will become the conductor 115 is formed in contact with the bottom and sidewalls of the opening 190 and at least a portion of the top surface of the insulator 180.
  • a conductor that can be used as the conductor 115 described above may be used as appropriate.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film is preferably formed in contact with the bottom and sidewalls of the opening 190 having a large aspect ratio.
  • a film forming method with good coverage it is preferable to use a CVD method, an ALD method, or the like.
  • a titanium nitride film may be formed as the conductive film using a CVD method.
  • the conductive film that will become the conductor 115 is processed using a lithography method to form the conductor 115 (see FIGS. 14A to 14C). As a result, a portion of the conductor 115 is formed in the opening 190. Further, the conductor 115 is in contact with a portion of the side surface and the top surface of the insulator 180.
  • an insulator 130 is formed on the conductor 115 and the insulator 180 (see FIGS. 15A to 15C).
  • the above-mentioned high-k material or a material capable of having ferroelectricity may be used as appropriate.
  • the insulator 130 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film of zirconium oxide, aluminum oxide, and zirconium oxide may be formed in this order using an ALD method.
  • a conductive film 120A is formed on the insulator 130 (see FIGS. 15A to 15C).
  • the conductive material described above may be used for the conductive film 120A.
  • the conductive film 120A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a stacked film of titanium nitride and tantalum nitride may be formed in this order using a CVD method.
  • a stacked film in which titanium nitride and tungsten are deposited in this order may be formed using a CVD method.
  • the conductive film 120A is processed to form the conductor 120 (see FIGS. 16A to 16C).
  • the conductor 120 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 120A. Processing by dry etching is suitable for microfabrication.
  • the capacitive element 100 including the conductor 115, the insulator 130, and the conductor 120 can be formed.
  • an insulator 280 is formed on the insulator 130 and the conductor 120 (see FIGS. 17A to 17C).
  • the insulating material described above may be used as appropriate for the insulator 280.
  • the insulator 280 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 280 is preferably subjected to CMP treatment after film formation to flatten the upper surface. By performing planarization treatment on the insulator 280, the conductor 240 functioning as a wiring can be suitably formed.
  • CMP treatment may be performed until the insulator 280 is reached.
  • the surface of the insulator 280 can be flattened and smoothed.
  • the upper surface of the insulator 280 has an upwardly convex curved shape.
  • the planarization process is not necessarily performed after forming all the insulators.
  • planarization treatment may be performed, and then the insulator 280c may be formed.
  • an aluminum oxide film is first formed on the insulator 280b etc. by a sputtering method, and then The aluminum oxide film may be removed by performing heat treatment and then CMP treatment. Through this step, more regions containing excess oxygen can be formed in the insulator 280b. Note that in this step, part of the insulator 280b may be removed. Further, this step may be performed before the planarization process of the insulator 280b is performed, or may be performed after the planarization process of the insulator 280b is performed.
  • the film thickness of the insulator 280 on the conductor 120 corresponds to the channel length of the transistor 200
  • the film thickness of the insulator 280 may be appropriately set according to the design value of the channel length of the transistor 200. .
  • the insulator 280 by forming the insulator 280 by a sputtering method in an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. By forming the insulator 280 in this manner, oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and V OH can be reduced.
  • a conductive film 240A is formed on the insulator 280 (see FIGS. 17A to 17C).
  • the conductive material described above may be used as appropriate for the conductive film 240A.
  • the conductive film 240A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the opening 290 may be formed using a lithography method.
  • the shape of the opening 290 shown in FIG. 18A is circular in plan view, it is not limited to this.
  • the shape of the opening 290 may be a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners when viewed from above.
  • the side wall of the opening 290 is preferably perpendicular to the top surface of the conductor 110. With such a configuration, it is possible to miniaturize or highly integrate the memory device. Further, the side wall of the opening 290 may have a tapered shape. By tapering the sidewall of the opening 290, coverage of an oxide semiconductor film or the like that becomes the oxide semiconductor 230 (described later) can be improved, and defects such as holes can be reduced.
  • the maximum width (maximum diameter when the opening 290 is circular in plan view) of the opening 290 is minute.
  • the maximum width of the opening 290 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and preferably 1 nm or more, or 5 nm or more.
  • the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive film 240A and a part of the insulator 280 using anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Further, the processing may be performed under different conditions. Note that depending on the conditions for processing a portion of the conductive film 240A and a portion of the insulator 280, as described above, the slope of the side surface of the conductor 240 at the opening 290 and the slope of the insulator 280 at the opening 290 may vary. The slopes of the sides may differ from each other.
  • heat treatment may be performed.
  • the heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • impurities such as water contained in the insulator 280 and the like can be reduced before forming an oxide semiconductor film that will become the oxide semiconductor 230 described later.
  • oxygen can be supplied to the insulator 280.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductive film 240A.
  • a metal oxide that can be used for the oxide semiconductor 230 described above may be used as appropriate.
  • the oxide semiconductor film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the oxide semiconductor film is preferably formed in contact with the bottom and sidewalls of the opening 290 having a large aspect ratio.
  • the oxide semiconductor film it is preferable to use a film forming method with good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a CVD method an ALD method, or the like.
  • an In-Ga-Zn oxide may be formed using an ALD method. Note that the details of the method for forming a metal oxide film using the ALD method will be described in the embodiment described later.
  • the method for forming the oxide semiconductor film that becomes the oxide semiconductor 230 is not limited to the CVD method or the ALD method.
  • a sputtering method may be used.
  • the deposition methods for each layer included in the oxide semiconductor 230 may be the same or different.
  • the lower layer of the oxide semiconductor film (the oxide semiconductor 230a shown in FIGS. 8A and 8B) is formed by a sputtering method
  • the upper layer of the oxide semiconductor film ( The oxide semiconductor 230b shown in FIGS. 8A and 8B) may be formed by an ALD method.
  • An oxide semiconductor film formed using a sputtering method tends to have crystallinity.
  • the crystallinity of the upper layer of the oxide semiconductor film can be improved. Furthermore, even if pinholes or step breaks are formed in the lower layer of the oxide semiconductor film formed by the sputtering method, the oxide semiconductor film formed by the ALD method, which has good coverage, can cover the overlapping portions. It can be closed with the upper layer of
  • the oxide semiconductor 230a is formed by a sputtering method and the oxide semiconductor 230b is formed by an ALD method
  • the upper surface of the conductor 240 is the surface on which the oxide semiconductor 230a and the oxide semiconductor 230b are formed.
  • the film thickness of the portion (hereinafter referred to as the first film thickness), and the film thickness of the portion where the side surfaces of the conductor 240 and the side surfaces of the insulator 280 are the formation surfaces (hereinafter referred to as the second film thickness).
  • the ratio may be different.
  • the ratio of the second thickness to the first thickness can be 1 or a value close to 1.
  • the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5.
  • the impurity concentration in the oxide semiconductor 230a is lower than the impurity concentration in the oxide semiconductor 230b. may also become lower. Therefore, in the oxide semiconductor 230, the impurity concentration in the film is low from the conductor 260 side toward the conductor 120 side, and there is a possibility that the impurity concentration in the film has a concentration gradient.
  • impurities in the film of the oxide semiconductor 230 include one or more selected from hydrogen, nitrogen, and carbon.
  • the oxide semiconductor film serving as the oxide semiconductor 230 covers the top surface of the conductor 120 in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the conductor 240 in the opening 290, and the side surface of the conductor 240 in the opening 290. Preferably, it is formed in contact with the upper surface.
  • the oxide semiconductor film in contact with the conductor 120 the conductor 120 functions as one of a source electrode and a drain electrode of the transistor 200.
  • the conductor 240 functions as the other of the source electrode and the drain electrode of the transistor 200.
  • the heat treatment may be performed at a temperature range in which the oxide semiconductor film does not become polycrystalline, and may be performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas.
  • the oxygen gas content may be about 20%.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of water contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the heat treatment is preferably performed with the insulator 280 containing excess oxygen provided in contact with the oxide semiconductor film.
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 230, and oxygen vacancies and VoH can be reduced.
  • heat treatment was performed after the oxide semiconductor film was formed, but the present invention is not limited to this.
  • a configuration may also be adopted in which heat treatment is performed in a later step.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 19A to 19C). As a result, part of the oxide semiconductor 230 is formed in the opening 290. Further, the oxide semiconductor 230 is in contact with a part of the side surface and the top surface of the conductor 240. Therefore, the area of the region where the oxide semiconductor 230 and the conductor 240 are in contact can be increased.
  • the conductive film 240A is processed to form the conductor 240 (see FIGS. 20A to 20C).
  • the conductor 240 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used to process the conductive film 240A. Processing by dry etching is suitable for microfabrication.
  • etching method with a high selectivity to the insulator 280 an etching method using the insulator 280 as a stop film.
  • etching method using the insulator 280 it is preferable to increase the etching selectivity between the conductive film 240A and the insulator 280c.
  • the insulator 280 has a laminated structure of an insulator 280a, an insulator 280b, an insulator 280c, and an insulator containing silicon oxide on the insulator 280c. Note that the side edge of the insulator may coincide with the side edge of the insulator 280 or the side edge of the conductor 240.
  • the method is the same as described above until the conductive film 240A shown in FIGS. 17A to 17C is formed.
  • the conductive film 240A is processed to form the conductor 240.
  • the above description can be referred to.
  • a part of the conductor 240 and a part of the insulator 280 are processed to form an opening 290 that reaches the conductor 120.
  • the above description can be referred to.
  • heat treatment may be performed.
  • the conditions of the heat treatment, etc. the above explanation can be referred to.
  • an oxide semiconductor film that will become the oxide semiconductor 230 is formed in contact with the bottom and sidewalls of the opening 290 and at least a portion of the top surface of the conductor 240. At this time, the oxide semiconductor film has a region in contact with the upper surface of the insulator 280.
  • the above description can be referred to.
  • the oxide semiconductor film that will become the oxide semiconductor 230 is processed using a lithography method to form the oxide semiconductor 230 (see FIGS. 20A to 20C).
  • an insulator 250 is formed over the oxide semiconductor 230, the conductor 240, and the insulator 280 (see FIGS. 21A to 21C).
  • the insulator 250 any of the above-mentioned insulating materials may be used as appropriate.
  • the insulator 250 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the insulator 250 is preferably formed in contact with the oxide semiconductor 230 provided in the opening 290 with a large aspect ratio.
  • the insulator 250 it is preferable to use a film forming method that provides good coverage, and it is more preferable to use a CVD method, an ALD method, or the like.
  • silicon oxide may be formed as the insulator 250 using an ALD method.
  • the method for forming the insulator 250 is not limited to the CVD method or the ALD method.
  • a sputtering method may be used.
  • the side edges of the oxide semiconductor 230 are covered with the insulator 250. Therefore, short circuit between the oxide semiconductor 230 and the conductor 260 can be prevented. Furthermore, with the above configuration, the side end portions of the conductor 240 are covered with the insulator 250. Therefore, short circuit between the conductor 240 and the conductor 260 can be prevented.
  • a conductive film 260A is formed to fill the recesses of the insulator 250 (see FIGS. 21A to 21C).
  • the conductive material described above may be used as appropriate for the conductive film 260A.
  • the conductive film 260A may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the conductive film 260A is preferably formed in contact with the insulator 250 provided in the opening 290 having a large aspect ratio.
  • the conductive film 260A it is preferable to use a film forming method that provides good coverage or embeddability, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a CVD method an ALD method
  • titanium nitride may be formed as the conductive film 260A using a CVD method or an ALD method.
  • the conductive film 260A is formed using the CVD method, the average surface roughness of the upper surface of the conductive film 260A may become large. In this case, it is preferable to planarize the conductive film 260A using a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed over the conductive film 260A, and the CMP treatment may be performed until the silicon oxide film or silicon oxynitride film is removed.
  • the conductive film 260A is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the center of the conductive film 260A.
  • the recess may be filled with an inorganic insulating material or the like.
  • the conductor 260 is processed to form the conductor 260 (see FIGS. 22A to 22C).
  • the conductor 260 may be formed using a lithography method.
  • a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for microfabrication.
  • the side end portion of the conductor 260 is located inside the side end portion of the oxide semiconductor 230 in plan view. Thereby, short circuit between the conductor 260 and the oxide semiconductor 230 can be prevented.
  • the transistor 200 including the conductor 120, the conductor 240, the oxide semiconductor 230, the insulator 250, and the conductor 260 can be formed.
  • an insulator 283 is formed to cover the conductor 260 and the insulator 250.
  • the above-mentioned insulating material may be used as appropriate.
  • the insulator 283 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a memory device having the memory cell 150 shown in FIGS. 1A to 1C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 illustrated in FIGS. 1A to 1C can be manufactured.
  • Example 2 of manufacturing method of storage device> Next, a method for manufacturing a memory device shown in FIGS. 11A to 11C, which is one embodiment of the present invention, will be described. Note that for the steps up to forming the insulator 280, the description in ⁇ Example 1 of manufacturing method of memory device> described above can be referred to.
  • An insulator 281 is formed on the insulator 280.
  • the above-mentioned insulating material may be used as appropriate.
  • the insulator 281 may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a silicon oxide film may be formed using a sputtering method.
  • the insulator 281 is preferably subjected to CMP treatment after film formation to flatten the upper surface.
  • an opening reaching the insulator 280 is formed in the insulator 281. Since the conductor 240 functioning as a wiring is formed inside the opening, the opening may be provided extending in the X direction.
  • the opening may be formed using a lithography method. Further, a dry etching method or a wet etching method can be used for etching the opening. Processing by dry etching is suitable for microfabrication.
  • the insulator 280 may have a laminated structure, and an insulator functioning as an etching stopper film may be provided on the uppermost surface of the insulator 280.
  • the insulator corresponds to the insulator 280c in the configuration shown in FIGS. 9A and 9B.
  • silicon oxide or silicon oxynitride is used for the insulator 281 forming the opening
  • silicon nitride, aluminum oxide, hafnium oxide, or the like may be used as the etching stopper film.
  • a conductive film that will become the conductor 240 is formed so as to fill the opening formed in the insulator 281.
  • the above-mentioned conductive material may be appropriately used for the conductive film.
  • the conductive film may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • a laminated film in which tantalum nitride and tungsten are deposited in this order may be formed using a sputtering method.
  • the conductor 240 may be formed by performing CMP treatment on the conductive film until the upper surface of the insulator 281 is exposed.
  • a memory device having the memory cell 150 shown in FIGS. 11A to 11C can be manufactured. Further, a memory device including the transistor 200 and the capacitor 100 illustrated in FIGS. 11A to 11C can be manufactured.
  • a new transistor, a new semiconductor device, and a new memory device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a storage device with good frequency characteristics can be provided.
  • a storage device with high operating speed can be provided.
  • a highly reliable storage device can be provided.
  • a storage device with low power consumption can be provided.
  • a memory device including a transistor with a large on-state current can be provided.
  • a memory device with less variation in transistor characteristics can be provided.
  • a storage device with good electrical characteristics can be provided.
  • the memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, it is possible to retain stored contents for a long period of time by using the transistor 200 in a memory device. In other words, since no refresh operation is required or the frequency of refresh operations is extremely low, power consumption of the storage device can be sufficiently reduced. Further, since the transistor 200 has high frequency characteristics, reading and writing to the memory device can be performed at high speed.
  • FIG. 23A is a plan view of the storage device.
  • FIG. 23B is a cross-sectional view of a portion shown by a dashed line A1-A2 in FIG. 23A. Note that in the plan view of FIG. 23A, some elements are omitted for clarity.
  • each of the memory cell 150a and the memory cell 150b shown in FIGS. 23A and 23B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b. Therefore, in the storage devices shown in FIGS. 23A and 23B, structures having the same functions as the structures configuring the storage devices shown in FIGS. 1A to 1C are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • the conductor 260 functioning as the wiring WL is provided in the memory cell 150a and the memory cell 150b, respectively. Further, a conductor 240 that functions as a part of the wiring BL is provided in common to the memory cell 150a and the memory cell 150b. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of the memory cell 150a and the oxide semiconductor 230 of the memory cell 150b.
  • the memory device shown in FIGS. 23A and 23B includes a conductor 245 and a conductor 246 that are electrically connected to the memory cell 150a and the memory cell 150b and function as a plug (also referred to as a connection electrode).
  • the conductor 245 is disposed within the openings formed in the insulator 180, the insulator 130, the insulator 280, and the insulator 140, and is in contact with the lower surface of the conductor 240.
  • the conductor 246 is disposed within the openings formed in the insulator 287, the insulator 283, and the insulator 250, and is in contact with the upper surface of the conductor 240. Note that for the conductor 245 and the conductor 246, a conductive material that can be used for the conductor 240 can be used.
  • the dielectric constant is low.
  • an insulator containing a material with a low dielectric constant described in the above-mentioned [Insulator] item can be used in a single layer or a laminated form.
  • the concentration of impurities such as water and hydrogen in the insulator 287 is reduced. Thereby, impurities such as water and hydrogen can be suppressed from entering the channel formation region of the oxide semiconductor 230.
  • the conductor 245 and the conductor 246 electrically connect the memory cell 150a and the memory cell 150b to circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistance elements, and diodes. Acts as a plug or wiring for.
  • the conductor 245 is electrically connected to a sense amplifier (not shown) provided below the storage device shown in FIGS. 23A and 23B, and the conductor 246 is connected to the storage device shown in FIGS. 23A and 23B. It can be configured to be electrically connected to a similar storage device (not shown) provided above. In this case, the conductor 245 and the conductor 246 function as part of the wiring BL. In this way, by providing a storage device or the like above or below the storage device shown in FIGS. 23A and 23B, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150b have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200b are also arranged in line-symmetrical positions with the conductor 245 and the conductor 246 in between.
  • the conductor 240 has a function as the other of the source electrode and the drain electrode of the transistor 200a, and a function as the other of the source electrode and the drain electrode of the transistor 200b.
  • the transistor 200a and the transistor 200b share a conductor 245 and a conductor 246 that function as a plug. In this way, by connecting the two transistors and the plug to the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • the conductor 110 functioning as the wiring PL may be provided in each of the memory cell 150a and the memory cell 150b, or may be provided in common with the memory cell 150a and the memory cell 150b. However, as shown in FIG. 23B, the conductor 110 is provided apart from the conductor 245 to prevent short circuit between the conductor 110 and the conductor 245.
  • a memory cell array can be configured by arranging the memory cells 150 three-dimensionally in a matrix.
  • FIGS. 24A and 24B show an example of a memory device in which 4 ⁇ 2 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 24A is a plan view of the storage device.
  • FIG. 24B is a cross-sectional view of a portion shown by a dashed line A1-A2 in FIG. 24A. Note that in the plan view of FIG. 24A, some elements are omitted for clarity.
  • each of the memory cells 150a to 150d shown in FIGS. 24A and 24B has the same configuration as the memory cell 150.
  • the memory cell 150a includes a capacitor 100a and a transistor 200a
  • the memory cell 150b includes a capacitor 100b and a transistor 200b
  • the memory cell 150c includes a capacitor 100c and a transistor 200c
  • the memory cell 150d includes: It has a capacitive element 100d and a transistor 200d. Therefore, in the storage devices shown in FIGS. 24A and 24B, structures having the same functions as the structures configuring the storage devices shown in FIGS. 1A to 1C are given the same reference numerals. Note that also in this item, the materials described in detail in ⁇ Example of configuration of storage device> can be used as the constituent materials of the storage device.
  • FIGS. 24A and 24B includes memory units 160[1,1] to 160[2,4].
  • the memory units 160[1,1] to 160[2,4] may be collectively referred to as the memory unit 160.
  • Memory unit 160[1,2] is provided on memory unit 160[1,1]
  • memory unit 160[1,3] is provided on memory unit 160[1,2]
  • memory unit 160[1,3] is provided on memory unit 160[1,2].
  • 1,4] are provided on the memory unit 160[1,3].
  • Memory unit 160[2,1] is provided adjacent to memory unit 160[1,1] in the Y direction.
  • Memory unit 160[2,2] is provided on memory unit 160[2,1]
  • memory unit 160[2,3] is provided on memory unit 160[2,2]
  • memory unit 160[2,2] is provided on memory unit 160[2,2].
  • 160[2,4] is provided above memory unit 160[2,3].
  • a memory cell 150c is arranged outside the memory cell 150a, and a memory cell 150d is arranged outside the memory cell 150b, with the conductor 245 at the center.
  • the memory device shown in FIGS. 23A and 23B is a memory device in which the memory cell 150c is provided adjacent to the memory cell 150a, and the memory cell 150d is provided adjacent to the memory cell 150b.
  • the conductor 260 functioning as the wiring WL is shared by memory cells 150 adjacent to each other in the Y direction. Furthermore, the conductor 240 that functions as part of the wiring BL is shared within the same memory unit. In other words, the conductor 240 is in contact with the oxide semiconductor 230 of each of the memory cells 150a to 150d.
  • a conductor 245 is provided between conductors 240 of memory units adjacent in the Z direction.
  • the conductor 245 is provided in contact with the upper surface of the conductor 240 of the memory unit 160[1,1] and the lower surface of the conductor 240 of the memory unit 160[1,2].
  • the wiring BL is formed by the conductor 240 and the conductor 245 provided in each memory unit 160.
  • the conductor 245 is electrically connected to a sense amplifier (not shown) provided below the memory device shown in FIGS. 24A and 24B. In this way, in the storage device shown in FIGS. 24A and 24B, by stacking a plurality of memory units, the storage capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150c, and the memory cell 150b and the memory cell 150d have a line-symmetric configuration with the perpendicular bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Therefore, the transistor 200a and the transistor 200c, and the transistor 200b and the transistor 200d are also arranged in line-symmetrical positions with the conductor 245 in between.
  • the conductor 240 functions as the other of the source electrode and drain electrode of each of the transistors 200a to 200d.
  • the transistors 200a to 200d share a conductor 245 that functions as a plug. In this way, by connecting the four transistors and the plugs in the above-described configuration, it is possible to provide a memory device that can be miniaturized or highly integrated.
  • FIG. 24B by stacking a plurality of memory cells, cells can be arranged in an integrated manner without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be configured.
  • FIGS. 24A and 24B illustrate a configuration in which four layers each having two memory units are stacked, the present invention is not limited to this.
  • the memory device may have one layer having at least one memory cell 150, or may have two or more layers stacked.
  • 24A and 24B show a configuration in which a conductor 245 functioning as a plug is arranged between memory cells 150. In other words, a configuration is shown in which the conductor 245 functioning as a plug is arranged inside the memory unit 160. Note that the present invention is not limited to this. Electrical conductor 245 may be placed outside the memory unit.
  • FIGS. 25A and 25B show an example of a memory device in which 3 ⁇ 3 ⁇ 4 memory cells 150 are arranged in the X direction, Y direction, and Z direction.
  • FIG. 25A is a plan view of the storage device.
  • FIG. 25B is a cross-sectional view of a portion shown by a dashed line A1-A2 in FIG. 25A. Note that in the plan view of FIG. 25A, some elements are omitted for clarity.
  • the memory device shown in FIGS. 25A and 25B has a structure in which m (m is an integer of 2 or more) layers including the memory cell 150 are laminated.
  • m is an integer of 2 or more
  • the above layer provided as the first layer (bottom) is referred to as layer 170[1]
  • the above layer provided as the second layer is referred to as layer 170[2]
  • the (m-1) layer is referred to as layer 170[1].
  • FIG. 25B shows the provided layer as a layer 170 [m-1], and the m-th (top) layer as a layer 170 [m].
  • the memory device of one embodiment of the present invention may have a plurality of layers including the memory cell 150, and may have a structure in which the plurality of layers are stacked.
  • the conductor 245 may be provided outside the memory unit. Further, the conductor 245 may be electrically connected to a wiring provided in an upper layer of the layer including the conductor 245. For example, the conductor 245 provided in layer 170[1] is electrically connected to the wiring provided in layer 170[2]. Note that the wiring provided in layer 170[2] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[2]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 25B shows a configuration in which the conductor 245 is electrically connected to the wiring provided in the layer above the layer including the conductor 245, the present invention is not limited to this.
  • the conductor 245 may be electrically connected to wiring provided in a layer including the conductor 245.
  • the conductor 245 provided in the layer 170[1] may be electrically connected to the wiring provided in the layer 170[1].
  • the wiring provided in layer 170[1] is provided in the same layer as the lower electrode (conductor 110) of memory cell 150 included in layer 170[1]. In other words, the wiring can be formed in the same process as the conductor 110.
  • FIG. 26A the planar layout of the storage device shown in FIG. 25A is shown in FIG. 26A.
  • the planar layout of FIG. 26A shows a region including 4 ⁇ 4 memory cells 150.
  • a conductor 260 functioning as the wiring WL a conductor 240 functioning as the wiring BL, and an opening 290 are illustrated.
  • the memory cell 150 is provided in a region where the conductor 260, the conductor 240, and the opening 290 overlap.
  • the opening 290 is provided in a region of the conductor 240 where the conductor 240 and the conductor 260 intersect.
  • FIG. 26A shows a configuration in which memory cells 150 are arranged in a matrix. Further, a configuration is shown in which the openings 290 are arranged in a matrix. Further, a configuration is shown in which a conductor 260 is provided extending in the Y direction, and a conductor 240 is provided extending in the X direction. In other words, a configuration is shown in which the conductor 260 and the conductor 240 are perpendicular to each other. Further, the width of the conductor 260 in the direction (X direction) perpendicular to the direction in which the conductor 260 extends is uniform, and the width of the conductor 260 in the direction (Y direction) perpendicular to the direction in which the conductor 240 extends is uniform. This shows a configuration in which the width of the area is uniform. Note that the present invention is not limited to this.
  • FIG. 26B is another example of the planar layout of the storage device.
  • the planar layout of FIG. 26B illustrates the conductor 260, the conductor 240, and the opening 290, similarly to FIG. 26A.
  • the memory device shown in FIG. 26B differs from the memory device shown in FIG. 26A mainly in the arrangement of the memory cells 150 (openings 290), the shape of the conductors 240, and the direction in which the conductors 260 extend.
  • the memory cells 150 may be arranged in a zigzag pattern in the Y direction.
  • a memory cell adjacent to the first memory cell in the X direction is a second memory cell
  • a memory cell adjacent to the first memory cell and the second memory cell in the Y direction is a third memory cell.
  • the center of the third memory cell may be located on a straight line that passes between the first memory cell and the second memory cell and is parallel to the Y direction. At this time, it can be said that the third memory cell is located at a position shifted by half in the X direction from the first memory cell and the second memory cell.
  • the conductor 240 has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and the width of the first region in the Y direction is defined as the first width.
  • the first region can be said to have a shape of a quadrilateral with rounded corners.
  • the second region is a region between adjacent openings 290 in one conductor 240, and the width in the Y direction in the second region is defined as the second width.
  • the second width is preferably smaller than the first width.
  • the extending direction of the conductor 260 is arranged at an angle with respect to the Y direction. That is, depending on the arrangement of the memory cells 150 (openings 290), the extending direction of the conductor 260 may not be orthogonal to the extending direction of the conductor 240. In other words, the conductor 260 may intersect with the conductor 240.
  • FIG. 26C is another example of the planar layout of the storage device.
  • the conductor 260, the conductor 240, and the opening 290 are illustrated similarly to FIG. 26B.
  • the memory device shown in FIG. 26C differs from the memory device shown in FIG. 26B mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 26B has a rectangular shape with rounded corners in a plan view, and one side of the rectangle is parallel to the X direction or the Y direction.
  • the first region of the conductor 240 shown in FIG. 26C has a rectangular shape with rounded corners in plan view, and the diagonal lines of the rectangle are parallel to the X direction or the Y direction.
  • FIGS. 26B and 26C show an example in which the first region of the conductor 240 has a rectangular shape with rounded corners in plan view, the present invention is not limited to this.
  • FIG. 27A is another example of the planar layout of the storage device.
  • the conductor 260, the conductor 240, and the opening 290 are illustrated similarly to FIG. 26B.
  • the memory device shown in FIG. 27A differs from the memory device shown in FIG. 26B or 26C mainly in the shape of the first region of the conductor 240.
  • the first region of the conductor 240 shown in FIG. 27A has a circular shape in plan view.
  • the memory cells 150 openings 290
  • the physical distance between the conductors 240 can be reduced. Therefore, miniaturization and high integration of the memory device can be achieved.
  • the first region of the conductor 240 in plan view is not limited to the shape described above.
  • the first region of the conductor 240 in plan view may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrilateral, or a polygonal shape such as a quadrilateral with rounded corners.
  • FIG. 27A shows a configuration in which the width of the conductor 260 in the direction perpendicular to the direction in which the conductor 260 extends is uniform, the present invention is not limited to this.
  • FIG. 27B is another example of the planar layout of the storage device.
  • the conductor 260, the conductor 240, and the opening 290 are illustrated similarly to FIG. 27A.
  • the memory device shown in FIG. 27B differs from the memory device shown in FIG. 27A mainly in the shape of the conductor 260.
  • the conductor 260 shown in FIG. 27B has a first region and a second region.
  • the first region is the opening 290 and its vicinity, and is circular in plan view.
  • the second region is a region between adjacent openings 290 in one conductor 260. Note that the first region of the conductor 260 overlaps with the first region of the conductor 240.
  • FIG. 27C is another example of the planar layout of the storage device.
  • the conductor 260, the conductor 240, and the opening 290 are illustrated similarly to FIG. 27A.
  • the memory device shown in FIG. 27C differs from the memory device shown in FIG. 27A mainly in the shape and stretching direction of the conductor 260.
  • the conductor 260 shown in FIG. 27C has a triangular wave-like shape in plan view and is provided extending in the Y direction. With this configuration, when the memory cells 150 (openings 290) are arranged in a zigzag pattern in the Y direction, the physical distance between the conductors 240 can be reduced. Therefore, miniaturization and high integration of the memory device can be achieved. Note that the conductor 260 in plan view is not limited to the above, and may have a meander shape or the like.
  • one or both of the physical distance between the conductors 260 and the physical distance between the conductors 240 can be reduced, and the storage device can be miniaturized and highly integrated.
  • a memory device having a 3D memory cell array will be described in detail in a later embodiment.
  • the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also referred to as a layered crystal or layered structure). At this time, the c-axis of the crystal is oriented in the direction in which a plurality of layers are stacked.
  • a metal oxide having the above layered crystal structure it is preferable to deposit atoms one layer at a time.
  • an ALD method can be used as a method for forming the metal oxide.
  • the ALD method can deposit atoms one layer at a time, it is possible to form extremely thin films, to form structures with high aspect ratios, to form films with few defects such as pinholes, and to improve coverage. It has the advantage of being able to form an excellent film and being able to form a film at low temperatures.
  • the ALD method also includes a thermal ALD method, which is a film forming method that uses heat, and a plasma ALD method, which is a film forming method that uses plasma. By using plasma, it is possible to form a film at a lower temperature, which may be preferable.
  • some precursors used in the ALD method include elements such as carbon or chlorine. For this reason, a film formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that these elements can be quantified using XPS or SIMS.
  • the ALD method is a film-forming method in which a film is formed by a reaction on the surface of an object, unlike a film-forming method in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio.
  • the precursor 611a is introduced into the chamber, and the precursor 611a is adsorbed onto the surface of the substrate 610 (see FIG. 28A.
  • this process may be referred to as a first step).
  • a self-stopping mechanism of the surface chemical reaction acts, and the precursor 611a is further adsorbed onto the layer of the precursor 611a on the substrate 610. There's nothing to do.
  • the ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and may be, for example, 100°C or more and 600°C or less, preferably 200°C or more and 400°C or less.
  • an inert gas such as argon, helium, or nitrogen
  • the second step is also called purge.
  • a reactant 612a for example, an oxidizing agent (ozone (O 3 ), oxygen (O 2 ), water (H 2 O), and their plasmas, radicals, ions, etc.
  • a reactant 612a for example, an oxidizing agent (ozone (O 3 ), oxygen (O 2 ), water (H 2 O), and their plasmas, radicals, ions, etc.
  • a precursor 611b having a metal element different from that of the precursor 611a is introduced, and a process similar to the first step is performed to adsorb the precursor 611b on the surface of the oxide 613a layer (see FIG. 28C).
  • a process similar to the first step is performed to adsorb the precursor 611b on the surface of the oxide 613a layer.
  • FIG. 28C when the precursor 611b is adsorbed to the layer of the oxide 613a, a self-stopping mechanism of the surface chemical reaction acts, and the precursor 611b is further formed on the layer of the precursor 611b on the substrate 610. It will not be absorbed.
  • the reactant 612b is introduced into the chamber.
  • the reactant 612b may be the same as the reactant 612a, or may be different (see FIG. 28D).
  • a layer of oxide 613b which is formed by oxidizing a portion of precursor 611b, is formed on the layer of oxide 613a.
  • a layer of oxide 613c can be formed on the layer of oxide 613b by performing the first to fourth steps in the same manner.
  • a metal oxide with a layered crystal structure in which the stacked structure of the oxides 613a to 613c is repeated (See Figure 28E).
  • an oxide layer can be formed by setting the first to fourth steps as one set, and by repeating the set, a layered crystal structure in which multiple oxide layers are stacked can be formed. Can be done.
  • the thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.
  • the substrate temperature may be set to 200° C. or more and 600° C. or less, preferably 300° C. or more and below the decomposition temperature of the precursor.
  • the substrate temperature is preferably lower than the decomposition temperature of the lowest precursor among the plurality of precursors.
  • impurities such as hydrogen or carbon contained in the precursor and reactant are removed from the metal oxide in each process from Step 1 to Step 4.
  • impurities such as hydrogen or carbon contained in the precursor and reactant
  • carbon in a metal oxide can be released as CO2 and CO
  • hydrogen in a metal oxide can be released as H2O .
  • the metal atoms and oxygen atoms are rearranged, and each oxide layer can be arranged with high orderliness. Therefore, a highly crystalline metal oxide having a layered crystal structure can be formed.
  • the precursor used for the film formation has a high decomposition temperature.
  • the decomposition temperature of the precursor is preferably 200°C or more and 700°C or less, more preferably 300°C or more and 600°C or less.
  • an inorganic precursor a precursor formed of an inorganic substance (hereinafter referred to as an inorganic precursor). Since inorganic precursors generally tend to have a higher decomposition temperature than precursors formed from organic substances (hereinafter referred to as organic precursors), some precursors have an ALD window in the above temperature range. Furthermore, since the inorganic precursor does not contain impurities such as hydrogen or carbon, it is possible to prevent the concentration of impurities such as hydrogen or carbon from increasing in the metal oxide to be formed.
  • heat treatment after forming the metal oxide film.
  • the heat treatment is performed at a temperature of 100°C or more and 1200°C or less, preferably 200°C or more and 1000°C or less, more preferably 250°C or more and 650°C or less, even more preferably 300°C or more and 600°C or less, and even more preferably 400°C or more and 550°C or less. More preferably, the temperature may be 420°C or higher and 480°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in a nitrogen gas or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • impurities such as hydrogen or carbon contained in the metal oxide can be removed.
  • carbon in a metal oxide can be released as CO2 and CO
  • hydrogen in a metal oxide can be released as H2O .
  • metal atoms and oxygen atoms are rearranged, and crystallinity can be improved. Therefore, a highly crystalline metal oxide having a layered crystal structure can be formed.
  • microwave processing refers to processing using, for example, a device having a power source that generates high-density plasma using microwaves.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated.
  • oxygen that acts on metal oxides has various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals, atoms, molecules, or ions having unpaired electrons). Note that the oxygen acting on the metal oxide may be any one or more of the above-mentioned forms, and oxygen radicals are particularly preferred.
  • the temperature at which the above-mentioned substrate is heated may be 100°C or more and 650°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more and 450°C or less.
  • the carbon concentration in the metal oxide obtained by SIMS can be reduced to less than 1 ⁇ 10 20 atoms/cm 3 , preferably 1 ⁇ 10 19 It can be less than 1 ⁇ 10 18 atoms/cm 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • microwave treatment may be performed on an insulating film, more specifically a silicon oxide film, located near a metal oxide in an atmosphere containing oxygen.
  • microwave treatment may be performed after the insulator 250 is formed.
  • the microwave treatment is not necessarily performed after all the insulators included in the insulator 250 are formed.
  • microwave treatment may be performed after forming the insulator 250a and the insulator 250b, and then the insulator 250c may be formed.
  • the insulator 250 has a stacked structure of the insulator 250a, the insulator 250b, the insulator having a function of capturing or fixing hydrogen, and the insulator 250c , after forming the insulator 250a and the insulator 250b, microwave treatment is performed, then after forming an insulator having a function of capturing or fixing hydrogen, microwave treatment is performed, and then An insulator 250c may be formed. In this way, the microwave treatment in an atmosphere containing oxygen may be performed multiple times.
  • FIG. 28E describes a structure in which the stacked structure of the oxides 613a to 613c is repeated, the present invention is not limited to this.
  • it may be a metal oxide in which a single layer, two layers, or four or more oxide layers are repeatedly formed.
  • ozone, oxygen, or water when used as a reactant or oxidizing agent, it is not limited to a gas or molecular state, but is in a plasma state, a radical state, It also includes those in ionic state.
  • a radical ALD device or a plasma ALD device when forming a film using an oxidizing agent in a plasma state, a radical state, or an ion state, a radical ALD device or a plasma ALD device, which will be described later, may be used.
  • the precursor In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to cause the precursor to sufficiently react with an oxidizing agent.
  • the pulse time for introducing the oxidizing agent may be increased.
  • the oxidizing agent may be introduced multiple times.
  • the same type of oxidizing agent or different types of oxidizing agent may be introduced.
  • water may be introduced into the chamber as the first oxidizing agent, and then evacuation may be performed, and ozone or oxygen that does not contain hydrogen may be introduced into the chamber as the second oxidizing agent, and evacuation may be performed.
  • the ALD method is a film forming method in which a precursor and a reactant are reacted using thermal energy.
  • the temperature required for the reaction of the precursor and reactant is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., but is 100°C or more and 600°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more.
  • the temperature is 600°C or less.
  • an ALD method in which a plasma-excited reactant is introduced into a chamber as a third raw material gas to perform processing is sometimes referred to as a plasma ALD method.
  • a plasma generation device is provided in the third raw material gas introduction section.
  • ICP Inductively coupled plasma
  • thermal ALD method an ALD method in which a reaction between a precursor and a reactant is performed using thermal energy is sometimes referred to as a thermal ALD method.
  • a plasma-excited reactant is introduced to form a film.
  • film formation is performed by repeatedly performing the first to fourth steps and simultaneously introducing a plasma-excited reactant (second reactant).
  • the reactant introduced in the third step is called the first reactant.
  • the second reactant used for the third source gas can be made of the same material as the oxidizing agent. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant.
  • a nitriding agent may be used in addition to the oxidizing agent.
  • nitrogen (N 2 ) or ammonia (NH 3 ) can be used.
  • a mixed gas of nitrogen (N 2 ) and hydrogen (H 2 ) can be used as the nitriding agent.
  • a mixed gas of 5% nitrogen (N 2 ) and 95% hydrogen (H 2 ) can be used as the nitriding agent.
  • argon (Ar), helium (He), or nitrogen (N 2 ) may be used as the carrier gas for the second reactant. It is preferable to use a carrier gas such as argon, helium, or nitrogen because it facilitates plasma discharge and generates a plasma-excited second reactant. Note that when forming an oxide film such as a metal oxide film using a plasma ALD method, if nitrogen is used as a carrier gas, nitrogen may be mixed into the film, and the desired film quality may not be obtained. In this case, it is preferable to use argon or helium as the carrier gas.
  • the ALD method can form an extremely thin film with a uniform thickness. Moreover, the surface coverage rate is high even on surfaces having unevenness.
  • FIGS. 29A to 29D when the metal oxide with the layered crystal structure is an In-M-Zn oxide, the atomic arrangement in the crystal will be explained using FIGS. 29A to 29D.
  • atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines.
  • the c-axis direction in the crystal structure of In-M-Zn oxide is indicated by an arrow in the figure.
  • the a-b plane direction in the crystal structure of the In-M-Zn oxide is a direction perpendicular to the c-axis direction indicated by the arrow in FIGS. 29B and 29D.
  • FIG. 29A is a diagram showing an oxide 660 having an In-M-Zn oxide formed in the structure 650.
  • the structure refers to an element that constitutes a semiconductor device such as a transistor.
  • the structure 650 includes a substrate, a conductor such as a gate electrode, a source electrode, and a drain electrode, an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film, a metal oxide, and a semiconductor such as silicon. It will be done.
  • FIG. 29A shows a case where the film-forming surface of the structure 650 is arranged parallel to the substrate (or base body, not shown).
  • FIG. 29B is an enlarged view showing the atomic arrangement in the crystal in region 653, which is a part of oxide 660 in FIG. 29A.
  • the element M is a +3-valent metal element.
  • the crystal of the oxide 660 includes a layer 621 containing indium (In) and oxygen, a layer 631 containing element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen in this order. , are repeatedly laminated.
  • the layer 621, the layer 631, and the layer 641 are arranged approximately parallel to the film-forming surface of the structure 650. That is, the a-b plane of the oxide 660 is approximately parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is approximately parallel to the normal direction of the deposition surface of the structure 650. parallel.
  • each of the layers 621, 631, and 641 of the crystal is composed of one metal element and oxygen, so that they are arranged with good crystallinity, and the metal oxide
  • the carrier mobility of objects can be increased.
  • the stacking order of the layers 621, 631, and 641 may be changed.
  • the layers 621, 641, and 631 may be repeatedly stacked in this order.
  • the layers 621, 631, 641, 621, 641, and 631 may be repeatedly stacked in this order.
  • part of the element M in the layer 631 may be replaced with zinc
  • part of the zinc in the layer 641 may be replaced with the element M.
  • the crystalline In-M-Zn oxide, represented by ⁇ ) O 3 (ZnO) m ( ⁇ is a real number greater than 0 and less than 1, and m is a positive number) similarly has a layered crystal structure. be able to.
  • FIG. 29C is a diagram showing an oxide 662 having an In-M-Zn oxide formed in the structure 650.
  • FIG. 29D is an enlarged view showing the atomic arrangement in the crystal in region 654, which is part of oxide 662 in FIG. 29C.
  • the crystal of the oxide 662 includes a layer 622 containing indium (In), the element M, and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 641 containing the element M and oxygen. It has a layer 631.
  • a plurality of layers are repeatedly stacked in the order of layer 622, layer 641, layer 631, and layer 641.
  • the layer 622, the layer 631, and the layer 641 are arranged approximately parallel to the film-forming surface of the structure 650. That is, the a-b plane of the oxide 662 is approximately parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is approximately parallel to the normal direction of the deposition surface of the structure 650. parallel.
  • the structure may change within the range according to 4 [atomic ratio].
  • the stacking order of layer 622, layer 631, and layer 641 may be changed.
  • part of the element M in the layer 631 may be replaced with zinc
  • part of the zinc in the layer 641 may be replaced with the element M.
  • the layer 621 or the layer 631 may be formed instead of the layer 622.
  • a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the structure 650 (see FIG. 30A).
  • the source gas includes a carrier gas such as argon, helium, or nitrogen in addition to the precursor.
  • precursors containing indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)indium, cyclopentadienylindium, indium (III) acetylacetonate, ( 3-(dimethylamino)propyl)dimethylindium and the like can be used.
  • an inorganic precursor that does not contain hydrocarbons may be used.
  • the inorganic precursor containing indium halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide can be used.
  • Indium trichloride has a decomposition temperature of approximately 500°C or higher and 700°C or lower. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at about 400° C. or more and 600° C. or less, for example, 500° C.
  • an oxidizing agent is introduced into the chamber as a reactant and reacts with the adsorbed precursor to remove components other than indium while adsorbing indium to the substrate, thereby creating a layer 621 in which indium and oxygen are combined.
  • Ozone, oxygen, water, etc. can be used as the oxidizing agent.
  • the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant, reaction products, etc. are discharged from the chamber.
  • a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto the layer 621 (see FIG. 30C).
  • the source gas includes a carrier gas such as argon, helium, or nitrogen.
  • gallium trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3, Gallium (5-heptanedioate), dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, etc. can be used.
  • an inorganic precursor containing no hydrocarbon may be used.
  • the inorganic precursor containing gallium halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide can be used.
  • Gallium trichloride has a decomposition temperature of approximately 550°C or higher and 700°C or lower. Therefore, by using gallium trichloride, film formation can be performed by the ALD method while heating the substrate at about 450° C. or more and 650° C. or less, for example, 550° C.
  • an oxidizing agent is introduced into the chamber as a reactant, and reacts with the adsorbed precursor to desorb components other than element M while adsorbing element M to the substrate, thereby bonding element M and oxygen.
  • a layer 631 is formed (see FIG. 30D). At this time, part of the oxygen constituting the layer 641 may be adsorbed onto the layer 631.
  • the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant, reaction products, etc. are discharged from the chamber.
  • a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the layer 631 (see FIG. 31A). At this time, a part of the layer 641 in which zinc and oxygen are combined may be formed.
  • the source gas includes a carrier gas such as argon, helium, or nitrogen.
  • a carrier gas such as argon, helium, or nitrogen.
  • the precursor containing zinc dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioic acid)zinc, zinc acetate, etc. can be used.
  • an inorganic precursor without hydrocarbons may be used.
  • the inorganic precursor containing zinc halogen-based zinc compounds such as zinc dichloride, zinc dibromide, and zinc diiodide can be used.
  • Zinc dichloride has a decomposition temperature of approximately 450°C or higher and 700°C or lower. Therefore, by using zinc dichloride, film formation can be performed by the ALD method while heating the substrate at about 350° C. or more and 550° C. or less, for example, 450° C.
  • an oxidizing agent is introduced into the chamber as a reactant, reacts with the adsorbed precursor, and removes components other than zinc while adsorbing zinc to the substrate, thereby forming a layer 641 in which zinc and oxygen are combined. (See Figure 31B).
  • the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant, reaction products, etc. are discharged from the chamber.
  • the layer 621 is formed again on the layer 641 by the method described above (see FIG. 31C).
  • the oxide 660 can be formed on the substrate or the structure.
  • precursors include one or both of carbon and chlorine in addition to metal elements.
  • a film formed using a precursor containing carbon may contain carbon.
  • a film formed using a precursor containing halogen such as chlorine may contain halogen such as chlorine.
  • the oxide 660 by forming the oxide 660 using the ALD method, it is possible to form a metal oxide in which the c-axis is oriented approximately parallel to the normal direction of the surface on which the film is to be formed.
  • a metal oxide in which the c-axis is oriented approximately parallel to the normal direction of the surface on which the film is to be formed.
  • a layered crystal that is approximately parallel to the side wall of the opening 290, particularly the side surface of the insulator 280, can be formed.
  • the layered crystal of the oxide semiconductor 230 is formed approximately parallel to the channel length direction of the transistor 200, so that the on-state current of the transistor can be increased.
  • the substrate temperature may be set to 200° C. or more and 600° C. or less, preferably 300° C. or more and below the decomposition temperature of the precursor.
  • the precursor used for the film formation has a high decomposition temperature.
  • the decomposition temperature of the precursor is preferably 200°C or more and 700°C or less, more preferably 300°C or more and 600°C or less.
  • an inorganic precursor As such a precursor having a high decomposition temperature, it is preferable to use an inorganic precursor. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if film formation is performed while heating the substrate as described above, the precursors are difficult to decompose.
  • the inorganic precursor for example, the above-mentioned indium trichloride, gallium trichloride, and zinc dichloride can be used.
  • the decomposition temperature of these precursors is about 350° C. or higher and 700° C. or lower, which is considerably higher than the decomposition temperature of general organic precursors.
  • the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. In this way, when forming a film by the ALD method using a plurality of different types of precursors, it is preferable that the substrate temperature be lower than or equal to the decomposition temperature of the lowest precursor among the plurality of precursors.
  • the substrate temperature may be set within a range where the precursor decomposition temperature is the lowest and zinc dichloride does not decompose.
  • other indium trichloride and gallium trichloride can also be adsorbed onto a target object (for example, a substrate) without being decomposed.
  • a layer 621 is formed as a layer containing indium
  • a layer 631 is formed as a layer containing element M thereon
  • a layer 641 is further formed as a layer containing zinc thereon.
  • the present embodiment is not limited to this.
  • One of the layers 631 and 641 may be formed, the layer 621 may be formed thereon, and the other of the layers 631 and 641 may be formed thereon.
  • one of the layers 631 and 641 may be formed, the other of the layers 631 and 641 may be formed thereon, and the layer 621 may be further formed thereon.
  • the layers 621, 631, and 641 are adjusted according to the atomic ratio. , may be formed as appropriate. For example, by repeating the formation of the layer 641 multiple times before and after the formation of the layer 631 shown in FIG. It is sufficient to form a stack with layer 641.
  • This embodiment mode describes a configuration example of a memory device in which a layer having a functional circuit having a function of amplifying and outputting a data potential held in a memory cell is provided between layers having stacked memory cells. explain.
  • FIG. 32 shows a block diagram illustrating a configuration example of a storage device 300 according to one aspect of the present invention.
  • a storage device 300 shown in FIG. 32 includes a drive circuit 21 and a memory array 20.
  • Memory array 20 has a functional layer 50 having a plurality of memory cells 10 and a plurality of functional circuits 51.
  • FIG. 32 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or more). Further, the functional circuit 51 is provided for each wiring BL functioning as a bit line, for example. FIG. 32 shows an example in which a plurality of functional circuits 51 are provided corresponding to n wires BL.
  • the memory cell 10 in the first row and first column is shown as a memory cell 10[1,1] and the memory cell 10 in the mth row and nth column is shown as a memory cell 10[m,n].
  • the memory cell 10 in the mth row and nth column is shown as a memory cell 10[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the memory cell 10 in the i-th row and j-th column is referred to as a memory cell 10[i,j].
  • the memory array 20 includes m wires WL extending in the row direction, m wires PL extending in the row direction, and n wires BL extending in the column direction.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1]
  • the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m].
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • the wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • the wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the plurality of memory cells 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of memory cells 10 provided in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).
  • DOSRAM Dynamic Oxide Semiconductor Random Access Memory
  • 1T transistor
  • 1C capactance
  • DOSRAM can hold charge corresponding to data held in a capacitive element (capacitor) for a long time by turning off the access transistor (making it non-conductive). Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM configured with a transistor having silicon in a channel formation region (hereinafter also referred to as "Si transistor"). As a result, it is possible to reduce power consumption.
  • the memory cells 10 can be provided in a stacked manner by stacking and arranging OS transistors as described in Embodiment Mode 1 and the like.
  • a plurality of memory arrays 20[1] to 20[m] can be stacked and provided.
  • the memory array 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, it is possible to improve the memory density of the memory cell 10.
  • the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction.
  • the storage device 300 can reduce the manufacturing cost of the memory array 20.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling on or off (conductive state or non-conductive state) of an access transistor functioning as a switch.
  • the wiring PL has a function as a constant potential line connected to the capacitive element.
  • the memory cells 10 each of the memory arrays 20[1] to 20[m] have are connected to the functional circuit 51 via the wiring BL.
  • the wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided.
  • the length of the wiring between the memory array 20 and the functional circuit 51 can be reduced. It can be made shorter. Therefore, the signal propagation distance between two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, so that power consumption and signal delay can be reduced. Furthermore, it is possible to operate the memory cell 10 even if the capacitance of the capacitive element is reduced.
  • the functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 via a wiring GBL (not shown) to be described later. With this configuration, a slight potential difference in the wiring BL can be amplified when reading data.
  • the wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided. By providing the wiring BL and wiring GBL extending from the memory cells 10 of the memory arrays 20 [1] to 20 [m] in the vertical direction of the substrate surface, the wiring between the functional circuit 51 and the sense amplifier 46 can be reduced. The length can be shortened. Therefore, the signal propagation distance between the two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL can be significantly reduced, so that power consumption and signal delay can be reduced.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 10.
  • the wiring BL is provided in contact with a conductor provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the memory cell 10.
  • the wiring BL can be said to be a wiring for electrically connecting each of the sources and drains of the transistors included in the memory cells 10 in each layer of the memory array 20 and the functional circuit 51 in the vertical direction.
  • the memory array 20 can be provided over the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, resistance and parasitic capacitance between drive circuit 21 and memory array 20 are reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 300 can be made smaller.
  • the functional circuit 51 is constructed of OS transistors like the transistors included in the memory cell 10 of the DOSRAM, and can be freely mounted on a circuit using Si transistors in the same way as the memory arrays 20[1] to 20[m]. Since it can be arranged, integration can be easily performed. By configuring the functional circuit 51 to amplify the signal, it is possible to reduce the size of circuits such as the sense amplifier 46, which is a subsequent circuit, so that the storage device 300 can be made smaller.
  • the drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • the signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling input of the signal CLK to the voltage generation circuit 33. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. Further, the peripheral circuit 41 is a circuit that outputs various signals for controlling the functional circuit 51.
  • the peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46. (Sense Amplifier).
  • the row decoder 42 and column decoder 44 have a function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the memory cell 10, a function of reading data from the memory cell 10, a function of holding the read data, and the like.
  • the input circuit 47 has a function of holding the signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • the PSW 23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the storage device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls the on/off of the PSW22
  • the signal PON2 controls the on/off of the PSW23.
  • the number of power domains to which VDD is supplied is one, but the number may be plural. In this case, a power switch may be provided for each power domain.
  • the memory array 20 having the memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and the functional layer 50 can be provided by overlapping multiple layers of the memory array 20 on the drive circuit 21. By overlapping multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased.
  • FIG. 33A the memory array 20 provided in the first layer is indicated as memory array 20[1], the memory array 20 provided in the second layer is indicated as memory array 20[2], and the memory array 20 provided in the fifth layer is indicated as memory array 20[2].
  • the memory array 20 that has been constructed is shown as a memory array 20[5].
  • FIG. 33A illustrates a wiring WL and a wiring PL extending in the X direction, and a wiring BL extending in the Z direction (direction perpendicular to the surface of the substrate on which the drive circuit is provided). Note that in order to make the drawing easier to read, some of the wiring WL and wiring PL included in each of the memory arrays 20 are omitted. Note that although FIG.
  • the wiring PL may be provided extending in the X direction, the present invention is not limited to this.
  • the wiring PL may be provided extending in the Y direction, or the wiring PL may be provided extending in the X direction and the Y direction, for example, the wiring PL may be provided in a planar shape.
  • FIG. 33B is a schematic diagram illustrating a configuration example of the functional circuit 51 connected to the wiring BL illustrated in FIG. 33A and the memory cells 10 included in the memory arrays 20[1] to 20[5] connected to the wiring BL. shows. Further, FIG. 33B illustrates a wiring GBL provided between the functional circuit 51 and the drive circuit 21. Note that a configuration in which a plurality of memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Note that in the drawings, the wiring GBL may be illustrated with thick lines to improve visibility.
  • FIG. 33B illustrates an example of the circuit configuration of the memory cell 10 connected to the wiring BL.
  • Memory cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitive element 12, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may be referred to as the wiring BL and the wiring WL.
  • one of the source and drain of the transistor 11 is connected to the wiring BL.
  • the other of the source and drain of the transistor 11 is connected to one electrode of the capacitive element 12.
  • the other electrode of the capacitive element 12 is connected to the wiring PL.
  • the gate of the transistor 11 is connected to the wiring WL.
  • two memory cells 10 connected to a common wiring BL in the same layer can have a structure shown in FIG. 25 according to the first embodiment.
  • FIG. 33B and the like show a configuration in which two memory cells 10 are connected to a common wiring BL in the same layer
  • the present invention is not limited to this.
  • four memory cells 10 may be connected to a common wiring BL in the same layer, or eight memory cells 10 may be connected to a common wiring BL in the same layer.
  • the structure shown in FIGS. 24A and 24B according to the first embodiment can be used.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitive element 12.
  • FIG. 34A shows a schematic diagram of a storage device 300 in which the functional layer 50 and the memory arrays 20[1] to 20[m] are the repeating units 70. Note that although one wiring GBL is shown in FIG. 34A, the wiring GBL may be provided as appropriate depending on the number of functional circuits 51 provided in the functional layer 50.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor included in the functional circuit 51.
  • the wiring GBL is provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51.
  • the wiring GBL is provided in contact with a conductor provided in contact with a region functioning as a source or drain of a semiconductor layer of a transistor included in the functional circuit 51.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the functional circuit 51 in the functional layer 50 and the drive circuit 21 in the vertical direction.
  • the repeating unit 70 having the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked.
  • the storage device 300A according to one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 34B.
  • the wiring GBL is connected to the functional layer 50 that the repeating unit 70 has.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 51.
  • the OS transistors are provided in a stacked manner, and the wiring functioning as the bit line is arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided.
  • the wiring extending from the memory array 20 and functioning as a bit line in a direction perpendicular to the substrate surface the length of the wiring between the memory array 20 and the drive circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.
  • the layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 having a function of amplifying and outputting the data potential held in the memory cell 10.
  • FIG. 35 A configuration example of the functional circuit 51 described in FIGS. 32 to 34B and a configuration example of the sense amplifier 46 included in the memory array 20 and the drive circuit 21 will be described using FIG. 35.
  • wires GBL GBL (GBL_A, GBL_B) are connected to functional circuits 51 (51_A, 51_B) connected to memory cells 10 (10_A, 10_B) connected to different wires BL (BL_A, BL_B).
  • a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write/read circuit 73 are illustrated.
  • a transistor 52_a, a transistor 52_b, a transistor 53_a, a transistor 53_b, a transistor 54_a, a transistor 54_b, a transistor 55_a, and a transistor 55_b are illustrated as the functional circuit 51_A and the functional circuit 51_B.
  • Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b illustrated in FIG. 35 are OS transistors like the transistor 11 included in the memory cell 10.
  • the functional layer 50 having the functional circuit 51 can be provided in a stacked manner similar to the memory arrays 20[1] to 20[m].
  • Wirings BL_A and BL_B are connected to the gates of transistors 52_a and 52_b.
  • Wirings GBL_A and GBL_B are connected to one of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b.
  • the wirings GBL_A and GBL_B are provided in the vertical direction similarly to the wirings BL_A and BL_B, and are connected to the transistors included in the drive circuit 21.
  • control signals WE, RE, and MUX are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b.
  • Transistors 81_1 to 81_6 and transistors 82_1 to 82_4, which constitute the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B shown in FIG. 35, are composed of Si transistors.
  • the switches 83_A to 83_D making up the switch circuit 72_A and the switch circuit 72_B can also be made of Si transistors.
  • One of the sources or drains of the transistors 53_a, 53_b, 54_a, and 54_b is connected to a transistor or a switch forming the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.
  • the precharge circuit 71_A includes n-channel transistors 81_1 to 81_3.
  • the precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL1. .
  • the precharge circuit 71_B has n-channel transistors 81_4 to 81_6.
  • the precharge circuit 71_B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC corresponding to the potential VDD/2 between VDD and VSS in accordance with a precharge signal applied to the precharge line PCL2. be.
  • the sense amplifier 46 includes a p-channel transistor 82_1, a p-channel transistor 82_2, an n-channel transistor 82_3, and an n-channel transistor 82_4, which are connected to the wiring VHH or the wiring VLL.
  • the wiring VHH or the wiring VLL is a wiring that has a function of providing VDD or VSS.
  • the transistors 82_1 to 82_4 are transistors forming an inverter loop.
  • the potentials of the wiring GBL_A and the wiring GBL_B can be output to the outside via the switch 83_C, the switch 83_D, and the write/read circuit 73.
  • the wiring BL_A and the wiring BL_B, and the wiring GBL_A and the wiring GBL_B correspond to a bit line pair.
  • writing of a data signal is controlled according to the signal EN_data.
  • the switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B.
  • the switch circuit 72_A is turned on or off under the control of the switching signal CSEL1.
  • the switch 83_A and the switch 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and turned off when the switching signal CSEL1 is at a low level.
  • the switch circuit 72_B is a circuit for controlling the conduction state between the write/read circuit 73 and the bit line pair connected to the sense amplifier 46.
  • the switch circuit 72_B is turned on or off under the control of the switching signal CSEL2.
  • the switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.
  • the memory device 300 has a configuration in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via a wiring BL and a wiring GBL provided in the vertical direction, which are the shortest distances. be able to.
  • the number of functional layers 50 having transistors forming the functional circuit 51 increases, the load on the wiring BL is reduced, so that writing time can be shortened and data can be read easily.
  • each transistor included in functional circuits 51_A and 51_B is controlled according to control signals WE, RE, and selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the drive circuit 21 via the wiring GBL in accordance with the control signal and the selection signal.
  • the functional circuits 51_A and 51_B can function as sense amplifiers made up of OS transistors. With this configuration, it is possible to amplify a slight potential difference in the wiring BL during reading and drive the sense amplifier 46 using a Si transistor.
  • FIGS. 36A and 36B An example of a chip 1200 on which a storage device of the present invention is mounted is shown using FIGS. 36A and 36B.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) and is connected to the first surface of the package substrate 1201, as shown in FIG. 36B. Furthermore, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.
  • the motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222.
  • storage devices such as a DRAM 1221 and a flash memory 1222.
  • the DOSRAM described in the previous embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have lower power consumption, higher speed, and larger capacity.
  • the CPU 1211 has multiple CPU cores. Further, it is preferable that the GPU 1212 has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory that temporarily stores data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The above-mentioned DOSRAM can be used as the memory. Further, the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing or product-sum calculation. By providing the GPU 1212 with an image processing circuit or a product-sum calculation circuit using the oxide semiconductor of the present invention, image processing and product-sum calculation can be performed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation in the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation section 1213 may be provided with the above product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with external connection devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a DRAM 1221, and a flash memory 1222 can be called a GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), etc.
  • the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • This embodiment shows an example of an electronic component and an electronic device in which the storage device and the like shown in the above embodiments are incorporated.
  • the electronic components and electronic devices can have lower power consumption and higher speed.
  • FIG. 37A shows a perspective view of the electronic component 700 and a board (mounted board 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 37A has a storage device 720 within a mold 711. 37A omits a portion to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to memory device 720 by wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the memory device 720 includes a drive circuit layer 721 and a memory circuit layer 722.
  • FIG. 37B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
  • the storage device described in the above embodiment as the storage device 720, power consumption can be reduced and speed can be increased.
  • the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • interposers are sometimes called "rewiring boards” or “intermediate boards.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV Thinough Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, since wiring formation in a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult to do with a resin interposer.
  • a silicon interposer in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to the difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
  • 2.5D package 2.5-dimensional packaging
  • a heat sink may be provided overlapping the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the storage device 720 and the semiconductor device 735 have the same height.
  • an electrode 733 may be provided on the bottom of the package board 732.
  • FIG. 37B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded pack
  • age or QFN (Quad Flat Non-leaded package).
  • the storage devices described in the above embodiments are, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.). Applicable to By using the storage device described in the above embodiment as the storage device of the electronic device described above, the electronic device can have lower power consumption and higher speed.
  • the term "computer” as used herein includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the storage device shown in the previous embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIGS. 38A to 38E schematically show several configuration examples of removable storage devices.
  • the storage device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.
  • FIG. 38A is a schematic diagram of a USB memory.
  • USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the board 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the storage device described in the previous embodiment can be incorporated into the memory chip 1105 or the like.
  • FIG. 38B is a schematic diagram of the external appearance of the SD card
  • FIG. 38C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the board 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data can be read from and written to the memory chip 1114 through wireless communication between the host device and the SD card 1110.
  • the memory device described in the previous embodiment can be incorporated into the memory chip 1114 or the like.
  • FIG. 38D is a schematic diagram of the external appearance of the SSD
  • FIG. 38E is a schematic diagram of the internal structure of the SSD.
  • SSD 1150 has a housing 1151, a connector 1152, and a board 1153.
  • the board 1153 is housed in a housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and may be a DOSRAM chip, for example.
  • the capacity of the SSD 1150 can be increased.
  • the memory device described in the previous embodiment can be incorporated into the memory chip 1154 or the like.
  • a storage device can be used for a processor such as a CPU or a GPU, or a chip.
  • processors or chips such as CPUs and GPUs in electronic devices, it is possible to reduce power consumption and speed up the electronic devices.
  • 39A to 39H show specific examples of electronic devices equipped with processors, such as CPUs and GPUs, or chips using the storage device.
  • a GPU or a chip according to one embodiment of the present invention can be installed in various electronic devices.
  • electronic devices include relatively large screens such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, etc.
  • examples include digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, personal digital assistants, sound playback devices, and the like.
  • the electronic device can be equipped with artificial intelligence.
  • An electronic device may include an antenna. By receiving signals with the antenna, images, information, etc. can be displayed on the display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.
  • An electronic device includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (including the ability to sense, detect, or measure voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).
  • sensors force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (including the ability to sense, detect, or measure voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).
  • An electronic device can have various functions. For example, functions that display various information (still images, videos, text images, etc.) on the display, touch panel functions, calendars, functions that display date or time, etc., functions that execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, etc. Examples of electronic devices are shown in FIGS. 39A to 39H.
  • FIG. 39A illustrates a mobile phone (smartphone) that is a type of information terminal.
  • the information terminal 5100 has a housing 5101 and a display section 5102. As an input interface, the display section 5102 is equipped with a touch panel, and the housing 5101 is equipped with buttons.
  • the information terminal 5100 can have lower power consumption and higher speed.
  • a notebook information terminal 5200 is illustrated in FIG. 39B.
  • the notebook information terminal 5200 includes an information terminal main body 5201, a display section 5202, and a keyboard 5203.
  • the notebook information terminal 5200 can have lower power consumption and higher speed by applying the chip of one embodiment of the present invention.
  • a smartphone and a notebook information terminal are shown as examples of electronic devices in FIGS. 39A and 39B, respectively, but information terminals other than smartphones and notebook information terminals can be applied.
  • Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.
  • FIG. 39C shows a portable game machine 5300 that is an example of a game machine.
  • the portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like.
  • the housing 5302 and the housing 5303 can be removed from the housing 5301.
  • the connection portion 5305 provided in the casing 5301 to another casing (not shown)
  • the video output to the display portion 5304 can be output to another video device (not shown). can.
  • the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time.
  • the chips described in the previous embodiments can be incorporated into chips provided on the substrates of the housings 5301, 5302, and 5303.
  • FIG. 39D shows a stationary game machine 5400, which is an example of a game machine.
  • a controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.
  • a game machine with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • FIGS. 39C and 39D illustrate a portable game machine and a stationary game machine as examples of game machines
  • the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited thereto.
  • Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like. can be mentioned.
  • a GPU or a chip according to one embodiment of the present invention can be applied to large-sized computers.
  • FIG. 39E is a diagram showing a supercomputer 5500, which is an example of a large computer.
  • FIG. 39F is a diagram showing a rack-mount computer 5502 included in the supercomputer 5500.
  • the supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that the plurality of computers 5502 are stored in a rack 5501. Further, the computer 5502 is provided with a plurality of boards 5504, on which the GPU or chip described in the above embodiment can be mounted.
  • the supercomputer 5500 is a large computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of huge amounts of calculations, which consumes a lot of power and generates a lot of heat from the chip. For example, in a data center having multiple supercomputers 5500, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yota) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a major contribution to global warming countermeasures.
  • FIGS. 39E and 39F illustrate a supercomputer as an example of a large-sized computer
  • the large-sized computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this.
  • Examples of large-scale computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers), large-scale general-purpose computers (mainframes), and the like.
  • a GPU or a chip according to one embodiment of the present invention can be applied to an automobile, which is a moving object, and around the driver's seat of the automobile.
  • FIG. 39G is a diagram showing the area around the windshield in the interior of an automobile, which is an example of a moving object.
  • FIG. 39G illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, as well as a display panel 5704 attached to a pillar.
  • the display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Furthermore, the display items, layout, etc. displayed on the display panel can be changed as appropriate to suit the user's preferences, making it possible to improve the design.
  • the display panels 5701 to 5703 can also be used as a lighting device.
  • the display panel 5704 By displaying an image from an imaging device (not shown) installed in the vehicle on the display panel 5704, it is possible to supplement the field of view (blind spot) blocked by the pillar. That is, by displaying images from an imaging device installed outside the vehicle, blind spots can be compensated for and safety can be improved. In addition, by displaying images that complement the invisible parts, safety confirmation can be performed more naturally and without any discomfort.
  • the display panel 5704 can also be used as a lighting device.
  • the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system for a car. Furthermore, the chip can be used in systems that perform road guidance, danger prediction, etc.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving objects.
  • flying objects helicopters, unmanned aerial vehicles (drones), airplanes, and rockets
  • the chip of one embodiment of the present invention can be applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • FIG. 39H shows an electric refrigerator-freezer 5800 that is an example of an electrical appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 has a function that automatically generates a menu based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, etc. It can have a function to automatically adjust the temperature according to the temperature.
  • an electric refrigerator-freezer has been described as an example of an electric appliance
  • other electric appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioning appliances including air conditioners, Examples include washing machines, dryers, and audio-visual equipment.
  • the electronic device the functions of the electronic device, the application examples of artificial intelligence, the effects thereof, etc. described in this embodiment can be combined as appropriate with the descriptions of other electronic devices.
  • a memory device includes an OS transistor.
  • the OS transistor has small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space.
  • OS transistors can be suitably used when used in outer space.
  • FIG. 40 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is illustrated in outer space.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the electric power necessary for the operation of the artificial satellite 6800 is generated.
  • the power necessary for satellite 6800 to operate may not be generated.
  • the solar panel is sometimes called a solar cell module.
  • the satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a ground-based receiver or other satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a memory device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the storage device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
  • Tables 1 and 2 show the results of comparing the density, write time, read time, and retention time of a DOSRAM, which is an OS memory, and a DRAM made of Si transistors.
  • the on-state current of the transistor can be increased.
  • IGZO(111) ⁇ (401) ⁇ (111) can be said to be a semiconductor material with a larger on-current than IGZO(111).
  • the straight cell arrangement shown in Tables 1 and 2 refers to the cell arrangement shown in FIG. 26A
  • the zigzag cell arrangement shown in Tables 1 and 2 refers to the cell arrangement shown in FIG. 27C.
  • the DOSRAM was estimated based on a structure in which an OS transistor having an opening 290 with a diameter of 25 nm ⁇ was manufactured using a design rule of 20 nm or 14 nm, and five element layers each having an OS transistor were laminated. Also, in DOSRAM, the cell capacity was estimated at 1.5 fF. Table 1 shows the results of estimating the OS transistor using a 20 nm design rule, and Table 2 shows the results of estimating the OS transistor using a 14 nm design rule.
  • the DRAM having Si transistors was estimated based on the design rule of 14 nm for Si transistors.
  • DRAM has 383 cells/ ⁇ m2
  • DOSRAM with a 20 nm design rule has 331 cells/ ⁇ m per layer with a straight cell arrangement. ⁇ m 2 , and with a zigzag cell arrangement, it becomes 382 cells/ ⁇ m 2 .
  • DOSRAM has the potential to exceed the performance of current DRAM by increasing the number of layers.
  • the cell density per layer is 416 cells/ ⁇ m 2 in a straight cell arrangement and 481 cells/ ⁇ m 2 in a zigzag cell arrangement. Therefore, it has been found that DOSRAM has the potential to outperform current DRAM when the design rules are the same.
  • the write time and read time of DRAM are 20 ns or less, while the write time of DOSRAM is short and the read time is on. It was found that the same level can be achieved by using a semiconductor material with a large current. In other words, it has been found that DOSRAM may have performance equal to or higher than that of DRAM by using a semiconductor material with a large on-current.
  • DOSRAM In terms of retention time, which compares data retention time, it is estimated that DOSRAM is refreshed more than once every 6.4s, compared to a configuration in which DRAM refreshes data in all memory cells once every 64ms. As a result, it was found that DOSRAM has the possibility of reducing the power consumption required for refreshing DRAM to 1/100.
  • a sample including a transistor that can be used in the memory cell described in Embodiment 1 was manufactured, and the electrical characteristics of the transistor were evaluated.
  • FIGS. 41A and 41B Three-sectional views of the transistor included in the sample are shown in FIGS. 41A and 41B.
  • the conductor 120 includes a conductor 120a, a conductor 120b on the conductor 120a, and a conductor 120c on the conductor 120b.
  • the conductor 120a is a conductor that includes a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion
  • the conductor 120b is a conductor that is
  • the conductor 120c is a conductor containing a material with a high oxygen content
  • the conductor 120c is a conductor containing a conductive material containing oxygen.
  • the conductor 240 includes a conductor 240a and a conductor 240b on the conductor 240a.
  • the content of the first conductor of the conductor 240 described in Embodiment 1 can be referred to.
  • the content of the second conductor of the conductor 240 described in Embodiment 1 can be referred to.
  • the insulator 280 includes an insulator 280a, an insulator 280b on the insulator 280a, an insulator 280c on the insulator 280b, and an insulator 280d on the insulator 280c.
  • the insulators 280a to 280c the details described in Embodiment 1 can be referred to.
  • the insulator 280d corresponds to the insulator described in Embodiment 1 that has high etching selectivity with respect to the conductive film serving as the conductor 240a.
  • the insulator 250 includes an insulator 250a, an insulator 250b on the insulator 250a, an insulator 250d on the insulator 250b, and an insulator 250c on the insulator 250d.
  • Insulator 250d corresponds to the insulator provided between insulator 250b and insulator 250c described in Embodiment 1.
  • the insulator 250d is an insulator that has the function of capturing or fixing hydrogen.
  • the side edges of the oxide semiconductor 230a and the side edges of the conductor 240b may coincide with each other. .
  • Embodiment 1 For configurations other than the above, the content described in Embodiment 1 can be referred to.
  • Embodiment Mode 1 can be referred to for details of the manufacturing method.
  • a conductor 120 was provided on the silicon oxide film.
  • the conductor 120a was formed using a titanium nitride film formed by a sputtering method.
  • the conductor 120b was formed using a tungsten film formed by sputtering.
  • the conductor 120c was formed using an ITSO film formed using a sputtering method. Note that the conductor 120a and the conductor 120b were continuously formed into films using a multi-chamber sputtering apparatus without being exposed to the outside air.
  • insulator 280a a silicon nitride film with a thickness of 8 nm was used, which was formed by an ALD method.
  • insulator 280b a silicon oxide film formed by a sputtering method was used.
  • CMP treatment was performed to flatten the upper surface of the insulator 280b. By performing CMP treatment, the film thickness of the insulator 280b on the conductor 120 was set to 20 nm.
  • insulator 280c a silicon nitride film with a thickness of 5 nm was used, which was formed by a sputtering method.
  • insulator 280d a silicon oxide film with a thickness of 10 nm was used, which was formed by a sputtering method.
  • the conductor 240a was formed using a tungsten film with a thickness of 15 nm, which was formed by a sputtering method.
  • the conductor 240b was formed using an ITSO film with a thickness of 10 nm, which was formed by a sputtering method.
  • the opening 290 was formed so that its maximum width was 60 nm in diameter.
  • the oxide semiconductor 230b was formed using an In-Ga-Zn oxide film with a thickness of 5 nm, which was formed by an ALD method.
  • the precursors used to form the oxide film that will become the oxide semiconductor 230b are triethyl indium (TEI), triethyl gallium (TEG), and diethyl zinc (DEZ).
  • TEI triethyl indium
  • TOG triethyl gallium
  • DEZ diethyl zinc
  • O 3 ozone
  • oxygen O 2
  • the insulator 250a was formed using an aluminum oxide film with a thickness of 1 nm, which was formed by an ALD method.
  • the insulator 250b was formed using a silicon oxide film with a thickness of 2 nm, which was formed by an ALD method.
  • the insulator 250d was formed using a hafnium oxide film with a thickness of 2 nm, which was formed by an ALD method.
  • the insulator 250c was formed using a silicon nitride film with a thickness of 1 nm, which was formed by an ALD method.
  • the conductor 260a was formed using a titanium nitride film with a thickness of 5 nm, which was formed by a metal CVD method. Further, the conductor 260b was formed using a 20 nm thick tungsten film formed by a sputtering method.
  • a silicon nitride film with a thickness of 5 nm was used, which was formed by a sputtering method.
  • Id-Vg characteristics were measured as electrical characteristics.
  • the Id-Vg characteristic was measured by setting the drain voltage Vd to 1.2V, the source voltage Vs to 0V, and sweeping the gate voltage Vg from -4V to +4V in 0.1V steps. Moreover, the measurement was performed under a room temperature environment.
  • FIG. 42 shows the Id-Vg characteristics of the transistor included in the fabricated sample.
  • the vertical axis represents the drain current Id [A]
  • the horizontal axis represents the gate-source voltage (Vg) [V].
  • BL wiring, PL: wiring, Tr: transistor, WL: wiring, 10: memory cell, 11: transistor, 12: capacitive element, 20: memory array, 21: drive circuit, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48 : output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 53_a: transistor, 53_b: transistor, 54_a: transistor, 54_b: transistor, 55_a: Transistor, 55_b: Transistor, 70: Repeat unit, 71_A: Precharge circuit, 71_B: Precharge circuit, 72_A: Switch circuit, 72_B: Switch circuit, 73: Write/read circuit, 81_1: Transistor,

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JP2020120116A (ja) * 2019-01-25 2020-08-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2021114563A (ja) * 2020-01-20 2021-08-05 キオクシア株式会社 半導体記憶装置

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US9312257B2 (en) 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR20220062524A (ko) 2019-09-20 2022-05-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법

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* Cited by examiner, † Cited by third party
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JP2020120116A (ja) * 2019-01-25 2020-08-06 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
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