WO2024046141A1 - 时延校准装置及时延校准方法 - Google Patents

时延校准装置及时延校准方法 Download PDF

Info

Publication number
WO2024046141A1
WO2024046141A1 PCT/CN2023/113693 CN2023113693W WO2024046141A1 WO 2024046141 A1 WO2024046141 A1 WO 2024046141A1 CN 2023113693 W CN2023113693 W CN 2023113693W WO 2024046141 A1 WO2024046141 A1 WO 2024046141A1
Authority
WO
WIPO (PCT)
Prior art keywords
pulse signal
delay calibration
air interface
delay
subunit
Prior art date
Application number
PCT/CN2023/113693
Other languages
English (en)
French (fr)
Inventor
于鹤杰
黄新星
Original Assignee
深圳市中兴微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市中兴微电子技术有限公司 filed Critical 深圳市中兴微电子技术有限公司
Publication of WO2024046141A1 publication Critical patent/WO2024046141A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of communication technology, and specifically relate to a delay calibration device and a delay calibration method.
  • 5G communications have developed rapidly in recent years. Technologies such as Massive MIMO (large-scale antenna technology) and GPS 1PPS (Global Positioning System Pulse Per Second) timing have improved system capacity and clock accuracy. This is accompanied by higher requirements for the accuracy of the digital link delay of the radio frequency transceiver system.
  • Massive MIMO large-scale antenna technology
  • GPS 1PPS Global Positioning System Pulse Per Second
  • PVT Process angle, power supply voltage and temperature
  • the method used for this kind of processing is to construct special excitation data, perform double-point sampling on the digital link data, analyze it based on the correlation algorithm, obtain the transmission delay of the data link, and then align the data through correction.
  • the accuracy of dual-point sampling link delay calibration is limited, and the entire algorithm analysis process is complex, cumbersome, and costly.
  • the present disclosure provides a delay calibration device and a delay calibration method.
  • an embodiment of the present disclosure provides a delay calibration device, which includes a delay calibration module.
  • the delay calibration module includes a coarse delay calibration unit and a fine delay calibration unit.
  • the coarse delay calibration unit is equipped with Set to receive an air interface pulse signal, and perform delay compensation on the associated pulse signal in the digital clock domain according to the air interface pulse signal.
  • the fine delay calibration unit includes a fine delay calibration subunit and a phase calibration subunit.
  • the fine delay calibration subunit is configured to, after the coarse delay calibration unit performs delay compensation on the associated path pulse signal in the digital clock domain according to the air interface pulse signal, perform delay compensation on the associated path in the analog clock domain.
  • the pulse signal is subjected to delay compensation;
  • the phase calibration subunit is configured to calibrate the clock domain phase after the fine delay calibration subunit performs delay compensation on the associated pulse signal in the analog clock domain.
  • embodiments of the present disclosure also provide a delay calibration method, which is applied to the delay calibration device as described above.
  • the method includes: receiving an air interface pulse signal, and calculating the time delay calibration in the digital clock domain according to the air interface pulse signal.
  • the path-associated pulse signal is subjected to delay compensation; the path-associated pulse signal is subjected to delay compensation in the analog clock domain, and the clock domain phase is calibrated.
  • Figure 1 is a schematic structural diagram of a delay calibration module in a delay calibration device according to an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the overall structure of a delay calibration device according to an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a second delay calibration module according to an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of RX link delay calibration timing according to an embodiment of the present disclosure
  • Figure 5 is a schematic structural diagram of a first delay calibration module according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of TX link delay calibration timing according to an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of a gate_pluse differential circuit according to an embodiment of the present disclosure.
  • Figure 8 is a timing diagram of the gate_pluse differential circuit according to an embodiment of the present disclosure.
  • Figure 9 is a schematic flow chart of a delay calibration method according to an embodiment of the present disclosure.
  • Figure 10 is a schematic flowchart of delay compensation for path-associated pulse signals in a transmission link according to an embodiment of the present disclosure
  • FIG. 11 is a schematic flowchart of delay compensation for a path-associated pulse signal in a receiving link according to an embodiment of the present disclosure.
  • Embodiments described herein may be described with reference to plan and/or cross-sectional illustrations, with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified based on manufacturing techniques and/or tolerances. Therefore, the embodiments are not limited to those shown in the drawings but include modifications of configurations formed based on the manufacturing process. Accordingly, the regions illustrated in the figures are of a schematic nature and the shapes of the regions shown in the figures are illustrative of the specific shapes of regions of the element and are not intended to be limiting.
  • FIG. 1 is a schematic structural diagram of a delay calibration module in a delay calibration device according to an embodiment of the present disclosure.
  • the delay calibration module includes a coarse delay calibration unit 10 and a fine delay calibration unit 20.
  • the coarse delay calibration unit 10 is configured to receive an air interface pulse signal (ref_pluse), Delay compensation is performed on the associated pulse signal (data_pluse) in the digital clock domain based on the air interface pulse signal (ref_pluse).
  • the fine delay calibration unit 20 includes a fine delay calibration subunit 21 and a phase calibration subunit 22.
  • the fine delay calibration subunit 21 is configured to, in the coarse delay calibration unit 22, perform calibration on the associated path in the digital clock domain according to the air interface pulse signal. After delay compensation is performed on the pulse signal, delay compensation is performed on the accompanying pulse signal in the analog clock domain.
  • the phase calibration subunit 22 is configured to calibrate the clock domain phase after the fine delay calibration subunit 21 performs delay compensation on the associated pulse signal in the analog clock domain.
  • the air interface pulse signal (ref_pluse) is generated by frequency division of the GPS 1PPS signal. It is generally an integer multiple of the T period and lasts for a period of high level.
  • the period of the accompanying pulse signal (data_pluse) is the same as the period of the air interface pulse signal, and it lasts for one period of high level in the clock domain.
  • the delay calibration device of the embodiment of the present disclosure uses the air interface pulse signal as a benchmark, and can improve the delay calibration accuracy to two high-frequency clock cycles by performing delay compensation in the digital clock domain and performing phase calibration in the analog high-frequency clock domain; By adjusting the path-associated pulse signal delay and digital clock phase in the digital clock domain, it replaces the traditional two-point synchronous post-sampling algorithm analysis, simplifies the calibration process, reduces the amount of algorithm calculations, and achieves fast and high-precision link timing; delay calibration device
  • the overall structure is simple and can be adapted to multi-channel, multi-mode and various working scenarios.
  • FIG. 2 is a schematic diagram of the overall structure of a delay calibration device according to an embodiment of the present disclosure.
  • the delay calibration device includes a transmit link (TX link), and the delay calibration module includes a first delay calibration module (DAC calibration) 100.
  • the first delay calibration module is located in the transmit link.
  • the coarse delay calibration unit 10 is the first coarse delay calibration unit 101
  • the fine delay calibration unit 20 is the first fine delay calibration unit 201
  • the path associated pulse signal is the transmitted path associated pulse signal.
  • the transmit link also includes a transmit link associated pulse generation module 110 and a transmit link associated pulse transmission module 120 .
  • the transmit associated pulse generation module 110 is configured to receive an air interface pulse signal and generate a transmit associated pulse signal based on the air interface pulse signal.
  • the transmit link associated pulse transmission module 120 is configured to, in the multi-clock domain of the transmit link, use the data valid enable signal to align the transmit link pulse signal and the link data, and send them to the first delay The first coarse delay calibration unit 101 of the calibration module 100.
  • the transmit associated pulse signal is generated in the transmit associated pulse signal generating module 110, and reaches the first delay calibration module (DAC calibration) 100 through each clock domain of the TX link for calibration.
  • DAC calibration first delay calibration module
  • the path-associated pulse signal and the link data are sent together through the multi-clock domain of the TX link, using the data effectively
  • the enable signal is aligned with the link data for transmission, so sending the path-associated pulse signal can reflect the link data transmission delay.
  • the delay calibration device also includes a receiving link (RX link), and the delay calibration module includes a second delay calibration module (ADC calibration) 200.
  • the second delay calibration module 200 is located at the receiving link; the path associated pulse signal is a received path associated pulse signal, the fine delay calibration unit 20 is the second fine delay calibration unit 202, the coarse delay calibration unit 10 is the second coarse delay calibration unit 102, and the second coarse delay calibration unit
  • the delay calibration unit 102 is also configured to generate a reception associated pulse signal (rx_data_pluse) according to the air interface pulse signal after receiving the air interface pulse signal.
  • the receive link also includes a receive link associated pulse calibration module 210 and a receive link associated pulse transmission module 220.
  • the receiving link associated pulse transmission module 220 is configured to, in the multi-clock domain of the receiving link, use the data valid enable signal to align and transmit the receiving link accompanying pulse signal and the link data, and send them to the receiving link associated pulse Calibration module 210.
  • the receiving channel associated pulse calibration module 210 is configured to perform delay compensation on the received channel associated pulse signal in the digital clock domain according to the air interface pulse signal.
  • the receive associated pulse signal is generated in the second delay calibration module (ADC calibration) 200, passes through each clock domain of the RX link, and reaches the receive associated pulse calibration module 210 for calibration.
  • ADC calibration second delay calibration module
  • the received path-associated pulse signal and link data pass through the multi-clock domain of the RX link together, and the data effective enable signal is used to align the transmission with the link data. Therefore, receiving the path-associated pulse signal can reflect the link Data transmission delay status.
  • FIG 3 is a schematic structural diagram of a second delay calibration module according to an embodiment of the present disclosure.
  • the second delay calibration module 200 includes a second coarse delay calibration unit (GEN_PLUSE) 102 and a second fine delay calibration unit.
  • the second coarse delay calibration unit 102 includes a second air interface pulse processing subunit (posedge0), a second path associated pulse signal regeneration subunit (regen2), a second delay subunit (delay2) and a second coarse delay calibration subunit. (ct_g).
  • the second air interface pulse processing subunit (posedge0) is configured to generate a single-cycle air interface pulse signal according to the rising edge of the air interface pulse signal (ref_pluse).
  • the second path-associated pulse signal regeneration subunit (regen) is respectively connected to the second air interface pulse processing subunit (posedge0) and the second delay subunit (delay2), and is configured to send data to the second air interface pulse processing subunit (posedge0).
  • the single-cycle air interface pulse signal is reduced by a preset multiple in a year-on-year period to generate a regenerative receive path associated pulse signal, and the regenerated receive path associated pulse signal is sent to the second delay subunit (delay2).
  • the air interface pulse is pre-configured in the second path-associated pulse signal regeneration subunit (regen).
  • the period T of the signal and the preset multiple N are used to generate a cyclic regenerative reception associated pulse signal based on the period T of the air interface pulse signal and the preset multiple N.
  • the second delay subunit (delay2) is configured to eliminate the delay between the regenerated reception path associated pulse signal and the next air interface pulse signal to obtain a second signal.
  • the second signal is the regenerated reception path associated pulse signal after eliminating the delay.
  • the second delay subunit (delay2) adds one beat each time for successive approximation.
  • Figure 4 is a schematic diagram of RX link delay calibration timing according to an embodiment of the present disclosure. As shown in Figure 4, at this time, the time delay difference Rd1 between the received path-associated pulse signal (i.e., the second signal) and the next air interface pulse signal is the asynchronous sampling uncertainty delay.
  • the second coarse delay calibration subunit (ct_g) is configured to perform a logical AND operation on the second signal and the single-cycle air interface pulse signal. If the operation result is not 1, perform coarse delay calibration until the operation result is 1. Stop the operation and generate a second instruction signal (gen_int_flag). The second instruction signal (gen_int_flag) is used to instruct the second fine delay calibration unit 202 to perform fine delay calibration.
  • the second coarse delay calibration subunit (ct_g) triggers a coarse delay calibration interrupt each time through the rising edge of the air interface pulse signal, until the AND result of the associated path pulse signal and the air interface pulse signal is 1, and generates ct_int_flag, indicating coarse delay calibration Finish.
  • the second coarse delay calibration unit 102 also includes a second expansion sub-unit (expand2), a second expansion sub-unit (expand2) and a second delay sub-unit (delay2) and a third
  • the two coarse delay calibration subunits (ct_g) are connected and configured to expand the high level length of the second signal according to 1 clock cycle, and send the expanded signal to the second coarse delay calibration subunit (ct_g), For the second coarse delay calibration subunit (ct_g) to perform a logical AND operation on the expanded signal and the single-cycle air interface pulse signal.
  • the second expansion subunit (expand2) expands the high-level length of the accompanying pulse signal (i.e. the second signal) according to 1 clock cycle, thereby eliminating the possible impact of the uncertainty of the asynchronous sampling delay difference and ensuring that the accompanying The pulse signal is earlier than the air interface pulse signal.
  • the second delay calibration module 200 sends out a receive path-associated pulse signal, and the receive path-associated pulse signal passes through multiple clock domains of the receive link associated pulse transmission module 220 in order to ensure that the path-associated pulse signal is received.
  • the signal remains at a high level for one clock cycle and is transmitted to the lower-level circuit synchronously with the data.
  • the difference between the receiving channel-associated pulse signal and the air interface pulse signal is R d3 -R d2 , where R d2 is The delay between receiving the path-associated pulse signal and the next air interface pulse signal, R d3 , is the link fixed delay R d31 plus the cross-clock domain uncertain delay R d32 .
  • Coarse delay calibration is performed in the receive path associated pulse calibration module 210 , and the coarse delay calibration process is the same as the coarse delay calibration process of the first delay calibration module 100 .
  • FIG. 5 is a schematic structural diagram of a first delay calibration module according to an embodiment of the present disclosure.
  • the first delay calibration module 100 includes a first coarse delay calibration unit (CT_PLUSE) 101 in the digital domain and a first fine delay calibration unit (DAC_FT_PLUSE) 201 in the analog domain.
  • CT_PLUSE first coarse delay calibration unit
  • DAC_FT_PLUSE first fine delay calibration unit
  • the first coarse delay calibration unit 101 includes a first air interface pulse processing subunit (posedge0), a first delay subunit (delay1) and a first coarse delay calibration subunit (ct_f).
  • the first air interface pulse processing subunit (posedge0) is configured to generate a single-cycle air interface pulse signal according to the rising edge of the air interface pulse signal.
  • the first delay subunit (delay1) is configured to eliminate the delay between the transmission associated pulse signal transmitted to the first coarse delay calibration unit 101 and the next air interface pulse signal to obtain the first signal (ct_data_pluse).
  • the transmit link associated pulse signal transmitted to the first coarse delay calibration unit 101 is the signal (dac_data_pluse) transmitted by the transmit link associated pulse transmission module 120 to the first coarse delay calibration unit 101 .
  • the first coarse delay calibration subunit (ct_f) is configured to perform a logical AND operation on the first signal (ct_data_pluse) and the single-cycle air interface pulse signal. If the operation result is not 1, perform coarse delay calibration until the required When the operation result is 1, the operation is stopped and a first instruction signal (ct_int_flag) is generated. The first instruction signal (ct_int_flag) is used to instruct the first fine delay calibration unit 201 to perform fine delay calibration.
  • the first coarse delay calibration subunit (ct_f) triggers a coarse delay calibration interrupt each time through the rising edge of the associated channel pulse signal until the AND result of the associated channel pulse signal and the air interface pulse signal is 1, and generates ct_int_flag, indicating the coarse delay Calibration completed.
  • FIG. 6 is a schematic diagram of the timing of TX link delay calibration according to an embodiment of the present disclosure.
  • T d4 T d1 +T d22 +T d31
  • T d1 is the transmitted associated channel pulse signal.
  • T d22 is the uncertain delay across the clock domain
  • T d31 is the sampling delay of the air interface pulse signal in the DAC digital clock domain.
  • the first coarse delay calibration unit 101 also includes a comparison subunit (counter0).
  • the comparison subunit (counter0) is configured to calculate a single-cycle air interface pulse signal and transmit it to the first The time difference of the transmit associated pulse signal (dac_data_pluse) of the coarse delay calibration unit 101, so as to configure the transmit associated pulse signal (dac_data_pluse) and the next air interface pulse signal transmitted to the first coarse delay calibration unit according to the time difference delay between.
  • the comparison subunit (counter0) obtains the time difference between the single-cycle air interface pulse signal and the transmission associated pulse signal (dac_data_pluse), it adds one beat each time to successively approach the configuration.
  • the first coarse delay calibration unit 101 also includes a first air port pulse impulse signal regeneration sub-unit (regen_1) and the first path-associated pulse signal regeneration sub-unit (regen_0).
  • the first air interface pulse signal regeneration subunit (regen_1) is connected to the first air interface pulse processing subunit (posedge0) and the first coarse delay calibration subunit (ct_f), and is configured to reduce the air interface pulse signal (ref_pluse) according to the same period
  • the regenerated air interface pulse signal is generated at a preset multiple, and the regenerated air interface pulse signal is sent to the first coarse delay calibration subunit (ct_f).
  • the period T and the preset multiple N of the air interface pulse signal (ref_pluse) are pre-configured in the first air interface pulse signal regeneration subunit (regen_1), and a cyclic regeneration is generated according to the period T and the preset multiple N of the air interface pulse signal (ref_pluse).
  • Air interface pulse signal is pre-configured in the first air interface pulse signal regeneration subunit (regen_1), and a cyclic regeneration is generated according to the period T and the preset multiple N of the air interface pulse signal (ref_pluse).
  • the first path associated pulse signal regeneration sub-unit (regen_0) is connected to the first delay sub-unit (delay1), and is configured to reduce the transmit path associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101 by a year-on-year period
  • the preset multiple generates the regenerative transmission path associated pulse signal, and sends the regeneration transmission path associated pulse signal to the first delay subunit (delay1), so that the first delay subunit can eliminate the regeneration transmission path associated pulse signal and the next air interface pulse signal. delay between.
  • the period T and the preset multiple N for sending the accompanying pulse signal (dac_data_pluse) are pre-configured in the first accompanying pulse signal regeneration subunit (regen_0). According to the period T and the preset multiple N for sending the accompanying pulse signal (dac_data_pluse) N generates cycles of regeneration and transmission of path-associated pulse signals.
  • the transmitted path-associated pulse signal (dac_data_pluse) and the air interface pulse signal (ref_pluse) are cyclically regenerated by reducing the N times of the same period.
  • the coarse delay calibration process can be performed N times within an air interface pulse signal period, which greatly speeds up the coarse delay calibration.
  • the first coarse delay calibration unit 101 also includes a first expansion subunit (expand1), a first expansion subunit (expand1) and a first delay subunit (delay1) and a first A coarse delay calibration subunit (ct_f) is connected and configured to expand the high-level length of the first signal (ct_data_pluse) according to 1 clock cycle, and send the expanded signal to the first coarse delay calibration subunit ( ct_f), for the first coarse delay calibration subunit (ct_f) to perform a logical AND operation on the expanded signal sum and the single-cycle air interface pulse signal.
  • the first expansion subunit (expand1) expands the high-level length of the accompanying pulse signal (i.e. the first signal) according to 1 clock cycle, thereby avoiding the uncertainty of the delay difference that may be caused by two asynchronous sampling and crossing the clock domain. , ensuring that the accompanying pulse signal is earlier than the air interface pulse signal.
  • the transmission channel associated pulse generation module 110 synchronously generates the channel associated pulse signal (data_pluse).
  • the channel-associated pulse signal (data_pluse) here refers to the transmission of the channel-associated pulse signal.
  • the clock since the clock asynchronously samples the air interface pulse signal (ref_pluse), there may be a metastable situation, and the path pulse signal (data_pluse)
  • the delay difference from the air interface pulse signal (ref_pluse) is one T1 clock domain period Td1.
  • the path-associated pulse signal (data_pluse) passes through multiple clock domains of the sending link path-associated pulse transmission module 120 in sequence, and is controlled by the data effective enable signal.
  • the path-associated pulse signal (data_pluse) is processed according to different working scenarios or modes. For example, multiple expansion of different decimation filters or non-power-saving processing of TDD (Time Division Duplexing) scenarios ensure that the pulse signal along the path is sampled by the lower-level circuit and only maintains a high level for one clock cycle, and is transmitted synchronously with the data. to lower level circuits.
  • TDD Time Division Duplexing
  • the pulse When arriving at the DAC digital clock domain, the pulse The difference between the signal (data_pluse) and the air interface pulse signal (ref_pluse) that generates it is Td1+Td2, where Td2 is the link fixed delay Td21 plus the cross-clock domain uncertain delay Td22.
  • the structures of the first fine delay calibration unit 201 and the second fine delay calibration unit 202 are basically the same.
  • the first precision delay calibration unit 201 and the second precision delay calibration unit 202 both include a path associated pulse processing subunit (posedge), a judgment subunit (count), and an air interface pulse synchronization subunit. (sync1), path-associated pulse synchronization subunit (sync0), fine delay calibration subunit (not shown in the figure) and fine delay calibration interrupt subunit (ft_int_gen).
  • the path-associated pulse processing subunit (posedge) is configured to receive the path-associated pulse signal sent by the coarse delay calibration unit in the delay calibration module, generate a single-cycle path-associated pulse signal according to the rising edge of the path-associated pulse signal, and The single-cycle path-associated pulse signal is sent to the first fine delay calibration interrupt subunit; where, in the first fine delay calibration unit 201, the path-associated pulse signal is the first signal sent by the first coarse delay calibration unit 101, In the second fine delay calibration unit 202, the associated pulse signal is the second signal sent by the second coarse delay calibration unit 102.
  • the air interface pulse synchronization subunit (sync1) is configured to synchronize the air interface pulse signal to the clock domain where it is located, and send the synchronized air interface pulse signal to the judgment subunit (count).
  • the path-associated pulse synchronization subunit (sync0) is configured to synchronize the path-associated pulse signal to the clock domain where it is located, and send the synchronized path-associated pulse signal to the judgment subunit (count).
  • the judgment subunit (count) is configured to perform a logical AND operation on the synchronized air interface pulse signal and the synchronized path associated pulse signal.
  • the fine delay calibration subunit is used to perform fine delay calibration when the calculation result calculated by the judgment subunit (count) is 0. It should be noted that the precision delay calibration subunit can be a functional module implemented through software.
  • the fine delay calibration interrupt subunit (ft_int_gen) is configured to, according to the single-cycle path accompanying pulse signal
  • the trigger generates an interrupt signal, which is used to stop fine delay calibration.
  • the fine delay calibration subunit of the first fine delay calibration unit 201 is configured to successively add 1 to the read address of the first-in first-out memory (FIFO) across the clock domain in the transmission link to adjust the transmission.
  • the fine delay calibration subunit of the second fine delay calibration unit 202 is configured to adjust the delay between the regenerated reception associated pulse signal and the next air interface pulse signal.
  • the first precise delay calibration unit 201 of the first delay calibration module 100 includes a phase calibration sub-unit
  • the second precise delay calibration unit 202 of the second delay calibration module 200 includes a phase calibration sub-unit. subunit.
  • the phase calibration subunit includes a differential pulse gate control subunit (gate_pluse) and a clock frequency division subunit (clk_div).
  • the differential pulse gate control subunit (gate_pluse) is configured to adjust the initial phase of the clock signal in the analog domain according to the gate control signal.
  • the clock frequency division subunit (clk_div) is configured to adjust the initial phase of the clock signal in the digital domain according to the initial phase of the clock signal in the analog domain.
  • Precision delay calibration includes precision delay compensation and phase calibration.
  • the synchronized air interface pulse signal and the synchronized path associated pulse signal are subjected to a logical AND operation in the judgment subunit (count).
  • the fine delay calibration subunit is instructed to perform fine delay compensation.
  • the delay difference is one clock cycle T dac_dig in the DAC digital clock domain and one clock cycle T dac_ana in the DAC analog clock domain.
  • FIG. 7 is a schematic structural diagram of a gate_pluse differential circuit according to an embodiment of the present disclosure
  • FIG. 8 is a schematic timing diagram of a gate_pluse differential circuit according to an embodiment of the present disclosure.
  • the differential pulse gate control subunit can turn off a clock every time the gate control is enabled.
  • the periodic clock combined with the clock frequency division subunit (clk_div), allows the DAC's digital clock clk_dac_dig to adjust the initial frequency division phase of the DAC's analog clock clk_dac_ana each time.
  • the phase calibration is completed, as shown in Figure 6.
  • the delay accuracy of sending the accompanying pulse signal and the next air interface pulse signal is T d5 , that is, two DAC analog clocks Domain clock period T dac_ana .
  • the second fine delay calibration unit 202 performs fine delay calibration.
  • the fine delay calibration process is the same as the fine delay calibration process performed by the first fine delay calibration unit 201, but there are the following differences:
  • Precision delay compensation adjusts delay in different ways.
  • the delay between the regenerated reception associated pulse signal and the next air interface pulse signal is adjusted;
  • the first precision delay calibration unit In 201 the FIFO read address across the clock domain in the transmission link is increased by 1 successively to adjust the delay of the transmission associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit.
  • the trigger signals for precision delay calibration interrupts are different.
  • the fine delay calibration interrupt is triggered by the rising edge of the air interface pulse signal (ref_pluse); in the first fine delay calibration unit 201, the fine delay calibration interrupt is triggered by the accompanying pulse signal (data_pluse) Triggered by rising edge.
  • the delay accuracy of receiving the accompanying pulse signal and the next air interface pulse signal is R d2 , that is, the two ADC analog clock domain clock periods T adc_ana .
  • the delay calibration device of the embodiment of the present disclosure uses the air interface pulse signal as the benchmark, utilizes the synchronous transmission property after the alignment of the path pulse signal and the link data, and performs delay compensation in the digital clock domain and simulates the ADDA high-frequency clock domain.
  • Phase calibration can improve the delay calibration accuracy to two high-frequency clock cycles.
  • the software adjusts the path-following pulse signal delay and digital clock phase of the initial/last-level digital clock domain, replacing the traditional two-point synchronous post-sampling algorithm analysis. It not only greatly simplifies the calibration process, but also avoids a large number of algorithm calculations. High-precision timing of the link can be quickly performed during the initialization of the power-on process or during normal operation.
  • the delay calibration device of the embodiment of the present disclosure has a simple overall structure and can be adapted to multi-channel, multi-mode and various working scenarios.
  • Embodiments of the present disclosure can be applied to radio frequency transceiver systems of terminals or base stations, supporting high-precision delay calibration in multiple links, multiple clock domains, and multiple working modes. Supports TX and RX multi-link expansion, and can combine the multi-link path-associated pulse signals to be generated and calibrated in the transmit-associated pulse signal generation module 110 and the receive-associated pulse signal calibration module 210 in the digital interface.
  • the embodiment of the present disclosure supports multi-system docking of the whole machine, and can transfer the transmit path-associated pulse signal generation module 110 and the receive path-associated pulse signal calibration module 210 in the digital interface to the upstream chip system link source/end, which can control the entire chain. High-precision calibration of path delay.
  • the disclosed embodiments are suitable for transceiver systems with high latency requirements and cross-clock domain or asynchronous clock domains, and can be widely used in radio frequency chips, terminal chips and baseband chips with corresponding requirements.
  • An embodiment of the present disclosure also provides a delay calibration method, which method is applied to the delay calibration device as described above. As shown in Figure 9, the method includes the following steps:
  • Step S11 Receive the air interface pulse signal, and perform delay compensation on the associated pulse signal in the digital clock domain based on the air interface pulse signal.
  • the coarse delay calibration unit 10 performs delay compensation on the associated pulse signal in the digital clock domain according to the air interface pulse signal.
  • Step S12 perform delay compensation on the path-associated pulse signal in the analog clock domain, and calibrate the clock domain phase.
  • the fine delay calibration subunit 21 of the fine delay calibration unit 20 performs delay compensation on the associated pulse signal in the analog clock domain, and the phase calibration subunit of the fine delay calibration unit 20 performs calibration on the clock domain phase. .
  • the delay calibration method of the embodiment of the present disclosure uses the air interface pulse signal as the benchmark, and can improve the delay calibration accuracy to two high-frequency clock cycles by performing delay compensation in the digital clock domain and performing phase calibration in the analog high-frequency clock domain. ; By adjusting the path-associated pulse signal delay and digital clock phase in the digital clock domain, it replaces the traditional algorithm analysis after two-point synchronous sampling, simplifies the calibration process, reduces the amount of algorithm calculations, and achieves fast and high-precision link timing; delay calibration
  • the overall structure of the device is simple and can be adapted to multi-channel, multi-mode and various working scenarios.
  • step S11 performing delay compensation on the associated pulse signal in the digital clock domain according to the air interface pulse signal (i.e. step S11) includes the following steps:
  • Step S111 Generate a transmission associated pulse signal based on the air interface pulse signal.
  • Step S112 In the multi-clock domain of the transmission link, the transmission path associated pulse signal and the link data are aligned and transmitted using the data valid enable signal.
  • Step S113 Perform delay compensation on the transmitted path-associated pulse signal in the digital clock domain according to the air interface pulse signal.
  • step S11 in the receiving link, performing delay compensation on the associated pulse signal in the digital clock domain according to the air interface pulse signal (i.e. step S11) includes the following steps:
  • Step S111' Generate a receive associated pulse signal based on the air interface pulse signal.
  • Step S112' in the multi-clock domain of the receiving link, use the data valid enable signal to align and transmit the receiving path associated pulse signal and the link data.
  • Step S113' perform delay compensation on the received path-associated pulse signal that has undergone aligned transmission in the digital clock domain according to the air interface pulse signal.
  • generating a receive associated pulse signal based on the air interface pulse signal includes the following steps: generating a single-cycle air interface pulse signal based on the rising edge of the air interface pulse signal, and generating a single-cycle air interface pulse signal based on the rising edge of the air interface pulse signal.
  • the air interface pulse signal is reduced by a preset multiple in a year-on-year period to generate a regenerated reception associated pulse signal.
  • Performing delay compensation includes the following steps:
  • the method further includes the following steps: extending the high frequency of the second signal according to 1 clock cycle.
  • the level length is used to perform a logical AND operation on the expanded signal and the single-cycle air interface pulse signal.
  • delay compensation for transmitting the associated pulse signal in the digital clock domain according to the air interface pulse signal includes the following steps:
  • the method before eliminating the delay between the transmission associated pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method further includes the following steps: calculating the single cycle The time difference between the air interface pulse signal and the transmit associated pulse signal transmitted to the first coarse delay calibration unit, so as to configure the transmit associated pulse transmitted to the first coarse delay calibration unit according to the time difference The delay between the signal and the next air interface pulse signal.
  • the method before eliminating the delay between the transmission associated pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal, the method further includes the following steps: Reduce the preset multiple of the year-on-year period to generate a regenerated air interface pulse signal; reduce the transmission path associated pulse signal transmitted to the first coarse delay calibration unit by reducing the preset multiple of the year-on-year period to generate a regenerated transmission path associated pulse signal, so as to eliminate the regeneration transmission path associated pulse signal. The delay between the channel pulse signal and the next air interface pulse signal.
  • the method before performing a logical AND operation on the first signal and the single-cycle air interface pulse signal, the method further includes the following steps: extending the high-level length of the first signal according to 1 clock cycle, so as to The expanded signal sum is logically ANDed with the single-cycle air interface pulse signal.
  • the method further includes the following steps:
  • the path-following pulse signal Receives the path-following pulse signal, and generate a single-cycle path-following pulse signal according to the rising edge of the path-following pulse signal; the path-following pulse signal is the first signal or the second signal;
  • performing precise delay calibration includes the following steps:
  • calibrating the clock domain phase includes the following steps:
  • the initial phase of the clock signal in the digital domain is adjusted according to the initial phase of the clock signal in the analog domain.
  • the delay calibration process of the embodiment of the present disclosure is described in detail below through a specific example.
  • the specific steps of the delay calibration process are as follows:
  • the air interface pulse signal is sent in an external loop, and the TX path accompanying pulse generator is used to directly generate the path accompanying pulse signal of the TX link.
  • the ADC calibration unit is used to generate the path accompanying pulse of the RX link through coarse delay calibration and fine delay calibration. Signal.
  • the ADC coarse delay calibration process is: the rising edge of the air interface pulse signal triggers the ADC coarse delay calibration interrupt of the software. Each time the software increases the delay by 1 beat until the result of the sum of the channel pulse signal and the air interface pulse signal is 1, which means Coarse delay calibration is completed.
  • the ADC precision delay calibration process is: the rising edge of the air interface pulse signal triggers the ADC fine adjustment interrupt of the software. If the count value of the sum of the accompanying pulse signal and the air interface pulse signal is 0, continue to increase the delay by 1 beat to perform precise timing. Delayed compensation. If the count value is not 0, the software performs a process of closing and opening the clock gating, and performs phase adjustment until the count value equals the established threshold, indicating that the fine delay calibration is completed.
  • TX and RX pulse signals are transmitted in the link and reach the DAC calibration unit and RX pulse signal calibrator respectively.
  • the DAC coarse delay calibration process is: the rising edge of the path pulse signal triggers the software's DAC coarse delay calibration interrupt. After reading the counter value of the comparison module, set a similar delay value, and then the software increases the delay by 1 beat each time. , until the result of the AND of the channel pulse signal and the air interface pulse signal is 1, indicating that the coarse delay calibration is completed.
  • the DAC fine delay calibration process is: the rising edge of the associated pulse signal triggers the software's DAC fine delay calibration interrupt.
  • the DAC cross-clock domain FIFO Read the address and add 1 successively to adjust the pulse delay along the path to perform precise delay compensation.
  • the software performs a process of closing and opening the clock gating, and performs phase adjustment until the count value equals the established threshold, indicating that the fine delay calibration is completed.
  • the coarse delay calibration in the RX pulse calibrator is the same as the coarse delay calibration process of the DAC.
  • Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a general illustrative sense only and not for purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics and/or elements described in connection with a particular embodiment may be used alone, or may be used in conjunction with other embodiments, unless expressly stated otherwise. Features and/or components used in combination. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention as set forth in the appended claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Pulse Circuits (AREA)

Abstract

本公开提供一种时延校准装置，包括时延校准模块，时延校准模块包括粗时延校准单元和精时延校准单元，粗时延校准单元用于，接收空口脉冲信号，根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿；精时延校准单元包括精时延校准子单元和相位校准子单元，精时延校准子单元用于在模拟时钟域对随路脉冲信号进行时延补偿，相位校准子单元用于对时钟域相位进行校准。本公开还提供一种时延校准方法。摘图1

Description

时延校准装置及时延校准方法
相关公开的交叉引用
本公开要求在2022年8月31日提交国家知识产权局、公开号为CN202211058378.8、发明名称为“时延校准装置及时延校准方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本公开中。
技术领域
本公开的实施例涉及但不限于通信技术领域，具体涉及一种时延校准装置及时延校准方法。
背景技术
近些年5G通信迅速发展，Massive MIMO(大规模天线技术)和GPS 1PPS(Global Positioning System Pulse Per Second，全球定位系统秒脉冲)授时等技术提高了系统容量和时钟精度。伴随而来的对于射频收发系统的数字链路时延的精度也提出了更高的要求。但受限于数字链路的跨时钟域异步处理，复位路径长度差异，集成电路工艺特性的变化(如工艺角、电源电压和温度，统称PVT)等因素，在初始上电和工作过程中，数字链路的时延会存在差异。这种差异会在产品形态的多天线表现出来，需要进行数据对齐处理。
目前对于这种处理，采用的方法是构造特殊激励数据，对数字链路数据进行双点采样，根据相关性算法分析，得到数据链路的传输延时，再通过校正对齐数据。但是，双点采样链路时延校准精度有限，整个算法分析过程比较复杂和繁琐，代价较大。
发明内容
本公开提供一种时延校准装置及时延校准方法。
第一方面，本公开实施例提供一种时延校准装置，包括时延校准模块，所述时延校准模块包括粗时延校准单元和精时延校准单元。所述粗时延校准单元被配 置成，接收空口脉冲信号，根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿。所述精时延校准单元包括精时延校准子单元和相位校准子单元。所述精时延校准子单元被配置成，在所述粗时延校准单元根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿之后，在模拟时钟域对所述随路脉冲信号进行时延补偿；所述相位校准子单元被配置成，在所述精时延校准子单元在模拟时钟域对所述随路脉冲信号进行时延补偿之后，对时钟域相位进行校准。
又一方面，本公开实施例还提供一种时延校准方法，应用于如前所述的时延校准装置，所述方法包括：接收空口脉冲信号，根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿；在模拟时钟域对所述随路脉冲信号进行时延补偿，并对时钟域相位进行校准。
附图说明
图1为根据本公开实施例的时延校准装置中时延校准模块的结构示意图；
图2为根据本公开实施例的时延校准装置的整体结构示意图；
图3为根据本公开实施例的第二时延校准模块的结构示意图；
图4为根据本公开实施例的RX链路时延校准时序示意图；
图5为根据本公开实施例的第一时延校准模块的结构示意图；
图6为根据本公开实施例的TX链路时延校准时序示意图；
图7为根据本公开实施例的gate_pluse差分电路结构示意图；
图8为根据本公开实施例的gate_pluse差分电路时序示意图；
图9为根据本公开实施例的时延校准方法流程示意图；
图10为根据本公开实施例的发送链路中对随路脉冲信号进行时延补偿的流程示意图；
图11为根据本公开实施例的接收链路中对随路脉冲信号进行时延补偿的流程示意图。
具体实施方式
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施 例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其他特征、整体、步骤、操作、元件、组件和/或其群组。
本文所述实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此，可根据制造技术和/或容限来修改示例图示。因此，实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不旨在是限制性的。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
在相关技术中，对数字链路数据进行双点采样进行时延校准，存在以下弊端：
1、链路时延校准精度有限。传统的双点同步采样方法面对链路跨时钟域时，都存在1个该时钟域时钟周期精度的不确定性，而且由于是在数字时钟域采样，其时钟频率较低，单时钟周期的时间差异。
2、整个算法分析过程比较复杂和繁琐，代价较大。首先，需要针对不同系统数字链路的不同场景下数据处理方式构造对应的激励数据进行处理；其次，离线分析无法做到产品即时应用，而在线分析、将会消耗大量的软硬件资源，增加较多的功耗；最后无论是对于上电过程的初始化校正还是正常工作过程中的再校正，整体的耗时都比较长，不利于快速完成系统的高精度授时。
为了解决上述问题，本公开实施例提供一种时延校准装置，所述时延校准装置包括时延校准模块。图1为根据本公开实施例的时延校准装置中时延校准模块的结构示意图。如图1所示，所述时延校准模块包括粗时延校准单元10和精时延校准单元20，粗时延校准单元10被配置成，接收空口脉冲信号(ref_pluse)， 根据空口脉冲信号(ref_pluse)在数字时钟域对随路脉冲信号(data_pluse)进行时延补偿。
精时延校准单元20包括精时延校准子单元21和相位校准子单元22，精时延校准子单元21被配置成，在粗时延校准单元22根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿之后，在模拟时钟域对随路脉冲信号进行时延补偿。
相位校准子单元22被配置成，在精时延校准子单元21在模拟时钟域对随路脉冲信号进行时延补偿之后，对时钟域相位进行校准。
空口脉冲信号(ref_pluse)由GPS 1PPS信号分频产生，一般为T周期整数倍，持续一段时间的高电平。随路脉冲信号(data_pluse)的周期与空口脉冲信号的周期相同，持续所处时钟域1个周期的高电平。
本公开实施例的时延校准装置以空口脉冲信号为基准，通过在数字时钟域进行时延补偿和模拟高频时钟域进行相位校准，可以将时延校准精度提升为两个高频时钟周期；通过调整数字时钟域的随路脉冲信号时延和数字时钟相位，取代了传统的双点同步采样后算法分析，简化校准流程，降低算法计算量，实现链路快速高精度授时；时延校准装置整体结构简单，可以适配多通道、多模式和多种工作场景。
图2为根据本公开实施例的时延校准装置的整体结构示意图。如图2所示，所述时延校准装置包括发送链路(TX链路)，而时延校准模块包括第一时延校准模块(DAC校准)100，第一时延校准模块位于发送链路；粗时延校准单元10为第一粗时延校准单元101，精时延校准单元20为第一精时延校准单元201，随路脉冲信号为发送随路脉冲信号。
所述发送链路(TX链路)还包括发送链路还包括发送随路脉冲发生模块110和发送链路随路脉冲传输模块120。发送随路脉冲发生模块110被配置成，接收空口脉冲信号，根据空口脉冲信号生成发送随路脉冲信号。
发送链路随路脉冲传输模块120被配置成，在发送链路的多时钟域内，利用数据有效使能信号，将发送随路脉冲信号和链路数据进行对齐传输，并发送给第一时延校准模块100的第一粗时延校准单元101。
发送随路脉冲信号在发送随路脉冲信号发生模块110中产生，经过TX链路各时钟域到达第一时延校准模块(DAC校准)100进行校准。在进行信号传输时，发送随路脉冲信号和链路数据一起通过TX链路的多时钟域，利用数据有效 使能信号与链路数据进行对齐传输，因此发送随路脉冲信号可以体现出链路数据传输的时延状况。
如图2所示，所述时延校准装置还包括接收链路(RX链路)，而时延校准模块包括第二时延校准模块(ADC校准)200，第二时延校准模块200位于接收链路；随路脉冲信号为接收随路脉冲信号，精时延校准单元20为第二精时延校准单元202，粗时延校准单元10为第二粗时延校准单元102，第二粗时延校准单元102还用于在接收空口脉冲信号之后，根据空口脉冲信号生成接收随路脉冲信号(rx_data_pluse)。
接收链路(RX链路)还包括接收随路脉冲校准模块210和接收链路随路脉冲传输模块220。接收链路随路脉冲传输模块220被配置成，在接收链路的多时钟域内，利用数据有效使能信号，将接收随路脉冲信号和链路数据进行对齐传输，并发送给接收随路脉冲校准模块210。
接收随路脉冲校准模块210被配置成，根据空口脉冲信号在数字时钟域对接收到的随路脉冲信号进行时延补偿。
接收随路脉冲信号在第二时延校准模块(ADC校准)200中产生，经过RX链路各时钟域到达接收随路脉冲校准模块210进行校准。在进行信号传输时，接收随路脉冲信号和链路数据一起通过RX链路的多时钟域，利用数据有效使能信号与链路数据进行对齐传输，因此接收随路脉冲信号可以体现出链路数据传输的时延状况。
图3为根据本公开实施例的第二时延校准模块的结构示意图，如图3所示，第二时延校准模块200包括第二粗时延校准单元(GEN_PLUSE)102和第二精时延校准单元(ADC_FT_PLUSE)202。
第二粗时延校准单元102包括第二空口脉冲处理子单元(posedge0)、第二随路脉冲信号再生子单元(regen2)、第二延迟子单元(delay2)和第二粗时延校准子单元(ct_g)。第二空口脉冲处理子单元(posedge0)被配置成，根据空口脉冲信号(ref_pluse)的上升沿生成单周期空口脉冲信号。
第二随路脉冲信号再生子单元(regen)分别与第二空口脉冲处理子单元(posedge0)和第二延迟子单元(delay2)相连，被配置成对第二空口脉冲处理子单元(posedge0)发送的单周期空口脉冲信号按同比周期缩小预设倍数生成再生接收随路脉冲信号，并将再生接收随路脉冲信号发送给第二延迟子单元(delay2)。其中，第二随路脉冲信号再生子单元(regen)中预先配置空口脉冲 信号的周期T和预设倍数N，根据空口脉冲信号的周期T和预设倍数N生成循环的再生接收随路脉冲信号。
第二延迟子单元(delay2)被配置成，消除再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第二信号，第二信号为消除延迟后的再生接收随路脉冲信号。第二延迟子单元(delay2)配置与空口脉冲信号的周期T相近的延迟后，每次增加一拍进行逐次逼近。图4为根据本公开实施例的RX链路时延校准时序示意图。如图4所示，此时接收随路脉冲信号(即第二信号)和下一个空口脉冲信号的时延差异Rd1为异步采样不确定时延。
第二粗时延校准子单元(ct_g)被配置成，将第二信号和单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到运算结果为1时停止运算，并生成第二指示信号(gen_int_flag)，第二指示信号(gen_int_flag)用于指示第二精时延校准单元202进行精时延校准。第二粗时延校准子单元(ct_g)每次通过空口脉冲信号的上升沿触发粗时延校准中断，直到随路脉冲信号和空口脉冲信号相与结果为1，产生ct_int_flag，表示粗时延校准完成。
在一些实施例中，如图3所示，第二粗时延校准单元102还包括第二扩展子单元(expand2)，第二扩展子单元(expand2)与第二延迟子单元(delay2)和第二粗时延校准子单元(ct_g)连接，被配置成按照1个时钟周期扩展第二信号的高电平长度，并将扩展后的信号发送给第二粗时延校准子单元(ct_g)，以供第二粗时延校准子单元(ct_g)将扩展后的信号和单周期空口脉冲信号进行逻辑与运算。第二扩展子单元(expand2)按照1个时钟周期扩展随路脉冲信号(即第二信号)的高电平长度，从而消除异步采样时延差的不确定性可能带来的影响，保证随路脉冲信号早于空口脉冲信号。
结合图2和图4所示，第二时延校准模块200发出接收随路脉冲信号，接收随路脉冲信号依次经过接收链路随路脉冲传输模块220的多个时钟域，保证接收随路脉冲信号保持一个时钟周期高电平，与数据同步传输给下级电路，到达接收随路脉冲校准模块210时，接收随路脉冲信号与空口脉冲信号的差异为Rd3-Rd2，其中，Rd2为接收随路脉冲信号和下一个空口脉冲信号的时延，Rd3为链路固定时延Rd31加跨时钟域不确定时延Rd32。在接收随路脉冲校准模块210内进行粗时延校准，该粗时延校准过程与第一时延校准模块100的粗时延校准过程相同。最终的时延精度为Rd5＝Rd2+Rd51，其中，Rd51为一个RX接口时钟域的时钟周期R1，Rd2为两个ADC模拟时钟域的时钟周期Tadc_ana之和。
图5为根据本公开实施例的第一时延校准模块的结构示意图。如图5所示，第一时延校准模块100包括数字域的第一粗时延校准单元(CT_PLUSE)101和模拟域的第一精时延校准单元(DAC_FT_PLUSE)201。
第一粗时延校准单元101包括第一空口脉冲处理子单元(posedge0)、第一延迟子单元(delay1)和第一粗时延校准子单元(ct_f)。
第一空口脉冲处理子单元(posedge0)被配置成，根据空口脉冲信号的上升沿生成单周期空口脉冲信号。
第一延迟子单元(delay1)被配置成，消除传输至第一粗时延校准单元101的发送随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第一信号(ct_data_pluse)。其中，传输至第一粗时延校准单元101的发送随路脉冲信号是发送链路随路脉冲传输模块120传输给第一粗时延校准单元101的信号(dac_data_pluse)。
第一粗时延校准子单元(ct_f)被配置成，将第一信号(ct_data_pluse)和单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到所述运算结果为1时停止运算，并生成第一指示信号(ct_int_flag)，第一指示信号(ct_int_flag)用于指示第一精时延校准单元201进行精时延校准。第一粗时延校准子单元(ct_f)每次通过随路脉冲信号的上升沿触发粗时延校准中断，直到随路脉冲信号和空口脉冲信号相与结果为1，产生ct_int_flag，表示粗时延校准完成。
图6为根据本公开实施例的TX链路时延校准时序示意图。如图6所示，经过粗时延校准后，此时发送随路脉冲信号和下一个空口脉冲信号的时延差异Td4＝Td1+Td22+Td31，其中，Td1为发送随路脉冲信号与空口脉冲信号的异步采样时延，Td22为跨时钟域不确定时延，Td31为DAC数字时钟域空口脉冲信号采样时延。
在一些实施例中，如图5所示，第一粗时延校准单元101还包括比较子单元(counter0)，比较子单元(counter0)被配置成，计算单周期空口脉冲信号和传输至第一粗时延校准单元101的发送随路脉冲信号(dac_data_pluse)的时间差，以便根据所述时间差配置传输至所述第一粗时延校准单元的发送随路脉冲信号(dac_data_pluse)和下一个空口脉冲信号之间的延迟。比较子单元(counter0)得到单周期空口脉冲信号和发送随路脉冲信号(dac_data_pluse)的时间差后，每次增加一拍逐次逼近配置。
在一些实施例中，如图5所示，第一粗时延校准单元101还包括第一空口脉 冲信号再生子单元(regen_1)和第一随路脉冲信号再生子单元(regen_0)。
第一空口脉冲信号再生子单元(regen_1)与第一空口脉冲处理子单元(posedge0)和第一粗时延校准子单元(ct_f)连接，被配置成将空口脉冲信号(ref_pluse)按同比周期缩小预设倍数生成再生空口脉冲信号，并将再生空口脉冲信号发送给第一粗时延校准子单元(ct_f)。其中，第一空口脉冲信号再生子单元(regen_1)中预先配置空口脉冲信号(ref_pluse)的周期T和预设倍数N，根据空口脉冲信号(ref_pluse)的周期T和预设倍数N生成循环的再生空口脉冲信号。
第一随路脉冲信号再生子单元(regen_0)与第一延迟子单元(delay1)连接，被配置成对传输至第一粗时延校准单元101的发送随路脉冲信号(dac_data_pluse)按同比周期缩小预设倍数生成再生发送随路脉冲信号，并将再生发送随路脉冲信号发送给第一延迟子单元(delay1)，以供第一延迟子单元消除再生发送随路脉冲信号和下一个空口脉冲信号之间的延迟。其中，第一随路脉冲信号再生子单元(regen_0)中预先配置发送随路脉冲信号(dac_data_pluse)的周期T和预设倍数N，根据发送随路脉冲信号(dac_data_pluse)的周期T和预设倍数N生成循环的再生发送随路脉冲信号。
发送随路脉冲信号(dac_data_pluse)和空口脉冲信号(ref_pluse)按同比周期缩小N倍循环再生，可以在一个空口脉冲信号周期内进行N次粗时延校准流程，大大加快粗时延校准的速度。
在一些实施例中，如图5所示，第一粗时延校准单元101还包括第一扩展子单元(expand1)，第一扩展子单元(expand1)与第一延迟子单元(delay1)和第一粗时延校准子单元(ct_f)连接，被配置成按照1个时钟周期扩展第一信号(ct_data_pluse)的高电平长度，并将扩展后的信号发送给第一粗时延校准子单元(ct_f)，以供第一粗时延校准子单元(ct_f)将扩展后的信号和和单周期空口脉冲信号进行逻辑与运算。第一扩展子单元(expand1)按照1个时钟周期扩展随路脉冲信号(即第一信号)的高电平长度，从而避免两次异步采样和跨时钟域可能造成的时延差的不确定性，保证随路脉冲信号早于空口脉冲信号。
结合图2和图6所示，发送随路脉冲发生模块110在接收到空口脉冲信号(ref_pluse)后，同步产生随路脉冲信号(data_pluse)。需要说明的是，这里的随路脉冲信号(data_pluse)指的是发送随路脉冲信号。此时由于时钟异步采样空口脉冲信号(ref_pluse)，可能存在亚稳态情景，随路脉冲信号(data_pluse) 与空口脉冲信号(ref_pluse)的延迟差异为一个T1时钟域周期Td1。随路脉冲信号(data_pluse)依次经过发送链路随路脉冲传输模块120的多个时钟域，通过数据有效使能信号控制，根据不同的工作场景或者模式对随路脉冲信号(data_pluse)进行处理，如不同抽取滤波器的倍数扩展或者TDD(Time Division Duplexing，时分双工)场景的不节电处理，保证随路脉冲信号被下级电路采样到并且只保持一个时钟周期高电平，与数据同步传输给下级电路。但由于每次上电或者长时间时钟波动等造成跨时钟域两边时钟相位关系不确定，因此每个跨时钟域传输时都存在一个时钟周期的不确定性，到达DAC数字时钟域时随路脉冲信号(data_pluse)与产生其的空口脉冲信号(ref_pluse)的差异为Td1+Td2，其中，Td2为链路固定时延Td21加跨时钟域不确定时延Td22。
在本公开实施例中，第一精时延校准单元201和第二精时延校准单元202的结构基本相同。如图3和图5所示，第一精时延校准单元201和第二精时延校准单元202均包括随路脉冲处理子单元(posedge)、判断子单元(count)、空口脉冲同步子单元(sync1)、随路脉冲同步子单元(sync0)、精时延校准子单元(图中未绘示)和精时延校准中断子单元(ft_int_gen)。
随路脉冲处理子单元(posedge)被配置成，接收所在时延校准模块中粗时延校准单元发送的随路脉冲信号，根据随路脉冲信号的上升沿生成单周期随路脉冲信号，并将单周期随路脉冲信号发送给第一精时延校准中断子单元；其中，在第一精时延校准单元201中，随路脉冲信号为第一粗时延校准单元101发送的第一信号，在第二精时延校准单元202中，随路脉冲信号为第二粗时延校准单元102发送的第二信号。
空口脉冲同步子单元(sync1)被配置成，将空口脉冲信号同步到所在的时钟域，并将同步后的空口脉冲信号发送给判断子单元(count)。
随路脉冲同步子单元(sync0)被配置成，将随路脉冲信号同步到所在的时钟域，并将同步后的随路脉冲信号发送给判断子单元(count)。
判断子单元(count)被配置成，将同步后的空口脉冲信号和同步后的随路脉冲信号进行逻辑与运算。
精时延校准子单元用于，在判断子单元(count)计算得到的运算结果为0的情况下，进行精时延校准。需要说明的是，精时延校准子单元可以为通过软件实现的功能模块。
精时延校准中断子单元(ft_int_gen)被配置成，根据单周期随路脉冲信号 触发生成中断信号，中断信号用于停止精时延校准。
在一些实施例中，第一精时延校准单元201的精时延校准子单元被配置成，将发送链路中跨时钟域的先进先出存储器(FIFO)的读地址逐次加1以调整传输至第一粗时延校准单元101的发送随路脉冲信号(dac_data_pluse)的延迟。
在一些实施例中，第二精时延校准单元202的精时延校准子单元被配置成，调整再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟。
如图3和图5所示，第一时延校准模块100的第一精时延校准单元201包括相位校准子单元，第二时延校准模块200的第二精时延校准单元202包括相位校准子单元。相位校准子单元包括差分脉冲门控子单元(gate_pluse)和时钟分频子单元(clk_div)，差分脉冲门控子单元(gate_pluse)被配置成，根据门控信号调整模拟域的时钟信号的初始相位。时钟分频子单元(clk_div)被配置成，根据模拟域的时钟信号的初始相位调整数字域的时钟信号的初始相位。
当粗时延校准完成后，就进入精时延校准。精时延校准包括精时延补偿和相位校准。同步后的空口脉冲信号和同步后的随路脉冲信号在判断子单元(count)中进行逻辑与运算，当运算结果(adc_ft_counter)为0时，指示精时延校准子单元进行精时延补偿，直到运算结果不为0，表示已经消除两次异步采样空口脉冲加跨时钟域的不确定时延，此时时延差异为DAC数字时钟域一个时钟周期Tdac_dig与DAC模拟时钟域一个时钟周期Tdac_ana之和。
图7为根据本公开实施例的gate_pluse差分电路结构示意图，图8为根据本公开实施例的gate_pluse差分电路时序示意图。以第一精时延校准单元201为例，结合图5、图6、图7和图8所示，差分脉冲门控子单元(gate_pluse)可以在每次门控使能生效时，关闭一个时钟周期的时钟，配合时钟分频子单元(clk_div)可以使DAC的数字时钟clk_dac_dig每次调整一个DAC的模拟时钟clk_dac_ana的分频初始相位。这样当运算结果达到最大时，相位校准完成，如图6所示，经过精时延校准后，发送随路脉冲信号和下一个空口脉冲信号的时延精度为Td5，即两个DAC模拟时钟域时钟周期Tdac_ana。
需要说明的是，在第二时延校准模块200中，当第二粗时延校准单元102完成粗时延校准之后，第二精时延校准单元202进行精时延校准。该精时延校准过程与第一精时延校准单元201进行精时延校准的过程相同，但存在以下区别：
1、精时延补偿调整延迟的方式不同。第二精时延校准单元202中，调整再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟；第一精时延校准单元 201中，将发送链路中跨时钟域的FIFO读地址逐次加1以调整传输至第一粗时延校准单元的发送随路脉冲信号(dac_data_pluse)的延迟。
2、精时延校准中断的触发信号不同。第二精时延校准单元202中，精时延校准中断由空口脉冲信号(ref_pluse)的上升沿触发；第一精时延校准单元201中，精时延校准中断由随路脉冲信号(data_pluse)的上升沿触发。
如图4所示，经过精时延校准后，接收随路脉冲信号和下一个空口脉冲信号的时延精度为Rd2，即两个ADC模拟时钟域时钟周期Tadc_ana。
本公开实施例的时延校准装置，以空口脉冲信号为基准，利用随路脉冲信号和链路数据对齐后的同步传输性，通过在数字时钟域进行时延补偿和模拟ADDA高频时钟域进行相位校准，可以将时延校准精度提升为两个高频时钟周期。通过软件调整最初/最后一级数字时钟域的随路脉冲信号时延和数字时钟相位，取代了传统的双点同步采样后算法分析，不仅大大简化校准流程，避免了大量的算法计算，无论是在上电过程的初始化或者正常工作过程中，都可以快速进行链路的高精度授时。本公开实施例的时延校准装置，整体结构简单，可以适配多通道、多模式和多种工作场景。
本公开实施例可以应用于终端或者基站的射频收发系统，支持多链路、多时钟域和多工作模式下的高精度时延校准。支持TX和RX多链路扩展，可将多链路的随路脉冲信号合并在数字接口内的发送随路脉冲信号发生模块110和接收随路脉冲信号校准模块210内产生和校准。本公开实施例支持整机多系统对接，可将数字接口内的发送随路脉冲信号发生模块110和接收随路脉冲信号校准模块210转移到上游芯片系统链路源/尽头，这样可对整体链路时延进行高精度校准。
本公开实施例适用于时延要求较高、具有跨时钟域或者异步时钟域的收发系统，可以推广应用于具有相应需求的射频芯片、终端芯片以及基带芯片中。
本公开实施例还提供一种时延校准方法，所述方法应用于如前所述的时延校准装置，如图9所示，所述方法包括以下步骤：
步骤S11，接收空口脉冲信号，根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿。
在本步骤中，粗时延校准单元10根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿。
步骤S12，在模拟时钟域对随路脉冲信号进行时延补偿，并对时钟域相位进行校准。
在本步骤中，精时延校准单元20的精时延校准子单元21在模拟时钟域对随路脉冲信号进行时延补偿，精时延校准单元20的相位校准子单元对时钟域相位进行校准。
本公开实施例的时延校准方法，以空口脉冲信号为基准，通过在数字时钟域进行时延补偿和模拟高频时钟域进行相位校准，可以将时延校准精度提升为两个高频时钟周期；通过调整数字时钟域的随路脉冲信号时延和数字时钟相位，取代了传统的双点同步采样后算法分析，简化校准流程，降低算法计算量，实现链路快速高精度授时；时延校准装置整体结构简单，可以适配多通道、多模式和多种工作场景。
在一些实施例中，如图10所示，在发送链路中，所述根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿(即步骤S11)，包括以下步骤：
步骤S111，根据空口脉冲信号生成发送随路脉冲信号。
步骤S112，在发送链路的多时钟域内，利用数据有效使能信号，将发送随路脉冲信号和链路数据进行对齐传输。
步骤S113，根据所空口脉冲信号在数字时钟域对发送随路脉冲信号进行时延补偿。
在一些实施例中，如图11所示，在接收链路中，所述根据空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿(即步骤S11)，包括以下步骤：
步骤S111’，根据空口脉冲信号生成接收随路脉冲信号。
步骤S112’，在接收链路的多时钟域内，利用数据有效使能信号，将接收随路脉冲信号和链路数据进行对齐传输。
步骤S113’，根据空口脉冲信号在数字时钟域对经过对齐传输的接收随路脉冲信号进行时延补偿。
在一些实施例中，所述根据空口脉冲信号生成接收随路脉冲信号(即步骤S111’)，包括以下步骤：根据所述空口脉冲信号的上升沿生成单周期空口脉冲信号，对所述单周期空口脉冲信号按同比周期缩小预设倍数生成再生接收随路脉冲信号。
所述根据空口脉冲信号在数字时钟域对经过对齐传输的接收随路脉冲信号 进行时延补偿(即步骤S113’)，包括以下步骤：
消除再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第二信号；将第二信号和单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到运算结果为1时停止运算，并生成第二指示信号。
在一些实施例中，在得到第二信号之后、将第二信号和所述单周期空口脉冲信号进行逻辑与运算之前，所述方法还包括以下步骤：按照1个时钟周期扩展第二信号的高电平长度，以便将扩展后的信号和单周期空口脉冲信号进行逻辑与运算。
在一些实施例中，根据空口脉冲信号在数字时钟域对发送随路脉冲信号进行时延补偿(即步骤S113)，包括以下步骤：
根据空口脉冲信号的上升沿生成单周期空口脉冲信号；消除传输至第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第一信号；将第一信号和单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到运算结果为1时停止运算，并生成第一指示信号。
在一些实施例中，在消除传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟之前，所述方法还包括以下步骤：计算所述单周期空口脉冲信号和所述传输至所述第一粗时延校准单元的发送随路脉冲信号的时间差，以便根据所述时间差配置所述传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
在一些实施例中，在消除传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟之前，所述方法还包括以下步骤：将空口脉冲信号按同比周期缩小预设倍数生成再生空口脉冲信号；对传输至所述第一粗时延校准单元的发送随路脉冲信号按同比周期缩小预设倍数生成再生发送随路脉冲信号，以便消除再生发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
在一些实施例中，在将第一信号和单周期空口脉冲信号进行逻辑与运算之前，所述方法还包括以下步骤：按照1个时钟周期扩展所述第一信号的高电平长度，以便将扩展后的信号和和所述单周期空口脉冲信号进行逻辑与运算。
在一些实施例中，在进行粗时延校准之后，所述方法还包括以下步骤：
接收随路脉冲信号，根据随路脉冲信号的上升沿生成单周期随路脉冲信号；随路脉冲信号为第一信号或第二信号；
将空口脉冲信号同步到所在的时钟域，并将随路脉冲信号同步到所在的时钟域；
将同步后的空口脉冲信号和同步后的随路脉冲信号进行逻辑与运算，在运算结果为0的情况下，进行精时延校准，其中，根据单周期随路脉冲信号触发生成中断信号，中断信号用于停止精时延校准。
在一些实施例中，所述进行精时延校准，包括以下步骤：
将发送链路中跨时钟域的先进先出存储器的读地址逐次加1以调整传输至所述第一粗时延校准单元的发送随路脉冲信号的延迟；或者，
调整再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟。
在一些实施例中，所述对时钟域相位进行校准，包括以下步骤：
根据门控信号调整模拟域的时钟信号的初始相位；
根据模拟域的时钟信号的初始相位调整数字域的时钟信号的初始相位。
为清楚说明本公开实施例的方案，以下通过一具体实例对本公开实施例的时延校准过程进行详细说明。时延校准过程的具体步骤如下：
1、根据实际芯片需要，上电后启动TX、RX时延校准。
2、根据产品应用的工作场景，通过软件进行初始化配置TX、RX的随路脉冲生成和校准相关的脉冲周期、链路配置、校准初始值、寄存器等参数。
3、外部循环发送空口脉冲信号，利用TX随路脉冲发生器直接产生TX链路的随路脉冲信号，利用ADC校准单元，通过粗时延校准和精时延校准产生RX链路的随路脉冲信号。
ADC的粗时延校准流程为：空口脉冲信号的上升沿触发软件的ADC粗时延校准中断，每次软件增加1拍延迟，直至随路脉冲信号和空口脉冲信号相与的结果为1，表示粗时延校准完成。
ADC的精时延校准流程为：空口脉冲信号的上升沿触发软件的ADC精调中断，如果随路脉冲信号和空口脉冲信号相与的计数值为0，则继续增加1拍延迟，进行精时延补偿。若计数值不为0，则软件进行一次关闭、打开时钟门控的过程，进行相位调整，直到计数值等于既定的阈值时，表示精时延校准完成。
4、TX和RX随路脉冲信号在链路中传输，分别到达DAC校准单元和RX随路脉冲信号校准器。
5、在DAC校准单元内依次进行粗时延和精时延校准，在RX随路脉冲校准器内进行粗时延校准。
DAC的粗时延校准流程为：随路脉冲信号的上升沿触发软件的DAC粗时延校准中断，读取比较模块的counter值后，设置一个相近的delay值，然后每次软件增加1拍延迟，直至随路脉冲信号和空口脉冲信号相与的结果为1，表示粗时延校准完成。
DAC的精时延校准流程为：随路脉冲信号的上升沿触发软件的DAC精时延校准中断，当随路脉冲信号和空口脉冲信号相与的计数值为0，则DAC跨时钟域FIFO的读地址进行逐次加1调整随路脉冲延迟，进行精时延补偿。当计数值不为0，则软件进行一次关闭、打开时钟门控的过程，进行相位调整，直到计数值等于既定的阈值时，表示精时延校准完成。RX随路脉冲校准器内的粗时延校准同DAC的粗时延校准流程。
6、退出时延校准流程，等待下一次正常工作过程中的TX和RX链路时延检测校准，再重复步骤2-5。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其他实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本发明的范围的情况下，可进行各种形式和细节上的改变。

Claims (25)

  1. 一种时延校准装置，包括时延校准模块，所述时延校准模块包括粗时延校准单元和精时延校准单元，
    所述粗时延校准单元被配置成，接收空口脉冲信号，根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿；
    所述精时延校准单元包括精时延校准子单元和相位校准子单元；
    所述精时延校准子单元被配置成，在所述粗时延校准单元根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿之后，在模拟时钟域对所述随路脉冲信号进行时延补偿；
    所述相位校准子单元被配置成，在所述精时延校准子单元在模拟时钟域对所述随路脉冲信号进行时延补偿之后，对时钟域相位进行校准。
  2. 如权利要求1所述的时延校准装置，其中，所述时延校准装置还包括发送链路，所述时延校准模块包括第一时延校准模块，所述第一时延校准模块位于所述发送链路；
    所述粗时延校准单元为第一粗时延校准单元，所述精时延校准单元为第一精时延校准单元，所述随路脉冲信号为发送随路脉冲信号；
    所述发送链路还包括发送随路脉冲发生模块和发送链路随路脉冲传输模块；
    所述发送随路脉冲发生模块被配置成，接收空口脉冲信号，根据所述空口脉冲信号生成所述发送随路脉冲信号；
    所述发送链路随路脉冲传输模块被配置成，在所述发送链路的多时钟域内，利用数据有效使能信号，将所述发送随路脉冲信号和链路数据进行对齐传输，并发送给所述第一时延校准模块的所述第一粗时延校准单元。
  3. 如权利要求1或2所述的时延校准装置，其中，所述时延校准装置还包还包括接收链路，所述时延校准模块包括第二时延校准模块，所述第二时延校准模块位于所述接收链路；
    所述随路脉冲信号为接收随路脉冲信号，所述精时延校准单元为第二精时延校准单元，所述粗时延校准单元为第二粗时延校准单元，所述第二粗时延校准单元还被配置成在接收空口脉冲信号之后，根据所述空口脉冲信号生成所述接收随路脉冲信号；
    所述接收链路还包括接收随路脉冲校准模块和接收链路随路脉冲传输模块；
    所述接收链路随路脉冲传输模块被配置成，在所述接收链路的多时钟域内，利用数据有效使能信号，将所述接收随路脉冲信号和链路数据进行对齐传输，并发送给所述接收随路脉冲校准模块；
    所述接收随路脉冲校准模块被配置成，根据所述空口脉冲信号在数字时钟域对接收到的随路脉冲信号进行时延补偿。
  4. 如权利要求3所述的时延校准装置，其中，所述第二粗时延校准单元包括第二空口脉冲处理子单元、第二随路脉冲信号再生子单元、第二延迟子单元和第二粗时延校准子单元；
    所述第二空口脉冲处理子单元被配置成，根据所述空口脉冲信号的上升沿生成单周期空口脉冲信号；
    所述第二随路脉冲信号再生子单元分别与所述第二空口脉冲处理子单元和所述第二延迟子单元相连，被配置成对所述第二空口脉冲处理子单元发送的所述单周期空口脉冲信号按同比周期缩小预设倍数生成再生接收随路脉冲信号，并将所述再生接收随路脉冲信号发送给所述第二延迟子单元；
    所述第二延迟子单元被配置成，消除所述再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第二信号；
    所述第二粗时延校准子单元被配置成，将所述第二信号和所述单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到所述运算结果为1时停止运算，并生成第二指示信号。
  5. 如权利要求4所述的时延校准装置，其中，所述第二粗时延校准单元还包括第二扩展子单元，
    所述第二扩展子单元与所述第二延迟子单元和所述第二粗时延校准子单元连接，被配置成按照1个时钟周期扩展所述第二信号的高电平长度，并将扩展后的信号发送给所述第二粗时延校准子单元，以供所述第二粗时延校准子单元将所述扩展后的信号和所述单周期空口脉冲信号进行逻辑与运算。
  6. 如权利要求4所述的时延校准装置，其中，所述第一粗时延校准单元包括第一空口脉冲处理子单元、第一延迟子单元和第一粗时延校准子单元；
    所述第一空口脉冲处理子单元被配置成，根据所述空口脉冲信号的上升沿生成单周期空口脉冲信号；
    所述第一延迟子单元被配置成，消除传输至所述第一粗时延校准单元的发送 随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第一信号；
    所述第一粗时延校准子单元被配置成，将所述第一信号和所述单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到所述运算结果为1时停止运算，并生成第一指示信号。
  7. 如权利要求6所述的时延校准装置，其中，所述第一粗时延校准单元还包括比较子单元，
    所述比较子单元被配置成，计算所述单周期空口脉冲信号和所述传输至所述第一粗时延校准单元的发送随路脉冲信号的时间差，以便根据所述时间差配置所述传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
  8. 如权利要求6所述的时延校准装置，其中，所述第一粗时延校准单元还包括第一空口脉冲信号再生子单元和第一随路脉冲信号再生子单元；
    所述第一空口脉冲信号再生子单元与所述第一空口脉冲处理子单元和所述第一粗时延校准子单元连接，被配置成将所述空口脉冲信号按同比周期缩小预设倍数生成再生空口脉冲信号，并将所述再生空口脉冲信号发送给所述第一粗时延校准子单元；
    所述第一随路脉冲信号再生子单元与所述第一延迟子单元连接，被配置成对所述传输至所述第一粗时延校准单元的发送随路脉冲信号按同比周期缩小预设倍数生成再生发送随路脉冲信号，并将所述再生发送随路脉冲信号发送给所述第一延迟子单元，以供所述第一延迟子单元消除所述再生发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
  9. 如权利要求6所述的时延校准装置，其中，所述第一粗时延校准单元还包括第一扩展子单元，
    所述第一扩展子单元与所述第一延迟子单元和所述第一粗时延校准子单元连接，被配置成按照1个时钟周期扩展所述第一信号的高电平长度，并将扩展后的信号发送给所述第一粗时延校准子单元，以供所述第一粗时延校准子单元将所述扩展后的信号和和所述单周期空口脉冲信号进行逻辑与运算。
  10. 如权利要求6所述的时延校准装置，其中，所述第一精时延校准单元和所述第二精时延校准单元均包括随路脉冲处理子单元、判断子单元、空口脉冲同 步子单元、随路脉冲同步子单元、精时延校准子单元和精时延校准中断子单元；
    所述随路脉冲处理子单元被配置成，接收所在时延校准模块中粗时延校准单元发送的随路脉冲信号，根据所述随路脉冲信号的上升沿生成单周期随路脉冲信号，并将所述单周期随路脉冲信号发送给所述第一精时延校准中断子单元，其中，在所述第一精时延校准单元中，所述随路脉冲信号为所述第一信号，在所述第二精时延校准单元中，所述随路脉冲信号为所述第二信号；
    所述空口脉冲同步子单元被配置成，将所述空口脉冲信号同步到所在的时钟域，并将同步后的空口脉冲信号发送给所述判断子单元；
    所述随路脉冲同步子单元被配置成，将所述随路脉冲信号同步到所在的时钟域，并将同步后的随路脉冲信号发送给所述判断子单元；
    所述判断子单元被配置成，将所述同步后的空口脉冲信号和所述同步后的随路脉冲信号进行逻辑与运算；
    所述精时延校准子单元被配置成，在所述判断子单元计算得到的运算结果为0的情况下，进行精时延校准；
    所述精时延校准中断子单元被配置成，根据所述单周期随路脉冲信号触发生成中断信号，所述中断信号用于停止精时延校准。
  11. 如权利要求10所述的时延校准装置，其中，所述第一精时延校准单元的所述精时延校准子单元被配置成，将发送链路中跨时钟域的先进先出存储器的读地址逐次加1以调整所述传输至所述第一粗时延校准单元的发送随路脉冲信号的延迟。
  12. 如权利要求10所述的时延校准装置，其中，所述第二精时延校准单元的所述精时延校准子单元被配置成，调整所述再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟。
  13. 如权利要求1-12任一项所述的时延校准装置，其中，所述相位校准子单元包括差分脉冲门控子单元和时钟分频子单元；
    所述差分脉冲门控子单元被配置成，根据门控信号调整模拟域的时钟信号的初始相位；
    所述时钟分频子单元被配置成，根据所述模拟域的时钟信号的初始相位调整数字域的时钟信号的初始相位。
  14. 一种时延校准方法，应用于如权利要求1-13任一项所述的时延校准装置，所述方法包括：
    接收空口脉冲信号，根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿；
    在模拟时钟域对所述随路脉冲信号进行时延补偿，并对时钟域相位进行校准。
  15. 如权利要求14所述的方法，其中，在发送链路中，所述根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿，包括：
    根据所述空口脉冲信号生成所述发送随路脉冲信号；
    在所述发送链路的多时钟域内，利用数据有效使能信号，将所述发送随路脉冲信号和链路数据进行对齐传输；
    根据所述空口脉冲信号在数字时钟域对所述发送随路脉冲信号进行时延补偿。
  16. 如权利要求14或15所述的方法，其在，在接收链路中，所述根据所述空口脉冲信号在数字时钟域对随路脉冲信号进行时延补偿，包括：
    根据所述空口脉冲信号生成接收随路脉冲信号；
    在所述接收链路的多时钟域内，利用数据有效使能信号，将所述接收随路脉冲信号和链路数据进行对齐传输；
    根据所述空口脉冲信号在数字时钟域对经过对齐传输的接收随路脉冲信号进行时延补偿。
  17. 如权利要求16所述的方法，应用于如权利要求4-13任一项所述的时延校准装置，所述根据所述空口脉冲信号生成接收随路脉冲信号，包括：
    根据所述空口脉冲信号的上升沿生成单周期空口脉冲信号，对所述单周期空口脉冲信号按同比周期缩小预设倍数生成再生接收随路脉冲信号；
    所述根据所述空口脉冲信号在数字时钟域对经过对齐传输的接收随路脉冲信号进行时延补偿，包括：
    消除所述再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第二信号；
    将所述第二信号和所述单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到所述运算结果为1时停止运算，并生成第二指示信号。
  18. 如权利要求17所述的方法，应用于如权利要求5-13任一项所述的时延校准装置，在得到第二信号之后、将所述第二信号和所述单周期空口脉冲信号进行逻辑与运算之前，所述方法还包括：
    按照1个时钟周期扩展所述第二信号的高电平长度，以便将扩展后的信号和所述单周期空口脉冲信号进行逻辑与运算。
  19. 如权利要求17所述的方法，应用于如权利要求6-13任一项所述的时延校准装置，所述根据所述空口脉冲信号在数字时钟域对所述发送随路脉冲信号进行时延补偿，包括：
    根据所述空口脉冲信号的上升沿生成单周期空口脉冲信号；
    消除传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟，得到第一信号；
    将所述第一信号和所述单周期空口脉冲信号进行逻辑与运算，在运算结果非1的情况下，进行粗时延校准，直到所述运算结果为1时停止运算，并生成第一指示信号。
  20. 如权利要求19所述的方法，应用于如权利要求7-13任一项所述的时延校准装置，在消除传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟之前，所述方法还包括：
    计算所述单周期空口脉冲信号和所述传输至所述第一粗时延校准单元的发送随路脉冲信号的时间差，以便根据所述时间差配置所述传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
  21. 如权利要求19所述的方法，应用于如权利要求8-13任一项所述的时延校准装置，在消除传输至所述第一粗时延校准单元的发送随路脉冲信号和下一个空口脉冲信号之间的延迟之前，所述方法还包括：
    将所述空口脉冲信号按同比周期缩小预设倍数生成再生空口脉冲信号；
    对所述传输至所述第一粗时延校准单元的发送随路脉冲信号按同比周期缩小预设倍数生成再生发送随路脉冲信号，以便消除所述再生发送随路脉冲信号和下一个空口脉冲信号之间的延迟。
  22. 如权利要求19所述的方法，应用于如权利要求9-13任一项所述的时延 校准装置，在将所述第一信号和所述单周期空口脉冲信号进行逻辑与运算之前，所述方法还包括：
    按照1个时钟周期扩展所述第一信号的高电平长度，以便将扩展后的信号和和所述单周期空口脉冲信号进行逻辑与运算。
  23. 如权利要求19所述的方法，应用于如权利要求10-13任一项所述的时延校准装置，在进行粗时延校准之后，所述方法还包括：
    接收随路脉冲信号，根据所述随路脉冲信号的上升沿生成单周期随路脉冲信号；所述随路脉冲信号为所述第一信号或所述第二信号；
    将所述空口脉冲信号同步到所在的时钟域，并将所述随路脉冲信号同步到所在的时钟域；
    将所述同步后的空口脉冲信号和所述同步后的随路脉冲信号进行逻辑与运算，在所述运算结果为0的情况下，进行精时延校准，其中，根据所述单周期随路脉冲信号触发生成中断信号，所述中断信号用于停止精时延校准。
  24. 如权利要求23所述的方法，其中，所述进行精时延校准，包括：
    将发送链路中跨时钟域的先进先出存储器的读地址逐次加1以调整所述传输至所述第一粗时延校准单元的发送随路脉冲信号的延迟；或者，
    调整所述再生接收随路脉冲信号和下一个空口脉冲信号之间的延迟。
  25. 如权利要求14-24任一项所述的方法，其中，所述对时钟域相位进行校准，包括：
    根据门控信号调整模拟域的时钟信号的初始相位；
    根据所述模拟域的时钟信号的初始相位调整数字域的时钟信号的初始相位。
PCT/CN2023/113693 2022-08-31 2023-08-18 时延校准装置及时延校准方法 WO2024046141A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211058378.8A CN117675065A (zh) 2022-08-31 2022-08-31 时延校准装置及时延校准方法
CN202211058378.8 2022-08-31

Publications (1)

Publication Number Publication Date
WO2024046141A1 true WO2024046141A1 (zh) 2024-03-07

Family

ID=90066858

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/113693 WO2024046141A1 (zh) 2022-08-31 2023-08-18 时延校准装置及时延校准方法

Country Status (2)

Country Link
CN (1) CN117675065A (zh)
WO (1) WO2024046141A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060178850A1 (en) * 2005-02-07 2006-08-10 Lecroy Corporation Sequential timebase
CN101015022A (zh) * 2004-02-27 2007-08-08 夏普株式会社 延迟闩锁环电路
CN102457285A (zh) * 2010-10-27 2012-05-16 国际商业机器公司 用于多个并行数据通信线路的校准的通信接口和方法
CN109257033A (zh) * 2018-08-27 2019-01-22 中国科学院电子学研究所 高精度步进延迟系统
CN110365317A (zh) * 2019-07-24 2019-10-22 电子科技大学 具有自适应延迟补偿的高精度混合型数字脉宽调制器
CN113364434A (zh) * 2021-06-23 2021-09-07 中国科学院微电子研究所 一种占空比校准电路及方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101015022A (zh) * 2004-02-27 2007-08-08 夏普株式会社 延迟闩锁环电路
US20060178850A1 (en) * 2005-02-07 2006-08-10 Lecroy Corporation Sequential timebase
CN102457285A (zh) * 2010-10-27 2012-05-16 国际商业机器公司 用于多个并行数据通信线路的校准的通信接口和方法
CN109257033A (zh) * 2018-08-27 2019-01-22 中国科学院电子学研究所 高精度步进延迟系统
CN110365317A (zh) * 2019-07-24 2019-10-22 电子科技大学 具有自适应延迟补偿的高精度混合型数字脉宽调制器
CN113364434A (zh) * 2021-06-23 2021-09-07 中国科学院微电子研究所 一种占空比校准电路及方法

Also Published As

Publication number Publication date
CN117675065A (zh) 2024-03-08

Similar Documents

Publication Publication Date Title
US6031847A (en) Method and system for deskewing parallel bus channels
US8824224B2 (en) Frequency-agile strobe window generation
EP1159687B1 (en) Dynamic wave-pipelined interface apparatus and methods therefor
US6334163B1 (en) Elastic interface apparatus and method therefor
US7940667B1 (en) Delay measurements and calibration methods and apparatus for distributed wireless systems
US8073090B2 (en) Synchronous de-skew with programmable latency for multi-lane high speed serial interface
JPH08507668A (ja) 直列データ・バス用スキュー除去装置
TW201635153A (zh) 使用經校準、單一時脈來源同步串列器－解串列器協定之高速資料傳輸
EP1813039A2 (en) Method and apparatus for aligning data in a wide, high-speed, source synchronous parallel link
JP3966511B2 (ja) 同期バス・インターフェースのための自動遅延検出およびレシーバ調節の方法およびシステム
US6949955B2 (en) Synchronizing signals between clock domains
WO2004109524A2 (en) Synchronous data transfer across clock domains
KR20110115572A (ko) 메모리 요청과 데이터 전송 간 타이밍 교정을 포함하는 프로토콜
WO2024046141A1 (zh) 时延校准装置及时延校准方法
US7793021B2 (en) Method for synchronizing a transmission of information and a device having synchronizing capabilities
WO2008130825A1 (en) Dynamic phase alignment
WO2012009160A1 (en) Methods and apparatus for determining a phase error in signals
CN113491082B (zh) 一种数据处理装置
US6542999B1 (en) System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock
US6571346B1 (en) Elastic interface for master-slave communication
WO2024139457A1 (zh) 时延电路同步方法及装置
Deev et al. Subnanosecond synchronization method based on the synchronous Ethernet network
Xie et al. Application of Synchronous Acquisition Technology Based on JESD204B Protocol in Phased Array Radar
Sarmah et al. A circuit to eliminate serial skew in high-speed serial communication channels
WO2023087588A1 (zh) 采样电路、采样电路的使用方法、存储介质、电子装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23859175

Country of ref document: EP

Kind code of ref document: A1