WO2024046065A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2024046065A1
WO2024046065A1 PCT/CN2023/111904 CN2023111904W WO2024046065A1 WO 2024046065 A1 WO2024046065 A1 WO 2024046065A1 CN 2023111904 W CN2023111904 W CN 2023111904W WO 2024046065 A1 WO2024046065 A1 WO 2024046065A1
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WIPO (PCT)
Prior art keywords
layer
barrier layer
flexible substrate
semiconductor layer
display substrate
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PCT/CN2023/111904
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English (en)
French (fr)
Inventor
王格
胡明
蒋志亮
陈鸿
郭永林
潘向南
袁晓敏
于池
燕青青
何庆
陈敏
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024046065A1 publication Critical patent/WO2024046065A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the present disclosure relates to the technical field of display product manufacturing, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • Flexible OLED displays have gradually become the mainstream of mobile phone displays due to their excellent performance.
  • Flexible OLED usually makes a flexible PI (polyimide) substrate on glass, and then makes a TFT drive circuit on the flexible PI substrate; then evaporates the EL luminescent material on the TFT drive circuit; after the evaporation is completed, TFE (thin film encapsulation) is used ) encapsulates the luminescent material.
  • OLED displays using flexible PI substrates have much worse afterimage performance than OLED displays using rigid glass substrates.
  • the main reason is that impurities in the PI substrate affect the TFT drive circuit above it, causing the TFT characteristics to shift and cause afterimages.
  • the impurities that affect the residual image in the PI substrate are mainly fluoride ions.
  • the PI raw material can remove fluoride ions and reduce the impact of the raw material; however, there are many processes in the flexible OLED process that will introduce fluoride ions into the PI substrate, causing fluorine ions in the PI substrate. Ion pollution, the most important process is the semiconductor ion implantation process. BF3 is mostly used when injecting boron ions into the semiconductor layer. Where there is no semiconductor layer or metal layer blocking, high-energy ions can penetrate the film layer and enter the PI substrate, so Fluoride ions are small and have strong binding force and are easily attached to the PI substrate and cannot be discharged.
  • the present disclosure provides a display substrate, a manufacturing method thereof, and a display device to solve the problem of display afterimage caused by contamination of the PI substrate by fluorine ions.
  • the technical solution adopted in the embodiment of the present disclosure is: a display substrate, including a flexible substrate, and a TFT drive circuit located on the flexible substrate, the TFT drive circuit including a pattern located on the flexible substrate ionized semiconductor layer, the display substrate further includes a barrier layer, the barrier layer is configured to prevent fluorine ions from entering the flexible substrate, the barrier layer is provided in the same layer as the semiconductor layer, or the barrier layer is located on the same layer as the semiconductor layer. between the semiconductor layer and the flexible substrate.
  • the barrier layer is made of polysilicon material.
  • the barrier layer and the semiconductor layer are arranged on the same layer, the barrier layer includes a hollow portion and a shielding portion, and the orthographic projection of the semiconductor layer on the flexible substrate is located on the side of the hollow portion on the flexible substrate. within the orthographic projection on the base.
  • the TFT driving circuit further includes a gate metal layer located on a side away from the semiconductor layer or on a side of the substrate, and the orthographic projection of the semiconductor layer on the flexible substrate is a first projection, and the The orthographic projection of the gate metal layer on the flexible substrate is a second projection, and the first projection and the second projection partially overlap to form a third projection;
  • the barrier layer is arranged on the same layer as the semiconductor layer, the barrier layer includes a hollow portion and a shielding portion, and the third projection is located within the orthographic projection of the hollow portion on the flexible substrate.
  • the orthographic projection of the TFT drive circuit on the flexible substrate is a fourth projection
  • the barrier layer is provided on the same layer as the semiconductor layer
  • the barrier layer includes a hollow part and a shielding part
  • the third The four projections are located within the orthographic projection of the hollow portion on the flexible substrate.
  • the barrier layer is located between the semiconductor layer and the flexible substrate, and the barrier layer is made of polysilicon or metal.
  • a buffer layer is provided between the semiconductor layer and the flexible substrate, and the barrier layer is located between the buffer layer and the flexible substrate.
  • an isolation layer and a buffer layer are sequentially provided on the flexible substrate, the semiconductor layer is formed on a side of the buffer layer away from the isolation layer, and the barrier A layer is provided between the buffer layer and the isolation layer, or the barrier layer is provided between the flexible substrate and the isolation layer.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate.
  • the polysilicon layer is subjected to a patterning process to obtain a patterned semiconductor layer and barrier layer.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, including:
  • the polysilicon layer is subjected to a patterning process to obtain a patterned semiconductor layer, or the polysilicon layer is subjected to a patterning process to simultaneously obtain a patterned semiconductor layer and a barrier layer.
  • the step further includes:
  • An isolation layer is formed on the barrier layer.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, including:
  • the polysilicon layer is subjected to a patterning process to obtain a patterned semiconductor layer, or the polysilicon layer is subjected to a patterning process to simultaneously obtain a patterned semiconductor layer and a barrier layer.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the beneficial effect of the present disclosure is to prevent fluorine ions from infiltrating into the flexible substrate through the provision of the barrier layer, thereby improving OLED residual image defects.
  • Figure 1 shows a schematic diagram of a state in which a semiconductor layer is lightly doped in the related art
  • Figure 2 shows a schematic diagram of a state in which a semiconductor layer is heavily doped in the related art
  • Figure 3 is a schematic diagram showing a state in which afterimages occur in the related art
  • Figure 4 shows a schematic structural diagram of the semiconductor layer
  • Figure 5 shows a schematic structural diagram of the semiconductor layer and the gate metal layer
  • Figure 6 shows a schematic structural diagram of the barrier layer in an embodiment of the present disclosure
  • Figure 7 shows a schematic diagram 2 of the structure of the barrier layer in an embodiment of the present disclosure
  • Figure 8 shows a schematic diagram of a state of light doping in an embodiment of the present disclosure
  • Figure 9 shows a schematic diagram of a heavily doped state in an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram showing a state in which afterimage does not occur in an embodiment of the present disclosure.
  • Figure 11 shows a schematic diagram three of the structure of the barrier layer in the embodiment of the present disclosure.
  • Figure 12 shows a schematic diagram 4 of the structure of the barrier layer in an embodiment of the present disclosure.
  • the semiconductor ion implantation process includes light doping and heavy doping.
  • BF 3 is mostly used when implanting boron ions, where there is no polysilicon or metal layer (refer to gate metal layer 3 in Figure 2) to block.
  • high-energy ions can penetrate the membrane layer and enter the PI substrate. Because fluoride ions are small and have strong binding force, they are easily attached to the PI substrate 1 and cannot be discharged.
  • the TFT drive circuit above the PI substrate 1 starts to work, as the electrical signal changes, the fluorine ions in the PI substrate 1 move directionally to form an induced electric field. This induced electric field interferes with the upper TFT channel signal, causing the signal response to slow down.
  • Causes display afterimage refer to Figure 3.
  • this embodiment provides a display substrate, including a flexible substrate 1 and a TFT drive circuit located on the flexible substrate 1.
  • the TFT drive circuit includes a display substrate located on the flexible substrate 1. on the patterned semiconductor layer 2, the display substrate further includes a barrier layer 5.
  • the barrier layer 5 is configured to block fluorine ions from entering the flexible substrate 1.
  • the barrier layer 5 is provided in the same layer as the semiconductor layer 2, or the barrier layer 5 is located between the semiconductor layer 2 and the semiconductor layer 2. between flexible substrates 1.
  • the arrangement of the barrier layer 5 prevents fluorine ions from infiltrating into the flexible substrate 1 and improves OLED residual image defects.
  • the flexible substrate 1 is made of polyimide, but is not limited thereto.
  • the barrier layer 5 is made of polysilicon material, but it is not limited to this.
  • the barrier layer 5 is provided in the same layer as the semiconductor layer 2.
  • the barrier layer 5 includes a hollow portion and a shielding portion.
  • the shape of the hollow portion is consistent with the shape of the semiconductor layer 2. So that the semiconductor layer 2 is located within the hollow part (that is, the orthographic projection of the semiconductor layer 2 on the flexible substrate is located within the orthographic projection of the hollow part on the flexible substrate).
  • the barrier layer 5 can be made of polysilicon.
  • the barrier layer 5 and the semiconductor layer 2 can use a synchronous illumination process (i.e., patterning process, including exposure, development). etc.) to form and reduce the process, but it is not limited to this.
  • the shape of the semiconductor layer 2 is as shown in FIG. 4 .
  • the shape of the hollow portion is consistent with the shape of the semiconductor layer 2 .
  • the shape surrounding the semiconductor layer 2 is All around, it plays a blocking role, which can reduce or prevent fluoride ions from entering the flexible substrate 1, see Figure 6.
  • the barrier layer 5 there is a gap between the barrier layer 5 and the semiconductor layer 2 so as not to affect the performance of the TFT.
  • the gap between the barrier layer 5 and the semiconductor layer 2 is greater than or equal to 1 ⁇ m, but is not limited to this.
  • the barrier layer 5 and the semiconductor layer 2 are arranged in the same layer. In a direction parallel to the flexible substrate 1 , the barrier layer 5 is surrounded by the barrier layer 5 and is located at the same layer. around the gate metal layer 3 on the semiconductor layer 2.
  • the barrier layer 5 in this embodiment is arranged around the barrier layer 5 and the gate metal layer 3 located on the semiconductor layer 2 to avoid blocking the gate metal layer. 3. Prevent affecting the performance of the TFT drive circuit.
  • the TFT driving circuit also includes a semiconductor layer located on the side of the semiconductor layer 2 away from or on the side of the substrate 1
  • the gate metal layer 3, the orthographic projection of the semiconductor layer 2 on the flexible substrate 1 is the first projection, and the orthographic projection of the gate metal layer 3 on the flexible substrate 1 is the second projection, so The first projection and the second projection partially overlap to form a third projection;
  • the barrier layer 5 is arranged in the same layer as the semiconductor layer 2.
  • the barrier layer 5 includes a hollow portion and a shielding portion.
  • the shape of the orthographic projection of the hollow portion on the flexible substrate 1 is consistent with the shape of the third projection. The shapes match, so that the semiconductor layer 2 and the gate metal layer 3 are located within the hollow portion (that is, the third projection is located within the orthogonal projection of the hollow portion on the flexible substrate).
  • the orthographic projection of the TFT drive circuit on the flexible substrate 1 is the fourth projection
  • the barrier layer 5 is provided in the same layer as the semiconductor layer 2
  • the barrier layer 5 includes a hollow portion. and a shielding portion.
  • the shape of the orthographic projection of the hollow portion on the flexible substrate 1 matches the shape of the fourth projection, so that the entire TFT drive circuit is located within the hollow portion (i.e., the fourth projection Located within the orthographic projection of the hollow portion on the flexible base).
  • the TFT drive circuit includes the semiconductor layer 2, gate metal layer 3, source and drain metal layers, etc.
  • the barrier layer 5 is provided in the area where the TFT drive circuit is not provided, effectively preventing Fluorine ions enter the flexible substrate 1 to avoid affecting the performance of the TFT drive circuit.
  • Figure 8 shows a schematic diagram of a lightly doped state in an embodiment of the present disclosure
  • Figure 9 shows a schematic diagram of a heavily doped state in an embodiment of the present disclosure.
  • the barrier layer 5 is made of polysilicon and is arranged in the same layer as the semiconductor layer 2 made of polysilicon, which has the following advantages: 1. In the polysilicon coverage area, fluorine ions cannot penetrate the polysilicon during the ion implantation process. Entering the flexible substrate 1 below can prevent the flexible substrate 1 from being contaminated by fluorine ions and avoid the deterioration of afterimages caused by fluorine ions; 2. Use low-temperature polysilicon to block non-circuit areas, which does not affect the performance of the TFT and saves a block of light; 3. Polysilicon It is light-transmissive, and using polysilicon to block non-circuit areas has little impact on the transmittance of the display.
  • the TFT driving circuit in this embodiment may only include driving transistors and switching transistors, or may be the entire TFT driving circuit (including not only driving transistors and switching transistors, but also signal lines, etc.).
  • the barrier layer 5 is located between the semiconductor layer 2 and the flexible substrate 1 , and the barrier layer 5 is made of polysilicon or metal.
  • the barrier layer 5 is located between the semiconductor layer 2 and the flexible substrate 1 , that is, the barrier layer 5 and the semiconductor are arranged in different layers.
  • the material of the barrier layer 5 is selected relative to the barrier layer. 5.
  • the range of options for setting the same layer as the semiconductor layer 2 is wider. For example, polysilicon or metal can be selected, but it is not limited to this, as long as fluorine ions can be blocked from entering the flexible substrate 1.
  • the orthographic projection of the barrier layer 5 on the flexible substrate 1 can completely cover the flexible substrate 1 .
  • a buffer layer 6 is provided between the semiconductor layer 2 and the flexible substrate 1 , and the barrier layer 5 is located between the buffer layer 6 and the flexible substrate 1 .
  • an isolation layer 7 and a buffer layer 6 are sequentially provided on the flexible substrate 1 in a direction away from the flexible substrate 1, and the semiconductor layer 2 is formed on the buffer layer 6 on the side away from the isolation layer 7, the barrier layer 5 is disposed between the buffer layer 6 and the isolation layer 7, or the barrier layer 5 is disposed between the flexible substrate 1 and the isolation layer between 7.
  • the isolation layer 7 can reduce or prevent the infiltration of impurities, moisture or external air from below the flexible substrate 1 .
  • the flexible substrate 1 is formed on a glass substrate 10 .
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, including:
  • the polysilicon layer is subjected to a patterning process to obtain a patterned semiconductor layer and barrier layer.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, including:
  • the step further includes:
  • An isolation layer is formed on the barrier layer.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, including:
  • the polysilicon layer is subjected to a patterning process to obtain a patterned semiconductor layer, or the polysilicon layer is subjected to a patterning process to simultaneously obtain a patterned semiconductor layer and a barrier layer.
  • An embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.

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Abstract

本公开涉及一种显示基板及其制作方法、显示装置，显示基板包括柔性基底，以及位于所述柔性基底上的TFT驱动电路，所述TFT驱动电路包括位于所述柔性基底上的图案化的半导体层，所述显示基板还包括阻挡层，所述阻挡层被配置为阻挡氟离子进入所述柔性基底，所述阻挡层与所述半导体层同层设置，和/或所述阻挡层位于所述半导体层和所述柔性基底之间。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2022年8月31日在中国提交的中国专利申请号No.202211065002.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示产品制作技术领域，尤其涉及一种显示基板及其制作方法、显示装置。
背景技术
柔性OLED显示器因其优异的性能逐渐成为手机显示屏的主流。柔性OLED通常在玻璃上制作柔性PI(聚酰亚胺)基底，然后在柔性PI基底上制作TFT驱动电路；接着在TFT驱动电路上蒸镀EL发光材料；蒸镀完成后再使用TFE(薄膜封装)将发光材料封装起来。
采用柔性PI基底的OLED显示器相较于采用刚性玻璃基底的OLED显示器残像表现要差很多，主要原因为PI基底中杂质对于其上方的TFT驱动电路存在影响，导致TFT特性偏移，造成残像。
PI基底中影响残像的杂质主要为氟离子，PI原材料可以去除氟离子，减少原材的影响；但在柔性OLED工艺过程中有多处工艺会向PI基底中引入氟离子，造成PI基底的氟离子污染，其中最主要的工艺为半导体离子注入工艺，在向半导体层注入硼离子时大多使用BF3，在没有半导体层或金属层阻挡的地方，高能离子可穿透膜层进入PI基底中，因氟离子较小且有较强的结合力容易附着在PI基底中无法排出。在PI基底上方的TFT驱动电路开始工作时，随着电信号变化，PI基底中的氟离子定向移动形成感应电场，该感应电场对TFT沟道信号形成干扰，导致信号响应变慢，造成显示残像。
发明内容
为了解决上述技术问题，本公开提供一种显示基板及其制作方法、显示装置，解决PI基底被氟离子污染而造成显示残像的问题。
为了达到上述目的，本公开实施例采用的技术方案是：一种显示基板，包括柔性基底，以及位于所述柔性基底上的TFT驱动电路，所述TFT驱动电路包括位于所述柔性基底上的图案化的半导体层，所述显示基板还包括阻挡层，所述阻挡层被配置为阻挡氟离子进入所述柔性基底，所述阻挡层与所述半导体层同层设置，或者所述阻挡层位于所述半导体层和所述柔性基底之间。
可选的，所述阻挡层采用多晶硅材料制成。
可选的，所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述半导体层在所述柔性基底上的正投影位于所述镂空部在所述柔性基底上的正投影内。
可选的，所述TFT驱动电路还包括位于所述半导体层远离或所述基底的一侧的栅极金属层，所述半导体层在所述柔性基底上的正投影为第一投影，所述栅极金属层在所述柔性基底上的正投影为第二投影，所述第一投影和所述第二投影部分重叠形成第三投影；
所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述第三投影位于所述镂空部在所述柔性基底上的正投影内。
可选的，所述TFT驱动电路在所述柔性基底上的正投影为第四投影，所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述第四投影位于所述镂空部在所述柔性基底上的正投影内。
可选的，所述阻挡层位于所述半导体层和所述柔性基底之间，所述阻挡层采用多晶硅或金属制成。
可选的，所述半导体层和所述柔性基底之间设置有缓冲层，所述阻挡层位于所述缓冲层和所述柔性基底之间。
可选的，沿着远离所述柔性基底的方向，所述柔性基底上依次设置有隔离层和缓冲层，所述半导体层形成于所述缓冲层远离所述隔离层的一侧，所述阻挡层设置于所述缓冲层和所述隔离层之间，或者所述阻挡层设置于所述柔性基底和所述隔离层之间。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板， 包括：
在所述柔性基底上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层和阻挡层。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板，包括：
在所述柔性基底上形成阻挡层；
在所述阻挡层上形成缓冲层；
在所述阻挡层上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
可选的，在所述阻挡层上形成缓冲层的步骤之前还包括：
在所述阻挡层上形成隔离层。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板，包括：
在所述柔性基底上依次形成隔离层、阻挡层和缓冲层；
在所述缓冲层上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
本公开实施例还提供一种显示装置，包括上述的显示基板。
本公开的有益效果是：通过所述阻挡层的设置防止氟离子浸入所述柔性基底，改善OLED残像不良。
附图说明
图1表示相关技术中半导体层进行轻掺杂的状态示意图；
图2表示相关技术中半导体层进行重掺杂的状态示意图；
图3表示相关技术中发生残像的状态示意图；
图4表示半导体层的结构示意图；
图5表示半导体层和栅极金属层的结构示意图；
图6表示本公开实施例中阻挡层的结构示意图一；
图7表示本公开实施例中的阻挡层的结构示意图二；
图8表示本公开实施例中进行轻掺杂的状态示意图；
图9表示本公开实施例中进行重掺杂的状态示意图；
图10表示本公开实施例中未出现残像的状态的示意图；
图11表示本公开实施例中的阻挡层的结构示意图三；
图12表示本公开实施例中的阻挡层的结构示意图四。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
参考图1和图2，半导体离子注入工艺包括轻掺杂和重掺杂，注入硼离子时大多使用BF3，在没有多晶硅或金属层(参考图2中的栅极金属层3)阻挡的地方，高能离子可穿透膜层进入PI基底中，因氟离子较小且有较强的结合力容易附着在PI基底1中无法排出。在PI基底1上方的TFT驱动电路开始工作时，随着电信号变化，PI基底1中的氟离子定向移动形成感应电场，该感应电场对上部TFT沟道信号形成干扰，导致信号响应变慢，造成显示残像，参考图3。
参考图4-图12，针对上述问题，本实施例提供一种显示基板，包括柔性基底1，以及位于所述柔性基底1上的TFT驱动电路，所述TFT驱动电路包括位于所述柔性基底1上的图案化的半导体层2，所述显示基板还包括阻挡层 5，所述阻挡层5被配置为阻挡氟离子进入所述柔性基底1，所述阻挡层5与所述半导体层2同层设置，或者所述阻挡层5位于所述半导体层2和所述柔性基底1之间。
通过所述阻挡层5的设置防止氟离子浸入所述柔性基底1，改善OLED残像不良。
需要说明的是，所述柔性基底1采用聚酰亚胺制成，但并不以此为限。
示例性的实施方式中，因为多晶硅膜层较致密，可以抵挡离子注入能量的穿透，所述阻挡层5采用多晶硅材料制成，但并不以此为限。
示例性的实施方式中，所述阻挡层5与所述半导体层2同层设置，所述阻挡层5包括镂空部和遮挡部，所述镂空部的形状与所述半导体层2的形状相符，以使得所述半导体层2位于所述镂空部内(即所述半导体层2在所述柔性基底上的正投影位于所述镂空部在所述柔性基底上的正投影内)。
所述阻挡层5可采用多晶硅制成，在所述半导体层2也采用多晶硅制成时，所述阻挡层5和所述半导体层2可以采用同步光照处理工艺(即构图工艺，包括曝光、显影等)形成，减化工序，但并不以此为限。
在平行于所述柔性基底1的方向上，所述半导体层2的形状如图4所示，所述镂空部的形状与所述半导体层2的形状相符，围设于所述半导体层2的四周，起到阻挡作用，可以减少或避免氟离子进入所述柔性基底1，参考图6。
示例性的，所述阻挡层5和所述半导体层2之间具有间隙，以免影响TFT的性能。
示例性的，所述阻挡层5和所述半导体层2之间的间隙大于或等于1um，但并不以此为限。
示例性的实施方式中，所述阻挡层5与所述半导体层2同层设置，在平行于所述柔性基底1的方向上，所述阻挡层5围设于所述阻挡层5和位于所述半导体层2上的栅极金属层3的四周。
参考图5和图7，本实施方式中的所述阻挡层5围设于所述阻挡层5和位于所述半导体层2上的栅极金属层3的四周，避免遮挡所述栅极金属层3，防止影响TFT驱动电路的性能。
所述TFT驱动电路还包括位于所述半导体层2远离或所述基底1的一侧 的栅极金属层3，所述半导体层2在所述柔性基底1上的正投影为第一投影，所述栅极金属层3在所述柔性基底1上的正投影为第二投影，所述第一投影和所述第二投影部分重叠形成第三投影；
所述阻挡层5与所述半导体层2同层设置，所述阻挡层5包括镂空部和遮挡部，所述镂空部在所述柔性基底1上的正投影的形状与所述第三投影的形状相符，使得所述半导体层2和所述栅极金属层3位于所述镂空部内(即使得所述第三投影位于所述镂空部在所述柔性基底上的正投影内)。
示例性的实施方式中，所述TFT驱动电路在所述柔性基底1上的正投影为第四投影，所述阻挡层5与所述半导体层2同层设置，所述阻挡层5包括镂空部和遮挡部，所述镂空部在所述柔性基底1上的正投影的形状与所述第四投影的形状相符，以使得所述TFT驱动电路整体位于所述镂空部内(即所述第四投影位于所述镂空部在所述柔性基底上的正投影内)。
所述TFT驱动电路包括所述半导体层2、栅极金属层3、源漏金属层等，本实施方式中，在未设置所述TFT驱动电路的区域设置所述阻挡层5，在有效的防止氟离子进入所述柔性基底1的基础上，避免影响TFT驱动电路的性能。
图8表示本公开实施例中进行轻掺杂的状态示意图，图9表示本公开实施例中的重掺杂的状态示意图，图1和图8进行对比，2和图9进行对比，通过所述阻挡层5的设置，无论是轻掺杂工艺还是重掺杂工艺，都减少了氟离子进入柔性基底1的量，对比图3和图10可知，增加阻挡层5后，明显改善残像问题。
需要说明的是，所述阻挡层5采用多晶硅制成，且与所述多晶硅制成的半导体层2同层设置具有以下优点：1、在多晶硅覆盖区域，离子注入工序中氟离子无法穿透多晶硅进入下方的柔性基底1，可以防止柔性基底1被氟离子污染，避免氟离子导致的残像恶化；2、使用低温多晶硅遮挡非电路区域，既不影响TFT性能又能节省一道遮挡光照；3、多晶硅具有透光性，使用多晶硅遮挡非电路区域对显示器透过率影响较小。
需要说明的是，本实施方式中的所述TFT驱动电路可以仅包括驱动晶体管和开关晶体管，也可以是TFT驱动电路全部(不仅包括驱动晶体管和开关晶体管，还包括信号线等)。
示例性的实施方式中，所述阻挡层5位于所述半导体层2和所述柔性基底1之间，所述阻挡层5采用多晶硅或金属制成。
所述阻挡层5位于所述半导体层2和所述柔性基底1之间，即所述阻挡层5与所述半导体异层设置，则所述阻挡层5的材料的选择相对于所述阻挡层5与所述半导体层2同层设置选择范围更大了，示例性的可以选择多晶硅或金属，但并不以此为限，只要可以阻挡氟离子进入所述柔性基底1即可。
所述阻挡层5设置于所述半导体层2和所述柔性基底1之间时，所述阻挡层5在所述柔性基底1上的正投影可以完全覆盖所述柔性基底1。
在所述柔性基底1和所述半导体层2之间还有其他膜层，所述阻挡层5的设置位置可以根据实际需要设定。
参考图11，示例性的实施方式中，所述半导体层2和所述柔性基底1之间设置有缓冲层6，所述阻挡层5位于所述缓冲层6和所述柔性基底1之间。
参考图12，示例性的实施方式中，沿着远离所述柔性基底1的方向，所述柔性基底1上依次设置有隔离层7和缓冲层6，所述半导体层2形成于所述缓冲层6远离所述隔离层7的一侧，所述阻挡层5设置于所述缓冲层6和所述隔离层7之间，或者所述阻挡层5设置于所述柔性基底1和所述隔离层7之间。
隔离层7可减少或防止来自所述柔性基底1的下方的杂质、水分或外部空气的渗入。
本实施例中，所述柔性基底1形成于玻璃衬底基板10上。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板，包括：
在所述柔性基底上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层和阻挡层。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板，包括：
在所述柔性基底上形成阻挡层；
在所述阻挡层上形成缓冲层；
在所述阻挡层上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述 多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
可选的，在所述阻挡层上形成缓冲层的步骤之前还包括：
在所述阻挡层上形成隔离层。
本公开实施例还提供一种显示基板的制作方法，用于制作上述的显示基板，包括：
在所述柔性基底上依次形成隔离层、阻挡层和缓冲层；
在所述缓冲层上形成多晶硅层；
对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
本公开实施例还提供一种显示装置，包括上述的显示基板。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (13)

  1. 一种显示基板，包括柔性基底，以及位于所述柔性基底上的TFT驱动电路，所述TFT驱动电路包括位于所述柔性基底上的图案化的半导体层，其中，所述显示基板还包括阻挡层，所述阻挡层被配置为阻挡氟离子进入所述柔性基底，所述阻挡层与所述半导体层同层设置，和/或所述阻挡层位于所述半导体层和所述柔性基底之间。
  2. 根据权利要求1所述的显示基板，其中，所述阻挡层采用多晶硅材料制成。
  3. 根据权利要求2所述的显示基板，其中，所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述半导体层在所述柔性基底上的正投影位于所述镂空部在所述柔性基底的正投影内。
  4. 根据权利要求2所述的显示基板，其中，所述TFT驱动电路还包括位于所述半导体层远离或所述基底的一侧的栅极金属层，所述半导体层在所述柔性基底上的正投影为第一投影，所述栅极金属层在所述柔性基底上的正投影为第二投影，所述第一投影和所述第二投影部分重叠形成第三投影；
    所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述第三投影位于所述镂空部在所述柔性基底上的正投影内。
  5. 根据权利要求2所述的显示基板，其中，所述TFT驱动电路在所述柔性基底上的正投影为第四投影，所述阻挡层与所述半导体层同层设置，所述阻挡层包括镂空部和遮挡部，所述第四投影位于所述镂空部在所述柔性基底上的正投影内。
  6. 根据权利要求1所述的显示基板，其中，所述阻挡层位于所述半导体层和所述柔性基底之间，所述阻挡层采用多晶硅或金属制成。
  7. 根据权利要求1所述的显示基板，其中，所述半导体层和所述柔性基底之间设置有缓冲层，所述阻挡层位于所述缓冲层和所述柔性基底之间。
  8. 根据权利要求1所述的显示基板，其中，沿着远离所述柔性基底的方向，所述柔性基底上依次设置有隔离层和缓冲层，所述半导体层形成于所述缓冲层远离所述隔离层的一侧，所述阻挡层设置于所述缓冲层和所述隔离层之间， 或者所述阻挡层设置于所述柔性基底和所述隔离层之间。
  9. 一种显示基板的制作方法，用于制作权利要求1-8任一项所述的显示基板，其中，包括：
    在所述柔性基底上形成多晶硅层；
    对所述多晶硅层进行构图工艺处理以获得图案化的半导体层和阻挡层。
  10. 一种显示基板的制作方法，用于制作权利要求1-8任一项所述的显示基板，其中，包括：
    在所述柔性基底上形成阻挡层；
    在所述阻挡层上形成缓冲层；
    在所述阻挡层上形成多晶硅层；
    对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
  11. 根据权利要求10所述的显示基板的制作方法，其中，在所述阻挡层上形成缓冲层的步骤之前还包括：
    在所述阻挡层上形成隔离层。
  12. 一种显示基板的制作方法，用于制作权利要求1-8任一项所述的显示基板，其中，包括：
    在所述柔性基底上依次形成隔离层、阻挡层和缓冲层；
    在所述缓冲层上形成多晶硅层；
    对所述多晶硅层进行构图工艺处理以获得图案化的半导体层，或者对所述多晶硅层进行构图工艺处理以同时获得图案化的半导体层和阻挡层。
  13. 一种显示装置，其中，包括权利要求1-8任一项所述的显示基板。
PCT/CN2023/111904 2022-08-31 2023-08-09 显示基板及其制作方法、显示装置 WO2024046065A1 (zh)

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CN114497145A (zh) * 2020-11-12 2022-05-13 三星显示有限公司 显示设备和制造其的方法
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CN114497145A (zh) * 2020-11-12 2022-05-13 三星显示有限公司 显示设备和制造其的方法
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