WO2024045864A9 - 半导体器件、制备方法以及电子设备 - Google Patents

半导体器件、制备方法以及电子设备 Download PDF

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Publication number
WO2024045864A9
WO2024045864A9 PCT/CN2023/104275 CN2023104275W WO2024045864A9 WO 2024045864 A9 WO2024045864 A9 WO 2024045864A9 CN 2023104275 W CN2023104275 W CN 2023104275W WO 2024045864 A9 WO2024045864 A9 WO 2024045864A9
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layer
channel
gate
substrate
semiconductor device
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PCT/CN2023/104275
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English (en)
French (fr)
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WO2024045864A1 (zh
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张齐飞
黄敬勇
李洋洋
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华为技术有限公司
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Publication of WO2024045864A1 publication Critical patent/WO2024045864A1/zh
Publication of WO2024045864A9 publication Critical patent/WO2024045864A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to semiconductor devices, preparation methods and electronic devices.
  • CMOS Complementary Metal Oxide Semiconductor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • Fin FET Fin Field-Effect Transistor
  • GAAFET Gate All Around Field-Effect Transistor
  • the common preparation method of GAAFET devices is: first, alternately epitaxially grow stacked film layers of sacrificial layers and channel layers. Afterwards, use selective etching technology to remove the sacrificial layer and retain the channel layer to form GAAFET.
  • selective etching technology usually adopts dry etching process, but ion bombardment and tip discharge will occur in the dry etching process, which can easily cause etching damage to the channel layer and faster etching rate at the corners, resulting in unsatisfactory channel profile and channel interface. In this way, on the one hand, the effective channel width is reduced, and on the other hand, the mobility is degraded, which degrades the device performance.
  • the embodiments of the present application provide a semiconductor device, a preparation method, and an electronic device for improving the problems of unsatisfactory channel profile and channel interface caused by etching damage and a faster etching rate at corners.
  • an embodiment of the present application provides a method for preparing a semiconductor device, which comprises: forming a plurality of stacked structures arranged at intervals from each other on a substrate, and making the stacked structures include alternatingly stacked sacrificial layers and channel layers, and forming an isolation structure in the substrate between two adjacent stacked structures; forming a dummy gate structure spanning the stacked structures, and making the dummy gate structure cover the channel region of the channel layer, forming gate sidewalls, source and drain regions, and an interlayer insulating layer in sequence on both sides of the dummy gate structure, removing the dummy gate structure to form a gate opening, etching the sacrificial layer inwardly from the exposed surface of the sacrificial layer in the gate opening, protruding a portion of the channel region of each channel layer from the sacrificial layer, coating the surface of the channel region exposed in the gate opening with a protective layer, removing the sacrificial layer in the gate opening,
  • the present application can make the first surface of the channel layer farthest from the substrate covered by the protective layer, while a part of the second surface of each channel layer is covered by the sacrificial layer but not covered by the protective layer. Therefore, compared with the area at the corresponding reference area in the second surface, the area at the corresponding reference area in the first surface is protected by the protective layer during the process of etching and removing the sacrificial layer, and the etching damage can be reduced. Therefore, the flatness of the first surface at the corresponding reference area is greater than the flatness of the second surface of the channel layer at the corresponding reference area.
  • part of the third surface of the channel layer has a partial area covered by the sacrificial layer but not covered by the protective layer. Therefore, compared with the area at the corresponding reference area in the third surface, the area at the corresponding reference area in the first surface is protected by the protective layer during the process of etching and removing the sacrificial layer, thereby reducing etching damage. Therefore, the flatness of the first surface at the corresponding reference area is greater than the flatness of the third surface at the corresponding reference area of the channel layer.
  • the protective layer not only the first surface is covered by the protective layer, but also the partial area of the channel region of each channel layer protruding from the sacrificial layer (i.e., the corners and sidewalls of the channel region) is also covered by the protective layer, so that the sidewalls and corners of the channel region are protected by the protective layer, which can avoid the problem of unsatisfactory channel profile and channel interface due to etching damage and fast etching rate at the corners. Therefore, in the embodiment of the present application, by setting a protective layer, the channel region is protected from damage during the etching process of the sacrificial layer, and a channel region with an ideal profile and intact interface is formed. Thereby, the problem of reduced effective channel width and mobility degradation of the device is improved, and the device performance is improved.
  • the gate structure is formed to surround the channel region of each channel layer.
  • the gate structure includes a metal gate and a gate Dielectric layer.
  • the metal gate surrounds the channel region of the channel layer, and the gate dielectric layer is arranged between the metal gate and the channel region of the channel layer.
  • the metal gate surrounds the channel region of the channel layer through the gate dielectric layer.
  • the channel layer surrounded by the gate structure is a nanosheet channel layer, that is, the formed GAAFET is a nanosheet GAAFET.
  • the substrate may be bulk silicon, a silicon-on-insulator (SOI) substrate, a strain buffer layer (SRB), a Ge substrate or other substrates, without limitation herein.
  • SOI silicon-on-insulator
  • SRB strain buffer layer
  • the substrate is used to prepare the wafer part of the integrated circuit or semiconductor device.
  • the substrate needs to be highly doped to suppress the formation of the inversion layer channel.
  • an ion distribution with a certain concentration and depth distribution is formed in the substrate to achieve high doping of the substrate.
  • diffusion an ion distribution with a certain concentration and depth distribution is formed in the substrate to achieve high doping of the substrate.
  • the surface of the channel layer in the gate opening is coated with a protective layer, including:
  • a material having a high etching selectivity ratio with the sacrificial layer material and the channel layer material may be used to deposit a protective initial film layer on the surface of the sacrificial layer and the surface of the channel layer in the gate opening.
  • a deposition process is used to deposit a protective layer.
  • the thickness of the protective layer may be different. Generally, the thickness of the protective layer is about half of the thickness of the sacrificial layer.
  • the environmental conditions of different sizes are different.
  • the material of the protective layer should be selected to have high etching selectivity for the sacrificial layer and the channel layer material.
  • the material of the protective layer should also be different from the materials used in the gate sidewalls, inner sidewalls and isolation structures to ensure that the protective layer material here can be selectively removed in the following step of removing the protective layer without corroding the gate sidewalls, inner sidewalls and isolation structures.
  • the material of the protective layer includes but is not limited to a-Si, SiN, SiNO, SiOC and other materials, which can be flexibly selected according to different scenarios.
  • a deposition process is used to form a protective initial film layer.
  • a deposition process with poor conformality can be selected.
  • a vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and a plasma enhanced atomic layer deposition process can be used to utilize the poor conformality of the deposition process to form the following filling method: depositing a protective initial film layer in the gate opening so that the protective initial film layer covers the surface of the sacrificial layer and the surface of the channel layer in the gate opening, and the protective initial film layer seals the open end of the first groove to stop the deposition after the protective initial film layer is enclosed in the first groove to form a cavity.
  • the thickness of the protective initial film layer on the surface of the sacrificial layer is less than the thickness of the protective initial film layer on the surface of the channel layer.
  • the protective layer material inside the first groove is not fully filled, and the open end of the first groove is sealed in advance by the protective layer material, resulting in holes in the protective layer inside the first groove, while the protective layer material on the sidewalls, top and corners of the channel layer is filled more fully and thicker.
  • the protective initial film layer on the surface of the sacrificial layer is removed, and the protective initial film layer on the surface of the channel layer in the gate opening is retained to form a protective layer.
  • the structure of the protective layer is modified by utilizing the difference in filling inside and outside the first groove.
  • a dry etching process is used to thin the protective initial film layer, so that an opening is formed in the protective initial film layer that closes the open end of the first groove, so as to remove the protective initial film layer on the surface of the sacrificial layer at the bottom end of the first groove, and retain the protective initial film layer on the surface of the channel layer to form a protective layer.
  • a dry etching process with precise etching control is used to ensure that the seal of the first groove is opened, the protective layer material inside the first groove (especially the bottom) is etched, and the protective layer material on the sidewalls, top and corners of the channel layer is partially left.
  • the contour of filling and etching of the protective layer is not limited to the above-mentioned contour, as long as the protective layer is deposited and etched to form the shape of the corners, top and sidewalls of the channel region of the channel layer protected, for example, the protective layer inside the first groove may have many holes, or the quality may be very poor, and it does not matter whether the protective layer is deposited on the sidewalls of the sacrificial layer, as long as the bottom of the first groove is finally formed after the protective layer is etched to expose the sacrificial layer, and the sidewalls, top and corners of the channel layer are protected by the protective layer.
  • this is only an ideal situation. In the preparation process, the process of removing the protective layer may deviate.
  • the protective initial film layer at the corners of the sacrificial layer and the channel layer is not completely removed, and there is a small amount of residue.
  • the protective initial film layer near the above-mentioned corners of the channel layer is removed, which can also meet the requirements.
  • the sacrificial layer exposed in the gate opening may be partially selectively etched to etch a first groove of a certain depth.
  • the first groove is formed by adjacent channel layers and the sacrificial layer disposed between adjacent channel layers, so that a portion of the channel region of each channel layer protrudes from the sacrificial layer.
  • the bottom of the first groove is formed by the sacrificial layer, and in the second direction, the sidewalls of the first groove are formed by the adjacent channel layers.
  • the sidewall of the first groove is formed by the inner sidewall, so that the height of the first groove can be equal to the thickness of the sacrificial layer.
  • a partial area of the channel layer protruding from the sacrificial layer has a first width.
  • the sacrificial layer has a first thickness.
  • the present application does not limit the first width.
  • the first width can generally be made no greater than the first thickness.
  • the first width defines the depth of the first groove.
  • the first width is 5nm to 10nm, that is, the depth of the first groove is 5nm to 10nm.
  • the first width can also be made greater than the first thickness. In practical applications, the first width and the first thickness can be determined according to the needs of the practical application.
  • the sacrificial layer is etched using an atomic layer etching (ALE) process with precise etching control or a dry continuous etching process, and the etching needs to have good selectivity for the channel layer to minimize damage to the channel layer.
  • ALE atomic layer etching
  • the surface of the channel layer in the gate opening is coated with the protective layer, including: a selective deposition process can be used to deposit the protective layer on the surface of the channel layer in the gate opening.
  • a dry etching process may be used to remove the protective layer, and in the dry etching process for removing the protective layer, the etching bias voltage may be set to a range of 0 to 150 V to ensure that the ion bombardment generated in the step of etching to remove the protective layer is small, so as to minimize etching damage to the first surface of the channel layer farthest from the substrate, and to ensure that the flatness of the first surface is better than the flatness of the second surface and the third surface.
  • wet etching may also be used to remove the protective layer to avoid etching damage to the first surface, and to ensure that the flatness of the first surface is better than the flatness of the second surface and the third surface.
  • the process includes:
  • gate sidewalls may be formed on both sides of the dummy gate structure along the first direction to reduce the short channel effect.
  • the hard mask on the top of the dummy gate structure may be temporarily retained without additional removal. In this way, the hard mask may be used as an etching stop layer during the formation of the gate sidewalls.
  • the present application does not limit the material of the gate sidewall, for example, it can be a dielectric material such as silicon nitride (SiNx), silicon oxynitride, silicon oxycarbide, or a low dielectric constant material such as an air gap.
  • a dielectric material such as silicon nitride (SiNx), silicon oxynitride, silicon oxycarbide, or a low dielectric constant material such as an air gap.
  • the present application does not impose any limitation on the thickness of the gate spacer, which may be, for example, 2 nm to 10 nm.
  • the gate spacer material is grown isotropically, and the grown thickness is consistent with the designed gate spacer thickness. Afterwards, anisotropic etching is performed to remove the gate spacer except for the two sides of the dummy gate structure, and the etching stops on the hard mask as an etching stop layer.
  • the stacked structures on both sides of the dummy gate structure are removed to expose the sides of the sacrificial layer and the channel layer under the gate spacer, that is, the stacked structures not covered by the dummy gate structure and the gate spacer are removed by etching to expose the sides of the channel layer and the sacrificial layer along the first direction.
  • the sacrificial layer below the gate spacer is removed, and a second groove is formed between adjacent channel layers below the gate spacer.
  • the bottom of the second groove is formed by the sacrificial layer
  • the sidewalls of the second groove in the second direction are formed by the adjacent channel layer
  • the sidewalls of the second groove in the third direction are formed by the gate spacer.
  • the height of the second groove can be equal to the thickness of the sacrificial layer.
  • a selective etching process is used to etch the exposed sacrificial layer to recess the sacrificial layer to form a second groove.
  • the depth of the second groove ultimately defines the thickness of the inner sidewall
  • the height of the second groove is the thickness of the sacrificial layer and ultimately defines the height of the inner sidewall.
  • the height of the inner sidewall is greater than its thickness, so the height of the second groove is not less than its depth.
  • the ideal shape of the second groove is a rectangle, and the etching process for etching the sacrificial layer here needs to have a high selectivity ratio for the channel layer material and precise etching control.
  • the shape of the second groove may not be completely rectangular, and it only needs to roughly meet the above conditions.
  • the present application does not impose any limitation on the thickness of the inner sidewall, for example, it may be 1nm to 10nm. Then the depth of the second groove may be the same as the thickness of the inner sidewall to be formed.
  • the width of the inner sidewall in the extension direction parallel to the channel region is not greater than the thickness of the sacrificial layer in the plane perpendicular to the substrate. It should be noted that in practical applications, the width of the inner sidewall may but does not have to be consistent with the thickness of the gate sidewall. For example, the width of the inner sidewall may be less than the thickness of the gate sidewall. In practical applications, the width of the inner sidewall may be determined according to the requirements of the actual application environment and is not limited here.
  • a dielectric material is filled in the second groove to form an inner sidewall, and the width of the inner sidewall in a direction parallel to the extension direction of the channel region is generally not greater than the thickness of the sacrificial layer in a direction perpendicular to the plane where the substrate is located.
  • the inner sidewalls are located at both ends of the sacrificial layer to isolate the metal gate from the source/drain region and reduce the overlap between the gate and the source and the gate and the drain. Capacitors, while ensuring that the first and second regions are not exposed and etched during the channel release process, thereby achieving precise gate length control.
  • the material selection of the inner sidewall needs to have high etching resistance during the sacrificial layer etching. In addition, the material selection of the inner sidewall also needs to have high selectivity for the channel material. Due to the need for low overlap capacitance, dielectric materials with low dielectric constants (for example, dielectric materials with a dielectric constant not greater than 7) are used as much as possible.
  • the material of the inner sidewall can be a single layer, or a multilayer design with different material combinations can be used as required, and there is no limitation here.
  • the material of the inner sidewall includes but is not limited to a dielectric material composed of any combination of silicon (Si) and carbon (C), oxygen (O), and nitrogen (N).
  • a deposition process is used to isotropically deposit the dielectric material of the inner sidewall, and the deposition process needs to have good filling properties to perfectly fill the second groove.
  • the deposition process includes but is not limited to a process.
  • an etching process is used to etch the deposited inner sidewall material, leaving only the material in the second groove to form the inner sidewall.
  • source and drain regions connected to the channel layer are epitaxially formed on the substrate at both sides of the dummy gate structure.
  • epitaxial process is used to grow source and drain regions on both sides of the dummy gate structure.
  • the materials of the source and drain regions can be designed according to the conductive channel type of the transistor to provide stress and other methods to promote transistor performance, and the materials of the source and drain regions are generally similar to the channel layer material and the sacrificial layer material to ensure effective growth of the source and drain regions.
  • the materials of the source region and the drain region include but are not limited to Si, GaAs, GaAsP, SiP or other suitable materials, and doping (such as phosphorus (P), arsenic (As)) is introduced during the epitaxial growth process or non-in-situ doping is performed using an ion implantation process.
  • doping such as phosphorus (P), arsenic (As)
  • the materials of the source region and the drain region include but are not limited to Si, Ge, SiGe, AlGaAs, boron-doped SiGe or other suitable materials, and boron (B) is introduced by in-situ doping during the epitaxial growth process or non-in-situ doping is performed by ion implantation process.
  • an interlayer insulating layer is deposited on the source/drain region and the dummy gate structure.
  • the interlayer insulating layer includes an etch stop layer (Contact Etch Stop Layer, CESL) and an interlayer dielectric (Inter Layer Dielectrics, ILD) layer.
  • CESL covers the surface of the substrate 10 formed with the source and drain regions to prevent serious over-etching when etching contact holes (the source region is provided with contact holes corresponding to the source region, which are used to connect the source region with an external signal line, and the drain region is also provided with contact holes corresponding to the drain region, which are used to connect the drain region with an external signal line).
  • the ILD layer covers the top of the etch stop layer.
  • a thin CESL and a thick ILD layer are deposited over the entire structure of the substrate where the source and drain regions are formed.
  • the material of CESL includes but is not limited to silicon nitride, silicon oxide, and silicon oxynitride.
  • the present application does not limit the thickness of CESL, which is generally thin.
  • the material of the ILD layer includes but is not limited to tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG) and other dielectric materials.
  • TEOS tetraethyl orthosilicate
  • BPSG borophosphosilicate glass
  • FSG fused silica glass
  • PSG phosphosilicate glass
  • BSG boron-doped silica glass
  • other dielectric materials such as boron-doped silica glass (BSG) and other dielectric materials.
  • a suitable process is selected from deposition processes such as ALD and PECVD processes or oxidation processes to form a thinner CESL. Afterwards, a suitable process is selected from deposition processes such as PECVD to overfill the thicker ILD layer, and the height of the overfilled ILD layer is often higher than a certain thickness above the dummy gate structure. Afterwards, it is necessary to remove the excess ILD layer material and expose the top of the dummy gate structure. A planarization process such as CMP is often used to planarize the overfilled ILD layer, and stop when the top of the dummy gate structure is exposed.
  • deposition processes such as ALD and PECVD processes or oxidation processes to form a thinner CESL.
  • a suitable process is selected from deposition processes such as PECVD to overfill the thicker ILD layer, and the height of the overfilled ILD layer is often higher than a certain thickness above the dummy gate structure. Afterwards, it is necessary to remove the excess ILD layer material and expose the top of the
  • the overfilled ILD layer is planarized using a planarization process such as CMP, stop when the top of the hard mask on the dummy gate structure is exposed. Afterwards, the hard mask can be removed using an etching process. Afterwards, the overfilled ILD layer is planarized using a planarization process such as CMP, and stop when the top of the dummy gate structure is exposed.
  • a planarization process such as CMP
  • a gate structure surrounding each channel region is formed in a gate opening, including:
  • the gate structure extends along the third direction, and the same gate structure may span across channel regions of channel layers in one or more channel structures.
  • the gate structure includes a metal gate and a gate dielectric layer located between the metal gate and the channel layer, that is, the gate structure is a stacked structure formed by the metal gate and the gate dielectric layer.
  • a suitable deposition process is selected from ALD, CVD and other deposition processes, and a dielectric material is deposited on the substrate after removing the protective layer, and a gate dielectric layer is formed on the surface of each channel region and the sidewalls of the gate spacer in the gate opening.
  • a suitable deposition process is selected from ALD, CVD and other deposition processes, and a metal gate is deposited on the substrate with the gate dielectric layer formed to fill the gate opening. The metal gate covers the gate dielectric layer to surround the channel region of each channel layer.
  • the dielectric material forming the gate dielectric layer is a dielectric material with a high dielectric constant, which may be a dielectric material with a dielectric constant greater than that of silicon oxide, for example, aluminum oxide ( Al2O3 ), hafnium oxide ( HfO2 ), zirconium oxide ( ZrO2 ), lanthanum oxide ( La2O3 ) and the like.
  • the metal gate is generally a multi-layer structure, which includes but is not limited to a combination of a work function metal (possibly multiple work function metals), a liner layer, a wetting layer, an adhesion layer, a metal conductive layer or a metal silicide, etc.
  • the metal gate includes but is not limited to titanium (Ti), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), etc.
  • the gate structure in order to achieve better interface contact between the gate dielectric layer and the channel region and improve carrier mobility, the gate structure further includes an interface layer disposed between the gate dielectric layer and the channel layer.
  • the interface layer includes a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride.
  • other methods such as chemical oxidation, thermal oxidation, ALD, CVD, etc. may be used to grow the interface layer, and the process of growing the interface layer may occur before or after the gate dielectric layer is deposited.
  • a dummy gate structure spanning across each stacked structure including:
  • the dummy gate structure extends along a third direction, and the same dummy gate structure may span across multiple stacked structures (i.e., fins).
  • the present application does not limit the width of the dummy gate structure (i.e., the width along the first direction), but it must comply with the requirements of the technology node set by the International Roadmap for Equipment and Systems (IRDS) and be as short as possible while suppressing the short channel effect and the lithography process capabilities.
  • IRDS International Roadmap for Equipment and Systems
  • a dummy gate structure may include a dummy gate film layer and a dummy gate oxide layer located between the dummy gate film layer and the channel layer. That is, the dummy gate structure is a stacked structure formed by the dummy gate oxide layer and the dummy gate film layer, also called a gate stack.
  • the material of the dummy gate film layer is, for example, polysilicon.
  • a dummy gate oxide layer covering the entire substrate is formed on a substrate having a stacked structure. Then, a dummy gate film layer is formed on the dummy gate oxide layer. Then, a photolithography process and an etching process are used to pattern the dummy gate oxide layer and the dummy gate film layer, and the dummy gate oxide layer and the dummy gate film layer covering the area outside the channel area are removed, and the dummy gate oxide layer and the dummy gate film layer covering the channel area are retained to form a dummy gate structure.
  • a suitable process is selected from thermal oxidation process, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) to grow a thin dummy gate oxide layer and a thick polysilicon dummy gate film layer covering the entire substrate on a substrate having a stacked structure, so as to form a dummy gate stack.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a photolithography process and an etching process are used to form a hard mask on the dummy gate stack to define the pattern of the dummy gate structure through the hard mask.
  • an etching process is used to etch the dummy gate stack to pattern the dummy gate stack, remove the dummy gate stack covering the area outside the channel area, retain the dummy gate stack covering the channel area, and form the pattern of the dummy gate structure.
  • the hard mask on the top of the dummy gate structure can be temporarily retained without additional removal.
  • a substrate including:
  • a sacrificial layer and a channel layer are alternately epitaxially grown on a substrate to form a stacked film layer.
  • a superlattice stack of multiple layers of alternating sacrificial layers and channel layers is epitaxially grown on a substrate, with the top layer being the channel layer and the sacrificial layer being above the substrate, to form a stacked film layer.
  • the present application does not limit the number of channel layers in the stacked film layers, for example, it can be 3 to 7 layers.
  • the present application does not limit the thickness of the channel layer, which may be, for example, 5 nm to 40 nm.
  • the thickness of each channel layer is the same, which may be, for example, one of 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm.
  • the present application does not limit the thickness of the sacrificial layer, which may be, for example, 5 nm to 40 nm.
  • the thickness of each sacrificial layer is the same, which may be, for example, one of 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm.
  • the thickness of the sacrificial layer defines the filling thickness of the gate structure 40 .
  • the thickness of the channel layer is similar to or the same as the thickness of the sacrificial layer.
  • the present application does not limit the materials of the sacrificial layer and the channel layer.
  • Different types of sacrificial layer materials may be matched with different channel materials according to the requirements of etching selectivity.
  • the sacrificial layer not only plays a certain supporting role for the channel layer, but also needs to be able to be selectively etched and removed, that is, when etching and removing the sacrificial layer, the material of the sacrificial layer has high selectivity compared to the material of the channel layer.
  • the sacrificial layer sometimes needs to provide stress for the channel layer.
  • the material of the channel layer is Si
  • the corresponding material of the sacrificial layer may be SiGe.
  • the corresponding material of the sacrificial layer is GeSi or Ge.
  • the corresponding material of the sacrificial layer is Ge.
  • the corresponding material of the sacrificial layer is a III-V material.
  • the stacked film layers are patterned to form a plurality of stacked structures spaced apart from each other, and shallow grooves are formed in the substrate; the channel layer in the stacked structure is a nanosheet channel layer.
  • the stacked film layers may be patterned by a spacer image transfer (SIT) process to form a plurality of stacked structures spaced apart from each other, and shallow grooves may be formed in the substrate to form a fin pattern.
  • the stacked structure is the fin, the top layer is the channel layer, the bottom layer is the sacrificial layer, and the bottom is the substrate.
  • the channel layer in the stacked structure is the nanosheet channel layer.
  • the stacked film layers may be patterned by photolithography and etching processes to form a plurality of stacked structures spaced apart from each other, and shallow grooves may be formed in the substrate to form fin patterns.
  • the stacked structure is a fin
  • the top layer is a channel layer
  • the bottom layer is a sacrificial layer
  • the bottom is a substrate.
  • the channel layer in the stacked structure formed is a nanosheet channel layer.
  • the photolithography process may be an extreme ultraviolet (EUV) photolithography process, or a self-aligned multiple photolithography process (such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), etc.).
  • the etching process may be a reactive ion etching (RIE) process.
  • a self-aligned multiple photolithography process is used.
  • the pattern of the photoresist is first transferred to a hard mask (for example, the hard mask may be at least one of silicon oxide, silicon nitride, or a composite layer of silicon oxide and silicon nitride) through an RIE process, and then the stacked film layer and the substrate are etched through an RIE process to form a fin pattern.
  • the fin is a stacked structure, with the top layer being the channel layer, the bottom layer being the sacrificial layer, and the bottom being the substrate.
  • the width of the fin determines the width of the final nanosheet channel layer, which is approximately 20nm to 300nm, and the height of the stacked structure is approximately 60nm to 600nm.
  • the height of the stacked structure determines the depth of the shallow trench, which is approximately 50nm to 1000nm.
  • the hard mask on the top of the stacked structure can be temporarily retained without additional removal.
  • an isolation structure is formed in a substrate between two adjacent stacked structures, including: filling a dielectric material in a shallow trench to form an isolation structure.
  • a dielectric material may be filled in the shallow trenches between adjacent stacked structures to form a shallow trench isolation (STI) structure.
  • the STI structure is located at the bottom of the stacked structure (i.e., fins), and the upper surface of the STI structure is roughly flush with the lower surface of the sacrificial layer (i.e., the surface where the sacrificial layer contacts the substrate).
  • the parameters of the preparation process can be adjusted to make the upper surface of the STI structure as flush as possible with the lower surface of the sacrificial layer.
  • the dielectric material forming the STI structure includes, but is not limited to, silicon dioxide (SiO 2 ), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), and the like.
  • a dielectric material such as SiO 2
  • a thin and high-quality dielectric material such as SiO 2
  • a substrate formed with a shallow groove a substrate formed with a shallow groove
  • a high aspect ratio process such as SiO 2
  • SOD spin on dielectric
  • FCVD flowable chemical vapor deposition
  • the dielectric material (such as SiO 2 ) film layer is planarized by a chemical mechanical polishing ( CMP ) process, and the planarization process is stopped when it is about to reach the channel layer of the stacked structure (i.e., the fin), and a certain process window is reserved.
  • CMP chemical mechanical polishing
  • the filled dielectric material eg SiO 2
  • the etching is stopped when the lower surface (ie, the surface where the sacrificial layer contacts the substrate) of the stacked structure (ie, the fin) is etched.
  • an embodiment of the present application further provides a semiconductor device, which is formed by the above-mentioned preparation method.
  • the semiconductor device includes: a substrate, and one or more transistors arranged on the substrate.
  • the transistor includes a channel structure arranged on the substrate, a gate structure arranged on the substrate, a gate sidewall arranged on both sides of the gate structure, a source and drain region arranged on both sides of the gate structure, and an interlayer insulating layer arranged on the source and drain region.
  • the channel structure may include a plurality of channel layers stacked on the substrate. And, adjacent channel layers are not in direct contact with each other, but are provided with a gate structure.
  • the channel layer and the substrate are not in direct contact with each other, but are provided with a gate structure.
  • the channel layer may be extended along a first direction, and the channel layer may be arranged along a second direction.
  • the gate structure may be extended along a third direction.
  • the first direction, the second direction, and the third direction are perpendicular to each other.
  • the gate structure surrounds the channel region of each channel layer.
  • the gate structure includes a metal gate and a gate dielectric layer.
  • the metal gate surrounds the channel region of the channel layer, and the gate dielectric layer is disposed between the metal gate and the channel region of the channel layer.
  • the metal gate surrounds the channel region of the channel layer via the gate dielectric layer.
  • the channel layer has a first region and a second region, and a channel region between the first region and the second region. Furthermore, the orthographic projections of the first region in the channel layer on the substrate may overlap, the orthographic projections of the second region in the channel layer on the substrate may overlap, and the orthographic projections of the channel regions in the channel layer on the substrate may overlap. Furthermore, the orthographic projections of the gate spacers on the substrate cover the orthographic projections of the first region and the second region in the channel layer on the substrate.
  • the orthographic projection of the gate spacer on the substrate can overlap with the orthographic projection of the first and second regions in the channel layer on the substrate, and the orthographic projection of the gate structure on the substrate covers the orthographic projection of the channel region of the channel layer on the substrate.
  • the source region is arranged on the side of the first region of the channel layer away from the channel region and in contact with the first region of the channel layer, so that the source region can be used as a source electrode for transmitting electrical signals.
  • the drain region is arranged on the side of the second region of the channel layer away from the channel region and in contact with the second region of the channel layer, so that the drain region can be used as a drain electrode for transmitting electrical signals.
  • the above overlap cannot be completely overlapped and there may be some deviations. Therefore, as long as the above overlap relationship roughly meets the above conditions, it belongs to the protection scope of this application.
  • the above overlap can be an overlap allowed within the allowable error range.
  • the semiconductor device may further include an isolation structure disposed in the substrate between two adjacent channel structures.
  • the substrate has a shallow trench isolation region to define an area covered by the channel structure on the substrate, and the isolation structure is disposed in the shallow trench isolation region to form a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • the channel layers are stacked on the substrate, the surface of the channel layer farthest from the substrate facing away from the substrate is defined as the first surface, the surface of any channel layer facing the substrate is defined as the second surface, and the surface of the remaining channel layers other than the channel layer farthest from the substrate facing away from the substrate is defined as the third surface.
  • a reference area is set, and the reference area covers the center of gravity of each channel layer in the direction perpendicular to the plane where the substrate is located.
  • the channel region of the channel layer has an uncovered area on the second surface that is not covered by the protective layer, and the reference area can be set in the uncovered area of each channel layer in the direction perpendicular to the plane where the substrate is located.
  • the first surface is covered by the protective layer, and part of the second surface is covered by the sacrificial layer but not covered by the protective layer, therefore, the area corresponding to the reference area in the first surface is compared with the area corresponding to the reference area in the second surface.
  • the protective layer which can reduce etching damage, so the flatness of the first surface corresponding to the reference area is greater than the flatness of the second surface corresponding to the reference area of the channel layer.
  • the flatness of the first surface corresponding to the reference region is greater than the flatness of the third surface of the channel layer corresponding to the reference region.
  • a protective layer is provided to protect the channel region from damage during the etching process of the sacrificial layer, thereby forming a channel region with an ideal profile and a good interface. This improves the problem of reduced effective channel width and mobility degradation of the device, and improves device performance.
  • the channel layer in the embodiment of the present application is a nanosheet (NS) channel layer. That is to say, the transistor in the embodiment of the present application can be a nanosheet surround gate field effect transistor (NS-GAAFET). Therefore, in the embodiment of the present application, a protective layer is provided to protect the nanosheet channel layer from damage during the etching process of the sacrificial layer, thereby forming a nanosheet channel region with an ideal profile and a good interface.
  • NS nanosheet
  • a protective layer is provided to protect the nanosheet channel layer from damage during the etching process of the sacrificial layer, thereby forming a nanosheet channel region with an ideal profile and a good interface.
  • the material of the channel layer may be Si, SiGe, Ge, GeSn, III-V compound semiconductor materials, etc. It should be noted that the NS-GAAFET provided in the embodiment of the present application is universal to all nanosheet structured GAAFET devices and integrated circuits.
  • the semiconductor device further includes: a plurality of inner spacers.
  • the gate spacer covers the inner spacer.
  • an inner spacer is arranged between the first region of the channel layer and the substrate, and an inner spacer is arranged between the first regions of each adjacent channel layer.
  • an inner spacer is arranged between the second region of the channel layer and the substrate, and an inner spacer is arranged between the second regions of each adjacent channel layer.
  • the metal gate can be isolated from the source region/drain region, the overlap capacitance between the gate source and the gate drain can be reduced, and at the same time, it is ensured that the first region and the second region are not exposed and etched during the channel release process, thereby achieving precise gate length control.
  • the orthographic projection of the gate spacer on the substrate overlaps with the orthographic projection of the inner sidewall on the substrate.
  • the orthographic projection of the inner sidewall on the substrate is arranged within the orthographic projection of the gate spacer on the substrate.
  • the embodiments of the present application also provide an electronic device, which may be a smart phone, a smart TV, a laptop computer and other devices.
  • the electronic device may include: a circuit board and a semiconductor device, and the semiconductor device is connected to the circuit board.
  • the semiconductor device may be a semiconductor device prepared by the first aspect or various embodiments of the first aspect, or the semiconductor device may also be a semiconductor device such as the second aspect or various embodiments of the second aspect. Since the performance of the transistor in the above-mentioned semiconductor device is better, the performance of the electronic device including the above-mentioned semiconductor device is also better.
  • the principle of solving the problem by the electronic device is similar to that of the aforementioned semiconductor device, so the implementation of the electronic device can refer to the implementation of the aforementioned semiconductor device, and the repeated parts will not be repeated.
  • FIG. 1a is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application.
  • FIG1b is a schematic cross-sectional view of the structure schematic diagram shown in FIG1a along the AA' direction;
  • FIG1c is another cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in FIG1a;
  • FIG. 1d is a schematic top view of a channel layer in the semiconductor device shown in FIG. 1a ;
  • FIG2 is a schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application
  • FIG3 is a schematic structural diagram of a process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG4a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG4b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG4a;
  • FIG5a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG5b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG5a;
  • Fig. 5c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 5a;
  • FIG6a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG6b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG6a;
  • Fig. 6c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 6a;
  • FIG7a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG7b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG7a;
  • Fig. 7c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 7a;
  • FIG8a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG8b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG8a;
  • Fig. 8c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 8a;
  • FIG9a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG9b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG9a;
  • Fig. 9c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 9a;
  • FIG10a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG10b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG10a;
  • FIG10c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in FIG10a;
  • FIG. 11a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG11b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG11a;
  • FIG11c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in FIG11a;
  • FIG12a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG12b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG12a;
  • Fig. 12c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 12a;
  • FIG13a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG13b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG13a;
  • Fig. 13c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 13a;
  • FIG. 14a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG14b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG14a;
  • Fig. 14c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 14a;
  • FIG15a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG15b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG15a;
  • Fig. 15c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 15a;
  • FIG16a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG16b is a schematic cross-sectional view of the structure along the AA' direction in the schematic diagram of the structure shown in FIG16a;
  • Fig. 16c is a cross-sectional structural schematic diagram along the BB' direction in the structural schematic diagram shown in Fig. 16a;
  • FIG16d is a schematic cross-sectional view of the structure after a protective layer is formed along the BB' direction in the structural schematic diagram shown in FIG16a;
  • FIG16e is a schematic cross-sectional view of the structure after the sacrificial layer is removed along the BB' direction in the structural schematic diagram shown in FIG16a;
  • FIG17a is a schematic structural diagram of another process for preparing a semiconductor device provided in an embodiment of the present application.
  • FIG17b is a cross-sectional structural schematic diagram along the AA' direction in the structural schematic diagram shown in FIG17a;
  • FIG. 17 c is a cross-sectional structural diagram along the BB′ direction in the structural diagram shown in FIG. 17 a .
  • connection refers to electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components.
  • a and B are connected, which can be either A and B directly connected, or A and B are indirectly connected through one or more other electrical components, for example, A and B are connected, or A and C are directly connected, C and B are directly connected, and A and B are connected through C.
  • example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art.
  • the same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted.
  • the words expressing position and direction described in this application are all illustrated using the accompanying drawings as examples, but changes may be made as needed, and all changes are included in the scope of protection of this application.
  • the drawings of this application are only used to illustrate relative position relationships and do not represent true proportions.
  • the transistor provided in the embodiment of the present application can achieve ideal control of the channel due to the setting of the gate structure wrapping the channel to form a GAAFET.
  • the performance of the semiconductor device can be improved.
  • the semiconductor device provided in the embodiment of the present application can be widely used in various electronic devices, for example, it can be applied to electronic devices with logic devices or storage devices.
  • the electronic device can be a smart phone, a smart TV, a laptop computer, a PDA (personal digital assistant), a wearable device with wireless communication function (such as a smart watch, smart glasses, smart bracelet), a vehicle-mounted device or a data center, etc.
  • the semiconductor device proposed in the embodiment of the present application is intended to include but is not limited to application in these and any other suitable types of electronic devices.
  • Figure 1a shows a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application
  • Figure 1b shows a schematic diagram of the cross-sectional structure along the AA' direction in Figure 1a of the present application
  • Figure 1c shows a schematic diagram of the cross-sectional structure along the BB' direction in Figure 1a of the present application
  • Figure 1d shows a schematic diagram of the top view structure of a channel layer (such as 31_4) in Figure 1a of the present application.
  • the semiconductor device in the embodiment of the present application may have one or more transistors, which have a channel structure 30, and the channel structure 30 includes a plurality of channel layers stacked and spaced apart.
  • the number of channel layers in the channel structure 30 can be set to 3 to 7 layers.
  • the number of channel layers set in the channel structure 30 can be determined according to the needs of the actual application environment, and is not limited here.
  • FIG. 1 a to FIG. 1 c only illustrate the four channel layers 31_1 to 31_4 of the channel structure 30 in a transistor by way of example.
  • the semiconductor device may include a substrate 10 and a transistor disposed on the substrate 10.
  • the transistor includes: a channel structure 30 disposed on the substrate 10, a gate structure 40 disposed on the substrate 10, a gate spacer 50 disposed on both sides of the gate structure 40, a source and drain region (such as a source region 60_1 and a drain region 60_2) disposed on both sides of the gate structure 40, and a gate structure 50 disposed on both sides of the gate structure 40.
  • An interlayer insulating layer 70 is disposed on the source and drain regions (such as the source region 60_1 and the drain region 60_2).
  • the channel structure 30 may include channel layers 31_1 to 31_4 stacked on the substrate 10, the channel layer 31_1 is closest to the substrate 10 compared to the other channel layers 31_2 to 31_4, the channel layer 31_2 is disposed on the side of the channel layer 31_1 away from the substrate 10, the channel layer 31_3 is disposed on the side of the channel layer 31_2 away from the substrate 10, and the channel layer 31_4 is disposed on the side of the channel layer 31_2 away from the substrate 10.
  • the channel layer 31_1 is not in direct contact with the substrate 10, but a gate structure 40 is disposed thereon, and the channel layer 31_1 is not in direct contact with the channel layer 31_2, but a gate structure 40 is disposed thereon.
  • the channel layer 31_2 is not in direct contact with the channel layer 31_3, but a gate structure 40 is disposed thereon.
  • the channel layer 31_3 and the channel layer 31_4 are not in direct contact with each other, but a gate structure 40 is disposed therebetween.
  • the channel layers 31_1 to 31_4 may be extended along the first direction F1, and the channel layers 31_1 to 31_4 may be arranged along the second direction F2.
  • the gate structure 40 may be extended along the third direction F3.
  • the first direction F1, the second direction F2 and the third direction F3 are perpendicular to each other.
  • the gate structure 40 surrounds the channel region of each channel layer 31_1 to 31_4.
  • the gate structure 40 includes a metal gate 42 and a gate dielectric layer 41.
  • the metal gate 42 surrounds the channel region G of the channel layers 31_1 to 31_4, and the gate dielectric layer 41 is disposed between the metal gate 42 and the channel region G of the channel layers 31_1 to 31_4.
  • the metal gate 42 surrounds the channel region G of the channel layers 31_1 to 31_4 via the gate dielectric layer 41. In this way, by making the metal gate 42 surround the channel region G of the channel layers 31_1 to 31_4, the arrangement of the metal gate 42 wrapping the channel is realized, and the ideal control of the channel can be achieved to form a GAAFET.
  • the channel layers 31_1 to 31_4 have a first region A1 and a second region A2, and a channel region G located between the first region A1 and the second region A2. Furthermore, the orthographic projections of the first region A1 in the channel layers 31_1 to 31_4 on the substrate 10 may overlap, the orthographic projections of the second region A2 in the channel layers 31_1 to 31_4 on the substrate 10 may overlap, and the orthographic projections of the channel regions G in the channel layers 31_1 to 31_4 on the substrate 10 may overlap.
  • the orthographic projections of the gate spacers 50 on the substrate 10 cover the orthographic projections of the first region A1 and the second region A2 in the channel layers 31_1 to 31_4 on the substrate 10.
  • the orthographic projection of the gate spacer 50 on the substrate 10 can overlap with the orthographic projection of the first area A1 and the second area A2 of the channel layers 31_1 to 31_4 on the substrate 10
  • the orthographic projection of the gate structure 40 on the substrate 10 covers the orthographic projection of the channel area G of the channel layers 31_1 to 31_4 on the substrate 10.
  • the source region 60_1 is arranged on the side of the first area A1 of the channel layers 31_1 to 31_4 away from the channel area G, and contacts the first area A1 of the channel layers 31_1 to 31_4, so that the source region 60_1 can be used as a source electrode for transmitting electrical signals.
  • the drain region 60_2 is arranged on the side of the second area A2 of the channel layers 31_1 to 31_4 away from the channel area G, and contacts the second area A2 of the channel layers 31_1 to 31_4, so that the drain region 60_2 can be used as a drain electrode for transmitting electrical signals.
  • the above overlap cannot be completely overlapped and there may be some deviations. Therefore, as long as the above overlap relationship roughly meets the above conditions, it belongs to the protection scope of this application.
  • the above overlap can be an overlap allowed within the allowable error range.
  • the semiconductor device may further include an isolation structure 20 disposed in the substrate 10 between two adjacent channel structures 30.
  • the substrate 10 has a shallow trench isolation region to define the region covered by the channel structure 30 on the substrate 10, and the isolation structure 20 is disposed in the shallow trench isolation region to form a shallow trench isolation (STI) structure.
  • STI shallow trench isolation
  • the channel layers 31_1 to 31_4 are stacked on the substrate 10, the channel layer 31_1 is closest to the substrate 10, and the channel layer 31_4 is farthest from the substrate 10, then the surface of the channel layer 31_4 facing away from the substrate 10 is defined as a first surface S1, the surface of the channel layer 31_1 facing the substrate 10 is defined as a second surface S2_1, the surface of the channel layer 31_1 facing away from the substrate 10 is defined as a third surface S3_1, the surface of the channel layer 31_2 facing the substrate 10 is defined as a second surface S2_2, the surface of the channel layer 31_2 facing away from the substrate 10 is defined as a third surface S3_2, the surface of the channel layer 31_3 facing the substrate 10 is defined as a second surface S2_3, the surface of the channel layer 31_3 facing away from the substrate 10 is defined as a third surface S3_3, and the surface of the channel layer 31_4 facing the substrate 10 is defined as a second surface S2_3, the surface of the channel layer 31_3 facing
  • a reference area ZQ is set, and in a direction perpendicular to the plane where the substrate 10 is located (i.e., the second direction F2), the reference area ZQ covers the center of gravity of each channel layer.
  • the channel region of the channel layer has an uncovered area on the second surface that is not covered by the protective layer.
  • the reference area ZQ can be set in the uncovered area of each channel layer.
  • the area corresponding to the reference area ZQ in the first surface S1 i.e., the area covered by the reference area ZQ in the first surface S1 in the second direction F2
  • the area corresponding to the reference area ZQ in the second surfaces S2_1 ⁇ S2_4 i.e., the area covered by the reference area ZQ in the second direction F2
  • the flatness of the first surface S1 at the reference area ZQ is greater than the flatness of the second surfaces S2_1 ⁇ S2_4 of the channel layers 31_1 ⁇ 31_4 at the reference area ZQ.
  • the area corresponding to the reference area ZQ in the first surface S1 (i.e., the area covered by the reference area ZQ in the first surface S1 in the second direction F2) is protected by the protective layer during the process of etching away the sacrificial layer, compared to the area corresponding to the reference area ZQ in the third surfaces S3_1 ⁇ S3_3 (i.e., the area covered by the reference area ZQ in the third surfaces S3_1 ⁇ S3_3 in the second direction F2), and the etching damage can be reduced. Therefore, the flatness of the first surface S1 corresponding to the reference area ZQ is greater than the flatness of the third surfaces S3_1 ⁇ S3_3 of the channel layers 31_1 ⁇ 31_3 corresponding to the reference area ZQ.
  • the protective layer not only the first surface S1 is covered by the protective layer, but also the partial area of the channel region of each channel layer 31_1 to 31_4 protruding from the sacrificial layer (i.e., the corners and sidewalls of the channel region) is covered by the protective layer, so that the sidewalls and corners of the channel region are protected by the protective layer, which can avoid the problem of unsatisfactory channel profile and channel interface due to etching damage and fast etching rate at the corners. Therefore, in the embodiment of the present application, by setting a protective layer, the channel region is protected from damage during the etching process of the sacrificial layer, and a channel region with an ideal profile and a good interface is formed. Thereby, the problem of reduced effective channel width and mobility degradation of the device is improved, and the device performance is improved.
  • the channel layer in the embodiment of the present application is a nanosheet (NS) channel layer. That is to say, the transistor in the embodiment of the present application can be a nanosheet surround gate field effect transistor (NS-GAAFET). Therefore, in the embodiment of the present application, by setting a protective layer, the nanosheet channel layer is protected from damage as much as possible during the etching process of the sacrificial layer, and a nanosheet channel region with an ideal profile and a good interface is formed as much as possible.
  • NS-GAAFET nanosheet surround gate field effect transistor
  • the material of the channel layer may be Si, SiGe, Ge, GeSn, III-V compound semiconductor materials, etc. It should be noted that the NS-GAAFET provided in the embodiment of the present application is universal to all nanosheet structured GAAFET devices and integrated circuits.
  • the semiconductor device further includes: a plurality of inner spacers 90.
  • the gate spacer 50 covers the inner spacer 90.
  • an inner spacer 90 is provided between the first area A1 of the channel layer 31_1 and the substrate 10
  • an inner spacer 90 is provided between the first area A1 of the channel layer 31_1 and the first area A1 of the channel layer 31_2
  • an inner spacer 90 is provided between the first area A1 of the channel layer 31_2 and the first area A1 of the channel layer 31_3
  • an inner spacer 90 is provided between the first area A1 of the channel layer 31_3 and the first area A1 of the channel layer 31_4.
  • an inner sidewall 90 is disposed between the second area A2 of the channel layer 31_1 and the substrate 10
  • an inner sidewall 90 is disposed between the second area A2 of the channel layer 31_1 and the second area A2 of the channel layer 31_2
  • an inner sidewall 90 is disposed between the second area A2 of the channel layer 31_2 and the second area A2 of the channel layer 31_3
  • an inner sidewall 90 is disposed between the second area A2 of the channel layer 31_3 and the second area A2 of the channel layer 31_4.
  • the metal gate can be isolated from the source area 60_1/drain area 60_2, the overlap capacitance between the gate source and the gate drain is reduced, and at the same time, it is ensured that the first area and the second area are not exposed and etched during the channel release process, thereby achieving precise gate length control.
  • the orthographic projection of the gate spacer 50 on the substrate 10 overlaps with the orthographic projection of the inner sidewall 90 on the substrate 10.
  • the orthographic projection of the inner sidewall 90 on the substrate 10 is disposed within the orthographic projection of the gate spacer 50 on the substrate 10.
  • FIG. 2 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application.
  • the manufacturing method may include the following steps:
  • S101 forming a plurality of stacked structures spaced apart from each other on a substrate, and making the stacked structures include sacrificial layers and channel layers stacked alternately.
  • a substrate 10 is provided.
  • the substrate 10 may be bulk silicon, a silicon-on-insulator (SOI) substrate, a strain buffer layer (SRB), a Ge substrate, or other substrates, without limitation herein.
  • SOI silicon-on-insulator
  • SRB strain buffer layer
  • the substrate 10 is used to prepare the wafer portion of an integrated circuit or a semiconductor device.
  • the substrate 10 needs to be highly doped to suppress the formation of the inversion layer channel.
  • an ion distribution with a certain concentration and depth distribution is formed in the substrate 10 to achieve high doping of the substrate 10.
  • diffusion an ion distribution with a certain concentration and depth distribution is formed in the substrate 10 to achieve high doping of the substrate 10.
  • sacrificial layers 01_1 ⁇ 01_4 and channel layers 31_1 ⁇ 31_4 are alternately epitaxially grown on the substrate 10 to form a stacked film layer.
  • a superlattice stack of alternating sacrificial layers 01_1 to 01_4 and channel layers 31_1 to 31_4 is epitaxially grown on a substrate 10, where the top layer is the channel layer 31_4 and the sacrificial layer 01_1 is above the substrate 10, forming a stacked film layer.
  • the present application does not limit the number of channel layers in the stacked film layers, and the number of channel layers may be, for example, 3 to 7.
  • FIG. 4a and FIG. 4b are merely illustrative of a case where four channel layers are used as an example.
  • the present application does not limit the thickness of the channel layer, which may be, for example, 5 nm to 40 nm.
  • the thickness of each channel layer is the same, which may be, for example, one of 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm.
  • the present application does not limit the thickness of the sacrificial layer, which may be 5 nm to 40 nm.
  • the same for example, can be one of 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, and 40nm.
  • the thickness of the sacrificial layer defines the filling thickness of the gate structure 40 .
  • the thickness of the channel layer is similar to or the same as the thickness of the sacrificial layer.
  • the present application does not limit the materials of the sacrificial layer and the channel layer.
  • Different types of sacrificial layer materials may be matched with different channel materials according to the requirements of etching selectivity.
  • the sacrificial layer not only plays a certain supporting role for the channel layer, but also needs to be able to be selectively etched and removed, that is, when etching and removing the sacrificial layer, the material of the sacrificial layer has high selectivity compared to the material of the channel layer.
  • the sacrificial layer sometimes needs to provide stress for the channel layer.
  • the material of the channel layer is Si
  • the corresponding material of the sacrificial layer may be SiGe.
  • the corresponding material of the sacrificial layer is GeSi or Ge.
  • the corresponding material of the sacrificial layer is Ge.
  • the corresponding material of the sacrificial layer is a III-V material.
  • the stacked film layers are patterned to form a plurality of stacked structures spaced apart from each other, and shallow trenches are formed in the substrate.
  • the channel layer in the stacked structure is a nanosheet channel layer.
  • the stacked film layers may be patterned by a spacer image transfer (SIT) process to form a plurality of stacked structures spaced apart from each other, and shallow grooves may be formed in the substrate to form a fin pattern.
  • the stacked structure is the fin, the top layer is the channel layer, the bottom layer is the sacrificial layer, and the bottom is the substrate.
  • the channel layer in the stacked structure is the nanosheet channel layer.
  • the stacked film layers may be patterned by photolithography and etching processes to form a plurality of stacked structures spaced apart from each other, and shallow grooves may be formed in the substrate to form fin patterns.
  • the stacked structure is a fin
  • the top layer is a channel layer
  • the bottom layer is a sacrificial layer
  • the bottom is a substrate.
  • the channel layer in the stacked structure formed is a nanosheet channel layer.
  • the photolithography process may be an extreme ultraviolet (EUV) photolithography process, or a self-aligned multiple photolithography process (such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), etc.).
  • the etching process may be a reactive ion etching (RIE) process.
  • a self-aligned multi-photolithography process is adopted, and the pattern of the photoresist is first transferred to a hard mask (for example, the hard mask may be at least one of silicon oxide, silicon nitride, and a composite layer of silicon oxide and silicon nitride) by an RIE process, and then the stacked film layer and the substrate 10 are etched by an RIE process to form a fin pattern.
  • the fin is a stacked structure, the top layer is a channel layer, the bottom layer is a sacrificial layer, and the bottom is a substrate 10.
  • the fin width determines the width of the final nanosheet channel layer (i.e., the width in the third direction F3), which is about 20nm to 300nm
  • the height of the stacked structure i.e., the height in the second direction F2 is about 60nm to 600nm
  • the height of the stacked structure determines the depth of the shallow groove (i.e., the depth in the second direction F2), and the depth of the shallow groove is about 50nm to 1000nm.
  • the hard mask on the top of the stacked structure can be temporarily retained without additional removal.
  • a dielectric material is filled in the shallow trench to form an isolation structure 20 .
  • a dielectric material may be filled in the shallow trenches between adjacent stacked structures to form a shallow trench isolation (STI) structure.
  • the STI structure is located at the bottom of the stacked structure (i.e., fins), and the upper surface of the STI structure is roughly flush with the lower surface of the sacrificial layer 01_1 (i.e., the surface where the sacrificial layer 01_1 contacts the substrate 10).
  • the preparation process may be adjusted to make the upper surface of the STI structure as flush as possible with the lower surface of the sacrificial layer 01_1.
  • the dielectric material forming the STI structure includes, but is not limited to, silicon dioxide (SiO 2 ), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), and the like.
  • a dielectric material such as SiO 2
  • a thin and high-quality dielectric material such as SiO 2
  • a substrate 10 formed with a shallow groove a substrate 10 formed with a shallow groove
  • a high aspect ratio process High Aspect Ratio Process, HARP
  • SOD spin on dielectric
  • FCVD flowable chemical vapor deposition
  • the dielectric material (such as SiO 2 ) film layer is planarized by a chemical mechanical polishing (CMP) process, and the planarization process is stopped when it is about to be on the channel layer 31_4 of the stacked structure (i.e., the fin), and a certain process window is reserved.
  • CMP chemical mechanical polishing
  • the filled dielectric material (eg SiO 2 ) is etched to a certain depth by an etch-back process, and the etching stops when the lower surface of the sacrificial layer 01_1 of the stacked structure (ie, the fin) (ie, the surface where the sacrificial layer 01_1 contacts the substrate 10 ).
  • the dummy gate structure 80 extends along the third direction F3, and the same dummy gate structure 80 may span across multiple stacked structures (ie, fins).
  • FIG. 7a to 7c only illustrate one stacked structure (ie, fin).
  • the present application does not limit the width of the dummy gate structure (i.e., the width along the first direction F1), but it must comply with the requirements of the technology node set by the International Equipment and System Roadmap (IRDS) and be as short as possible within the scope of suppressing the short channel effect and the lithography process capability.
  • IRDS International Equipment and System Roadmap
  • a dummy gate structure may include a dummy gate film layer and a dummy gate oxide layer located between the dummy gate film layer and the channel layer. That is, the dummy gate structure is a stacked structure formed by the dummy gate oxide layer and the dummy gate film layer, also called a gate stack.
  • the material of the dummy gate film layer is, for example, polysilicon.
  • a dummy gate oxide layer covering the entire substrate is formed on a substrate having a stacked structure. Then, a dummy gate film layer is formed on the dummy gate oxide layer. Then, a photolithography process and an etching process are used to pattern the dummy gate oxide layer and the dummy gate film layer, and the dummy gate oxide layer and the dummy gate film layer covering the area outside the channel area are removed, and the dummy gate oxide layer and the dummy gate film layer covering the channel area are retained to form a dummy gate structure.
  • a suitable process is selected from thermal oxidation process, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), and a thin dummy gate oxide layer and a thick polysilicon dummy gate film layer covering the entire substrate are grown on the substrate 10 formed with the stacked structure to form a dummy gate stack.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a thin dummy gate oxide layer and a thick polysilicon dummy gate film layer covering the entire substrate are grown on the substrate 10 formed with the stacked structure to form a dummy gate stack.
  • a hard mask 81 is formed on the dummy gate stack by using a photolithography process and an etching process to define the pattern of the dummy gate structure 80 through the hard mask 81.
  • an etching process is used to etch the dummy gate stack to pattern the dummy gate stack, remove the dummy gate stack covering the area outside the channel area, retain the dummy gate stack covering the channel area, and form the pattern of the dummy gate structure 80.
  • the hard mask 81 on the top of the dummy gate structure can also be temporarily retained without additional removal.
  • the material of the hard mask 81 may be silicon oxide, silicon nitride layer or silicon oxynitride, or a mixed film layer therebetween.
  • the thickness of the hard mask 81 in the second direction F2 ranges from 100 nm to 1000 nm. Moreover, the thickness value may be different in different stacked film layer height conditions. The thickness of the hard mask 81 in the second direction F2 may be determined according to actual application requirements and is not limited here.
  • gate spacers 50 may be formed on both sides of the dummy gate structure 80 along the first direction F1 to reduce the short channel effect.
  • the hard mask 81 on the top of the dummy gate structure may be temporarily retained without additional removal. In this way, the hard mask 81 may be used as an etching stop layer during the formation of the gate spacers.
  • the present application does not limit the material of the gate spacer 50, and can be, for example, a dielectric material such as silicon nitride (SiNx), silicon oxynitride, silicon oxycarbide, or a material with a low dielectric constant such as an air gap.
  • a dielectric material such as silicon nitride (SiNx), silicon oxynitride, silicon oxycarbide, or a material with a low dielectric constant such as an air gap.
  • the present application does not impose any limitation on the thickness of the gate spacer 50 (ie, the thickness along the first direction F1 ), which may be, for example, 2 nm to 10 nm.
  • the gate spacer 50 material is grown isotropically, and the grown thickness is consistent with the designed thickness of the gate spacer 50. Afterwards, anisotropic etching is performed to remove the gate spacer 50 except for the two sides of the dummy gate structure 80, and the etching stops on the hard mask as an etch stop layer.
  • the stacked structures on both sides of the dummy gate structure are removed to expose the side surfaces of the sacrificial layers 01_1 to 01_4 and the channel layers 31_1 to 31_4 under the gate spacer 50. That is, an etching process is used to remove the stacked structures not covered by the dummy gate structure 80 and the gate spacer 50 to expose the side surfaces of the channel layers 31_1 to 31_4 and the sacrificial layers 01_1 to 01_4 along the first direction F1.
  • a second groove AX2 is formed between adjacent channel layers below the gate spacer 50.
  • the bottom of the second groove AX2 is formed by the sacrificial layer
  • the sidewalls of the second groove AX2 are formed by the adjacent channel layers in the second direction F2
  • the sidewalls of the second groove AX2 are formed by the gate spacer 50 in the third direction F3.
  • the height of the second groove AX2 i.e., the height along the second direction F2 can be equal to the thickness of the sacrificial layer.
  • the exposed sacrificial layers 01_1 to 01_4 are etched by a selective etching process to recess the sacrificial layers 01_1 to 01_4 to form a second groove AX2.
  • the depth of the second groove AX2 i.e., the depth along the first direction F1 ultimately defines the thickness of the inner sidewall 90 (i.e., the thickness along the first direction F1)
  • the height of the second groove AX2 i.e., the height along the second direction F2
  • the height of the second groove AX2 is the thickness of the sacrificial layer and ultimately defines the height of the inner sidewall 90 (i.e., the height along the second direction F2).
  • the height of the inner sidewall 90 is greater than its thickness, so the height of the second groove AX2 is not less than its depth.
  • the ideal shape of the second groove AX2 is a rectangle, and the etching process for etching the sacrificial layer here needs to have a high selectivity ratio for the channel layer material and precise etching control.
  • the shape of the second groove AX2 may not be completely rectangular, and it only needs to roughly meet the above conditions.
  • the present application does not impose any limitation on the thickness of the inner sidewall 90, which may be, for example, 1 nm to 10 nm.
  • the depth along the first direction F1) can be the same as the thickness of the inner sidewall 90 to be formed.
  • the width of the inner sidewall in the extension direction parallel to the channel region is generally not greater than the thickness of the sacrificial layer in the plane perpendicular to the substrate.
  • the width of the inner sidewall can be but not necessarily consistent with the thickness of the gate sidewall.
  • the width of the inner sidewall can be less than the thickness of the gate sidewall.
  • the width of the inner sidewall can be determined according to the requirements of the actual application environment and is not limited here.
  • a dielectric material is filled in the second groove AX2 to form an inner sidewall 90.
  • the width of the inner sidewall 90 in the extension direction parallel to the channel region i.e., the first direction F1 is not greater than the thickness of the sacrificial layer in the direction perpendicular to the plane where the substrate is located (i.e., the second direction F2).
  • the inner sidewall 90 is located at both ends of the sacrificial layer to isolate the metal gate from the source/drain region, reduce the gate-source and gate-drain overlap capacitance, and ensure that the first and second regions are not exposed and etched during the channel release process, thereby achieving precise gate length control.
  • the material selection of the inner sidewall 90 needs to have high etching resistance when the sacrificial layer is etched.
  • the material selection of the inner sidewall 90 also needs to have high selectivity for the channel material. Due to the requirement for low overlap capacitance, a dielectric material with a low dielectric constant (for example, a dielectric material with a dielectric constant not greater than 7) is used as much as possible.
  • the material of the inner sidewall 90 can be a single layer, or a multilayer design with different material combinations can be used as required, which is not limited here.
  • the material of the inner sidewall 90 includes but is not limited to a dielectric material composed of any combination of silicon (Si) and carbon (C), oxygen (O), and nitrogen (N).
  • a deposition process is used to isotropically deposit the dielectric material of the inner sidewall 90, and the deposition process needs to have good filling properties to perfectly fill the second groove AX2.
  • the deposition process includes but is not limited to the ALD process.
  • an etching process is used to etch the deposited inner sidewall 90 material, leaving only the material in the second groove AX2 to form the inner sidewall 90.
  • source and drain regions connected to the channel layer are epitaxially formed on the substrate 10 at both sides of the dummy gate structure.
  • the source region 60_1 and the drain region 60_2 are grown on both sides of the dummy gate structure by using an epitaxial process.
  • the materials of the source region 60_1 and the drain region 60_2 can be designed according to the conductive channel type of the transistor to provide stress and other methods to promote transistor performance, and the materials of the source region 60_1 and the drain region 60_2 are generally similar to the channel layer material and the sacrificial layer material to ensure the effective growth of the source region 60_1 and the drain region 60_2.
  • the materials of the source region 60_1 and the drain region 60_2 include but are not limited to Si, GaAs, GaAsP, SiP or other suitable materials, and doping (such as phosphorus (P), arsenic (As)) is introduced during the epitaxial growth process or non-in-situ doping is performed using an ion implantation process.
  • doping such as phosphorus (P), arsenic (As)
  • the materials of the source region 60_1 and the drain region 60_2 include but are not limited to Si, Ge, SiGe, AlGaAs, boron-doped SiGe or other suitable materials, and boron (B) is introduced by in-situ doping during the epitaxial growth process or ion implantation process is used for non-in-situ doping.
  • the source region 60_1 is disposed in contact with the first region of the channel layers 31_1 to 31_4 so as to be connected to the source region 60_1 and the drain region 60_2 is disposed in contact with the second region of the channel layers 31_1 to 31_4 so as to be connected to the channel layers 31_1 to 31_4.
  • an interlayer insulating layer 70 is deposited on the source/drain regions and the dummy gate structure.
  • the interlayer insulating layer 70 includes an etch stop layer (CESL) and an interlayer dielectric (ILD) layer.
  • the CESL covers the surface of the substrate 10 where the source and drain regions are formed to prevent serious over-etching when etching contact holes (the source region is provided with contact holes for connecting the source region with external signal lines, and the drain region is also provided with contact holes for connecting the drain region with external signal lines).
  • the ILD layer covers the etch stop layer.
  • a thin CESL layer and a thick ILD layer are deposited over the entire structure of the substrate 10 having the source and drain regions formed therein.
  • the pattern of the interlayer insulating layer 70 in Figures 13a to 13c is a composite layer including a thin CESL layer and a thick ILD layer.
  • the material of CESL includes but is not limited to silicon nitride, silicon oxide, and silicon oxynitride.
  • the present application does not limit the thickness of CESL, which is generally thin.
  • the material of the ILD layer includes but is not limited to tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG) and other dielectric materials.
  • TEOS tetraethyl orthosilicate
  • BPSG borophosphosilicate glass
  • FSG fused silica glass
  • PSG phosphosilicate glass
  • BSG boron-doped silica glass
  • other dielectric materials such as boron-doped silica glass (BSG) and other dielectric materials.
  • a suitable process is selected from deposition processes such as ALD and PECVD processes or oxidation processes to form a thinner CESL. Afterwards, a suitable process is selected from deposition processes such as PECVD to overfill a thicker ILD layer, and the height of the overfilled ILD layer is often higher than a certain thickness above the dummy gate structure 80. Afterwards, it is necessary to remove the excess ILD layer material and expose the top of the dummy gate structure 80. A planarization process such as CMP is often used to planarize the overfilled ILD layer and stop when the top of the dummy gate structure 80 is exposed. It should be noted that when the excess ILD layer material is planarized, the dummy gate structure 80 is also removed.
  • deposition processes such as ALD and PECVD processes or oxidation processes to form a thinner CESL.
  • a suitable process is selected from deposition processes such as PECVD to overfill a thicker ILD layer, and the height of the overfilled ILD layer is often higher than a
  • planarization process such as CMP
  • the process stops when the top of the hard mask on the dummy gate structure is exposed. Thereafter, an etching process may be used to remove the hard mask. Thereafter, a planarization process such as CMP is continued to planarize the overfilled ILD layer, and the process stops when the top of the dummy gate structure is exposed.
  • the dummy gate structure adopts a stacked structure of a dummy gate oxide layer and a dummy gate film layer.
  • the materials of the dummy gate oxide layer and the dummy gate film layer need to be selectively etched.
  • tetramethylammonium hydroxide may be used for selective wet etching, or selective dry etching or a combination thereof to remove the material of the dummy gate structure to expose the channel layer and the sacrificial layer at the location covered by the original dummy gate structure.
  • the sacrificial layers 01_1 to 01_4 exposed in the gate opening GK are partially selectively etched to etch a first groove AX1 of a certain depth.
  • the first groove AX1 is formed by adjacent channel layers and sacrificial layers disposed between adjacent channel layers, so that a portion of the channel region of each channel layer protrudes from the sacrificial layer.
  • the bottom of the first groove AX1 is formed by the sacrificial layer, and in the second direction F2, the sidewalls of the first groove AX1 are formed by the adjacent channel layers, and in the first direction F1, the sidewalls of the first groove AX1 are formed by the inner sidewall 90.
  • the height of the first groove AX1 i.e., the height along the second direction F2 can be the thickness of the sacrificial layer.
  • the partial area of the channel layer 31_1 to 31_4 protruding from the sacrificial layer 01_1 to 01_4 has a first width D1.
  • the sacrificial layer 01_1 to 01_4 has a first thickness H1.
  • the present application does not limit the first width D1.
  • the first width D1 can generally be made not greater than the first thickness H1.
  • the first width D1 defines the depth of the first groove AX1 (i.e., the depth along the third direction).
  • the first width D1 may be different, and accordingly, the depth of the first groove AX1 (i.e., the depth along the first direction F1) is also different.
  • the first width D1 is 5nm to 10nm, that is, the depth of the first groove AX1 is 5nm to 10nm.
  • the first width can also be made greater than the first thickness. In practical applications, the first width and the first thickness may be determined according to requirements of the practical application.
  • the sacrificial layer is etched using an atomic layer etching (ALE) process with precise etching control or a dry continuous etching process, and the etching needs to have good selectivity for the channel layer to minimize damage to the channel layer.
  • ALE atomic layer etching
  • a protective initial film layer 100 is deposited on the surfaces of the sacrificial layers 01_1 ⁇ 01_4 and the channel layers 31_1 ⁇ 31_4 in the gate opening GK using a material having a different etching selectivity from the sacrificial layer material and the channel layer material.
  • a deposition process is used to deposit a protective layer.
  • the thickness of the protective layer may be different.
  • the thickness of the protective layer is about half of the thickness of the sacrificial layer.
  • the environmental conditions of different sizes are different.
  • the material of the protective layer should be selected to have high etching selectivity for the sacrificial layer 01_1 ⁇ 01_4 and the channel layer 31_1 ⁇ 31_4 materials.
  • the material of the protective layer should also be different from the material used in the gate sidewall 50, the inner sidewall 90 and the isolation structure 20 to ensure that the protective layer material here can be selectively removed in the following step of removing the protective layer without corroding the gate sidewall 50, the inner sidewall 90 and the isolation structure 20.
  • the material of the protective layer includes but is not limited to a-Si, SiN, SiNO, SiOC and other materials, which can be flexibly selected according to different scenarios.
  • a deposition process is used to form a protective initial film layer.
  • a deposition process with poor conformality can be selected.
  • a vapor deposition process, an atomic layer deposition process, a plasma enhanced chemical vapor deposition process, and a plasma enhanced atomic layer deposition process can be used to utilize the poor conformality of the deposition process to form the following filling method: Referring to Figures 16a to 16c, a protective initial film layer 100 is deposited in the gate opening GK, so that the protective initial film layer 100 covers the surface of the sacrificial layer 01_1 ⁇ 01_4 and the surface of the channel layer 31_1 ⁇ 31_4 in the gate opening GK, and the protective initial film layer 100 closes the open end of the first groove AX1, so as to stop the deposition after the protective initial film layer 100 is enclosed into a cavity in the first groove AX1.
  • the thickness of the protective initial film layer 100 on the surface of the sacrificial layer 01_1 ⁇ 01_4 is less than the thickness of the protective initial film layer 100 on the surface of the channel layer 31_1 ⁇ 31_4. That is to say, the protective layer material inside the first groove AX1 is not filled sufficiently, and the open end of the first groove AX1 is sealed by the protective layer material in advance, resulting in holes in the protective layer inside the first groove AX1, while the protective layer material on the sidewalls, top and corners of the channel layer is filled relatively sufficiently and has a thicker thickness.
  • the protective initial film layer 100 on the surface of the sacrificial layer 01_1 to 01_4 is removed, and the gate opening GK is retained.
  • the protective initial film layer on the surface of the channel layers 31_1 ⁇ 31_4 forms a protective layer 110 .
  • the structure of the protective layer is modified by utilizing the difference in filling inside and outside the first groove AX1.
  • a dry etching process is used to thin the protective initial film layer, so that an opening is formed in the protective initial film layer that closes the open end of the first groove AX1, so as to remove the protective initial film layer on the surface of the sacrificial layer at the bottom end of the first groove AX1, and retain the protective initial film layer on the surface of the channel layer to form a protective layer.
  • a dry etching process with precise etching control is used to ensure that the seal of the first groove AX1 is opened, the protective layer material inside the first groove AX1 (especially the bottom) is etched, and the protective layer material on the sidewalls, top and corners of the channel layer is partially left, forming the profile of the protective layer as shown in FIG. 16d.
  • the profile of the filling and etching of the protective layer includes but is not limited to the profile shown in FIG. 16d.
  • FIG. 16d only illustrates a possible example.
  • the protective layer is deposited and etched to form the shape of the channel region corners, tops and sidewalls of the channel layers 31_1 to 31_4 protected, for example, the protective layer inside the first groove AX1 may have many holes or may be of poor quality.
  • the protective layer is deposited on the sidewalls of the sacrificial layer is acceptable, as long as the bottom of the first groove AX1 is finally formed after the protective layer is etched to expose the sacrificial layer, and the sidewalls, tops and corners of the channel layers 31_1 to 31_4 are protected by the protective layer.
  • this is only an ideal case.
  • the process of removing the protective layer may deviate.
  • the protective initial film layer at the corners of the sacrificial layer and the channel layer is not completely removed, and there is a small amount of residue.
  • the protective initial film layer near the above-mentioned corners of the channel layer is removed, which can also meet the requirements.
  • the surface of the channel layer in the gate opening is coated with the protection layer, including: a selective deposition process may also be used to deposit the protection layer on the surface of the channel layer in the gate opening.
  • an etching operation is performed to etch the sacrificial layer, remove the sacrificial layer in the gate opening GK, and release the channel regions of the channel layers 31_1 to 31_4 .
  • the etching process of the sacrificial layer can be isotropic etching, using an etching process with high etching selectivity for the channel layer material and the protective layer material, and also requires an etching process with etching selectivity for the used gate sidewall 50, inner sidewall 90 and other materials.
  • the channel regions of the channel layers 31_1 to 31_4 have uncovered areas on the second surface that are not covered by the protective layer.
  • the reference area ZQ can be set in the uncovered area of each channel layer.
  • the area corresponding to the reference area ZQ in the first surface S1 i.e., the area covered by the reference area ZQ in the first surface S1 in the second direction F2
  • the flatness of the first surface S1 at the reference area ZQ is greater than the flatness of the second surfaces S2_1 to S2_4 at the reference area ZQ of the channel layers 31_1 to 31_4.
  • the area corresponding to the reference area ZQ in the first surface S1 (i.e., the area covered by the reference area ZQ in the first surface S1 in the second direction F2) is protected by the protective layer during the process of etching away the sacrificial layer, compared to the area corresponding to the reference area ZQ in the third surfaces S3_1 ⁇ S3_3 (i.e., the area covered by the reference area ZQ in the third surfaces S3_1 ⁇ S3_3 in the second direction F2), and the etching damage can be reduced. Therefore, the flatness of the first surface S1 corresponding to the reference area ZQ is greater than the flatness of the third surfaces S3_1 ⁇ S3_3 of the channel layers 31_1 ⁇ 31_3 corresponding to the reference area ZQ.
  • the protective layer not only the first surface S1 is covered by the protective layer, but also the partial area of the channel region of each channel layer 31_1 to 31_4 protruding from the sacrificial layer (i.e., the corners and sidewalls of the channel region) is covered by the protective layer, so that the sidewalls and corners of the channel region are protected by the protective layer, which can avoid the problem of unsatisfactory channel profile and channel interface due to etching damage and fast etching rate at the corners. Therefore, in the embodiment of the present application, by setting a protective layer, the channel region is protected from damage during the etching process of the sacrificial layer, and a channel region with an ideal profile and a good interface is formed. Thereby, the problem of reduced effective channel width and mobility degradation of the device is improved, and the device performance is improved.
  • an etching process is used to remove the protection layer that protects the channel region, so as to expose all the channel regions and form a channel structure 30 .
  • the etching process of the protection layer should adopt an etching process with high etching selectivity to materials such as the channel layers 31_1 to 31_4, the gate sidewalls 50, and the inner sidewalls 90, so as not to damage the channel as much as possible, ensure complete removal of the protection layer material, and ensure effective filling of the subsequent gate structure.
  • a dry etching process may be used to remove the protective layer, and in the dry etching process for removing the protective layer, the etching bias voltage may be set to a range of 0 to 150 V to ensure that the ion bombardment generated in the step of etching to remove the protective layer is small, thereby minimizing the distance between the substrate and the ion bombardment.
  • the first surface of the channel layer farthest from the bottom is etched and damaged, and the flatness of the first surface is ensured to be better than the flatness of the second surface and the third surface as much as possible.
  • wet etching can also be used to remove the protective layer to avoid etching damage on the first surface, and the flatness of the first surface is ensured to be better than the flatness of the second surface and the third surface as much as possible.
  • the gate structure 40 extends along the third direction F3, and the same gate structure 40 may cross the channel region of the channel layer in one or more channel structures 30. Only one channel structure 30 is shown in FIG1a to 1c.
  • the gate structure 40 includes a metal gate 42 and a gate dielectric layer 41 located between the metal gate 42 and the channel layers 31_1 to 31_4. That is, the gate structure 40 is a stacked structure formed by the metal gate 42 and the gate dielectric layer 41.
  • the gate dielectric layer 41 may also cover the surface of the inner sidewall 90 exposed in the gate opening, the surface of the gate sidewall 50 exposed in the gate opening, and the surface of the substrate 10 exposed in the gate opening.
  • a suitable deposition process is selected from deposition processes such as ALD and CVD, and a dielectric material is deposited on the substrate 10 after the protective layer is removed, and a gate dielectric layer is formed on the surface of each channel region and on the sidewalls of the gate spacer 50 in the gate opening GK.
  • a suitable deposition process is selected from deposition processes such as ALD and CVD, and a metal gate is deposited on the substrate 10 formed with the gate dielectric layer, filling the gate opening GK, so that the metal gate covers the gate dielectric layer to surround the channel region of each channel layer 31_1 to 31_4.
  • the dielectric material forming the gate dielectric layer is a dielectric material with a high dielectric constant, which may be a dielectric material with a dielectric constant greater than that of silicon oxide, for example, aluminum oxide ( Al2O3 ), hafnium oxide ( HfO2 ), zirconium oxide ( ZrO2 ), lanthanum oxide ( La2O3 ) and the like.
  • the metal gate is generally a multi-layer structure, which includes but is not limited to a combination of a work function metal (possibly multiple work function metals), a liner layer, a wetting layer, an adhesion layer, a metal conductive layer or a metal silicide, etc.
  • the metal gate includes but is not limited to titanium (Ti), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), etc.
  • the gate structure 40 further includes an interface layer disposed between the gate dielectric layer and the channel layer.
  • the interface layer includes a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride.
  • other methods such as chemical oxidation, thermal oxidation, ALD, CVD, etc. may be used to grow the interface layer, and the process of growing the interface layer may occur before or after the gate dielectric layer is deposited.
  • the present application can complete the preparation process of the nanosheet GAAFET through the above steps.
  • the above embodiments are for better explanation of the present application, but do not limit the present application.
  • FIG. 15 a FIG. 16 a and FIG. 17 a , in order to illustrate the contents of the gate opening, the gate spacer and the interlayer insulating layer are not illustrated.
  • the embodiment of the present application also provides an electronic device, which includes a circuit board (such as a printed circuit board) and any semiconductor device provided in the above embodiment of the present application, and the semiconductor device is connected to the circuit board. Since the principle of solving the problem by the electronic device is similar to that of the above semiconductor device, the implementation of the electronic device can refer to the implementation of the above semiconductor device, and the repeated parts will not be repeated.
  • a circuit board such as a printed circuit board

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Abstract

本申请提供了半导体器件、制备方法以及电子设备，在衬底上形成多个相互间隔排列的堆叠结构，使堆叠结构包括交替堆叠的牺牲层和沟道层，在相邻两个堆叠结构之间的衬底中形成隔离结构；形成横跨各堆叠结构的假栅结构，在假栅结构的两侧依次形成栅侧墙、源漏区以及层间绝缘层，去除假栅结构形成栅极开口，从处于栅极开口中的牺牲层裸露表面开始向内刻蚀牺牲层，将各沟道层的沟道区的部分区域凸出于牺牲层，在处于栅极开口中裸露出的沟道区表面包覆保护层，去除处于栅极开口中的牺牲层，去除保护层，将所有沟道区暴露，在栅极开口中，形成环绕每一个沟道区的栅极结构。通过设置保护层，形成轮廓和界面较完好的沟道区。

Description

半导体器件、制备方法以及电子设备
相关申请的交叉引用
本申请要求在2022年08月31日提交中国专利局、申请号为202211059213.2、申请名称为“半导体器件、制备方法以及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到半导体技术领域，尤其涉及到半导体器件、制备方法以及电子设备。
背景技术
互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)技术是当今集成电路(Integrated Circuit，IC)的主流技术。随着器件尺寸的不断缩小，集成度呈指数增长，电路性能也不断得到改善。但是随着金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)器件的特征尺寸进入到深亚微米以及纳米的范围，短沟效应将对器件性能带来重要影响，与此同时，传统的器件结构以及制备工艺也遇到了新的挑战。为了延续摩尔定律的有效性，新的器件结构如鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)、环绕栅极场效应晶体管(Gate All Around Field-Effect Transistor，GAAFET)等被广泛研究。其中，GAAFET在抑制短沟效应、提高电流控制等方面的优越能力，使得其成为未来MOSFET器件的最有力竞争者之一。
目前GAAFET器件的常用制备方法是：先交替外延生长牺牲层和沟道(Channel)层的堆叠膜层。之后，使用选择性刻蚀技术，去除牺牲层，保留沟道层，从而形成GAAFET。然而，选择性刻蚀技术通常采用干法刻蚀工艺，但是干法刻蚀工艺中会出现离子轰击和尖端放电等现象，容易引起沟道层出现刻蚀损伤和边角处刻蚀速率较快的问题，从而引起沟道轮廓和沟道界面不理想。这样，一方面，降低了有效沟道宽度，另一方面，造成迁移率退化，退化器件性能。
发明内容
本申请实施例提供了一种半导体器件、制备方法以及电子设备，用于改善由于刻蚀损伤和边角处刻蚀速率较快，引起的沟道轮廓和沟道界面不理想的问题。
第一方面，本申请实施例提供了一种半导体器件的制备方法，该制备方法包括：在衬底上形成多个相互间隔排列的堆叠结构，并使堆叠结构包括交替堆叠的牺牲层和沟道层，在相邻两个堆叠结构之间的衬底中形成隔离结构；形成横跨各堆叠结构的假栅结构，并使假栅结构覆盖沟道层的沟道区，在假栅结构的两侧依次形成栅侧墙、源漏区以及层间绝缘层，去除假栅结构形成栅极开口，从处于栅极开口中的牺牲层裸露表面开始向内刻蚀牺牲层，将各沟道层的沟道区的部分区域凸出于牺牲层，在处于栅极开口中裸露出的沟道区表面包覆保护层，去除处于栅极开口中的牺牲层，去除保护层，将所有沟道区暴露，在栅极开口中，形成环绕每一个沟道区的栅极结构。
本申请通过设置保护层，可使距离衬底最远的沟道层的第一表面被保护层覆盖，而每一个沟道层的第二表面有部分区域被牺牲层覆盖但未被保护层覆盖，因此，第一表面中对应基准区域处的区域相比第二表面中对应基准区域处的区域，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面对应基准区域处的平整度大于沟道层的第二表面对应基准区域处的平整度。
以及，通过设置保护层，部分沟道层的第三表面有部分区域被牺牲层覆盖但未被保护层覆盖，因此，第一表面中对应基准区域处的区域相比第三表面中对应基准区域处的区域，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面对应基准区域处的平整度大于沟道层的第三表面对应基准区域处的平整度。
以及，通过设置保护层，不仅第一表面被保护层覆盖，各沟道层的沟道区中凸出于牺牲层设置的部分区域(即沟道区的边角和侧壁)也被保护层覆盖，以通过保护层对沟道区的侧壁和边角处进行保护，可以避免由于刻蚀损伤和边角处刻蚀速率较快，导致沟道轮廓和沟道界面不理想的问题。因此，本申请实施例，通过设置保护层，保护沟道区在牺牲层刻蚀过程中不受损伤，形成理想轮廓和界面完好的沟道区。从而改善器件的有效沟道宽度降低和迁移率退化的问题，提高器件性能。
需要说明的是，形成的栅极结构环绕每一个沟道层的沟道区。可选地，栅极结构包括金属栅极和栅 介质层。金属栅极环绕沟道层的沟道区，且栅介质层设置于金属栅极和沟道层的沟道区之间。也就是说，金属栅极隔着栅介质层环绕沟道层的沟道区。这样通过使金属栅极环绕沟道层的沟道区，实现金属栅极包裹沟道的设置，能实现对沟道的理想控制，形成GAAFET。并且，栅极结构环绕的沟道层为纳米片沟道层，即形成的GAAFET为纳米片GAAFET。
在本申请一个可能的实现方式中，衬底可为体硅(Bulk silicon)，可为绝缘体上硅(Silicon-On-Insulator，SOI)衬底，可为应变缓冲层(Strain Relaxed Buffer，SRB)，Ge衬底等其他衬底，在此不做限制。
需要说明的是，衬底用于制备集成电路或半导体器件的晶圆部分。一般地，为防止最底层的寄生沟道导通，需要对衬底进行高掺杂，以抑制反型层沟道的形成。示例性地，通过对衬底进行离子注入加退火，在衬底中形成一定浓度和深度分布的离子分布，以实现对衬底进行高掺杂。或，采用扩散的方式，在衬底中形成一定浓度和深度分布的离子分布，以实现对衬底进行高掺杂。
在本申请一个可能的实现方式中，为了形成保护层，在处于所述栅极开口中的沟道层表面包覆保护层，包括：
首先，可采用与牺牲层材料和沟道层材料具有高刻蚀选择比的材料，在处于栅极开口中的牺牲层表面和沟道层表面沉积保护初始膜层。
示例性地，采用沉积工艺，进行保护层沉积，对于不同牺牲层厚度的纳米片GAAFET，保护层的厚度的可不同。一般地，保护层的厚度约为牺牲层厚度的一半，不同尺寸环境情况不同，保护层的材料应选择对牺牲层和沟道层材料具有高刻蚀选择性的材料。并且，保护层的材料还应不同于栅侧墙，内侧墙和隔离结构处已采用过的材料，以保证这里的保护层材料在下面去除保护层的步骤中，能够被选择性去除，而不侵蚀栅侧墙，内侧墙和隔离结构。
可选地，保护层的材料包括但不限于a-Si，SiN，SiNO，SiOC等材料，根据不同场景，可灵活选择。
可选地，采用沉积工艺形成保护初始膜层。其中，可选取保形性差的沉积工艺。示例性地，可以采用气相沉积工艺、原子层沉积、等离子体增强化学的气相沉积工艺以及等离子体增强原子层沉积等工艺，以利用沉积工艺保形性差的特点，形成如下形式的填充方式：在栅极开口中沉积保护初始膜层，使保护初始膜层覆盖处于栅极开口中的牺牲层表面和沟道层表面，并在保护初始膜层将第一凹槽的开口端封闭，以在第一凹槽中通过保护初始膜层合围成腔体后停止沉积。其中，牺牲层表面的保护初始膜层的厚度小于沟道层表面的保护初始膜层的厚度。也就是说，第一凹槽内部的保护层材料填充不充分，第一凹槽的开口端提前被保护层材料封口，导致第一凹槽内部的保护层存在孔洞，而沟道层的侧壁，顶部和边角处的保护层材料填充比较充分且厚度较厚。
之后，去除牺牲层表面的保护初始膜层，保留处于栅极开口中的沟道层表面的保护初始膜层，形成保护层。
在一些实施例中，利用第一凹槽内外填充的差异性，对保护层的结构进行修饰。采用干法刻蚀工艺，将保护初始膜层减薄，使封闭第一凹槽的开口端的保护初始膜层形成开口，以去除第一凹槽的底端处的牺牲层表面的保护初始膜层，保留沟道层表面的保护初始膜层，形成保护层。也就是说，采用具有精确的刻蚀控制的干法刻蚀工艺，以保证第一凹槽封口被打开，第一凹槽内部(尤其是底部)的保护层材料被刻蚀，而沟道层的侧壁，顶部和边角处的保护层材料部分剩余。
需要说明的是，保护层的填充和刻蚀的轮廓不限于上述的轮廓，只要通过保护层的沉积和刻蚀，形成沟道层的沟道区边角、顶部以及侧壁被保护的形状即可，比如第一凹槽内部的保护层的孔洞可以具有很多，也可以质量很差，牺牲层侧壁是否沉积保护层均可，只要最终经保护层刻蚀后，形成第一凹槽的底部暴露出牺牲层，沟道层的侧壁、顶部和边角处被保护层保护的轮廓即可。当然，此处也仅是说明的理想情况。在制备工艺中，去除保护层的工艺可能会有所偏差，例如，处于牺牲层与沟道层的边角处的保护初始膜层并未完全去除，有少量残留。又例如，处于沟道层的靠近上述边角处的保护初始膜层被去除，也能满足要求。这些情况均在本专利的保护范围之内。
在本申请一个可能的实现方式中，为了将各沟道层的沟道区的部分区域凸出于牺牲层，可对栅极开口中暴露出的牺牲层进行部分地选择性刻蚀，以刻蚀出一定深度的第一凹槽。该第一凹槽由相邻的沟道层以及设置于相邻的沟道层之间的牺牲层形成，从而将各沟道层的沟道区的部分区域凸出于牺牲层。例如，第一凹槽的底部由牺牲层形成，在第二方向上，第一凹槽的侧壁由相邻沟道层形成，在第一方向上， 第一凹槽的侧壁由内侧墙形成。这样可以使第一凹槽的高度为牺牲层的厚度。
可选地，在平行于衬底所在平面且垂直于沟道区的延伸方向的方向上，沟道层中凸出于牺牲层的部分区域具有第一宽度。在垂直于衬底所在平面的方向上，牺牲层具有第一厚度。本申请对第一宽度不进行限制。示例性地，一般地可以使第一宽度不大于第一厚度。第一宽度定义了第一凹槽的深度，对于不同纳米片沟道层宽度的GAAFET器件，第一宽度可不同，相应地，第一凹槽的深度也不同。可选地，第一宽度为5nm～10nm，即第一凹槽的深度为5nm～10nm。当然，也可以使第一宽度大于第一厚度。在实际应用中，可以根据实际应用的需求确定第一宽度和第一厚度。
以及，牺牲层的刻蚀采用具有精确刻蚀控制的原子层刻蚀工艺(Atomic Layer Etching，ALE)或者干法连续刻蚀工艺，且刻蚀需要对沟道层具有很好的选择性，以尽可能降低对沟道层的损伤。
在本申请一个可能的实现方式中，为了形成保护层，在处于所述栅极开口中的沟道层表面包覆保护层，包括：可采用选择性沉积工艺，在处于栅极开口中的沟道层表面沉积保护层。
可选地，可以采用干法刻蚀工艺去除保护层，并且，在去除保护层的干法刻蚀工艺中，可将刻蚀偏压的范围设置为0～150V，以保证刻蚀去除保护层步骤中产生的离子轰击较小，从而尽可能不对距离衬底最远的沟道层的第一表面产生刻蚀损伤，尽可能的保证第一表面的平整度优于第二表面和第三表面的平整度。当然，也可以采用湿法刻蚀去除保护层，以避免第一表面出现刻蚀损伤，尽可能的保证第一表面的平整度优于第二表面和第三表面的平整度。
在本申请一个可能的实现方式中，为了形成栅侧墙、源漏区以及层间绝缘层，即在假栅结构的侧壁处依次形成栅侧墙、源漏区以及层间绝缘层，包括：
首先，在假栅结构制造完成之后，可在沿第一方向上的假栅结构的两侧形成栅侧墙，以减小短沟道效应。可选地，暂时还可将假栅结构顶部上的硬掩膜保留，不用额外去除。这样可以将硬掩膜作为栅侧墙形成过程中的刻蚀停止层。
本申请对栅侧墙的材料可不做限制，例如可为氮化硅(SiNx)、氮氧化硅、碳氧化硅等介质材料或者气隙等低介电常数的材料。在设置气隙时，不会影响器件的集成，同时有助于降低寄生电容，提高器件性能。
本申请对栅侧墙的厚度可不做限制，例如可为2nm～10nm。
作为具体实施的一个示例，各向同性生长栅侧墙材料，生长的厚度与设计的栅侧墙厚度一致。之后，各向异性刻蚀，去除假栅结构的两侧之外的上述栅侧墙，并且刻蚀停止在上述硬掩膜作为的刻蚀停止层上。
之后，去除假栅结构两侧的堆叠结构，暴露出栅侧墙下方的牺牲层和沟道层的侧面。即采用刻蚀工艺，去除未由假栅结构和栅侧墙覆盖的堆叠结构，暴露出沟道层和牺牲层在沿第一方向上的侧面。
之后，去除栅侧墙下方的至少部分牺牲层，在栅侧墙下方相邻的沟道层之间形成第二凹槽。例如，第二凹槽的底部由牺牲层形成，在第二方向上，第二凹槽的侧壁由相邻沟道层形成，在第三方向上，第二凹槽的侧壁由栅侧墙形成。这样可以使第二凹槽的高度为牺牲层的厚度。
作为具体实施的一个示例，采用选择性刻蚀工艺对暴露出的牺牲层进行刻蚀，以将牺牲层凹进形成第二凹槽。第二凹槽的深度最终定义了内侧墙的厚度，第二凹槽的高度为牺牲层的厚度并最终定义了内侧墙的高度。可选地，内侧墙的高度大于其厚度，因此第二凹槽的高度不小于其深度。理想的第二凹槽的形状为矩形，这里对牺牲层进行刻蚀的刻蚀工艺需要对沟道层材料具有很高的选择比，且具有精确的刻蚀控制。
需要说明的是，在实际应用中，由于制备工艺的因素，第二凹槽的形状可能不能完全是矩形，其仅需大致满足上述条件即可。
并且，本申请对内侧墙的厚度可不做限制，例如可为1nm～10nm。则第二凹槽的深度即可与将要形成的内侧墙的厚度相同。示例性地，内侧墙在平行于沟道区的延伸方向上的宽度不大于牺牲层在垂直于衬底所在平面上的厚度。需要说明的是，在实际应用中，内侧墙的宽度可以但不必须与栅侧墙的厚度一致，例如，内侧墙的宽度可以小于栅侧墙的厚度。在实际应用中，内侧墙的宽度可以根据实际应用环境的需求进行确定，在此不作限定。
之后，在第二凹槽中填充介质材料，形成内侧墙。并使，内侧墙在平行于沟道区的延伸方向上的宽度一般不大于牺牲层沿垂直于衬底所在平面的方向上的厚度。
可选地，设置的内侧墙位于牺牲层的两端，以将金属栅极与源区/漏区隔离，降低栅源和栅漏交叠 电容，同时保证沟道释放过程第一区和第二区不被暴露和刻蚀，从而实现精确的栅长控制。内侧墙的材料选择上，需要在牺牲层刻蚀时具有高抗刻蚀能力，另外内侧墙材料选择上也需要它的刻蚀对沟道材料具有高选择性，由于低交叠电容的需求，尽量采用低介电常数的介质材料(例如，介电常数不大于7的介质材料)。
可选地，内侧墙的材料可以用单层，也可以按照需求采用不同材料组合的多层设计，这里不做限制。例如，内侧墙的材料包括但不限于由硅(Si)与碳(C)、氧(O)、氮(N)任意几种组合而成的介质材料。
作为具体实施的一个示例，采用沉积工艺各向同性沉积内侧墙的介质材料，该沉积工艺需要具有很好的填充性，以完美填充上述第二凹槽。例如，沉积工艺包括但不限于工艺。之后，采用刻蚀工艺，对沉积后的内侧墙材料进行刻蚀，仅保留第二凹槽内的材料，形成内侧墙。
之后，在假栅结构两侧的衬底上外延形成连接沟道层的源漏区。
在一些实施例中，在上述假栅结构两侧采用外延工艺生长源区和漏区。其中，可以根据晶体管的导电沟道类型设计源区和漏区的材料，以提供应力等促进晶体管性能的方法，并且，源区和漏区的材料一般与沟道层材料和牺牲层材料类似，以保证源区和漏区的有效生长。
示例性地，在本申请实施例中的GAAFET为N型晶体管时，源区和漏区的材料包括但不限于Si、GaAs、GaAsP、SiP或其他合适的材料，并在外延生长过程中引入掺杂(如磷(P)、砷(As))或使用离子注入工艺进行非原位掺杂。
示例性地，在本申请实施例中的GAAFET为P型晶体管时，源区和漏区的材料包括但不限于Si、Ge、SiGe、AlGaAs、掺硼SiGe或其他合适的材料，并在外延生长过程中原位掺杂引入硼(B)或离子注入工艺进行非原位掺杂。
之后，在源漏区以及假栅结构上沉积层间绝缘层。
在一些实施例中，层间绝缘层包括刻蚀停止层(Contact Etch Stop Layer，CESL)和层间介质(Inter Layer Dielectrics，ILD)层。其中，CESL覆盖形成有源漏区的衬底10的表面，防止刻蚀接触孔(源区对应设置有接触孔，用于将源区与外部信号线连接，并且，漏区也对应设置有接触孔，用于将漏区与外部信号线连接)时发生严重的过刻。ILD层覆盖在刻蚀停止层的上方。
示例性地，在形成有源漏区的衬底的整个结构上方沉积薄的CESL和厚的ILD层。
可选地，CESL的材料包括但不限于氮化硅、氧化硅、氮氧化硅。并且，本申请对CESL的厚度不作限定，一般厚度较薄。
可选地，ILD层的材料包括但不限于正硅酸四乙酯(TEOS)氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅，如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂硅玻璃(BSG)等介电材料。
作为具体实施的一个示例，从ALD、PECVD工艺等沉积工艺或氧化工艺中选取合适的工艺，形成厚度较薄的CESL。之后，从PECVD等沉积工艺中选取合适的工艺，过填充厚度较厚的ILD层，且过填充后的ILD层的高度常高于假栅结构之上一定厚度。之后，需要去除多余的ILD层材料并暴露出假栅结构的顶部，常采用CMP等平坦化工艺，对过填充后的ILD层进行平坦化处理，并在暴露出假栅结构的顶部时停止。需要说明的是，在对多余的ILD层材料进行平坦化处理时，还去除假栅结构顶部的硬掩膜。或者，采用CMP等平坦化工艺对过填充后的ILD层进行平坦化处理时，在暴露出假栅结构上的硬掩膜的顶部时停止。之后，可以采用刻蚀工艺去除该硬掩膜。之后，继续采用CMP等平坦化工艺对过填充后的ILD层进行平坦化处理，并在暴露出假栅结构的顶部时停止。
在本申请一个可能的实现方式中，为了形成栅极结构，在栅极开口中，形成环绕每一个沟道区的栅极结构，包括：
示例性地，栅极结构沿第三方向延伸，且同一栅极结构可横跨一个或多个沟道结构中沟道层的沟道区。
示例性地，栅极结构包括金属栅极和位于金属栅极与沟道层之间的栅介质层。即，栅极结构为由金属栅极和栅介质层形成的叠层结构。
在一些实施例中，首先，从ALD、CVD等沉积工艺中选取合适的沉积工艺，在去除保护层后的衬底上沉积介电材料，在每一个沟道区表面和栅极开口中栅侧墙的侧壁上形成栅介质层。之后，从ALD、CVD等沉积工艺中选取合适的沉积工艺，在形成有栅介质层的衬底上沉积金属栅极，填充栅极开口， 使金属栅极覆盖栅介质层，以环绕每一个沟道层的沟道区。
可选地，形成栅介质层的介电材料为高介电常数的介电材料，可为大于氧化硅的介电常数的介电材料，例如，为氧化铝(Al2O3)、氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)等材料。
可选地，金属栅极一般为多层结构，该多层结构包含但不限于功函数金属(可能多层功函数金属)、衬垫层、浸润层、粘附层、金属导电层或金属硅化物等组合。例如，金属栅极包含但不限于钛(Ti)、钌(Ru)、钴(Co)，氮化钛(TiN)、钛铝(TiAl)、氮化钽(TaN)、碳化钛铝(TiAlC)、钨(W)等。
在另一些实施例中，为实现更好的栅介质层与沟道区的界面接触，提高载流子迁移率，栅极结构还包括设置于栅介质层和沟道层之间的界面层。示例性地，界面层包括介电材料，诸如，氧化硅、硅酸铪或氮氧化硅等。可选地，可以使用化学氧化、热氧化、ALD、CVD等其他方法来生长界面层，生长界面层的过程可发生在栅介质层沉积之前，也可以发生在栅介质层沉积之后。
在本申请一个可能的实现方式中，为了形成假栅结构，形成横跨各堆叠结构的假栅结构，包括：
示例性地，假栅结构(dummy gate)沿第三方向延伸，且同一假栅结构(dummy gate)可横跨多个堆叠结构(即鳍片)。
需要说明的是，本申请对假栅结构(dummy gate)的宽度(即沿第一方向上的宽度)不作限制，但需符合国际设备和系统路线图(IRDS)制定的技术节点的要求，在抑制短沟道效应和光刻工艺能力范围内尽量做短。
示例性地，对于硅基器件，假栅结构(dummy gate)可包括假栅膜层和位于假栅膜层与沟道层之间的假栅氧化层。即，假栅结构(dummy gate)为由假栅氧化层和假栅膜层形成的叠层结构，又叫栅堆栈(gate stack)。
可选地，假栅膜层的材料例如为多晶硅。
在一些实施例中，首先，在形成有堆叠结构的衬底上形成覆盖整个衬底的假栅氧化层。之后，在假栅氧化层上形成假栅膜层。之后，采用光刻工艺和刻蚀工艺，对假栅氧化层和假栅膜层图案化，去除覆盖沟道区之外区域的假栅氧化层和假栅膜层，保留覆盖沟道区的假栅氧化层和假栅膜层，形成假栅结构。
作为具体实施的一个示例，从热氧化工艺、化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、原子层沉积(Atomic Layer Deposition，ALD)选取合适的工艺，在形成有堆叠结构的衬底上生长覆盖整个衬底的薄的假栅氧化层和厚的多晶硅假栅膜层，形成假栅叠层。之后，采用光刻工艺和刻蚀工艺，在假栅叠层上形成硬掩膜，以通过硬掩膜定义出假栅结构的图形。之后，采用刻蚀工艺，刻蚀假栅叠层，以将假栅叠层图案化，去除覆盖沟道区之外区域的假栅叠层，保留覆盖沟道区的假栅叠层，形成假栅结构的图形。可选地，暂时还可将假栅结构顶部上的硬掩膜保留，不用额外去除。
在本申请一个可能的实现方式中，为了形成堆叠结构，在衬底上形成多个相互间隔排列的堆叠结构，包括：
首先，交替地在衬底上外延生长牺牲层和沟道层，形成堆叠膜层。
在一些实施例中，在衬底上外延生长牺牲层和沟道层交替的多叠层的超晶格叠层，最上层为沟道层，衬底之上为牺牲层，形成堆叠膜层。
示例性地，本申请对堆叠膜层中的沟道层的层数不做限制，例如可为3～7层。
示例性地，本申请对沟道层的厚度不做限制，例如可为5nm～40nm。可选地，每个沟道层的厚度相同，例如可为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm中的一个。
示例性地，本申请对牺牲层的厚度不做限制，例如可为5nm～40nm。可选地，每个牺牲层的厚度相同，例如可为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm中的一个。
示例性地，本申请中，牺牲层的厚度定义了栅极结构40的填充厚度。
示例性地，本申请中，沟道层的厚度和牺牲层的厚度相近或相同。
示例性地，本申请对牺牲层和沟道层的材料不做限制，对于不同沟道材料可能根据刻蚀选择性的需求匹配不同种类的牺牲层材料，牺牲层不仅对沟道层起一定的支撑作用，也需要能够被选择性的刻蚀去除，即在刻蚀去除牺牲层时，牺牲层的材料相比沟道层的材料具有高选择性。而且，牺牲层有时还需要为沟道层提供应力。例如沟道层的材料为Si时，对应的牺牲层的材料可为SiGe。例如沟道层的材料为SiGe时，对应的牺牲层的材料为GeSi或Ge。例如沟道层的材料为GeSn时，对应的牺牲层的材料为Ge。例如沟道层的材料为三五族材料时，对应的牺牲层的材料为三五族材料。
之后，将堆叠膜层图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽；堆叠结构中的沟道层为纳米片沟道层。
在一些实施例中，可采用侧墙转移(Spacer Image Transfer，SIT)工艺，将上述堆叠膜层进行图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽，从而形成鳍片图形。其中，堆叠结构即为鳍片，最上层为沟道层，最下层为牺牲层，底部为衬底。形成的堆叠结构中的沟道层即为纳米片沟道层。
在另一些实施例中，也可采用光刻工艺和刻蚀工艺，将上述堆叠膜层进行图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽，从而形成鳍片图形。其中，堆叠结构即为鳍片，最上层为沟道层，最下层为牺牲层，底部为衬底。形成的堆叠结构中的沟道层即为纳米片沟道层。可选地，光刻工艺可以采用极紫外(Extreme Ultra Violet，EUV)光刻工艺，也可以采用自对准多重光刻工艺(如自对准双重图形技术(Self-Aligned Double Patterning，SADP)、自对准四重图形技术(Self-Aligned Quadruple Pattern，SAQP)等)。刻蚀工艺可以采用反应离子刻蚀(Reactive Ion Etching，RIE)工艺。
作为具体实施的一个示例，采用自对准多重光刻工艺，先通过RIE工艺把光刻胶的图形转移到硬掩膜(例如，该硬掩膜可为氧化硅，氮化硅，氧化硅与氮化硅复合层中的至少一种)上，然后通过RIE工艺，刻蚀堆叠膜层和衬底，形成鳍片图形。该鳍片即为堆叠结构，最上层为沟道层，最下层为牺牲层，底部为衬底。并且，鳍片宽度决定了最终的纳米片沟道层的宽度，其宽度约为20nm～300nm，堆叠结构的高度约为60nm～600nm，堆叠结构高度决定了浅沟槽的深度，浅沟槽的深度约为50nm～1000nm。另外，堆叠结构顶部的硬掩膜可以暂时保留，无需额外去除。
在本申请一个可能的实现方式中，为了形成隔离结构，在相邻两个堆叠结构之间的衬底中形成隔离结构，包括：在浅沟槽中填充介电材料，形成隔离结构。
在一些实施例中，为隔离相邻晶体管的堆叠结构(即鳍片)，可在相邻堆叠结构之间的浅沟槽中填充介电材料，形成浅槽隔离(Shallow Trench Isolation，STI)结构。STI结构位于堆叠结构(即鳍片)的底部，且STI结构的上表面与牺牲层下表面(即牺牲层和衬底接触的表面)大致齐平。当然，可以调整制备工艺的参数，使STI结构的上表面与上述牺牲层下表面尽可能齐平。
可选地，形成STI结构的介电材料包括但不限于二氧化硅(SiO2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
作为具体实施的一个示例，采用介电材料(如SiO2)，在形成有浅沟槽的衬底上沉积薄且质量高的介电材料(如SiO2)膜层，之后，采用高深宽比工艺(High Aspect Ratio Process，HARP)或旋转涂覆(Spin On Dielectric，SOD)工艺或流体化学气相沉积(Flowable Chemical Vapor Deposition，FCVD)工艺，采用介电材料(如SiO2)，过填充厚的介电材料(如SiO2)膜层。之后，通过化学机械抛光(Chemical Mechanical Polishing，CMP)工艺对上述介电材料(如SiO2)膜层进行平坦化处理，在将要平坦化处理至堆叠结构(即鳍片)的沟道层上时停止，并预留一定的工艺窗口。之后，通过回刻工艺将填充的介电材料(如SiO2)刻蚀一定深度，并在刻蚀至堆叠结构(即鳍片)的牺牲层的下表面(即牺牲层和衬底接触的表面)时停止。
第二方面，本申请实施例还提供了一种半导体器件，该半导体器件采用上述制备方法形成。该半导体器件包括：衬底，以及设置于衬底上的一个或多个晶体管。晶体管包括设置于衬底上的沟道结构、设置于衬底上的栅极结构、设置于栅极结构两侧的栅侧墙、设置于栅极结构两侧的源漏区以及设置于源漏区上的层间绝缘层。其中，沟道结构可以包括层叠设置于衬底上的多个沟道层。以及，相邻的沟道层之间并未直接接触，而是设置有栅极结构。沟道层和衬底之间并未直接接触，而是设置有栅极结构。
示例性地，沟道层可以沿第一方向延伸设置，沟道层可以沿第二方向排列设置。栅极结构可以沿第三方向延伸设置。其中，第一方向、第二方向以及第三方向两两垂直。
示例性地，栅极结构环绕每一个沟道层的沟道区。可选地，栅极结构包括金属栅极和栅介质层。金属栅极环绕沟道层的沟道区，且栅介质层设置于金属栅极和沟道层的沟道区之间。也就是说，金属栅极隔着栅介质层环绕沟道层的沟道区。这样通过使金属栅极环绕沟道层的沟道区，实现金属栅极包裹沟道的设置，能实现对沟道的理想控制，形成GAAFET。
示例性地，沟道层具有第一区和第二区，以及位于第一区和第二区之间的沟道区。并且，沟道层中的第一区在衬底的正投影可以重叠，沟道层中的第二区在衬底的正投影可以重叠，沟道层中的沟道区在衬底的正投影可以重叠。以及，栅侧墙在衬底的正投影覆盖沟道层中的第一区和第二区在衬底的正投影。 例如，栅侧墙在衬底的正投影覆盖可以与沟道层中的第一区和第二区在衬底的正投影重叠，栅极结构在衬底的正投影覆盖沟道层的沟道区在衬底的正投影。并且，源区设置于沟道层的第一区背离沟道区的一侧，且与沟道层的第一区接触，这样可以将源区作为传输电信号的源电极。并且，漏区设置于沟道层的第二区背离沟道区的一侧，且与沟道层的第二区接触，这样可以将漏区作为传输电信号的漏电极。
需要说明的是，在实际工艺过程中，由于工艺条件的限制或其他因素，上述重叠并不能完全重叠，可能会有一些偏差，因此上述重叠关系只要大致满足上述条件即可，均属于本申请的保护范围。例如，上述重叠可以是在误差允许范围之内所允许的重叠。
在本申请提供的一些实施例中，半导体器件还可以包括设置于相邻两个沟道结构之间的衬底中的隔离结构。其中，衬底具有浅沟槽隔离区，以定义出沟道结构在衬底上覆盖的区域，隔离结构设置于浅沟槽隔离区中，形成浅沟槽隔离(Shallow trench isolation，STI)结构。这样，通过隔离结构隔离不同晶体管的沟道结构在衬底上所在的区域。
在本申请提供的一些实施例中，沟道层层叠设置于衬底上，将距离衬底最远的沟道层背离衬底一侧的表面定义为第一表面，将任一个沟道层面向衬底一侧的表面定义为第二表面，将除距离衬底最远的沟道层之外的其余沟道层背离衬底一侧的表面定义为第三表面。其中，设置一个基准区域，在垂直于衬底所在平面的方向上，该基准区域覆盖每一个沟道层的重心。例如，在上述制备过程中，沟道层的沟道区在第二表面具有未被保护层覆盖的未覆盖区域，在垂直于衬底所在平面的方向上，基准区域可以设置于每一个沟道层的未覆盖区域内。由于，在上述制备过程中，第一表面被保护层覆盖，而第二表面有部分区域被牺牲层覆盖但未被保护层覆盖，因此，第一表面中对应基准区域处的区域相比第二表面中对应基准区域处的区域，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面对应基准区域处的平整度大于沟道层的第二表面对应基准区域处的平整度。同理，第一表面对应基准区域处的平整度大于沟道层的第三表面对应基准区域处的平整度。
以及，在工艺制备过程中，不仅第一表面被保护层覆盖，各沟道层的沟道区中凸出于牺牲层设置的部分区域(即沟道区的边角和侧壁)也被保护层覆盖，以通过保护层对沟道区的侧壁和边角处进行保护，可以避免由于刻蚀损伤和边角处刻蚀速率较快，导致沟道轮廓和沟道界面不理想的问题。因此，本申请实施例，通过设置保护层，保护沟道区在牺牲层刻蚀过程中不受损伤，形成理想轮廓和界面完好的沟道区。从而改善器件的有效沟道宽度降低和迁移率退化的问题，提高器件性能。
本申请实施例中的沟道层为纳米片(Nano Sheet，NS)沟道层。也就是说，本申请实施例中的晶体管可以为纳米片环绕栅极场效应晶体管(NS-GAAFET)。因此，本申请实施例，通过设置保护层，保护纳米片沟道层在牺牲层刻蚀过程中不受损伤，形成理想轮廓和界面完好的纳米片沟道区。
示例性地，沟道层的材料可以为Si、SiGe、Ge、GeSn、III-V化合物半导体材料等。需要说明的是，本申请实施例提供的NS-GAAFET，对所有纳米片结构的GAAFET的器件和集成电路具有普适性。
在本申请提供的一些实施例中，半导体器件还包括：多个内侧墙(Inner Spacer)。其中，在垂直于衬底的方向上，栅侧墙覆盖内侧墙。并且，沟道层的第一区和衬底之间设置一个内侧墙，每相邻沟道层的第一区之间设置一个内侧墙。以及，沟道层的第二区和衬底之间设置一个内侧墙，每相邻沟道层的第二区之间设置一个内侧墙。本申请实施例中，通过设置内侧墙，可将金属栅极与源区/漏区隔离，降低栅源和栅漏之间的交叠电容，同时保证沟道释放过程中，第一区和第二区不被暴露和刻蚀，从而实现精确的栅长控制。
可选地，栅侧墙在衬底的正投影与内侧墙在衬底的正投影重叠。或者，内侧墙在衬底的正投影设置于栅侧墙在衬底的正投影内。
第三方面，本申请实施例还提供了一种电子设备，该电子设备可以为智能手机、智能电视、笔记本电脑等设备。该电子设备可以包括：电路板和半导体器件，并且该半导体器件与电路板连接。其中，该半导体器件可以为如采用第一方面或第一方面的各种实施方式制备的半导体器件，或者该半导体器件也可以为如第二方面或第二方面的各种实施方式的半导体器件。由于上述半导体器件中的晶体管的性能较好，因而，包括上述半导体器件的电子设备的性能也较好。以及，该电子设备解决问题的原理与前述半导体器件相似，因此该电子设备的实施可以参照前述半导体器件的实施，重复之处不再赘述。
附图说明
图1a为本申请实施例提供的一种半导体器件的结构示意图；
图1b为图1a所示的结构示意图中沿AA’方向上的一种剖视结构示意图；
图1c为图1a所示的结构示意图中沿BB’方向上的另一种剖视结构示意图；
图1d为图1a所示的半导体器件中的一个沟道层的俯视结构示意图；
图2为本申请实施例提供的一种半导体器件的制备方法的流程示意图；
图3为本申请实施例提供的一种制备半导体器件的过程的结构示意图；
图4a为本申请实施例提供的另一种制备半导体器件的过程的结构示意图；
图4b为图4a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图5a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图5b为图5a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图5c为图5a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图6a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图6b为图6a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图6c为图6a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图7a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图7b为图7a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图7c为图7a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图8a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图8b为图8a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图8c为图8a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图9a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图9b为图9a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图9c为图9a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图10a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图10b为图10a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图10c为图10a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图11a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图11b为图11a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图11c为图11a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图12a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图12b为图12a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图12c为图12a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图13a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图13b为图13a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图13c为图13a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图14a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图14b为图14a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图14c为图14a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图15a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图15b为图15a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图15c为图15a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图16a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图16b为图16a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图16c为图16a所示的结构示意图中沿BB’方向上的剖视结构示意图；
图16d为对应图16a所示的结构示意图中沿BB’方向上形成保护层后的剖视结构示意图；
图16e为对应图16a所示的结构示意图中沿BB’方向上的去除牺牲层后的剖视结构示意图；
图17a为本申请实施例提供的又一种制备半导体器件的过程的结构示意图；
图17b为图17a所示的结构示意图中沿AA’方向上的剖视结构示意图；
图17c为图17a所示的结构示意图中沿BB’方向上的剖视结构示意图。
附图标记：
01_1、01_2、01_3、01_4-牺牲层；10-衬底；20-隔离结构；30-沟道结构；31_1、31_2、31_3、31_4-
沟道层；40-栅极结构；41-栅介质层；42-金属栅极；50-栅侧墙；60_1-源区；60_2-漏区；70-层间绝缘层；80-假栅结构；81-硬掩膜；90-内侧墙；100-保护初始膜层；110-保护层；F1-第一方向；F2-第二方向；F3-第三方向；D1-第一宽度；H1-第一厚度；GK-栅极开口；AX1-第一凹槽；AX2-第二凹槽；S-第一区；D-第二区；G-沟道区；ZQ-基准区域；S1-第一表面；S2_1、S2_2、S2_3、S2_4-第二表面。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
需要指出的是，本申请实施例中“连接”指的是电连接，两个电学元件连接可以是两个电学元件之间的直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元件间接连接，例如A与B连接，也可以是A与C直接连接，C与B直接连接，A与B之间通过C实现了连接。
并且，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然而描述是以说明本申请的一般原则为目的，并非用以限定本申请的范围。
为了方便理解本申请实施例提供的半导体器件、制备方法及电子设备，下面首先介绍一下其应用场景。
本申请实施例提供的晶体管，由于栅极结构包裹沟道的设置能实现对沟道的理想控制，形成GAAFET，在该GAAFET应用于半导体器件中时，可以提高半导体器件的性能。并且，本申请实施例提供的半导体器件可以被广泛应用在各种电子设备中，例如可以应用于具有逻辑器件或存储器件等的电子设备中。示例性地，该电子设备可以为智能手机、智能电视、笔记本电脑、掌上电脑(personal digital assistant，PDA)、具备无线通讯功能的可穿戴设备(如智能手表、智能眼镜、智能手环)、车载设备或数据中心等。应注意的是，本申请实施例提出的半导体器件旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
参照图1a至图1d，图1a示出了本申请一种实施例提供的半导体器件的结构示意图，图1b示出了本申请的图1a中沿AA’方向上的剖视结构示意图，图1c示出了本申请的图1a中沿BB’方向上的剖视结构示意图，图1d示出了本申请的图1a中的一个沟道层(如31_4)的俯视结构示意图。本申请实施例中的半导体器件可以具有一个或多个晶体管，该晶体管具有沟道结构30，沟道结构30包括层叠且间隔设置的多个沟道层。例如，沟道结构30中的沟道层的数量可以设置3～7层。当然，在实际应用中，沟道结构30中沟道层设置的数量，可以根据实际应用环境的需求进行确定，在此不作限定。
图1a至图1c中仅是以一个晶体管中的沟道结构30具有的4个沟道层31_1～31_4为例进行示意。
参照图1a至图1c，在本申请提供的一些实施例中，半导体器件可以包括衬底10以及设置于衬底10上的晶体管。晶体管包括：设置于衬底10上的沟道结构30、设置于衬底10上的栅极结构40、设置于栅极结构40两侧的栅侧墙50、设置于栅极结构40两侧的源漏区(如源区60_1、漏区60_2)以及设 置于源漏区(如源区60_1、漏区60_2)上的层间绝缘层70。其中，沟道结构30可以包括层叠设置于衬底10上的沟道层31_1～31_4，沟道层31_1相比其他沟道层31_2～31_4距离衬底10最近，沟道层31_2设置于沟道层31_1背离衬底10的一侧，沟道层31_3设置于沟道层31_2背离衬底10的一侧，沟道层31_4设置于沟道层31_2背离衬底10的一侧。以及，沟道层31_1与衬底10之间并未直接接触，而是设置有栅极结构40，沟道层31_1与沟道层31_2之间并未直接接触，而是设置有栅极结构40。沟道层31_2与沟道层31_3之间并未直接接触，而是设置有栅极结构40。沟道层31_3与沟道层31_4之间并未直接接触，而是设置有栅极结构40。
示例性地，参照图1a至图1c，沟道层31_1～31_4可以沿第一方向F1延伸设置，沟道层31_1～31_4可以沿第二方向F2排列设置。栅极结构40可以沿第三方向F3延伸设置。其中，第一方向F1、第二方向F2以及第三方向F3两两垂直。
示例性地，参照图1a至图1c，栅极结构40环绕每一个沟道层31_1～31_4的沟道区。可选地，栅极结构40包括金属栅极42和栅介质层41。金属栅极42环绕沟道层31_1～31_4的沟道区G，且栅介质层41设置于金属栅极42和沟道层31_1～31_4的沟道区G之间。也就是说，金属栅极42隔着栅介质层41环绕沟道层31_1～31_4的沟道区G。这样通过使金属栅极42环绕沟道层31_1～31_4的沟道区G，实现金属栅极42包裹沟道的设置，能实现对沟道的理想控制，形成GAAFET。
示例性地，参照图1a至图1c，沟道层31_1～31_4具有第一区A1和第二区A2，以及位于第一区A1和第二区A2之间的沟道区G。并且，沟道层31_1～31_4中的第一区A1在衬底10的正投影可以重叠，沟道层31_1～31_4中的第二区A2在衬底10的正投影可以重叠，沟道层31_1～31_4中的沟道区G在衬底10的正投影可以重叠。以及，栅侧墙50在衬底10的正投影覆盖沟道层31_1～31_4中的第一区A1和第二区A2在衬底10的正投影。例如，栅侧墙50在衬底10的正投影覆盖可以与沟道层31_1～31_4中的第一区A1和第二区A2在衬底10的正投影重叠，栅极结构40在衬底10的正投影覆盖沟道层31_1～31_4的沟道区G在衬底10的正投影。并且，源区60_1设置于沟道层31_1～31_4的第一区A1背离沟道区G的一侧，且与沟道层31_1～31_4的第一区A1接触，这样可以将源区60_1作为传输电信号的源电极。并且，漏区60_2设置于沟道层31_1～31_4的第二区A2背离沟道区G的一侧，且与沟道层31_1～31_4的第二区A2接触，这样可以将漏区60_2作为传输电信号的漏电极。
需要说明的是，在实际工艺过程中，由于工艺条件的限制或其他因素，上述重叠并不能完全重叠，可能会有一些偏差，因此上述重叠关系只要大致满足上述条件即可，均属于本申请的保护范围。例如，上述重叠可以是在误差允许范围之内所允许的重叠。
参照图1a与图1c，在本申请提供的一些实施例中，半导体器件还可以包括设置于相邻两个沟道结构30之间的衬底10中的隔离结构20。其中，衬底10具有浅沟槽隔离区，以定义出沟道结构30在衬底10上覆盖的区域，隔离结构20设置于浅沟槽隔离区中，形成浅沟槽隔离(Shallow trench isolation，STI)结构。这样，通过隔离结构20隔离不同晶体管的沟道结构30在衬底10上所在的区域。
参照图1b至图1d，在本申请提供的一些实施例中，沟道层31_1～31_4层叠设置于衬底10上，则沟道层31_1距离衬底10最近，沟道层31_4距离衬底10最远，则将沟道层31_4背离衬底10一侧的表面定义为第一表面S1，将沟道层31_1面向衬底10一侧的表面定义为第二表面S2_1，将沟道层31_1背离衬底10一侧的表面定义为第三表面S3_1，将沟道层31_2面向衬底10一侧的表面定义为第二表面S2_2，将沟道层31_2背离衬底10一侧的表面定义为第三表面S3_2，将沟道层31_3面向衬底10一侧的表面定义为第二表面S2_3，将沟道层31_3背离衬底10一侧的表面定义为第三表面S3_3，将沟道层31_4面向衬底10一侧的表面定义为第二表面S2_4。其中，设置一个基准区域ZQ，在垂直于衬底10所在平面的方向(即第二方向F2)上，该基准区域ZQ覆盖每一个沟道层的重心。例如，在工艺制备过程中，沟道层的沟道区在第二表面具有未被保护层覆盖的未覆盖区域，在垂直于衬底10所在平面的方向上，基准区域ZQ可以设置于每一个沟道层的未覆盖区域内。由于，在工艺制备过程中，第一表面S1被保护层覆盖，而第二表面S2_1～S2_4有部分区域被牺牲层覆盖但未被保护层覆盖，因此，第一表面S1中对应基准区域ZQ处的区域(即在第二方向F2上，第一表面S1中被基准区域ZQ覆盖的区域)相比第二表面S2_1～S2_4中对应基准区域ZQ处的区域(即在第二方向F2上，第二表面S2_1～S2_4中被基准区域ZQ覆盖的区域)，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面S1对应基准区域ZQ处的平整度大于沟道层31_1～31_4的第二表面S2_1～S2_4对应基准区域ZQ处的平整度。
同理，第一表面S1中对应基准区域ZQ处的区域(即在第二方向F2上，第一表面S1中被基准区域ZQ覆盖的区域)相比第三表面S3_1～S3_3中对应基准区域ZQ处的区域(即在第二方向F2上，第三表面S3_1～S3_3中被基准区域ZQ覆盖的区域)，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面S1对应基准区域ZQ处的平整度大于沟道层31_1～31_3的第三表面S3_1～S3_3对应基准区域ZQ处的平整度。
以及，在工艺制备过程中，不仅第一表面S1被保护层覆盖，各沟道层31_1～31_4的沟道区中凸出于牺牲层设置的部分区域(即沟道区的边角和侧壁)也被保护层覆盖，以通过保护层对沟道区的侧壁和边角处进行保护，可以避免由于刻蚀损伤和边角处刻蚀速率较快，导致沟道轮廓和沟道界面不理想的问题。因此，本申请实施例，通过设置保护层，保护沟道区在牺牲层刻蚀过程中不受损伤，形成理想轮廓和界面完好的沟道区。从而改善器件的有效沟道宽度降低和迁移率退化的问题，提高器件性能。
参照图1a至图1d，本申请实施例中的沟道层为纳米片(Nano Sheet，NS)沟道层。也就是说，本申请实施例中的晶体管可以为纳米片环绕栅极场效应晶体管(NS-GAAFET)。因此，本申请实施例，通过设置保护层，保护纳米片沟道层在牺牲层刻蚀过程中尽可能不受损伤，尽可能形成理想轮廓和界面完好的纳米片沟道区。
示例性地，沟道层的材料可以为Si、SiGe、Ge、GeSn、III-V化合物半导体材料等。需要说明的是，本申请实施例提供的NS-GAAFET，对所有纳米片结构的GAAFET的器件和集成电路具有普适性。
参照图1a与图1b，在本申请提供的一些实施例中，半导体器件还包括：多个内侧墙90(Inner Spacer)。其中，在垂直于衬底10的方向(即第二方向F2)上，栅侧墙50覆盖内侧墙90。并且，沟道层31_1的第一区A1和衬底10之间设置一个内侧墙90，沟道层31_1的第一区A1和沟道层31_2的第一区A1之间设置一个内侧墙90，沟道层31_2的第一区A1和沟道层31_3的第一区A1之间设置一个内侧墙90，沟道层31_3的第一区A1和沟道层31_4的第一区A1之间设置一个内侧墙90。以及，沟道层31_1的第二区A2和衬底10之间设置一个内侧墙90，沟道层31_1的第二区A2和沟道层31_2的第二区A2之间设置一个内侧墙90，沟道层31_2的第二区A2和沟道层31_3的第二区A2之间设置一个内侧墙90，沟道层31_3的第二区A2和沟道层31_4的第二区A2之间设置一个内侧墙90。本申请实施例中，通过设置内侧墙90，可将金属栅极与源区60_1/漏区60_2隔离，降低栅源和栅漏之间的交叠电容，同时保证沟道释放过程中，第一区和第二区不被暴露和刻蚀，从而实现精确的栅长控制。
可选地，栅侧墙50在衬底10的正投影与内侧墙90在衬底10的正投影重叠。或者，内侧墙90在衬底10的正投影设置于栅侧墙50在衬底10的正投影内。
参照图2，图2为本申请一种实施例提供的半导体器件的制备方法的流程示意图。在该制备方法中，可以包括以下步骤：
S101、在衬底上形成多个相互间隔排列的堆叠结构。并使堆叠结构包括交替堆叠的牺牲层和沟道层。
首先，参照图3，提供一衬底10。
在一些实施例中，衬底10可为体硅(Bulk silicon)，可为绝缘体上硅(Silicon-On-Insulator，SOI)衬底，可为应变缓冲层(Strain Relaxed Buffer，SRB)，Ge衬底等其他衬底，在此不做限制。
需要说明的是，衬底10用于制备集成电路或半导体器件的晶圆部分。一般地，为防止最底层的寄生沟道导通，需要对衬底10进行高掺杂，以抑制反型层沟道的形成。示例性地，通过对衬底10进行离子注入加退火，在衬底10中形成一定浓度和深度分布的离子分布，以实现对衬底10进行高掺杂。或，采用扩散的方式，在衬底10中形成一定浓度和深度分布的离子分布，以实现对衬底10进行高掺杂。
之后，参照图4a与图4b，交替地在衬底10上外延生长牺牲层01_1～01_4和沟道层31_1～31_4，形成堆叠膜层。
参照图4a与图4b，在一些实施例中，在衬底10上外延生长牺牲层01_1～01_4和沟道层31_1～31_4交替的多叠层的超晶格叠层，最上层为沟道层31_4，衬底10之上为牺牲层01_1，形成堆叠膜层。
示例性地，本申请对堆叠膜层中的沟道层的层数不做限制，例如可为3～7层。图4a与图4b仅是以4层沟道层为例进行示意。
示例性地，本申请对沟道层的厚度不做限制，例如可为5nm～40nm。可选地，每个沟道层的厚度相同，例如可为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm中的一个。
示例性地，本申请对牺牲层的厚度不做限制，例如可为5nm～40nm。可选地，每个牺牲层的厚度相 同，例如可为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm中的一个。
示例性地，本申请中，牺牲层的厚度定义了栅极结构40的填充厚度。
示例性地，本申请中，沟道层的厚度和牺牲层的厚度相近或相同。
示例性地，本申请对牺牲层和沟道层的材料不做限制，对于不同沟道材料可能根据刻蚀选择性的需求匹配不同种类的牺牲层材料，牺牲层不仅对沟道层起一定的支撑作用，也需要能够被选择性的刻蚀去除，即在刻蚀去除牺牲层时，牺牲层的材料相比沟道层的材料具有高选择性。而且，牺牲层有时还需要为沟道层提供应力。例如沟道层的材料为Si时，对应的牺牲层的材料可为SiGe。例如沟道层的材料为SiGe时，对应的牺牲层的材料为GeSi或Ge。例如沟道层的材料为GeSn时，对应的牺牲层的材料为Ge。例如沟道层的材料为三五族材料时，对应的牺牲层的材料为三五族材料。
之后，参照图5a至图5c，将堆叠膜层图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽。堆叠结构中的沟道层为纳米片沟道层。
在一些实施例中，可采用侧墙转移(Spacer Image Transfer，SIT)工艺，将上述堆叠膜层进行图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽，从而形成鳍片图形。其中，堆叠结构即为鳍片，最上层为沟道层，最下层为牺牲层，底部为衬底。形成的堆叠结构中的沟道层即为纳米片沟道层。
在另一些实施例中，也可采用光刻工艺和刻蚀工艺，将上述堆叠膜层进行图案化，形成多个相互间隔排列的堆叠结构，并在衬底中形成浅沟槽，从而形成鳍片图形。其中，堆叠结构即为鳍片，最上层为沟道层，最下层为牺牲层，底部为衬底。形成的堆叠结构中的沟道层即为纳米片沟道层。可选地，光刻工艺可以采用极紫外(Extreme Ultra Violet，EUV)光刻工艺，也可以采用自对准多重光刻工艺(如自对准双重图形技术(Self-Aligned Double Patterning，SADP)、自对准四重图形技术(Self-Aligned Quadruple Pattern，SAQP)等)。刻蚀工艺可以采用反应离子刻蚀(Reactive Ion Etching，RIE)工艺。
作为具体实施的一个示例，参照图5a至图5c，采用自对准多重光刻工艺，先通过RIE工艺把光刻胶的图形转移到硬掩膜(例如，该硬掩膜可为氧化硅，氮化硅，氧化硅与氮化硅复合层中的至少一种)上，然后通过RIE工艺，刻蚀堆叠膜层和衬底10，形成鳍片图形。该鳍片即为堆叠结构，最上层为沟道层，最下层为牺牲层，底部为衬底10。并且，鳍片宽度(即在第三方向F3上的宽度)决定了最终的纳米片沟道层的宽度(即在第三方向F3上的宽度)，其宽度约为20nm～300nm，堆叠结构的高度(即在第二方向F2上的高度)约为60nm～600nm，堆叠结构高度决定了浅沟槽的深度(即在第二方向F2上的深度)，浅沟槽的深度约为50nm～1000nm。另外，堆叠结构顶部的硬掩膜可以暂时保留，无需额外去除。
S102、在相邻两个堆叠结构之间的衬底中形成隔离结构。
参照图6a至图6c，在浅沟槽中填充介电材料，形成隔离结构20。
在一些实施例中，为隔离相邻晶体管的堆叠结构(即鳍片)，可在相邻堆叠结构之间的浅沟槽中填充介电材料，形成浅槽隔离(Shallow Trench Isolation，STI)结构。STI结构位于堆叠结构(即鳍片)的底部，且STI结构的上表面与牺牲层01_1下表面(即牺牲层01_1和衬底10接触的表面)大致齐平。当然，可以调整制备工艺，使STI结构的上表面与牺牲层01_1下表面尽可能齐平。
可选地，形成STI结构的介电材料包括但不限于二氧化硅(SiO2)、氮氧化硅(SiNO)、碳氧化硅(SiCO)、氮化硅(SiNx)等。
作为具体实施的一个示例，参照图6a至图6c，采用介电材料(如SiO2)，在形成有浅沟槽的衬底10上沉积薄且质量高的介电材料(如SiO2)膜层，之后，采用高深宽比工艺(High Aspect Ratio Process，HARP)或旋转涂覆(Spin On Dielectric，SOD)工艺或流体化学气相沉积(Flowable Chemical Vapor Deposition，FCVD)工艺，采用介电材料(如SiO2)，过填充厚的介电材料(如SiO2)膜层。之后，通过化学机械抛光(Chemical Mechanical Polishing，CMP)工艺对上述介电材料(如SiO2)膜层进行平坦化处理，在将要平坦化处理至堆叠结构(即鳍片)的沟道层31_4上时停止，并预留一定的工艺窗口。之后，通过回刻工艺将填充的介电材料(如SiO2)刻蚀一定深度，并在刻蚀至堆叠结构(即鳍片)的牺牲层01_1的下表面(即牺牲层01_1和衬底10接触的表面)时停止。
S103、形成横跨各堆叠结构的假栅结构(dummy gate)。且在第二方向F2上，假栅结构覆盖沟道层的沟道区。
示例性地，参照图7a至图7c，假栅结构(dummy gate)80沿第三方向F3延伸，且同一假栅结构(dummy gate)80可横跨多个堆叠结构(即鳍片)。图7a至图7c中仅示意出一个堆叠结构(即鳍片)。
需要说明的是，本申请对假栅结构(dummy gate)的宽度(即沿第一方向F1上的宽度)不作限制，但需符合国际设备和系统路线图(IRDS)制定的技术节点的要求，在抑制短沟道效应和光刻工艺能力范围内尽量做短。
示例性地，对于硅基器件，假栅结构(dummy gate)可包括假栅膜层和位于假栅膜层与沟道层之间的假栅氧化层。即，假栅结构(dummy gate)为由假栅氧化层和假栅膜层形成的叠层结构，又叫栅堆栈(gate stack)。
可选地，假栅膜层的材料例如为多晶硅。
在一些实施例中，首先，在形成有堆叠结构的衬底上形成覆盖整个衬底的假栅氧化层。之后，在假栅氧化层上形成假栅膜层。之后，采用光刻工艺和刻蚀工艺，对假栅氧化层和假栅膜层图案化，去除覆盖沟道区之外区域的假栅氧化层和假栅膜层，保留覆盖沟道区的假栅氧化层和假栅膜层，形成假栅结构。
作为具体实施的一个示例，参照图7a至图7c，从热氧化工艺、化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、原子层沉积(Atomic Layer Deposition，ALD)选取合适的工艺，在形成有堆叠结构的衬底10上生长覆盖整个衬底的薄的假栅氧化层和厚的多晶硅假栅膜层，形成假栅叠层。之后，采用光刻工艺和刻蚀工艺，在假栅叠层上形成硬掩膜81，以通过硬掩膜81定义出假栅结构80的图形。之后，采用刻蚀工艺，刻蚀假栅叠层，以将假栅叠层图案化，去除覆盖沟道区之外区域的假栅叠层，保留覆盖沟道区的假栅叠层，形成假栅结构80的图形。可选地，暂时还可将假栅结构顶部上的硬掩膜81保留，不用额外去除。
可选地，硬掩膜81的材料可以为氧化硅、氮化硅层或氮氧化硅以及其之间的混合膜层。
可选地，硬掩膜81在第二方向F2上的厚度范围为100nm～1000nm。并且，在不同的堆叠膜层的高度情况，其厚度值可不同。硬掩膜81在第二方向F2上的厚度可以根据实际应用的需求进行确定，在此不作限定。
S104、在假栅结构的两侧依次形成栅侧墙、源漏区以及层间绝缘层。
首先，参照图8a至图8c，在假栅结构80制造完成之后，可在沿第一方向F1上的假栅结构80的两侧形成栅侧墙50，以减小短沟道效应。可选地，暂时还可将假栅结构顶部上的硬掩膜81保留，不用额外去除。这样可以将硬掩膜81作为栅侧墙形成过程中的刻蚀停止层。
本申请对栅侧墙50的材料可不做限制，例如可为氮化硅(SiNx)、氮氧化硅、碳氧化硅等介质材料或者气隙等低介电常数的材料。在设置气隙时，不会影响器件的集成，同时有助于降低寄生电容，提高器件性能。
本申请对栅侧墙50的厚度(即沿第一方向F1上的厚度)可不做限制，例如可为2nm～10nm。
作为具体实施的一个示例，各向同性生长栅侧墙50材料，生长的厚度与设计的栅侧墙50厚度一致。之后，各向异性刻蚀，去除假栅结构80的两侧之外的上述栅侧墙50，并且刻蚀停止在上述硬掩膜作为的刻蚀停止层上。
之后，参照图9a至图9c，去除假栅结构两侧的堆叠结构，暴露出栅侧墙50下方的牺牲层01_1～01_4和沟道层31_1～31_4的侧面。即采用刻蚀工艺，去除未由假栅结构80和栅侧墙50覆盖的堆叠结构，暴露出沟道层31_1～31_4和牺牲层01_1～01_4在沿第一方向F1上的侧面。
之后，参照图10a至图10c，去除栅侧墙50下方的至少部分牺牲层，在栅侧墙50下方相邻的沟道层之间形成第二凹槽AX2。例如，第二凹槽AX2的底部由牺牲层形成，在第二方向F2上，第二凹槽AX2的侧壁由相邻沟道层形成，在第三方向F3上，第二凹槽AX2的侧壁由栅侧墙50形成。这样可以使第二凹槽AX2的高度(即沿第二方向F2的高度)为牺牲层的厚度。
作为具体实施的一个示例，采用选择性刻蚀工艺对暴露出的牺牲层01_1～01_4进行刻蚀，以将牺牲层01_1～01_4凹进形成第二凹槽AX2。第二凹槽AX2的深度(即沿第一方向F1上的深度)最终定义了内侧墙90的厚度(即沿第一方向F1上的厚度)，第二凹槽AX2的高度(即沿第二方向F2上的高度)为牺牲层的厚度并最终定义了内侧墙90的高度(即沿第二方向F2上的高度)。可选地，内侧墙90的高度大小于其厚度，因此第二凹槽AX2的高度不小于其深度。理想的第二凹槽AX2的形状为矩形，这里对牺牲层进行刻蚀的刻蚀工艺需要对沟道层材料具有很高的选择比，且具有精确的刻蚀控制。
需要说明的是，在实际应用中，由于制备工艺的因素，第二凹槽AX2的形状可能不能完全是矩形，其仅需大致满足上述条件即可。
并且，本申请对内侧墙90的厚度可不做限制，例如可为1nm～10nm。则第二凹槽AX2的深度(即 沿第一方向F1上的深度)即可与将要形成的内侧墙90的厚度相同。示例性地，内侧墙在平行于沟道区的延伸方向上的宽度一般不大于牺牲层在垂直于衬底所在平面上的厚度。需要说明的是，在实际应用中，内侧墙的宽度可以但不必须与栅侧墙的厚度一致，例如，内侧墙的宽度可以小于栅侧墙的厚度。在实际应用中，内侧墙的宽度可以根据实际应用环境的需求进行确定，在此不作限定。
之后，参照图11a至图11c，在第二凹槽AX2中填充介质材料，形成内侧墙90。并使，内侧墙90在平行于沟道区的延伸方向(即第一方向F1)上的宽度不大于牺牲层沿垂直于衬底所在平面的方向(即第二方向F2)上的厚度。
可选地，设置的内侧墙90位于牺牲层的两端，以将金属栅极与源区/漏区隔离，降低栅源和栅漏交叠电容，同时保证沟道释放过程第一区和第二区不被暴露和刻蚀，从而实现精确的栅长控制。内侧墙90的材料选择上，需要在牺牲层刻蚀时具有高抗刻蚀能力，另外内侧墙90材料选择上也需要它的刻蚀对沟道材料具有高选择性，由于低交叠电容的需求，尽量采用低介电常数的介质材料(例如，介电常数不大于7的介质材料)。
可选地，内侧墙90的材料可以用单层，也可以按照需求采用不同材料组合的多层设计，这里不做限制。例如，内侧墙90的材料包括但不限于由硅(Si)与碳(C)、氧(O)、氮(N)任意几种组合而成的介质材料。
作为具体实施的一个示例，采用沉积工艺各向同性沉积内侧墙90的介质材料，该沉积工艺需要具有很好的填充性，以完美填充上述第二凹槽AX2。例如，沉积工艺包括但不限于ALD工艺。之后，采用刻蚀工艺，对沉积后的内侧墙90材料进行刻蚀，仅保留第二凹槽AX2内的材料，形成内侧墙90。
之后，参照图12a至图12c，在假栅结构两侧的衬底10上外延形成连接沟道层的源漏区。
在一些实施例中，在上述假栅结构两侧采用外延工艺生长源区60_1和漏区60_2。其中，可以根据晶体管的导电沟道类型设计源区60_1和漏区60_2的材料，以提供应力等促进晶体管性能的方法，并且，源区60_1和漏区60_2的材料一般与沟道层材料和牺牲层材料类似，以保证源区60_1和漏区60_2的有效生长。
示例性地，在本申请实施例中的GAAFET为N型晶体管时，源区60_1和漏区60_2的材料包括但不限于Si、GaAs、GaAsP、SiP或其他合适的材料，并在外延生长过程中引入掺杂(如磷(P)、砷(As))或使用离子注入工艺进行非原位掺杂。
示例性地，在本申请实施例中的GAAFET为P型晶体管时，源区60_1和漏区60_2的材料包括但不限于Si、Ge、SiGe、AlGaAs、掺硼SiGe或其他合适的材料，并在外延生长过程中原位掺杂引入硼(B)或离子注入工艺进行非原位掺杂。
并且，源区60_1与沟道层31_1～31_4的第一区接触设置，以使源区60_1与沟道层31_1～31_4连接。漏区60_2与沟道层31_1～31_4的第二区接触设置，以使漏区60_2与沟道层31_1～31_4连接。
之后，参照图13a至图13c，在源漏区以及假栅结构上沉积层间绝缘层70。
在一些实施例中，层间绝缘层70包括刻蚀停止层(Contact Etch Stop Layer，CESL)和层间介质(Inter Layer Dielectrics，ILD)层。其中，CESL覆盖形成有源漏区的衬底10的表面，防止刻蚀接触孔(源区对应设置有接触孔，用于将源区与外部信号线连接，并且，漏区也对应设置有接触孔，用于将漏区与外部信号线连接)时发生严重的过刻。ILD层覆盖在刻蚀停止层的上方。
示例性地，在形成有源漏区的衬底10的整个结构上方沉积薄的CESL和厚的ILD层。图13a至图13c中层间绝缘层70的图形为包含薄的CESL和厚的ILD层的复合层。
可选地，CESL的材料包括但不限于氮化硅、氧化硅、氮氧化硅。并且，本申请对CESL的厚度不作限定，一般厚度较薄。
可选地，ILD层的材料包括但不限于正硅酸四乙酯(TEOS)氧化物、未掺杂硅酸盐玻璃或掺杂氧化硅，如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂硅玻璃(BSG)等介电材料。
作为具体实施的一个示例，从ALD、PECVD工艺等沉积工艺或氧化工艺中选取合适的工艺，形成厚度较薄的CESL。之后，从PECVD等沉积工艺中选取合适的工艺，过填充厚度较厚的ILD层，且过填充后的ILD层的高度常高于假栅结构80之上一定厚度。之后，需要去除多余的ILD层材料并暴露出假栅结构80的顶部，常采用CMP等平坦化工艺，对过填充后的ILD层进行平坦化处理，并在暴露出假栅结构80的顶部时停止。需要说明的是，在对多余的ILD层材料进行平坦化处理时，还去除假栅结 构80顶部的硬掩膜81。或者，采用CMP等平坦化工艺对过填充后的ILD层进行平坦化处理时，在暴露出假栅结构上的硬掩膜的顶部时停止。之后，可以采用刻蚀工艺去除该硬掩膜。之后，继续采用CMP等平坦化工艺对过填充后的ILD层进行平坦化处理，并在暴露出假栅结构的顶部时停止。
S105、去除假栅结构形成栅极开口，将沟道层中的沟道区和牺牲层的侧壁暴露出来。
在一些实施例中，假栅结构采用假栅氧化层和假栅膜层的叠层结构，去除假栅结构需要将上述假栅氧化层和假栅膜层的材料进行选择性蚀刻。
作为具体实施的一个示例，参照图14a至图14c，可以采用四甲基氢氧化铵(THMA)进行选择性湿法蚀刻、或者选择性干蚀刻或其组合来去除假栅结构的材料，暴露出原假栅结构覆盖处的沟道层和牺牲层。
S106、从处于栅极开口中的牺牲层裸露表面开始向内刻蚀牺牲层，将各沟道层的沟道区的部分区域凸出于牺牲层。
在一些实施例中，参照图15a至图15c，对栅极开口GK中暴露出的牺牲层01_1～01_4进行部分地选择性刻蚀，以刻蚀出一定深度的第一凹槽AX1。该第一凹槽AX1由相邻的沟道层以及设置于相邻的沟道层之间的牺牲层形成，从而将各沟道层的沟道区的部分区域凸出于牺牲层。例如，第一凹槽AX1的底部由牺牲层形成，在第二方向F2上，第一凹槽AX1的侧壁由相邻沟道层形成，在第一方向F1上，第一凹槽AX1的侧壁由内侧墙90形成。这样可以使第一凹槽AX1的高度(即沿第二方向F2的高度)为牺牲层的厚度。
可选地，参照图15c，在平行于衬底10所在平面且垂直于沟道区的延伸方向的方向(即第三方向F3)上，沟道层31_1～31_4中凸出于牺牲层01_1～01_4的部分区域具有第一宽度D1。在垂直于衬底10所在平面的方向(即第二方向F2)上，牺牲层01_1～01_4具有第一厚度H1。本申请对第一宽度D1不进行限制。示例性地，一般地可以使第一宽度D1不大于第一厚度H1。第一宽度D1定义了第一凹槽AX1的深度(即沿第三方向上的深度)，对于不同纳米片沟道层宽度的GAAFET器件，第一宽度D1可不同，相应地，第一凹槽AX1的深度(即沿第一方向F1上的深度)也不同。可选地，第一宽度D1为5nm～10nm，即第一凹槽AX1的深度为5nm～10nm。当然，也可以使第一宽度大于第一厚度。在实际应用中，可以根据实际应用的需求确定第一宽度和第一厚度。
以及，牺牲层的刻蚀采用具有精确刻蚀控制的原子层刻蚀工艺(Atomic Layer Etching，ALE)或者干法连续刻蚀工艺，且刻蚀需要对沟道层具有很好的选择性，以尽可能降低对沟道层的损伤。
S107、在处于栅极开口中裸露出的沟道区表面包覆保护层。
在一些实施例中，首先，参照图16a至图16c，采用与牺牲层材料和沟道层材料具有不同刻蚀选择比的材料，在处于栅极开口GK中的牺牲层01_1～01_4表面和沟道层31_1～31_4表面沉积保护初始膜层100。
示例性地，采用沉积工艺，进行保护层沉积，对于不同牺牲层厚度的纳米片GAAFET，保护层的厚度的可不同。一般地，保护层的厚度约为牺牲层厚度的一半，不同尺寸环境情况不同，保护层的材料应选择对牺牲层01_1～01_4和沟道层31_1～31_4材料具有高刻蚀选择性的材料。并且，保护层的材料还应不同于栅侧墙50，内侧墙90和隔离结构20处已采用过的材料，以保证这里的保护层材料在下面去除保护层的步骤中，能够被选择性去除，而不侵蚀栅侧墙50，内侧墙90和隔离结构20。
可选地，保护层的材料包括但不限于a-Si，SiN，SiNO，SiOC等材料，根据不同场景，可灵活选择。
可选地，采用沉积工艺形成保护初始膜层。其中，可选取保形性差的沉积工艺。示例性地，可以采用气相沉积工艺、原子层沉积、等离子体增强化学的气相沉积工艺以及等离子体增强原子层沉积等工艺，以利用沉积工艺保形性差的特点，形成如下形式的填充方式：参照图16a至图16c，在栅极开口GK中沉积保护初始膜层100，使保护初始膜层100覆盖处于栅极开口GK中的牺牲层01_1～01_4表面和沟道层31_1～31_4表面，并在保护初始膜层100将第一凹槽AX1的开口端封闭，以在第一凹槽AX1中通过保护初始膜层100合围成腔体后停止沉积。其中，牺牲层01_1～01_4表面的保护初始膜层100的厚度小于沟道层31_1～31_4表面的保护初始膜层100的厚度。也就是说，第一凹槽AX1内部的保护层材料填充不充分，第一凹槽AX1的开口端提前被保护层材料封口，导致第一凹槽AX1内部的保护层存在孔洞，而沟道层的侧壁，顶部和边角处的保护层材料填充比较充分且厚度较厚。
之后，参照图16d，去除牺牲层01_1～01_4表面的保护初始膜层100，保留处于栅极开口GK中的 沟道层31_1～31_4表面的保护初始膜层，形成保护层110。
在一些实施例中，利用第一凹槽AX1内外填充的差异性，对保护层的结构进行修饰。采用干法刻蚀工艺，将保护初始膜层减薄，使封闭第一凹槽AX1的开口端的保护初始膜层形成开口，以去除第一凹槽AX1的底端处的牺牲层表面的保护初始膜层，保留沟道层表面的保护初始膜层，形成保护层。也就是说，采用具有精确的刻蚀控制的干法刻蚀工艺，以保证第一凹槽AX1封口被打开，第一凹槽AX1内部(尤其是底部)的保护层材料被刻蚀，而沟道层的侧壁，顶部和边角处的保护层材料部分剩余，形成如图16d所示的保护层的轮廓。
需要说明的是，保护层的填充和刻蚀的轮廓包括不限于图16d中所示的轮廓，图16d示意的只是提供的一种可能的实例，只要通过保护层的沉积和刻蚀，形成沟道层31_1～31_4的沟道区边角、顶部以及侧壁被保护的形状即可，比如第一凹槽AX1内部的保护层的孔洞可以具有很多，也可以质量很差，牺牲层侧壁是否沉积保护层均可，只要最终经保护层刻蚀后，形成第一凹槽AX1的底部暴露出牺牲层，沟道层31_1～31_4的侧壁、顶部和边角处被保护层保护的轮廓即可。当然，此处也仅是说明的理想情况。在制备工艺中，去除保护层的工艺可能会有所偏差，例如，处于牺牲层与沟道层的边角处的保护初始膜层并未完全去除，有少量残留。又例如，处于沟道层的靠近上述边角处的保护初始膜层被去除，也能满足要求。这些情况均在本专利的保护范围之内。
在另一些实施例中，为了形成保护层，在处于所述栅极开口中的沟道层表面包覆保护层，包括：也可采用选择性沉积工艺，在处于栅极开口中的沟道层表面沉积保护层。
S108、去除处于栅极开口中的牺牲层。
参照图16e，采用刻蚀工作，进行牺牲层刻蚀，去除处于栅极开口GK中的牺牲层，将沟道层31_1～31_4的沟道区进行释放。
可选地，牺牲层的刻蚀工艺可采用各向同性刻蚀，采用对沟道层材料，保护层材料具有高刻蚀选择性的刻蚀工艺，也需要对已采用过的栅侧墙50，内侧墙90等材料具有刻蚀选择性的刻蚀工艺。
需要说明的是，沟道层31_1～31_4的沟道区在第二表面具有未被保护层覆盖的未覆盖区域，在垂直于衬底10所在平面的方向上，基准区域ZQ可以设置于每一个沟道层的未覆盖区域内。由于，第一表面S1被保护层110覆盖，而第二表面S2_1～S2_4有部分区域被牺牲层覆盖但未被保护层覆盖，因此，第一表面S1中对应基准区域ZQ处的区域(即在第二方向F2上，第一表面S1中被基准区域ZQ覆盖的区域)相比第二表面S2_1～S2_4中对应基准区域ZQ处的区域(即在第二方向F2上，第二表面S2_1～S2_4中被基准区域ZQ覆盖的区域)，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面S1对应基准区域ZQ处的平整度大于沟道层31_1～31_4的第二表面S2_1～S2_4对应基准区域ZQ处的平整度。
同理，第一表面S1中对应基准区域ZQ处的区域(即在第二方向F2上，第一表面S1中被基准区域ZQ覆盖的区域)相比第三表面S3_1～S3_3中对应基准区域ZQ处的区域(即在第二方向F2上，第三表面S3_1～S3_3中被基准区域ZQ覆盖的区域)，在刻蚀去除牺牲层的过程中，受到保护层的保护作用，可以降低刻蚀损伤，因此，第一表面S1对应基准区域ZQ处的平整度大于沟道层31_1～31_3的第三表面S3_1～S3_3对应基准区域ZQ处的平整度。
以及，不仅第一表面S1被保护层覆盖，各沟道层31_1～31_4的沟道区中凸出于牺牲层设置的部分区域(即沟道区的边角和侧壁)也被保护层覆盖，以通过保护层对沟道区的侧壁和边角处进行保护，可以避免由于刻蚀损伤和边角处刻蚀速率较快，导致沟道轮廓和沟道界面不理想的问题。因此，本申请实施例，通过设置保护层，保护沟道区在牺牲层刻蚀过程中不受损伤，形成理想轮廓和界面完好的沟道区。从而改善器件的有效沟道宽度降低和迁移率退化的问题，提高器件性能。
S109、去除保护层，将所有沟道区暴露，形成沟道结构。
参照图17a至图17c，采用刻蚀工艺，将完成沟道区保护作用的保护层进行去除，以将所有的沟道区暴露，形成沟道结构30。
可选地，保护层的刻蚀工艺应采用对沟道层31_1～31_4、栅侧墙50、内侧墙90等材料具有高刻蚀选择性的刻蚀工艺，尽可能的不损伤沟道，并保证保护层材料的完全去除，以及确保后续栅极结构的有效填充。
可选地，可以采用干法刻蚀工艺去除保护层，并且，在去除保护层的干法刻蚀工艺中，可将刻蚀偏压的范围设置为0～150V，以保证刻蚀去除保护层步骤中产生的离子轰击较小，从而尽可能不对距离衬 底最远的沟道层的第一表面产生刻蚀损伤，尽可能的保证第一表面的平整度优于第二表面和第三表面的平整度。当然，也可以采用湿法刻蚀去除保护层，以避免第一表面出现刻蚀损伤，尽可能的保证第一表面的平整度优于第二表面和第三表面的平整度。
S110、在栅极开口中，形成环绕每一个沟道区的栅极结构。
示例性地，参照图1a至图1c，栅极结构40沿第三方向F3延伸，且同一栅极结构40可横跨一个或多个沟道结构30中沟道层的沟道区。图1a至图1c中仅示意出一个沟道结构30。
示例性地，栅极结构40包括金属栅极42和位于金属栅极42与沟道层31_1～31_4之间的栅介质层41。即，栅极结构40为由金属栅极42和栅介质层41形成的叠层结构。可选地，栅介质层41还可以覆盖在栅极开口中暴露出的内侧墙90的表面、以及覆盖在栅极开口中暴露出的栅侧墙50的表面、以及覆盖在栅极开口中暴露出的衬底10的表面。
在一些实施例中，首先，从ALD、CVD等沉积工艺中选取合适的沉积工艺，在去除保护层后的衬底10上沉积介电材料，在每一个沟道区表面和栅极开口GK中栅侧墙50的侧壁上形成栅介质层。之后，从ALD、CVD等沉积工艺中选取合适的沉积工艺，在形成有栅介质层的衬底10上沉积金属栅极，填充栅极开口GK，使金属栅极覆盖栅介质层，以环绕每一个沟道层31_1～31_4的沟道区。
可选地，形成栅介质层的介电材料为高介电常数的介电材料，可为大于氧化硅的介电常数的介电材料，例如，为氧化铝(Al2O3)、氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)等材料。
可选地，金属栅极一般为多层结构，该多层结构包含但不限于功函数金属(可能多层功函数金属)、衬垫层、浸润层、粘附层、金属导电层或金属硅化物等组合。例如，金属栅极包含但不限于钛(Ti)、钌(Ru)、钴(Co)，氮化钛(TiN)、钛铝(TiAl)、氮化钽(TaN)、碳化钛铝(TiAlC)、钨(W)等。
在另一些实施例中，为实现更好的栅介质层与沟道区的界面接触，提高载流子迁移率，栅极结构40还包括设置于栅介质层和沟道层之间的界面层。示例性地，界面层包括介电材料，诸如，氧化硅、硅酸铪或氮氧化硅等。可选地，可以使用化学氧化、热氧化、ALD、CVD等其他方法来生长界面层，生长界面层的过程可发生在栅介质层沉积之前，也可以发生在栅介质层沉积之后。
综上，本申请通过上述步骤，即可以完成纳米片GAAFET的制备过程。当然，上述实施例中是为了更好的解释本申请，但不限制本申请。
需要说明的是，在GAAFET完成制备之后，后续还需要进行刻蚀接触孔、布线、电极的引出和电路的互连，可完成环栅纳米片晶体管的集成电路的制造过程。
需要说明的是，图15a、图16a以及图17a中，为了便于示意出栅极开口的内容，未示意出栅侧墙和层间绝缘层。
本申请实施例还提供了电子设备，该电子设置包括电路板(如印刷电路板)和本申请上述实施例提供的任一种半导体器件，该半导体器件与电路板连接。由于该电子设备解决问题的原理与前述半导体器件相似，因此该电子设备的实施可以参见前述半导体器件的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种半导体器件的制备方法，其特征在于，包括：
    在衬底上形成多个相互间隔排列的堆叠结构；其中，所述堆叠结构包括交替堆叠的牺牲层和沟道层；
    在相邻两个所述堆叠结构之间的所述衬底中形成隔离结构；
    形成横跨各所述堆叠结构的假栅结构；其中，所述假栅结构覆盖所述沟道层的沟道区；
    在所述假栅结构的两侧依次形成栅侧墙、源漏区以及层间绝缘层；
    去除所述假栅结构形成栅极开口；
    从处于所述栅极开口中的牺牲层裸露表面开始向内刻蚀所述牺牲层，将各所述沟道层的沟道区的部分区域凸出于所述牺牲层；
    在处于所述栅极开口中裸露出的沟道区表面包覆保护层；
    去除处于所述栅极开口中的牺牲层；
    去除所述保护层，将所有沟道区暴露；
    在所述栅极开口中，形成环绕每一个所述沟道区的栅极结构。
  2. 如权利要求1所述的半导体器件的制备方法，其特征在于，所述在处于所述栅极开口中的沟道层表面包覆保护层，包括：
    采用与所述牺牲层材料和所述沟道层材料具有高刻蚀选择比的材料，在处于所述栅极开口中的所述牺牲层表面和所述沟道层表面沉积保护初始膜层；
    去除所述牺牲层表面的保护初始膜层，保留所述沟道层表面的保护初始膜层，形成所述保护层。
  3. 如权利要求2所述的半导体器件的制备方法，其特征在于，相邻的沟道层以及设置于所述相邻的沟道层之间的牺牲层形成第一凹槽；
    所述在处于所述栅极开口中的所述牺牲层表面和所述沟道层表面沉积保护初始膜层，包括：
    采用沉积工艺，在所述栅极开口中沉积保护初始膜层，使所述保护初始膜层覆盖处于所述栅极开口中的所述牺牲层表面和所述沟道层表面，并在所述保护初始膜层将所述第一凹槽的开口端封闭，以在所述第一凹槽中通过所述保护初始膜层合围成腔体后停止沉积；其中，所述牺牲层表面的保护初始膜层的厚度小于所述沟道层表面的保护初始膜层的厚度；
    所述去除所述牺牲层表面的保护初始膜层，保留所述沟道层表面的保护初始膜层，包括：
    采用干法刻蚀工艺，将所述保护初始膜层减薄，使封闭所述第一凹槽的开口端的保护初始膜层形成开口，以去除所述第一凹槽的底端处的所述牺牲层表面的保护初始膜层，保留所述沟道层表面的保护初始膜层。
  4. 如权利要求2或3所述的半导体器件的制备方法，其特征在于，沉积所述保护初始膜层的工艺为下述工艺中的至少一个：
    气相沉积工艺、原子层沉积、等离子体增强化学的气相沉积工艺以及等离子体增强原子层沉积。
  5. 如权利要求1所述的半导体器件的制备方法，其特征在于，所述在处于所述栅极开口中的沟道层表面包覆保护层，包括：
    采用选择性沉积工艺，在处于所述栅极开口中的所述沟道层表面沉积保护层。
  6. 如权利要求1-5任一项所述的半导体器件的制备方法，其特征在于，所述在所述假栅结构的侧壁处依次形成栅侧墙、源漏区以及层间绝缘层，包括：
    在所述假栅结构两侧形成所述栅侧墙；
    去除所述假栅结构两侧的所述堆叠结构，暴露出所述栅侧墙下方的所述牺牲层和所述沟道层的侧面；
    去除所述栅侧墙下方的至少部分所述牺牲层，在所述栅侧墙下方相邻的所述沟道层之间形成第二凹槽；
    在所述第二凹槽中填充介质材料，形成内侧墙；
    在所述假栅结构两侧的所述衬底上外延形成连接沟道层的所述源漏区；
    在所述源漏区以及所述假栅结构上沉积所述层间绝缘层。
  7. 如权利要求6所述的半导体器件的制备方法，其特征在于，所述内侧墙在平行于所述沟道区的延伸方向上的宽度不大于所述牺牲层的厚度。
  8. 如权利要求1-7任一项所述的半导体器件的制备方法，其特征在于，所述在所述栅极开口中，形成环绕每一个所述沟道区的栅极结构，包括：
    在去除所述保护层后的衬底上沉积介电材料，在每一个所述沟道区表面和所述栅极开口中栅侧墙的侧壁上形成栅介质层；
    在形成有所述栅介质层的衬底上沉积金属栅极，填充所述栅极开口，使所述金属栅极覆盖所述栅介质层，以环绕每一个所述沟道区。
  9. 如权利要求1-8任一项所述的半导体器件的制备方法，其特征在于，所述形成横跨各所述堆叠结构的假栅结构，包括：
    在形成有所述堆叠结构的衬底上形成覆盖整个所述衬底的假栅氧化层；
    在所述假栅氧化层上形成假栅膜层；
    采用光刻工艺和刻蚀工艺，对所述假栅氧化层和所述假栅膜层图案化，去除覆盖所述沟道区之外区域的所述假栅氧化层和所述假栅膜层，保留覆盖所述沟道区的所述假栅氧化层和所述假栅膜层，形成所述假栅结构。
  10. 如权利要求1-9任一项所述的半导体器件的制备方法，其特征在于，所述在衬底上形成多个相互间隔排列的堆叠结构，包括：
    交替地在所述衬底上外延生长牺牲层和沟道层，形成堆叠膜层；
    将所述堆叠膜层图案化，形成多个相互间隔排列的堆叠结构，并在所述衬底中形成浅沟槽；所述堆叠结构中的沟道层为纳米片沟道层；
    所述在相邻两个所述堆叠结构之间的所述衬底中形成隔离结构，包括：
    在所述浅沟槽中填充介电材料，形成所述隔离结构。
  11. 一种半导体器件，其特征在于，采用如权利要求1-10任一项所述的制备方法制备形成；
    所述半导体器件包括：
    衬底；
    晶体管，设置于所述衬底上；其中，所述晶体管包括：
    设置于所述衬底上的沟道结构；其中，所述沟道结构包括层叠且间隔设置的多个沟道层；将距离所述衬底最远的沟道层背离所述衬底一侧的表面定义为第一表面，将任一个所述沟道层面向所述衬底一侧的表面定义为第二表面，将除距离所述衬底最远的沟道层之外的其余沟道层背离所述衬底一侧的表面定义为第三表面，所述第一表面对应基准区域处的平整度大于任一个所述沟道层的所述第二表面对应所述基准区域处的平整度，且所述第一表面对应基准区域处的平整度大于任一个所述沟道层的所述第三表面对应所述基准区域处的平整度；在垂直于所述衬底所在平面的方向上，所述基准区域覆盖每一个所述沟道层的重心；
    设置于所述衬底上的栅极结构；其中，所述栅极结构环绕每一个所述沟道层的所述沟道区；
    设置于所述栅极结构两侧的栅侧墙；
    设置于所述栅极结构两侧的源漏区；
    设置于所述源漏区上的层间绝缘层；
    隔离结构，设置于相邻两个所述沟道结构之间的衬底中。
  12. 如权利要求11所述的半导体器件，其特征在于，所述沟道层为纳米片沟道层。
  13. 如权利要求11或12所述的半导体器件，其特征在于，所述半导体器件还包括：多个内侧墙；其中，所述栅侧墙在所述衬底的正投影覆盖所述内侧墙在所述衬底的正投影；
    每相邻两个沟道层的第一区之间设置一个所述内侧墙，且距离所述衬底最近的沟道层的第一区与所述衬底之间设置一个所述内侧墙；
    每相邻两个沟道层的第二区之间设置一个所述内侧墙，且距离所述衬底最近的沟道层的第二区与所述衬底之间设置一个所述内侧墙。
  14. 如权利要求11-13任一项所述的半导体器件，其特征在于，所述栅极结构包括栅介质层和金属栅极；
    所述金属栅极环绕所述沟道层的所述沟道区；
    所述栅介质层设置于所述金属栅极和所述沟道层的沟道区之间。
  15. 一种电子设备，其特征在于，包括电路板和半导体器件，所述半导体器件与所述电路板连接；
    所述半导体器件采用如权利要求1-10任一项所述的制备方法形成，或者所述半导体器件为如权利要求11-14任一项所述的半导体器件。
PCT/CN2023/104275 2022-08-31 2023-06-29 半导体器件、制备方法以及电子设备 WO2024045864A1 (zh)

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