WO2024045733A1 - 半导体结构的制备方法、半导体结构及半导体器件 - Google Patents

半导体结构的制备方法、半导体结构及半导体器件 Download PDF

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Publication number
WO2024045733A1
WO2024045733A1 PCT/CN2023/097869 CN2023097869W WO2024045733A1 WO 2024045733 A1 WO2024045733 A1 WO 2024045733A1 CN 2023097869 W CN2023097869 W CN 2023097869W WO 2024045733 A1 WO2024045733 A1 WO 2024045733A1
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Prior art keywords
bit line
semiconductor
transistor
capacitor
along
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French (fr)
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WO2024045733A9 (zh
Inventor
赵文礼
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a method of manufacturing a semiconductor structure, a semiconductor structure and a semiconductor device.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • Embodiments of the present disclosure provide a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor device, which can further save space, increase the unit density of the semiconductor structure, and improve storage performance.
  • Embodiments of the present disclosure provide a method for preparing a semiconductor structure, including: providing a substrate; forming a bit line structure on the substrate, the bit line structure including a plurality of bit lines stacked along a first direction; A capacitor structure is formed on the substrate, the capacitor structure includes a plurality of capacitors stacked along the first direction; a transistor structure extending along the second direction is formed on the substrate, the transistor structure includes a plurality of capacitors stacked along the first direction.
  • a plurality of stacked transistors the transistor structure has a first end and a second end in the second direction; the first end is connected to the bit line structure, and the second end is connected to the capacitor structure, so
  • the bit line structure and the capacitor structure are located on opposite sides of the transistor structure along a third direction; the first direction is perpendicular to the substrate, and the second direction and the third direction are located parallel to the within the plane of the base.
  • the method further includes: forming a plurality of epitaxial structures stacked along the first direction on the substrate, the epitaxial structures including sacrificial layers stacked sequentially along the first direction. and a semiconductor layer; etching the epitaxial structure so that the epitaxial structure has a first epitaxial part, a second epitaxial part and a third epitaxial part, the second epitaxial part extends along the second direction, and the first epitaxial part
  • the first extension part and the third extension part are respectively connected to the first end and the second end of the second extension part along the second direction; and the first extension part and the third extension part are located on the Opposite sides of the second extension part along the third direction; removing the first end and the second end of the second extension part, and the first extension part and the third extension part
  • Each sacrificial layer of the first portion is formed to form a plurality of first spaces to be filled; an insulating layer is filled into the first spaces to be filled.
  • forming a bit line structure on the substrate includes: removing the semiconductor layer in the first epitaxial portion to form a plurality of second spaces to be filled; The first conductive material is filled to form the bit line structure.
  • the method further includes: forming the bit line structure into a ladder structure along the first direction to expose at least part of the upper surface of each layer of the bit lines; A plurality of first wiring posts are respectively formed on the bit lines.
  • the second epitaxial portion further includes a middle portion between the first end and the second end, and the bit line structure has a relationship with the middle portion in the second direction.
  • a first interval, the capacitor structure has a second interval from the middle part in the second direction;
  • forming a transistor structure extending along the second direction on the substrate includes: removing all parts of the second epitaxial part The sacrificial layer in the middle part forms a gap; a gate dielectric layer is formed on the surface of the semiconductor layer in the middle part of the second epitaxial part; a gate electrode is formed on the surface of the gate dielectric layer, and the gate electrode fills the gap.
  • the second epitaxial portion further includes a middle portion between the first end and the second end, and the bit line structure has a relationship with the middle portion in the second direction.
  • a first interval, the capacitor structure has a second interval from the middle part in the second direction;
  • forming a transistor structure extending along the second direction on the substrate includes: removing all parts of the second epitaxial part The sacrificial layer in the middle part; a gate dielectric layer is formed on the surface of the semiconductor layer in the middle part of the second epitaxial part; a gate electrode is formed on the surface of the gate dielectric layer, and the gate electrode is formed along the first
  • the third direction or the fourth direction extends on one side of the second epitaxial portion and is not in contact with the bit line structure or the capacitor structure; the fourth direction and the third direction are located parallel to the substrate.
  • an insulating material layer is filled between adjacent gate electrodes.
  • the method further includes: forming the stacked plurality of gate electrodes into a ladder structure, exposing at least part of the upper surface of each layer of the gate electrode; A plurality of second terminals are respectively formed on the electrodes.
  • the method further includes: forming a conductive connection on one end of the bit line structure along the first direction and away from the transistor structure, and the conductive connection is connected to each of the bit line connection.
  • forming a transistor structure extending along the second direction on the substrate includes: performing ion doping on the first end and the second end of the second epitaxial part, respectively. Forming the source and drain of the transistor structure; performing a metal silicide treatment on at least a portion of the source connected to a bit line in the bit line structure to form a bit line contact; at least a portion of the drain connected to the bit line in the bit line structure.
  • the portion where the capacitors are connected in the capacitor structure is metal silicided to form a capacitor contact.
  • Some embodiments of the present disclosure also provide a semiconductor structure, including: a substrate, a bit line structure, a capacitor structure and a transistor structure.
  • bit line structure is located on the substrate, and the bit line structure includes a plurality of bit lines stacked along a first direction; a capacitor structure is located on the substrate, and the capacitor structure includes a plurality of bit lines stacked along the first direction.
  • a transistor structure is located on the substrate and extends along the second direction, the transistor structure includes a plurality of transistors stacked along the first direction, the transistor structure has a third One end and a second end, the first end is connected to the bit line structure, the second end is connected to the capacitor structure, and the transistor structure and the capacitor structure are located along the third direction of the transistor structure Opposite sides; wherein the first direction is perpendicular to the base, and the second direction and the third direction are located in a plane parallel to the base.
  • the transistor includes: a channel located between a first end and a second end of the transistor; a gate dielectric layer located on a surface of the channel; a gate electrode located on the gate
  • the surface of the dielectric layer extends on one side of the transistor along the third direction or the fourth direction and is not in contact with the bit line structure or the capacitor structure.
  • the fourth direction and the third The direction is located in a plane parallel to the substrate, a plurality of multi-layered gate electrodes of the transistors stacked along the first direction have a ladder structure, and at least part of the upper surface of the gate electrode of each layer is exposed.
  • the semiconductor structure also includes: a plurality of second wiring posts, respectively located on the multiple layers of gate electrodes in a ladder structure; and an insulating material layer located between adjacent gate electrodes.
  • the bit line structure has a first spacing from the gate electrode in the second direction
  • the capacitor structure has a second spacing from the gate electrode in the second direction.
  • a first terminal of the transistor is a source
  • a second terminal of the transistor is a drain
  • the transistor includes: a bit line contact located between the source and the bit line structure between the bit lines; a capacitive contact between the drain and the capacitor of the capacitive structure.
  • Some embodiments of the present disclosure also provide a semiconductor device including a first semiconductor unit including a first semiconductor structure having a first line structure, a first transistor structure and a first capacitor structure, the first transistor structure extends along the second direction, the first line structure and the first capacitor structure are located on opposite sides of the first transistor structure in the third direction; second A semiconductor structure, the second semiconductor structure has a second bit line structure, a second transistor structure and a second capacitor structure, the second transistor structure extends along a second direction, the second bit line structure and the second capacitor structure The capacitor structure is located on opposite sides of the second transistor structure in the third direction; wherein the projection of the first capacitor structure along the second direction at least partially coincides with the second capacitor structure; the first transistor structure The projection along the third direction coincides with the second transistor structure; wherein the second direction and the third direction are perpendicular to each other.
  • the first transistor structure and the second transistor structure respectively have opposite first and second sides in the third direction, wherein the first line structure and the first transistor structure
  • the second capacitor structure is located on the first side, and the first capacitor structure and the second bit line structure are located on the second side.
  • the semiconductor device further includes: a second semiconductor unit having the same structure as the first semiconductor unit; the second semiconductor unit and the first semiconductor unit The units are spaced apart in the second direction and the third direction.
  • the semiconductor device further includes: a third semiconductor unit having a structure symmetrical with the first semiconductor unit about a symmetry axis; the symmetry axis is along the third extending in the direction; the third semiconductor unit and the first semiconductor unit are spaced apart in the second direction and the third direction.
  • the bit line structure and the capacitor structure are provided on opposite sides of the transistor structure along the third direction to form the semiconductor structure.
  • this semiconductor structure can further save space, increase the unit density of the semiconductor structure, and improve storage performance.
  • FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of forming an epitaxial structure on a substrate according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of forming an epitaxial structure having various epitaxial portions according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of forming a first space to be filled in an epitaxial structure according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of forming an insulating layer in an epitaxial structure according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of forming a gap in an epitaxial structure according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a gate electrode and a drain electrode forming a transistor structure in some embodiments of the present disclosure.
  • Figure 8 is a schematic diagram of forming a gate dielectric layer on a channel surface according to some embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of a gate electrode forming a transistor structure shown in some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of forming a second space to be filled in the first extension part in some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a semiconductor structure formed with a bit line structure, a capacitor structure and a transistor structure in some embodiments of the present disclosure.
  • 12 to 15 are schematic diagrams of the bit line structure forming a ladder structure in some embodiments of the present disclosure.
  • FIG. 16 is a schematic diagram of a semiconductor structure in which the bit line structure is a ladder structure in some embodiments of the present disclosure.
  • FIG. 17 is a schematic diagram of a semiconductor structure in which the gate electrode is a stepped structure in other embodiments of the present disclosure.
  • FIG. 18 is a flowchart of a method of forming a gate electrode of a transistor structure illustrated in some embodiments of the present disclosure.
  • 19 is a flowchart of a method of forming a gate electrode of a transistor structure shown in other embodiments of the present disclosure.
  • Figure 20 is a layout diagram of a semiconductor device shown in some embodiments of the present disclosure.
  • Figure 21 is another layout diagram of a semiconductor device shown in some embodiments of the present disclosure.
  • Figure 22 is another layout diagram of a semiconductor device shown in some embodiments of the present disclosure.
  • Figure 23 is another layout diagram of a semiconductor device shown in some embodiments of the present disclosure.
  • Capacitive contact; 230 capacitor structure; 231, capacitor; 240, first terminal; 250, second terminal; 260, conductive connector; 1000, first semiconductor unit; 1100, first semiconductor structure; 1110, first line structure; 1120. First transistor structure; 1130. First capacitor structure; 1200. Second semiconductor structure; 1210. Second bit line structure; 1220. Second transistor structure; 1230. Second capacitor structure; 2000. Second semiconductor unit; 3000. Third semiconductor unit; Z, first direction; Y, second direction; X, third direction; P, fourth direction; C1, first space to be filled; C2, second space to be filled; G, gap ;F, symmetry axis; d1, first interval; d2, second interval.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • plural means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.
  • FIGS. 1 to 17 embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • Figure 1 shows a flow chart of the preparation method of the semiconductor structure of the present disclosure.
  • Figures 2 to 17 respectively show schematic diagrams of the semiconductor structure during the preparation process.
  • Figure 3 Base 1 has been omitted in Figure 17 .
  • the method for preparing a semiconductor structure according to an embodiment of the present disclosure includes steps: S110 to S140.
  • the substrate 1 provided by the embodiment of the present disclosure is a semiconductor substrate. Shallow trench isolations (not shown in the figure) are formed in the substrate 1 , and active areas are provided between the shallow trench isolations.
  • the material of the substrate 1 in the embodiment of the present disclosure may be silicon, silicon carbide, silicon nitride, silicon on insulator, silicon on insulator, silicon germanium on insulator, silicon germanium on insulator or germanium on insulator, etc., which are not mentioned here. Make special restrictions.
  • the method for preparing the semiconductor structure according to the embodiment of the present disclosure may further include the following contents A to D.
  • the epitaxial structures 2 include sacrificial layers 201 and semiconductor layers 202 sequentially stacked along the first direction Z.
  • the material of the sacrificial layer 201 can be SiGe, silicon oxide, silicon nitride, silicon carbonitride, etc.
  • the semiconductor layer 202 can be silicon, silicon carbide, silicon on insulator, etc., as long as there is a gap between the semiconductor layer 202 and the sacrificial layer 201.
  • a larger etching selectivity ratio is sufficient.
  • the material of the sacrificial layer 201 is SiGe
  • the material of the semiconductor layer is Si.
  • FIG. 2 and FIG. 3 only show three layers of sacrificial layer 201 and semiconductor layer 202 stacked in sequence. It can also be four, five, six or more layers, and is not specifically limited here.
  • the first direction Z is a direction perpendicular to the surface of the substrate 1 .
  • the second epitaxial portion 22 extends along the second direction Y
  • the first epitaxial portion 21 and the third epitaxial portion 23 extend along the second direction Y
  • the extension portion 23 is respectively connected to the first end 221 and the second end 222 of the second extension portion 22 along the second direction Y; and the first extension portion 21 and the third extension portion 23 are located along the third end of the second extension portion 22 .
  • Direction X on opposite sides.
  • a mask layer may be formed on the epitaxial structure 2.
  • the mask layer has a pattern.
  • the epitaxial structure 2 is etched using the pattern of the mask layer.
  • Multiple epitaxial etching structures may be formed.
  • Each epitaxial etching structure may include a first etching structure.
  • the etching process can be wet etching or dry etching. Wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants.
  • concentration of the etchant the degree of etching can be controlled; dry etching can be plasma etching, and the plasma process uses
  • the etching gas can be chlorine gas. By controlling the amount of etching gas, the degree of etching can be controlled. There is no special limitation here.
  • the second extension 22 extends along the second direction Y.
  • the second direction Y is located in a plane parallel to the substrate 1 , that is, the second extension 22 extends along the second direction Y.
  • One direction Z is perpendicular to the second direction Y.
  • the second extension part 22 has an opposite first end 221 and a second end 222 in the second direction Y.
  • the first extension part 21 is connected to the first end 221 of the second extension part 22 and the third extension part 23 is connected to the first end 221 of the second extension part 22 .
  • the second end 222 of the second extension part 22 , and the first extension part 21 and the third extension part 23 are located on opposite sides of the second extension part 22 along the third direction X.
  • the third direction X and the second direction Y are located in a plane parallel to the substrate 1, and the third direction X and the second direction Y have an included angle.
  • the third direction X is perpendicular to the second direction Y.
  • the third direction 22 has two opposite sides in the third direction The opposite sides are not limited to the two sides along the second direction Y, and there is no special limitation here.
  • the first extension part 21 may have a first included angle with the second extension part 22
  • the third extension part 23 may have a second included angle with the second extension part 22
  • the first included angle may be equal to the second included angle.
  • the first extension portion 21 and the third extension portion 23 extend in parallel in a direction away from the second extension portion 22
  • the first included angle may not be equal to the second included angle, that is, the first extension portion 21 and the third extension portion 23 extend in parallel in a direction away from the second extension portion 22 .
  • the extension portions 23 respectively extend in different directions away from the second extension portion 22 , but in either case, the extension directions of the first extension portion 21 and the third extension portion 23 are located in a plane parallel to the base 1 , so that The first extension portion 21 , the second extension portion 22 and the third extension portion 23 form a substantially “Z” shaped structure.
  • the first included angle and the second included angle are equal and 90° respectively, that is, the first extension portion 21 and the third extension portion 23 are both vertically connected to the second extension portion 22 .
  • the size of the first end 221 of the second extension part 22 along the second direction Y may be equal to or larger than the size of the first extension part 21 in the second direction Y.
  • the second end 222 The size in the second direction Y may be equal to or larger than the size of the third extension portion 23 in the second direction Y.
  • the epitaxial structure 2 located on the substrate 1 in FIG. 2 can be etched to form a plurality of structures including the first epitaxial portion 21, the second epitaxial portion 22 and the third epitaxial portion 23. In order to be more For clarity, only one of the structures is shown in FIG. 3 .
  • the upper surface and both sides of the portion of the second epitaxial portion 22 located between the first end 221 and the second end 222 are blocked, and an etching process is used to remove the first epitaxial portion 21 and the second epitaxial portion.
  • the first end 221 and the second end 222 of 22 and each sacrificial layer 201 of the third epitaxial portion 23 form a plurality of first spaces C1 to be filled.
  • the portion of the second epitaxial portion 22 located between the first end 221 and the second end 222 can be continued to be blocked, and the first to-be-filled space C1 is filled with an insulating layer 203.
  • the insulating layer 203 can be silicon nitride, silicon oxynitride, and At least one of silicon oxides to act as an insulator.
  • the bit line structure 210 includes a plurality of bit lines 211 stacked along the first direction Z.
  • S120 may include: removing the semiconductor layer 202 in the first epitaxial portion 21 to form a plurality of second spaces C2 to be filled; The first conductive material is filled to form a bit line structure 210 .
  • the first conductive material may be filled using a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, which is not particularly limited here.
  • the first conductive material may be tungsten, titanium, nickel, aluminum, platinum, etc.
  • the first conductive material filled in the second to-be-filled space C2 forms the bit line 211 of each bit line structure 210 .
  • the insulating layer 203 and the first conductive material filled in the first space C1 to be filled form a bit line structure 210 .
  • the method of the embodiment of the present disclosure also includes: forming the bit line structure 210 into a ladder structure along the first direction Z, exposing at least part of the upper surface of the bit lines 211 of each layer; A plurality of first terminals 240 are respectively formed on 211 .
  • bit line structure 210 in the bit line structure 210 , a plurality of bit lines 211 stacked from top to bottom along the first direction Z include a first bit line, a second bit line... and an Nth bit.
  • Line, N is a positive integer greater than 1.
  • Forming the bit line structure 210 into a ladder structure along the first direction Z includes: as shown in Figure 12, forming a mask layer 212 with a first opening K1 on the bit line structure 210, the capacitor structure 230 and the transistor structure 220.
  • the first opening K1 is located above the first bit line, and the area of the first opening K1 is smaller than the area of the upper surface of the first bit line; as shown in Figure 13, the first bit line is etched along the first opening K1, so that the first opening K1 Through the first bit line; as shown in Figure 14, remove part of the mask layer 212 from the first opening K1 toward the direction close to the transistor 224 (the source 225 as shown in the figure), and expand the first opening K1 for better clarity. , the enlarged part of the first opening K1 is called the second opening K2; as shown in Figure 15, continue to etch the second bit line along the first opening K1, and at the same time etch the first bit line along the second opening K2, so that the second bit line is etched along the second opening K2.
  • An opening K1 continues to extend downward and penetrates the second bit line, exposing part of the upper surface of the third bit line.
  • the second opening K2 penetrates the first bit line, exposing part of the upper surface of the second bit line.
  • the N-1th opening penetrates the first bit line
  • the N-2th opening penetrates the first bit line and the second bit line, exposing part of the upper surface of the second bit line... ...
  • the first opening penetrates the N-1 bit line and exposes part of the upper surface of the N-th bit line.
  • the mask layer 212 is removed to expose the upper surface of the first bit line to form a ladder structure.
  • the upper surface of each ladder is is the upper surface of the bit line 211 of the corresponding layer.
  • bit line structure 210 In order to more clearly show the specific process of forming the ladder structure of the bit line structure 210, only part of the bit line structure 210 is shown in FIGS. 12 to 15 of the present disclosure, because during this process, the mask layer 212 always covers The transistor structure 220 (or the second epitaxial part 22 ) and the capacitor structure 230 (or the third epitaxial part 23 ) are not explained. Other processing is performed and therefore these structures are not shown.
  • the bit line 211 needs to be connected to the peripheral circuit. Therefore, a first binding post 240 is formed on the surface of each step, and a wire is connected to each first binding post 240 to realize the connection between the bit line 211 and the peripheral circuit. Peripheral circuit connections. Forming the bit line structure 210 into a ladder structure can form a space for the first connecting post 240. While realizing the connection between the bit line 211 of each layer and the peripheral circuit, it also saves the internal space of the semiconductor structure and improves the efficiency of the semiconductor structure. performance.
  • the capacitor structure 230 includes a plurality of capacitors 231 stacked along the first direction Z.
  • the insulating layer 203 is filled into the first spaces C1 to be filled.
  • this step can be performed simultaneously with the formation of the insulating layer 203 on the first epitaxial portion 21 , or can be performed separately, and is not specifically limited here.
  • the semiconductor layer 202 of the third epitaxial portion 23 is removed to form a plurality of third spaces to be filled (not shown in the figure), and each capacitor 231 is formed in each of the third spaces to be filled.
  • a lower electrode layer is first deposited in the third space to be filled, a dielectric layer is deposited on the lower electrode layer, and an upper electrode layer is deposited on the dielectric layer.
  • the lower electrode layer, dielectric layer and upper electrode layer form the capacitor 231.
  • the capacitor 231 formed in is a barrel capacitor.
  • the insulating layer 203 is not filled first, but the bit line structure 210 (or the first epitaxial part 22) and the transistor structure 220 (the second epitaxial part 22) are
  • the upper electrode layer is shielded, and an upper electrode layer is deposited on the surface of each semiconductor layer 202 of the third epitaxial portion 23 so that the upper electrode layer covers each surface of the semiconductor layer 202.
  • a dielectric layer is deposited on each surface of the upper electrode layer.
  • a lower electrode layer is deposited on each surface of the layer to form each capacitor 231, and then an insulating layer 203 is formed in each first space C1 to be filled.
  • the capacitor 231 formed in this embodiment is a columnar capacitor.
  • the different processes in the above different embodiments are mainly caused by the different structures of the capacitor 231.
  • the capacitor 231 can be formed between adjacent insulating layers 203 and electrically connected to the transistor structure 220, there is no special limitation here.
  • the The capacitor 231 adopts a deposition process, which may be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and is not specifically limited here.
  • a transistor structure 220 extending along the second direction Y is formed on the substrate 1.
  • the transistor structure 220 includes a plurality of transistors 224 stacked along the first direction Z; the transistor structure 220 is in the second direction Y. It has a first end 221 and a second end 222; the first end 221 is connected to the bit line structure 210, and the second end 222 is connected to the capacitor structure 230.
  • the bit line structure 210 and the capacitor structure 230 are located on opposite sides of the transistor structure 220; first The direction Z is perpendicular to the second direction Y.
  • the bit line structure 210 and the capacitor structure 230 are located on opposite sides of the transistor structure 220 in the third direction X. In the layout of semiconductor devices, this semiconductor structure can further save space, increase the unit density of the semiconductor structure, and improve storage performance.
  • the portion of the second extension portion 22 between the first end 221 and the second end 222 is the middle part of the second extension portion 22
  • the bit line structure 210 (or The first epitaxial part 21) has a first distance d1 from the middle part in the second direction Y
  • the capacitor structure 230 (or the third epitaxial part 23) has a second distance d2 from the middle part in the second direction Y.
  • the size of the first end 221 in the second direction Y is larger than the size of the first extension portion 21 in the second direction Y
  • the size of the second end 222 in the second direction Y is larger than the size of the third extension portion 23 size in the second direction Y
  • the first extension portion 21 and the third extension portion 23 are respectively spaced from the middle portion of the second extension portion 22 .
  • the above-mentioned spacing is formed to prevent the capacitor 231 in the capacitor structure 230 from being electrically connected to the gate electrodes 227 in the plurality of transistors 224 in the transistor structure 220 at the same time, and also to prevent the bit line 211 in the bit line structure 210 from being electrically connected to the gate electrodes 227 in the transistor structure 220.
  • the gate electrodes 227 in the plurality of transistors 224 are electrically connected at the same time, ensuring the stability of the electrical performance of the semiconductor structure and improving the yield of the semiconductor structure.
  • S140 may include S141 ⁇ S143.
  • the first end 221 and the second end 222 of the first epitaxial part 21 , the second epitaxial part 22 and the third epitaxial part 23 can be blocked (the shielding part is not shown in the figure) and removed by an etching process.
  • the sacrificial layer 201 in the middle of the second epitaxial portion 22 forms a gap G.
  • S142 Form the gate dielectric layer 2241 on the surface of the semiconductor layer 202 in the middle part of the second epitaxial part 22.
  • the first end 221 and the second end 222 of the second epitaxial portion 22 are used to form the source electrode 225 and the drain electrode 226. Specifically, parts other than the first end 221 and the second end 222 can be blocked. As shown in FIG. 7 , the first terminal 221 and the second terminal 222 are ion-doped to form the source electrode 225 and the drain electrode 226 .
  • the semiconductor layer 202 of the second epitaxial portion 22 between the source electrode 225 and the drain electrode 226 forms a channel 223 of the transistor 224 . As shown in FIG.
  • a deposition process can be used to form a gate dielectric layer 2241 on the surface of the channel 223 to insulate the channel 223 from the subsequently formed gate electrode 227 .
  • a mask layer may be formed on the second epitaxial part 22 , and the mask layer may be silicon oxide or silicon nitride.
  • the mask layer may be etched to expose the middle part of the second epitaxial part 22 , and a gate dielectric may be deposited in the middle part.
  • the material of the gate dielectric layer 2241 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride, and is not specifically limited here.
  • S143 Form the gate electrode 227 on the surface of the gate dielectric layer 2241, and fill the gap G with the gate electrode 227.
  • a diffusion barrier layer 2271 is formed on the surface of the gate dielectric layer 2241 .
  • the material of the diffusion barrier layer 2271 may be titanium nitride (TiN) or tantalum nitride (TaN).
  • the gap G between the diffusion barrier layers 2271 is filled with a conductive layer 2272.
  • the material of the conductive layer 2272 can be tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), silver ( Ag), gold (Au) or a combination thereof.
  • a diffusion barrier layer 2271 is formed on the surface of the gate dielectric layer 2241, which can prevent the material of the conductive layer 2272 from penetrating into the semiconductor layer 202, ensuring the stability of the semiconductor structural performance.
  • the diffusion barrier layer 2271 of this embodiment is conductive, and together with the conductive layer 2272, forms the gate electrode 227 of the transistor 224 in the transistor structure 220.
  • a conductive layer 2272 can be formed on the surface of the gate dielectric layer 2241 and in the gap G.
  • the material of the conductive layer 2272 can be doped Si, doped Ge, tungsten silicide (WSi), cobalt silicide (CoSi). ), titanium silicide (TiSi) or combinations thereof.
  • the diffusion barrier layer 2271 is not formed on the surface of the gate dielectric layer 2241.
  • the conductive layer 2272 is the gate electrode 227 of the transistor 224 in the transistor structure 220 .
  • the gate electrode 227 formed in the above embodiment is filled between the transistors 224 of each layer, so that the gate electrodes 227 of each transistor 224 are electrically connected. Therefore, the gate electrode 227 of the transistor structure 220 can also be used as a word line and Peripheral circuit connections. Of course, metal can also be deposited on the surface of the gate electrode 227 to form a word line, which is not particularly limited here.
  • the transistor 224 formed in the above embodiment of the present disclosure is a Gate All Around transistor.
  • the size of the capacitor 231 in the first direction Z may increase.
  • each layer of the capacitor is deposited on a semiconductor. on layer 202.
  • the size of the capacitor 231 in the first direction Z will be larger than the size of the drain electrode 226, if there is no gap between the capacitor structure 230 and the gate electrode 227 of the transistor structure 220 (the middle part of the second epitaxial portion 22).
  • the capacitor 231 may be electrically connected to the conductive layer 2272 of the gate electrode 227, causing the multi-layer capacitor 231 to be electrically connected to the multi-layer gate electrode 227, causing the semiconductor structure to not work properly, and the bit line structure 210 may have the same problem.
  • the problem will not be discussed again here. Therefore, as shown in FIG. 11 , a second gap d2 is left between the capacitor structure 230 and the gate electrode 227 in the second direction Y, and a first gap d2 is left between the bit line structure 210 and the gate electrode 227 in the second direction Y. , which can solve the above problems.
  • the gate electrode 227 formed in the above embodiment can be formed as a part of the semiconductor structure together with the bit line structure 210 of the ladder structure.
  • S140 may include S141 to S144'.
  • S141 Remove the sacrificial layer 201 in the middle part of the second epitaxial part 22 to form the gap G. This step is the same as S141 in the above embodiment.
  • S142 Form the gate dielectric layer 2241 on the surface of the semiconductor layer 202 in the middle part of the second epitaxial part 22. This step is the same as S142 in the above embodiment.
  • a mask layer may be formed on the second epitaxial part 22 , and the mask layer may be silicon oxide or silicon nitride.
  • the mask layer may be etched to expose the middle part of the second epitaxial part 22 , and a gate dielectric may be formed in the middle part.
  • S143' Form the gate electrode 227 on the surface of the gate dielectric layer 2241, and the gate electrode 227 extends along the third direction X or the fourth direction P (not shown in the figure) on one side of the second epitaxial portion 22 and is in contact with the position.
  • the line structure 210 and the capacitor structure 230 are not in contact, and the third direction X, the fourth direction P and the second direction Y are located in a plane parallel to the substrate 1 .
  • the gate electrode 227 extends along the third direction X. In other embodiments, the gate electrode 227 It can extend along the fourth direction P.
  • Those skilled in the art can determine the extension direction of the gate electrode 227 according to the specific structural settings of the bit line structure 210, the transistor structure 220 and the capacitor structure 230, and there is no special limitation here.
  • the gate electrode 227 can be formed using a deposition process, including forming the gate electrode 227 on the surface of the gate dielectric layer 2241, and the gate electrode 227 extends from the gate dielectric layer 2241 along the third direction X or the fourth direction P toward the second epitaxy. One side of portion 22 extends.
  • S144' In the Among the multi-layered gate electrodes 227 stacked in one direction Z, an insulating material layer 2273 is filled between adjacent gate electrodes 227 .
  • the third direction The gate electrode 227 is formed, and an insulating material layer 2273 is formed on the gate electrode 227, and finally the gate electrode 227 and the insulating material layer 2273 are formed in a spaced stack.
  • the structure is sufficient, and there are no special restrictions here.
  • the transistor 224 formed in the above embodiment of the present disclosure is a gate all around transistor.
  • the method of the embodiment of the present disclosure also includes: forming the stacked multi-layer gate electrodes 227 into a ladder structure, exposing at least part of the upper surface of each layer of gate electrodes 227; A plurality of second terminals 250 are respectively formed.
  • the process of forming the stacked multi-layer gate electrode 227 into a ladder structure is the same as the process of forming the bit line structure 210 into a ladder structure, and will not be described again here.
  • the surface of each step is the surface of the gate electrode 227 of the layer.
  • a second binding post 250 is formed on the exposed surface of the gate electrode 227 of each layer to connect to the wire and further to the peripheral circuit.
  • Forming the stacked multi-layer gate electrodes 227 into a ladder structure can form a space for the second terminal 250. While realizing the connection between each layer of gate electrodes 227 and peripheral circuits, it also saves the space occupied by the semiconductor structure and improves the efficiency of the semiconductor structure. Properties of Semiconductor Structures.
  • the method may further include: forming a conductive connection 260 on an end of the bit line structure 210 along the first direction Z and away from the transistor structure 220 , and The conductive connectors 260 are connected to each bit line 211 respectively.
  • the conductive connector 260 may be a wire, a conductive sheet, etc., and is not particularly limited here.
  • the method for preparing the semiconductor structure according to the embodiment of the present disclosure may further include: performing ion doping on the first end 221 and the second end 222 of the second epitaxial part 22 to form the source electrode 225 of the transistor structure 220 respectively. and drain 226.
  • the source electrode 225 that is connected to the bit line 211 in the bit line structure 210 is metal silicided to form a bit line contact 228 ; at least the portion of the drain electrode 226 that is connected to the capacitor 231 in the capacitor structure 230 is The connected parts are metal silicided to form capacitive contacts 229 .
  • the first end 221 and the second end 222 of the second epitaxial portion 22 may be ion doped through an ion implantation process to form the source electrode 225 and the drain electrode 226 of the transistor 224 .
  • FIG. 9 at least the portion of the source electrode 225 that is connected to the bit line 211 in the bit line structure 210 is subjected to a metal silicide treatment to form a metal silicide on the connected portion to form a bit line contact 228 to lower the bit line 211 and the source electrode 225.
  • the portion of the drain electrode 226 connected to the capacitor 231 in the capacitor structure 230 is metal silicided to form a capacitor contact 229 to reduce the resistance between the capacitor 231 and the drain electrode 226.
  • the metal material for metal silicide treatment can be at least one of Co, Ni, Pt, Ti, Ta, Mo and W, which is not specifically limited here.
  • the portions of the source electrode 225/drain electrode 226 forming the bit line contact 228/capacitor contact 229 can at least be connected to the bit line 211/capacitor 231 to reduce resistance.
  • the entire surface of the source electrode 225/drain electrode 226 can be subjected to a certain degree of metal silicide treatment to form a larger contact area.
  • the bit line structure 210 and the capacitor structure 230 are disposed on opposite sides of the transistor structure 220 along the third direction X to form a semiconductor structure.
  • this semiconductor structure can further save space, increase the unit density of the semiconductor structure, improve storage performance, and have a simpler structure.
  • the sacrificial layer 201 between the first end 221 and the second end 222 of the second epitaxial part 22 forms a gap G to form multiple layers of mutually spaced channels 223, which makes the preparation process simpler and can effectively improve the preparation of semiconductor structures. Yield.
  • Embodiments of the present disclosure also provide a semiconductor structure.
  • the semiconductor structure includes: a substrate 1 , a bit line structure 210 , a capacitor structure 230 and a transistor structure 220 .
  • the bit line structure 210 is located on the substrate 1 , and the bit line structure 210 includes a plurality of bit lines 211 stacked along the first direction Z.
  • the capacitor structure 230 is located on the substrate 1 , and the capacitor structure 230 includes a plurality of capacitors 231 stacked along the first direction Z.
  • the transistor structure 220 is located on the substrate 1 and extends along the second direction Y.
  • the transistor structure 220 includes a plurality of transistors 224 stacked along the first direction Z.
  • the transistor structure 220 has a first end 221 and a second end in the second direction Y.
  • the first end 221 is connected to the bit line structure 210
  • the second end 222 is connected to the capacitor structure 230
  • the transistor structure 220 and the capacitor structure 230 are located on opposite sides of the transistor structure 220 along the third direction X; wherein, the first direction Z Perpendicular to the base 1, the second direction Y and the third direction X lie in planes parallel to the base.
  • the bit line structure 210 in the embodiment of the present disclosure includes a plurality of first insulating layers (insulating layers 203 ) and a plurality of bit lines 211 stacked at intervals along the first direction Z.
  • the bit line structure 210 is a ladder structure, and at least part of the upper surface of each bit line 211 is exposed.
  • the semiconductor structure also includes a plurality of first connecting posts 240, respectively located on the exposed upper surfaces of the plurality of bit lines 211 in a ladder structure, for connecting with peripheral circuits.
  • the transistor 224 in the transistor structure 220 includes a channel 223 (refer to FIG. 7 ), a gate dielectric layer 2241 , a diffusion barrier layer 2271 and a conductive layer 2272 .
  • the channel 223 is located between the first end 221 and the second end 222 , the gate dielectric layer 2241 is located on the surface of the channel 223 , the diffusion barrier layer 2271 is located on the surface of the gate dielectric layer 2241 , and the conductive layer 2272 is located on the adjacent transistor 224 between the diffusion barrier layers 2271. Conductive layer 2272 and diffusion barrier layer 2271 form gate electrode 227 of transistor 224 .
  • the multi-layer stacked gate electrode 227 may also be a word line, connected to peripheral circuits.
  • the semiconductor structure in the embodiment of the present disclosure can be prepared by the preparation method described in any of the above embodiments, and will not be described again here.
  • the transistor 224 includes a channel 223 (refer to FIG. 7 ), a gate dielectric layer 2241 (not shown in the figure) and a gate electrode 227 .
  • the channel 223 is located between the first terminal 221 and the second terminal 222 of the transistor 224 .
  • the gate dielectric layer 2241 is located on the surface of the channel 223 .
  • the gate electrode 227 is located on the surface of the gate dielectric layer 2241 and extends on one side of the transistor 224 along the third direction P and the third direction
  • the semiconductor structure also includes a plurality of second binding posts 250, respectively located on the plurality of gate electrodes 227 in a stepped structure, to connect the gate electrodes 227 with peripheral circuits; an insulating material layer 2273, located adjacent to between the gate electrodes 227 so that adjacent gate electrodes 227 are insulated from each other.
  • the first direction Z, the second direction Y and the third direction can form a space for the second binding post 250. While realizing the connection between the gate electrode 227 of each layer and the peripheral circuit, the size of the bit line structure 210 in its extension direction can be reduced, saving the space occupied by the semiconductor structure. , further reducing the overall size of the semiconductor structure and improving the performance of the semiconductor structure.
  • the first terminal 221 of the transistor 224 may be the source 225, and the second terminal 222 of the transistor 224 may be the drain. 226 , the transistor 224 also includes: a bit line contact 228 and a capacitor contact 229 .
  • the bit line contact 228 is located between the source electrode 225 and the bit line 211 of the bit line structure 210 to reduce the resistance between the bit line 211 and the source electrode 225;
  • the capacitor contact 229 is located between the drain electrode 226 and the capacitor of the capacitor structure 230 231 to reduce the resistance between capacitor 231 and drain 226.
  • the bit line structure 210 has a first distance d1 from the gate electrode 227 in the second direction Y, and the capacitor structure has a second distance d2 from the gate electrode 227 in the second direction Y, which can avoid capacitance.
  • Contact between the structure 230, the transistor structure 220, and the bit line structure 210 results in electrical connection with each other, ensuring the stability of the electrical performance of the semiconductor structure.
  • the capacitor structure 230 includes a plurality of second insulating layers (insulating layers 203 ) and a plurality of capacitors 231 stacked at intervals along the first direction Z.
  • the capacitor 231 in the embodiment of the present disclosure may be a columnar electrode or a barrel electrode, which is not limited here.
  • the bit line structure 210 and the capacitor structure 230 are located on opposite sides of the transistor 224 structure 220 along the third direction X.
  • the semiconductor structure can further save space and improve the semiconductor structure.
  • the unit density improves storage performance and the structure is simpler.
  • the semiconductor device includes a first semiconductor unit 1000 .
  • the first semiconductor unit 1000 includes a first semiconductor structure 1100 and a second semiconductor structure 1200 .
  • the first semiconductor structure 1100 has a first line structure 1110, a first transistor structure 1120 and a first capacitor structure 1130.
  • the first transistor structure 1120 extends in the second direction Y, the first line structure 1110 and the first capacitor structure 1130 Located on opposite sides of the first transistor structure 1120 in the third direction X.
  • the second semiconductor structure 1200 has a second bit line structure 1210, a second transistor structure 1220 and a second capacitor structure 1230.
  • the second transistor structure 1220 extends along the second direction Y.
  • the second bit line structure 1210 and the second capacitor structure 1230 are located at Opposite sides of the second transistor structure 1220 in the third direction X.
  • the projection of the first capacitor structure 1130 along the second direction Y at least partially coincides with the second capacitor structure 1230 .
  • the projection of the first transistor structure 1120 along the third direction X coincides with the second transistor structure 1220 .
  • the second direction Y and the third direction X are perpendicular to each other. This layout of the first semiconductor structure 1100 and the second semiconductor structure 1200 minimizes the space occupied by the first semiconductor unit 1000 in the semiconductor device.
  • the first transistor structure 1120 and the second transistor structure 1220 respectively have opposite first and second sides in the third direction X, wherein the first bit line structure 1110 and the second capacitor structure 1230 are located on the first side, and the first capacitor structure 1130 and the second bit line structure 1210 are located on the second side.
  • the first bit line structure 1110 is located on the first side of the first transistor structure 1120
  • the second capacitor structure 1230 is located on the first side of the second transistor structure 1220
  • the first capacitor structure 1130 is located on the first side of the first transistor structure 1120
  • the second bit line structure 1210 is located on the second side of the second transistor structure 1220 .
  • the semiconductor device in the embodiment of the present disclosure also includes a second semiconductor unit 2000.
  • the second semiconductor unit 2000 has the same structure as the first semiconductor unit 1000; the second semiconductor unit 2000 and the first semiconductor unit 1000 are in Set at intervals in the second direction Y and the third direction X.
  • each semiconductor unit in the semiconductor device has the same structure. As shown in Figure 22, these semiconductor units are arranged at intervals. For example, multiple semiconductor units can be arranged in a matrix, and the spacing between adjacent semiconductor units can be the same. It can also be different, as long as the occupied space can be reduced as much as possible without affecting the performance of the semiconductor device, there is no special limit here.
  • the semiconductor device further includes a third semiconductor unit 3000.
  • the body unit 3000 has a structure symmetrical with the first semiconductor unit 1000 about the symmetry axis F; the symmetry axis F extends along the third direction X; the third semiconductor unit 3000 and the first semiconductor unit 1000 are in the second direction Y and the third direction X Upper interval setting.
  • the third semiconductor unit 3000 includes the same first semiconductor structure 1100 and the second semiconductor structure 1200 as the first semiconductor unit 1000, but is symmetrical with the first semiconductor unit 1000 about the symmetry axis F.
  • the first semiconductor unit 1000 and the third semiconductor unit 3000 shown in FIG. 21 can be regarded as a whole.
  • a plurality of the wholes can be arranged at intervals in the second direction Y and the third direction X, as shown in FIG.
  • the whole body can be arranged in a matrix or non-equally spaced arrangement, as long as the occupied space can be minimized without affecting the performance of the semiconductor device.
  • the first semiconductor unit 1000, the second semiconductor unit 2000 and the third semiconductor unit 3000 can also be provided in the semiconductor device at the same time.
  • the three can be spaced apart in the second direction Y and the third direction X, such as in the second direction Y. above, the three can be arranged in the following manner: the first semiconductor unit 1000, the second semiconductor unit 2000, and the third semiconductor unit 3000 are arranged in sequence, or the first semiconductor unit 1000, the third semiconductor unit 3000, the second semiconductor unit 3000, and the third semiconductor unit 3000.
  • the units 2000 are arranged at intervals in sequence, and of course they may not be arranged in a specific order; in the third direction 3000 are arranged at intervals in sequence, or the first semiconductor unit 1000, the third semiconductor unit 3000, and the second semiconductor unit 2000 are arranged at intervals in sequence. Of course, they may not be arranged in a specific order.
  • the semiconductor device should be able to arrange as many semiconductor structures as possible in a limited space without affecting the performance of the semiconductor device, improving storage performance and avoiding waste of space.
  • the bit line structure 210 and the capacitor structure are provided on opposite sides of the transistor structure 220 along the third direction X to form a semiconductor structure.
  • this semiconductor structure can further save space, increase the unit density of the semiconductor structure, improve storage performance, and have a simpler structure.
  • the sacrificial layer 201 between the first end 221 and the second end 222 of the second epitaxial portion 22 is removed to form a gap G to form multiple layers of mutually spaced channels 223, making the preparation process more efficient. It is simple and can effectively improve the production yield of semiconductor structures.

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Abstract

一种半导体结构的制备方法、半导体结构及半导体器件。该方法包括：提供基底（1）并在基底（1）上分别形成位线结构（210）、电容结构（230）和沿第二方向（Y）延伸的晶体管结构（220）。其中，位线结构（210）中包括沿第一方向（Z）堆叠的多个位线（211）；电容结构（230）中包括沿第一方向（X）堆叠的多个电容器（231）；晶体管结构（220）中包括沿第一方向（Z）堆叠的多个晶体管（224）；晶体管结构（220）在第二方向（Y）上具有第一端（221）和第二端（222）；第一端（221）连接位线结构（210），第二端（222）连接电容结构（230），位线结构（210）与电容结构（230）位于晶体管结构（220）的沿第三方向（X）相对的两侧；第一方向（Z）垂直于基底（1），第二方向（Y）和第三方向（X）位于平行于基底（1）的平面内。

Description

半导体结构的制备方法、半导体结构及半导体器件
交叉引用
本公开要求于2022年8月30日提交的申请号为202211048488.6、名称为“半导体结构的制备方法、半导体结构及半导体器件”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构的制备方法、半导体结构及半导体器件。
背景技术
DRAM(Dynamic Random Access Memory，动态随机存取存储器)是常用的半导体存储器件，由许多重复的存储单元组成，储存单元与外围电路连接执行存储功能。每个存储单元中通常包括晶体管、电容器和位线等结构。DRAM集成度越高，其可容纳的存储单元的数目就越多，其性能也更为优异。
随着尺寸的进一步微缩，存储单元出现堆叠式的存储结构。然而，目前的堆叠式的存储结构中，晶体管、电容器和位线的结构设置在一定程度上存在浪费空间的问题，不能进一步提高存储单元的数目。
发明内容
本公开实施例提供一种半导体结构的制备方法、半导体结构及半导体器件，能够进一步节省空间，提高半导体结构的单位密度，提升存储性能。
本公开实施例提供一种半导体结构的制备方法，包括：提供基底；在所述基底上形成位线结构，所述位线结构中包括沿第一方向堆叠的多个位线；在所述基底上形成电容结构，所述电容结构中包括沿所述第一方向堆叠的多个电容器；在所述基底上形成沿第二方向延伸的晶体管结构，所述晶体管结构中包括沿所述第一方向堆叠的多个晶体管；所述晶体管结构在所述第二方向上具有第一端和第二端；所述第一端连接所述位线结构，所述第二端连接所述电容结构，所述位线结构与所述电容结构位于所述晶体管结构的沿第三方向相对的两侧；所述第一方向垂直于所述基底，所述第二方向和所述第三方向位于平行于所述基底的平面内。
根据本公开的一些实施例，所述方法还包括：在所述基底上形成多个沿所述第一方向堆叠的外延结构，所述外延结构包括沿所述第一方向依序堆叠的牺牲层和半导体层；蚀刻所述外延结构，使所述外延结构具有第一外延部、第二外延部和第三外延部，所述第二外延部沿所述第二方向延伸，所述第一外延部和所述第三外延部分别连接于所述第二外延部的沿所述第二方向的第一端和第二端；且所述第一外延部和所述第三外延部位于所述第二外延部的沿所述第三方向的相对的两侧；去除所述第二外延部的所述第一端和所述第二端、以及所述第一外延部和所述第三外延部的各个牺牲层，形成多个第一待填充空间；向所述第一待填充空间中填充绝缘层。
根据本公开的一些实施例，在所述基底上形成位线结构，包括：去除所述第一外延部中的半导体层，形成多个第二待填充空间；向所述第二待填充空间中填充第一导电材料，形成所述位线结构。
根据本公开的一些实施例，所述方法还包括：沿所述第一方向将所述位线结构形成阶梯结构，露出每层所述位线的至少部分上表面；在呈阶梯结构的多层所述位线上分别形成多个第一接线柱。
根据本公开的一些实施例，所述第二外延部还包括位于所述第一端和所述第二端之间的中部，所述位线结构在所述第二方向上与所述中部具有第一间隔，所述电容结构在所述第二方向上与所述中部具有第二间隔；在所述基底上形成沿第二方向延伸的晶体管结构，包括：去除所述第二外延部的所述中部的所述牺牲层，形成间隙；在所述第二外延部的中部的所述半导体层的表面形成栅介质层；在所述栅介质层的表面形成栅电极，且所述栅电极填充所述间隙。
根据本公开的一些实施例，所述第二外延部还包括位于所述第一端和所述第二端之间的中部，所述位线结构在所述第二方向上与所述中部具有第一间隔，所述电容结构在所述第二方向上与所述中部具有第二间隔；在所述基底上形成沿第二方向延伸的晶体管结构，包括：去除所述第二外延部的所述中部的所述牺牲层；在所述第二外延部的所述中部的所述半导体层的表面形成栅介质层；在所述栅介质层的表面形成栅电极，且所述栅电极沿第三方向或第四方向在所述第二外延部的一侧延伸，且与所述位线结构或所述电容结构不接触；所述第四方向和所述第三方向位于平行于所述基底的平面内；在所述第一方向上堆叠的多层所述栅电极中，向相邻的所述栅电极之间填充绝缘材料层。
根据本公开的一些实施例，所述方法还包括：将堆叠的多层所述栅电极形成阶梯结构，露出每层所述栅电极的至少部分上表面；在呈阶梯结构的多层所述栅电极上分别形成多个第二接线柱。
根据本公开的一些实施例，所述方法还包括：在所述位线结构上沿所述第一方向且远离所述晶体管结构的一端形成导电连接件，且所述导电连接件分别与各所述位线连接。
根据本公开的一些实施例，在所述基底上形成沿第二方向延伸的晶体管结构，包括：对所述第二外延部的所述第一端和所述第二端进行离子掺杂，分别形成所述晶体管结构的源极和漏极；对所述源极的至少与所述位线结构中的位线连接的部分进行金属硅化处理，形成位线接触；对所述漏极的至少与所述电容结构中的电容器连接的部分进行金属硅化处理，形成电容接触。
本公开的一些实施例还提供了一种半导体结构，包括：基底、位线结构、电容结构和晶体管结构。
其中，位线结构位于所述基底上，所述位线结构中包括沿第一方向堆叠的多个位线；电容结构位于所述基底上，所述电容结构中包括沿所述第一方向堆叠的多个电容器；晶体管结构位于所述基底上并沿第二方向延伸，所述晶体管结构中包括沿所述第一方向堆叠的多个晶体管，所述晶体管结构在所述第二方向上具有第一端和第二端，所述第一端连接所述位线结构，所述第二端连接所述电容结构，且所述晶体管结构与所述电容结构位于所述晶体管结构的沿第三方向相对的两侧；其中，所述第一方向垂直于所述基底，所述第二方向和所述第三方向位于平行于所述基底的平面内。
根据本公开的一些实施例，所述晶体管包括：沟道，位于所述晶体管的第一端和第二端之间；栅介质层，位于所述沟道的表面；栅电极，位于所述栅介质层的表面，并沿所述第三方向或第四方向在所述晶体管的一侧延伸，且与所述位线结构或所述电容结构不接触，所述第四方向和所述第三方向位于平行于所述基底的平面内，多个沿所述第一方向堆叠的所述晶体管的多层栅电极为阶梯结构，每层所述栅电极的至少部分上表面露出。
所述半导体结构还包括：多个第二接线柱，分别位于呈阶梯结构的多层所述栅电极上；绝缘材料层，位于相邻的所述栅电极之间。
根据本公开的一些实施例，所述位线结构在所述第二方向上与所述栅电极具有第一间隔，所述电容结构在所述第二方向上与所述栅电极具有第二间隔。
根据本公开的一些实施例，所述晶体管的第一端为源极，所述晶体管的第二端为漏极，所述晶体管包括：位线接触，位于所述源极和所述位线结构的位线之间；电容接触，位于所述漏极和所述电容结构的电容器之间。
本公开的一些实施例还提供了一种半导体器件，包括第一半导体单元，所述第一半导体单元包括第一半导体结构，所述第一半导体结构具有第一位线结构、第一晶体管结构以及第一电容结构，所述第一晶体管结构沿第二方向延伸，所述第一位线结构和所述第一电容结构位于所述第一晶体管结构的在第三方向上相对的两侧；第二半导体结构，所述第二半导体结构具有第二位线结构、第二晶体管结构以及第二电容结构，所述第二晶体管结构沿第二方向延伸，所述第二位线结构和所述第二电容结构位于所述第二晶体管结构的在第三方向上相对的两侧；其中，所述第一电容结构沿第二方向的投影至少部分与所述第二电容结构重合；所述第一晶体管结构沿第三方向的投影与所述第二晶体管结构重合；其中，所述第二方向和所述第三方向相互垂直。
根据本公开的一些实施例，所述第一晶体管结构和所述第二晶体管结构分别在所述第三方向上具有相对的第一侧和第二侧，其中，所述第一位线结构和所述第二电容结构位于所述第一侧，所述第一电容结构和所述第二位线结构位于所述第二侧。
根据本公开的一些实施例，所述半导体器件还包括：第二半导体单元，所述第二半导体单元具有与所述第一半导体单元相同的结构；所述第二半导体单元和所述第一半导体单元在所述第二方向和所述第三方向上间隔设置。
根据本公开的一些实施例，所述半导体器件还包括：第三半导体单元，所述第三半导体单元具有与所述第一半导体单元关于对称轴对称的结构；所述对称轴沿所述第三方向延伸；所述第三半导体单元和所述第一半导体单元在所述第二方向和所述第三方向上间隔设置。
本公开实施例的半导体结构的制备方法，将位线结构与电容结构设于晶体管结构的沿第三方向相对的两侧，以形成半导体结构。在半导体器件的布局中，该半导体结构能够进一步节省空间，提高半导体结构的单位密度，提升存储性能。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一些实施例示出的半导体结构的制备方法的流程图。
图2为本公开一些实施例示出的在基底上形成外延结构的示意图。
图3为本公开一些实施例示出的形成具有各个外延部的外延结构的示意图。
图4为本公开一些实施例示出的在外延结构中形成第一待填充空间的示意图。
图5为本公开一些实施例示出的在外延结构中形成绝缘层的示意图。
图6为本公开一些实施例中示出的在外延结构中形成间隙的示意图。
图7为本公开一些实施例中示出的形成晶体管结构的栅极、漏极的示意图。
图8为本公开一些实施例示出的在沟道表面形成栅介质层的示意图；
图9为本公开一些实施例中示出的形成晶体管结构的栅电极的示意图。
图10为本公开一些实施例中示出的在第一外延部中形成第二待填充空间的示意图。
图11为本公开一些实施例中示出的形成有位线结构、电容结构和晶体管结构的半导体结构示意图。
图12至图15为本公开一些实施例中示出的位线结构形成阶梯结构的示意图。
图16为本公开一些实施例中示出的位线结构为阶梯结构的半导体结构的示意图。
图17为本公开另一些实施例中示出的栅电极为阶梯结构的半导体结构的示意图。
图18为本公开一些实施例中示出的形成晶体管结构的栅电极的方法流程图。
图19为本公开另一些实施例中示出的形成晶体管结构的栅电极的方法流程图。
图20为本公开一些实施例中示出的半导体器件的布局图。
图21为本公开一些实施例中示出的半导体器件的另一种布局图。
图22为本公开一些实施例中示出的半导体器件的另一种布局图。
图23为本公开一些实施例中示出的半导体器件的另一种布局图。
附图标记说明：
1、基底；2、外延结构；201、牺牲层；202、半导体层；203、绝缘层；21、第一外延部；22、第二外延部；221、第一端；222、第二端；223、沟道；23、第三外延部；210、位线结构；211、位线；212、掩膜层；K1、第一开口；K2、第二开口；220、晶体管结构；224、晶体管；2241、栅介质层；225、源极；226、漏极；227、栅电极；2271、扩散阻挡层；2272、导电层；2273、绝缘材料层；228、位线接触；229、电容接触；230、电容结构；231、电容器；240、第一接线柱；250、第二接线柱；260、导电连接件；1000、第一半导体单元；1100、第一半导体结构；1110、第一位线结构；1120、第一晶体管结构；1130、第一电容结构；1200、第二半导体结构；1210、第二位线结构；1220、第二晶体管结构；1230、第二电容结构；2000、第二半导体单元；3000、第三半导体单元；Z、第一方向；Y、第二方向；X、第三方向；P、第四方向；C1、第一待填充空间；C2、第二待填充空间；G、间隙；F、对称轴；d1、第一间隔；d2、第二间隔。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在对本公开的不同示例性实施例的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能 性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。此外，权利要求书中的术语“第一”、“第二”等仅作为标记使用，不是对其对象的数字限制。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解，而有的操作/步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
另外，在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。
如图1至图17所示，本公开实施例提供了一种半导体结构的制备方法。其中，图1示出了本公开半导体结构的制备方法的流程图，图2至图17分别示出了在制备过程中的半导体结构的示意图，为了更加清晰地示出半导体结构的变化，图3至图17中省略了基底1。如图1所示，本公开实施例的半导体结构的制备方法包括步骤：S110～S140。
S110：提供基底1。
如图2所示，本公开实施例提供的基底1为半导体基底，基底1中形成有浅沟槽隔离(图中未示出)，浅沟槽隔离之间设有有源区。本公开实施例的基底1的材料可以为硅、碳化硅、氮化硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上层锗化硅或绝缘体上层锗等，此处不做特殊限定。
在提供基底1后，本公开实施例的半导体结构的制备方法还可以包括如下内容A～D。
A：如图2所示，在基底1上形成多个沿第一方向Z堆叠的外延结构2，外延结构2包括沿第一方向Z依序堆叠的牺牲层201和半导体层202。
其中，牺牲层201的材质可以是SiGe、氧化硅、氮化硅、碳氮化硅等，半导体层202可以是硅、碳化硅、绝缘体上硅等，只要半导体层202与牺牲层201之间具有较大的蚀刻选择比即可，例如在本实施例中，牺牲层201的材质选择SiGe，半导体层的材质选择Si，此处不做特殊限定。图2和图3中仅示出了三层依序堆叠的牺牲层201和半导体层202，还可以是四层、五层、六层或更多层，此处不做特殊限定。第一方向Z为垂直于基底1表面的方向。
B：蚀刻外延结构2，使外延结构2具有第一外延部21、第二外延部22和第三外延部23，第二外延部22沿第二方向Y延伸，第一外延部21和第三外延部23分别连接于第二外延部22的沿第二方向Y的第一端221和第二端222；且第一外延部21和第三外延部23位于第二外延部22的沿第三方向X相对的两侧。
具体地，可以在外延结构2上形成掩膜层，掩膜层具有图案，利用掩膜层的图案对外延结构2进行蚀刻，可以形成多个外延蚀刻结构，每个外延蚀刻结构可以包括第一外延部21、第二外延部22和第三外延部23。蚀刻工艺可以为湿法蚀刻或干法蚀刻，湿法蚀刻可以利用浓硫酸和双氧水作为蚀刻剂，通过调整蚀刻剂的浓度，可以控制蚀刻程度；干法蚀刻可以是等离子蚀刻，等离子体工艺采用的蚀刻气体可以为氯气，通过控制蚀刻气体的用量，可以控制蚀刻程度，此处不做特殊限定。
如图3所示，第二外延部22沿第二方向Y延伸，第二方向Y位于平行于基底1的平面内，即第 一方向Z与第二方向Y垂直。第二外延部22在第二方向Y上具有相对的第一端221和第二端222，第一外延部21连接于第二外延部22的第一端221、第三外延部23连接于第二外延部22的第二端222，并且第一外延部21和第三外延部23位于第二外延部22的沿第三方向X的相对的两侧。第三方向X与第二方向Y位于平行于基底1的平面内，第三方向X与第二方向Y具有夹角。在一些实施例中，如图3所示，第三方向X与第二方向Y垂直。在另一些实施例中，第三方向X可以与第二方向Y不垂直，也就是说，第二外延部22的形状与图3中示出的实施利中的形状可以不同，第二外延部22在第三方向X上具有相对的两侧，本领域技术人员可以根据第二外延部22的具体形状设定，只要能够满足第一外延部21和第三外延部23位于第二外延部22的相对的两侧，该相对的两侧并非是沿第二方向Y的两侧即可，此处不做特殊限定。
第一外延部21可以与第二外延部22之间具有第一夹角，第三外延部23可以与第二外延部22之间具有第二夹角，第一夹角可以等于第二夹角，即第一外延部21和第三外延部23平行地向远离第二外延部22的方向延伸，或者，第一夹角可以不等于第二夹角，即第一外延部21和第三外延部23分别沿不同的方向向远离第二外延部22的方向延伸，但无论是哪种情况，第一外延部21和第三外延部23的延伸方向均位于平行于基底1的平面内，使得第一外延部21、第二外延部22和第三外延部23形成大致呈“Z”形的结构。在一些实施例中，如图3所示，第一夹角和第二夹角相等且分别为90°，即第一外延部21和第三外延部23均与第二外延部22垂直连接。
继续参考图3，在一些实施例中，第二外延部22的第一端221沿第二方向Y的尺寸可以等于或大于第一外延部21在第二方向Y上的尺寸，第二端222在第二方向Y上的尺寸可以等于或大于第三外延部23在第二方向Y上的尺寸。另外，需要说明的是，图2中的位于基底1上的外延结构2经过蚀刻后可以形成多个包含第一外延部21、第二外延部22和第三外延部23的结构，为了能更加清晰地示出，图3中仅仅示出了其中一个结构。
C：去除第二外延部22的第一端221和第二端222、以及第一外延部21和第三外延部23的各个牺牲层201，形成多个第一待填充空间C1。
如图4所示，对第二外延部22的位于第一端221和第二端222之间的部分的上表面及两侧进行遮挡，采用蚀刻工艺去除第一外延部21、第二外延部22的第一端221和第二端222、第三外延部23的各个牺牲层201，形成多个第一待填充空间C1。
D：向第一待填充空间C1中填充绝缘层203。
可以继续遮挡第二外延部22的位于第一端221和第二端222之间的部分，向第一待填充空间C1中填充绝缘层203，绝缘层203可以是氮化硅、氮氧化硅和氧化硅中的至少一种，以起到绝缘的作用。
S120：在基底1上形成位线结构210，位线结构210中包括沿第一方向Z堆叠的多个位线211。
如图10和图11所示，在本公开实施例中，S120可以包括：去除第一外延部21中的半导体层202，形成多个第二待填充空间C2；向第二待填充空间C2中填充第一导电材料，形成位线结构210。
填充第一导电材料可以利用沉积工艺，如化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺，此处不做特殊限定。第一导电材料可以是钨、钛、镍、铝、铂等，填充于第二待填充空间C2中的第一导电材料形成各个位线结构210的位线211。填充于第一待填充空间C1中的绝缘层203与第一导电材料形成了位线结构210。
如图16所示，本公开实施例的方法还包括：沿第一方向Z将位线结构210形成阶梯结构，露出每层位线211的至少部分上表面；在呈阶梯结构的多个位线211上分别形成多个第一接线柱240。
具体地，如图12至图15所示，在位线结构210中，沿第一方向Z自上而下堆叠的多个位线211包括第一位线、第二位线……第N位线，N为大于1的正整数。沿第一方向Z将位线结构210形成阶梯结构包括：如图12所示，在位线结构210、电容结构230和晶体管结构220上形成具有第一开口K1的掩膜层212，第一开口K1位于第一位线的上方，且第一开口K1的面积小于第一位线的上表面的面积；如图13所示，沿该第一开口K1蚀刻第一位线，使第一开口K1贯穿第一位线；如图14所示，自第一开口K1向靠近晶体管224(如图中所示的源极225)的方向去除部分掩膜层212，扩大第一开口K1，为了更加清楚地描述，将第一开口K1扩大的部分称为第二开口K2；如图15所示，沿第一开口K1继续蚀刻第二位线，同时沿第二开口K2蚀刻第一位线，使第一开口K1继续向下延伸贯穿第二位线，露出第三位线的部分上表面，第二开口K2贯穿第一位线，露出第二位线的部分上表面。重复上述方法，直至形成第N-1开口，该第N-1开口贯穿第一位线，第N-2开口贯穿第一位线和第二位线，露出第二位线的部分上表面……第一开口贯穿第N-1位线，并露出第N位线的部分上表面，除去掩膜层212，使第一位线的上表面露出，形成阶梯结构，每个阶梯的上表面均为对应层的位线211的上表面。
为了能够更加清晰地示出位线结构210形成阶梯结构的具体过程，本公开的图12至图15中仅示出了位线结构210的部分，由于在该过程中，掩膜层212一直覆盖晶体管结构220(或第二外延部22)和电容结构230(或第三外延部23)，并未对晶体管结构220(或第二外延部22)和电容结构230(或第三外延部23)进行其他处理，因此，未示出这些结构。
在本公开实施例中，位线211需要与外围电路连接，因此，在每个阶梯的表面上形成第一接线柱240，在每个第一接线柱240上连接导线，以实现位线211与外围电路连接。将位线结构210形成阶梯结构，能够对第一接线柱240形成让位空间，在实现了每层位线211与外围电路连接的同时，还节省了半导体结构的内部空间，提升了半导体结构的性能。
S130：在基底1上形成电容结构230，电容结构230中包括沿第一方向Z堆叠的多个电容器231。
如图3至图5所示，在一些实施例中，第三外延部23的各个牺牲层201被去除形成多个第一待填充空间C1后，向第一待填充空间C1中填充绝缘层203，该步骤可以与第一外延部21形成绝缘层203同时进行，也可以分别进行，此处不做特殊限定。去除第三外延部23的半导体层202，形成多个第三待填充空间(图中未示出)，在各个第三待填充空间中形成各个电容器231。例如，在第三待填充空间中先沉积下电极层，在下电极层上沉积电介质层，在电介质层上沉积上电极层，该下电极层、电介质层和上电极层形成电容器231，本实施例中形成的电容器231为桶状电容器。
在另一些实施例中，在形成第一待填充空间C1后，先不填充绝缘层203，而是对位线结构210(或第一外延部22)、晶体管结构220(第二外延部22)的部分进行遮挡，在第三外延部23的各个半导体层202的表面沉积上电极层，使上电极层包覆于半导体层202的各个表面，在上电极层的各个表面沉积电介质层，在电介质层的各个表面沉积下电极层，形成各个电容器231，之后再向各个第一待填充空间C1中形成绝缘层203。本实施例中形成的电容器231为柱状电容器。
上述不同实施例的不同工艺主要是由电容器231的不同结构导致的，只要能够在相邻的绝缘层203之间形成电容器231，并与晶体管结构220电连接即可，此处不做特殊限定。另外，上述实施例中形成 电容器231采用沉积工艺，该沉积工艺可以是化学气相沉积、物理气相沉积或原子层沉积等，此处不做特殊限定。
S140：如图11所示，在基底1上形成沿第二方向Y延伸的晶体管结构220，晶体管结构220中包括沿第一方向Z堆叠的多个晶体管224；晶体管结构220在第二方向Y上具有第一端221和第二端222；第一端221连接位线结构210，第二端222连接电容结构230，位线结构210与电容结构230位于晶体管结构220的相对的两侧；第一方向Z与第二方向Y垂直。位线结构210与电容结构230位于晶体管结构220的在第三方向X上的相对的两侧。在半导体器件的布局中，该半导体结构能够进一步节省空间，提高半导体结构的单位密度，提升存储性能。
本公开实施例中，如图6和图11所示，第二外延部22的位于第一端221和第二端222之间的部分为第二外延部22的中部，位线结构210(或第一外延部21)在第二方向Y上与该中部具有第一间隔d1，电容结构230(或第三外延部23)在第二方向Y上与该中部具有第二间隔d2。也就是说，第一端221在第二方向Y上的尺寸大于第一外延部21的在第二方向Y上的尺寸，第二端222在第二方向Y上的尺寸大于第三外延部23的在第二方向Y上的尺寸，且在第二方向Y上，第一外延部21和第三外延部23分别与第二外延部22的中部具有间隔。形成上述间隔，是为了防止电容结构230中的电容器231与晶体管结构220中的多个晶体管224中的栅电极227同时电连接，也防止位线结构210中的位线211与晶体管结构220中的多个晶体管224中的栅电极227同时电连接，确保半导体结构的电性能的稳定性，提高半导体结构的良率。
在一些实施例中，如图18所示，S140可以包括S141～S143。
S141：去除第二外延部22的中部的牺牲层201，形成间隙G。
如图6所示，可以将第一外延部21、第二外延部22的第一端221和第二端222以及第三外延部23遮挡(图中未示出遮挡部)，利用蚀刻工艺去除第二外延部22的中部的牺牲层201，形成间隙G。
S142：在第二外延部22的中部的半导体层202的表面形成栅介质层2241。
本公开实施例中，第二外延部22的第一端221和第二端222用于形成源极225和漏极226，具体地，可以将第一端221和第二端222以外的部分遮挡，如图7所示，对第一端221和第二端222进行离子掺杂，以形成源极225和漏极226。第二外延部22的位于该源极225和漏极226之间的半导体层202形成为晶体管224的沟道223。如图8所示，可以利用沉积工艺，在沟道223的表面形成栅介质层2241，以使沟道223与后续形成的栅电极227绝缘。具体地，可以在第二外延部22上形成掩膜层，该掩膜层可以是氧化硅或氮化硅，对掩膜层蚀刻，露出第二外延部22的中部，在该中部沉积栅介质层2241。栅介质层2241的材质可以是氮化硅、氧化硅和氮氧化硅中的至少一种，此处不做特殊限定。
S143：在栅介质层2241的表面形成栅电极227，且栅电极227填充间隙G。
如图9所示，在一些实施例中，在栅介质层2241的表面形成扩散阻挡层2271，扩散阻挡层2271的材质可以是氮化钛(TiN)、氮化钽(TaN)。在扩散阻挡层2271之间的间隙G中填充导电层2272，导电层2272的材质可以是钨(W)、钛(Ti)、钽(Ta)、铜(Cu)、铝(Al)、银(Ag)、金(Au)中或其组合。在栅介质层2241的表面形成扩散阻挡层2271，能够阻挡导电层2272的材料渗入半导体层202中，确保了半导体结构性能的稳定性。本实施例的扩散阻挡层2271能够导电，其与导电层2272共同形成晶体管结构220中的晶体管224的栅电极227。
在另一些实施例中，可以在栅介质层2241的表面以及间隙G中形成导电层2272，该导电层2272的材质可以为掺杂Si、掺杂Ge、硅化钨(WSi)、硅化钴(CoSi)、硅化钛(TiSi)或其组合。与上述实施例不同的是，由于上述导电层2272的材料不会渗入到半导体层202中，因此，并未在栅介质层2241的表面形成扩散阻挡层2271。该导电层2272为晶体管结构220中的晶体管224的栅电极227。
上述实施例中形成的栅电极227由于填充于各层晶体管224之间，使得各个晶体管224的栅电极227之间是电连接的，因此，该晶体管结构220的栅电极227也可以作为字线与外围电路连接。当然，也可以在栅电极227的表面再沉积金属形成字线，此处不做特殊限定。本公开上述实施例中形成的晶体管224为全环绕栅极(Gate All Around)晶体管。
如图11所示，需要说明的是，在制备电容结构230的电容器231时，电容器231在第一方向Z上的尺寸可能会增加，如在形成柱状电容器时，电容器的各个层是沉积于半导体层202上的。在这种情况下，电容器231的在第一方向Z上的尺寸会大于漏极226的尺寸，如果在电容结构230与晶体管结构220的栅电极227(第二外延部22的中部)之间不设置第二间隔d2，则电容器231可能会与栅电极227的导电层2272电连接，导致多层电容器231与多层栅电极227电连接，使半导体结构不能正常工作，位线结构210可能存在同样的问题，此处不再赘述。因此，如图11所示，在电容结构230和栅电极227在第二方向Y上留有第二间隔d2，在位线结构210和栅电极227在第二方向Y上留有第一间隔d2，就能够解决上述问题。
如图16所示，上述实施例形成的栅电极227能够与阶梯结构的位线结构210形成为半导体结构的一部分。
在本公开的另一些实施例中，如图19所示，S140可以包括S141～S144’。
S141：去除第二外延部22的中部的牺牲层201，形成间隙G。该步骤与上述实施例中的S141相同。
S142：在第二外延部22的中部的半导体层202的表面形成栅介质层2241。该步骤与上述实施例中的S142相同。
具体地，可以在第二外延部22上形成掩膜层，该掩膜层可以是氧化硅或氮化硅，对掩膜层蚀刻，露出第二外延部22的中部，在该中部形成栅介质层2241。
S143’：在栅介质层2241的表面形成栅电极227，且栅电极227沿第三方向X或第四方向P(图中未示出)在第二外延部22的一侧延伸，且与位线结构210和电容结构230不接触，第三方向X、第四方向P和第二方向Y位于平行于基底1的平面内。
其中，第四方向P与第三方向X之间具有夹角，在一些实施例中，如图17所示，栅电极227沿着第三方向X延伸，在另一些实施例中，栅电极227可以沿着第四方向P延伸。栅电极227分别与位线结构210、电容结构230不接触是指，栅电极227无论沿第三方向X延伸还是沿第四方向P延伸，均与位线结构210和电容结构230之间具有间隔，彼此不会发生接触导致互相电连接。本领域技术人员可以根据位线结构210、晶体管结构220和电容结构230的具体结构设置决定栅电极227的延伸方向，此处不做特殊限定。
具体地，可以利用沉积工艺形成栅电极227，包括在栅介质层2241的表面形成栅电极227，且栅电极227自该栅介质层2241沿第三方向X或第四方向P向该第二外延部22的一侧延伸。S144’：在第 一方向Z上堆叠的多层栅电极227中，向相邻的栅电极227之间填充绝缘材料层2273。
在一些实施例中，如图17所示，第三方向X垂直于第二方向Y；利用沉积工艺在该栅电极227上形成一层绝缘材料层2273；在该绝缘材料层2273上再沉积形成栅电极227，再在该栅电极227上形成绝缘材料层2273，最终形成间隔堆叠的栅电极227与绝缘材料层2273。当然，也可以先形成块状的栅电极227，然后重新蚀刻出间隙G，再在相邻的栅电极227之间填充绝缘材料层2273，只要能够形成栅电极227与绝缘材料层2273间隔设置的结构即可，此处不做特殊限定。本公开上述实施例中形成的晶体管224为全环绕栅极(Gate All Around)晶体管。
如图17所示，本公开实施例的方法还包括：将堆叠的多层栅电极227形成阶梯结构，露出每层栅电极227的至少部分上表面；在呈阶梯结构的多个栅电极227上分别形成多个第二接线柱250。
本公开实施例中，关于将堆叠的多层栅电极227形成阶梯结构的工艺，与将位线结构210形成阶梯结构的工艺相同，此处不再赘述。每个阶梯的表面为该层的栅电极227的表面，如图17所示，在每层栅电极227露出的表面上形成第二接线柱250，以与导线连接，进而与外围电路连接。将堆叠的多层栅电极227形成阶梯结构，能够对第二接线柱250形成让位空间，在实现了每层栅电极227与外围电路连接的同时，还节省了半导体结构占用的空间，提升了半导体结构的性能。
如图17所示，在栅电极227形成为阶梯结构的实施例中，该方法还可以包括：在位线结构210上沿第一方向Z且远离晶体管结构220的一端形成导电连接件260，且导电连接件260分别与各位线211连接。
即将各层的位线211通过导电连接件260引出以与外围电路连接，此时，位线结构210在其延伸方向的尺寸可以减小，进一步缩小半导体结构整体的尺寸。导电连接件260可以是导线、导电片等，此处不做特殊限定。
如图7所示，本公开实施例的半导体结构的制备方法还可以包括：对第二外延部22的第一端221和第二端222进行离子掺杂，分别形成晶体管结构220的源极225和漏极226。如图9所示，对源极225的至少与位线结构210中的位线211连接的部分进行金属硅化处理，形成位线接触228；对漏极226的至少与电容结构230中的电容器231连接的部分进行金属硅化处理，形成电容接触229。
如图7所示，可以通过离子注入工艺对第二外延部22的第一端221和第二端222进行离子掺杂，以形成晶体管224的源极225和漏极226。如图9所示，对源极225的至少与位线结构210中的位线211连接的部分进行金属硅化处理，使该连接的部分形成金属硅化物，形成位线接触228，以降低位线211与源极225之间的电阻，同时，对漏极226的至少与电容结构230中的电容器231连接的部分进行金属硅化处理，形成电容接触229，以降低电容器231与漏极226之间的电阻。进行金属硅化处理的金属材料可以是Co、Ni、Pt、Ti、Ta、Mo和W中的至少一种，此处不做特殊限定。在源极225/漏极226形成位线接触228/电容接触229的部分至少能够与位线211/电容器231连接，以起到降低电阻的作用。当然，为了进一步降低电阻，可以在上述基础上，对整个源极225/漏极226的表面进行一定程度的金属硅化处理，以形成面积较大的接触。
综上所述，本公开实施例的半导体结构的制备方法，将位线结构210与电容结构230设于晶体管结构220的沿第三方向X相对的两侧，以形成半导体结构。在半导体器件的布局中，该半导体结构能够进一步节省空间，提高半导体结构的单位密度，提升存储性能，且结构更加简单。另外，通过去除 第二外延部22的第一端221和第二端222之间的牺牲层201，形成间隙G，以形成多层互相间隔的沟道223，使得制备工艺更加简单，能够有效提高半导体结构的制备良率。
本公开实施例还提供了一种半导体结构，如图16和图17所示，半导体结构包括：基底1、位线结构210、电容结构230和晶体管结构220。
其中，位线结构210位于基底1上，位线结构210中包括沿第一方向Z堆叠的多个位线211。电容结构230位于基底1上，电容结构230中包括沿第一方向Z堆叠的多个电容器231。晶体管结构220位于基底1上并沿第二方向Y延伸，晶体管结构220中包括沿第一方向Z堆叠的多个晶体管224，晶体管结构220在第二方向Y上具有第一端221和第二端222，第一端221连接位线结构210，第二端222连接电容结构230，且晶体管结构220与电容结构230位于晶体管结构220的沿第三方向X相对的两侧；其中，第一方向Z垂直于基底1，第二方向Y和第三方向X位于平行于基底的平面内。
如图16所示，本公开实施例中的位线结构210包括沿第一方向Z间隔堆叠的多个第一绝缘层(绝缘层203)和多个位线211。其中，位线结构210为阶梯结构，每个位线211至少部分上表面露出。半导体结构还包括多个第一接线柱240，分别位于呈阶梯结构的多个位线211的露出的上表面上，以与外围电路连接。
继续参考图16，在本公开实施例中，晶体管结构220中的晶体管224包括沟道223(参考图7)、栅介质层2241、扩散阻挡层2271和导电层2272。
其中，沟道223位于第一端221和第二端222之间，栅介质层2241位于沟道223的表面，扩散阻挡层2271位于栅介质层2241的表面，导电层2272位于相邻的晶体管224的扩散阻挡层2271之间。导电层2272和扩散阻挡层2271形成晶体管224的栅电极227。多层堆叠的栅电极227同时也可以是字线，与外围电路连接。本公开实施例中的半导体结构可以通过上述任一实施例中描述的制备方法制备，此处不再赘述。
在另一些实施例中，如图17所示，晶体管224包括沟道223(参考图7)、栅介质层2241(图中未示出)和栅电极227。其中，沟道223位于晶体管224的第一端221和第二端222之间。栅介质层2241位于沟道223的表面。栅电极227位于栅介质层2241的表面，并沿第三方向X或第四方向P在晶体管224的一侧延伸，且栅电极227位线结构210或电容结构230不接触，其中，第四方向P和第三方向X位于平行于基底1的平面内，多个沿第一方向Z堆叠的晶体管224的多层栅电极227为阶梯结构，每层栅电极227的至少部分上表面露出。
在本公开实施例中，半导体结构还包括多个第二接线柱250，分别位于呈阶梯结构的多个栅电极227上，以将栅电极227与外围电路连接；绝缘材料层2273，位于相邻的栅电极227之间，以使相邻的栅电极227相互绝缘。
在一些实施例中，第一方向Z、第二方向Y和第三方向X相互垂直，即栅电极227沿垂直于晶体管224的方向向晶体管224的一侧延伸，该多层栅电极227形成阶梯结构，能够对第二接线柱250形成让位空间，在实现了每层栅电极227与外围电路连接的同时，位线结构210在其延伸方向的尺寸可以减小，节省了半导体结构的占用空间，进一步缩小半导体结构整体的尺寸，提升了半导体结构的性能。
在本公开实施例中，晶体管224的第一端221可以为源极225，晶体管224的第二端222可以为漏 极226，晶体管224还包括：位线接触228和电容接触229。其中，位线接触228位于源极225和位线结构210的位线211之间，以减小位线211和源极225之间的电阻；电容接触229位于漏极226和电容结构230的电容器231之间，以减小电容器231和漏极226之间的电阻。
在本公开实施例中，位线结构210在第二方向Y上与栅电极227具有第一间隔d1，电容结构在所述第二方向Y上与栅电极227具有第二间隔d2，能够避免电容结构230、晶体管结构220、位线结构210之间发生接触导致互相电连接，确保半导体结构的电性能的稳定性。
在本公开实施例中，如图16和图17所示，电容结构230包括沿第一方向Z间隔堆叠的多个第二绝缘层(绝缘层203)和多个电容器231。本公开实施例中的电容器231可以是柱状电极、桶状电极，此处不做限定。
本公开实施例的半导体结构，位线结构210与电容结构230位于晶体管224结构220的沿第三方向X相对的两侧，在半导体器件的布局中，该半导体结构能够进一步节省空间，提高半导体结构的单位密度，提升存储性能，且结构更加简单。
本公开实施例还提供了一种半导体器件，如图20和图21所示，该半导体器件包括第一半导体单元1000。该第一半导体单元1000包括第一半导体结构1100和第二半导体结构1200。
其中，第一半导体结构1100具有第一位线结构1110、第一晶体管结构1120以及第一电容结构1130，第一晶体管结构1120第二方向Y延伸，第一位线结构1110和第一电容结构1130位于第一晶体管结构1120的在第三方向X上相对的两侧。第二半导体结构1200具有第二位线结构1210、第二晶体管结构1220以及第二电容结构1230，第二晶体管结构1220沿第二方向Y延伸，第二位线结构1210和第二电容结构1230位于第二晶体管结构1220的在第三方向X上相对的两侧。
如图20和18所示，第一电容结构1130沿第二方向Y的投影至少部分与第二电容结构1230重合。第一晶体管结构1120沿第三方向X的投影与第二晶体管结构1220重合。其中，第二方向Y和第三方向X相互垂直。第一半导体结构1100和第二半导体结构1200的这种布局，使得第一半导体单元1000在半导体器件中占据的空间尽量缩小。
如图20所示，在本公开实施例中，第一晶体管结构1120和第二晶体管结构1220分别在第三方向X上具有相对的第一侧和第二侧，其中，第一位线结构1110和第二电容结构1230位于第一侧，第一电容结构1130和第二位线结构1210位于第二侧。
也就是说，第一位线结构1110位于第一晶体管结构1120的第一侧，第二电容结构1230位于第二晶体管结构1220的第一侧，而第一电容结构1130位于第一晶体管结构1120的第二侧，第二位线结构1210位于第二晶体管结构1220的第二侧。
继续参考图20，本公开实施例中的半导体器件还包括第二半导体单元2000，第二半导体单元2000具有与第一半导体单元1000相同的结构；第二半导体单元2000和第一半导体单元1000在第二方向Y和第三方向X上间隔设置。
也就是说，半导体器件中的每个半导体单元具有相同的结构，如图22所示，这些半导体单元间隔设置，例如多个半导体单元可以呈矩阵排列，相邻的半导体单元之间的间距可以相同也可以不同，只要在不影响半导体器件的性能的情况下能够尽量缩小占用空间即可，此处不做特殊限定。
如图21所示，在本公开的另外一些实施例中，半导体器件还包括第三半导体单元3000，第三半导 体单元3000具有与第一半导体单元1000关于对称轴F对称的结构；该对称轴F沿第三方向X延伸；第三半导体单元3000和第一半导体单元1000在第二方向Y和第三方向X上间隔设置。
具体地，如图21所示，定义一对称轴F，该对称轴F沿第三方向X延伸。第三半导体单元3000包括与第一半导体单元1000相同的第一半导体结构1100和第二半导体结构1200，但第三半导体单元3000与第一半导体单元1000关于该对称轴F对称。
可以将如图21所示的第一半导体单元1000和第三半导体单元3000看作一个整体，在半导体器件中，可以在第二方向Y和第三方向X上间隔设置多个该整体，如图23所示，该整体可以呈矩阵排布，也可以是非等间距的排布，只要在不影响半导体器件的性能的情况下能够尽量缩小占用空间即可。
当然，半导体器件中也可以同时设置第一半导体单元1000、第二半导体单元2000和第三半导体单元3000，三者可以在第二方向Y和第三方向X上间隔设置，如在第二方向Y上，三者可以按照如下方式排布：第一半导体单元1000、第二半导体单元2000、第三半导体单元3000依序间隔排布，或者第一半导体单元1000、第三半导体单元3000、第二半导体单元2000依序间隔排布，当然也可以不按照特定顺序排布；在第三方向X上，三者可以按照如下方式排布：第一半导体单元1000、第二半导体单元2000、第三半导体单元3000依序间隔排布，或者第一半导体单元1000、第三半导体单元3000、第二半导体单元2000依序间隔排布，当然也可以不按照特定顺序排布。但需注意的是，应该使得半导体器件在有限的空间中尽量排布更多的半导体结构，同时不影响半导体器件的性能，提升存储性能，避免空间浪费。
综上所述，本公开实施例的半导体结构的制备方法、半导体结构以及半导体器件中，将位线结构210与电容结构设于晶体管结构220的沿第三方向X相对的两侧，以形成半导体结构。在半导体器件的布局中，该半导体结构能够进一步节省空间，提高半导体结构的单位密度，提升存储性能，且结构更加简单。另外，在制备方法中，通过去除第二外延部22的第一端221和第二端222之间的牺牲层201，形成间隙G，以形成多层互相间隔的沟道223，使得制备工艺更加简单，能够有效提高半导体结构的制备良率。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施例，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施例说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (17)

  1. 一种半导体结构的制备方法，其特征在于，包括：
    提供基底(1)；
    在所述基底(1)上形成位线结构(210)，所述位线结构(210)中包括沿第一方向(Z)堆叠的多个位线(211)；
    在所述基底(1)上形成电容结构(230)，所述电容结构(230)中包括沿所述第一方向(Z)堆叠的多个电容器(231)；
    在所述基底(1)上形成沿第二方向(Y)延伸的晶体管结构(220)，所述晶体管结构(220)中包括沿所述第一方向(Z)堆叠的多个晶体管(224)；所述晶体管结构(220)在所述第二方向(Y)上具有第一端(221)和第二端(222)；所述第一端(221)连接所述位线结构(210)，所述第二端(222)连接所述电容结构(230)，所述位线结构(210)与所述电容结构(230)位于所述晶体管结构(220)的沿第三方向(X)相对的两侧；所述第一方向(Z)垂直于所述基底(1)，所述第二方向(Y)和所述第三方向(X)位于平行于所述基底(1)的平面内。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    在所述基底(1)上形成多个沿所述第一方向(Z)堆叠的外延结构(2)，所述外延结构(2)包括沿所述第一方向(Z)依序堆叠的牺牲层(201)和半导体层(202)；
    蚀刻所述外延结构(2)，使所述外延结构(2)具有第一外延部(21)、第二外延部(22)和第三外延部(23)，所述第二外延部(22)沿所述第二方向(Y)延伸，所述第一外延部(21)和所述第三外延部(23)分别连接于所述第二外延部(22)的沿所述第二方向(Y)的第一端(221)和第二端(222)；且所述第一外延部(21)和所述第三外延部(23)位于所述第二外延部(22)的沿所述第三方向(X)的相对的两侧；
    去除所述第二外延部(22)的所述第一端(221)和所述第二端(222)、以及所述第一外延部(21)和所述第三外延部(23)的各个牺牲层(201)，形成多个第一待填充空间(C1)；
    向所述第一待填充空间(C1)中填充绝缘层(203)。
  3. 根据权利要求2所述的方法，其特征在于，在所述基底(1)上形成位线结构(210)，包括：
    去除所述第一外延部(21)中的所述半导体层(202)，形成多个第二待填充空间(C2)；
    向所述第二待填充空间(C2)中填充第一导电材料，形成所述位线结构(210)。
  4. 根据权利要求3所述的方法，其特征在于，还包括：
    沿所述第一方向(Z)将所述位线结构(210)形成阶梯结构，露出每层所述位线(211)的至少部分上表面；
    在呈阶梯结构的多层所述位线(211)上分别形成多个第一接线柱(240)。
  5. 根据权利要求3或4所述的方法，其特征在于，所述第二外延部(22)还包括位于所述第一端(221)和所述第二端(222)之间的中部，所述位线结构(210)在所述第二方向(Y)上与所述中部具有第一间隔(d1)，所述电容结构(230)在所述第二方向(Y)上与所述中部具有第二间隔(d2)；
    在所述基底(1)上形成沿第二方向(Y)延伸的晶体管结构(220)，包括：
    去除所述第二外延部(22)的所述中部的所述牺牲层(201)，形成间隙(G)；
    在所述第二外延部(22)的所述中部的所述半导体层(202)的表面形成栅介质层(2241)；
    在所述栅介质层(2241)的表面形成栅电极(227)，且所述栅电极(227)填充所述间隙(G)。
  6. 根据权利要求3所述的方法，其特征在于，所述第二外延部(22)还包括位于所述第一端(221)和所述第二端(222)之间的中部，所述位线结构(210)在所述第二方向(Y)上与所述中部具有第一间隔(d1)，所述电容结构(230)在所述第二方向(Y)上与所述中部具有第二间隔(d2)；
    在所述基底(1)上形成沿第二方向(Y)延伸的晶体管结构(220)，包括：
    去除所述第二外延部(22)的所述中部的所述牺牲层(201)；
    在所述第二外延部(22)的所述中部的所述半导体层(202)的表面形成栅介质层(2241)；
    在所述栅介质层(2241)的表面形成栅电极(227)，且所述栅电极(227)沿所述第三方向(X)或第四方向(P)在所述第二外延部(22)的一侧延伸，且与所述位线结构(210)或所述电容结构(230)不接触；所述第四方向(P)和所述第三方向(X)位于平行于所述基底(1)的平面内；
    在所述第一方向(Z)上堆叠的多层所述栅电极(227)中，向相邻的所述栅电极(227)之间填充绝缘材料层(2273)。
  7. 根据权利要求6所述的方法，其特征在于，还包括：
    将堆叠的多层所述栅电极(227)形成阶梯结构，露出每层所述栅电极(227)的至少部分上表面；
    在呈阶梯结构的多层所述栅电极(227)上分别形成多个第二接线柱(250)。
  8. 根据权利要求7所述的方法，其特征在于，还包括：
    在所述位线结构(210)上沿所述第一方向(Z)且远离所述晶体管结构(220)的一端形成导电连接件(260)，且所述导电连接件(260)分别与各所述位线(211)连接。
  9. 根据权利要求2至8中任一项所述的方法，其特征在于，在所述基底(1)上形成沿第二方向(Y)延伸的晶体管结构(220)，包括：
    对所述第二外延部(22)的所述第一端(221)和所述第二端(222)进行离子掺杂，分别形成所述晶体管结构(220)的源极(225)和漏极(226)；
    对所述源极(225)的至少与所述位线结构(210)中的位线(211)连接的部分进行金属硅化处理，形成位线接触(228)；
    对所述漏极(226)的至少与所述电容结构(230)中的电容器(231)连接的部分进行金属硅化处理，形成电容接触(229)。
  10. 一种半导体结构，其特征在于，包括：
    基底(1)；
    位线结构(210)，位于所述基底(1)上，所述位线结构(210)中包括沿第一方向(Z)堆叠的多个位线(211)；
    电容结构(230)，位于所述基底(1)上，所述电容结构(230)中包括沿所述第一方向(Z)堆叠的多个电容器(231)；
    晶体管结构(220)，位于所述基底(1)上并沿第二方向(Y)延伸，所述晶体管结构(220)中包括沿所述第一方向(Z)堆叠的多个晶体管(224)，所述晶体管结构(220)在所述第二方向(Y)上具有第一端(221)和第二端(222)，所述第一端(221)连接所述位线结构(210)，所述第二端(222)连接所述电容结构(230)，且所述晶体管结构(220)与所述电容结构(230)位于所述晶体管结构(220)的沿第三方向(X)相对的两侧；其中，所述第一方向(Z)垂直于所述基底(1)，所述第二方向(Y)和所述第三方向(X)位于平行于所述基底(1)的平面内。
  11. 根据权利要求10所述的半导体结构，其特征在于，所述晶体管(224)包括：
    沟道(223)，位于所述晶体管(224)的所述第一端(221)和所述第二端(222)之间；
    栅介质层(2241)，位于所述沟道(223)的表面；
    栅电极(227)，位于所述栅介质层(2241)的表面，并沿所述第三方向(X)或第四方向(P)在所述晶体管(224)的一侧延伸，且与所述位线结构(210)或所述电容结构(230)不接触，所述第四方向(P)和所述第三方向(X)位于平行于所述基底(1)的平面内，多个沿所述第一方向(Z)堆叠的所述晶体管(224)的多层栅电极(227)为阶梯结构，每层所述栅电极(227)的至少部分上表面露出；
    所述半导体结构还包括：
    多个第二接线柱(250)，分别位于呈阶梯结构的多层所述栅电极(227)上；
    绝缘材料层(2273)，位于相邻的所述栅电极(227)之间。
  12. 根据权利要求11所述的半导体结构，其特征在于，所述位线结构(210)在所述第二方向(Y)上与所述栅电极(227)具有第一间隔(d1)，所述电容结构(230)在所述第二方向(Y)上与所述栅电极(227)具有第二间隔(d2)。
  13. 根据权利要求10至12中任一项所述的半导体结构，其特征在于，所述晶体管(224)的第一端(221)为源极(225)，所述晶体管(224)的第二端(222)为漏极(226)，所述晶体管(224)包括：
    位线接触(228)，位于所述源极(225)和所述位线结构(210)的位线(211)之间；
    电容接触(229)，位于所述漏极(226)和所述电容结构(230)的电容器(231)之间。
  14. 一种半导体器件，其特征在于，包括：
    第一半导体单元(1000)，所述第一半导体单元(1000)包括：
    第一半导体结构(1100)，所述第一半导体结构(1100)具有第一位线结构(1110)、第一晶体管结构(1120)以及第一电容结构(1130)，所述第一晶体管结构(1120)沿第二方向(Y)延伸，所述第一位线结构(1110)和所述第一电容结构(1130)位于所述第一晶体管结构(1120)的在第三方向(X)上相对的两侧；
    第二半导体结构(1200)，所述第二半导体结构(1200)具有第二位线结构(1210)、第二晶体管结构(1220)以及第二电容结构(1230)，所述第二晶体管结构(1220)沿第二方向(Y)延伸，所述第二位线结构(1210)和所述第二电容结构(1230)位于所述第二晶体管结构(1220)的在第三方向(X)上相对的两侧；
    其中，所述第一电容结构(1130)沿第二方向(Y)的投影至少部分与所述第二电容结构(1230) 重合；
    所述第一晶体管结构(1120)沿第三方向(X)的投影与所述第二晶体管结构(1220)重合；其中，所述第二方向(Y)和所述第三方向(X)相互垂直。
  15. 根据权利要求14所述半导体器件，其特征在于，所述第一晶体管结构(1120)和所述第二晶体管结构(1220)分别在所述第三方向(X)上具有相对的第一侧和第二侧，其中，所述第一位线结构(1110)和所述第二电容结构(1230)位于所述第一侧，所述第一电容结构(1130)和所述第二位线结构(1210)位于所述第二侧。
  16. 根据权利要求14或15所述半导体器件，其特征在于，还包括：
    第二半导体单元(2000)，所述第二半导体单元(2000)具有与所述第一半导体单元(1000)相同的结构；
    所述第二半导体单元(2000)和所述第一半导体单元(1000)在所述第二方向(Y)和所述第三方向(X)上间隔设置。
  17. 根据权利要求15或16所述半导体器件，其特征在于，还包括：
    第三半导体单元(3000)，所述第三半导体单元(3000)具有与所述第一半导体单元(1000)关于对称轴(F)对称的结构；
    所述对称轴(F)沿所述第三方向(X)延伸；
    所述第三半导体单元(3000)和所述第一半导体单元(1000)在所述第二方向(Y)和所述第三方向(X)上间隔设置。
PCT/CN2023/097869 2022-08-30 2023-06-01 半导体结构的制备方法、半导体结构及半导体器件 Ceased WO2024045733A1 (zh)

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