WO2024045290A1 - 版图结构、半导体结构以及存储器 - Google Patents

版图结构、半导体结构以及存储器 Download PDF

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Publication number
WO2024045290A1
WO2024045290A1 PCT/CN2022/126213 CN2022126213W WO2024045290A1 WO 2024045290 A1 WO2024045290 A1 WO 2024045290A1 CN 2022126213 W CN2022126213 W CN 2022126213W WO 2024045290 A1 WO2024045290 A1 WO 2024045290A1
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WIPO (PCT)
Prior art keywords
line
along
wiring layer
power
local
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PCT/CN2022/126213
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English (en)
French (fr)
Inventor
吕庆
姜伟
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长鑫存储技术有限公司
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Priority to US18/449,594 priority Critical patent/US20240079411A1/en
Publication of WO2024045290A1 publication Critical patent/WO2024045290A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a layout structure, a semiconductor structure and a memory.
  • Standard cells are the basis of integrated circuit design.
  • Standard cells can include inverters, logic gates, registers, buffers and other logic devices commonly used in integrated circuits.
  • the standard cell layout in the standard cell library can be called according to design needs to complete the layout design of the integrated circuit, which can improve the design efficiency of the circuit.
  • optimizing standard cells is a feasible means that can not only improve design efficiency, but also improve the integration and performance of semiconductor devices.
  • a semiconductor structure including:
  • the logic device includes a first power line and a second power line located on the same wiring layer.
  • the first power line and the second power line both extend along the first direction and are arranged side by side along the second direction.
  • the first direction and the second direction intersect and are both parallel to the plane where the wiring layer is located;
  • a switch driving device is arranged in parallel with the logic device along the first direction.
  • the switch driving device includes a first input line and a first output line.
  • the first input line and the first output line are connected to the first input line and the first output line.
  • the first power line is located on the same wiring layer, the first input line and the first output line both extend along the first direction and are arranged side by side along the second direction, wherein the first output line
  • the power line is connected to the first power line or the second power line.
  • the first power line includes a first main body line and a first local line, and the first main body line and the first local line are arranged side by side along the second direction;
  • the first output line is connected to the first local line, and the first input line is connected to the first body line.
  • the second power line includes a second body line and a second local line, and the second body line and the second local line are arranged side by side along the second direction;
  • the switch driving device also includes: a second input line and a second output line, which are located on the same wiring layer as the second power line, and both the second input line and the second output line are along the first direction. extending and arranged side by side along the second direction, wherein the second input line is connected to the second body line, and the second output line is connected to the second local line.
  • the line width of the first output line along the second direction is equal to the line width of the first local line along the second direction
  • the line width of the first input line along the second direction is equal to the line width of the first body line along the second direction
  • the line width of the second output line along the second direction is equal to the line width of the second local line along the second direction
  • the line width of the second input line along the second direction is equal to the line width of the second body line along the second direction.
  • the logic device further includes: a first component and a second component arranged side by side in the second direction, the first component has a first power lead-out line located on the first wiring layer, and the second component The component has a second power supply lead-out line located on the first wiring layer, and both the first power supply lead-out line and the second power supply lead-out line extend along the second direction;
  • the first body line, the first local line, the second body line and the second local line are located on a second wiring layer, and the second wiring layer is located on the first wiring layer;
  • the first local wire is electrically connected to the first power lead-out wire through a first interconnection hole
  • the second body wire is electrically connected to the second power supply lead-out wire through a second interconnection hole
  • the first body line is electrically connected to the first power lead-out line through a third interconnection hole
  • the second local line is electrically connected to the second power lead-out line through a fourth interconnection hole.
  • the switch driving device also includes:
  • a first well region includes a first source region, a first channel and a first drain region arranged side by side along the first direction;
  • a first gate located on the first channel and extending along the second direction;
  • a first source line is located on the first wiring layer.
  • the first source line, the first source region and the first input line are electrically connected.
  • the first source line is along the first wiring layer. Extend in two directions;
  • a first drain line is located on the first wiring layer.
  • the first drain line, the first drain region and the first output line are electrically connected.
  • the first drain line is along the first wiring layer. Extends in two directions.
  • the first well region includes a plurality of the first source regions and a plurality of the first drain regions, and the first source regions and the first drain regions are along the first Alternately arranged in one direction, the first channels are provided between the adjacent first source regions and the first drain regions, and the first gate is provided on each of the first channels. ;
  • first gate electrodes There are multiple first gate electrodes, and the plurality of first gate electrodes are arranged side by side and connected along the first direction.
  • the switch driving device also includes:
  • a second well region is arranged parallel to the first well region along the second direction.
  • the second well region includes a second source region, a second channel and a second well region arranged parallel to the first direction.
  • a second gate located on the second channel and extending along the second direction;
  • a second source line is located on the first wiring layer.
  • the second source line, the second source region and the second input line are electrically connected.
  • the second source line is along the first wiring layer. Extend in two directions;
  • a second drain line is located on the first wiring layer.
  • the second drain line, the second drain region and the second output line are electrically connected.
  • the second drain line is along the first wiring layer. Extends in two directions.
  • the second well region includes a plurality of the second source regions and a plurality of the second drain regions, and the second source regions and the second drain regions are along the first Alternately arranged in one direction, the second channels are disposed between the adjacent second source regions and the second drain regions, and the second gates are disposed on each of the second channels. ;
  • the plurality of second gates are arranged side by side and connected along the first direction.
  • the switch driving device also includes:
  • a first gate connection line is located on the same wiring layer as the first gate.
  • the first gate connection line extends along the first direction and connects multiple first gates relatively close to the first gate. The end of the second gate;
  • a second gate connection line is located on the same wiring layer as the second gate.
  • the second gate connection line extends along the first direction and connects a plurality of second gates relatively close to the first gate. The end of a gate;
  • a first auxiliary connection line is located on the first wiring layer.
  • the first auxiliary connection line includes a first part extending along the first direction and a second part extending along the second direction. The first part is connected to The first gate connection line is electrically connected;
  • a second auxiliary connection line is located on the first wiring layer.
  • the second auxiliary connection line includes a third part extending along the first direction and a fourth part extending along the second direction.
  • the third part extends along the second direction. part is electrically connected to the second gate connection line; in a plane perpendicular to the first direction, the orthographic projection of the second part and the orthographic projection of the fourth part at least partially overlap;
  • a gate control line extends along the first direction and is electrically connected to the second part and the fourth part.
  • the semiconductor structure includes a plurality of standard units, the standard units include the logic device and the switch driving device, and a plurality of the standard units are arranged in an array;
  • first input line, first output line, second input line and second output line of the standard unit are respectively connected with the first main body line, The first local line, the second main line and the second local line are connected;
  • the semiconductor structure further includes: a power connection line located on a third wiring layer, the third wiring layer is located on the second wiring layer, the power connection line extends along the second direction, and is connected along the second wiring layer.
  • the first local lines or the first output lines of a plurality of standard units arranged in parallel in the second direction are connected.
  • the logic device includes at least one of an inverter, a logic gate circuit, a buffer or a latch.
  • a memory including the semiconductor structure as described in the first aspect of the present disclosure.
  • a layout structure including:
  • the logic device layout includes a first power line pattern and a second power line pattern located on the same layout wiring layer.
  • the first power line pattern and the second power line pattern both extend along the first direction and extend along the second direction.
  • the logic device layout is used to define the logic device, the first power line pattern is used to define the first power line, and the second power line pattern Used to define the second power line;
  • a switch driving device layout is arranged side by side with the logic device layout along the first direction.
  • the switch driving device layout includes a first input line pattern and a first output line pattern.
  • the first input line pattern and the The first output line pattern and the first power line pattern are located on the same layout wiring layer.
  • the first input line pattern and the first output line pattern both extend along the first direction and extend along the second direction. arranged in parallel, wherein the first output line pattern extends along the first direction and is connected to the first power line pattern or the second power line pattern; the switch driving device layout is used to define switches
  • a driving device the first input line pattern is used to define a first input line, and the first output line pattern is used to define a first output line.
  • the layout structure includes a standard unit layout
  • the standard unit layout includes the logic device layout and the switch driving device layout
  • the standard unit layout is used to define the standard unit.
  • the logic device and the switch driving device are arranged side by side along the first direction, the first power line and the second power line of the logic device extend along the first direction, and the first output line of the switch driving device , the first power line and the second power line are located on the same wiring layer, wherein the first output line is connected to the first power line, or the first output line or the second power line is connected.
  • the switch driving device provides local power to the logic device, the current flows directly from the first output line of the switch driving device into the first power line or the second power line of the logic device without passing through the interconnection hole, so local power can be greatly reduced.
  • the resistance value of the power network reduces the loss during current transfer, thereby improving the stability of the local power supply of the logic device, thereby improving the stability of the delay time of the logic device.
  • first power line (or the second power line) and the first output line both extend along the first direction until they are connected to each other. Therefore, the first power line (or the second power line) and the first output line
  • the shorter lines can further reduce the resistance value of the local network, reduce the loss during current transmission, and improve the stability of the delay time of the logic device.
  • Figure 1 is a schematic layout diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2a is a schematic circuit connection diagram of a logic device and a switch driving device provided by an embodiment of the present disclosure
  • Figure 2b is another circuit connection schematic diagram of a logic device and a switch driving device provided by an embodiment of the present disclosure
  • FIG 3 is an enlarged schematic diagram of the logic device and switch driving device in the semiconductor structure shown in Figure 1;
  • Figure 4 is a circuit diagram of the logic device and switch driving device shown in Figure 3;
  • Figure 5 is an enlarged schematic diagram of the logic device in Figure 3;
  • Figure 6 is a cross-sectional view of the logic device shown in Figure 5 along line A-A;
  • Figure 7 is a schematic layout diagram of yet another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 8 is an enlarged schematic diagram of a standard unit in the semiconductor structure shown in Figure 7;
  • FIG. 9 is a circuit diagram of the switch driving device in the standard unit shown in Figure 8.
  • Figure 10 is a schematic diagram of the current path of the semiconductor structure shown in Figure 1 in the working state
  • FIG. 11 is a schematic diagram of the current path of the semiconductor structure shown in FIG. 7 in a working state.
  • orientation or positional relationship indicated by the terms “length”, “width”, “depth”, “upper”, “lower”, “outer”, etc. are based on those shown in the accompanying drawings.
  • the orientation or positional relationship is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the disclosure.
  • FIG. 1 is a schematic layout diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes a standard cell array 10, and the standard cell array 10 includes a plurality of standard cells.
  • the standard cell array includes 4 ⁇ 12 standard cells.
  • Standard cells can include different types of logic devices.
  • the logic device can be a buffer (buffer, abbreviated as buf), a register (Register), an inverter (abbreviated as inv), a logic gate circuit, etc.
  • Logic gate circuits include, but are not limited to, NOR gate circuits (nor), NAND gate circuits (nand), etc. It should be noted that there is a similar expression to nand3PF ⁇ 2 in the figure. Here is a unified definition and explanation, where nand represents any logic gate circuit, "3" represents the number of input terminals of the logic gate circuit, and PF represents no limit to the power supply terminal.
  • the ground terminal is limited to the main ground terminal Vss, and the parallel one also includes GF, which means that the ground terminal is not limited.
  • the power terminal is limited to the main power terminal Vcc. " ⁇ 2" represents the width-to-length ratio of the MOS tube in the logic gate circuit.
  • the semiconductor structure also includes two switch driving device arrays 20, which are arranged on both sides of the standard cell array 10 along the Y direction.
  • the switch driver device array 20 includes a plurality of switch driver devices (Switch CMOS Driver Cell, abbreviated as Scmos Drv cell).
  • the switch drive device array may include 10 ⁇ 1 switch drive devices, where “10” represents the number of switch drive devices, and “ ⁇ 1” represents the width-to-length ratio of the MOS transistor in the switch drive device. .
  • the semiconductor structure also includes a plurality of local power buses 30 extending along the Y direction.
  • the local power buses 30 electrically connect the switch driving device and the logic device.
  • the switch driver device is used to control the switching of the power supply of the logic device (that is, the standard cell array).
  • the switch driving device includes a PMOS transistor (P-channel enhancement type field effect transistor), an NMOS transistor (N-channel enhancement type field effect transistor), or a CMOS circuit composed of a PMOS transistor and an NMOS transistor.
  • Figure 2a and Figure 2b show two connection methods of the switch driving device and the logic device.
  • the switch driving device is a PMOS transistor MPa.
  • the drain of the PMOS transistor MPa is connected to the power supply Vcc, the source is connected to the power supply terminal of the logic device, and the ground terminal of the logic device is connected to the common ground Vss.
  • the switch driving device provides power to the logic device.
  • the power supply provided by the switch driver device is called the local power supply local Vcc.
  • the PMOS transistor MPa is turned off, the power supply to the logic device can be turned off.
  • the switch driving device is an NMOS transistor MNa.
  • the drain of the NMOS transistor MNa is connected to the common ground Vss, the source is connected to the ground terminal of the logic device, and the power terminal of the logic device is connected to the power supply Vcc.
  • the switch driver device is used to provide a ground signal to the logic device.
  • the ground signal provided by the switch driver device is called the local ground signal local Vss.
  • the NMOS transistor MNa is turned off, the power supply to the logic device can be turned off.
  • the power terminal is connected to the power supply Vcc, and the ground terminal is connected to the public ground Vss; the second is that the power terminal is connected to the switch driving device and receives the local power supply local Vcc. , the ground terminal is connected to the public ground Vss; the third is that the power terminal is connected to the power supply Vcc, and the ground terminal is connected to the switch driving device to receive the local ground signal local Vss.
  • FIG. 3 is an enlarged schematic diagram of the logic device and the switch driving device in the semiconductor structure shown in FIG. 1 , that is, an enlarged schematic diagram of the area indicated by the dotted box in FIG. 1 .
  • the logic device 100 is invPF ⁇ 4.
  • the logic device 100 is invPF ⁇ 4 as an example to illustrate the layout and connection method of the logic device 100 and the switch driving device 200 .
  • FIG. 4 is a circuit diagram of the logic device and switch driving device shown in FIG. 3 .
  • the switch driving device 200 includes a plurality of parallel-connected PMOS transistors MPa.
  • the switch driving device 200 includes five parallel PMOS transistors Mpa. Therefore, the switch driving device array 20 in FIG. 1 provides local power supply local Vcc to the standard cell array 10 through multiple local power buses 30. It should be understood that in other embodiments, the switch driving device array may also provide the local ground signal local Vss to the standard cell array through multiple local power buses.
  • the logic device 100 includes a first load tube MP1, a first drive tube MN1, a second load tube MP2 and a second drive tube MN2, wherein the first load tube MP1 and the second load tube MP2 are PMOS transistors, The first driving transistor MN1 and the second driving transistor MN2 are NMOS transistors.
  • the source of the first load tube MP1 is connected to the output end of the switch driving device for receiving the local power supply local Vcc.
  • the drain of the first load tube MP1 and the drain of the first driver tube MN1 are both connected to node b1.
  • the first driver The source of the tube MN1 is connected to the common ground Vss, and the gate of the first load tube MP1 and the first driving tube MN1 are both connected to the node a1.
  • the source of the second load tube MP2 is also connected to the output end of the switch driving device for receiving the local power supply local Vcc.
  • the drain of the second load tube MP2 and the drain of the second driving tube MN2 are both connected to node b2.
  • the second The source of the driving tube MN2 is connected to the common ground Vss, and the gate of the second load tube MP2 and the gate of the second driving tube MN2 are both connected to the node a2.
  • node a1 is connected to node a2
  • node b1 is connected to node b2.
  • the logic device 100 includes two parallel inverters, in which the first load tube MP1 and the first drive tube MN1 constitute the first inverter, the node a1 is the input end of the first inverter, and the node b1 is the first inverter.
  • Node a1 is connected to node a2
  • node b1 is connected to node b2, that is, the input terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter.
  • the output terminals are connected, and the first inverter and the second inverter are connected in parallel.
  • FIG. 5 is an enlarged schematic diagram of the logic device in FIG. 3
  • FIG. 6 is a cross-sectional view of the logic device shown in FIG. 5 along line A-A.
  • an n-type well region and a p-type well region are formed in the substrate, and a first load tube MP1 and a second load tube MP2 are formed in the n-type well region.
  • the first load tube MP1 and the second load tube are formed in the substrate.
  • MP2 is arranged side by side along the X direction, and a first driving tube MN1 and a second driving tube MN2 are formed in the p-type well region.
  • the first driving tube MN1 and the second driving tube MN2 are arranged side by side along the X direction.
  • the first load tube MP1 and the first drive tube MN1 are arranged in parallel along the Y direction
  • the second load tube MP2 and the second drive tube MN2 are arranged in parallel along the Y direction.
  • the first load tube MP1 and the second load tube MP2 both include a source region 111 and a drain region 112 located in the n-type well region.
  • the source region 111 and the drain region 112 are both p-type doped. complex area.
  • the source region 111 and the drain region 112 are arranged along the X direction and isolated from each other, and a channel is formed between the source region 111 and the drain region 112 .
  • the first load tube and the second load tube share the drain region 112 .
  • the two load tubes (referring to the first load tube MP1 and the second load tube MP2) also include a gate structure covering the channel.
  • the gate structure includes a gate electrode 113 extending along the Y direction, and a gate electrode 113 located between the gate electrode 113 and the channel. gate dielectric layer between them.
  • the gates 113 of the two load tubes are arranged side by side along the X direction and are electrically connected through sub-connection lines 114 extending along the X direction.
  • the sub-connection line 114 and the gate electrode 113 are located on the same wiring layer.
  • the first driver tube MN1 and the second driver tube MN2 both include a source region (not shown in the figure), a channel and a drain region (not shown in the figure) located in the p-type well region, and a covering
  • the gate structure of the channel in which the source region, channel and drain regions are arranged side by side along the X direction, the source region and the drain region are both n-type doped regions, the first driver tube MN1 and the second driver Tube MN2 shares the drain region.
  • the gate structure includes a gate electrode 123 extending along the Y direction, and a gate dielectric layer located between the gate electrode 123 and the channel.
  • the gates 123 of the two drive tubes are arranged side by side along the X direction and are electrically connected through the sub-connection lines 124 extending along the X direction.
  • the sub-connection line 124 and the gate electrode 123 are located on the same wiring layer.
  • the gate electrodes 113 of the two load tubes and the gate electrodes 123 of the two drive tubes are located on the same wiring layer, but are isolated from each other, that is, they are not electrically connected at the wiring layer.
  • the logic device 100 also includes source lines 115 and drain lines 116 of two load tubes.
  • the source lines 115 and drain lines 116 of the two load tubes both extend along the Y direction, and
  • the contact plug CT is electrically connected to its source and drain regions.
  • the source line 115 and the drain line 116 that define the two load tubes are located on the first wiring layer M0, and the first wiring layer M0 is located on the wiring layer where the gate is located.
  • the contact plug CT is located between the first wiring layer M0 and the substrate, or the contact plug CT is located between the first wiring layer M0 and the active area.
  • each load tube can be electrically connected to its source region 111 through the corresponding contact plug CT
  • the drain line 116 of each load tube can be electrically connected to its drain region 112 through the corresponding contact plug CT. Electrical connection.
  • the logic device also includes source lines 125 and drain lines 126 of two driving tubes.
  • the source lines 125 and drain lines 126 of the two driving tubes both extend along the Y direction and are connected through contact plugs CT respectively. electrically connected to its source and drain regions.
  • the source lines 125 and the drain lines 126 of the two driving tubes are both located on the first wiring layer M0.
  • the drain line 116 shared by the two load tubes and the drain line 126 shared by the two drive tubes are connected to each other.
  • the drain line 116 and the drain line 126 are one conductive line. Drain line 116 and drain line 126 are connected to each other, corresponding to nodes b1 and b2 in the circuit.
  • the first wiring layer M0 also includes a main connection line 118 extending along the Y direction.
  • the main connection line 118 is electrically connected to the sub-connection lines 114 and 124 through the contact plug CT, corresponding to the node a1 and the node a2 in the circuit.
  • the logic device also includes a first local line 420 and a second body line 510.
  • the first local line 420 is used to provide local power supply local Vcc to the logic device
  • the second body line 510 is used to Provides common ground signal Vss to logic devices.
  • the first local line 420 and the second body line 510 both extend along the X direction, and are arranged side by side along the Y direction.
  • the first local line 420 is electrically connected to the source lines 115 of the two load tubes through the interconnection hole V1
  • the second body line 510 is electrically connected to the source lines 125 of the two drive tubes through the contact hole V1.
  • first local line 420 and the second body line 510 are located on the second wiring layer M1
  • the second wiring layer M1 is located on the first wiring layer M0.
  • the interconnection hole V1 is located between the second wiring layer M1 and the first wiring layer M0.
  • the first local line 420 is electrically connected to the source lines 115 of the two load tubes through a plurality of interconnection holes V1
  • the second body line 510 is electrically connected to the source lines 125 of the two drive tubes through a plurality of interconnection holes V1. Electrical connection.
  • the local power bus 30 is located on the third wiring layer M2, and the third wiring layer M2 is located on the second wiring layer M1.
  • the local power bus 30 is electrically connected to the first local line 420 of the logic device through the interconnection hole V2.
  • the interconnection hole V2 is located between the third wiring layer M2 and the second wiring layer M1.
  • the logic device also includes an interconnection hole V3 and an interconnection hole V4, wherein the interconnection hole V3 is located on the drain line 116 and/or the drain line 126 and is used as an output terminal of the logic device, and the interconnection hole V4 is located on the overall drain line 116 and/or the drain line 126 .
  • the connection line 118 is used as the input terminal of the logic device.
  • the switch driving device 200 includes a plurality of parallel PMOS transistors MPa, whose structure and layout are basically the same as those of the first load transistor MP1 and the second load transistor MP2 in the logic device.
  • the PMOS transistor Mpa includes: a first source region, a first channel and a first drain region (not shown in the figure) located in the first well region of the substrate, as well as a first gate electrode 213, a first source electrode Line 215, first drain line 216, first input line 610 and first output line 620.
  • the first well region is an n-type well region
  • the first source region, the first channel and the first drain region are arranged side by side along the X direction
  • the first source region and the first drain region are p-type doped. complex area.
  • the first gate 213 covers the first channel and extends along the Y direction.
  • the first source line 215 and the first drain line 216 are located on the first wiring layer M0.
  • the first source line 215 and the first drain line 216 both extend along the Y direction, and are arranged side by side along the X direction.
  • the first source line 215 is electrically connected to the first source region through the contact plug CT, and the first drain line 216 is electrically connected to the first drain region through the contact plug CT.
  • the first input line 610 and the first output line 620 are located on the second wiring layer M1.
  • the first input line 610 and the first output line 620 both extend along the X direction and are arranged side by side along the Y direction.
  • the first input line 610 is electrically connected to the first source line 215 through the interconnection hole V1
  • the first output line 620 is electrically connected to the first drain line 216 through the interconnection hole V1.
  • the local power bus 30 is electrically connected to the first output line 620 through the interconnection hole V2, so that the switch driving device provides the local power local VCC to the first local line 420 of the logic device.
  • LPDDR Low Power Double Data Rate SDRAM
  • some logic devices such as invPF ⁇ 4, nor3PF ⁇ 2, nand3PF ⁇ 2, included in the solid line box in Figure 1 nor2PF ⁇ 2, nand2PF ⁇ 2
  • Lvt transistors Low V th
  • High-speed transistors have low threshold voltage (V th ), short delay time, and fast turn-on speed.
  • V th threshold voltage
  • the transistor noise of high-speed transistors is easy to superpose, resulting in poor stability of the delay time of high-speed transistors.
  • One possible approach is to improve the power supply stability of high-speed transistors, that is, to improve the stability of the local power supply.
  • the resistance value of the local power network can be reduced by increasing the number of local power buses 30 or increasing the line width of the local power bus 30, thereby improving the stability of the local power supply.
  • This method has two shortcomings. The first is that when the local power supply requirements are extremely stringent (such as a double-edge handshake signal), even if power is provided to the standard cell array through all local power buses 30, the local power supply cannot be guaranteed. The resistance of the network meets the requirements.
  • the second is that even if the resistance value of the power network is reduced to meet the requirements by increasing the number of local power buses 30 and increasing the line width of the local power buses 30, this will occupy more lines of the third wiring layer M2 ( track), resulting in insufficient lines for subsequent layout settings.
  • FIG. 7 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 8 is an enlarged schematic diagram of a standard unit in the semiconductor structure shown in FIG. 7 .
  • the semiconductor structure includes a new standard cell array 10 ′.
  • the new standard cell array 10 ′ includes a plurality of standard cells, where at least some of the standard cells include a logic device 100 and a switch driving device 200 .
  • the switch driving device 200 and the logic device 100 are arranged in a standard unit to form a logic device standard unit with a switch driving device.
  • the semiconductor structure shown in Figure 7 includes an inverter standard unit invPF ⁇ 4_new with a switch driver device, a NOR gate standard unit nor3PF ⁇ 2_new with a switch driver device, and a NOR gate standard unit nor2PF ⁇ 2_new with a switch driver device.
  • Figure 8 shows the inverter standard unit invPF ⁇ 4_new with switch driving device.
  • This embodiment takes invPF ⁇ 4_new as an example to illustrate the layout and connection method of the logic device 100 and the switch driving device 200 in each standard unit.
  • the logic device 100 includes a first power line 400 and a second power line 500 located on the same wiring layer.
  • the first power line 400 and the second power line 500 both extend along a first direction (for example, the X direction), and along The second direction (for example, Y direction) is arranged side by side, and the first direction and the second direction intersect and are parallel to the plane where the wiring layer is located.
  • the switch driving device 200 and the logic device 100 are arranged side by side along the On the same wiring layer, the first input line 610 and the first output line 620 both extend along the X direction and are arranged side by side along the Y direction, where the first output line 620 is connected to the first power line 400 .
  • the first power line 400 is used to receive the power supply Vcc or the local power supply local Vcc
  • the second power line 500 is used to receive the common ground signal Vss or the local ground signal local Vss.
  • the switch driving device 200 includes a PMOS transistor MPa.
  • the PMOS transistor MPa includes a first input line 610 and a first output line 620.
  • the first output line 620 is connected to the first power line 400 of the logic device 100.
  • the switch driving device 200 The first power line 400 of the logic device 100 provides local power supply local Vcc.
  • the second power line 500 of the logic device 100 is used to receive the common ground signal Vss.
  • the logic device 100 and the switch driving device 200 are arranged side by side along the first direction, and the first power line 400 and the second power line 500 of the logic device 100 are arranged along the first direction.
  • the first output line 620, the first power line 400 and the second power line 500 of the switch driving device 200 are all located in the same wiring layer (that is, the second wiring layer M1), where the first output line 620 and the second power line 500 are all located in the same wiring layer (ie, the second wiring layer M1).
  • One power cord for 400 connections are provided.
  • the current flows through the following path: the first drain line 216 of the switching driving device 200 ⁇ the interconnection hole V1 ⁇ the first output line 620 of the switching driving device 200 ⁇ logic
  • the first power line 400 of the device 100 ⁇ the interconnection hole V1 ⁇ the source line 115 of the logic device 100, that is, the current flows through: M0 ⁇ V1 ⁇ M1 ⁇ V1 ⁇ M0.
  • the interconnection hole V2 is not passed through during the transmission process, so the resistance value of the local power network can be reduced and the loss during current transmission can be reduced, thereby improving the stability of the local power supply of the logic device 100 and thereby improving the delay time of the logic device 100 stability.
  • first power line 400 and the first output line 620 both extend along the X direction until they are connected to each other. Therefore, the first power line 400 and the first output line 620 are shorter, which can further reduce the local network The resistance value reduces the loss during current transmission.
  • the first power line 400 includes a first body line 410 and a first local line 420.
  • the first body line 410 and the first local line 420 are arranged side by side along the Y direction, wherein the first output line 620 and The first local line 420 is connected, and the first input line 610 is connected to the first body line 410 .
  • the first body line 410 is used to connect the power supply Vcc
  • the first local line 420 is used to connect the local power supply local Vcc.
  • the first input line 610 of the PMOS transistor MPa is used to connect the power supply Vcc
  • the first body line 410 of the logic device 100 is used to connect the power supply Vcc. Therefore, the first input line 610 and the first body line 410 can be connected, It is used to provide power Vcc to the PMOS transistor MPa or the logic device 100 .
  • the first output line 620 of the PMOS transistor MPa is connected to the first local line 420 of the logic device 100, so that the PMOS transistor MPa provides the local power supply local Vcc to the logic device 100.
  • the second power line 500 includes a second body line 510 and a second local line 520, and the second body line 510 and the second local line 520 are arranged side by side along the Y direction.
  • the switch driving device 200 further includes an NMOS transistor MNa.
  • the NMOS transistor MNa includes a second input line 630 and a second output line 640.
  • the second input line 630, the second output line 640 and the second power line 500 are located on the same wiring layer, that is, Located on the second wiring layer M1.
  • the second input line 630 and the second output line 640 both extend along the X direction and are arranged side by side along the Y direction.
  • the second input line 630 is connected to the second body line 510 and the second output line 640 is connected to the second local line. 520 connection.
  • the second body line 510 is used to connect the common ground Vss
  • the second local line 520 is used to connect the local ground local Vss.
  • the second input line 630 of the NMOS transistor MNa is used to connect to the common ground Vss
  • the second body line 510 of the logic device 100 is used to connect to the common ground Vss. Therefore, the second input line 630 and the second body line 510 can be connected to the common ground Vss. Connection for providing common ground Vss to NMOS transistor MNa or logic device 100 .
  • the second output line 640 of the NMOS transistor MNa is connected to the second local line 520 of the logic device 100, so that the NMOS transistor MNa provides the local ground signal local Vss to the logic device 100.
  • the logic device 100 includes a first body line 410 , a first local line 420 , a second body line 510 and a second local line 520 arranged side by side along the Y direction
  • the switch driving device 200 includes a The first input line 610, the first output line 620, the second input line 630 and the second output line 640 are arranged side by side in the Y direction, wherein the first body line 410 and the first input line 610 are connected to each other, and the first local line 420 and the first output line 620 are connected to each other, the second body line 510 and the second input line 630 are connected to each other, and the second local line 520 and the second output line 640 are connected to each other.
  • the first local line 420 can be electrically connected to the source lines 115 of the two load tubes through the first interconnection hole V1a.
  • the second interconnection hole V1b electrically connects the second body line 510 to the source lines 125 of the two drive tubes, and is used to provide local power supply local Vcc to the sources of the two load tubes, and to provide local power Vcc to the sources of the two drive tubes.
  • Common ground signal Vss Common ground signal
  • the first body line 410 can be electrically connected to the two load tube source lines 115 through a third interconnect hole (not shown in the figure), and the first body line 410 can be electrically connected to the two load tube source lines 115 through a fourth interconnect hole (not shown in the figure).
  • the second local line 520 is electrically connected to the source lines 125 of the two drive tubes to provide power Vcc to the sources of the two load tubes and the local ground signal local Vss to the sources of the two drive tubes. .
  • the first body line 410 can be electrically connected to the two load tube source lines 115 through the third interconnection hole V1b
  • the second body line 510 can be electrically connected to the two drive tube source lines 115 through the second interconnection hole V1b.
  • the source lines 125 of the tubes are electrically connected and used to provide power Vcc to the sources of the two load tubes and a common ground signal Vss to the sources of the two drive tubes.
  • the interconnection hole V1 includes a first interconnection hole V1a, a second interconnection hole V1b, a third interconnection hole, and a fourth interconnection hole, that is, the first interconnection hole V1a, the second interconnection hole V1b, and the fourth interconnection hole V1.
  • the third interconnection hole and the fourth interconnection hole are both located between the second wiring layer M1 and the first wiring layer M0.
  • first body line 410 and the first local line 420 cannot be electrically connected to the source lines 115 of the two load tubes at the same time, and only one of them can be selected to be connected to the source line 115 .
  • the second body line 510 and the second local line 520 cannot be electrically connected to the source lines 125 of the two drive tubes at the same time, and only one of them can be selected to be connected to the source line 125 .
  • the standard unit provided by the embodiment of the present disclosure can be provided with the first interconnection hole V1a and the second interconnection hole V1b, or the third interconnection hole and the fourth interconnection hole, or the third interconnection hole as needed. hole and the second interconnect hole V1b to provide three power supplies to the logic device 100.
  • This standard unit has a wide range of applications and can provide different power supplies to a variety of logic devices 100 .
  • the switch driving device 200 includes a PMOS transistor and an NMOS transistor.
  • the switch driving device may also include only PMOS transistors for providing local power supply local Vcc to the logic device.
  • the switch driving device may only include an NMOS transistor, the first output line of the switch driving device may be connected to the second power line, and the switch driving device provides the local ground signal local Vss to the second power line of the logic device. , the first power line of the logic device is used to receive the power supply Vcc.
  • the line width of the first output line 620 along the Y direction is equal to the line width of the first local line 420 along the Y direction
  • the line width of the first input line 610 along the Y direction is equal to the line width of the first body line 410 along the Y direction
  • the line width of the second output line 640 along the Y direction is equal to the line width of the second local line 520 along the Y direction
  • the line width of the second input line 630 along the Y direction is equal to the line width of the second body line 510 along the Y direction. Width.
  • the first output line 620 and the first local line 420 are actually one conductive line
  • the second output line 640 and the second local line 520 are also one conductive line
  • the second input line 630 and the second body line 510 are also one conductive line
  • the second output line 640 and the second local line 520 are also a conductive line.
  • the second wiring layer includes four conductive lines arranged side by side along the Y direction. This arrangement can make the standard cells more regular and help improve the layout efficiency of the semiconductor structure.
  • FIG. 9 is a circuit diagram of the switch driving device in the standard unit shown in FIG. 8 .
  • the switch driving device 200 includes a plurality of parallel PMOS transistors MPa and a plurality of parallel NMOS transistors MNa.
  • the source of each PMOS transistor MPa is connected to the power supply Vcc; the drains are connected to each other for outputting the local power supply local Vcc; the gates are connected to each other so that the multiple parallel-connected PMOS transistors MPa can be connected simultaneously. Turn on.
  • each NMOS transistor MNa is connected to the common ground Vss; the drains are connected to each other for outputting the local common ground signal local Vss; the gates are connected to each other to enable multiple parallel NMOS Transistor MNa is turned on at the same time.
  • multiple parallel-connected PMOS transistors MPa and multiple parallel-connected NMOS transistors MNa can improve the driving capability of the switch driving device 200 to meet the power consumption requirements of the logic device 100.
  • the structure of the PMOS transistor MPa is basically the same as the structure of the first load transistor MP1 and the second load transistor MP2 in the logic device 100, and therefore will not be described again.
  • the first well region includes multiple first source regions and multiple first drain regions.
  • the pole regions are alternately arranged along the X direction, each first active region is provided with a first source line 215, each first drain region is provided with a first drain line 216, and multiple first source lines 215 and a plurality of first drain lines 216 are alternately arranged along the X direction on the first wiring layer M0.
  • a first channel is provided between the adjacent first source region and the first drain region in the first well region.
  • a first gate 213 is provided on each first channel.
  • a plurality of first gates 213 are provided along the The directions are arranged side by side and connected.
  • each PMOS transistor MPa includes a first gate 213 , and first source regions and first drain regions located on both sides of the first gate 213 .
  • Two adjacent PMOS transistors MPa share a first source region or a first drain region.
  • the first input line 610 is electrically connected to the plurality of first source lines 215 through the interconnection hole V1, and the sources of the plurality of PMOS transistors MPa in the corresponding circuit are all connected to Vcc.
  • the first output line 620 is electrically connected to the plurality of first drain lines 216 through the interconnection hole V1, and the drains of the plurality of PMOS transistors MPa in the corresponding circuit are connected to each other for outputting the local power supply local Vcc.
  • each NMOS transistor MNa is basically the same as the structure of the first driving transistor MN1 and the second driving transistor MN2 in the logic device 100 .
  • each NMOS transistor MNa also includes: a second source region, a second channel and a second drain region (not shown in the figure) located in the second well region of the substrate, and a third Two gates 223, a second source line 225 and a second drain line 226.
  • the second well region is a p-type well region
  • the second source region, the second channel and the second drain region are arranged side by side along the X direction
  • the second source region and the second drain region are n-type doped. complex area.
  • the second gate 223 covers the second channel and extends along the Y direction.
  • the second source line 225 and the second drain line 226 are located on the first wiring layer M0.
  • the second source line 225 and the second drain line 226 both extend along the Y direction, and are arranged side by side along the X direction.
  • the second source line 225 is electrically connected to the second source region through the contact plug CT
  • the second drain line 226 is electrically connected to the second drain region through the contact plug CT.
  • the second input line 630 and the second output line 640 are located on the second wiring layer M1.
  • the second input line 630 is electrically connected to the second source line 225 through the interconnection hole V1.
  • the second output line 640 is electrically connected to the second source line 225 through the interconnection hole V1.
  • the two drain lines 226 are electrically connected.
  • the second well region includes multiple second source regions and multiple second drain regions, and the second source regions and the second drain regions are along the X direction.
  • each second active region is provided with a second source line 225
  • each second drain region is provided with a second drain line 226, a plurality of second source lines 225 and a plurality of third
  • the two drain lines 226 are alternately arranged along the X direction on the first wiring layer M0.
  • a second channel is provided between the adjacent second source region and the second drain region in the second well region.
  • a second gate 223 is provided on each second channel.
  • a plurality of second gates 223 are provided along the The directions are arranged side by side and connected.
  • each NMOS transistor MNa includes a second gate 223 , and a second source region and a second drain region located on both sides of the second gate 223 .
  • Two adjacent NMOS transistors MNa share a second source region or a second drain region.
  • the second input line 630 is electrically connected to the plurality of second source lines 225 through the interconnection hole V1, and the sources of the plurality of NMOS transistors MNa in the corresponding circuit are connected to Vss.
  • the second output line 640 is electrically connected to the plurality of second drain lines 226 through the interconnection hole V1, and the drains of the plurality of NMOS transistors MNa in the corresponding circuit are connected to each other for outputting the local ground signal local Vss.
  • the first gate 213 of the PMOS transistor MPa and the second gate 223 of the NMOS transistor MNa are connected. It should be understood that the PMOS transistor MPa is turned on at a low level and turned off at a high level, while the NMOS transistor MNa is turned on at a high level and turned off at a low level. In this embodiment, the first gate 213 of the PMOS transistor MPa and the second gate 223 of the NMOS transistor MNa are connected. When a high level is applied to the gates of both, the NMOS transistor MNa is turned on and the PMOS transistor MPa is turned off, so that , the local ground signal local Vss can be provided to the logic device 100. When a low level is applied, the PMOS transistor MPa is turned on and the NMOS transistor MNa is turned off. In this way, the local power supply local Vss can be provided to the logic device 100.
  • the first gate 213 of the PMOS transistor MPa and the second gate 223 of the NMOS transistor MNa may be disconnected from each other and controlled independently.
  • the first gate 213 of the PMOS transistor MPa and the second gate 223 of the NMOS transistor MNa are connected.
  • it can avoid the situation of simultaneously providing the local power supply local Vcc and the local ground signal local Vss to the logic device 100.
  • the situation on the other hand, is simpler in operation. It only needs to change the level to achieve the output of local power supply local Vcc or local ground signal local Vss.
  • the switch driving device 200 also includes:
  • the first gate connection line 217 is located on the same wiring layer as the first gate electrode 213.
  • the first gate connection line 217 extends along the X direction and connects the ends of the plurality of first gate electrodes 213 relatively close to the second gate electrode 223. ;
  • the second gate connection line 227 is located on the same wiring layer as the second gate electrode 223.
  • the second gate connection line 227 extends along the X direction and connects the ends of the plurality of second gate electrodes 223 relatively close to the first gate electrode 213. ;
  • the first auxiliary connection line 218 is located on the first wiring layer M0.
  • the first auxiliary connection line 218 includes a first part extending along the X direction and a second part extending along the Y direction. The first part is in contact with the first gate connection line 217. Plug CT electrical connection;
  • the second auxiliary connection line 228 is located on the first wiring layer M0.
  • the second auxiliary connection line 228 includes a third part extending along the X direction and a fourth part extending along the Y direction.
  • the third part is connected to the second gate connection line 227 Electrically connected by contact plug CT; in a plane perpendicular to the X direction, the orthographic projection of the second part and the orthographic projection of the fourth part at least partially overlap;
  • the gate control line (not shown in the figure) extends along the X direction and is electrically connected to the second part and the fourth part.
  • the gate control line is located on the first wiring layer M0. Since the orthographic projection of the second part and the orthographic projection of the fourth part at least partially overlap in the plane perpendicular to the X direction, the gate control line extending along the X direction can be provided in the second wiring layer to convert the The second part and the fourth part are connected to control the opening of the PMOS transistor MPa or the NMOS transistor MNa by inputting a low level or a high level to the gate control line to realize the output of the local power supply local Vcc or the local ground signal local Vss.
  • the gate control line may also be located on the second wiring layer M1 and be electrically connected to the second part and the fourth part through the interconnection hole V1.
  • nor3PF ⁇ 2_new, nor2PF ⁇ 2_new, nand3PF ⁇ 2_new and nand2PF ⁇ 2_new described in Figure 7 are respectively composed of nor3PF ⁇ 2, nor2PF ⁇ 2, nand3PF ⁇ 2, nand2PF ⁇ 2 and switch driving devices.
  • Nor3PF ⁇ 2, nor2PF ⁇ 2, nand3PF ⁇ 2, and nand2PF ⁇ 2 are basically composed of PMOS transistors and NMOS transistors. Therefore, the layout method of the inverter invPF ⁇ 4 provided by this embodiment can reasonably deduce the layout method of the NOR gate circuit Nor3PF ⁇ 2, nor2PF ⁇ 2 and the NAND gate circuit nand3PF ⁇ 2, nand2PF ⁇ 2.
  • the layout methods of nor2PF ⁇ 2_new, nor2PF ⁇ 2_new, nand3PF ⁇ 2_new and nand2PF ⁇ 2_new are effectively introduced, so the details will not be described in this disclosure.
  • the above-mentioned logic device usually includes a first component and a second component arranged in parallel in the Y direction.
  • the first component includes a plurality of PMOS transistors
  • the second component includes a plurality of NMOS transistors.
  • the first component has a first power lead-out line located on the first wiring layer.
  • the first power lead-out line is the source line of the PMOS transistor (for example, the source line 115 of the first load tube MP1 and the second load tube MP2).
  • the second component has a second power supply lead-out line located on the first wiring layer.
  • the second power supply lead-out line is the source line of the NMOS transistor (for example, the source line 125 of the first driver tube MN1 and the second driver tube MN2). .
  • the first local line is electrically connected to the first power lead-out line through the first interconnection hole
  • the second body line is electrically connected to the second power lead-out line through the second interconnection hole; or, the first body line is electrically connected to the third interconnection hole
  • the second local line is electrically connected to the first power outlet line through the fourth interconnection hole.
  • the switch driving devices of different logic devices can be different.
  • the size of the corresponding switch driving device (for example, the number of PMOS transistors and NMOS transistors in the switch driving device) can be obtained according to the driving requirements of the logic device, and then the logic device and its corresponding switch driving device can be integrated integrated into a standard unit.
  • the first input line, the first output line, the second input line and the second output line of the standard cell are respectively connected with the first body line, the first local line of the standard cell adjacent in the X direction.
  • the line, the second body line and the second local line are connected, and FIG. 7 shows the first local line 420 and the second body line 510 therein.
  • multiple standard units arranged side by side in the X direction share four conductive lines arranged side by side in the Y direction. Each conductive line extends along the Ground signal Vss and local ground signal Local Vss.
  • the semiconductor structure also includes a power connection line 700 located in the third wiring layer M2.
  • the power connection line 700 extends along the Y direction and is connected to the first local line 420 or the first output line of a plurality of standard cells arranged side by side along the Y direction. .
  • the power connection line 700 connects the first local lines 420 of multiple standard units arranged in parallel along the Y direction to form a parallel branch for balancing the driving capabilities of each standard unit.
  • the power connection line 700 and the local power bus 30 in Figure 1 are both located at the third wiring layer M2, their functions are different.
  • the local power bus 30 is used to provide local power to the standard cell array, with large driving capacity and relatively low power consumption. Large, the line width is large, and the power connection line 700 shown in Figure 7 only functions as a parallel branch, so the line width is smaller and the number can be smaller, thereby saving the line channels of the third wiring layer M2 .
  • FIG. 10 is a schematic diagram of the current path of the semiconductor structure shown in FIG. 1 in the working state
  • FIG. 11 is a schematic diagram of the current path of the semiconductor structure shown in FIG. 7 in the working state.
  • the gray area in the figure is the location of the switch driving device 200. Comparing Figure 11 and Figure 10, it can be seen that in the semiconductor structure provided by the embodiment of the present disclosure, the switch driving device 200 and the logic device 100 are alternately arranged along the X direction. The distance between the switch driving device 200 and the logic device 100 is closer, and the current transmission path is shorter. Short, almost the shortest, so it can greatly reduce the resistance of the local power network and improve the stability of the local power supply.
  • the resistance values of the second wiring layer M1 and the third wiring layer M2 in the local power network shown in Figure 10 are mostly 2ohm to 4ohm, and some areas are even 4ohm to 5ohm.
  • the resistance values of the second wiring layer M1 and the third wiring layer M2 in the local power network shown in Figure 11 are mostly 1.3ohm to 2ohm, and some are 2ohm to 3.3ohm. It can be seen that the resistance value of the local power supply network of the semiconductor structure shown in Figure 7 is significantly better than that of the semiconductor structure shown in Figure 1.
  • the semiconductor structure provided by the embodiment of the present disclosure can reduce the resistance of the local power supply network and improve the stability of the local power supply.
  • the present disclosure also provides a memory including the semiconductor structure as described above.
  • the memory may be dynamic random access memory (DRAM), static random access memory (SRAM), three-dimensional NAND flash memory, two-dimensional NAND flash memory, phase change memory, etc.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • three-dimensional NAND flash memory three-dimensional NAND flash memory
  • two-dimensional NAND flash memory phase change memory, etc.
  • Embodiments of the present disclosure also provide a layout structure for preparing the semiconductor structure as described above.
  • the layout structure includes:
  • the logic device layout includes a first power line pattern and a second power line pattern located on the same layout wiring layer.
  • the first power line pattern and the second power line pattern both extend along the first direction and are arranged side by side along the second direction. cloth, the first direction and the second direction intersect, the logic device layout is used to define the logic device, the first power line graphic is used to define the first power line, and the second power line graphic is used to define the second power line;
  • the switch driving device layout is arranged side by side with the logic device layout along the first direction.
  • the switch driving device layout includes a first input line pattern and a first output line pattern, the first input line pattern and the first output line pattern and the first power line.
  • the graphics are located on the same layout wiring layer.
  • the first input line pattern and the first output line pattern both extend along the first direction and are arranged side by side along the second direction.
  • the first output line pattern extends along the first direction and is parallel to the first output line pattern.
  • a power line pattern or a second power line pattern is connected; the switch driving device layout is used to define the switch driving device, the first input line pattern is used to define the first input line, and the first output line pattern is used to define the first output line.
  • the layout structure includes a standard cell layout
  • the standard cell layout includes a logic device layout and a switch driving device layout
  • the standard cell layout is used to define the above-mentioned standard cells.
  • the first power line pattern includes a first body line pattern and a first local line pattern, and the first body line pattern and the first local line pattern are arranged side by side along the second direction; the first body line pattern is used to Define the first main body line, and the first local line graphic is used to define the first local line;
  • the first output line pattern is connected to the first local line pattern, and the first input line pattern is connected to the first body line pattern.
  • the second power line pattern includes a second body line pattern and a second local line pattern, and the second body line pattern and the second local line pattern are arranged side by side along the second direction; the second body line pattern is used to Define the second body line, and the second local line graphic is used to define the second local line;
  • the switch driving device layout also includes: a second input line pattern and a second output line pattern, which are located on the same layout wiring layer as the second power line pattern, both of the second input line pattern and the second output line pattern extend along the first direction, and Arranged side by side along the second direction, wherein the second output line graphic is connected to the second local line graphic, the second input line graphic is connected to the second body line graphic; the second input line graphic is used to define the second input line, The Second Output Line graphic is used to define the second output line.
  • the logic device layout further includes: a first component layout and a second component layout arranged side by side in the second direction.
  • the first component layout has a first power pinout pattern located on the wiring layer of the first layout, and the second component layout
  • the component layout has a second power supply pinout pattern located on the first layout wiring layer, and both the first power supply pinout line pattern and the second power supply pinout line pattern extend along the second direction; the first component layout is used to define the first component, and the second power supply pinout pattern is used to define the first component.
  • the component layout is used to define the second component, the first power supply lead-out line graphic is used to define the first power supply lead-out line, and the second power supply lead-out line graphic is used to define the second power supply lead-out line;
  • the first body line pattern, the first local line pattern, the second body line pattern and the second local line pattern are located on the second layout wiring layer, and the second layout wiring layer is located on the first layout wiring layer; wherein, the first local line pattern
  • the first plug pattern is connected to the first power lead-out line pattern, and the second body line pattern is connected to the second power lead-out line pattern through the second plug pattern; or the first body line pattern is connected to the third power lead-out line pattern through the third plug pattern.
  • a power lead-out line pattern is connected, the second local line is connected to the second power lead-out line pattern through a fourth plug pattern, the first plug pattern, the second plug pattern, the third plug pattern and the fourth plug pattern are respectively Used to define the first plug, second plug, third plug and fourth plug.
  • the number of multiple standard unit layouts is multiple, and the multiple standard unit layouts are arranged in an array, wherein, along the first direction, the first input line pattern and the first output line pattern of the standard unit layout are , the second input line graphics and the second output line graphics are respectively connected to the first body line graphics, the first local line graphics, the second body line graphics and the second local line graphics of the adjacent standard unit layout;
  • the layout structure also includes: a power connection line pattern located on a third layout wiring layer, the third layout wiring layer is located on the second layout wiring layer, the power connection line pattern extends along the second direction and is arranged side by side along the second direction.
  • the first local line graphic or the first output line graphic of multiple standard unit layouts is connected; the power connection line graphic is used to define the power connection line.
  • the logic device layout includes at least one of an inverter layout, a logic gate circuit layout, a buffer layout, or a latch layout, and the inverter layout, logic gate circuit layout, buffer layout, and latch
  • the inverter layout is used to define the inverter, logic gate circuit, buffer and latch respectively.
  • the logic device and the switch driving device are arranged side by side along the first direction, the first power line and the second power line of the logic device extend along the first direction, and the first output line of the switch driving device , the first power line and the second power line are located on the same wiring layer, wherein the first output line is connected to the first power line, or the first output line or the second power line is connected.
  • the switch driving device provides local power to the logic device, the current flows directly from the first output line of the switch driving device into the first power line or the second power line of the logic device without passing through the interconnection hole, so local power can be greatly reduced.
  • the resistance value of the power network reduces the loss during current transfer, thereby improving the stability of the local power supply of the logic device, thereby improving the stability of the delay time of the logic device.
  • first power line (or the second power line) and the first output line both extend along the first direction until they are connected to each other. Therefore, the first power line (or the second power line) and the first output line
  • the shorter lines can further reduce the resistance value of the local network, reduce the loss during current transmission, and improve the stability of the delay time of the logic device.

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Abstract

本公开实施例提供了一种版图结构、半导体结构以及存储器，该半导体结构包括：逻辑器件，包括位于同一布线层的第一电源线和第二电源线，所述第一电源线和所述第二电源线均沿第一方向延伸，且沿第二方向并列排布，所述第一方向和所述第二方向相交且均平行于所述布线层所在平面；开关驱动器件，与所述逻辑器件沿所述第一方向并列排布，所述开关驱动器件包括第一输入线和第一输出线，所述第一输入线和所述第一输出线与所述第一电源线位于同一布线层，所述第一输入线和所述第一输出线均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第一输出线与所述第一电源线或者所述第二电源线连接。

Description

版图结构、半导体结构以及存储器
相关申请的交叉引用
本公开基于申请号为202211073818.7、申请日为2022年09月02日、发明名称为“版图结构、半导体结构以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，特别是涉及一种版图结构、半导体结构以及存储器。
背景技术
标准单元是集成电路设计的基础，标准单元可包括反相器、逻辑门电路、寄存器、缓冲器等集成电路中常使用的逻辑器件。在进行集成电路设计时，可根据设计需要，调用标准单元库中的标准单元版图来完成集成电路的版图布局设计，能够提高电路的设计效率。随着半导体器件的高集成度和高性能，优化标准单元是一种既能提高设计效率，又能提高半导体器件集成度和性能的可行手段。
发明内容
根据本公开的第一个方面，提供了一种半导体结构，包括：
逻辑器件，包括位于同一布线层的第一电源线和第二电源线，所述第一电源线和所述第二电源线均沿第一方向延伸，且沿第二方向并列排布，所述第一方向和所述第二方向相交且均平行于所述布线层所在平面；
开关驱动器件，与所述逻辑器件沿所述第一方向并列排布，所述开关驱动器件包括第一输入线和第一输出线，所述第一输入线和所述第一输出线与所述第一电源线位于同一布线层，所述第一输入线和所述第一输出线均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第一输出线与所述第一电源线或者所述第二电源线连接。
上述方案中，所述第一电源线包括第一主体线和第一本地线，所述第一主体线和所述第一本地线沿所述第二方向并列排布；
所述第一输出线与所述第一本地线连接，所述第一输入线与所述第一主体线连接。
上述方案中，所述第二电源线包括第二主体线和第二本地线，所述第二主体线和所述第二本地线沿所述第二方向并列排布；
所述开关驱动器件还包括：第二输入线和第二输出线，与所述第二电源线位于同一布线层，所述第二输入线和所述第二输出线均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第二输入线与所述第二主体线连接，所述第二输出线与所述第二本地线连接。
上述方案中，所述第一输出线沿所述第二方向的线宽，等于所述第一本地线沿所述第二方向的线宽；
所述第一输入线沿所述第二方向的线宽，等于所述第一主体线沿所述第二方向的线宽；
所述第二输出线沿所述第二方向的线宽，等于所述第二本地线沿所述第二方向的线宽；
所述第二输入线沿所述第二方向的线宽，等于所述第二主体线沿所述第二方向的线宽。
上述方案中，所述逻辑器件还包括：在所述第二方向并列设置的第一部件和第二部件，所述第一部件具有位于第一布线层的第一电源引出线，所述第二部件具有位于所述第一布线层的第二电源引出线，所述第一电源引出线和所述第二电源引出线均沿所述第二方向延伸；
所述第一主体线、所述第一本地线、所述第二主体线和所述第二本地线位于第二布线层，所述第二布线层位于所述第一布线层上；
其中，所述第一本地线通过第一互连孔与所述第一电源引出线电连接，所述第二主体线通过第二互连孔与所述第二电源引出线电连接；或者，所述第一主体线通过第三互连孔与所述第一电源引出线电连接，所述第二本地线通过第四互连孔与所述第二电源引出线电连接。
上述方案中，所述开关驱动器件还包括：
第一阱区，包括沿所述第一方向并列排布的第一源极区、第一沟道和第一漏极区；
第一栅极，位于所述第一沟道上且沿所述第二方向延伸；
第一源极线，位于所述第一布线层，所述第一源极线、所述第一源极区和所述第一输入线电连接，所述第一源极线沿所述第二方向延伸；
第一漏极线，位于所述第一布线层，所述第一漏极线、所述第一漏极区和所述第一输出线电连接，所述第一漏极线沿所述第二方向延伸。
上述方案中，所述第一阱区包括多个所述第一源极区和多个所述第一漏极区，所述第一源极区和所述第一漏极区沿所述第一方向交替排布，相邻所述第一源极区和所述第一漏极区之间设置有所述第一沟道，每一所述第一沟道上设置有所述第一栅极；
所述第一栅极的数量为多个，多个所述第一栅极沿所述第一方向并列排布且相连接。
上述方案中，所述开关驱动器件还包括：
第二阱区，与所述第一阱区沿所述第二方向并列排布，所述第二阱区包括沿所述第一方向并列排布的第二源极区、第二沟道和第二漏极区；
第二栅极，位于所述第二沟道上且沿所述第二方向延伸；
第二源极线，位于所述第一布线层，所述第二源极线、所述第二源极区和所述第二输入线电连接，所述第二源极线沿所述第二方向延伸；
第二漏极线，位于所述第一布线层，所述第二漏极线、所述第二漏极区和所述第二输出线电连接，所述第二漏极线沿所述第二方向延伸。
上述方案中，所述第二阱区包括多个所述第二源极区和多个所述第二漏极区，所述第二源极区和所述第二漏极区沿所述第一方向交替排布，相邻所述第二源极区和所述第二漏极区之间设置有所述第二沟道，每一所述第二沟道上设置有所述第二栅极；
所述第二栅极的数量为多个，多个所述第二栅极沿所述第一方向并列排布且相连接。
上述方案中，所述开关驱动器件还包括：
第一栅极连接线，与所述第一栅极位于同一布线层，所述第一栅极连接线沿所述第一方向延伸，且连接多个所述第一栅极相对靠近所述第二栅极的端部；
第二栅极连接线，与所述第二栅极位于同一布线层，所述第二栅极连接线沿所述第一方向延伸，且连接多个所述第二栅极相对靠近所述第一栅极的端部；
第一辅助连接线，位于所述第一布线层，所述第一辅助连接线包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一部分与所述第一栅极连接线电连接；
第二辅助连接线，位于所述第一布线层，所述第二辅助连接线包括沿所述第一方向延伸的第三部分和沿所述第二方向延伸的第四部分，所述第三部分与所述第二栅极连接线电连接；在垂直于所述第一方向的平面内，所述第二部分的正投影和所述第四部分的正投影至少部分重叠；
栅极控制线，沿所述第一方向延伸，且与所述第二部分和所述第四部分电连接。
上述方案中，所述半导体结构包括多个标准单元，所述标准单元包括所述逻辑器件和所述开关驱动器件，多个所述标准单元呈阵列排布；
其中，所述标准单元的所述第一输入线、第一输出线、第二输入线和第二输出线分别与沿所述第一方向上相邻的所述标准单元的第一主体线、第一本地线、第二主体线和第二本地线连接；
所述半导体结构还包括：电源连接线，位于第三布线层，所述第三布线层位于所述第二布线层上，所述电源连接线沿所述第二方向延伸，且与沿所述第二方向并列排布的多个所述标准单元的所述第一本地线或所述第一输出线连接。
上述方案中，所述逻辑器件包括反相器、逻辑门电路、缓冲器或锁存器中的至少一种。
根据本公开的第二个方面，提供了一种存储器，包括如本公开第一个方面所述的半导体结构。
根据本公开的第三个方面，提供了一种版图结构，包括：
逻辑器件版图，包括位于同一版图布线层的第一电源线图形和第二电源线图形，所述第一电源线图形和所述第二电源线图形均沿第一方向延伸，且沿第二方向并列排布，所述第一方向和所述第二方向相交，所述逻辑器件版图用于定义逻辑器件，所述第一电源线图形用于定义第一电源线，所述第二电源线图形用于定义第二电源线；
开关驱动器件版图，与所述逻辑器件版图沿所述第一方向并列排布，所述开关驱动器件版图包括第一输入线图形和第一输出线图形，所述第一输入线图形和所述第一输出线图形与所述第一电源线图形位于同一版图布线层，所述第一输入线图形和所述第一输出线图形均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第一输出线图形沿所述第一方向延伸，且与所述第一电源线图形或者所述第二电源线图形连接；所述开关驱动器件版图用于定义开关驱动器件，所述第一输入线图形用于定义第一输入线，所述第一输出线图形用于定义第一输出线。
上述方案中，所述版图结构包括标准单元版图，所述标准单元版图包括所述逻辑器件版图和所述开关驱动器件版图，所述标准单元版图用于定义所述标准单元。
本公开实施例提供的半导体结构中，逻辑器件和开关驱动器件沿第一方向并列排布，逻辑器件的第一电源线和第二电源线沿第一方向延伸，开关驱动器件的第一输出线、第一电源线和第二电源线位于同一布线层，其中，第一输出线与第一电源线连接，或者第一输出线或第二电源线连接。当开关驱动器件向逻辑器件提供本地电源时，电流从开关驱动器件的第一输出线直接流入逻辑器件的第一电源线或第二电源线，不会经过互连孔，因此可以大大减小本地电源网络的电阻值，减少电流传递过程中的损失，从而提高逻辑器件的本地电源的稳定性，进而提高逻辑器件的延迟时间的稳定性。
进一步地，第一电源线(或第二电源线)和第一输出线均是沿第一方向延伸至二者相互连接，因此，第一电源线(或第二电源线)和第一输出线的线路较短，可进一步减小本地网络的电阻值，减小电流传递过程中的损耗，提高逻辑器件的延迟时间的稳定性。
附图说明
图1为本公开实施例提供的一种半导体结构的版图布局示意图；
图2a为本公开实施例提供的逻辑器件和开关驱动器件的一种电路连接示意图；
图2b为本公开实施例提供的逻辑器件和开关驱动器件的又一种电路连接示意图；
图3为图1所示的半导体结构中逻辑器件和开关驱动器件的放大示意图；
图4为图3所示的逻辑器件和开关驱动器件的电路图；
图5为图3中逻辑器件的放大示意图；
图6为图5所示的逻辑器件沿A-A线的剖视图；
图7为本公开实施例提供的又一种半导体结构的版图布局示意图；
图8为图7所示的半导体结构中一种标准单元的放大示意图；
图9为图8所示的标准单元中开关驱动器件的电路图；
图10为图1所示的半导体结构在工作状态的电流路径示意图；
图11为图7所示的半导体结构在工作状态的电流路径示意图。
具体实施方式
以下结合说明书附图及具体实施例对本公开的技术方案做详细阐述。
在本公开的描述中，需要理解的是，术语“长度”、“宽度”、“深度”、“上”、“下”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
图1为本公开实施例提供的一种半导体结构的版图布局示意图。该半导体结构包括标准单元阵列10，标准单元阵列10包括多个标准单元。示例地，如图1所示，标准单元阵列包括4×12个标准单元。
标准单元可包括不同类型的逻辑器件。逻辑器件可以是缓冲器(buffer，简写为buf)、寄存器(Register)、反相器(inverter，简写为inv)以及逻辑门电路等。逻辑门电路包括但不限于或非门电路(nor)、与非门电路(nand)等。需要说明的是，图中存在nand3PF×2类似的表述，在此进行统一的定义说明，其中nand表征任意逻辑门电路，“3”表征逻辑门电路的输入端数量，PF表征不限制电源端，将接地端限定为主接地端Vss，并列的还包括GF，表征不限制接地端，将电源端限定为主电源端Vcc，“×2”表征逻辑门电路中MOS管的宽长比。
该半导体结构还包括两个开关驱动器件阵列20，沿Y方向分设于标准单元阵列10的两侧。开关驱动器件阵列20包括多个开关驱动器件(Switch CMOS Driver Cell，简写为Scmos Drv cell)。示例地，如图1所示，开关驱动器件阵列可包括10×1个开关驱动器件，其中，“10”表征开关驱动器件的数量，“×1”表征开关驱动器件中MOS管的宽长比。
该半导体结构还包括多条沿Y方向延伸的本地电源总线30(local power bus)，本地电源总线30将开关驱动器件和逻辑器件电连接。开关驱动器件用来控制逻辑器件(也即标准单元阵列)的电源的开关。示例地，开关驱动器件包括PMOS晶体管(P沟道增强型场效应管)、NMOS晶体管(N沟道增强型场效应管)、或者由PMOS晶体管和NMOS晶体管组成的CMOS电路。
开关驱动器件与逻辑器件的电路连接方式有两种，一种是通过关断逻辑器件的电源信号来关断逻辑器件，另一种是通过断开逻辑器件的接地信号来关断逻辑器件。
图2a和图2b示出了开关驱动器件和逻辑器件的两种连接方式。如图2a所示，开关驱动器件为PMOS晶体管MPa，PMOS晶体管MPa的漏极与电源Vcc连接，源极与逻辑器件的电源端连接，逻辑器件的接地端与公共接地Vss连接。当PMOS晶体管MPa开启时，开关驱动器件向逻辑器件提供电源。示例地，将由开关驱动器件提供的电源，称为本地电源local Vcc。当PMOS晶体管MPa关闭时，则可关断逻辑器件的电源。
如图2b所示，开关驱动器件为NMOS晶体管MNa，NMOS晶体管MNa的漏极与公共接地Vss连接，源极与逻辑器件的接地端连接，逻辑器件的电源端与电源Vcc连接。当NMOS晶体管MNa开启时，开关驱动器件用于向逻辑器件提供接地信号。示例地，将由开关驱动器件提供的接地信号，称为本地接地信号local Vss。当NMOS晶体管MNa关闭时，则可关断逻辑器件的电源。
结合上述分析，需说明的是，逻辑器件有三种电源提供方式，第一种是电源端连接电源Vcc，接地端连接公共接地Vss；第二种是电源端连接开关驱动器件，接收本地电源local Vcc，接地端连接公共接地Vss；第三种是电源端连接电源Vcc，接地端连接开关驱动器件，接收本地接地信号local Vss。
图3为图1所示的半导体结构中逻辑器件和开关驱动器件的放大示意图，也即图1中虚线框所示的区域的放大示意图。这里，逻辑器件100为invPF×4，本实施例以逻辑器件为invPF×4为例，说明逻辑器件100与开关驱动器件200的布局和连接方式。
图4为图3所示的逻辑器件和开关驱动器件的电路图。如图4所示，开关驱动器件200包括多个并联的PMOS晶体管Mpa。示例地，本实施例中，开关驱动器件200包括5个并联的PMOS晶体管Mpa。因此，图1中开关驱动器件阵列20通过多条本地电源总线30向标准单元阵列10提供本地电源local Vcc。应当理解，在另一些实施例中，开关驱动器件阵列也可通过多条本地电源总线向标准单元阵列提供本地接地信号local Vss。
参见图4，该逻辑器件100包括第一负载管MP1、第一驱动管MN1、第二负载管MP2以及第二驱动管MN2，其中，第一负载管MP1和第二负载管MP2为PMOS晶体管，第一驱动管MN1和第二驱动管MN2为NMOS晶体管。
第一负载管MP1的源极连接开关驱动器件的输出端，用于接收本地电源local Vcc，第一负载管MP1的漏极和第一驱动管MN1的漏极均连接至节点b1，第一驱动管MN1的源极连接公共接地Vss，第一负载管MP1栅极和第一驱动管MN1的栅极均连接至节点a1。第二负载管MP2的源极也连接开关驱动器件的输出端，用于接收本地电源local Vcc，第二负载管MP2的漏极和第二驱动管MN2的漏极均连接至节点b2，第二驱动管MN2的源极连接公共接地Vss，第二负载管MP2的栅极和第二驱动管MN2的栅极均连接至节点a2。其中，节点a1和节点a2连接，节点b1和节点b2连接。
该逻辑器件100包括两个并联的反相器，其中，第一负载管MP1和第一驱动管MN1构成 第一反相器，节点a1为第一反相器的输入端，节点b1为第一反相器的输出端；第二负载管MP2和第二驱动管MN2构成第二反相器，节点a2为第二反相器的输入端，节点b2为第二反相器的输出端。节点a1和节点a2连接，节点b1和节点b2连接，也即第一反相器的输入端和第二反相器的输入端连接，第一反相器的输出端和第二反相器的输出端连接，第一反相器和第二反相器并联。
图5为图3中逻辑器件的放大示意图，图6为图5所示的逻辑器件沿A-A线的剖视图。参见图4至图6，在衬底内形成n型阱区和p型阱区，在n型阱区形成第一负载管MP1和第二负载管MP2，第一负载管MP1和第二负载管MP2沿X方向并列排布，在p型阱区形成第一驱动管MN1和第二驱动管MN2，第一驱动管MN1和第二驱动管MN2沿X方向并列排布。第一负载管MP1和第一驱动管MN1沿Y方向并列排布，第二负载管MP2和第二驱动管MN2沿Y方向并列排布。
如图6所示，第一负载管MP1和第二负载管MP2均包括位于n型阱区内的源极区111和漏极区112，源极区111和漏极区112均为p型掺杂区域。源极区111和漏极区112沿X方向排布且相互隔离，源极区111和漏极区112之间形成沟道。本实施例中，第一负载管和第二负载管共用漏极区112。
两个负载管(指第一负载管MP1和第二负载管MP2)还包括覆盖沟道的栅极结构，栅极结构包括沿Y方向延伸的栅极113，以及位于栅极113和沟道之间的栅极介质层。两个负载管的栅极113沿X方向并列排布，并且通过沿X方向延伸的子连接线114电连接。子连接线114与栅极113位于同一布线层。
同理，第一驱动管MN1和第二驱动管MN2均包括位于p型阱区内的源极区(图中未示出)、沟道和漏极区(图中未示出)，以及覆盖沟道的栅极结构，其中，源极区、沟道和漏极区沿X方向并列排布，源极区和漏极区均为n型掺杂区域，第一驱动管MN1和第二驱动管MN2共用漏极区。如图5所示，栅极结构包括沿Y方向延伸的栅极123，以及位于栅极123和沟道之间的栅极介质层。两个驱动管(指第一驱动管MN1和第二驱动管MN2)的栅极123沿X方向并列排布，并且通过沿X方向延伸的子连接线124电连接。子连接线124与栅极123位于同一布线层。
这里，两个负载管的栅极113和两个驱动管的栅极123位于同一布线层，但是相互隔离，也即未在该布线层进行电连接。
继续参见图5和图6，该逻辑器件100还包括两个负载管的源极线115和漏极线116，两个负载管的源极线115和漏极线116均沿Y方向延伸，且通过接触插塞CT与其源极区和漏极区电连接。这里，定义两个负载管的源极线115和漏极线116位于第一布线层M0，第一布线层M0位于栅极所在的布线层之上。接触插塞CT位于第一布线层M0和衬底之间，或者接触插塞CT位于第一布线层M0和有源区之间。
示例地，每个负载管的源极线115可通过对应的接触插塞CT与其源极区111电连接，每个负载管的漏极线116可通过对应的接触插塞CT与其漏极区112电连接。
同理，该逻辑器件还包括两个驱动管的源极线125和漏极线126，两个驱动管的源极线125和漏极线126均沿Y方向延伸，且通过接触插塞CT分别与其源极区和漏极区电连接。这里，两个驱动管的源极线125和漏极线126均位于第一布线层M0。
这里，在第一布线层M0中，两个负载管共用的漏极线116与两个驱动管共用的漏极线126彼此连接，换言之，漏极线116和漏极线126为一条导电线。漏极线116和漏极线126彼此连接，对应电路中节点b1和b2连接。
第一布线层M0中还包括总连接线118，沿Y方向延伸，总连接线118通过接触插塞CT与子连接线114、子连接线124电连接，对应电路中节点a1和节点a2连接。
继续参见图5和图6，该逻辑器件还包括第一本地线420和第二主体线510，这里，第一本地线420用于向逻辑器件提供本地电源local Vcc，第二主体线510用于向逻辑器件提供公共接地信号Vss。第一本地线420和第二主体线510均沿X方向延伸，且两者沿Y方向并列排布。其中，第一本地线420通过互连孔V1与两个负载管的源极线115电连接，第二主体线510通过接触孔V1与两个驱动管的源极线125电连接。这里，第一本地线420和第二主体线510位于第二布线层M1，第二布线层M1位于第一布线层M0至上。互连孔V1位于第二布线层M1和第 一布线层M0之间。
示例地，第一本地线420通过多个互连孔V1与两个负载管的源极线115电连接，第二主体线510通过多个互连孔V1与两个驱动管的源极线125电连接。
继续参见图5和图6，本地电源总线30位于第三布线层M2，第三布线层M2位于第二布线层M1之上。本地电源总线30通过互连孔V2与逻辑器件的第一本地线420电连接。互连孔V2位于第三布线层M2和第二布线层M1之间。
该逻辑器件还包括互连孔V3和互连孔V4，其中，互连孔V3位于漏极线116和/或漏极线126上，用作该逻辑器件的输出端，互连孔V4位于总连接线118上，用作该逻辑器件的输入端。
参见图3，开关驱动器件200包括多个并联的PMOS晶体管MPa，其结构和布局方式与逻辑器件中的第一负载管MP1和第二负载管MP2的结构和布局方式基本相同。PMOS晶体管Mpa包括：位于衬底的第一阱区内的第一源极区、第一沟道和第一漏极区(图中未示出)、以及第一栅极213、第一源极线215、第一漏极线216、第一输入线610和第一输出线620。其中，第一阱区为n型阱区，第一源极区、第一沟道和第一漏极区沿X方向并列排布，第一源极区和第一漏极区为p型掺杂区域。
第一栅极213覆盖第一沟道，且沿Y方向延伸。第一源极线215和第一漏极线216位于第一布线层M0，第一源极线215和第一漏极线216均沿Y方向延伸，且二者沿X方向并列排布。其中，第一源极线215通过接触插塞CT与第一源极区电连接，第一漏极线216通过接触插塞CT与第一漏极区电连接。
第一输入线610和第一输出线620位于第二布线层M1，第一输入线610和第一输出线620均沿X方向延伸，且二者沿Y方向并列排布。其中，第一输入线610通过互连孔V1与第一源极线215电连接，第一输出线620通过互连孔V1与第一漏极线216电连接。
本地电源总线30通过互连孔V2与第一输出线620电连接，以使开关驱动器件向逻辑器件的第一本地线420提供本地电源local VCC。
当图1所示的半导体结构应用至LPDDR(Low Power Double Data Rate SDRAM)的电路中时，部分逻辑器件(例如图1中实线框所包括的invPF×4、nor3PF×2、nand3PF×2、nor2PF×2、nand2PF×2)可由多个高速晶体管(简称Lvt管，Low V th)组成。高速晶体管的阈值电压(V th)低，延迟时间短，开启速度快。但是高速晶体管的晶体管噪声容易叠加，导致高速晶体管的延迟时间的稳定性差。一种可行的方法是提高高速晶体管的电源稳定性，也即提高本地电源的稳定性。
在一些实施例中，可通过增加本地电源总线30的条数，或者增大本地电源总线30的线宽，来减小本地电源网络的电阻值，从而提高本地电源的稳定性。
但是这种方式有两个缺点，第一是当对本地电源要求极其严苛的情况下(比如双沿握手信号)，即使通过所有本地电源总线30向标准单元阵列提供电源，也无法保证本地电源网络的阻值达到要求。这是因为当开关驱动器件向逻辑器件提供本地电源时，电流的流经路径为：开关驱动器件的第一漏极线216→互连孔V1→开关驱动器件的第一输出线620→互连孔V2→本地电源总线30→互连孔V2→逻辑器件的第一本地线420→互连孔V1→逻辑器件的源极线115，也即电流依次流经：M0→V1→M1→V2→M2→V2→M1→V1→M0。传输过程中两次经过互连孔V1，两次经过互连孔V2，由于互连孔的电阻值较大，导致本地电源网络的电阻值较大，传输过程损耗较大，本地信号的稳定性较差。
第二是，即使通过增加本地电源总线30的数量，增大本地电源总线30的线宽来减小电源网络的电阻值至达到需要，但是这样占用了第三布线层M2较多的线道(track)，导致后续的版图设置没有足够的线道。
鉴于此，本公开实施例提供了一种半导体结构。图7为本公开实施例提供的一种半导体结构的示意图，图8为图7所示的半导体结构中一种标准单元的放大示意图。参见图7和图8，该半导体结构包括新标准单元阵列10′，新标准单元阵列10′包括多个标准单元，其中，至少部分标准单元包括逻辑器件100和开关驱动器件200。换言之，本公开实施例中，将开关驱动器件200和逻辑器件100设置在一个标准单元中，形成带开关驱动器件的逻辑器件标准单元。
图7所示的半导体结构包括带开关驱动器件的反相器标准单元invPF×4_new、带开关驱动器件的或非门标准单元nor3PF×2_new、带开关驱动器件的或非门标准单元nor2PF×2_new、带开关驱动器件的与非门标准单元nand3PF×2_new和带开关驱动器件的与非门标准单元nand2PF×2_new。
图8示出的是带开关驱动器件的反相器标准单元invPF×4_new。本实施例以invPF×4_new为例，说明每个标准单元中逻辑器件100与开关驱动器件200的布局和连接方式。
参见图8，逻辑器件100包括位于同一布线层的第一电源线400和第二电源线500，第一电源线400和第二电源线500均沿第一方向(例如X方向)延伸，且沿第二方向(例如Y方向)并列排布，第一方向和第二方向相交且均平行于布线层所在平面。
开关驱动器件200与逻辑器件100沿X方向并列排布，开关驱动器件200包括第一输入线610和第一输出线620，第一输入线610和第一输出线620与第一电源线400位于同一布线层，第一输入线610和第一输出线620均沿X方向延伸，且沿Y方向并列排布，其中，第一输出线620与第一电源线400连接。
示例地，第一电源线400用于接收电源Vcc或者本地电源local Vcc，第二电源线500用于接收公共接地信号Vss或者本地接地信号local Vss。
示例地，开关驱动器件200包括PMOS晶体管MPa，PMOS晶体管MPa包括第一输入线610和第一输出线620，第一输出线620与逻辑器件100的第一电源线400连接，开关驱动器件200向逻辑器件100的第一电源线400提供本地电源local Vcc。逻辑器件100的第二电源线500用于接收公共接地信号Vss。
以图8所示的标准单元为例，本公开实施例中，逻辑器件100和开关驱动器件200沿第一方向并列排布，逻辑器件100的第一电源线400和第二电源线500沿第一方向延伸，开关驱动器件200的第一输出线620、第一电源线400和第二电源线500均位于同一布线层(也即第二布线层M1)，其中，第一输出线620与第一电源线400连接。当开关驱动器件200向逻辑器件100提供本地电源时，电流的流经路径为：开关驱动器件200的第一漏极线216→互连孔V1→开关驱动器件200的第一输出线620→逻辑器件100的第一电源线400→互连孔V1→逻辑器件100的源极线115，也即电流依次流经：M0→V1→M1→V1→M0。传输过程中未经过互连孔V2，因此可以减小本地电源网络的电阻值，减少电流传递过程中的损失，从而提高逻辑器件100的本地电源的稳定性，进而提高逻辑器件100的延迟时间的稳定性。
进一步地，第一电源线400和第一输出线620均是沿X方向延伸至二者相互连接，因此，第一电源线400和第一输出线620的线路较短，可进一步减小本地网络的电阻值，减小电流传递过程中的损耗。
在一些实施例中，第一电源线400包括第一主体线410和第一本地线420，第一主体线410和第一本地线420沿Y方向并列排布，其中，第一输出线620与第一本地线420连接，第一输入线610与第一主体线410连接。
示例地，第一主体线410用于连接电源Vcc，第一本地线420用于连接本地电源local Vcc。
应当理解，PMOS晶体管MPa的第一输入线610用于连接电源Vcc，逻辑器件100的第一主体线410用于连接电源Vcc，因此，可以将第一输入线610和第一主体线410连接，用于向PMOS晶体管MPa或者逻辑器件100提供电源Vcc。PMOS晶体管MPa的第一输出线620与逻辑器件100的第一本地线420连接，以使PMOS晶体管MPa向逻辑器件100提供本地电源local Vcc。
在一些实施例中，第二电源线500包括第二主体线510和第二本地线520，第二主体线510和第二本地线520沿Y方向并列排布。
开关驱动器件200还包括NMOS晶体管MNa，NMOS晶体管MNa包括第二输入线630和第二输出线640，第二输入线630、第二输出线640与第二电源线500位于同一布线层，也即位于第二布线层M1。第二输入线630和第二输出线640均沿X方向延伸，且沿Y方向并列排布，其中，第二输入线630与第二主体线510连接，第二输出线640与第二本地线520连接。
示例地，第二主体线510用于连接公共接地Vss，第二本地线520用于连接本地接地local Vss。
应当理解，NMOS晶体管MNa的第二输入线630用于连接公共接地Vss，逻辑器件100的第二主体线510用于连接公共接地Vss，因此，可以将第二输入线630和第二主体线510连 接，用于向NMOS晶体管MNa或者逻辑器件100提供公共接地Vss。NMOS晶体管MNa的第二输出线640与逻辑器件100的第二本地线520连接，以使NMOS晶体管MNa向逻辑器件100提供本地接地信号local Vss。
总言之，本实施例中，逻辑器件100包括沿Y方向并列排布的第一主体线410、第一本地线420、第二主体线510和第二本地线520，开关驱动器件200包括沿Y方向并列排布的第一输入线610、第一输出线620、第二输入线630和第二输出线640，其中，第一主体线410和第一输入线610彼此连接，第一本地线420和第一输出线620彼此连接，第二主体线510和第二输入线630彼此连接，第二本地线520和第二输出线640彼此连接。
根据上文所述的逻辑器件100的电路提供方式可知，在一些实施例中，可通过第一互连孔V1a将第一本地线420与两个负载管的源极线115电连接，通过第二互连孔V1b将第二主体线510与两个驱动管的源极线125电连接，用于向两个负载管的源极提供本地电源local Vcc，向两个驱动管的源极提供的公共接地信号Vss。
在另一些实施例中，可通过第三互连孔(图中未示出)将第一主体线410与两个负载管源极线115电连接，通过第四互连孔(图中未示出)将第二本地线520与两个驱动管的源极线125电连接，用于向两个负载管的源极提供电源Vcc，向两个驱动管的源极提供的本地接地信号local Vss。
在另一些实施例中，还可通过第三互连孔将第一主体线410与两个负载管源极线115电连接，通过第二互连孔V1b将第二主体线510与两个驱动管的源极线125电连接，用于向两个负载管的源极提供电源Vcc，向两个驱动管的源极提供的公共接地信号Vss。
这里，互连孔V1包括第一互连孔V1a、第二互连孔V1b、第三互连孔和第四互连孔，也即第一互连孔V1a、第二互连孔V1b、第三互连孔和第四互连孔均位于第二布线层M1和第一布线层M0之间。
应当理解，第一主体线410和第一本地线420不能同时与两个负载管的源极线115电连接，只能择其一与源极线115连接。第二主体线510和第二本地线520不能同时与两个驱动管的源极线125电连接，只能择其一与源极线125连接。
综上所述，本公开实施例提供的标准单元，可根据需要设置第一互连孔V1a和第二互连孔V1b、或者第三互连孔和第四互连孔、或者第三互连孔和第二互连孔V1b，向逻辑器件100提供三种电源。该标准单元的适用范围广，能向多种逻辑器件100提供不同的电源。
需要说明的是，图8所示的实施例中，开关驱动器件200包括PMOS晶体管和NMOS晶体管。在另一些实施例中，开关驱动器件也可只包括PMOS晶体管，用于向逻辑器件提供本地电源local Vcc。在另一些实施例中，开关驱动器件也可只包括NMOS晶体管，开关驱动器件的第一输出线可与第二电源线连接，开关驱动器件向逻辑器件的第二电源线提供本地接地信号local Vss，逻辑器件的第一电源线用于接收电源Vcc。
在一些实施例中，第一输出线620沿Y方向的线宽等于第一本地线420沿Y方向的线宽，第一输入线610沿Y方向的线宽等于第一主体线410沿Y方向的线宽，第二输出线640沿Y方向的线宽等于第二本地线520沿Y方向的线宽，第二输入线630沿Y方向的线宽等于第二主体线510沿Y方向的线宽。
换言之，第一输出线620和第一本地线420其实是一条导电线，第二输出线640和第二本地线520也是一条导电线，第二输入线630和第二主体线510也是一条导电线，第二输出线640和第二本地线520也是一条导电线。第二布线层包括沿Y方向并列排布的四条导电线。这样设置，能使标准单元更加规整，利于提高半导体结构的布局效率。
图9为图8所示的标准单元中开关驱动器件的电路图。参见图8和图9，本实施例中，开关驱动器件200包括多个并联的PMOS晶体管MPa和多个并列的NMOS晶体管MNa。多个并联的PMOS晶体管MPa中，每个PMOS晶体管MPa的源极连接至电源Vcc；漏极相互连接，用于输出本地电源local Vcc；栅极相互连接，以使多个并联的PMOS晶体管MPa同时开启。多个并列的NMOS晶体管MNa中，每个NMOS晶体管MNa的源极连接至公共接地Vss；漏极相互连接，用于输出本地公共接地信号local Vss；栅极相互连接，以使多个并列的NMOS晶体管MNa同时开启。
本实施例中，多个并联的PMOS晶体管MPa和多个并联的NMOS晶体管MNa能够提高开 关驱动器件200的驱动能力，以满足逻辑器件100的功耗要求。
如上文所示，PMOS晶体管MPa的结构和逻辑器件100中的第一负载管MP1和第二负载管MP2的结构基本相同，故不赘述。
需要说明的是，当多个PMOS晶体管MPa并联时，如图8所示，第一阱区包括多个第一源极区和多个第一漏极区，第一源极区和第一漏极区沿X方向交替排布，每个第一有源区上设置有第一源极线215，每个第一漏极区上设置有第一漏极线216，多个第一源极线215和多个第一漏极线216在第一布线层M0沿X方向交替排布。
第一阱区内相邻第一源极区和第一漏极区之间设置有第一沟道，每个第一沟道上设置有第一栅极213，多个第一栅极213沿X方向并列排布且相连接。
这里，每个PMOS晶体管MPa包括一个第一栅极213，以及位于第一栅极213两侧的第一源极区和第一漏极区。相邻两个PMOS晶体管MPa共用第一源极区或者共用第一漏极区。
第一输入线610通过互连孔V1与多个第一源极线215电连接，对应电路中多个PMOS晶体管MPa的源极均连接至Vcc。第一输出线620通过互连孔V1与多个第一漏极线216电连接，对应电路中多个PMOS晶体管MPa的漏极相互连接，用于输出本地电源local Vcc。
此外，NMOS晶体管MNa的结构和逻辑器件100中的第一驱动管MN1和第二驱动管MN2的结构也基本相同。如图8所示，每个NMOS晶体管MNa还包括：位于衬底的第二阱区内的第二源极区、第二沟道和第二漏极区(图中未示出)、以及第二栅极223、第二源极线225和第二漏极线226。其中，第二阱区为p型阱区，第二源极区、第二沟道和第二漏极区沿X方向并列排布，第二源极区和第二漏极区为n型掺杂区域。
第二栅极223覆盖第二沟道，且沿Y方向延伸。第二源极线225和第二漏极线226位于第一布线层M0，第二源极线225和第二漏极线226均沿Y方向延伸，且二者沿X方向并列排布。其中，第二源极线225通过接触插塞CT与第二源极区电连接，第二漏极线226通过接触插塞CT与第二漏极区电连接。
第二输入线630和第二输出线640位于第二布线层M1，第二输入线630通过互连孔V1与第二源极线225电连接，第二输出线640通过互连孔V1与第二漏极线226电连接。
当多个NMOS晶体管MNa并联时，如图8所示，第二阱区包括多个第二源极区和多个第二漏极区，第二源极区和第二漏极区沿X方向交替排布，每个第二有源区上设置有第二源极线225，每个第二漏极区上设置有第二漏极线226，多个第二源极线225和多个第二漏极线226在第一布线层M0沿X方向交替排布。
第二阱区内相邻第二源极区和第二漏极区之间设置有第二沟道，每个第二沟道上设置有第二栅极223，多个第二栅极223沿X方向并列排布且相连接。
这里，每个NMOS晶体管MNa包括一个第二栅极223，以及位于第二栅极223两侧的第二源极区和第二漏极区。相邻两个NMOS晶体管MNa共用第二源极区或者共用第二漏极区。
第二输入线630通过互连孔V1与多个第二源极线225电连接，对应电路中多个NMOS晶体管MNa的源极均连接至Vss。第二输出线640通过互连孔V1与多个第二漏极线226电连接，对应电路中多个NMOS晶体管MNa的漏极相互连接，用于输出本地接地信号local Vss。
进一步地，参见图11，PMOS晶体管MPa的第一栅极213和NMOS晶体管MNa的第二栅极223相连接。应当理解，PMOS晶体管MPa为低电平导通，高电平截止，而NMOS晶体管MNa为高电平导通，低电平截止。本实施例中，将PMOS晶体管MPa的第一栅极213和NMOS晶体管MNa的第二栅极223连接，当向二者的栅极施加高电平时，NMOS晶体管MNa开启而PMOS晶体管MPa关闭，如此，可向逻辑器件100提供本地接地信号local Vss，当施加低电平时，PMOS晶体管MPa开启而NMOS晶体管MNa关闭，如此，可向逻辑器件100提供本地电源local Vss。
需要说明的是，在其它一些实施例中，PMOS晶体管MPa的第一栅极213和NMOS晶体管MNa的第二栅极223可互不连接，单独控制。而本实施例中，将PMOS晶体管MPa的第一栅极213和NMOS晶体管MNa的第二栅极223连接，一方面可避免出现同时向逻辑器件100提供本地电源local Vcc和本地接地信号local Vss的情况，另一方面，操作上更为简单，只需要改变电平，既能实现输出本地电源local Vcc或者本地接地信号local Vss。
为实现PMOS晶体管MPa的第一栅极213和NMOS晶体管MNa的第二栅极223相连接，在 布局上，开关驱动器件200还包括：
第一栅极连接线217，与第一栅极213位于同一布线层，第一栅极连接线217沿X方向延伸，且连接多个第一栅极213相对靠近第二栅极223的端部；
第二栅极连接线227，与第二栅极223位于同一布线层，第二栅极连接线227沿X方向延伸，且连接多个第二栅极223相对靠近第一栅极213的端部；
第一辅助连接线218，位于第一布线层M0，第一辅助连接线218包括沿X方向延伸的第一部分和沿Y方向延伸的第二部分，第一部分与第一栅极连接线217通过接触插塞CT电连接；
第二辅助连接线228，位于第一布线层M0，第二辅助连接线228包括沿X方向延伸的第三部分和沿Y方向延伸的第四部分，第三部分与第二栅极连接线227通过接触插塞CT电连接；在垂直于X方向的平面内，第二部分的正投影和第四部分的正投影至少部分重叠；
栅极控制线(图中未示出)，沿X方向延伸，且与第二部分和第四部分电连接。在一些实施例中，栅极控制线位于第一布线层M0。由于在垂直于X方向的平面内，第二部分的正投影和第四部分的正投影至少部分重叠，因此，可通过在第二布线层内设置沿X方向延伸的栅极控制线，将第二部分和第四部分连接，以通过向栅极控制线输入低电平或高电平，控制PMOS晶体管MPa或NMOS晶体管MNa的开启，实现输出本地电源local Vcc或者本地接地信号local Vss。
在另一些实施例中，栅极控制线也可位于第二布线层M1，通过互连孔V1与第二部分和第四部分电连接。
应当理解，图7所述的nor3PF×2_new、nor2PF×2_new、nand3PF×2_new和nand2PF×2_new，分别由nor3PF×2、nor2PF×2、nand3PF×2、nand2PF×2与开关驱动器件组合而成。Nor3PF×2、nor2PF×2、nand3PF×2、nand2PF×2基本由PMOS晶体管和NMOS晶体管组合而成。因此由本实施例提供的反相器invPF×4的布局方式，可合理地推出或非门电路Nor3PF×2、nor2PF×2和与非门电路nand3PF×2、nand2PF×2的布局方式，进而可合理地推出nor2PF×2_new、nor2PF×2_new、nand3PF×2_new和nand2PF×2_new的布局方式，故本公开不做赘述。
需要说明的是，上述逻辑器件通常包括在Y方向并列设置的第一部件和第二部件，示例地，第一部件包括多个PMOS晶体管，第二部件包括多个NMOS晶体管。第一部件具有位于第一布线层的第一电源引出线，示例地，第一电源引出线为PMOS晶体管的源极线(例如第一负载管MP1和第二负载管MP2的源极线115)。第二部件具有位于第一布线层的第二电源引出线，示例地，第二电源引出线为NMOS晶体管的源极线(例如第一驱动管MN1和第二驱动管MN2的源极线125)。第一本地线通过第一互连孔与第一电源引出线电连接，第二主体线通过第二互连孔与第二电源引出线电连接；或者，第一主体线通过第三互连孔与第一电源引出线电连接，第二本地线通过第四互连孔与第二电源引出线电连接。
需要说明的是，不同逻辑器件的开关驱动器件可以不同。在一些实施例中，可以根据逻辑器件的驱动需求，得到对应的开关驱动器件的尺寸(例如，开关驱动器件中PMOS晶体管和NMOS管的数量)，进而把逻辑器件和其对应的开关驱动器件集成整合成一个标准单元。
在标准单元阵列10′中，标准单元的第一输入线、第一输出线、第二输入线和第二输出线分别与沿X方向上相邻的标准单元的第一主体线、第一本地线、第二主体线和第二本地线连接，图7示出了其中的第一本地线420和第二主体线510。换言之，沿X方向并列排布的多个标准单元共用四条沿Y方向并列排布的导电线，每条导电线沿X方向延伸，四条导电线分别用于输出电源Vcc、本地电源local Vcc、公共接地信号Vss和本地接地信号Local Vss。
半导体结构还包括电源连接线700，位于第三布线层M2，电源连接线700沿Y方向延伸，且与沿Y方向并列排布的多个标准单元的第一本地线420或第一输出线连接。
电源连接线700将沿Y方向并列排布的多个标准单元的第一本地线420并联，形成并联支路，用于均衡各个标准单元的驱动能力。虽然电源连接线700和图1中的本地电源总线30都位于第三布线层M2，但是二者的作用不同，本地电源总线30用于向标准单元阵列提供本地电源，驱动能力大，功耗较大，线宽较大，而图7所示的电源连接线700，只起到并联支路的作用，因此线宽较小，数量也可较少，从而节省了第三布线层M2的线道。
对比图1和图7可知，图7所示的第三布线层M2中的相邻电源连接线700沿X方向 的间距L2，远大于图1所示的第三布线层M2中相邻本地电源总线30沿X方向的间距L1。间距L2几乎等于间距L1的二倍，如此节省了第三布线层M2的线道。并且新标准单元阵列更加规整，布局更容易。
图10为图1所示的半导体结构在工作状态的电流路径示意图，图11为图7所示的半导体结构在工作状态的电流路径示意图。图中灰色区域为开关驱动器件200所在位置。对比图11和图10可知，本公开实施例提供的半导体结构中开关驱动器件200与逻辑器件100沿X方向交替排布，开关驱动器件200和逻辑器件100的距离更近，电流的传输路径更短，几乎是最短，因此可大大降低本地电源网络的电阻，提高本地电源的稳定性。
此外，根据实测数据，图10所示的本地电源网络中第二布线层M1和第三布线层M2的阻值大部分为2ohm至4ohm，部分区域甚至在4ohm至5ohm。图11所示的本地电源网络中第二布线层M1和第三布线层M2的阻值大部分为1.3ohm至2ohm，部分在2ohm至3.3ohm。可见，图7所示的半导体结构的本地电源网络的电阻值明显优于图1所示的半导体结构，本公开实施例提供的半导体结构能降低本地电源网络的电阻，提高本地电源的稳定性。
本公开还提供了一种存储器，包括如上所述的半导体结构。
示例地，该存储器可以是动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、三维NAND闪存存储器、二维NAND闪存存储器、相变存储器等。
本公开实施例还提供了一种版图结构，用于制备如上所述的半导体结构，该版图结构包括：
逻辑器件版图，包括位于同一版图布线层的第一电源线图形和第二电源线图形，第一电源线图形和所述第二电源线图形均沿第一方向延伸，且沿第二方向并列排布，第一方向和第二方向相交，逻辑器件版图用于定义逻辑器件，第一电源线图形用于定义第一电源线，第二电源线图形用于定义第二电源线；
开关驱动器件版图，与逻辑器件版图沿第一方向并列排布，开关驱动器件版图包括第一输入线图形和第一输出线图形，第一输入线图形和第一输出线图形与第一电源线图形位于同一版图布线层，第一输入线图形和第一输出线图形均沿第一方向延伸，且沿第二方向并列排布，其中，第一输出线图形沿第一方向延伸，且与第一电源线图形或者第二电源线图形连接；开关驱动器件版图用于定义开关驱动器件，第一输入线图形用于定义第一输入线，所第一输出线图形用于定义第一输出线。
在一些实施例中，版图结构包括标准单元版图，标准单元版图包括逻辑器件版图和开关驱动器件版图，标准单元版图用于定义上述标准单元。
在一些实施例中，第一电源线图形包括第一主体线图形和第一本地线图形，第一主体线图形和第一本地线图形沿第二方向并列排布；第一主体线图形用于定义第一主体线，第一本地线图形用于定义第一本地线；
第一输出线图形与第一本地线图形连接，第一输入线图形与第一主体线图形连接。
在一些实施例中，第二电源线图形包括第二主体线图形和第二本地线图形，第二主体线图形和第二本地线图形沿第二方向并列排布；第二主体线图形用于定义第二主体线，第二本地线图形用于定义第二本地线；
开关驱动器件版图还包括：第二输入线图形和第二输出线图形，与第二电源线图形位于同一版图布线层，第二输入线图形和第二输出线图形均沿第一方向延伸，且沿第二方向并列排布，其中，第二输出线图形与第二本地线图形连接，第二输入线图形与第二主体线图形连接；第二输入线图形用于定义第二输入线，第二输出线图形用于定义第二输出线。
在一些实施例中，逻辑器件版图还包括：在第二方向并列设置的第一部件版图和第二部件版图，第一部件版图具有位于第一版图布线层的第一电源引出线图形，第二部件版图具有位于第一版图布线层的第二电源引出线图形，第一电源引出线图形和第二电源引出线图形均沿第二方向延伸；第一部件版图用于定义第一部件，第二部件版图用于定义第二部件，第一电源引出线图形用于定义第一电源引出线，第二电源引出线图形用于定义第二电源引出线；
第一主体线图形、第一本地线图形、第二主体线图形和第二本地线图形位于第二版图 布线层，第二版图布线层位于第一版图布线层上；其中，第一本地线图形通过第一插塞图形与第一电源引出线图形连接，第二主体线图形通过第二插塞图形与第二电源引出线图形连接；或者，第一主体线图形通过第三插塞图形与第一电源引出线图形连接，第二本地线通过第四插塞图形与第二电源引出线图形连接，第一插塞图形、第二插塞图形、第三插塞图形和第四插塞图形分别用于定义第一插塞、第二插塞、第三插塞和第四插塞。
在一些实施例中，多个标准单元版图的数量为多个，多个标准单元版图呈阵列排布，其中，沿第一方向上，标准单元版图的第一输入线图形、第一输出线图形、第二输入线图形和第二输出线图形分别与相邻标准单元版图的第一主体线图形、第一本地线图形、第二主体线图形和第二本地线图形连接；
版图结构还包括：电源连接线图形，位于第三版图布线层，所述第三版图布线层位于第二版图布线层上，电源连接线图形沿第二方向延伸，且与沿第二方向并列排布的多个标准单元版图的第一本地线图形或第一输出线图形连接；电源连接线图形用于定义电源连接线。
在一些实施例中，逻辑器件版图包括反相器版图、逻辑门电路版图、缓冲器版图或锁存器版图中的至少一种，反相器版图、逻辑门电路版图、缓冲器版图和锁存器版图分别用于定义反相器、逻辑门电路、所述缓冲器和锁存器。
上述实施例仅例示性说明本公开的原理及其功效，而非用于限制本公开。任何熟悉此技术的人士皆可在不违背本公开的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本公开所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本公开的权利要求所涵盖。
工业实用性
本公开实施例提供的半导体结构中，逻辑器件和开关驱动器件沿第一方向并列排布，逻辑器件的第一电源线和第二电源线沿第一方向延伸，开关驱动器件的第一输出线、第一电源线和第二电源线位于同一布线层，其中，第一输出线与第一电源线连接，或者第一输出线或第二电源线连接。当开关驱动器件向逻辑器件提供本地电源时，电流从开关驱动器件的第一输出线直接流入逻辑器件的第一电源线或第二电源线，不会经过互连孔，因此可以大大减小本地电源网络的电阻值，减少电流传递过程中的损失，从而提高逻辑器件的本地电源的稳定性，进而提高逻辑器件的延迟时间的稳定性。
进一步地，第一电源线(或第二电源线)和第一输出线均是沿第一方向延伸至二者相互连接，因此，第一电源线(或第二电源线)和第一输出线的线路较短，可进一步减小本地网络的电阻值，减小电流传递过程中的损耗，提高逻辑器件的延迟时间的稳定性。

Claims (15)

  1. 一种半导体结构，包括：
    逻辑器件，包括位于同一布线层的第一电源线和第二电源线，所述第一电源线和所述第二电源线均沿第一方向延伸，且沿第二方向并列排布，所述第一方向和所述第二方向相交且均平行于所述布线层所在平面；
    开关驱动器件，与所述逻辑器件沿所述第一方向并列排布，所述开关驱动器件包括第一输入线和第一输出线，所述第一输入线和所述第一输出线与所述第一电源线位于同一布线层，所述第一输入线和所述第一输出线均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第一输出线与所述第一电源线或者所述第二电源线连接。
  2. 根据权利要求1所述的半导体结构，其中，所述第一电源线包括第一主体线和第一本地线，所述第一主体线和所述第一本地线沿所述第二方向并列排布；
    所述第一输出线与所述第一本地线连接，所述第一输入线与所述第一主体线连接。
  3. 根据权利要求2所述的半导体结构，其中，所述第二电源线包括第二主体线和第二本地线，所述第二主体线和所述第二本地线沿所述第二方向并列排布；
    所述开关驱动器件还包括：第二输入线和第二输出线，与所述第二电源线位于同一布线层，所述第二输入线和所述第二输出线均沿所述第一方向延伸，且沿所述第二方向并列排布，其中，所述第二输入线与所述第二主体线连接，所述第二输出线与所述第二本地线连接。
  4. 根据权利要求3所述的半导体结构，其中，所述第一输出线沿所述第二方向的线宽，等于所述第一本地线沿所述第二方向的线宽；
    所述第一输入线沿所述第二方向的线宽，等于所述第一主体线沿所述第二方向的线宽；
    所述第二输出线沿所述第二方向的线宽，等于所述第二本地线沿所述第二方向的线宽；
    所述第二输入线沿所述第二方向的线宽，等于所述第二主体线沿所述第二方向的线宽。
  5. 根据权利要求3所述的半导体结构，其中，所述逻辑器件还包括：在所述第二方向并列设置的第一部件和第二部件，所述第一部件具有位于第一布线层的第一电源引出线，所述第二部件具有位于所述第一布线层的第二电源引出线，所述第一电源引出线和所述第二电源引出线均沿所述第二方向延伸；
    所述第一主体线、所述第一本地线、所述第二主体线和所述第二本地线位于第二布线层，所述第二布线层位于所述第一布线层上；
    其中，所述第一本地线通过第一互连孔与所述第一电源引出线电连接，所述第二主体线通过第二互连孔与所述第二电源引出线电连接；或者，所述第一主体线通过第三互连孔与所述第一电源引出线电连接，所述第二本地线通过第四互连孔与所述第二电源引出线电连接。
  6. 根据权利要求5所述的半导体结构，其中，所述开关驱动器件还包括：
    第一阱区，包括沿所述第一方向并列排布的第一源极区、第一沟道和第一漏极区；
    第一栅极，位于所述第一沟道上且沿所述第二方向延伸；
    第一源极线，位于所述第一布线层，所述第一源极线、所述第一源极区和所述第一输入线电连接，所述第一源极线沿所述第二方向延伸；
    第一漏极线，位于所述第一布线层，所述第一漏极线、所述第一漏极区和所述第一输出线电连接，所述第一漏极线沿所述第二方向延伸。
  7. 根据权利要求6所述的半导体结构，其中，所述第一阱区包括多个所述第一源极区和多个所述第一漏极区，所述第一源极区和所述第一漏极区沿所述第一方向交替排布，相邻所述第一源极区和所述第一漏极区之间设置有所述第一沟道，每一所述第一沟道上设置有所述第一栅极；
    所述第一栅极的数量为多个，多个所述第一栅极沿所述第一方向并列排布且相连接。
  8. 根据权利要求6所述的半导体结构，其中，所述开关驱动器件还包括：
    第二阱区，与所述第一阱区沿所述第二方向并列排布，所述第二阱区包括沿所述第一方向并列排布的第二源极区、第二沟道和第二漏极区；
    第二栅极，位于所述第二沟道上且沿所述第二方向延伸；
    第二源极线，位于所述第一布线层，所述第二源极线、所述第二源极区和所述第二输入线电连接，所述第二源极线沿所述第二方向延伸；
    第二漏极线，位于所述第一布线层，所述第二漏极线、所述第二漏极区和所述第二输出线电连接，所述第二漏极线沿所述第二方向延伸。
  9. 根据权利要求8所述的半导体结构，其中，所述第二阱区包括多个所述第二源极区和多个所述第二漏极区，所述第二源极区和所述第二漏极区沿所述第一方向交替排布，相邻所述第二源极区和所述第二漏极区之间设置有所述第二沟道，每一所述第二沟道上设置有所述第二栅极；
    所述第二栅极的数量为多个，多个所述第二栅极沿所述第一方向并列排布且相连接。
  10. 根据权利要求9所述的半导体结构，其中，所述开关驱动器件还包括：
    第一栅极连接线，与所述第一栅极位于同一布线层，所述第一栅极连接线沿所述第一方向延伸，且连接多个所述第一栅极相对靠近所述第二栅极的端部；
    第二栅极连接线，与所述第二栅极位于同一布线层，所述第二栅极连接线沿所述第一方向延伸，且连接多个所述第二栅极相对靠近所述第一栅极的端部；
    第一辅助连接线，位于所述第一布线层，所述第一辅助连接线包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一部分与所述第一栅极连接线电连接；
    第二辅助连接线，位于所述第一布线层，所述第二辅助连接线包括沿所述第一方向延伸的第三部分和沿所述第二方向延伸的第四部分，所述第三部分与所述第二栅极连接线电连接；在垂直于所述第一方向的平面内，所述第二部分的正投影和所述第四部分的正投影至少部分重叠；
    栅极控制线，沿所述第一方向延伸，且与所述第二部分和所述第四部分电连接。
  11. 根据权利要求5所述的半导体结构，其中，所述半导体结构包括多个标准单元，所述标准单元包括所述逻辑器件和所述开关驱动器件，多个所述标准单元呈阵列排布；
    其中，所述标准单元的所述第一输入线、第一输出线、第二输入线和第二输出线分别与沿所述第一方向上相邻的所述标准单元的第一主体线、第一本地线、第二主体线和第二本地线连接；
    所述半导体结构还包括：电源连接线，位于第三布线层，所述第三布线层位于所述第二布线层上，所述电源连接线沿所述第二方向延伸，且与沿所述第二方向并列排布的多个所述标准单元的所述第一本地线或所述第一输出线连接。
  12. 根据权利要求1所述的半导体结构，其中，所述逻辑器件包括反相器、逻辑门电路、缓冲器或锁存器中的至少一种。
  13. 一种存储器，包括如权利要求1至12任一项所述的半导体结构。
  14. 一种版图结构，包括：
    逻辑器件版图，包括位于同一版图布线层的第一电源线图形和第二电源线图形，所述第一电源线图形和所述第二电源线图形均沿第一方向延伸，且沿第二方向并列排布，所述第一方向和所述第二方向相交，所述逻辑器件版图用于定义逻辑器件，所述第一电源线图形用于定义第一电源线，所述第二电源线图形用于定义第二电源线；
    开关驱动器件版图，与所述逻辑器件版图沿所述第一方向并列排布，所述开关驱动器件版图包括第一输入线图形和第一输出线图形，所述第一输入线图形和所述第一输出线图形与所述第一电源线图形位于同一版图布线层，所述第一输入线图形和所述第一输出线图形均沿所述第 一方向延伸，且沿所述第二方向并列排布，其中，所述第一输出线图形沿所述第一方向延伸，且与所述第一电源线图形或者所述第二电源线图形连接；所述开关驱动器件版图用于定义开关驱动器件，所述第一输入线图形用于定义第一输入线，所述第一输出线图形用于定义第一输出线。
  15. 根据权利要求14所述的版图结构，其中，所述版图结构包括标准单元版图，所述标准单元版图包括所述逻辑器件版图和所述开关驱动器件版图，所述标准单元版图用于定义所述标准单元。
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