WO2024041186A1 - 半导体结构及其制备方法、电子设备 - Google Patents

半导体结构及其制备方法、电子设备 Download PDF

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Publication number
WO2024041186A1
WO2024041186A1 PCT/CN2023/103521 CN2023103521W WO2024041186A1 WO 2024041186 A1 WO2024041186 A1 WO 2024041186A1 CN 2023103521 W CN2023103521 W CN 2023103521W WO 2024041186 A1 WO2024041186 A1 WO 2024041186A1
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Prior art keywords
fins
fin
layer
substrate
patterns
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PCT/CN2023/103521
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English (en)
French (fr)
Inventor
张峰溢
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华为技术有限公司
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Publication of WO2024041186A1 publication Critical patent/WO2024041186A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and its preparation method, and electronic equipment.
  • fin field effect transistors have a three-dimensional channel structure, so they have better on-current and off-current characteristics, and can improve the short channel effect, making fin field effect transistors an important factor in semiconductor technology. Applications in the field are more extensive.
  • the structures of different regions are different.
  • the number of fins formed in different regions is also different.
  • the critical dimension (CD) of the fin is consistent in different areas (such as sparse areas and dense areas), where the critical dimension of the fin is also the width of the fin.
  • the spacer pattern is unevenly distributed, when the spacer pattern is used to etch the substrate to form fins, it is easy to cause the line width loading effect (Fin ISO/dense CD loading) in the fin dense area, making the fins in the sparse area and the dense area critical.
  • the dimensions i.e. width are different.
  • Embodiments of the present application provide a semiconductor structure, a preparation method thereof, and electronic equipment to improve the problem of uneven fin distribution and different widths of different fins.
  • a method for preparing a semiconductor structure includes: forming a plurality of first fins on a first surface of a substrate; the plurality of first fins protrudes side by side on the first surface. . Part of the first fins is etched to form blank areas between the remaining first fins. A protective layer is formed on the surface of the remaining first fins. Etching an area of the substrate not covered by the remaining first fins to form a second fin under the remaining first fins; each of the first fins and a second fin located below it to form a fin.
  • the substrate is first etched to form a plurality of first fins, the plurality of first fins protrude side by side on the first surface of the substrate, and then a portion of the first fin is etched. fins, forming a blank area.
  • the multiple first fins formed by etching are not prone to the line width loading effect of sparse and dense areas, and the widths of the multiple first fins can be the same.
  • the width of the first fins is related to the electrical performance of the electronic device. Therefore, when the widths of multiple first fins are the same, the performance of the electronic device can be higher, which is beneficial to improving the performance of the circuit module where the electronic device is located, and improving Properties of Semiconductor Structures.
  • the preparation method provided by the embodiments of the present application compared with the method of directly etching the substrate to form multiple uniformly distributed fins, and then etching the multiple fins to remove the portions of the multiple fins located in the blank area, the preparation method provided by the embodiments of the present application , since the height of the first fin formed by etching is small and the width of the first fin is better controllable during the preparation process, the spacing between the multiple first fins formed is larger, and the etching The process window can be larger when part of the first fin is used, and the etching process is easier to implement.
  • the preparation method provided by the embodiments of the present application is also more suitable for the preparation of semiconductor structures that require smaller fin widths and smaller fin spacing requirements.
  • forming a plurality of first fins on the first surface of the substrate includes: forming a first mask layer on the first surface of the substrate; A plurality of first spacing patterns are formed on a side away from the substrate.
  • the plurality of first spacing patterns extend along a first direction and are spaced apart along a second direction; both the first direction and the second direction are Parallel to the second surface of the substrate, and the first direction intersects the second direction; the second surface of the substrate is opposite to the first surface; based on the plurality of first Space the pattern and etch the first mask layer and the substrate to form a plurality of mask patterns and the plurality of first fins.
  • the first spacer pattern is evenly arranged on the first mask layer, so that the first spacer pattern is used to etch the liner
  • the first spacer pattern is directly used to etch the first mask layer and the substrate, and the preparation process is simple, which is conducive to simplifying the preparation process of the semiconductor structure and reducing the preparation time of the semiconductor structure. cost.
  • forming a plurality of first fins on the first surface of the substrate includes: forming a first mask layer on the first surface of the substrate.
  • a plurality of first spacing patterns are formed on a side of the first mask layer away from the substrate, the plurality of first spacing patterns extend along the first direction and are spaced apart along the second direction; the first The direction and the second direction are both parallel to the second surface of the substrate, and the first direction intersects the second direction; the second surface of the substrate is opposite to the first surface.
  • the first mask layer is etched using an atomic layer etching process to form a plurality of mask patterns; based on the plurality of mask patterns, the substrate is etched to form the plurality of first fins.
  • an atomic layer etching process is used to etch the first mask layer, so that the widths (dimensions in the second direction) of the multiple mask patterns are consistent, and the morphology of the mask patterns is better, thereby It is further advantageous to make the widths of the plurality of first fins consistent when etching the substrate based on multiple mask patterns to form the plurality of first fins, so that the morphology of the plurality of first fins is better. In this way, the morphology of the plurality of first fins may be better, and the area of the substrate that is not covered by the remaining plurality of first fins may be subsequently etched, and the second plurality of first fins may be formed under the remaining plurality of first fins. Fins provide convenience.
  • forming a plurality of first spacing patterns on a side of the first mask layer away from the substrate includes: forming a plurality of first spacer patterns on a side of the first mask layer away from the substrate. Forming a first mandrel layer and a second mandrel layer, the first mandrel layer being close to the substrate relative to the second mandrel layer; patterning the second mandrel layer to form a plurality of second mandrel layers mandrel pattern; forming a second spacer layer, the second spacer layer covering the plurality of second mandrel patterns; etching the second spacer layer to form a plurality of second spacer patterns, the second spacer pattern Covering the side of the second mandrel pattern; removing the plurality of second mandrel patterns; patterning the first mandrel layer based on the plurality of second spacing patterns to form a plurality of first mandrel patterns ; Form a first spacer layer, the first spacer layer covers the plurality of first
  • etching part of the first fins to form blank areas between the remaining first fins includes: forming a second mask layer, the second mask layer being located on the A side of the plurality of first fins away from the second surface, and the second mask layer has openings corresponding to the blank areas. Based on the second mask layer, a portion of the first fins is etched to form blank areas between the remaining first fins.
  • the preparation method before forming the second mask layer, further includes: forming a third mask layer, at least part of the third mask layer being sunk between the plurality of first fins. between; forming a fourth mask layer on the side of the third mask layer away from the substrate.
  • the preparation method further includes: etching part of the first fins.
  • the substrate underneath forms an initial groove.
  • forming a protective layer on the surface of the remaining first fins includes: using a steam in-situ generation process to form a protective layer on the sides of the remaining first fins, the lining The surface of the bottom that is not covered by the remaining first fins forms a protective layer; the protective layer is etched to remove the remaining plurality of first fins located on the substrate in the protective layer that are not covered by the remaining first fins. The portion of a surface covered by a fin.
  • the steam in-situ generation process is used to form protection on the sides of the remaining first fins and the surface of the substrate that is not covered by the remaining first fins.
  • layer including: measuring the width of the first fin; when the width of the first fin is equal to the set width, performing the steam in-situ generation process under reference process conditions to make the protective layer
  • the thickness is the set thickness; when the width of the first fin is greater than the set width, the steam in-situ generation process is performed under the first process condition, so that the thickness of the protective layer is greater than The set thickness; when the width of the first fin is less than the set width, the steam in-situ generation process is performed under the second process condition so that the thickness of the protective layer is less than the set width.
  • the set thickness wherein the reference process conditions, the first process conditions and the second process conditions are different.
  • a steam in-situ generation process is used to oxidize the sides of the remaining first fins and the parts of the substrate that are not covered by the remaining first fins.
  • a protective layer is formed on the surface of the protective layer.
  • the width of the first fin is measured, and according to the The value of the width is used to adjust the thickness of the formed protective layer, so that the width of the first fin can be further adjusted during the formation of the protective layer and the appearance of the first fin can be improved.
  • the preparation method further includes: forming a dielectric layer, at least part of the dielectric layer being sunken between a plurality of the fins; etching the dielectric layer and the protective layer to expose the For the first fin, the remaining dielectric layer forms a shallow trench isolation layer.
  • a semiconductor structure in a second aspect, includes a blank area and a plurality of device areas, the blank area is located on at least one side of the device area; the semiconductor structure includes: a substrate and a plurality of fins, The substrate includes a groove, the groove is located in a blank area; a plurality of fins protrude side by side on the first surface of the substrate; the plurality of fins are located in the device area, and in the arrangement of the plurality of fins direction, there is a spacing between the plurality of fins and the groove; the fins include a connected first fin part and a second fin part, and the first fin part is located away from the second fin part.
  • One side of the base; the first fin portions of the plurality of fins have the same width.
  • the width of one end of the first fin close to the second fin is smaller than the width of one end of the second fin close to the first fin. width.
  • the side of the fin includes the side of the first fin, the side of the second fin, and a transition surface connecting the side of the first fin and the side of the second fin;
  • the transition surface forms an obtuse angle with the side surface of the first fin part and the side surface of the second fin part.
  • the spacing between the first fin portions of the plurality of fins is equal.
  • the semiconductor structure further includes a shallow trench isolation layer filled between two adjacent fins; the first fin protrudes from the shallow trench isolation. layer.
  • an electronic device in a third aspect, includes the semiconductor structure and the printed circuit board as described in any of the above embodiments; the semiconductor structure and the printed circuit board are electrically connected.
  • Figure 1A is a schematic flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present application
  • Figures 1B to 1D are diagrams of the preparation state of the semiconductor structure corresponding to the preparation method shown in Figure 1A;
  • Figure 2 is a schematic flow chart of another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3A is a schematic top view of a semiconductor structure provided by an embodiment of the present application.
  • Figure 3B is a schematic cross-sectional view of the semiconductor structure shown in Figure 3A at D-D';
  • FIG. 4A is a schematic top view of another semiconductor structure provided by an embodiment of the present application.
  • Figure 4B is a schematic cross-sectional view of the semiconductor structure shown in Figure 4A at E-E';
  • Figure 5 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • Figure 7 is a schematic flowchart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figures 8 to 10 are preparation state diagrams of the semiconductor structure corresponding to the preparation method shown in Figure 7;
  • Figure 11 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 12 is a preparation state diagram of the semiconductor structure corresponding to the preparation method shown in Figure 11;
  • Figure 13 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figures 14 to 22 are preparation state diagrams of the semiconductor structure corresponding to the preparation method shown in Figure 13;
  • Figure 23 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 24 is a preparation state diagram of the semiconductor structure corresponding to the preparation method shown in Figure 23;
  • Figure 25 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 26 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 27 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 28 is a preparation state diagram of the semiconductor structure corresponding to the preparation method shown in Figure 27;
  • Figure 29 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 30 is a schematic flow chart of yet another method for preparing a semiconductor structure provided by an embodiment of the present application.
  • Figure 31 is a preparation state diagram of the semiconductor structure corresponding to the preparation method shown in Figure 30;
  • Figure 32 is a schematic structural diagram of yet another semiconductor structure provided by an embodiment of the present application.
  • Figure 33 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present application.
  • Figure 34 is a schematic structural diagram of a fin provided by an embodiment of the present application.
  • Figure 35 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • A/B can mean A or B; "and/or” in this application "It is just an association relationship that describes related objects. It means that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A , B can be singular or plural.
  • plural means two or more than two.
  • At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .
  • words such as “first” and “second” are used to distinguish the same or similar items with basically the same functions and effects. Those skilled in the art can understand that words such as “first” and “second” do not limit the number and execution order, and words such as “first” and “second” do not limit the number and execution order.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner that is easier to understand.
  • Embodiments of the present application provide a semiconductor structure.
  • the semiconductor structure includes a blank area and a plurality of device areas, and the blank area is located on at least one side of the device area.
  • the semiconductor structure includes a substrate and a plurality of fins disposed on the substrate, and the plurality of fins are distributed in the device area.
  • the device area is used to set circuit modules, and one circuit module is located in a device area.
  • a circuit module is a circuit that can have any function, such as drive circuit, pixel circuit, amplification circuit, power management circuit, charging protection circuit, control circuit and image sensor circuit, etc. Multiple circuit modules in a semiconductor structure can be used to implement the same function or can be used to implement different functions. The embodiments of the present application do not limit this. Fins are used to prepare electronic devices such as transistors to implement the above-mentioned circuit modules.
  • the structure and position of the blank area can be designed according to the arrangement position and number of device areas.
  • the semiconductor structure may include a blank region between the two device regions.
  • the semiconductor structure may include three or more device areas, and the semiconductor structure may include a blank area, and the blank area may include a plurality of branches, and a trunk connecting each branch, and each branch may connect two adjacent ones in the first direction.
  • the backbone can separate multiple device areas adjacent to each other in the second direction. The first direction intersects the second direction.
  • the semiconductor structure may include multiple blank areas, and the multiple blank areas are not connected.
  • an embodiment of the present application provides a method for preparing a semiconductor structure 100.
  • the preparation method includes:
  • a plurality of spacer patterns 20' are formed on the substrate 10'.
  • the plurality of spacing patterns 20' extend along the first direction X and are arranged at intervals along the second direction Y.
  • the distance d1 between any two adjacent spacing patterns 31' is the same.
  • the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are both parallel to the substrate 10'.
  • a self-aligned quadruple patterning (SAQP) process can be used to form a plurality of spacer patterns 20' on the substrate 10'.
  • SAQP self-aligned quadruple patterning
  • a mask layer may be formed on a side of the plurality of spacer patterns 20' away from the substrate 10', and the plurality of spacer patterns 20' are etched based on the mask layer. After the etching of the plurality of spacer patterns 20' is completed, the mask layer is removed.
  • a dry etching process may be used to etch the plurality of spacer patterns 20'.
  • the substrate 10' is etched to form a plurality of fins 11'.
  • a plurality of fins 11' are distributed in the device area DD, while no fins 11' are formed in the blank area CC.
  • a hard mask layer 30' may be formed on the substrate 10'.
  • the hard mask layer 30' serves as a mask when etching the substrate 10'.
  • the film protects the substrate 10' below it, so that the etching depth of the substrate 10' can be larger.
  • the spacer pattern 20' is first etched to form a spacer pattern 20' with uneven distribution density, and then the spacer pattern with uneven distribution density is used.
  • the method 20' of etching the substrate 10' has a sufficient process window, but since the patterned spacer patterns 20' are unevenly distributed in different areas of the substrate 10', it is easy to form the fins 11' during etching.
  • the line width loading effect of the sparse and dense areas occurs, resulting in different widths of the fins 11' in different areas (that is, the size of the fins 11' in the second direction Y).
  • the width of the fins 11' in the area where the density of the fins 11' is smaller is d2
  • the width of the fins 11' in the area where the fins 11' are distributed more densely (the dense area BB)
  • the width of is d3, d2 is greater than d3.
  • the value of d2 may exceed the value of d3 by 1 nm to 1.5 nm.
  • some embodiments of the present application provide a method for preparing a semiconductor structure 200 .
  • the semiconductor structure 200 includes a blank region CC and a device region DD.
  • the preparation method includes:
  • a plurality of first fins 101 are formed on the first surface 11 of the substrate 10.
  • a plurality of first fins 101 protrude side by side from the first surface 11 .
  • substrate 10 may include a semiconductor material.
  • a semiconductor material may be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI).
  • substrate 10 may be a wafer, such as a silicon wafer.
  • a plurality of first fins 101 protrudes side by side from the first surface 11 .
  • the plurality of first fins 101 may extend along the first direction X and be spaced apart along the second direction Y. on the first surface 11 of the substrate 10 .
  • the substrate 10 may further include a second surface 12 opposite to the first surface 11.
  • the first direction X and the second direction Y are both parallel to the second surface 12 of the substrate 10 and cross each other.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • the substrate 10 may be etched through a dry etching process to form a plurality of first fins 101 on the first surface 11 of the substrate 10 .
  • first fins 101 there is no limit on the number of first fins 101 as long as it can meet the functional and structural requirements of the semiconductor structure 200 .
  • the size h1 of the first fin 101 in the third direction Z there is no limit on the size h1 of the first fin 101 in the third direction Z.
  • the size h1 of the first fin part 101 in the third direction Z may be 470 nm to 530 nm.
  • the size h1 of the first fin part 101 in the third direction Z may be 470 nm or 480 nm. , 490 nanometer, 500 nanometer, 510 nanometer, 520 nanometer, 530 nanometer, etc.
  • a portion of the first fin portion 101 is etched to form a blank area CC between the remaining first fin portions 101.
  • the remaining first fins 101 may form a plurality of device regions DD.
  • a dry etching process may be used to etch part of the first fin 101 .
  • the etched portion of the first fin 101 should be completely removed in the third direction Z perpendicular to the substrate 10, so that there is no third fin in the blank area CC.
  • etching part of the first fins 101 may mean etching one or more of the plurality of first fins 101.
  • the end part of the first fin part 101 may be etched, or the middle part of the first fin part 101 may be etched. , the entire first fin 101 may also be etched.
  • 4A and 4B take etching the middle portions of three adjacent first fins 101 as an example for illustration.
  • the distance L1 between the first fins 101 is equal and small, and the first fins 101 are densely distributed.
  • the first fins 101 on both sides of the blank area CC are There are large gaps in the blank area CC and the distribution is sparse.
  • the plurality of first fins 101 are unevenly distributed on the first surface 11 of the substrate 10 .
  • a protective layer 20 is formed on the surfaces of the remaining first fins 101 .
  • the protective layer 20 may be formed on the sides of the remaining first fins 101 .
  • the material of protective layer 20 may include silicon dioxide.
  • the area of the substrate 10 not covered by the remaining first fins 101 is etched, and second fins 102 are formed below the remaining first fins 101.
  • Each first fin 101 and the second fin 102 below it form a fin 110 .
  • the area of the etched substrate 10 not covered by the remaining plurality of first fins 101 is not only the area of the etched substrate 10 located between two adjacent first fins 101
  • the portion of the substrate 10 located in the blank area CC is also etched.
  • a dry etching process may be used to etch areas of the substrate 10 that are not covered by the remaining plurality of first fins 101 .
  • the etching process will not damage the first fins. 101, thereby helping to ensure the consistency of the widths of the plurality of first fins 101. It can be understood that during the process of etching the substrate 10 , the surface of the protective layer 20 away from the first fin 101 will also be damaged, so that the thickness of the protective layer 20 is reduced.
  • the size h2 of the second fin 102 in the third direction Z perpendicular to the second surface 12 there is no limitation on the size h2 of the second fin 102 in the third direction Z perpendicular to the second surface 12 .
  • the size h2 of the second fin 102 in the third direction Z may be larger than the size h1 of the first fin 101 in the third direction Z.
  • the substrate 10 when forming the plurality of second fins 102, the substrate 10 is not completely etched in the third direction Z, and the remaining portion of the substrate 10 forms the base 103, and the plurality of second fins 102 The bottom is connected to the base 103. That is to say, the second fin portion 102 protrudes from the base 103 , and a first fin portion 101 also protrudes from each second fin portion 102 .
  • the fins 110 formed through the above steps are distributed in the device area DD and are used to prepare electronic devices such as transistors. Multiple electronic devices are used to construct circuit modules in the device area DD to realize the functions of the device area DD.
  • the second fin part 102 in the fin 110 is used to support the first fin part 101, and the correlation between the width of the second fin part 102 and the electrical performance of the electronic device is small. Therefore, even in an environment where the remaining first fins 101 are unevenly distributed, when the second fins 102 are formed by etching the areas of the substrate 10 that are not covered by the remaining first fins 101 , there are many problems.
  • the sparse area line width loading effect occurs in each of the second fins 102, resulting in different widths of the second fins 102 in different areas, which has little impact on the performance of the semiconductor structure.
  • the substrate 10 is first etched to form a plurality of first fins 101, and the plurality of first fins 101 protrude side by side on the first surface 11 of the substrate 10. Part of the first fin 101 is then etched to form a blank area CC.
  • the multiple first fin portions 101 formed by etching are not prone to sparse and dense area line width loading effects, and the widths of the multiple first fin portions 101 can be the same.
  • the width of the first fins 101 is related to the electrical performance of the electronic device. Therefore, when the widths of multiple first fins 101 are the same, the performance of the electronic device can be higher, which is beneficial to improving the performance of the circuit module where the electronic device is located. , improving the performance of the semiconductor structure 200.
  • the preparation method provided by the embodiments of the present application compared with the method of directly etching the substrate to form multiple uniformly distributed fins, and then etching the multiple fins to remove the portions of the multiple fins located in the blank area, the preparation method provided by the embodiments of the present application , since the height of the first fins formed by etching is small and the width of the first fins is better controllable during the preparation process, the spacing between the plurality of first fins 101 formed is larger, and the etching The process window when etching part of the first fin 101 can be larger, and the etching process is easier to implement.
  • the preparation method provided by the embodiments of the present application is also more suitable for the preparation of semiconductor structures that require smaller fin widths and smaller fin spacing requirements.
  • step S100 forming a plurality of first fins 101 on the first surface 11 of the substrate 10 , includes:
  • a first mask layer 30 is formed on the first surface 11 of the substrate 10.
  • the first mask layer 30 may be a single-layer structure. In other examples, the first mask layer 30 may be a multi-layer structure. When the first mask layer 30 has a multi-layer structure, as shown in FIG. 8 , the first mask layer 30 may include a stacked first mask sub-layer 301 , a second mask sub-layer 302 and a third mask layer. Sublayer 303. The first mask sub-layer 301 is further away from the substrate 10 than the third mask sub-layer 303 .
  • the first mask sub-layer 301 and the third mask sub-layer 303 may be made of the same material.
  • the materials of the first mask sub-layer 301 and the third mask sub-layer 303 may include oxide, such as silicon oxide.
  • the material of the second mask sub-layer 302 may include silicon nitride.
  • a deposition method may be used to form the first mask layer 30 on the first surface 11.
  • a chemical vapor deposition method (chemical vapor deposition, CVD) may be used to form the first mask layer 30.
  • a plurality of first spacer patterns 40 are formed on the side of the first mask layer 30 away from the substrate 10.
  • the plurality of first spacer patterns 40 extend along the first direction X and extend along the second direction. Y interval setting.
  • the number of the first isolation patterns 40 is the same as the number of the first fins 101 .
  • steps S121 to S129 the specific steps of forming the first spacer pattern 40 will not be described.
  • steps S121 to S129 please refer to steps S121 to S129 below.
  • the first mask layer 30 and the substrate 10 are etched to form a plurality of mask patterns 31 and a plurality of first fins 101.
  • a dry etching process may be used to etch the first mask layer 30 and the substrate 10 .
  • the plurality of spacer patterns 40 may be removed.
  • the mask pattern 31 when the first mask layer 30 has a multi-layer structure, the mask pattern 31 also has a multi-layer structure.
  • the mask pattern 31 includes a stacked first mask sub-layer 301 and a second mask sub-layer. 302 and the third mask sub-layer 303.
  • the mask pattern 31 can protect the top surface of the first fin portion 101 and prevent the top surface of the first fin portion 101 from being etched when etching the area of the substrate 10 that is not covered by the remaining plurality of first fin portions 101 .
  • the first spacer pattern 40 is evenly disposed on the first mask layer 30, so that when the first spacer pattern 40 is used to etch the substrate 10 and the first mask layer 30, sparse and dense areas are less likely to occur.
  • the line width loading effect enables the widths of the plurality of first fins 101 to be consistent.
  • the first spacer pattern 40 is directly used to etch the first mask layer 30 and the substrate 10. The preparation process is simple, which is conducive to simplifying the preparation process of the semiconductor structure 200 and reducing the cost. Fabrication Cost of Semiconductor Structure 200 .
  • step S100 forming a plurality of first fins 101 on the first surface of the substrate, includes:
  • the first mask layer 30 is formed on the first surface 11.
  • the first mask layer 30 may be formed on the first surface 11 by a deposition method.
  • a plurality of first spacer patterns 40 are formed on the side of the first mask layer 30 away from the substrate 10.
  • the plurality of first spacer patterns 40 extend along the first direction X and extend along the second direction. Y interval setting.
  • steps S121 to S129 the specific steps of forming the first spacer pattern 40 will not be described here.
  • steps S121 to S129 please refer to steps S121 to S129 below.
  • an atomic layer etching process (atomic layer etch, ALE) is used to etch the first mask layer 30 to form a plurality of mask patterns 31.
  • the mask pattern 31 when the first mask layer 30 has a multi-layer structure, the mask pattern 31 also has a multi-layer structure.
  • the mask pattern 31 includes a stacked first mask sub-layer 301 and a second mask sub-layer. 302 and the third mask sub-layer 303.
  • the third mask sub-layers 303 of the plurality of mask patterns 31 may be connected to each other. That is, the portion of the third mask sub-layer 303 of the first mask layer 30 corresponding to the area between the plurality of first spacer patterns 40 has not been completely etched. In this way, when the first mask layer is etched based on the plurality of first spacer patterns 40 to form the plurality of mask patterns 31, the substrate 10 is damaged after the third mask sub-layer 303 is completely etched. It appears that it is beneficial to control the size of the first fin 101 in the third direction Z perpendicular to the second surface 12 .
  • the substrate 10 is etched to form a plurality of first fins 101.
  • the first spacer pattern 40 may be removed before etching the substrate 10 based on the plurality of mask patterns 31, the first spacer pattern 40 may be removed.
  • the plurality of mask patterns 31 are separated from each other.
  • the first mask layer 30 is etched using an atomic layer etching process, so that the widths W2 (dimensions in the second direction Y) of the multiple mask patterns 31 are consistent, and the shape of the mask patterns 31 is The appearance is better, which further facilitates making the width W1 of the plurality of first fins 101 consistent when etching the substrate 10 based on the plurality of mask patterns 31 to form a plurality of first fins 101, so that The appearance of the plurality of first fins 101 is better.
  • the morphology of the plurality of first fins 101 can be better also be the area of the substrate 10 that is not covered by the remaining plurality of first fins 101 during subsequent etching. It is convenient to form the second fin 102 below.
  • the process of forming a plurality of first fins 101 on the first surface 11 of the substrate 10 is briefly described. The following is a description of the process of forming a plurality of first fins 101 on the first surface 11 of the substrate 10 with reference to FIGS. 13 to 22 . The specific process of forming a plurality of first spacing patterns 40 on one side will be described.
  • step S120 forming a plurality of first spacer patterns 40 on the side of the first mask layer 30 away from the substrate 10 , includes:
  • the first mandrel layer 51 and the second mandrel layer 52 are formed on the side of the first mask layer 30 away from the substrate 10.
  • the first mandrel layer 51 is opposite to the second mandrel layer. 52 is close to the substrate 10.
  • first mandrel layer 51 and second mandrel layer 52 may be the same.
  • the materials of the first and second core layers 51 and 52 may include silicon.
  • the process of forming the first mandrel layer 51 and the second mandrel layer on the side of the first mask layer 30 away from the substrate 10 may be an atomic layer deposition (ALD) process or chemical vapor deposition. process or physical vapor deposition process, etc.
  • ALD atomic layer deposition
  • chemical vapor deposition process or physical vapor deposition process, etc.
  • the barrier layer 501 may be formed on a side of the first mandrel layer 51 away from the substrate 10 .
  • the barrier layer 501 is used to prevent the first mandrel layer 51 from being damaged when the second mandrel layer 52 is etched.
  • the barrier layer 501 can also serve as a mask for etching the first mandrel layer 51 .
  • the barrier layer 501 is a multi-layer structure, and the barrier layer 501 includes a first sub-barrier layer 5011 and a second sub-barrier layer 5012.
  • the first sub-blocking layer 5011 is closer to the substrate 10 than the second sub-blocking layer 5012 .
  • the materials of the first sub-barrier layer 5011 and the second sub-barrier layer 5012 are different.
  • the material of the first sub-blocking layer 5011 may include silicon nitride
  • the material of the second sub-blocking layer 5012 may include silicon oxide.
  • the second mandrel layer 52 is patterned to form a plurality of second mandrel patterns 521.
  • the second mandrel layer 52 may be patterned through a wet etching process or a dry etching process.
  • the spin-coated carbon layer 502 may be formed on the side of the second mandrel layer 52 away from the substrate 10
  • the anti-reflective layer 503 may be formed on the side of the spin-coated carbon layer 502 away from the substrate 10
  • a photoresist pattern 504 is formed on the side of the anti-reflective layer 503 away from the substrate 10
  • the second mandrel layer 52 is patterned based on the spin-coated carbon layer 502 , the anti-reflective layer 503 and the photoresist pattern 504 .
  • the material of the anti-reflective layer 503 may include a silicon-containing anti-reflective layer.
  • the photoresist patterns 504 extend along the first direction X and are spaced apart along the second direction Y.
  • the anti-reflective layer 503 is used to reduce the reflection effect when exposing the photoresist pattern, improve the transfer accuracy of the pattern, and thereby improve the topography quality and dimensional accuracy of the second mandrel pattern 521.
  • a second spacer layer 53 is formed, and the second spacer layer 53 covers the plurality of second mandrel patterns 521.
  • the second spacer layer 53 may be an oxide layer.
  • the material of the second spacer layer 53 may include silicon dioxide.
  • the second spacer layer 53 may be formed through an atomic layer deposition process.
  • the second spacer layer 53 is etched to form a plurality of second spacer patterns 531, and the second spacer patterns 531 cover the side surfaces of the second mandrel pattern 521.
  • the second spacing pattern 531 covers the side surfaces of the second mandrel pattern 521 , that is, the second spacing pattern 531 covers one of the two opposite side surfaces of the second mandrel pattern 521 in the second direction Y.
  • the second spacer layer 53 may be etched through a wet etching process or a dry etching process.
  • the second spacing pattern 531 may extend along the first direction X and be spaced apart along the second direction Y.
  • the second mandrel patterns 521 may be etched through a wet etching process or a dry etching process, thereby removing the plurality of second mandrel patterns 521 .
  • the first mandrel layer 51 is patterned based on the plurality of second spacing patterns 531 to form a plurality of first mandrel patterns 511.
  • a portion of the first sub-barrier layer 5011 may remain on the side of the first mandrel pattern 511 away from the substrate 10 .
  • the first sub-barrier layer 5011 on the side of the first mandrel pattern 511 away from the substrate 10 may be removed.
  • a first spacer layer 54 is formed, and the first spacer layer 54 covers a plurality of first mandrel patterns 511.
  • the first spacer layer 54 may be an oxide layer.
  • the material of the first spacer layer 54 may include silicon dioxide.
  • the first spacer layer 54 may be formed through an atomic layer deposition process.
  • the first spacer layer 54 is etched to form a plurality of first spacer patterns 40.
  • the first spacer patterns 40 cover the side surfaces of the first mandrel pattern 511.
  • the first spacer layer 54 may be etched through a wet etching process or a dry etching process.
  • the first spacer pattern 40 covers the side surfaces of the first mandrel pattern 511", that is, the first spacer pattern 40 covers one of the two opposite sides of the first mandrel pattern 511 in the second direction Y.
  • the first mandrel patterns 511 may be etched through a wet etching process or a dry etching process, thereby removing the plurality of first mandrel patterns 511 .
  • step S100 the specific process steps of step S100 are described.
  • step S200 the specific process steps of step S200 will be described below with reference to FIGS. 23 to 25 .
  • step 200 is to etch part of the first fins 101 to form a blank area CC between the remaining first fins 101, including:
  • a second mask layer 61 is formed.
  • the second mask layer 61 is located on the side of the plurality of first fins 101 away from the second surface 12.
  • the second mask layer 61 has a corresponding blank area CC.
  • the material of the second mask layer 61 may include photoresist.
  • a coating process can be used to form the second mask layer 61 .
  • the second mask layer 61 includes a plurality of openings 611.
  • the number of openings 611 is the same as the number of blank areas CC.
  • the boundary of the orthographic projection of the opening 611 on the second surface 12 should be located in the gap between the orthographic projections of the plurality of first fins 101 on the second surface 12 to avoid After the blank area CC is formed, the size of the first fins 101 on both sides of the blank area CC is reduced in the second direction Y.
  • the preparation method further includes:
  • a third mask layer 62 is formed, and at least part of the third mask layer 62 is sunk between the plurality of first fins 101.
  • “at least part of the third mask layer 62 is embedded between the plurality of first fins 101", which may mean that the entire third mask layer 62 is embedded between the plurality of first fins 101.
  • the third mask layer 62 The surface away from the substrate 10 is flush with the surface of the first fin 101 away from the substrate.
  • “at least part of the third mask layer 62 is sunk between the plurality of first fins 101 ”, or a part of the third mask layer 62 is sunk between the plurality of first fins 101 .
  • the other part is located on the side of the first fin 101 away from the substrate 10 .
  • the etching depth can be made larger, and the etching parameters (such as etching rate, etching time, etc.) can be adjusted at any time during the etching process to obtain a flatter cutting point.
  • the etching parameters such as etching rate, etching time, etc.
  • the third mask layer 62 may be formed through a spin coating process.
  • the third mask layer 62 may be a carbon-containing mask layer.
  • a fourth mask layer 63 is formed on the side of the third mask layer 62 away from the substrate 10.
  • the material of the fourth mask layer 63 is different from the material of the third mask layer 62 , and the material of the fourth mask layer 63 is also different from the material of the second mask layer 61 .
  • the fourth mask layer 63 may be a silicon-containing anti-reflective layer.
  • the fourth mask layer 63 is an anti-reflective layer
  • the fourth mask layer 63 is used to reduce the reflection effect when forming the second mask layer 61 , improve the transfer accuracy of the pattern, and thereby improve the plurality of first fins 101 Topography quality and dimensional accuracy after etching.
  • step S200 a portion of the first fin 101 is etched, and the remaining portion is etched.
  • the preparation method also includes:
  • the substrate 10 under the part of the first fin 101 is etched to form an initial groove 104.
  • the height h3 of the initial groove 104 may be 50 angstroms to 100 angstroms.
  • the height h3 of the initial groove 104 may be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, etc.
  • the remaining plurality of first fins 101 are etched. While forming the second fin 102 below the first fin 101 , the surface of the substrate 10 located in the blank area CC can also be etched to form a groove 105 , and the groove 105 is located on the substrate 103 .
  • FIG. 27 is a specific process flow chart of step S300
  • FIG. 28 is a state diagram of the semiconductor structure corresponding to step S310 in the process flow chart provided in FIG. 27. Step S300 will be further described below with reference to Figures 27 and 28, as well as Figure 5.
  • step S300 forming a protective layer 20 on the surfaces of the remaining first fins 101 includes:
  • S310 use a steam in-situ generation process to form a protective layer 20 on the sides of the remaining first fins 101 and on the surface of the substrate 10 that is not covered by the remaining first fins 101 .
  • the protective layer 20 is etched to remove the portion of the protective layer 20 located on the surface of the substrate 10 that is not covered by the remaining plurality of first fins 101.
  • step S310 a steam in-situ generation process is used on the sides of the remaining first fins 101 and the portions of the substrate 10 that are not covered by the remaining first fins 101 .
  • a protective layer 20 is formed on the surface, including:
  • the width W1 is the size of the first fin part 101 along the second direction Y.
  • the width W1 of the first fin portion 101 is also a critical dimension of the first fin portion 101 .
  • the reference process conditions, the first process conditions and the second process conditions are different.
  • the reference process condition, the first process condition, and the second process condition may include at least one of temperature, time, and the like.
  • the reference process condition, the first process condition and the second process condition are all time conditions, and the time of the reference process condition, the first process condition and the second process condition are different.
  • a steam in-situ generation process is used to oxidize the remaining side surfaces of the first fins 101 and the remaining first fins of the substrate 10
  • the surface covered by the fin portion 101 forms a protective layer 20.
  • the width W1 of the first fin portion 101 after the protective layer 20 is formed is correspondingly smaller.
  • the width W1 of the first fin portion 101 after the protective layer 20 is formed is correspondingly larger.
  • the width W1 of the first fin portion 101 is measured, and the thickness L2 of the formed protective layer 20 is adjusted according to the value of the width W1 of the first fin portion 101, so that the protective layer 20 can be formed during the process.
  • the width W1 of the first fin part 101 is further adjusted to improve the appearance of the first fin part 101.
  • the preparation method also includes:
  • a dielectric layer 70 is formed, and at least part of the dielectric layer 70 is embedded between the plurality of fins 110.
  • the material of the dielectric layer 70 is an insulating material.
  • the material of the dielectric layer 70 may include binary or multi-component compounds composed of silicon (Si), carbon (C), nitrogen (N), oxygen (O) and other elements.
  • the material of the dielectric layer 70 may include, for example, silicon oxynitride (SiC x O y N z ), silicon oxycarbide (SiC x O y ), silicon nitride (SiN x ), silicon oxide (SiO x ), or At least one kind of silicon oxynitride (SiO x N y ). It can be understood that the material of the dielectric layer 70 may also contain one or more elements such as hydrogen (H), fluorine (F), chlorine (Cl), and the like.
  • a deposition method may be used to form the dielectric layer 70.
  • a chemical vapor deposition process may be used to form the dielectric layer.
  • a dry etching process may be used to etch the dielectric layer 70 and the protective layer 20 .
  • the dielectric layer 70 may be planarized.
  • a chemical mechanical polishing process may be used to polish the dielectric layer 70 .
  • the size of the mask pattern 31 in the third direction Z perpendicular to the second surface 12 is reduced, that is, the mask pattern 31 is reduced in size. The 31 part is removed.
  • the first mask layer 30 has a multi-layer structure
  • the first mask sub-layer 301 and the second mask sub-layer 302 of the mask pattern 31 are removed, and the mask pattern The third mask sub-layer 303 of 31 is retained.
  • the remaining portion of the mask pattern 31 can also be removed.
  • the semiconductor structure 200 includes a blank area CC and a plurality of device areas DD.
  • the blank area CC is located on at least one side of the device area DD.
  • Semiconductor structure 200 includes a substrate 103 and a plurality of fins 110 .
  • the substrate 103 includes a groove 105, and the groove 105 is located in the blank area CC.
  • the plurality of fins 110 protrude side by side from the first surface 11 of the base 103 .
  • the plurality of fins 110 are located in the device region DD, and in the arrangement direction of the plurality of fins 110 , there is a gap between the plurality of fins 110 and the groove 105 .
  • the fin 110 includes a connected first fin part 101 and a second fin part 102 .
  • the first fin part 101 is located on a side of the second fin part 102 away from the base 103 .
  • the width W1 of the first fin portions 101 of the plurality of fins 110 is the same.
  • the plurality of fins 110 protrude side by side on the first surface 11 of the base 103
  • the plurality of fins 110 extend along the first direction X and are spaced apart from the base along the second direction Y. 103 on.
  • the base 103 also includes a second surface 12 opposite to the first surface 11.
  • the first direction X and the second direction Y are both parallel to the second surface 12 of the base 103 and cross each other.
  • the first direction X and the second direction Y may be perpendicular to each other.
  • the width W1 of the first fin part 101 is the size of the first fin part 101 in the second direction Y.
  • the arrangement direction of the plurality of fins 110 is also the second direction Y.
  • the width W1 of the first fin 101 is not limited, as long as it can meet the structural requirements and functional requirements of the semiconductor structure 200 .
  • the size h1 of the first fin 101 in the third direction Z perpendicular to the base 103, as long as it can meet the functional requirements and structural requirements of the semiconductor structure 200.
  • the size h1 of the first fin part 101 in the third direction Z may be 470 nm to 530 nm.
  • the size h1 of the first fin part 101 in the third direction Z may be 470 nm or 480 nm. , 490 nanometer, 500 nanometer, 510 nanometer, 520 nanometer, 530 nanometer, etc.
  • the size h1 of the first fin 101 in the third direction Z perpendicular to the base 103 may be smaller than the size of the second fin 102 in the third direction Z perpendicular to the base 103 .
  • the number of fins 110 in the semiconductor structure 200 is not limited, as long as the structural requirements and functional requirements of the semiconductor structure 200 are met.
  • the dimension h4 of the groove 105 in the third direction Z perpendicular to the substrate 103 may be 50 angstroms to 100 angstroms.
  • the dimension h4 of the groove 105 in the third direction Z perpendicular to the substrate 103 may be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, etc.
  • the distance L3 is smaller than the distance between two adjacent fins 110. Pitch.
  • the semiconductor structure 200 provided in the above embodiment of the present application includes a blank area CC and a plurality of device areas DD.
  • a plurality of fins 110 are distributed in the device area DD. There are no fins 110 in the blank area CC.
  • the plurality of fins 110 are disposed on the substrate 103
  • the width W1 of the first fin portions 101 of the plurality of fins 110 is the same, and there is no line width load effect in the sparse and dense areas, which can make the performance of electronic devices such as transistors prepared by the first fin portions 101 better.
  • the performance of the semiconductor structure 200 is improved.
  • step S400 the area of the substrate 10 that is not covered by the remaining first fins 101 is etched to form a layer under the remaining first fins 101.
  • a protective layer 20 is formed on the surfaces of the remaining first fins 101. Therefore, in some embodiments, as shown in FIG. 34 , in the same fin 110 , the width W1 of one end of the first fin 101 close to the second fin 102 is smaller than the width W1 of the second fin 102 close to the first fin 101 The width of one end is W3.
  • the sides of the fin 110 include the side Q1 of the first fin 101 , the second fin 102 The side Q2 of the first fin 101 and the transition surface Q3 connecting the side Q1 of the first fin 101 and the side Q2 of the second fin 102 .
  • the transition surface Q3 forms an obtuse angle with the side surface Q1 of the first fin part 101 and the side surface Q2 of the second fin part 102 .
  • the spacing L1 between the first fin portions 101 of the plurality of fins 110 is equal.
  • the semiconductor structure 200 further includes a shallow trench isolation layer 701 filled between two adjacent fins 110 .
  • the first fin portion 101 protrudes from the shallow trench isolation layer 701 .
  • the material of the shallow trench isolation layer 701 may be an insulating material.
  • the material of the shallow trench isolation layer 701 may include binary or multi-component compounds composed of silicon (Si), carbon (C), nitrogen (N), oxygen (O) and other elements.
  • the material of the shallow trench isolation layer 701 may include, for example, silicon carbon oxynitride (SiC x O y N z ), silicon carbon oxide (SiC x O y ), silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ). It can be understood that the material of the shallow trench isolation layer 701 may also contain one or more of hydrogen (H), fluorine (F), chlorine (Cl) and other elements.
  • the electronic device 1000 includes the semiconductor structure 200 described in any of the above embodiments and a printed circuit board (PCB) 300.
  • the semiconductor structure 200 and the printed circuit board 300 are electrically connected to achieve signal intercommunication.
  • the electronic device 1000 is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product.
  • consumer electronic products include mobile phones, tablets, laptops, e-readers, personal computers (PC), personal digital assistants (PDA), desktop monitors, Smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc.
  • Home electronic products include smart door locks, TVs, remote controls, refrigerators, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc.
  • Vehicle-mounted electronic products include car navigation systems, car DVDs, etc.
  • Financial terminal products include ATM machines, self-service terminals, etc. The embodiment of the present application does not place any special restrictions on the specific form of the electronic device 1000 mentioned above.
  • the semiconductor structure 200 After the semiconductor structure 200 is packaged, it can be applied in the electronic device 1000 in the form of a chip. Of course, it can also be directly applied to the electronic device 1000 without encapsulation.

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Abstract

本申请提供一种半导体结构及其制备方法、电子设备，涉及半导体技术领域，用于改善鳍分布不均时，不同鳍的宽度存在差异的问题。半导体结构的制备方法包括：在衬底的第一表面形成多个第一鳍部；多个第一鳍部并排突出于第一表面上。刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区。在剩余的多个第一鳍部的表面形成保护层。刻蚀衬底的未被剩余的多个第一鳍部覆盖的区域，在剩余的多个第一鳍部的下方形成第二鳍部。每个第一鳍部和位于其下方的第二鳍部形成鳍。上述半导体结构应用于电子设备中，以提高电子设备的性能。

Description

半导体结构及其制备方法、电子设备
本申请要求于2022年08月22日提交国家知识产权局、申请号为202211008645.0、发明名称为“半导体结构及其制备方法、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法、电子设备。
背景技术
随着半导体工艺技术的不断发展，传统的平面式晶体管逐渐不能满足人们对高性能器件的需求。相比于平面式晶体管，鳍式场效应晶体管具有立体式沟道结构，故而具有更好的导通电流和关断电流特性，能够改善短沟道效应，从而使得鳍式场效应晶体管在半导体技术领域中的应用更加广泛。
在半导体结构中，由于所要实现的功能不同，不同区域的结构不相同，在制备半导体结构的过程中，不同区域形成的鳍的数目也就不同。理想的，在不同区域(例如稀疏区域和密集区域)中，鳍的关键尺寸(Critical Dimension，CD)一致，其中鳍的关键尺寸也即鳍的宽度。然而，随着线宽微缩，为了具有足够的制程窗口(process window)，在鳍的制备过程中需要先在衬底上形成具有不同分布密度的间隔图案，再基于该间隔图案刻蚀衬底形成在不同区域具有不同分布密度的鳍。由于间隔图案分布不均，因此利用该间隔图案刻蚀衬底形成鳍时，容易造成鳍疏密区线宽负载效应(Fin ISO/dense CD loading)，使得稀疏区域和密集区域中的鳍的关键尺寸(即宽度)不同。
发明内容
本申请实施例提供一种半导体结构及其制备方法、电子设备，用于改善鳍分布不均时，不同鳍的宽度不同的问题。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种半导体结构的制备方法，该方法包括：在衬底的第一表面形成多个第一鳍部；所述多个第一鳍部并排突出于所述第一表面上。刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区。在所述剩余的多个第一鳍部的表面形成保护层。刻蚀所述衬底的未被所述剩余的多个第一鳍部覆盖的区域，在所述剩余的多个第一鳍部的下方形成第二鳍部；每个所述第一鳍部和位于其下方的第二鳍部形成鳍。
本申请上述实施例所提供的半导体结构的制备方法中，先刻蚀衬底形成多个第一鳍部，多个第一鳍部并排突出于衬底的第一表面上，再刻蚀部分第一鳍部，形成空白区。这样，刻蚀形成的多个第一鳍部不容易出现疏密区线宽负载效应，多个第一鳍部的宽度可以相同。第一鳍部的宽度与电子器件的电学性能相关，因此当多个第一鳍部的宽度相同时，可以使电子器件的性能较高，从而有利于提高电子器件所在的电路模块的性能，提高半导体结构的性能。
同时，与直接刻蚀衬底形成均匀分布的多个鳍，再对多个鳍进行刻蚀，去除多个鳍位于空白区内的部分的方法相比，本申请实施例所提供的制备方法中，由于刻蚀形成的第一鳍部的高度较小，第一鳍部的宽度在制备过程中的可控性较好，因此形成的多个第一鳍部之间的间距较大，刻蚀部分第一鳍部时的制程窗口可以较大，刻蚀过程更加容易实现。本申请实施例所提供的制备方法，也更加适用于鳍宽度需求更小、鳍间距需求更小的半导体结构的制备。
在一些实施例中，所述在衬底的第一表面形成多个第一鳍部，包括：在所述衬底的第一表面上形成第一掩膜层；在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，所述多个第一间隔图案沿第一方向延伸，且沿第二方向间隔设置；所述第一方向和所述第二方向均平行于所述衬底的第二表面，且所述第一方向与所述第二方向相交叉；所述衬底的第二表面与所述第一表面相对设置；基于所述多个第一间隔图案，刻蚀所述第一掩膜层和所述衬底，形成多个掩膜图案及所述多个第一鳍部。
本申请实施例中，第一间隔图案均匀设置在第一掩膜层上，从而在利用第一间隔图案刻蚀衬 底和第一掩膜层时，不容易出现疏密区线宽负载效应，使得多个第一鳍部的宽度可以一致。同时，本申请上述实施例所提供的制备方法中，直接利用第一间隔图案刻蚀第一掩膜层和衬底，制备工艺简单，从而有利于简化半导体结构的制备工艺，降低半导体结构的制备成本。
在一些实施例中，所述在衬底的第一表面形成多个第一鳍部，包括：在所述衬底的第一表面上形成第一掩膜层。在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，所述多个第一间隔图案沿第一方向延伸，且沿第二方向间隔设置；所述第一方向和所述第二方向均平行于所述衬底的第二表面，且所述第一方向与所述第二方向相交叉；所述衬底的第二表面与所述第一表面相对设置。基于所述多个第一间隔图案，采用原子层刻蚀工艺刻蚀所述第一掩膜层，形成多个掩膜图案；基于所述多个掩膜图案，刻蚀所述衬底，形成所述多个第一鳍部。
本申请上述实施例中，利用原子层刻蚀工艺刻蚀第一掩膜层，使得多个掩膜图案的宽度(在第二方向上的尺寸)一致，掩膜图案的形貌较好，从而进一步有利于在基于多个掩膜图案刻蚀衬底形成多个第一鳍部时，使多个第一鳍部的宽度一致，使得多个第一鳍部的形貌更好。这样，多个第一鳍部的形貌更好还可以为后续刻蚀衬底的未被剩余的多个第一鳍部覆盖的区域，在剩余的多个第一鳍部的下方形成第二鳍部提供便利。
在一些实施例中，所述在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，包括：在所述第一掩膜层远离所述衬底的一侧形成第一芯轴层和第二芯轴层，所述第一芯轴层相对于所述第二芯轴层靠近所述衬底；图案化所述第二芯轴层，形成多个第二芯轴图案；形成第二间隔层，所述第二间隔层覆盖所述多个第二芯轴图案；刻蚀所述第二间隔层，形成多个第二间隔图案，所述第二间隔图案覆盖所述第二芯轴图案的侧面；去除所述多个第二芯轴图案；基于所述多个第二间隔图案，图案化所述第一芯轴层，形成多个第一芯轴图案；形成第一间隔层，所述第一间隔层覆盖所述多个第一芯轴图案；刻蚀所述第一间隔层，形成所述多个第一间隔图案，所述第一间隔图案覆盖所述第一芯轴图案的侧面；去除所述多个第一芯轴图案。
在一些实施例中，所述刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区，包括：形成第二掩膜层，所述第二掩膜层位于所述多个第一鳍部远离所述第二表面的一侧，所述第二掩膜层具有对应所述空白区的开口。基于所述第二掩膜层，刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区。
在一些实施例中，所述形成第二掩膜层之前，所述制备方法还包括：形成第三掩膜层，所述第三掩膜层的至少部分陷入所述多个第一鳍部之间；在所述第三掩膜层远离所述衬底的一侧形成第四掩膜层。
在一些实施例中，在所述刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区的过程中，所述制备方法还包括：刻蚀所述部分第一鳍部下方的衬底，形成初始凹槽。
在一些实施例中，所述在所述剩余的多个第一鳍部的表面形成保护层，包括：采用蒸汽原位生成工艺在所述剩余的多个第一鳍部的侧面、所述衬底的未被所述剩余的多个第一鳍部覆盖的表面形成保护层；刻蚀所述保护层，以去除所述保护层中位于所述衬底的未被所述剩余的多个第一鳍部覆盖的表面上的部分。
在一些实施例中，所述采用蒸汽原位生成工艺在所述剩余的多个第一鳍部的侧面、所述衬底的未被所述剩余的多个第一鳍部覆盖的表面形成保护层，包括：测量所述第一鳍部的宽度；在所述第一鳍部的宽度等于设定宽度的情况下，在参考工艺条件下进行所述蒸汽原位生成工艺，使所述保护层的厚度为设定厚度；在所述第一鳍部的宽度大于所述设定宽度的情况下，在第一工艺条件下进行所述蒸汽原位生成工艺，以使所述保护层的厚度大于所述设定厚度；在所述第一鳍部的宽度小于所述设定宽度的情况下，在第二工艺条件下进行所述蒸汽原位生成工艺，以使所述保护层的厚度小于所述设定厚度；其中，所述参考工艺条件、所述第一工艺条件和所述第二工艺条件各不相同。
本申请上述实施例中所提供的半导体结构的制备方法中，采用蒸汽原位生成工艺，通过氧化剩余的多个第一鳍部的侧面、衬底的未被剩余的多个第一鳍部覆盖的表面形成保护层，当保护层的厚度较大时，形成保护层后的第一鳍部的宽度相应较小，当保护层的厚度较小时，形成保护层后的第一鳍部的宽度相应较大。这样，在形成保护层前，测量第一鳍部的宽度，根据第一鳍部的 宽度的数值，调整形成的保护层的厚度，从而可以在形成保护层的过程中进一步调整第一鳍部的宽度，改善第一鳍部的形貌。
在一些实施例中，所示制备方法还包括：形成介质层，所述介质层的至少部分陷入多个所述鳍之间；刻蚀所述介质层和所述保护层，以暴露出所述第一鳍部，剩余的介质层形成浅沟槽隔离层。
第二方面，提供了一种半导体结构，所述半导体结构包括空白区和多个器件区，所述空白区位于所述器件区的至少一侧；所述半导体结构包括：基底和多个鳍，所述基底包括凹槽，所述凹槽位于空白区；多个鳍并排突出于所述基底的第一表面上；所述多个鳍位于所述器件区，且在所述多个鳍的排列方向上，所述多个鳍与所述凹槽之间存在间距；所述鳍包括相连接的第一鳍部和第二鳍部，所述第一鳍部位于所述第二鳍部远离所述基底的一侧；所述多个鳍的第一鳍部的宽度相同。
在一些实施例中，在同一所述鳍中，所述第一鳍部的靠近所述第二鳍部的一端的宽度，小于所述第二鳍部的靠近所述第一鳍部的一端的宽度。
在一些实施例中，所述鳍的侧面包括所述第一鳍部的侧面、所述第二鳍部的侧面，以及连接第一鳍部的侧面和第二鳍部的侧面的过渡面；所述过渡面与所述第一鳍部的侧面、第二鳍部的侧面之间均呈钝角。
在一些实施例中，在同一所述器件区内，所述多个鳍的第一鳍部之间的间距相等。
在一些实施例中，所述半导体结构还包括浅沟槽隔离层，浅沟槽隔离层填充于相邻两个所述鳍之间；所述第一鳍部凸出于所述浅沟槽隔离层。
第三方面，提供了一种电子设备，该电子设备包括如上述任一实施例所述的半导体结构和印刷电路板；所述半导体结构和所述印刷电路板电连接。
其中，第二方面至第三方面中任一种设计方式所带来的技术效果可参见第一方面中不同设计方式所带来的技术效果，此处不再赘述。
附图说明
图1A为本申请实施例提供的一种半导体结构的制备方法的流程示意图；
图1B～图1D为图1A所示的制备方法对应的半导体结构的制备状态图；
图2为本申请实施例提供的另一种半导体结构的制备方法的流程示意图；
图3A为本申请实施例提供的一种半导体结构的俯视示意图；
图3B为图3A所示的半导体结构在D-D’处的截面示意图；
图4A为本申请实施例提供的另一种半导体结构的俯视示意图；
图4B为图4A所示的半导体结构在E-E’处的截面示意图；
图5为本申请实施例提供的一种半导体结构的结构示意图；
图6为本申请实施例提供的另一种半导体结构的结构示意图；
图7为本申请实施例提供的再一种半导体结构的制备方法的流程示意图；
图8～图10为图7所示的制备方法对应的半导体结构的制备状态图；
图11为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图12为图11所示的制备方法对应的半导体结构的制备状态图；
图13为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图14～图22为图13所示的制备方法对应的半导体结构的制备状态图；
图23为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图24为图23所示的制备方法对应的半导体结构的制备状态图；
图25为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图26为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图27为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图28为图27所示的制备方法对应的半导体结构的制备状态图；
图29为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图30为本申请实施例提供的又一种半导体结构的制备方法的流程示意图；
图31为图30所示的制备方法对应的半导体结构的制备状态图；
图32为本申请实施例提供的再一种半导体结构的结构示意图；
图33为本申请实施例提供的又一种半导体结构的结构示意图；
图34为本申请实施例提供的一种鳍的结构示意图；
图35为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。其中，在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或”的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。
在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
同时，在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，便于理解。
本申请实施例提供一种半导体结构，半导体结构包括空白区和多个器件区，空白区位于器件区的至少一侧。半导体结构中包括基底和设置于基底上的多个鳍，多个鳍分布于器件区中。
器件区用于设置电路模块，一个电路模块位于一个器件区内。电路模块是可以具有任意功能的电路，例如，驱动电路、像素电路、放大电路、电源管理电路、充电保护电路、控制电路和图像传感器电路等。半导体结构中的多个电路模块可以是用于实现同一功能，也可以用于实现不同功能。本申请实施例对此不做限定。鳍用于制备晶体管等电子器件，实现上述电路模块。
空白区中不设置电路模块，用于间隔多个器件区，避免多个器件区中的电路模块在工作状态下互相干扰。因此，在空白区中不设置鳍。可以理解的是，为了较好的间隔开多个器件区，在多个鳍的排布方向上，空白区的尺寸大于器件区中任意两个鳍之间的间距，且大于鳍的宽度。
本申请实施例中对器件区的数目和布置位置也不做限制，只要能够满足半导体结构的功能需求即可。
空白区的结构和位置可以随着器件区的布置位置和数量进行设计。例如，当半导体结构包括平排设置的两个器件区时，半导体结构可以包括位于两个器件区之间的一个空白区。当半导体结构包括三个及以上的器件区时，半导体结构可以包括一个空白区，该空白区可以包括多个分支，以及连接各个分支的主干，各个分支可以将在第一方向上相邻的两个器件区分隔开来，主干可以将在第二方向上相邻的多个器件区分隔开来。第一方向与第二方向相交叉。或者，在半导体结构包括三个及以上的器件区时，半导体结构可以包括多个空白区，多个空白区之间不连通。
基于上述结构，如图1A所示，本申请实施例提供了一种半导体结构100的制备方法，该制备方法包括：
S1、如图1B所示，在衬底10’上形成多个间隔图案20’。多个间隔图案20’沿第一方向X延伸，且沿第二方向Y间隔排布。沿第二方向Y，任意相邻的两个间隔图案31’之间的间距d1相同。其中，第一方向X与第二方向Y相交叉，且第一方向X与第二方向Y均平行于衬底10’。
示例性的，可以利用自对准四重图案化(self aligned quadruple patterning，SAQP)工艺在衬底10’上形成多个间隔图案20’。
S2、如图1C所示，刻蚀多个间隔图案20’，以去除多个间隔图案20’中对应空白区CC的部 分。
示例性的，可以在多个间隔图案20’远离衬底10’的一侧形成掩膜层，基于掩膜层刻蚀多个间隔图案20’。在多个间隔图案20’刻蚀完成之后，再将掩膜层去除。
示例性的，可以采用干法刻蚀工艺刻蚀多个间隔图案20’。
S3、如图1D所示，基于剩余的多个间隔图案20’，刻蚀衬底10’，形成多个鳍11’。多个鳍11’分布在器件区DD中，而空白区CC中未形成有鳍11’。
示例性的，在衬底10’上形成多个间隔图案20’之前，可以在衬底10’上形成硬掩膜层30’，硬掩膜层30’在刻蚀衬底10’时作为掩膜保护其下方的衬底10’，从而可以使衬底10’的刻蚀深度较大。
本申请发明人经研究发现，虽然在上述实施例所提供的半导体结构的制备方法中，先刻蚀间隔图案20’，形成分布密度不均匀的间隔图案20’，再利用分布密度不均匀的间隔图案20’刻蚀衬底10’的方式具有足够的制程窗口，但由于图案化后的间隔图案20’在衬底10’的不同区域上的分布不均匀，因此容易在刻蚀形成鳍11’时出现疏密区线宽负载效应，导致不同区域中的鳍11’的宽度(也即，鳍11’在第二方向Y上的尺寸)不同。如图1D所示，在鳍11’密度较小的区域(稀疏区域AA)中的鳍11’的宽度为d2，在鳍11’分布密度较大的区域(密集区域BB)中的鳍11’的宽度为d3，d2大于d3。示例性的，d2的取值可以超出d3的取值1纳米～1.5纳米。
基于上述问题，如图2～图6所示，本申请的一些实施例中提供了一种半导体结构200的制备方法，该半导体结构200包括空白区CC和器件区DD。该制备方法包括：
S100、如图3A和图3B所示，在衬底10的第一表面11形成多个第一鳍部101。多个第一鳍部101并排突出于第一表面11上。
在一些示例中，衬底10可以包括半导体材料。例如，可以为体硅、体锗、硅锗、碳化硅、绝缘体上硅(silicon-on-insulator，SOI)、绝缘体上锗硅(SiGe-on-insulator，SGOI)中的一种。
在一些示例中，衬底10可以为晶圆，例如，硅晶圆。
如图3A和图3B所示，多个第一鳍部101并排突出于第一表面11上，可以是，多个第一鳍部101沿第一方向X延伸，沿第二方向Y间隔设置在衬底10的第一表面11上。
衬底10还可以包括与第一表面11相对的第二表面12，上述第一方向X与第二方向Y均平行于衬底10的第二表面12，且相互交叉。例如，第一方向X可以与第二方向Y相互垂直。
示例性的，可以通过干法刻蚀工艺刻蚀衬底10，在衬底10的第一表面11形成多个第一鳍部101。
本申请实施例中对第一鳍部101的数目不做限制，只要能够满足半导体结构200的功能和结构需求即可。
本申请实施例中对第一鳍部101在第三方向Z上的尺寸h1也不做限制。在一些示例中，第一鳍部101在第三方向Z上的尺寸h1可以为470纳米～530纳米，例如，第一鳍部101在第三方向Z上的尺寸h1可以为470纳米、480纳米、490纳米、500纳米、510纳米、520纳米、530纳米等。
S200、如图4A和图4B所示，刻蚀部分第一鳍部101，在剩余的多个第一鳍部101之间形成空白区CC。与此同时，剩余的多个第一鳍部101可以形成多个器件区DD。
示例性的，可以采用干法刻蚀工艺刻蚀部分第一鳍部101。
可以理解的是，在刻蚀第一鳍部101时，第一鳍部101被刻蚀的部分在垂直于衬底10的第三方向Z上应被完全去除，使得空白区CC内不具有第一鳍部101。
其中，“刻蚀部分第一鳍部101”，可以是刻蚀多个第一鳍部101中的一个或多个。在刻蚀第一鳍部101时，在第一鳍部101的延伸方向(第二方向Y)上，可以刻蚀第一鳍部101的端部，也可以刻蚀第一鳍部101的中部，还可以将刻蚀整个第一鳍部101。本申请实施例中，对上述步骤S200中刻蚀的第一鳍部101的数目以及刻蚀的第一鳍部101的位置不做限制，只要满足半导体结构的结构需求即可。图4A和图4B以刻蚀相邻的3个第一鳍部101的中部为例进行示意。
对比图3A和图4A，在刻蚀多个第一鳍部101之前，第一鳍部101之间的间距L1相等且较小，第一鳍部101分布密集。在刻蚀多个第一鳍部101之后，空白区CC两侧的第一鳍部101在 空白区CC范围内产生较大间隔，分布稀疏。通过刻蚀部分第一鳍部101，使得多个第一鳍部101在衬底10的第一表面11不均匀分布。
S300、如图5所示，在剩余的多个第一鳍部101的表面形成保护层20。
示例性的，可以在剩余的多个第一鳍部101的侧面形成保护层20。
在一些示例中，保护层20的材料可以包括二氧化硅。
S400、如图6所示，刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域，在剩余的多个第一鳍部101的下方形成第二鳍部102。每个第一鳍部101和位于其下方的第二鳍部102形成鳍110。
对比图5和图6，“刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域”，不仅是刻蚀衬底10的位于相邻的两个第一鳍部101之间的区域，还要刻蚀衬底10位于空白区CC的部分。
示例性的，可以采用干法刻蚀工艺刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域。
其中，在刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域时，由于第一鳍部101的表面形成有保护层20，因此刻蚀工艺不会损伤第一鳍部101，从而有利于保证多个第一鳍部101的宽度的一致性。可以理解的是，在刻蚀衬底10的过程中，保护层20的远离第一鳍部101的表面也会被损伤，使得保护层20的厚度减薄。
本申请上述实施例中对第二鳍部102在垂直于第二表面12的第三方向Z上的尺寸h2也不做限制。示例性的，如图6所示，第二鳍部102在第三方向Z上的尺寸h2可以大于第一鳍部101在第三方向Z上的尺寸h1。
可以理解的是，在形成多个第二鳍部102时，在第三方向Z上，衬底10并未被完全刻蚀，衬底10的剩余部分形成基底103，多个第二鳍部102的底部与基底103相连接。也就是说，第二鳍部102突出于基底103上，而在每个第二鳍部102上还突出有第一鳍部101。
通过上述步骤形成的鳍110分布于器件区DD中，用于制备晶体管等电子器件，多个电子器件用于构建器件区DD内的电路模块，实现器件区DD的功能。
鳍110中的第二鳍部102用于支撑第一鳍部101，第二鳍部102的宽度与电子器件的电学性能之间的相关性较小。因此，即使在剩余的多个第一鳍部101不均匀分布的环境下，刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域，形成第二鳍部102时，多个第二鳍部102中出现疏密区线宽负载效应，造成不同区域的第二鳍部102的宽度不同，对半导体结构的性能影响也不大。
本申请上述实施例所提供的半导体结构200的制备方法中，先刻蚀衬底10形成多个第一鳍部101，多个第一鳍部101并排突出于衬底10的第一表面11上，再刻蚀部分第一鳍部101，形成空白区CC。这样，刻蚀形成的多个第一鳍部101不容易出现疏密区线宽负载效应，多个第一鳍部101的宽度可以相同。第一鳍部101的宽度与电子器件的电学性能相关，因此当多个第一鳍部101的宽度相同时，可以使电子器件的性能较高，从而有利于提高电子器件所在的电路模块的性能，提高半导体结构200的性能。
同时，与直接刻蚀衬底形成均匀分布的多个鳍，再对多个鳍进行刻蚀，去除多个鳍位于空白区内的部分的方法相比，本申请实施例所提供的制备方法中，由于刻蚀形成的第一鳍部的高度较小，第一鳍部的宽度在制备过程中的可控性较好，因此形成的多个第一鳍部101之间的间距较大，刻蚀部分第一鳍部101时的制程窗口可以较大，刻蚀过程更加容易实现。本申请实施例所提供的制备方法，也更加适用于鳍宽度需求更小、鳍间距需求更小的半导体结构的制备。
上述实施例中对半导体结构200的制备方法的各个步骤进行了简单的描述，下面将结合附图以及具体实施例对上述各个步骤做出进一步的解释和说明。
如图7所示，在一些实施例中，步骤S100、在衬底10的第一表面11形成多个第一鳍部101，包括：
S110、如图8所示，在衬底10的第一表面11上形成第一掩膜层30。
在一些示例中，第一掩膜层30可以为单层结构。在另一些示例中，第一掩膜层30可以为多层结构。当第一掩膜层30为多层结构时，如图8所示，第一掩膜层30可以包括层叠设置的第一掩膜子层301，第二掩膜子层302和第三掩膜子层303。其中，第一掩膜子层301相比于第三掩膜子层303更远离衬底10。
示例性的，第一掩膜子层301和第三掩膜子层303的材料可以相同。示例性的，第一掩膜子层301和第三掩膜子层303的材料可以包括氧化物，例如氧化硅。
示例性的，第二掩膜子层302的材料可以包括氮化硅。
示例性的，可以采用沉积法在第一表面11上形成第一掩膜层30，例如，可以利用化学气相沉积法(chemical vapor deposition，CVD)形成第一掩膜层30。
S120、如图9所示，在第一掩膜层30远离衬底10的一侧形成多个第一间隔图案40，多个第一间隔图案40沿第一方向X延伸，且沿第二方向Y间隔设置。
可以理解的是，第一隔离图案40的数目与第一鳍部101的数目相同。
此处，对形成第一间隔图案40的具体步骤不做描述，具体步骤可以参见后文步骤S121～步骤S129。
S130、参阅图10，基于多个第一间隔图案40，刻蚀第一掩膜层30和衬底10，形成多个掩膜图案31及多个第一鳍部101。
示例性的，可以是利用干法刻蚀工艺刻蚀第一掩膜层30和衬底10。
如图10所示，在形成多个掩膜图案31和多个第一鳍部101之后，可以去除多个间隔图案40。
可以理解的是，当第一掩膜层30为多层结构时，掩膜图案31同样为多层结构，掩膜图案31包括层叠设置的第一掩膜子层301，第二掩膜子层302和第三掩膜子层303。
掩膜图案31可以在刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域时，保护第一鳍部101的顶面，避免第一鳍部101的顶面被刻蚀。
本申请实施例中，第一间隔图案40均匀设置在第一掩膜层30上，从而在利用第一间隔图案40刻蚀衬底10和第一掩膜层30时，不容易出现疏密区线宽负载效应，使得多个第一鳍部101的宽度可以一致。同时，本申请上述实施例所提供的制备方法中，直接利用第一间隔图案40刻蚀第一掩膜层30和衬底10，制备工艺简单，从而有利于简化半导体结构200的制备工艺，降低半导体结构200的制备成本。
在另一些实施例中，如图11所示，步骤S100、在衬底的第一表面形成多个第一鳍部101，包括：
S110、如图8所示，在第一表面11上形成第一掩膜层30。
与上述实施例相同，可以利用可以采用沉积法在第一表面11上形成第一掩膜层30。
S120、如图9所示，在第一掩膜层30远离衬底10的一侧形成多个第一间隔图案40，多个第一间隔图案40沿第一方向X延伸，且沿第二方向Y间隔设置。
同样的，此处不再对形成第一间隔图案40的具体步骤进行描述，具体步骤可以参见后文步骤S121～步骤S129。
S140、如图12所示，基于多个第一间隔图案40，采用原子层刻蚀工艺(atomic layer etch，ALE)刻蚀第一掩膜层30，形成多个掩膜图案31。
可以理解的是，当第一掩膜层30为多层结构时，掩膜图案31同样为多层结构，掩膜图案31包括层叠设置的第一掩膜子层301，第二掩膜子层302和第三掩膜子层303。
在一些示例中，如图12所示，多个掩膜图案31的第三掩膜子层303之间可以相互连接。也即，第一掩膜层30的第三掩膜子层303中对应多个第一间隔图案40之间区域的部分未被完全刻蚀。这样，可以避免在基于多个第一间隔图案40刻蚀第一掩膜层，形成多个掩膜图案31时，第三掩膜子层303被完全刻蚀后，衬底10被损伤的情况出现，有利于控制第一鳍部101在垂直于第二表面12的第三方向Z上的尺寸。
S150、参阅图10，基于多个掩膜图案31，刻蚀衬底10，形成多个第一鳍部101。
示例性的，在基于多个掩膜图案31刻蚀衬底10之前，可以去除第一间隔图案40。
可以理解的是，基于多个掩膜图案31，刻蚀衬底10，形成多个第一鳍部101后，多个掩膜图案31之间相互分离。
本申请上述实施例中，利用原子层刻蚀工艺刻蚀第一掩膜层30，使得多个掩膜图案31的宽度W2(在第二方向Y上的尺寸)一致，掩膜图案31的形貌较好，从而进一步有利于在基于多个掩膜图案31刻蚀衬底10形成多个第一鳍部101时，使多个第一鳍部101的宽度W1一致，使得 多个第一鳍部101的形貌更好。这样，多个第一鳍部101的形貌更好还可以为后续刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域，在剩余的多个第一鳍部101的下方形成第二鳍部102提供便利。
上述实施例中对在衬底10的第一表面11形成多个第一鳍部101的工艺过程进行了简单的描述，下面结合图13～图22对在第一掩膜层30远离衬底10的一侧形成多个第一间隔图案40的具体工艺过程进行阐述。
如图13所示，在一些实施例中，步骤S120、在第一掩膜层30远离衬底10的一侧形成多个第一间隔图案40，包括：
S121、如图14所示，在第一掩膜层30远离衬底10的一侧形成第一芯轴层51和第二芯轴层52，第一芯轴层51相对于第二芯轴层52靠近衬底10。
在一些示例中，第一芯轴层51和第二芯轴层52的材料可以相同。当第一芯轴层51和第二芯轴层52的材料相同时，第一芯轴层51和第二芯轴层52的材料可以包括硅。
示例性的，在第一掩膜层30远离衬底10的一侧形成第一芯轴层51和第二芯轴层的工艺可以为原子层沉积(atomic layer deposition，ALD)工艺、化学气相沉积工艺或者物理气相沉积工艺等。
示例性的，在形成第一芯轴层51之后，形成第二芯轴层52之前，可以在第一芯轴层51远离衬底10的一侧形成阻隔层501。阻隔层501用于避免刻蚀第二芯轴层52时，损伤第一芯轴层51。同时，阻隔层501还可以作为刻蚀第一芯轴层51的掩膜。
示例性的，阻隔层501为多层结构，阻隔层501包括第一子阻隔层5011和第二子阻隔层5012。第一子阻隔层5011相比于第二子阻隔层5012更加靠近衬底10。
第一子阻隔层5011和第二子阻隔层5012的材料不同。示例性的，第一子阻隔层5011的材料可以包括氮化硅，第二子阻隔层5012的材料可以包括氧化硅。
S122、如图15所示，图案化第二芯轴层52，形成多个第二芯轴图案521。
示例性的，可以通过湿法刻蚀工艺或者干法刻蚀工艺图案化第二芯轴层52。
在一些示例中，参阅图14，可以在第二芯轴层52远离衬底10的一侧形成旋涂碳层502，在旋涂碳层502远离衬底10的一侧形成抗反射层503，在抗反射层503远离衬底10的一侧形成光刻胶图案504，基于旋涂碳层502、抗反射层503和光刻胶图案504，图案化第二芯轴层52。其中，抗反射层503的材料可以包括含硅抗反射层。光刻胶图案504沿第一方向X延伸，沿第二方向Y间隔设置。
抗反射层503用于减小曝光光刻胶图案时的反射效应，提高图案的转移精度，进而提高第二芯轴图案521的形貌质量和尺寸精准度。
S123、如图16所示，形成第二间隔层53，第二间隔层53覆盖多个第二芯轴图案521。
示例性的，第二间隔层53可以为氧化物层。例如，第二间隔层53的材料可以包括二氧化硅。
示例性的，可以通过原子层沉积工艺形成第二间隔层53。
S124、如图17所示，刻蚀第二间隔层53，形成多个第二间隔图案531，第二间隔图案531覆盖第二芯轴图案521的侧面。
其中，第二间隔图案531覆盖第二芯轴图案521的侧面，即，第二间隔图案531覆盖第二芯轴图案521在第二方向Y上相对的两个侧面中的一个。
示例性的，可以通过湿法刻蚀工艺或者干法刻蚀工艺刻蚀第二间隔层53。
示例性的，第二间隔图案531可以沿第一方向X延伸，沿第二方向Y间隔设置。
S125、如图18所示，去除多个第二芯轴图案521。示例性的，可以通过湿法刻蚀工艺或者干法刻蚀工艺刻蚀第二芯轴图案521，从而去除多个第二芯轴图案521。
S126、如图19所示，基于多个第二间隔图案531，图案化第一芯轴层51，形成多个第一芯轴图案511。
示例性的，在形成第一芯轴图案511后，第一芯轴图案511远离衬底10的一侧可以残余有部分第一子阻隔层5011。
基于此，如图20所示，在后续形成第一间隔层54之前，可以先去除第一芯轴图案511远离衬底10的一侧的第一子阻隔层5011。
S127、如图21所示，形成第一间隔层54，第一间隔层54覆盖多个第一芯轴图案511。
示例性的，第一间隔层54可以为氧化物层。例如，第一间隔层54的材料可以包括二氧化硅。
示例性的，可以通过原子层沉积工艺形成第一间隔层54。
S128、如图22所示，刻蚀第一间隔层54，形成多个第一间隔图案40，第一间隔图案40覆盖第一芯轴图案511的侧面。
示例性的，可以通过湿法刻蚀工艺或者干法刻蚀工艺刻蚀第一间隔层54。
其中，“第一间隔图案40覆盖第一芯轴图案511的侧面”，即，第一间隔图案40覆盖第一芯轴图案511在第二方向Y上相对的两个侧面中的一个。
S129、参阅图9，去除多个第一芯轴图案511。
示例性的，可以通过湿法刻蚀工艺或者干法刻蚀工艺刻蚀第一芯轴图案511，从而去除多个第一芯轴图案511。
上述实施例中，对步骤S100的具体工艺步骤进行了说明，下面结合图23～图25对步骤S200的具体工艺步骤进行说明。
如图23所示，在一些实施例中，步骤200、刻蚀部分第一鳍部101，在剩余的多个第一鳍部101之间形成空白区CC，包括：
S210、如图24所示，形成第二掩膜层61，第二掩膜层61位于多个第一鳍部101远离第二表面12的一侧，第二掩膜层61具有对应空白区CC的开口611。
示例性的，第二掩膜层61的材料可以包括光刻胶。此时，可以利用涂布工艺形成第二掩膜层61。
当半导体结构200中需要设置多个空白区CC时，第二掩膜层61包括多个开口611。开口611的数目与空白区CC的数目相同。
可以理解的是，在第二方向Y上，开口611在第二表面12上正投影的边界应位于多个第一鳍部101在第二表面12上的正投影之间的间隙中，从而避免形成空白区CC后，空白区CC两侧第一鳍部101在第二方向Y上的尺寸减小。
S220、如图4B所示，基于第二掩膜层61，刻蚀部分第一鳍部101，在剩余的多个第一鳍部101之间形成空白区CC。
在一些实施例中，如图25所示，在步骤S210、形成第二掩膜层61之前，制备方法还包括：
S230、参阅图24，形成第三掩膜层62，第三掩膜层62的至少部分陷入多个第一鳍部101之间。
其中，“第三掩膜层62的至少部分陷入多个第一鳍部101之间”，可以是第三掩膜层62全部陷入多个第一鳍部101之间，第三掩膜层62远离衬底10的表面与第一鳍部101远离衬底的表面平齐。或者，如图24所示，“第三掩膜层62的至少部分陷入多个第一鳍部101之间”，还可以是第三掩膜层62的一部分陷入多个第一鳍部101之间，另一部分位于第一鳍部101远离衬底10的一侧。
通过在形成第三掩膜层62，可以使得刻蚀深度较大，在刻蚀过程中可以随时调整刻蚀参数(例如刻蚀速率，刻蚀时间等)，获得较平坦的切断处。
示例性的，第三掩膜层62可以通过旋涂工艺形成。示例性的，第三掩膜层62可以为含碳掩膜层。
S240、参阅图24，在第三掩膜层62远离衬底10的一侧形成第四掩膜层63。
示例性的，第四掩膜层63的材料与第三掩膜层62的材料不同，且第四掩膜层63的材料与第二掩膜层61的材料也不相同。示例性的，第四掩膜层63可以为含硅抗反射层。
当第四掩膜层63为抗反射层时，第四掩膜层63用于减小形成第二掩膜层61时的反射效应，提高图案的转移精度，进而提高多个第一鳍部101刻蚀后的形貌质量和尺寸精准度。
为了在第三方向Z上完全去除第一鳍部101中被刻蚀的部分，在一些实施例中，如图26所示，在步骤S200、刻蚀部分第一鳍部101，在剩余的多个第一鳍部101之间形成空白区CC的过程中，制备方法还包括：
S201、参阅图4B，刻蚀所述部分第一鳍部101下方的衬底10，形成初始凹槽104。
如图4B所示，在第二方向Y(也即第一鳍部101的排布方向)上，初始凹槽104和与初始凹槽104相邻的第一鳍部101之间均存在间距。
在一些示例中，在垂直于第二表面12的第三方向Z上，初始凹槽104的高度h3可以为50埃～100埃。例如，初始凹槽104的高度h3可以为50埃、60埃、70埃、80埃、90埃、100埃等。
在一些实施例中，如图6所示，在形成有初始凹槽104的情况下，在刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域，在剩余的多个第一鳍部101的下方形成第二鳍部102的同时，还可以刻蚀衬底10位于空白区CC的表面，形成凹槽105，凹槽105位于基底103上。
在一些示例中，如图6所示，在第二方向Y(鳍110的排布方向)上，凹槽105和与凹槽105相邻的鳍110之间也均存在间距。
图27为步骤S300的具体工艺流程图，图28为图27所提供的工艺流程图中步骤S310对应的半导体结构的状态图。以下将结合图27和图28，以及图5对步骤S300进一步描述。
在一些实施例中，如图27所示，步骤S300、在剩余的多个第一鳍部101的表面形成保护层20，包括：
S310、如图28所示，采用蒸汽原位生成工艺在剩余的多个第一鳍部101的侧面、衬底10的未被剩余的多个第一鳍部101覆盖的表面形成保护层20。
S320、参阅图5，刻蚀保护层20，以去除保护层20中位于衬底10的未被剩余的多个第一鳍部101覆盖的表面上的部分。
在一些示例中，如图29所示，步骤S310、采用蒸汽原位生成工艺在剩余的多个第一鳍部101的侧面、衬底10的未被剩余的多个第一鳍部101覆盖的表面形成保护层20，包括：
S311、测量第一鳍部101的宽度W1，宽度W1为第一鳍部101的沿第二方向Y的尺寸。第一鳍部101的宽度W1也即第一鳍部101的关键尺寸。
S312、在第一鳍部101的宽度W1等于设定宽度的情况下，在参考工艺条件下进行蒸汽原位生成工艺，使保护层20的厚度L2为设定厚度。
S313、在第一鳍部101的宽度W1大于设定宽度的情况下，在第一工艺条件下进行蒸汽原位生成工艺，以使保护层20的厚度L2大于设定厚度。
S314、在第一鳍部101的宽度W1小于设定宽度的情况下，在第二工艺条件下进行蒸汽原位生成工艺，以使保护层20的厚度L2小于设定厚度。
其中，参考工艺条件、第一工艺条件和第二工艺条件各不相同。
在一些示例中，参考工艺条件、第一工艺条件和第二工艺条件可以包括温度、时间等中的至少一个。例如，参考工艺条件、第一工艺条件和第二工艺条件均为时间条件，参考工艺条件、第一工艺条件和第二工艺条件的时间不同。
本申请上述实施例中所提供的半导体结构200的制备方法中，采用蒸汽原位生成工艺，通过氧化剩余的多个第一鳍部101的侧面、衬底10的未被剩余的多个第一鳍部101覆盖的表面形成保护层20，当保护层20的厚度L2较大时，形成保护层20后的第一鳍部101的宽度W1相应较小，当保护层20的厚度L2较小时，形成保护层20后的第一鳍部101的宽度W1相应较大。
这样，在形成保护层20前，测量第一鳍部101的宽度W1，根据第一鳍部101的宽度W1的数值，调整形成的保护层20的厚度L2，从而可以在形成保护层20的过程中进一步调整第一鳍部101的宽度W1，改善第一鳍部101的形貌。
除上述实施例所提供的工艺步骤外，在一些实施例中，如图30所示，制备方法还包括：
S500、如图31所示，形成介质层70，介质层70的至少部分陷入多个鳍110之间。
其中，介质层70的材料为绝缘材料。示例的，介质层70的材料可以包括硅(Si)、碳(C)、氮(N)、氧(O)等元素组成的二元或多元化合物。具体的，介质层70的材料例如可以包括碳氧氮化硅(SiCxOyNz)、碳氧化硅(SiCxOy)、氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。可以理解的是，介质层70的材料还可能会含有氢(H)、氟(F)、氯(Cl)等元素中的一种或多种。
示例性的，可以采用沉积法形成介质层70，例如，可以利用化学气相沉积工艺形成介质层。
S600、如图32所示，刻蚀介质层70和保护层20，以暴露出第一鳍部101，剩余的介质层70 形成浅沟槽隔离层701。
示例性的，可以采用干法刻蚀工艺刻蚀介质层70和保护层20。
示例性的，在形成介质层70后，刻蚀介质层70和保护层20之前，可以对介质层70进行平坦化处理。例如，可以采用化学机械研磨工艺对介质层70进行研磨。此时，如图31和图33所示，在对介质层70进行平坦化处理后，掩膜图案31在垂直于第二表面12的第三方向Z上的尺寸减小，也即掩膜图案31的部分被去除。在第一掩膜层30为多层结构时，在对介质层70进行平坦化处理后，掩膜图案31的第一掩膜子层301和第二掩膜子层302被去除，掩膜图案31的第三掩膜子层303被保留。
这样，在刻蚀介质层70和保护层20的同时，还可以去除掩膜图案31剩余的部分。
如图32所示，本申请一些实施例提供一种半导体结构200，该半导体结构200包括空白区CC和多个器件区DD，空白区CC位于器件区DD的至少一侧。半导体结构200包括基底103和多个鳍110。
其中，基底103包括凹槽105，凹槽105位于空白区CC。所述多个鳍110并排突出于基底103的第一表面11上。多个鳍110位于器件区DD，且在多个鳍110的排列方向上，多个鳍110与凹槽105之间存在间距。鳍110包括相连接的第一鳍部101和第二鳍部102，第一鳍部101位于第二鳍部102远离基底103的一侧。多个鳍110的第一鳍部101的宽度W1相同。
如图32所示，“所述多个鳍110并排突出于基底103的第一表面11上”，即所述多个鳍110沿第一方向X延伸，且沿第二方向Y间隔设置在基底103上。
基底103还包括与第一表面11相对的第二表面12，上述第一方向X与第二方向Y均平行于基底103的第二表面12，且相互交叉。例如，第一方向X可以与第二方向Y相互垂直。
其中，第一鳍部101的宽度W1，即第一鳍部101在第二方向Y上的尺寸。多个鳍110的排布方向也即第二方向Y。
可以理解的是，本申请上述实施例中对第一鳍部101的宽度W1不做限制，只要能够满足半导体结构200的结构需求和功能需求即可。
本申请实施例中对第一鳍部101在垂直于基底103的第三方向Z上的尺寸h1也不做限制，只要能满足半导体结构200的功能需求和结构需求即可。在一些示例中，第一鳍部101在第三方向Z上的尺寸h1可以为470纳米～530纳米，例如，第一鳍部101在第三方向Z上的尺寸h1可以为470纳米、480纳米、490纳米、500纳米、510纳米、520纳米、530纳米等。
在一些示例中，第一鳍部101在垂直于基底103的第三方向Z上的尺寸h1可以小于第二鳍部102在垂直于基底103的第三方向Z上的尺寸。
本申请上述实施例中对半导体结构200中的鳍110的数目也不做限制，只要满足半导体结构200的结构需求和功能需求即可。
在一些示例中，凹槽105在垂直于基底103的第三方向Z上的尺寸h4可以为50埃～100埃。例如，凹槽105在垂直于基底103的第三方向Z上的尺寸h4可以为50埃、60埃、70埃、80埃、90埃、100埃等。
在多个鳍110的排列方向上，多个鳍110与凹槽105之间存在间距L3，基于上述实施例中所提供的半导体结构的制备方法可知，间距L3小于相邻两个鳍110之间的间距。
本申请上述实施例所提供的半导体结构200包括空白区CC和多个器件区DD，多个鳍110分布在器件区DD中，在空白区CC中不设置鳍110，多个鳍110在基底103上不均匀分布，但多个鳍110的第一鳍部101的宽度W1相同，不存在疏密区线宽负载效应，可以使由第一鳍部101制备的晶体管等电子器件的性能较好，进而提高半导体结构200的性能。
由于在上述实施例所提供的制备方法中，在步骤S400、刻蚀衬底10的未被剩余的多个第一鳍部101覆盖的区域，在剩余的多个第一鳍部101的下方形成第二鳍部102之前，在剩余的多个第一鳍部101的表面上形成了保护层20。因此在一些实施例中，如图34所示，在同一鳍110中，第一鳍部101的靠近第二鳍部102的一端的宽度W1，小于第二鳍部102的靠近第一鳍部101的一端的宽度W3。
在一些实施例中，如图34所示，鳍110的侧面包括第一鳍部101的侧面Q1、第二鳍部102 的侧面Q2，以及连接第一鳍部101的侧面Q1和第二鳍部102的侧面Q2的过渡面Q3。过渡面Q3与第一鳍部101的侧面Q1、第二鳍部102的侧面Q2之间均呈钝角。
在一些实施例中，在同一器件区DD内，多个鳍110的第一鳍部101之间的间距L1相等。
在一些实施例中，半导体结构200还包括浅沟槽隔离层701，填充于相邻两个鳍110之间。第一鳍部101凸出于浅沟槽隔离层701。
其中，浅沟槽隔离层701的材料可以绝缘材料。示例的，浅沟槽隔离层701的材料可以包括硅(Si)、碳(C)、氮(N)、氧(O)等元素组成的二元或多元化合物。具体的，浅沟槽隔离层701的材料例如可以包括碳氧氮化硅(SiCxOyNz)、碳氧化硅(SiCxOy)、氮化硅(SiNx)、氧化硅(SiOx)或氮氧化硅(SiOxNy)中的至少一种。可以理解的是，浅沟槽隔离层701的材料还可能会含有氢(H)、氟(F)、氯(Cl)等元素中的一种或多种。
如图35所示，本申请一些实施例中还提供一种电子设备1000，该电子设备1000包括上述任一项实施例所述的半导体结构200和印刷电路板(printed circuit board，PCB)300。半导体结构200和印刷电路板300电连接，以实现信号互通。
在一些实施例中，该电子设备1000例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品。其中，消费性电子产品如为手机(mobile phone)、平板电脑(pad)、笔记本电脑、电子阅读器、个人计算机(personal computer，PC)、个人数字助理(personal digital assistant，PDA)、桌面显示器、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、无人机等。家居式电子产品如为智能门锁、电视、遥控器、冰箱、充电家用小型电器(例如豆浆机、扫地机器人)等。车载式电子产品如为车载导航仪、车载DVD等。金融终端产品如为ATM机、自助办理业务的终端等。本申请实施例对上述电子设备1000的具体形式不做特殊限制。
半导体结构200封装后，即可以芯片的形态应用于电子设备1000中。当然，也可以不封装，直接应用于电子设备1000中。
本申请一些实施例所提供的电子设备1000所能够达到的技术效果与上述人任一实施例所述的半导体结构200所能够达到的技术效果相同，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种半导体结构的制备方法，其特征在于，包括：
    在衬底的第一表面形成多个第一鳍部；所述多个第一鳍部并排突出于所述第一表面上；
    刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区；
    在所述剩余的多个第一鳍部的表面形成保护层；
    刻蚀所述衬底的未被所述剩余的多个第一鳍部覆盖的区域，在所述剩余的多个第一鳍部的下方形成第二鳍部；每个所述第一鳍部和位于其下方的第二鳍部形成鳍。
  2. 根据权利要求1所述的制备方法，其特征在于，所述在衬底的第一表面形成多个第一鳍部，包括：
    在所述衬底的第一表面上形成第一掩膜层；
    在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，所述多个第一间隔图案沿第一方向延伸，且沿第二方向间隔设置；所述第一方向和所述第二方向均平行于所述衬底的第二表面，且所述第一方向与所述第二方向相交叉；所述衬底的第二表面与所述第一表面相对设置；
    基于所述多个第一间隔图案，刻蚀所述第一掩膜层和所述衬底，形成多个掩膜图案及所述多个第一鳍部。
  3. 根据权利要求1所述的制备方法，其特征在于，所述在衬底的第一表面形成多个第一鳍部，包括：
    在所述衬底的第一表面上形成第一掩膜层；
    在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，所述多个第一间隔图案沿第一方向延伸，且沿第二方向间隔设置；所述第一方向和所述第二方向均平行于所述衬底的第二表面，且所述第一方向与所述第二方向相交叉；所述衬底的第二表面与所述第一表面相对设置；
    基于所述多个第一间隔图案，采用原子层刻蚀工艺刻蚀所述第一掩膜层，形成多个掩膜图案；
    基于所述多个掩膜图案，刻蚀所述衬底，形成所述多个第一鳍部。
  4. 根据权利要求2或3所述的制备方法，其特征在于，所述在所述第一掩膜层远离所述衬底的一侧形成多个第一间隔图案，包括：
    在所述第一掩膜层远离所述衬底的一侧形成第一芯轴层和第二芯轴层，所述第一芯轴层相对于所述第二芯轴层靠近所述衬底；
    图案化所述第二芯轴层，形成多个第二芯轴图案；
    形成第二间隔层，所述第二间隔层覆盖所述多个第二芯轴图案；
    刻蚀所述第二间隔层，形成多个第二间隔图案，所述第二间隔图案覆盖所述第二芯轴图案的侧面；
    去除所述多个第二芯轴图案；
    基于所述多个第二间隔图案，图案化所述第一芯轴层，形成多个第一芯轴图案；
    形成第一间隔层，所述第一间隔层覆盖所述多个第一芯轴图案；
    刻蚀所述第一间隔层，形成所述多个第一间隔图案，所述第一间隔图案覆盖所述第一芯轴图案的侧面；
    去除所述多个第一芯轴图案。
  5. 根据权利要求1～4中任一项所述的制备方法，其特征在于，所述刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区，包括：
    形成第二掩膜层，所述第二掩膜层位于所述多个第一鳍部远离所述第二表面的一侧，所述第二掩膜层具有对应所述空白区的开口；
    基于所述第二掩膜层，刻蚀部分第一鳍部，在剩余的多个第一鳍部之间形成空白区。
  6. 根据权利要求5所述的制备方法，其特征在于，所述形成第二掩膜层之前，所述制备方法还包括：
    形成第三掩膜层，所述第三掩膜层的至少部分陷入所述多个第一鳍部之间；
    在所述第三掩膜层远离所述衬底的一侧形成第四掩膜层。
  7. 根据权利要求1～6中任一项所述的制备方法，其特征在于，在所述刻蚀部分第一鳍部，在 剩余的多个第一鳍部之间形成空白区的过程中，所述制备方法还包括：
    刻蚀所述部分第一鳍部下方的衬底，形成初始凹槽。
  8. 根据权利要求1～7中任一项所述的制备方法，其特征在于，所述在所述剩余的多个第一鳍部的表面形成保护层，包括：
    采用蒸汽原位生成工艺在所述剩余的多个第一鳍部的侧面、所述衬底的未被所述剩余的多个第一鳍部覆盖的表面形成保护层；
    刻蚀所述保护层，以去除所述保护层中位于所述衬底的未被所述剩余的多个第一鳍部覆盖的表面上的部分。
  9. 根据权利要求1～8中任一项所述的制备方法，其特征在于，所述采用蒸汽原位生成工艺在所述剩余的多个第一鳍部的侧面、所述衬底的未被所述剩余的多个第一鳍部覆盖的表面形成保护层，包括：
    测量所述第一鳍部的宽度；
    在所述第一鳍部的宽度等于设定宽度的情况下，在参考工艺条件下进行所述蒸汽原位生成工艺，使所述保护层的厚度为设定厚度；
    在所述第一鳍部的宽度大于所述设定宽度的情况下，在第一工艺条件下进行所述蒸汽原位生成工艺，以使所述保护层的厚度大于所述设定厚度；
    在所述第一鳍部的宽度小于所述设定宽度的情况下，在第二工艺条件下进行所述蒸汽原位生成工艺，以使所述保护层的厚度小于所述设定厚度；
    其中，所述参考工艺条件、所述第一工艺条件和所述第二工艺条件各不相同。
  10. 根据权利要求1～9中任一项所述的制备方法，其特征在于，还包括：
    形成介质层，所述介质层的至少部分陷入多个所述鳍之间；
    刻蚀所述介质层和所述保护层，以暴露出所述第一鳍部，剩余的介质层形成浅沟槽隔离层。
  11. 一种半导体结构，其特征在于，所述半导体结构包括空白区和多个器件区，所述空白区位于所述器件区的至少一侧；所述半导体结构包括：
    基底，包括凹槽，所述凹槽位于空白区；
    多个鳍，并排突出于所述基底的第一表面上；所述多个鳍位于所述器件区，且在所述多个鳍的排列方向上，所述多个鳍与所述凹槽之间存在间距；所述鳍包括相连接的第一鳍部和第二鳍部，所述第一鳍部位于所述第二鳍部远离所述基底的一侧；所述多个鳍的第一鳍部的宽度相同。
  12. 根据权利要求11所述的半导体结构，其特征在于，在同一所述鳍中，所述第一鳍部的靠近所述第二鳍部的一端的宽度，小于所述第二鳍部的靠近所述第一鳍部的一端的宽度。
  13. 根据权利要求11或12所述的半导体结构，其特征在于，所述鳍的侧面包括所述第一鳍部的侧面、所述第二鳍部的侧面，以及连接第一鳍部的侧面和第二鳍部的侧面的过渡面；所述过渡面与所述第一鳍部的侧面、第二鳍部的侧面之间均呈钝角。
  14. 根据权利要求11～13中任一项所述的半导体结构，其特征在于，在同一所述器件区内，所述多个鳍的第一鳍部之间的间距相等。
  15. 根据权利要求11～14中任一项所述的半导体结构，其特征在于，还包括：
    浅沟槽隔离层，填充于相邻两个所述鳍之间；所述第一鳍部凸出于所述浅沟槽隔离层。
  16. 一种电子设备，其特征在于，包括如权利要求11～15中任一项所述的半导体结构和印刷电路板；所述半导体结构和所述印刷电路板电连接。
PCT/CN2023/103521 2022-08-22 2023-06-28 半导体结构及其制备方法、电子设备 WO2024041186A1 (zh)

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CN105826193A (zh) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
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