WO2024040698A1 - Procédé de fabrication de structure à semi-conducteur et structure à semi-conducteur - Google Patents

Procédé de fabrication de structure à semi-conducteur et structure à semi-conducteur Download PDF

Info

Publication number
WO2024040698A1
WO2024040698A1 PCT/CN2022/124144 CN2022124144W WO2024040698A1 WO 2024040698 A1 WO2024040698 A1 WO 2024040698A1 CN 2022124144 W CN2022124144 W CN 2022124144W WO 2024040698 A1 WO2024040698 A1 WO 2024040698A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
conductive
substrate
forming
Prior art date
Application number
PCT/CN2022/124144
Other languages
English (en)
Chinese (zh)
Inventor
黄文华
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024040698A1 publication Critical patent/WO2024040698A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure and its structure.
  • Memory is a common semiconductor structure, and the memory includes an array area and a peripheral circuit active area.
  • the array area has a memory array
  • the peripheral circuit active area has a circuit structure that controls the memory array
  • the array area and the peripheral circuit active area Isolation structures are provided in the substrates. Since different transistors in the active area of the peripheral circuit need to be configured with different functions, different structures need to be formed, such as the PMOS area, and usually a channel layer needs to be formed on the top of the substrate in the PMOS area to improve the efficiency of forming PMOS transistors in the PMOS area. Reading speed.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a PMOS region; forming a channel layer, the channel layer being located on the PMOS The surface of the substrate in the area; forming a gate structure and a protective layer, the gate structure is located on the surface of the channel layer, the protective layer covers the surface of the gate structure and the channel layer Part of the surface; after forming the gate structure and the protective layer, a hydrogen ion casting process is used to passivate the surface of the channel layer.
  • the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer, where the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas.
  • the passivation treatment temperature is 310 ⁇ 530°C.
  • the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min.
  • the duration of the passivation treatment is 21 minutes to 39 minutes.
  • the method before performing the passivation treatment, further includes: forming an insulating layer, the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; forming a first conductive layer Pillar, the first conductive pillar penetrates the insulating layer to connect with the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect with the gate structure .
  • the method of forming the first conductive pillar includes etching the insulating layer to form a groove penetrating the insulating layer to expose the PMOS region of the substrate.
  • the surface or the groove penetrates the insulating layer and the protective layer to expose the top surface of the gate; a conductive contact layer is formed, and the conductive contact layer is located on the bottom surface of the groove; a diffusion barrier layer is formed, so The diffusion barrier layer is located on the inner wall of the groove and on the surface of the conductive contact layer; a conductive plug layer is formed, and the conductive plug layer fills the groove.
  • the method of forming the conductive contact layer includes: forming a contact material layer located on the substrate surface or the gate top surface exposed by the bottom surface of the groove; using A rapid thermal annealing process causes the substrate or the gate electrode to react with the contact material layer to form the conductive contact layer.
  • the passivation treatment before performing the passivation treatment, it further includes: forming a first conductive layer, the first conductive layer is located on the surface of the insulating layer, and the first conductive layer is in contact with the first conductive layer. The top surface of the column contacts the connection.
  • the passivation process further includes: performing the passivation process on sidewalls of the first conductive line layer and the first conductive pillar facing the insulating layer.
  • the step of forming the gate structure includes: forming an initial gate dielectric layer covering the surface of the channel layer; forming an initial gate electrode covering the surface of the channel layer; The surface of the initial gate dielectric layer; etching the initial gate electrode and the initial gate dielectric layer, leaving the initial gate electrode as a gate electrode, and the remaining initial gate dielectric layer as a gate dielectric layer, the gate electrode and the gate dielectric layer
  • the dielectric layer serves as the gate structure.
  • the steps of forming the gate structure and the protective layer include: forming the gate structure, which is located on the surface of the channel layer; forming the protective layer, The protective layer covers part of the surface of the channel layer and the sidewalls and top surface of the gate structure.
  • the steps of forming the gate structure and the protective layer include: forming an initial protective layer covering the surface of the channel layer; etching the initial protective layer to form trench, the trench exposes the surface of the channel layer; forming the gate structure, the gate structure is located in the trench; forming a cover layer, the cover layer and the remaining initial protective layer constitute the protective layer.
  • another aspect of the present disclosure further provides a semiconductor structure, including: a substrate including a PMOS region; and a channel layer located at all parts of the PMOS region.
  • the surface of the substrate, hydrogen bonds are formed on the surface of the channel layer; a gate structure, the gate structure is located on the surface of the channel layer; a protective layer, the protective layer covers the gate structure
  • the protective layer also covers at least part of the surface of the channel layer.
  • an insulating layer the insulating layer is located on the surface of the substrate, and the insulating layer covers the sidewall of the protective layer; a first conductive pillar, the first conductive pillar penetrates the insulating layer Connected to the substrate of the PMOS region or the first conductive pillar penetrates the insulating layer and the protective layer to connect to the gate structure.
  • the first conductive pillar includes: a conductive contact layer located within the substrate of the PMOS region or on the top surface of the gate structure; a diffusion barrier layer, the diffusion The bottom surface of the barrier layer is in contact with the top surface of the conductive contact layer.
  • the diffusion barrier layer also includes side surfaces surrounding the bottom surface of the diffusion barrier layer. The bottom surface and side surfaces of the diffusion barrier layer form an accommodation space; a conductive plug layer , the conductive plug layer is located on the surface of the diffusion barrier layer and fills the accommodation space.
  • At least a portion of the conductive plug layer is located within the substrate of the PMOS region.
  • hydrogen bonds are formed on a surface of the first conductive pillar facing the insulating layer.
  • the thickness of the channel layer is 2-10 nm.
  • the technical solution provided by the embodiments of the present disclosure at least has the following advantages: by forming a channel layer in the PMOS region to meet the performance requirements required by the PMOS region, and by setting the channel layer as a channel in the PMOS region, the current carrying capacity of the semiconductor structure can be improved. By using hydrogen ions to passivate the channel layer, the interface state on the surface of the channel layer can be improved, thereby reducing the leakage of the semiconductor structure.
  • FIG. 1 and 2 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • the present disclosure provides a method for manufacturing a semiconductor structure.
  • By passivating the channel layer after forming the channel layer, the gate electrode and the protective layer, using hydrogen ions to passivate the channel layer can reduce the cost of the semiconductor structure.
  • the interface state on the surface of the channel layer can thereby reduce the leakage between the source and drain of the transistor structure formed in the PMOS region.
  • FIGS. 1 and 2 are structural schematic diagrams corresponding to each step of a semiconductor structure provided by embodiments of the present disclosure.
  • a substrate 100 is provided that includes a PMOS region 101 .
  • the substrate 100 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon carbide substrate.
  • the substrate 100 can also be an ion-doped substrate.
  • the doped ions are N-type ions or P-type ions.
  • the N-type ions can be phosphorus ions, arsenic ions or antimony ions, and the P-type ions can be boron ions or indium ions. Or boron fluoride ion.
  • the substrate 100 may be divided into a peripheral region, a core region, and an array region.
  • the peripheral area can be used to form peripheral circuit structures, for example, it can include a peripheral NMOS area and a peripheral PMOS area, where the peripheral NMOS area is the area where peripheral NMOS transistors are to be formed, and the peripheral PMOS area is the area where peripheral PMOS transistors are to be formed.
  • the core area can be used to form a core circuit structure, and the core area can include a core NMOS area and a core PMOS area, where the core NMOS area is the area where the core NMOS transistor is to be formed, and the core PMOS area is the area where the core PMOS transistor is to be formed.
  • the array area may be an area used to form a memory array, and the memory array may include word lines, bit lines, storage capacitors, and the like.
  • the substrate also includes an NMOS region 103 for forming NMOS transistors.
  • the channel layer 110 is formed, and the channel layer 110 is located on the surface of the substrate 100 in the PMOS region 101. It can be understood that by forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, the channel layer 110 can be used as a PMOS The channel of the region 101 , that is to say, by forming the channel layer 110 and using the channel layer 110 as a channel, the mobility of channel carriers in the PMOS region 101 can be improved, so that the required performance of the PMOS region 101 can be achieved.
  • the method of forming the channel layer 110 may be to form an initial channel layer on the surfaces of the PMOS region 101 and the NMOS region 103, and by etching the initial channel layer on the surface of the NMOS region 103, leaving the The initial channel layer serves as channel layer 110 .
  • the material of the channel layer 110 may be silicon germanium or the like.
  • a gate dielectric layer 120 is formed, and the gate dielectric layer 120 is located on the surface of the channel layer 110 .
  • the gate dielectric layer 120 is also located on the surface of the substrate 100 in the NMOS region 103 .
  • part of the channel layer 110 and the substrate 103 of the NMOS region 103 can be converted into the gate dielectric layer 120 by means of in-situ steam generation (ISSG In-Situ Steam Generation).
  • the gate dielectric layer 120 can also be formed on the surface of the substrate 100 of the channel layer 110 and the NMOS region 103 by atomic deposition. The density of the gate dielectric layer 120 can be improved by in-situ water vapor generation. The deposition method can improve the uniformity of the gate dielectric layer 120 .
  • the gate dielectric layer 120 of the NMOS region 103 and the PMOS region 101 may be formed in the same step.
  • Figure 2 is a schematic structural diagram of the PMOS region 101.
  • An isolation layer 130 is formed.
  • the isolation layer 130 includes: a first isolation layer 131; a second isolation layer 132.
  • the second isolation layer 132 is located at the bottom of the first isolation layer 131 and Sidewall; third isolation layer 133.
  • the third isolation layer 133 is located at the bottom and sidewall of the second isolation layer 132.
  • the first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and causing adjacent memory cells to conduct each other, thereby causing the performance of the semiconductor structure to decrease;
  • the second isolation layer The layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area to avoid the interconnection between the circuit structures, thereby preventing the data disorder after the circuit structures are connected from affecting the performance of the semiconductor structure;
  • the third isolation layer 133 can It is used to fill the semiconductor structure so that the morphology of the semiconductor structure is better, and the third isolation layer 133 can isolate adjacent active areas to form separate active areas.
  • the material of the first isolation layer 131 may be the same as the material of the third isolation layer 133, which may be silicon oxide; the material of the second isolation layer 132 may be silicon nitride, silicon oxynitride, or the like.
  • an ONO (Oxide-Nitride-Oxide) structure can be formed, that is, an oxide layer-nitride layer-oxide layer structure.
  • the manufacturing method of the semiconductor structure further includes: forming a gate structure 200 , the gate structure 200 is located on the surface of the channel layer 110 .
  • the gate structure 200 includes a gate electrode 140 and a gate dielectric layer 120 .
  • the steps of forming the gate structure 200 include: forming an initial gate dielectric layer covering the surface of the initial channel layer; forming an initial gate electrode covering the surface of the initial gate dielectric layer; etching The initial gate electrode and the initial gate dielectric layer are etched, and the remaining initial gate electrode is used as the gate electrode 140 , the remaining initial gate dielectric layer is used as the gate dielectric layer 120 , and the gate electrode 140 and the gate dielectric layer 120 are used as the gate electrode structure 200 .
  • the channel layer 110 covers the entire top surface of the substrate 100 , and the length of the channel layer 110 is greater than the length of the gate structure 200 .
  • the step of forming the gate structure 200 may also include forming an initial gate electrode, an initial gate dielectric layer, and an initial channel layer.
  • the initial gate dielectric layer covers the surface of the initial channel layer, and the initial gate electrode covers the initial gate layer.
  • the gate 140 and the gate dielectric layer 120 serve as the gate structure 200
  • the remaining initial channel layer serves as the channel layer 110 , that is to say, the channel layer 110 does not cover the entire top surface of the substrate 100 in the PMOS region 101 , and the length of the channel layer 110 is equal to the length of the gate electrode 140 .
  • the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143.
  • the first gate conductive layer 141 is located in the gate dielectric layer. 120
  • the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141
  • the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142.
  • the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
  • the material of the first gate conductive layer 141 may be a semiconductor material, such as polysilicon, and the material of the first diffusion barrier layer 142 may be a mixture of metal and non-metal materials, such as titanium nitride.
  • the material of the extremely conductive layer 143 can be a metal material, such as metal tungsten, etc.
  • metal ions in the second gate conductive layer 143 can be prevented from diffusing into the first gate conductive layer 141, thereby preventing the first gate conductive layer 141 from being contaminated, thereby improving the performance of the first gate conductive layer 141. Reliability of Semiconductor Structures.
  • parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
  • the gate structure 200 is used to control whether the first doped region 105 and the second doped region 106 are conductive. Theoretically, when the gate structure 200 has no voltage, the first doped region 105 and the second doped region 106 are conductive. No current will flow between the second doped regions 106, that is, the semiconductor structure is in a cut-off state.
  • the gate dielectric layer 120 assuming that the material of the channel layer 110 is silicon germanium, for example, A large number of germanium-oxygen bonds and interface states are formed on the surface of the channel layer 110 , resulting in a large number of leakage paths in the channel layer 110 and increasing the leakage between the first doped region 105 and the second doped region 106 . Therefore, passivation treatment is performed in subsequent steps to reduce the germanium-oxygen bonds and interface states formed on the surface of the channel layer 110, thereby reducing leakage between the first doped region 105 and the second doped region 106.
  • a protective layer 150 covers the surface of the gate structure 200 and part of the surface of the channel layer 110.
  • the gate structure 200 can be isolated from external structures by forming the protective layer 150. Therefore, the gate structure 200 can be prevented from contacting the outside world, the gate structure 200 can be prevented from being in contact with air, the gate structure 200 can be prevented from being oxidized, the reliability of the semiconductor structure can be improved, and the protective layer 150 can also be formed in the semiconductor.
  • the protective layer 150 absorbs part of the stress, thereby reducing the stress on the gate structure 200 and improving the reliability of the semiconductor structure.
  • the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer.
  • the materials of the first protective layer 151 and the third protective layer 153 may be the same.
  • the material of the first protective layer 151 and the third protective layer 153 may be silicon nitride, and the material of the second protective layer 152 may be silicon oxide, so that the protective layer 150 forms NON (Nitride- Oxide-Nitride) structure, that is, nitride layer-oxide layer-nitride layer structure, by providing the second protective layer 152, the insulation performance between the first protective layer 151 and the third protective layer 153 can be improved. Since the second protective layer 152 The material is soft and the morphology is poor. Therefore, the first protective layer 151 and the third protective layer 153 made of nitride layers are formed to improve the morphology of the second protective layer 152 .
  • the channel layer 110 is passivated using hydrogen ions.
  • the gap between the channel layer 110 and the gate electrode 140 It also includes a gate dielectric layer 120.
  • the germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110 will cause a large number of leakage paths in the channel layer 110, resulting in the source of the PMOS tube formed on the PMOS region 101.
  • Leakage occurs between the gate dielectric layer 120 and the channel layer 110 through passivation treatment to destroy the germanium oxide chemical bond formed between the gate dielectric layer 120 and the channel layer 110, thereby reducing the source and drain resistance of the PMOS tube formed on the PMOS region 101. Leakage in the room.
  • the channel layer 110 in the PMOS region 101 By forming the channel layer 110 in the PMOS region 101 to meet the required performance requirements of the PMOS region 101, and by providing the channel layer 110 as the channel layer 110 of the PMOS region 101, the carrier mobility of the semiconductor structure can be improved, The passivation treatment can improve the interface state on the surface of the channel layer 110, thereby reducing the leakage of the semiconductor structure.
  • the steps of forming the gate structure 200 and the protective layer 150 include: forming the gate structure 200, which is located on the surface of the channel layer 110; forming the protective layer 150, which covers the channel layer 110 surface and the sidewalls and top surface of the gate structure 200.
  • the gate structure 200 is formed first, and then the protective layer 150 is formed. This is also a gate-first process.
  • the gate structure 200 is formed first, and then the protective layer 150 is formed.
  • Layer 150 can reduce the process difficulty of the manufacturing method of the semiconductor structure.
  • the steps of forming the gate structure 200 and the protective layer 150 include: forming an initial protective layer to cover the surface of the channel layer 110; etching the initial protective layer to form a trench, and the trench exposes the trench. on the surface of the channel layer 110; a gate structure 200 is formed, and the gate structure 200 is located in the trench; a cover layer is formed, and the cover layer and the remaining initial protective layer constitute the protective layer 150.
  • a part of the protective layer is formed first. 150, and then the gate structure 200 is formed, which is a gate-last process.
  • the passivation process before performing the passivation process, it further includes: forming an insulating layer 160 , the insulating layer 160 is located on the surface of the substrate 100 , and the insulating layer 160 covers the sidewalls of the protective layer 150 .
  • the formation of the insulating layer 160 provides support for the subsequent formation of the first conductive layer 190 .
  • forming the insulating layer 160 further includes: forming a support layer 170 , the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 .
  • the material of the insulating layer 160 can be silicon oxide
  • the material of the supporting layer 170 can be silicon nitride.
  • the material of silicon nitride is relatively hard, so it can have a better supporting effect, and can avoid the problem of insulating the supporting layer.
  • the first conductor layer 190 formed on the surface of 170 is deformed.
  • it may also include: forming a first conductive pillar 180 penetrating the insulating layer 160 to connect with the substrate 100 of the PMOS region 101 or the first conductive pillar 180 penetrating the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 .
  • a first conductive pillar 180 electrical signals from the first doped region 105 and the second doped region 106 can be derived, or signals from the gate structure 200 can be derived, or electrical signals can be provided to the gate structure 200 .
  • the method of forming the first conductive pillar 180 may be: etching the insulating layer 160 and the support layer 170 through mask etching to form a groove, and the groove penetrates the insulating layer 160 to expose the PMOS region 101 lining.
  • the surface or groove of the bottom 100 penetrates the insulating layer 160 and the protective layer 150 to expose the top surface of the gate structure 200; a conductive contact layer 181 is formed, and the conductive contact layer 181 is located on the bottom surface of the groove; a diffusion barrier layer 182 is formed, the diffusion barrier layer 182 is located on the inner wall of the groove and the surface of the conductive contact layer 181; a conductive plug layer 183 is formed, and the conductive plug layer 183 fills the groove.
  • the conductive contact layer 181 can be used to avoid a too large gap between the material properties of the first conductive pillar 180 and the material properties of the substrate 100 when the first conductive pillar 180 contacts the substrate 100, thereby avoiding the first An abnormality occurs during signal transmission between the conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby preventing the metal ions of the conductive plug layer 183 from diffusing to The conductive contact layer 181 affects the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
  • the method of forming the conductive contact layer 181 includes: forming a contact material layer (not shown in the figure), the contact material layer is located on the surface of the substrate 100 exposed by the bottom surface of the groove or the top surface of the gate structure 200 ; Use a rapid thermal annealing process to react the substrate 100 or the gate structure 200 with the contact material layer to form the conductive contact layer 181.
  • the conductive contact layer 181 can be formed using a metal oxide process.
  • the contact resistance between the formed conductive contact layer 181 and the substrate 100 is relatively low, which can improve the performance of the semiconductor structure.
  • the groove is located in the substrate 100, and the formed conductive contact layer 181, part of the diffusion barrier layer 182 and part of the conductive plug layer 183 is located in the substrate 100; in other embodiments, the groove is located in the substrate 100.
  • the conductive contact layer 181 formed is located in the substrate 100 , and the diffusion barrier layer 182 and the conductive plug layer 183 are located on the surface of the substrate 100 .
  • the passivation treatment before performing the passivation treatment, it further includes: forming a first conductive layer 190 , the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 connect.
  • the first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
  • the passivation treatment includes: passing a hydrogen-containing passivation gas into the channel layer 110, the hydrogen-containing passivation gas includes: hydrogen or a mixed gas of hydrogen and an inert gas, passivating the channel layer 110 through hydrogen bonding.
  • the germanium-oxygen bond on the surface reduces the interface state on the surface of the channel layer 110, and after the surface of the channel layer 110 is passivated by hydrogen gas, a film layer with hydrogen bonds will be formed on the surface of the channel layer 110.
  • the bonding film layer can also improve the tightness of the connection between the channel layer 110 and the substrate 100 .
  • the semiconductor structure may be passivated after the protective layer 150 is formed and before the insulating layer 160 is formed. Passivating the semiconductor structure after the protective layer 150 is formed may prevent the gate structure 200 from being passivated. , thereby avoiding affecting the performance of the gate structure 200 .
  • the passivation process can also be performed after the first conductive layer 190 is formed. At this time, the hydrogen-containing passivation gas introduced in the passivation process can pass through the first conductive pillar 180, the insulating layer 160 and the support.
  • connection gap between the layers 170 flows to the surface of the channel layer 110, thereby reacting with the germanium-oxygen bonds on the surface of the channel layer 110, thereby destroying the germanium-oxygen bonds on the surface of the channel layer 110, and reducing the surface area of the channel layer 110. interface state, thereby reducing the leakage path in the channel layer 110 and reducing the possibility of leakage of the semiconductor structure.
  • the passivation process also includes: passivating the sidewalls of the first conductive layer 190 and the first conductive pillar 180 facing the insulating layer 160 , and the surface of the first conductive pillar 180 can also be repaired through the passivation process. , to improve the connection effect between the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160, so that the first conductive layer 190 and the first conductive pillar 180 and the insulating layer 160 can be connected more closely.
  • the gas flow rate of the hydrogen-containing passivation gas introduced into the passivation process is 3.5L/min to 6.5L/min, such as 4L/min or 5L/min. It can be understood that the passivation process The smaller the gas flow rate of the hydrogen-containing passivation gas introduced, the worse the ability to destroy germanium-oxygen bonds. That is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced during the passivation process is less than 3.5L/min At this time, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good.
  • the phenomenon of passivation that is to say, when the gas flow rate of the hydrogen-containing passivation gas introduced in the passivation process is greater than 6.5L/min, it may cause the parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated. ation, causing the performance of the gate structure 200 to degrade.
  • the duration of the passivation treatment is 21 minutes to 39 minutes, such as 25 minutes or 30 minutes.
  • the shorter the duration of the passivation treatment the correspondingly poorer the ability to destroy germanium-oxygen bonds. That is to say, When the passivation treatment time is less than 21 minutes, the passivation effect of the passivation treatment is not good, and the effect of improving the leakage of the semiconductor structure is not good.
  • the passivation phenomenon that is, when the passivation treatment lasts longer than 39 minutes, may cause parts that do not need to be passivated to be passivated, such as the gate structure 200 being passivated, resulting in a decrease in the performance of the gate structure 200 .
  • the temperature of the passivation treatment is 310-530°C, such as 350°C, 400°C, or 450°C.
  • the temperature of the passivation treatment is less than 310°C, the reaction between the hydrogen gas and the channel layer 110 is incomplete and thus As a result, the passivation effect of the passivation treatment is poor.
  • the temperature of the passivation treatment is greater than 530° C., it may affect other formed structures, such as the gate structure 200 , which may cause the performance of the gate structure 200 to decrease.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. After forming the channel layer 110 on the surface of the substrate 100 in the PMOS region 101, and then forming the gate structure 200 and the protective layer 150 on the surface of the channel layer 110, hydrogen is used.
  • the channel layer 110 is passivated by ions to reduce the interface state on the surface of the channel layer 110, thereby reducing the leakage path of the channel layer 110 and improving the reliability of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed by using all or part of the steps of the above-mentioned manufacturing method of the semiconductor structure.
  • the semiconductor structure will be described below with reference to the accompanying drawings. The same or corresponding parts can refer to the above-mentioned embodiments. No further details will be given below.
  • the semiconductor structure includes: a substrate 100, which includes a PMOS region 101; a channel layer 110, which is located on the surface of the substrate 100 in the PMOS region 101, and is formed on the surface of the channel layer 110. Hydrogen bonding; gate structure 200, the gate structure 200 is located on the surface of the channel layer 110; protective layer 150, the protective layer 150 covers the top surface and side walls of the gate structure 200, and the protective layer 150 also covers the channel layer 110 At least part of the surface. Through the hydrogen bonding on the surface of the channel layer 110, the interface state on the surface of the channel layer 110 can be reduced, thereby reducing the leakage of the channel layer 110.
  • the substrate 100 further includes: an NMOS region 103, and the NMOS region 103 is used to form an NMOS tube.
  • the thickness of the channel layer 110 may be 2 to 10 nm, such as 5 nm, 6 nm, 7 nm, or 8 nm.
  • the thickness of the channel layer 110 is greater than 10 nm, the probability of lattice dislocation may increase, resulting in The performance of the semiconductor structure decreases.
  • the thickness of the channel layer 110 is less than 2 nm, the number of carriers in the channel layer 110 is small, and the width of the channel as a semiconductor structure is narrow, which affects the carriers of the semiconductor structure.
  • the transmission rate affects the performance of semiconductor structures.
  • the semiconductor structure further includes: an isolation layer 130.
  • the isolation layer 130 may include: a first isolation layer 131; a second isolation layer 132 located on the bottom and sidewalls of the first isolation layer 131;
  • the third isolation layer 133 is located at the bottom and side walls of the second isolation layer.
  • the first isolation layer 131 can be used to isolate the memory cells in the array area to prevent the memory cells from being too close to each other and affecting each other.
  • the second isolation layer 132 is used to isolate the mutual influence between the circuit structures in the circuit area, to avoid the interconnection between the circuit structures, thereby Prevent data disorder after the circuit structure is connected from affecting the performance of the semiconductor structure;
  • the third isolation layer 133 can be used to fill the semiconductor structure, thereby making the morphology of the semiconductor structure better, and the third isolation layer 133 can separate adjacent active The areas are isolated to form separate active areas.
  • the gate structure 200 includes: a gate electrode 140 and a gate dielectric layer 120.
  • the gate electrode 140 is used to control the conduction of the channel layer 110.
  • the gate dielectric layer 120 is used to prevent the gate electrode 140 from contacting the channel layer 110. direct contact.
  • the gate 140 may have a three-layer structure, including a first gate conductive layer 141, a first diffusion barrier layer 142, and a second gate conductive layer 143.
  • the first gate conductive layer 141 is located in the gate dielectric layer. 120
  • the first diffusion barrier layer 142 is located on the top surface of the first gate conductive layer 141
  • the second gate conductive layer 143 is located on the surface of the first diffusion barrier layer 142.
  • the gate 140 may also be a single-layer structure. The embodiment of the present disclosure does not limit the specific structure of the gate 140 and can be adjusted according to actual conditions.
  • parts of the substrate 100 on both sides of the projection of the gate structure 200 on the surface of the substrate 100 may serve as the first doping region 105 and the second doping region 106 to serve as the source and drain.
  • the protective layer 150 may include a first protective layer 151; a second protective layer 152 located on the sidewall of the first protective layer; and a third protective layer 153 located on the sidewall of the first protective layer.
  • the first protective layer 151 and the third protective layer 153 can be made of the same material.
  • the second protective layer 150 can be made of the same material.
  • the protective layer 152 can improve the insulation performance between the first protective layer 151 and the third protective layer 153.
  • the second protective layer 152 is made of a nitride layer.
  • a protective layer 151 and a third protective layer 153 are used to improve the topography of the second protective layer 152.
  • it also includes: an insulating layer 160 located on the surface of the substrate 100 and covering the sidewalls of the protective layer 150; a first conductive pillar 180 penetrating the insulating layer 160 and The substrate 100 of the PMOS region 101 is connected or the first conductive pillar 180 penetrates the insulating layer 160 and the protective layer 150 to connect with the gate structure 200 .
  • the insulating layer 160 can support the sidewalls of the first conductive pillar 180 and can also support the first conductive line layer 190.
  • the first conductive pillar 180 When the first conductive pillar 180 is connected to the substrate 100 of the PMOS region 101, the first conductive pillar 180 can Electrical signals are extracted from the first doped region 105 and the second doped region 106 of the semiconductor structure, or electrical signals are provided to the first doped region 105 and the second doped region 106; when the first conductive pillar 180 and the gate structure 200 is connected, the electrical signal of the gate structure 200 can be extracted through the first conductive pillar 180 or the electrical signal can be provided to the gate structure 200 .
  • the first conductive pillar 180 includes: a conductive contact layer 181 located in the substrate 100 of the PMOS region 101 or on the top surface of the gate structure 200; a diffusion barrier layer 182 on the bottom surface of the diffusion barrier layer 182 In contact with the top surface of the conductive contact layer 181, the diffusion barrier layer 182 also includes side surfaces surrounding the bottom surface of the diffusion barrier layer 182. The bottom surface and side surfaces of the diffusion barrier layer 182 form an accommodation space; a conductive plug layer 183, which is located The surface of the diffusion barrier layer 182 is filled with the accommodation space. That is to say, when the first conductive pillar 180 is connected to the substrate 100, the conductive contact layer 181 is located in the substrate 100 of the PMOS region 101.
  • the conductive contact layer 181 When the first conductive pillar 180 is connected to the gate structure 200, the conductive contact layer 181 is located in the substrate 100. On the top surface of the gate structure 200, the conductive contact layer 181 can be used to avoid the gap between the material of the first conductive pillar 180 and the material of the substrate 100 being too large when the first conductive pillar 180 is in contact with the substrate 100, thereby preventing the second conductive pillar 180 from being in contact with the substrate 100.
  • An abnormality occurs during signal transmission between a conductive pillar 180 and the substrate 100; the diffusion barrier layer 182 can be used to isolate the conductive contact layer 181 from the conductive plug layer 183, thereby avoiding the diffusion of metal ions in the conductive plug layer 183. into the conductive contact layer 181 to affect the transmission of the conductive contact layer 181; the conductive plug layer 183 is used to increase the transmission speed of the first conductive pillar 180, reduce the response time of the semiconductor structure, and improve the performance of the semiconductor structure.
  • the conductive plug layer 183 may also be located within the substrate 100 of the PMOS region 101 , that is, the bottom surface of the conductive plug layer 183 is lower than the top surface of the substrate 100 .
  • the layer 183 located in the substrate 100 of the PMOS region 101 can improve the reliability of the connection between the first conductive pillar 180 and the substrate 100 , and can also increase the contact area between the first conductive pillar 180 and the substrate 100 and reduce the Contact resistance to substrate 100.
  • a support layer 170 is also included, the support layer 170 is located on the top surface of the insulating layer 160 , and the support layer 170 is located on the top surface of the protective layer 150 .
  • the support layer 170 may provide support for the first conductor layer 190 .
  • the first conductive layer 190 is located on the surface of the insulating layer 160 , and the first conductive layer 190 is in contact with the top surface of the first conductive pillar 180 .
  • the first conductor layer 190 can be used for wiring of the semiconductor structure. That is to say, the structure inside the semiconductor structure can be connected to external electrical signals through the first conductor layer 190 , for example, the first doped region 105 and the first conductor layer can be connected. 190 is connected, and then the electrical signal required by the first doping region 105 is input to the first conductor layer 190, so that the required electrical signal can be input to the first doping region 105.
  • a hydrogen bond is formed on the surface of the first conductive pillar 180 facing the insulating layer 160 .
  • the hydrogen bond disposed between the first conductive pillar 180 and the insulating layer 160 can improve the relationship between the first conductive pillar 180 and the insulating layer 160 . tightness of connection.
  • the embodiment of the present disclosure provides a semiconductor structure, including a substrate 100, a channel layer 110 located on the surface of the substrate 100 in the PMOS region 101, and hydrogen bonds are formed on the surface of the channel layer 110, and a channel layer 110 located on the surface of the channel layer 110.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Des modes de réalisation de la présente divulgation concernent le domaine des semi-conducteurs, et ont pour objet un procédé de fabrication de structure à semi-conducteur et une structure à semi-conducteur. Le procédé de fabrication de structure à semi-conducteur comprend : la fourniture d'un substrat, le substrat comprenant une région PMOS ; la formation d'une couche de canal, la couche de canal étant située sur la surface du substrat dans la région PMOS ; la formation d'une structure de grille et d'une couche de protection, la structure de grille étant située sur la surface de la couche de canal, et la couche de protection recouvrant la surface de la structure de grille et une partie de la surface de la couche de canal ; et, après la formation de la structure de grille et de la couche de protection, la passivation de la surface de la couche de canal à l'aide d'un processus d'implantation d'ions hydrogène. Par conséquent, une fuite électrique de la structure à semi-conducteur peut être réduite.
PCT/CN2022/124144 2022-08-25 2022-10-09 Procédé de fabrication de structure à semi-conducteur et structure à semi-conducteur WO2024040698A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211027230.8 2022-08-25
CN202211027230.8A CN117690794A (zh) 2022-08-25 2022-08-25 一种半导体结构的制作方法及其结构

Publications (1)

Publication Number Publication Date
WO2024040698A1 true WO2024040698A1 (fr) 2024-02-29

Family

ID=90012231

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/124144 WO2024040698A1 (fr) 2022-08-25 2022-10-09 Procédé de fabrication de structure à semi-conducteur et structure à semi-conducteur

Country Status (2)

Country Link
CN (1) CN117690794A (fr)
WO (1) WO2024040698A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299277A (ja) * 1987-05-29 1988-12-06 Seiko Epson Corp 薄膜トランジスタの製造方法
JPH05102471A (ja) * 1991-10-03 1993-04-23 Sharp Corp 半導体装置の製造方法
CN1196573A (zh) * 1997-02-06 1998-10-21 日本电气株式会社 可用氢离子改变其阈值电压的场效应晶体管的制造工艺
CN101183683A (zh) * 2006-11-16 2008-05-21 国际商业机器公司 用于减小mosfet器件中的浮体效应的方法和结构
CN110993607A (zh) * 2019-11-21 2020-04-10 长江存储科技有限责任公司 具有阻挡结构的存储器件及其制备方法
CN112490180A (zh) * 2019-09-12 2021-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299277A (ja) * 1987-05-29 1988-12-06 Seiko Epson Corp 薄膜トランジスタの製造方法
JPH05102471A (ja) * 1991-10-03 1993-04-23 Sharp Corp 半導体装置の製造方法
CN1196573A (zh) * 1997-02-06 1998-10-21 日本电气株式会社 可用氢离子改变其阈值电压的场效应晶体管的制造工艺
CN101183683A (zh) * 2006-11-16 2008-05-21 国际商业机器公司 用于减小mosfet器件中的浮体效应的方法和结构
CN112490180A (zh) * 2019-09-12 2021-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110993607A (zh) * 2019-11-21 2020-04-10 长江存储科技有限责任公司 具有阻挡结构的存储器件及其制备方法

Also Published As

Publication number Publication date
CN117690794A (zh) 2024-03-12

Similar Documents

Publication Publication Date Title
US6992358B2 (en) Semiconductor device and method for manufacturing the same
US9564352B2 (en) Method for fabricating semiconductor device including isolation layer
KR20040013578A (ko) 반도체 메모리 장치 및 그의 제조방법
JP2004119644A (ja) 半導体装置の製造方法及び半導体装置
JPH11251457A (ja) 半導体デバイス，メモリ・セル，およびその形成方法
JP3723173B2 (ja) 不揮発性半導体記憶装置の製造方法
JP2009044000A (ja) 不揮発性半導体メモリ及びその製造方法
TW202036859A (zh) 半導體裝置及其製造方法
JP4221214B2 (ja) 半導体装置の製造方法
US8043912B2 (en) Manufacturing method of a semiconductor device having polycide wiring layer
WO2024040698A1 (fr) Procédé de fabrication de structure à semi-conducteur et structure à semi-conducteur
US7964917B2 (en) Semiconductor device including liner insulating film
JP2001156271A (ja) 半導体素子の製造方法
US20050062113A1 (en) Semiconductor device with an insulating layer including deuterium and a manufacturing method thereof
US7038304B2 (en) Semiconductor memory device and manufacturing method thereof
US20050048763A1 (en) Method for preventing contact defects in interlayer dielectric layer
US11640981B2 (en) Semiconductor structure and manufacturing method thereof
JP2014099551A (ja) 半導体装置とその製造方法
JP7180425B2 (ja) 炭化珪素半導体装置
JPH06104399A (ja) 半導体記憶装置
JP4010425B2 (ja) 半導体装置及びその製造方法
JP3319856B2 (ja) 半導体装置及びその製造方法
KR100762232B1 (ko) 리세스된 셀어레이 트랜지스터의 제조방법
KR20230059494A (ko) 반도체 장치 및 그 제조방법
JP2021061450A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22956238

Country of ref document: EP

Kind code of ref document: A1