WO2024040693A1 - 一种延迟锁相环和存储器 - Google Patents

一种延迟锁相环和存储器 Download PDF

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Publication number
WO2024040693A1
WO2024040693A1 PCT/CN2022/123835 CN2022123835W WO2024040693A1 WO 2024040693 A1 WO2024040693 A1 WO 2024040693A1 CN 2022123835 W CN2022123835 W CN 2022123835W WO 2024040693 A1 WO2024040693 A1 WO 2024040693A1
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Prior art keywords
signal
clock signal
pulse
delay
output
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PCT/CN2022/123835
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English (en)
French (fr)
Inventor
李思曼
严允柱
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长鑫存储技术有限公司
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Priority to US18/448,946 priority Critical patent/US20240063802A1/en
Publication of WO2024040693A1 publication Critical patent/WO2024040693A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present disclosure relates to the field of semiconductor memory technology, and in particular to a delay locked loop and a memory.
  • DRAM Dynamic Random Access Memory
  • the delay-locked loop needs to phase synchronize and lock the four-phase clock signal (that is, the four clock signals with a phase difference of 90 degrees in sequence), resulting in a phase difference of 90 A set of target clock signals in order to sample the data signal DQ.
  • the phase difference between the target clock signals finally generated may be offset, reducing the data sampling effect.
  • the present disclosure provides a delay locked loop and a memory capable of reducing the phase deviation of a target clock signal output by the delay locked loop.
  • an embodiment of the present disclosure provides a delay locked loop, which includes:
  • a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal;
  • a first adjustable delay line configured to receive the first clock signal, adjust and transmit the first clock signal, and output a first target clock signal
  • a second adjustable delay line configured to receive the second clock signal, adjust and transmit the second clock signal, and output a second synchronous clock signal
  • a first adjustment module configured to receive the first target clock signal and the second synchronous clock signal, perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target clock signal.
  • the phase difference between the first target clock signal and the second target clock signal is a preset value.
  • the preprocessing module includes: a receiving module configured to receive the initial clock signal and output a clock signal to be processed; wherein the clock period of the clock signal to be processed is the same as the clock period of the initial clock signal. The cycles are the same; the phase separation module is configured to receive the clock signal to be processed, perform frequency division and phase separation processing on the clock signal to be processed, and output the first clock signal and the second clock signal; wherein, The clock period of the first clock signal and the second clock signal are the same, and the clock period of the first clock signal is twice the clock period of the initial clock signal.
  • the first adjustment module includes: a first control module configured to receive the first target clock signal and the second synchronization clock signal, based on the first target clock signal and the The phase difference between the second synchronization clock signals outputs a first control code; a first delay chain includes a plurality of first delay units configured to receive the first control code and the second synchronization clock signal; based on the The first control code uses a plurality of first delay units to perform delay adjustment on the second synchronization clock signal and output the second target clock signal.
  • the first control module includes: a first pulse processing module configured to receive the first target clock signal and the second synchronous clock signal, and output the first pulse signal and the second pulse signal ; Wherein, the first pulse signal and the second pulse signal each include 1 pulse, and the pulse width of the first pulse signal indicates the difference between the first target clock signal and the second synchronous clock signal.
  • the phase difference between, the pulse width of the second pulse signal indicates the phase difference between the second synchronous clock signal and the inverted signal of the first target clock signal;
  • the first time-to-digital conversion module is configured to receive The first pulse signal and the second pulse signal; the first pulse signal is converted to output a first conversion code, and the second pulse signal is converted to output a second conversion code; wherein, The first conversion code is used to characterize the width of the first pulse signal, and the second conversion code is used to characterize the width of the second pulse signal;
  • a first logic module is configured to receive the first conversion code and The second conversion code performs a subtraction operation on the second conversion code and the first conversion code, and outputs the first control code.
  • the first pulse processing module includes: the first pulse module configured to receive the first target clock signal and the second synchronization clock signal, and process the first target clock signal and the second synchronization clock signal. Perform XOR processing on two synchronous clock signals to obtain a first detection signal, perform pulse interception and broadening processing on the first detection signal to obtain a first intermediate signal, and perform AND processing on the first intermediate signal and the first detection signal. , output the first pulse signal; wherein the first detection signal includes a plurality of pulses, and the pulse width of the first detection signal indicates the distance between the first target clock signal and the second synchronization clock signal.
  • the phase difference, the first intermediate signal includes a pulse, the pulse width of the first intermediate signal is greater than the pulse width of the first detection signal;
  • the second pulse module is configured to receive the first target clock signal Invert the signal and the second synchronous clock signal, perform XOR processing on the inverted signal of the first target clock signal and the second synchronous clock signal to obtain a second detection signal, and perform pulse interception on the second detection signal and broadening processing to obtain a second intermediate signal, performing AND processing on the second intermediate signal and the second detection signal, and outputting the second pulse signal; wherein the second detection signal includes a plurality of pulses, and the The pulse width of the second detection signal indicates the phase difference between the inverted signal of the first target clock signal and the second synchronous clock signal, the second intermediate signal includes one pulse, and the pulse of the second intermediate signal The width is greater than the pulse width of the second detection signal.
  • the first time conversion module includes: a first conversion module configured to receive a first pulse signal, and use the first pulse signal to perform sampling and delay processing to obtain a plurality of first sampling clock signals, Use a plurality of the first sampling clock signals to perform sampling processing on the first pulse signal, and output the first conversion code; a second conversion module configured to receive a second pulse signal, and use the second pulse signal to perform sampling processing. Sampling and delay processing are performed to obtain a plurality of second sampling clock signals, the plurality of second sampling clock signals are used to perform sampling processing on the second pulse signal, and the second conversion code is output.
  • the preprocessing module is further configured to preprocess the initial clock signal and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal;
  • the delay lock The phase loop also includes: a third adjustable delay line configured to receive the third clock signal, adjust and transmit the third clock signal, and output a third target clock signal; wherein the first target clock signal The phase difference with the third target clock signal is 180 degrees; a fourth adjustable delay line is configured to receive the fourth clock signal, adjust and transmit the fourth clock signal, and output a fourth synchronous clock signal ;
  • the second adjustment module is configured to receive the third target clock signal and the fourth synchronous clock signal, perform delay adjustment on the fourth synchronous clock signal based on the third target clock signal, and output the fourth target clock signal; wherein the adjacent phase differences between the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are all 90 degrees.
  • the phase separation module is further configured to perform frequency division and phase separation processing on the clock signal to be processed, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. ; Wherein, the clock cycles of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are the same, and the clock cycle of the first clock signal is the initial clock 2 times the clock period of the signal.
  • the second adjustment module includes: a second control module configured to receive the third target clock signal and the fourth synchronization clock signal, based on the third target clock signal and the The phase difference between the fourth synchronous clock signals outputs a second control code;
  • the second delay chain includes a plurality of second delay units configured to receive the second control code and the fourth synchronous clock signal, based on the The second control code uses a plurality of second delay units to perform delay adjustment on the fourth synchronization clock signal and output the fourth target clock signal.
  • the second control module includes: a second pulse processing module configured to receive the third target clock signal and the fourth synchronous clock signal, and output a third pulse signal and a fourth pulse signal. ; Wherein, the third pulse signal and the fourth pulse signal each include 1 pulse, and the pulse width of the third pulse signal indicates the difference between the third target clock signal and the fourth synchronous clock signal.
  • the phase difference between, the pulse width of the fourth pulse signal indicates the phase difference between the fourth synchronous clock signal and the inverse signal of the third target clock signal;
  • the second time-to-digital conversion module is configured to receive The third pulse signal and the third pulse signal;
  • the third pulse signal is converted to output a third conversion code, and the fourth pulse signal is converted to output a fourth conversion code;
  • the third conversion code is used to characterize the width of the third pulse signal, the fourth conversion code is used to characterize the width of the fourth pulse signal;
  • the second logic module is configured to receive the third conversion code and The fourth conversion code performs a subtraction operation on the fourth conversion code and the third conversion code, and outputs the second control code.
  • the second pulse processing module includes: the third pulse module configured to receive the third target clock signal and the fourth synchronous clock signal, and perform the processing on the third target clock signal and the fourth synchronous clock signal.
  • the fourth synchronous clock signal is XOR-processed to obtain a third detection signal
  • the third detection signal is subjected to pulse interception and broadening processing to obtain a third intermediate signal
  • the third intermediate signal and the third detection signal are processed.
  • the third detection signal includes a plurality of pulses, and the pulse width of the third detection signal indicates the third target clock signal and the fourth synchronous clock signal
  • the phase difference between the third intermediate signal includes one pulse, and the pulse width of the third intermediate signal is greater than the pulse width of the third detection signal
  • the fourth pulse module is configured to receive the third
  • the inverted signal of the three target clock signals and the fourth synchronous clock signal are XOR-processed to obtain a fourth detection signal, and the fourth detection signal is obtained by XORing the inverted signal of the third target clock signal and the fourth synchronous clock signal.
  • the detection signal is subjected to pulse interception and broadening processing to obtain a fourth intermediate signal, the fourth intermediate signal and the fourth detection signal are AND-processed, and the fourth pulse signal is output; wherein the fourth detection signal includes a plurality of pulses, and the pulse width of the fourth detection signal indicates the phase difference between the inverted signal of the third target clock signal and the fourth synchronous clock signal, the fourth intermediate signal includes one pulse, and The pulse width of the fourth intermediate signal is greater than the pulse width of the fourth detection signal.
  • the second time conversion module includes: a third conversion module configured to receive a third pulse signal, sample and delay the third pulse signal to obtain a plurality of third sampling clock signals, Utilize a plurality of the third sampling clock signals to perform sampling processing on the third pulse signal and output the third conversion code; a fourth conversion module is configured to receive the fourth pulse signal and convert the fourth pulse signal to Sampling and delay processing are performed to obtain a plurality of fourth sampling clock signals, the plurality of fourth sampling clock signals are used to perform sampling processing on the fourth pulse signal, and the fourth conversion code is output.
  • the first pulse module includes: a first flip-flop, a second flip-flop, a first NOT gate, a fourth delay unit, a first AND gate, a first XOR gate, and a second AND gate;
  • the second pulse module, the third pulse module, the fourth pulse module and the first pulse module have the same structures; wherein, in the first pulse module, the first XOR gate
  • the first input terminal of the first XOR gate receives the first target clock signal
  • the second input terminal of the first XOR gate receives the second synchronous clock signal
  • the output terminal of the first XOR gate is used to output the The first detection signal
  • the input terminal of the first flip-flop receives the first power signal
  • the clock terminal of the first flip-flop is connected to the output terminal of the first XOR gate
  • the input of the first NOT gate The terminal is connected to the output terminal of the first XOR gate, the input terminal of the second flip-flop receives the ground signal, and the output terminal of the second flip-flop is connected to the output terminal of
  • Two input terminals are connected to the output terminal of the fourth delay unit, and the output terminal of the first AND gate is used to output the first intermediate signal; the first input terminal of the second AND gate is connected to the first The output terminal of the AND gate is connected, the second input terminal of the second AND gate is connected to the output terminal of the first XOR gate, and the output terminal of the second AND gate is used to output the first pulse signal.
  • each of the first conversion code, the second conversion code, the third conversion code, and the fourth conversion code includes a multi-bit sub-signal;
  • the first conversion module includes a third trigger , a third delay chain, and a plurality of fourth flip-flops, and the second conversion module, the third conversion module, and the fourth conversion module all have the same structure as the first conversion module; wherein, In the first conversion module, the input terminal of the third flip-flop receives the second power signal, the clock terminal of the third flip-flop receives the first pulse signal, and the output terminal of the third flip-flop receives the second power signal.
  • the third delay chain includes a plurality of third delay units arranged in series, one The clock terminal of the fourth flip-flop is connected correspondingly to the output terminal of a third delay unit, and the output terminal of the fourth flip-flop outputs a bit signal of the first conversion code.
  • the first delay chain includes a plurality of first delay units arranged in series, and the second delay chain includes a plurality of second delay units; the first delay unit in the first delay chain, The second delay unit in the second delay chain and the third delay unit in the third delay chain correspond to the same.
  • the i-th sub-signal of the first control code is used to control the i-th first delay unit to be in an on or off state
  • the i-th sub-signal of the second control code is used to control the i-th
  • a second delay unit is in an on state or a closed state
  • the first delay chain is specifically configured to use the first delay unit in an on state to delay the second synchronization clock signal and output the second target Clock signal
  • the second delay chain is specifically configured to use the second delay unit in an on state to delay the fourth synchronous clock signal and output the fourth target clock signal.
  • the first a-bit sub-signal of the first control code is in the first state
  • the last (A-a) bit signal of the first control code is in the second state
  • the first b-bit signal of the second control code is in the second state.
  • the signal is in the first state, and the last (B-b) bit signal of the second control code is in the second state;
  • A, B, a, and b are all positive integers, and a is less than or equal to A, and A refers to the first control code
  • the total number of sub-signal bits in the second control code, b is less than or equal to B, and B refers to the total number of sub-signal bits in the second control code;
  • the first delay chain is specifically configured to utilize the first to a-th all
  • the first delay unit performs delay processing on the second synchronization clock signal, and determines the output signal of the a-th first delay unit as the second target clock signal;
  • the second delay chain specific configuration In order to use the 1st to bth second delay units to perform delay processing on the fourth synchronous clock signal, and determine the output signal of the bth second delay unit as the fourth target clock signal .
  • the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are used for data sampling processing after passing through the corresponding signal transmission path.
  • the delay locked loop also includes: a feedback module configured to receive the first clock signal and output an analog clock signal, and the analog clock signal is used to simulate the first target clock signal through the signal transmission The waveform after the path; the detection module is configured to receive the first clock signal and the analog clock signal, perform phase detection on the first clock signal and the analog clock signal, and obtain a phase detection signal; the parameter adjustment module, The first adjustable delay line is configured to receive the phase detection signal and output a delay line control signal based on the phase detection signal; the first adjustable delay line is specifically configured to receive the delay line control signal and output a delay line control signal based on the delay line control signal.
  • the first clock signal is adjusted and transmitted to output the first target clock signal;
  • the second adjustable delay line is specifically configured to receive the delay line control signal, and adjust the third delay line control signal based on the delay line control signal.
  • the two clock signals are adjusted and transmitted, and the second synchronous clock signal is output.
  • the feedback module includes: a fifth adjustable delay line configured to receive the first clock signal and the delay line control signal, and modify the first clock signal based on the delay line control signal. Adjust and transmit, and output a replica clock signal; wherein the fifth adjustable delay line has the same structure as the first adjustable delay line, and the replica clock signal is used to simulate the waveform of the first target clock signal. ;
  • the replication delay module is configured to receive the replica clock signal, perform delay processing on the replica clock signal, and output an analog clock signal; wherein the replica delay module is configured to simulate the delay of the signal transmission path.
  • embodiments of the present disclosure provide a memory, which at least includes the delay-locked loop as described in the first aspect.
  • Embodiments of the present disclosure provide a delay locked loop and a memory.
  • the delay locked loop includes: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, and output a second A clock signal and a second clock signal; the first adjustable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal; the second adjustable delay line is configured to Receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal; the first adjustment module is configured to perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target Clock signal; wherein the phase difference between the first target clock signal and the second target clock signal is a preset value. In this way, the first adjustment module can correct the phase difference between the first synchronization clock signal and the second target clock signal, and improve the phase deviation between the target clock signals.
  • Figure 1 is a schematic structural diagram of a delay-locked loop
  • Figure 2 is a signal timing diagram 1
  • Figure 3 is a signal timing diagram 2
  • Figure 4 is a schematic structural diagram of a delay-locked loop provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram 2 of a delay-locked loop provided by an embodiment of the present disclosure
  • Figure 6 is a signal timing diagram 1 provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram 3 of a delay-locked loop provided by an embodiment of the present disclosure.
  • Figure 8 is a signal timing diagram 2 provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of a partial structure of a delay-locked loop provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram 2 of a partial structure of a delay-locked loop provided by an embodiment of the present disclosure
  • Figure 11 is a signal timing diagram 3 provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of a clock synchronization circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure.
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • Low Power DDR Low Power DDR (Low Power DDR, LPDDR)
  • DDRn The nth generation DDR standard (DDRn Specification, DDRn), such as DDR3, DDR4, DDR5, DDR6
  • LPDDRn The nth generation LPDDR standard (LPDDRn Specification, LPDDRn), such as LPDDR3, LPDDR4, LPDDR5, LPDDR6
  • DLL Delay Locked Loop
  • the initial clock signal CLK from the outside will be divided/phased internally to obtain a four-phase clock signal.
  • the four-phase clock signals are sent to the delay-locked loop for phase separation. Synchronize and lock, and then use the adjusted four-phase clock signal to sample and select the output of the data signal DQ through the data selection module (Mux) to obtain the target data signal.
  • FIG. 1 shows a schematic structural diagram of a delay-locked loop.
  • Figure 2 shows a signal timing diagram 1.
  • the initial clock signal CLK enters the delay locked loop through the receiving module, and is then processed by the phase splitting module into a four-phase clock signal (ie clk0, clk90, clk180 and clk270), and the four-phase clock signal
  • the frequency is reduced to half of the initial clock signal CLK; secondly, the four-phase clock signal is delayed and the duty cycle is adjusted through four adjustable delay lines.
  • the delay-locked loop performs phase locking, four-phase target clock signals (i.e., DLL0, DLL90, DLL180, and DLL270) are obtained, and the target clock signals DLL0, DLL90, DLL180, and DLL270 are transmitted to the data via corresponding signal transmission paths
  • the selection module and the data selection module convert the four-phase target clock signals DLL0, DLL90, DLL180 and DLL270 into the data sampling clock signal DQS, and then use the data sampling clock signal DQS to sample the data signal DQ to obtain the target data signal.
  • the delay-locked loop also includes a fifth adjustable delay line, a replica delay module, a detection module and a parameter adjustment module.
  • the fifth adjustable delay line and the replica delay module form a loop, and the fifth adjustable delay line receives the clock.
  • Signal clk0 the copy delay module outputs an analog clock signal.
  • the analog clock signal is used to simulate the waveform of the target clock signal DLL0 when it is transmitted to the data selection module.
  • the detection module detects the phase difference between the analog clock signal and the clock signal clk0, and adjusts the parameters.
  • the module outputs a delay line control signal according to the detection result of the detection module, and the delay line control signal is used to control the working parameters of all adjustable delay lines. In this way, the delay-locked loop has a closed-loop feedback mechanism to ensure that the final processed target clock signal DLL0/DLL90/DLL180/DLL270 meets the requirements.
  • the initial clock signal CLK is divided into four channels and enters the delay locked loop.
  • four main adjustable delays need to be prepared inside the delay locked loop. line to perform phase synchronization and locking processing on the four-phase clock signal, and finally transmit it to the data selection module (Mux).
  • the data selection module Mux
  • the target clock signal DLL0/DLL90/DLL180/DLL270 there is also a certain phase deviation between them.
  • FIG. 3 shows a signal timing diagram 2.
  • the phase differences (reflected in T1, T2, T3 and T4) between the target clock signals DLL0DLL90/DLL180/DLL270 that are finally sent to the data selection module are not the same.
  • the pulse in the data sampling clock signal DQS The lengths of the periods (reflected as t1 and t2) are not the same, that is, the effective window of the data sampling clock signal is smaller, which limits the improvement of memory performance.
  • embodiments of the present disclosure provide a delay-locked loop for improving the phase deviation between clock signals output by the delay-locked loop, so as to further improve the performance of the memory.
  • FIG. 4 shows a schematic structural diagram 1 of a delay-locked loop 10 provided by an embodiment of the present disclosure.
  • the delay locked loop 10 includes:
  • the preprocessing module 11 is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal;
  • the first adjustable delay line 12 is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal;
  • the second adjustable delay line 13 is configured to receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal;
  • the first adjustment module 14 is configured to receive a first target clock signal and a second synchronous clock signal, perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target clock signal, and the first target clock signal.
  • the phase difference between the second target clock signal and the second target clock signal is a preset value.
  • the delay locked loop 10 of the embodiment of the present disclosure can be applied to, but is not limited to, memories such as DRAM, SDRAM, etc.
  • a set of clock signals with different phases can be generated through the delay-locked loop 10 provided by the embodiment of the present disclosure.
  • the first target clock signal and the second synchronous clock signal are obtained respectively through the first adjustable delay line 12 and the second adjustable delay line 13, and then the first adjustment module 14 is used to adjust the second synchronous clock signal.
  • the signal is delayed and adjusted to obtain a second target clock signal, ensuring that the phase difference between the first target clock signal and the second target clock signal is a preset value.
  • the first adjustment module 14 the phase difference between the first synchronization clock signal and the second target clock signal can be corrected, and the phase deviation caused by delay line mismatch or preprocessing process can be improved.
  • the default value can be set according to the actual application scenario, such as 180 degrees and 90 degrees.
  • the embodiments of the present disclosure allow a certain error in limiting the phase difference, that is, the phase difference between the first target clock signal and the second target clock signal is a preset value within the allowed error range. Unless otherwise specified, subsequent limitations on phase difference and clock cycle can be understood accordingly.
  • the first target clock signal can be represented as DLL0 and the second target clock signal can be represented as DLL90. Please refer to other situations for understanding.
  • FIG. 5 shows a second structural schematic diagram of a delay-locked loop 10 provided by an embodiment of the present disclosure.
  • the preprocessing module 11 includes:
  • the receiving module 111 is configured to receive the initial clock signal CLK and output a clock signal to be processed; wherein the clock cycle of the clock signal to be processed is the same as the clock cycle of the initial clock signal CLK;
  • the phase separation module 112 is configured to receive a clock signal to be processed, perform frequency division and phase separation processing on the clock signal to be processed, and output a first clock signal clk0 and a second clock signal clk90; wherein, the first clock signal clk0 and the second clock signal The clock cycle of clk90 is the same, and the clock cycle of the first clock signal clk0 is twice the clock cycle of the initial clock signal CLK.
  • phase difference between the first clock signal clk0 and the second clock signal clk90 is 90 degrees.
  • the operating parameters of the phase separation module 112 There may be a deviation, causing the phase difference between the first clock signal clk0 and the second clock signal clk90 to be not 90 degrees and exceed the allowable error range, which is part of the reason why the first adjustment module 14 needs to be introduced.
  • the first adjustment module 14 includes:
  • the first control module 141 is configured to receive the first target clock signal DLL0 and the second synchronous clock signal DL90, and output the first control code DLLCode1 ⁇ based on the phase difference between the first target clock signal DLL0 and the second synchronous clock signal DL90. N:0>;
  • the first delay chain 142 includes a plurality of first delay units and is configured to receive the first control code DLLCode1 ⁇ N:0> and the second synchronization clock signal DL90; based on the first control code DLLCode1 ⁇ N:0>, using multiple The first delay unit performs delay adjustment on the second synchronization clock signal DL90 and outputs the second target clock signal DLL90.
  • the first control code DLLCode1 ⁇ N:0> is converted based on the phase deviation between the second synchronization clock signal DL90 and the ideal situation (that is, the first target clock signal DLL0 is delayed by 90 degrees). Further, the first delay chain 142 can control the phase of the second synchronization clock signal DL90 to adjust forward or backward based on the first control code DLLCode1 ⁇ N:0> to obtain the second target clock signal DLL90 to ensure the first target clock The phase difference between signal DLL0 and second target clock signal DLL90 is 90 degrees.
  • the first control module 141 includes:
  • the first pulse processing module 21 is configured to receive the first target clock signal DLL0 and the second synchronous clock signal DL90, and output the first pulse signal IN0 and the second pulse signal IN1; wherein, the first pulse signal IN0 and the second pulse signal IN1 Each includes 1 pulse, and the pulse width of the first pulse signal IN0 indicates the phase difference between the first target clock signal DLL0 and the second synchronous clock signal DL90, and the pulse width of the second pulse signal IN1 indicates the second synchronous clock signal.
  • the first time-to-digital conversion module 22 is configured to receive the first pulse signal IN0 and the second pulse signal IN1; convert the first pulse signal IN0, output the first conversion code TDCCode0 ⁇ N:0>, and convert the second pulse signal IN0 IN1 converts and outputs the second conversion code TDCCode1 ⁇ N:0>; among them, the first conversion code TDCCode0 ⁇ N:0> is used to characterize the width of the first pulse signal IN0, and the second conversion code TDCCode1 ⁇ N:0> is used To characterize the width of the second pulse signal IN1;
  • the first logic module 23 is configured to receive the first conversion code TDCCode0 ⁇ N:0> and the second conversion code TDCCode1 ⁇ N:0>, and to receive the second conversion code TDCCode1 ⁇ N:0> and the first conversion code TDCCode0 ⁇ N :0> performs subtraction operation and outputs the first control code DLLCode1 ⁇ N:0>.
  • the pulse width of the first pulse signal IN0 is greater than the pulse width of the second pulse signal IN1, it means that the second synchronous clock signal DL90 is too lagging; if the pulse width of the first pulse signal IN0 is less than the pulse width of the second pulse signal IN1, This indicates that the second synchronization clock signal DL90 is too advanced.
  • the value of the first conversion code TDCCode0 ⁇ N:0> corresponds to the pulse width of the first pulse signal IN0
  • the value of the second conversion code TDCCode1 ⁇ N:0> corresponds to the pulse width of the second pulse signal IN1.
  • the first conversion code TDCCode0 ⁇ N:0> can be obtained by subtracting the first conversion code TDCCode0 ⁇ N:0> from the second conversion code TDCCode1 ⁇ N:0> to obtain the first control code DLLCode1 ⁇ N:0>.
  • the first pulse processing module 21 includes:
  • the first pulse module 211 is configured to receive the first target clock signal DLL0 and the second synchronous clock signal DL90, perform XOR processing on the first target clock signal DLL0 and the second synchronous clock signal DL90 to obtain the first detection signal D0, and perform XOR processing on the first target clock signal DLL0 and the second synchronous clock signal DL90 to obtain the first detection signal D0.
  • a detection signal D0 is subjected to pulse interception and broadening processing to obtain a first intermediate signal S0.
  • the first intermediate signal S0 and the first detection signal D0 are AND-processed to output a first pulse signal IN0; wherein the first detection signal D0 includes a plurality of pulse, and the pulse width of the first detection signal D0 indicates the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90, the first intermediate signal S0 includes one pulse, and the pulse width of the first intermediate signal S0 is greater than the first - the pulse width of the detection signal D0;
  • the second pulse module 212 is configured to receive the inverted signal of the first target clock signal and the second synchronous clock signal DL90, and perform XOR processing on the inverted signal of the first target clock signal and the second synchronous clock signal DL90 to obtain the second Detect signal D1, perform pulse interception and broadening processing on the second detection signal D1 to obtain the second intermediate signal S1, perform AND processing on the second intermediate signal S1 and the second detection signal D1, and output the second pulse signal IN1; wherein, the second The detection signal D1 includes a plurality of pulses, and the pulse width of the second detection signal D1 indicates a phase difference between the inverted signal of the first target clock signal and the second synchronization clock signal DL90, the second intermediate signal S1 includes one pulse, and the second intermediate signal S1 includes one pulse. The pulse width of the second intermediate signal S1 is greater than the pulse width of the second detection signal D1.
  • the pulse of the first intermediate signal S0 covers at least one complete pulse in the first detection signal D0
  • the pulse of the second intermediate signal S1 covers at least one complete pulse in the second detection signal D1.
  • " ⁇ " represents the broadening amount in the broadening process.
  • first pulse module 211 and the second pulse module 212 can be combined using a variety of electrical devices, and a specific example will be provided later in the embodiment of this disclosure.
  • the first time conversion module 22 includes:
  • the first conversion module 221 is configured to receive the first pulse signal IN0, use the first pulse signal IN0 to perform sampling and delay processing to obtain a plurality of first sampling clock signals, and use the plurality of first sampling clock signals to convert the first pulse signal IN0 Perform sampling processing and output the first conversion code TDCCode0 ⁇ N:0>;
  • the second conversion module 222 is configured to receive the second pulse signal IN1, use the second pulse signal IN1 to perform sampling and delay processing to obtain a plurality of second sampling clock signals, and use the plurality of second sampling clock signals to convert the second pulse signal IN1 Sampling processing is performed, and the second conversion code TDCCode1 ⁇ N:0> is output.
  • first conversion module 221 and the second conversion module 222 are similar and can be combined using a variety of electrical devices. A specific example will be provided later in the embodiment of this disclosure.
  • FIG. 7 shows a schematic structural diagram 3 of a delay-locked loop 10 provided by an embodiment of the present disclosure.
  • the output signal of the delay locked loop 10 may further include a third target clock signal DLL180 and a fourth target clock signal DLL270 . That is to say, the delay locked loop 10 outputs the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270, and the phase difference between adjacent target clock signals is is 90 degrees.
  • the preprocessing module 11 is also configured to preprocess the initial clock signal CLK and output the first clock signal clk0, the second clock signal clk90, the third clock signal clk180 and the fourth clock signal clk270.
  • the delay locked loop 10 also includes:
  • the third adjustable delay line 15 is configured to receive the third clock signal clk180, adjust and transmit the third clock signal clk180, and output the third target clock signal DLL180; wherein, the first target clock signal DLL0 and the third target clock signal The phase difference of DLL180 is 180 degrees;
  • the fourth adjustable delay line 16 is configured to receive the fourth clock signal clk270, adjust and transmit the fourth clock signal clk270, and output the fourth synchronous clock signal DL270;
  • the second adjustment module 17 is configured to receive the third target clock signal DLL180 and the fourth synchronous clock signal DL270, perform delay adjustment on the fourth synchronous clock signal DL270 based on the third target clock signal DLL180, and output the fourth target clock signal DLL270.
  • the mismatch between the first target clock signal DLL0 output by the first adjustable delay line 12 and the third target clock signal DLL180 output by the third adjustable delay line 15 is relatively small. Small, see Figure 3 above. That is to say, it can be considered that the phase difference between the first target clock signal DLL0 and the third target clock signal DLL180 is stable at 180 degrees, that is, the first target clock signal DLL0 and the third target clock signal DLL180 are mutually inverted signals.
  • the phase of the fourth synchronous clock signal DL270 directly output by the fourth adjustable delay line 16 may deviate due to mismatch and other reasons.
  • the second adjustment module 17 is introduced to perform delay adjustment on the fourth synchronous clock signal DL270, so that The phase difference between the third target clock signal DLL180 and the fourth target clock signal DLL270 is 90 degrees, which improves the phase deviation caused by delay line mismatch or preprocessing process.
  • the phase separation module 112 is also configured to perform frequency division and phase separation processing on the clock signal to be processed, and output the first clock signal clk0, the second clock signal clk90, and the third clock signal clk180 and the fourth clock signal clk270; wherein, the clock periods of the first clock signal clk0, the second clock signal clk90, the third clock signal clk180 and the fourth clock signal clk270 are the same, and the clock period of the first clock signal clk0 is the initial clock signal 2 times the clock period of CLK.
  • composition of the second adjustment module 17 is similar to that of the first adjustment module 14, and the following is a detailed description.
  • the second adjustment module 17 includes:
  • the second control module 171 is configured to receive the third target clock signal DLL180 and the fourth synchronous clock signal DL270, and output the second control code DLLCode2 ⁇ based on the phase difference between the third target clock signal DLL180 and the fourth synchronous clock signal DL270. N:0>;
  • the second delay chain 172 includes a plurality of second delay units and is configured to receive the second control code DLLCode2 ⁇ N:0> and the fourth synchronization clock signal DL270, based on the second control code DLLCode2 ⁇ N:0>, using a plurality of The second delay unit performs delay adjustment on the fourth synchronization clock signal DL270 and outputs the fourth target clock signal DLL270.
  • the second control code DLLCode2 ⁇ N:0> is converted based on the phase deviation between the fourth synchronization clock signal DL270 and the ideal situation (that is, the third target clock signal DLL180 is delayed by 90 degrees). Further, the second delay chain 172 can control the phase of the fourth synchronization clock signal DL270 to adjust forward or backward based on the second control code DLLCode2 ⁇ N:0> to obtain the fourth target clock signal DLL270 to ensure the third target clock.
  • the phase difference between signal DLL180 and fourth target clock signal DLL270 is 90 degrees.
  • FIG. 8 shows a second signal timing diagram provided by an embodiment of the present disclosure. Please refer to Figure 7 and Figure 8.
  • the second control module 171 includes:
  • the second pulse processing module 24 is configured to receive the third target clock signal DLL180 and the fourth synchronous clock signal DL270, and output the third pulse signal IN2 and the fourth pulse signal IN3; wherein, the third pulse signal IN2 and the fourth pulse signal IN3 Each includes 1 pulse, and the pulse width of the third pulse signal IN2 indicates the phase difference between the third target clock signal DLL180 and the fourth synchronous clock signal DL270, and the pulse width of the fourth pulse signal IN3 indicates the fourth synchronous clock signal.
  • the second time-to-digital conversion module 25 is configured to receive the third pulse signal IN2 and the third pulse signal IN2; convert the third pulse signal IN2, output the third conversion code TDCCode2 ⁇ N:0>, and convert the fourth pulse signal IN3 converts and outputs the fourth conversion code TDCCode3 ⁇ N:0>; among them, the third conversion code TDCCode2 ⁇ N:0> is used to characterize the width of the third pulse signal IN2, and the fourth conversion code TDCCode3 ⁇ N:0> is used To characterize the width of the fourth pulse signal IN3;
  • the second logic module 26 is configured to receive the third conversion code TDCCode2 ⁇ N:0> and the fourth conversion code TDCCode3 ⁇ N:0>, and to receive the fourth conversion code TDCCode3 ⁇ N:0> and the third conversion code TDCCode2 ⁇ N :0> performs subtraction operation and outputs the second control code DLLCode2 ⁇ N:0>.
  • the pulse width of the third pulse signal IN2 is greater than the pulse width of the fourth pulse signal IN3, it means that the fourth synchronous clock signal DL270 is too lagging; if the pulse width of the third pulse signal IN2 is less than the pulse width of the fourth pulse signal IN3, This indicates that the fourth synchronization clock signal DL270 is too advanced.
  • the value of the third conversion code TDCCode2 ⁇ N:0> corresponds to the pulse width of the third pulse signal IN2
  • the value of the fourth conversion code TDCCode3 ⁇ N:0> corresponds to the pulse width of the fourth pulse signal IN3.
  • the second control code DLLCode2 ⁇ N:0> can be obtained by subtracting the third conversion code TDCCode2 ⁇ N:0> from the fourth conversion code TDCCode3 ⁇ N:0>.
  • the second pulse processing module 24 includes:
  • the third pulse module 213 is configured to receive the third target clock signal DLL180 and the fourth synchronous clock signal DL270, perform XOR processing on the third target clock signal DLL180 and the fourth synchronous clock signal DL270 to obtain the third detection signal D2, and perform XOR processing on the third target clock signal DLL180 and the fourth synchronous clock signal DL270 to obtain the third detection signal D2.
  • the third detection signal D2 is subjected to pulse interception and broadening processing to obtain a third intermediate signal S2.
  • the third intermediate signal S2 and the third detection signal D2 are AND-processed to output a third pulse signal IN2; wherein the third detection signal D2 includes a plurality of pulse, and the pulse width of the third detection signal D2 indicates the phase difference between the third target clock signal DLL180 and the fourth synchronous clock signal DL270, the third intermediate signal S2 includes one pulse, and the pulse width of the third intermediate signal S2 is greater than the 3. Pulse width of detection signal D2;
  • the fourth pulse module 214 is configured to receive the inverted signal of the third target clock signal and the fourth synchronous clock signal DL270, and perform XOR processing on the inverted signal of the third target clock signal and the fourth synchronous clock signal DL270 to obtain the fourth Detect signal D3, perform pulse interception and broadening processing on the fourth detection signal D3 to obtain the fourth intermediate signal S3, perform AND processing on the fourth intermediate signal S3 and the fourth detection signal D3, and output the fourth pulse signal IN3; wherein, the fourth The detection signal D3 includes a plurality of pulses, and the pulse width of the fourth detection signal D3 indicates a phase difference between the inverted signal of the third target clock signal and the fourth synchronization clock signal DL270.
  • the fourth intermediate signal S3 includes one pulse. The pulse width of the fourth intermediate signal S3 is greater than the pulse width of the fourth detection signal D3.
  • the pulse of the third intermediate signal S2 covers at least one complete pulse in the third detection signal D2
  • the pulse of the fourth intermediate signal S3 covers at least one complete pulse in the fourth detection signal D3.
  • the third pulse module 213 and the fourth pulse module 214 can be combined using a variety of electrical devices. A specific example will be provided later in the embodiment of this disclosure.
  • the second time conversion module 25 includes:
  • the third conversion module 223 is configured to receive the third pulse signal IN2, sample and delay the third pulse signal IN2 to obtain a plurality of third sampling clock signals, and use the plurality of third sampling clock signals to convert the third pulse signal IN2 Perform sampling processing and output the third conversion code TDCCode2 ⁇ N:0>;
  • the fourth conversion module 224 is configured to receive the fourth pulse signal IN3, sample and delay the fourth pulse signal IN3 to obtain a plurality of fourth sampling clock signals, and use the plurality of fourth sampling clock signals to convert the fourth pulse signal IN3 Perform sampling processing and output the fourth conversion code TDCCode3 ⁇ N:0>.
  • the structures of the third conversion module and the fourth conversion module are similar and can be combined using a variety of electrical devices. A specific example will be provided later in the embodiment of this disclosure.
  • the first adjustment module is used to perform additional adjustment on the second synchronous clock signal DL90 output by the second adjustable delay line
  • the second adjustment module is used to adjust the fourth adjustable delay
  • the fourth synchronization clock signal DL270 outputted by the line is delayed adjusted, so it can ensure that the phase difference of the final four-phase clock signal is the preset value, improve the phase deviation caused by delay line mismatch or preprocessing process, and improve data sampling. Effect.
  • the structures of the first pulse module 211 to the fourth pulse module 214 are the same, and the structures of the first conversion module 221 to the fourth conversion module 224 are the same.
  • the following takes the first pulse module 211 and the first conversion module 221 as an example to provide possible circuit components.
  • the first pulse module 211 (comprising two parts 211a and 211b in Figure 9) includes: a first flip-flop 301, a second flip-flop 302, a first NOT gate 303, a fourth delay unit 304, An AND gate 305, a first XOR gate 306, a second AND gate 307; in the first pulse module 211, the first input end of the first XOR gate 306 receives the first target clock signal DLL0, and the first XOR gate The second input terminal of 306 receives the second synchronous clock signal DL90, and the output terminal of the first XOR gate 306 is used to output the first detection signal D0; the input terminal of the first flip-flop 301 receives the first power supply signal VDD, and the first trigger The clock terminal of the detector 301 is connected to the output terminal of the first XOR gate
  • the output terminal of a flip-flop 301 is connected, the second input terminal of the first AND gate 305 is connected to the output terminal of the fourth delay unit 304, and the output terminal of the first AND gate 305 is used to output the first intermediate signal S0; the second AND gate 305 is connected to the output terminal of the fourth delay unit 304.
  • the first input terminal of the gate 307 is connected to the output terminal of the first AND gate 305, the second input terminal of the second AND gate 307 is connected to the output terminal of the first XOR gate 306, and the output terminal of the second AND gate 307 is used to The first pulse signal IN0 is output.
  • the first detection signal D0 includes a plurality of pulses, and the pulse width of each pulse indicates the phase difference between the first target clock signal DLL0 and the second synchronization clock signal DL90;
  • An intermediate signal S0 only includes one pulse signal, and the pulse width of the first intermediate signal S0 is (pulse width of the first detection signal D0 + delay value ⁇ of the fourth delay unit 304), and at the same time, the pulse width of the first intermediate signal S0 covers And only covers one pulse of the first detection signal D0.
  • the first intermediate signal S0 and the first detection signal D0 are ANDed, leaving just one pulse of the first detection signal D0, thereby obtaining a phase that can indicate the phase between the first target clock signal DLL0 and the second synchronization clock signal DL90
  • the difference is the first pulse signal IN0.
  • Figure 9 only numbers each device in the first pulse module 211, that is, the dotted box portion.
  • the devices in the second to fourth pulse modules are not numbered. Please understand accordingly.
  • the first input terminal of the first XOR gate is the second synchronous clock signal DL90
  • the second input terminal of the first XOR gate is the second synchronous clock signal DL90.
  • Three target clock signals DLL180 (equivalent to the inverted signal of the first target clock signal)
  • the output end of the first XOR gate is used to output the second detection signal D1
  • the output end of the first AND gate is used to output the second intermediate signal S1
  • the output terminal of the second AND gate is used to output the first pulse signal IN0
  • the connection relationship of other devices is the same as that of the first pulse module 211.
  • the first input terminal of the first exclusive OR gate is the third target clock signal DLL180
  • the second input terminal of the first exclusive OR gate is the third target clock signal DLL180.
  • Four synchronous clock signals DL270 the output terminal of the first XOR gate is used to output the third detection signal D2
  • the output terminal of the first AND gate is used to output the third intermediate signal S2
  • the output terminal of the second AND gate is used to output the third detection signal D2.
  • the connection relationship of the other components is the same as that of the first pulse module 211.
  • the first input terminal of the first XOR gate is the fourth synchronous clock signal DL270
  • the second input terminal of the first XOR gate is the fourth synchronous clock signal DL270.
  • a target clock signal DLL0 (equivalent to the inverted signal of the third target clock signal)
  • the output terminal of the first XOR gate is used to output the fourth detection signal D3
  • the output terminal of the first AND gate is used to output the fourth intermediate signal S3
  • the output terminal of the second AND gate is used to output the fourth pulse signal IN3, and the connection relationship of other components is the same as that of the first pulse module 211.
  • the first conversion code TDCCode0 ⁇ N:0>, the second conversion code TDCCode1 ⁇ N:0>, the third conversion code TDCCode2 ⁇ N:0>, and the fourth conversion code TDCCode3 ⁇ N:0> are all Each includes a multi-bit signal. Taking the first conversion code TDCCode0 ⁇ N:0> as an example, it includes sub-signals TDCcode0: ⁇ 0>, TDCcode0: ⁇ 1>...TDCcode0 ⁇ N>.
  • the first conversion module 221 includes a third flip-flop 308, a third delay chain 309, and a plurality of fourth flip-flops 310; wherein, the input end of the third flip-flop 308 receives the second power signal VDD, and the third flip-flop 308 receives the second power signal VDD.
  • the clock terminal of the third flip-flop 308 receives the first pulse signal IN0, and the output terminal of the third flip-flop 308 is connected to the input terminal of the third delay chain 309; all the input terminals of the fourth flip-flop 310 are used to receive the first pulse.
  • the third delay chain 309 includes a plurality of third delay units arranged in series.
  • the clock terminal of a fourth flip-flop 310 is connected correspondingly to the output terminal of a third delay unit.
  • the output terminal of a fourth flip-flop 310 outputs One bit signal of the first conversion code TDCCode0 ⁇ N:0>.
  • the output signal of the third flip-flop 308 is recorded as signal Clk_start_0. See FIG. 11 , which shows a signal timing diagram 3 provided by an embodiment of the present disclosure. As shown in Figure 11, at the rising edge of the first pulse signal IN0, the signal Clk_start_0 changes from a low level state to a high level state.
  • the signal Clk_start_0 sequentially obtains the signal Clk_start0 (used as The clock signal of the first fourth flip-flop 310), the signal Clk_start1 (used as the clock signal of the second fourth flip-flop 310)...the signal Clk_startN (used as the clock signal of the last fourth flip-flop 310), using
  • the signal Clk_start0 samples the first pulse signal IN0 to obtain TDC0code ⁇ 0>.
  • the signal Clk_start1 is used to sample the first pulse signal IN0 to obtain TDCcode0 ⁇ 1>...
  • the signal Clk_startN is used to sample the first pulse signal IN0 to obtain TDCcode0 ⁇ N>. , thereby obtaining the first conversion code TDCCode0 ⁇ N:0>.
  • the clock terminal of the third flip-flop and the input terminals of all fourth flip-flops are used to receive the second pulse signal IN1, and the output terminal of a fourth flip-flop outputs the second pulse signal IN1.
  • the clock terminal of the third flip-flop and the input terminals of all fourth flip-flops are used to receive the third pulse signal IN2, and the output terminal of one fourth flip-flop outputs the third conversion code TDCCode2 ⁇ N: A bit signal of 0>.
  • the clock terminal of the third flip-flop and the input terminals of all fourth flip-flops are used to receive the fourth pulse signal IN3, and the output terminal of one fourth flip-flop outputs the fourth conversion code TDCCode3 ⁇ N: A bit signal of 0>.
  • the phase difference between the first target clock signal DLL0 and the second synchronous clock signal DL90 is converted to obtain the first conversion code TDCCode0 ⁇ N:0>, and the inverse of the second synchronous clock signal DL90 and the first target clock signal DLL0 is obtained.
  • the phase difference between the phase signals is converted to obtain the second conversion code TDCCode1 ⁇ N:0>
  • the phase difference between the third target clock signal DLL180 and the fourth synchronous clock signal DL270 is converted to obtain the third conversion code TDCCode2 ⁇ N:0 >
  • convert the phase difference between the fourth synchronization clock signal DL270 and the inverted signal of the third target clock signal to obtain the fourth conversion code TDCCode3 ⁇ N:0>.
  • first delay chain 142 includes a plurality of first delay units arranged in series
  • second delay chain 172 includes a plurality of second delay units
  • first delay unit and the second delay chain 172 in the first delay chain 142 The second delay unit in and the third delay unit in the third delay chain 309 correspond to the same.
  • the i-th bit sub-signal of the first control code DLLCode1 ⁇ N:0> is used to control the i-th first delay unit to be in the on state or In the off state
  • the i-th sub-signal of the second control code DLLCode2 ⁇ N:0> is used to control the i-th second delay unit to be in the on state or off state
  • the first delay chain 142 is specifically configured to use the first delay unit in the on state to delay the second synchronization clock signal DL90 and output the second target clock signal DLL90;
  • the second delay chain 172 is specifically configured to use the second delay unit in the on state to delay the fourth synchronization clock signal DL270 and output the fourth target clock signal DLL270.
  • the delay value of the delay chain can be adjusted by reducing or increasing the number of turned-on delay units, and the target clock signal output by it can be processed in advance or delayed.
  • the first a-bit sub-signal of the first control code DLLCode1 ⁇ N:0> is in the first state
  • the last (A-a)-bit signal of the first control code DLLCode1 ⁇ N:0> is in the second state.
  • the first b-bit sub-signals of the second control code DLLCode2 ⁇ N:0> are in the first state, and the last (B-b) bit signals of the second control code DLLCode2 ⁇ N:0> are in the second state;
  • A, B, a, b are all positive integers, and a is less than or equal to A, A refers to the total number of sub-signal bits in the first control code, b is less than or equal to B, and B refers to the total number of sub-signal bits in the second control code.
  • the first delay chain 142 is specifically configured to use the 1st to a-th first delay units to delay the second synchronization clock signal DL90, and determine the output signal of the a-th first delay unit as the second target clock. signalDLL90;
  • the second delay chain 172 is specifically configured to use the first to b-th second delay units to delay the fourth synchronization clock signal DL270, and determine the output signal of the b-th second delay unit as the fourth target clock.
  • Signal DLL270 The second delay chain 172 is specifically configured to use the first to b-th second delay units to delay the fourth synchronization clock signal DL270, and determine the output signal of the b-th second delay unit as the fourth target clock.
  • Signal DLL270 Signal
  • the delay locked loop 10 introduces the first adjustment module 14 and the second adjustment module 17 the phase deviation caused by the delay line mismatch or the preprocessing process can be improved.
  • the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270 are used for data after passing through the corresponding signal transmission paths. Sampling processing. Specifically, the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270 arrive at the data selection module (Mux) after passing through the corresponding signal transmission path. The data selection module The four-phase target clock signal is used to sample and select the data signal DQ for output to obtain the target data signal.
  • a certain number of buffers can be set on each signal transmission path to increase the driving capability of the signal, and the number of buffers on the four signal transmission paths is the same.
  • the delay locked loop 10 also includes:
  • the feedback module (including the fifth adjustable delay line 411 and the copy delay module 412) is configured to receive the first clock signal clk0 and output an analog clock signal, and the analog clock signal is used to simulate the first target clock signal DLL0 after passing through the signal transmission path waveform;
  • the detection module 42 is configured to receive the first clock signal clk0 and the analog clock signal, perform phase detection on the first clock signal clk0 and the analog clock signal, and obtain a phase detection signal;
  • the parameter adjustment module 43 is configured to receive a phase detection signal and output a delay line control signal based on the phase detection signal;
  • the first adjustable delay line 12 is specifically configured to receive a delay line control signal, adjust and transmit the first clock signal clk0 based on the delay line control signal, and output the first target clock signal DLL0;
  • the second adjustable delay line 13 is specifically configured to receive a delay line control signal, adjust and transmit the second clock signal clk90 based on the delay line control signal, and output the second synchronous clock signal DL90.
  • the third adjustable delay line 15 is specifically configured to receive the delay line control signal, adjust and transmit the third clock signal clk180 based on the delay line control signal, and output the third target clock signal DLL180; the fourth adjustable delay line 16. Specifically configured to receive a delay line control signal, adjust and transmit the fourth clock signal clk270 based on the delay line control signal, and output the fourth synchronous clock signal DL270.
  • the waveform of the first target clock signal DLL0 when it reaches the data selection module needs to be consistent with the waveform of the first clock signal clk0, so a feedback adjustment mechanism needs to be constructed.
  • the first clock signal clk0 generates an analog clock signal after passing through the feedback module 151. Since the analog clock signal can simulate the waveform of the first target clock signal DLL0 when it reaches the data selection module, according to the analog clock signal and the first clock signal The difference between clk0 is used to adjust the delay line control signal so as to adjust the operating parameters of the first adjustable delay line.
  • the waveform of the analog clock signal and the waveform of the first target clock signal DLL0 after passing through the signal transmission path are not exactly the same.
  • the analog clock signal can be divided down to reduce the update frequency of the delay line adjustment signal, avoid signal jitter caused by signal glitches, and reduce power consumption.
  • the feedback module includes:
  • the fifth adjustable delay line 411 is configured to receive the first clock signal clk0 and the delay line control signal, adjust and transmit the first clock signal clk0 based on the delay line control signal, and output a replica clock signal; wherein, the fifth adjustable delay The line has the same structure as the first adjustable delay line, and the replica clock signal is used to simulate the waveform of the first target clock signal DLL0;
  • the replica delay module 412 is configured to receive the replica clock signal, perform delay processing on the replica clock signal, and output an analog clock signal; wherein the replica delay module is configured to simulate the delay of the signal transmission path.
  • the fifth adjustable delay line 411 is used to copy the processing process of the first adjustable delay line
  • the copy delay module 412 is at least configured to copy the delay when the first target clock signal DLL0 is transmitted through the signal transmission path, thereby forming feedback Adjustment closed loop.
  • the delay-locked loop in order to reduce the signal deviation caused by layout mismatch (Layout Mismatch), process error, voltage, temperature (Process Voltage Temperature, PVT), etc., first of all, through the first target
  • the rising edge information of the clock signal, the second synchronous clock signal, the third target clock signal and the fourth synchronous clock signal are logically processed to form the first pulse signal IN0 ⁇ the fourth pulse signal IN3, and the first pulse signal IN0 ⁇ the fourth pulse signal IN3 are formed.
  • the four pulse signals IN3 are respectively input to four independent time-to-digital conversion modules (i.e., the first conversion module to the fourth conversion module), corresponding to the first conversion code TDCcode0 ⁇ N:0> ⁇ the fourth conversion code TDCcode3 ⁇ N:0.
  • FIG. 12 shows a schematic structural diagram of a clock synchronization circuit 50 provided by an embodiment of the present disclosure.
  • the clock synchronization circuit 50 includes the aforementioned delay locked loop 10 and data selection module 51, and a signal transmission path is set between the delay locked loop 10 and the data selection module 51; wherein,
  • the delay locked loop 10 is configured to receive an initial clock signal and output a first target clock signal DLL0, a second target clock signal DLL90, a third target clock signal DLL180 and a fourth target clock signal DLL270; wherein the first target clock signal DLL0 , the phases of the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270 are sequentially different by 90 degrees;
  • the data selection module 51 is configured to respectively receive the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270 via corresponding signal transmission paths, and use the first target clock signal DLL0, the second target clock signal DLL90, the third target clock signal DLL180 and the fourth target clock signal DLL270 sample and selectively output the data signal DQ to obtain the target data signal and perform selection and output processing to obtain the target data signal.
  • the same number of buffers is set for each signal transmission path to achieve signal delay and drive enhancement.
  • two buffers are provided for each signal transmission path as an example, but in actual application, it can be more or less.
  • the delay locked loop 10 is provided with a first adjustment module on the output side of the second adjustable delay line, and a second adjustment module is provided on the output side of the fourth adjustable delay line. module, and then use the first adjustment module to perform delay adjustment on the signal output by the second adjustable delay line, and use the second adjustment module to perform delay adjustment on the signal output by the fourth adjustable delay line, thus ensuring the final four-phase
  • the phase difference of the clock signal is a preset value, which improves the phase deviation caused by delay line mismatch or preprocessing process and improves the effect of data sampling.
  • FIG. 13 shows a schematic structural diagram of a memory 60 provided by an embodiment of the present disclosure.
  • the memory 60 at least includes the aforementioned delay locked loop 10 .
  • the memory complies with at least one of the following specifications: DDR3, DDR4, DDR5, DDR6, LPDDR3, LPDDR4, LPDDR5, LPDDR6.
  • Embodiments of the present disclosure provide a delay locked loop and a memory.
  • the delay locked loop includes: a preprocessing module configured to receive an initial clock signal, preprocess the initial clock signal, and output a second A clock signal and a second clock signal; the first adjustable delay line is configured to receive the first clock signal, adjust and transmit the first clock signal, and output the first target clock signal; the second adjustable delay line is configured to Receive the second clock signal, adjust and transmit the second clock signal, and output the second synchronous clock signal; the first adjustment module is configured to perform delay adjustment on the second synchronous clock signal based on the first target clock signal, and output the second target Clock signal; wherein the phase difference between the first target clock signal and the second target clock signal is a preset value. In this way, the first adjustment module can correct the phase difference between the first synchronization clock signal and the second target clock signal, and improve the phase deviation between the target clock signals.

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Abstract

本公开实施例提供了一种延迟锁相环和存储器，该延迟锁相环包括：预处理模块，配置为接收初始时钟信号，对初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；第一可调延迟线，配置为接收第一时钟信号，对第一时钟信号进行调整及传输，输出第一目标时钟信号；第二可调延迟线，配置为接收第二时钟信号，对第二时钟信号进行调整及传输，输出第二同步时钟信号；第一调整模块，配置为基于第一目标时钟信号对第二同步时钟信号进行延迟调整，输出第二目标时钟信号。

Description

一种延迟锁相环和存储器
相关申请的交叉引用
本公开基于申请号为202211006012.6、申请日为2022年08月22日、发明名称为“一种延迟锁相环和存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体存储器技术领域，尤其涉及一种延迟锁相环和存储器。
背景技术
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，延迟锁相环需要对四相位时钟信号(即4个相位依次相差90度的时钟信号)进行相位同步和锁定，得到相位差为90度的一组目标时钟信号，以便对数据信号DQ进行采样处理。然而，由于延迟锁相环中的器件存在错配或性能偏差，所以其最终产生的目标时钟信号之间的相位差可能存在偏移，降低数据采样效果。
发明内容
本公开提供了一种延迟锁相环和存储器，能够减少延迟锁相环输出的目标时钟信号的相位偏差。
本公开的技术方案是这样实现的：
第一方面，本公开实施例提供了一种延迟锁相环，所述延迟锁相环包括：
预处理模块，配置为接收初始时钟信号，对所述初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；
第一可调延迟线，配置为接收所述第一时钟信号，对所述第一时钟信号进行调整及传输，输出第一目标时钟信号；
第二可调延迟线，配置为接收所述第二时钟信号，对所述第二时钟信号进行调整及传输，输出第二同步时钟信号；
第一调整模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，基于所述第一目标时钟信号对所述第二同步时钟信号进行延迟调整，输出第二目标时钟信号；
其中，所述第一目标时钟信号和所述第二目标时钟信号之间的相位差为预设值。
在一些实施例中，所述预处理模块包括：接收模块，配置为接收所述初始时钟信号，输出待处理时钟信号；其中，所述待处理时钟信号的时钟周期与所述初始时钟信号的时钟周期相同；分相模块，配置为接收所述待处理时钟信号，对所述待处理时钟信号进行分频和分相处理，输出所述第一时钟信号和所述第二时钟信号；其中，所述第一时钟信号和所述第二时钟信号的时钟周期相同，且所述第一时钟信号的时钟周期是所述初始时钟信号的时钟周期的2倍。
在一些实施例中，所述第一调整模块，包括：第一控制模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，基于所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，输出第一控制码；第一延迟链，包括多个第一延迟单元，配置为接收所述第一控制码和所述第二同步时钟信号；基于所述第一控制码，利用多个第一延迟单元对所述第二同步时钟信号的进行延迟调整，输出所述第二目标时钟信号。
在一些实施例中，所述第一控制模块，包括：第一脉冲处理模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，输出第一脉冲信号和第二脉冲信号；其中，所述第一脉冲信号和所述第二脉冲信号均各自包括1个脉冲，且所述第一脉冲信号的脉冲宽度指示所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，所述第二脉冲信号的脉冲宽度指示所述第二同步时钟信号和所述第一目标时钟信号的反相信号之间的相位差；第一时间数字转换模块，配置为接收所述第一脉冲信号和所述第二脉冲信号；对所述第一脉冲信号进行转换，输出第一转换码，并对所述第二脉冲信号进行转换，输出第二转换码；其中，所述第一转换码用于表征所述第一脉冲信号的宽度，所述第二转换码用于表征所述第二脉冲信号的宽度；第一逻辑模块，配置为接收所述第一转换码和所述第二转换码，对所述第二转换码和所述第一转换码进行减法运算，输出所述第一控制码。
在一些实施例中，第一脉冲处理模块，包括：所述第一脉冲模块，配置为接收所述第一目标时钟信号和第二同步时钟信号，对所述第一目标时钟信号和所述第二同步时钟信号进行异或处理得到第一检测信号，对所述第一检测信号进行脉冲截取及拓宽处理得到第一中间信号，对所述第一中间信号和所述第一检测信号进行与处理，输出所述第一脉冲信号；其中，所述第一检测信号包括多个脉冲，且所述第一检测信号的脉冲宽度指示所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，所述第一中间信号包括一个脉冲，第一中间信号的脉冲宽度大于所述第一检测信号的脉冲宽度；所述第二脉冲模块，配置为接收所述第一目标时钟信号的反相信号和第二同步时钟信号，对所述第一目标时钟信号的反相信号和所述第二同步时钟信号进行异或处理得到第二检测信号，对所述第二检测信号进行脉冲截取及拓宽处理得到第二中间信号，对所述第二中间信号和所述第二检测信号进行与处理，输出所述第二脉冲信号；其中，所述第二检测信号包括多个脉冲，且所述第二检测信号的脉冲宽度指示所述第一目标时钟信号的反相信号和所述第二同步时钟信号之间的相位差，所述第二中间信号包括一个脉冲，第二中间信号的脉冲宽度大于所述第二检测信号的脉冲宽度。
在一些实施例中，所述第一时间转换模块包括：第一转换模块，配置为接收第一脉冲信号，利用所述第一脉冲信号进行采样和延迟处理以得到多个第一采样时钟信号，利用多个所述第一采样时钟信号对所述第一脉冲信号进行采样处理，输出所述第一转换码；第二转换模块，配置为接收第二脉冲信号，利用所述第二脉冲信号进行采样和延迟处理以得到多个第二采样时钟信号，利用多个所述第二采样时钟信号对所述第二脉冲信号进行采样处理，输出所述第二转换码。
在一些实施例中，所述预处理模块，还配置为对所述初始时钟信号进行预处理，输出第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；所述延迟锁相环还包括：第三可调延迟线，配置为接收所述第三时钟信号，对所述第三时钟信号进行调整及传输，输出第三目标时钟信号；其中，所述第一目标时钟信号和所述第三目标时钟信号的相位差为180度；第四可调延迟线，配置为接收所述第四时钟信号，对所述第四时钟信号进行调整及传输，输出第四同步时钟信号；第二调整模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，基于所述第三目标时钟信号对所述第四同步时钟信号进行延迟调整，输出第四目标时钟信号；其中，所述第一目标时钟信号、所述第二目标时钟信号、所述第三目标时钟信号和所述第四目标时钟信号之间的相邻相位差均为90度。
在一些实施例中，所述分相模块，还配置为对所述待处理时钟信号进行分频和分相处理，输出第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的时钟周期相同，且所述第一时钟信号的时钟周期是所述初始时钟信号的时钟周期的2倍。
在一些实施例中，所述第二调整模块，包括：第二控制模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，基于所述第三目标时钟信号和所述第四同步时钟信号之间的相位差，输出第二控制码；第二延迟链，包括多个第二延迟单元，配置为接收所述第二控制码和所述第四同步时钟信号，基于所述第二控制码，利用多个第二延迟单元对所述第四同步时钟信号的进行延迟调整，输出所述第四目标时钟信号。
在一些实施例中，所述第二控制模块，包括：第二脉冲处理模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，输出第三脉冲信号和第四脉冲信号；其中，所述第三脉冲信号和所述第四脉冲信号均各自包括1个脉冲，且所述第三脉冲信号的脉冲宽度指示所述第 三目标时钟信号和所述第四同步时钟信号之间的相位差，所述第四脉冲信号的脉冲宽度指示所述第四同步时钟信号和所述第三目标时钟信号的反相信号之间的相位差；第二时间数字转换模块，配置为接收所述第三脉冲信号和所述第三脉冲信号；对所述第三脉冲信号进行转换，输出第三转换码，并对所述第四脉冲信号进行转换，输出第四转换码；其中，所述第三转换码用于表征所述第三脉冲信号的宽度，所述第四转换码用于表征所述第四脉冲信号的宽度；第二逻辑模块，配置为接收所述第三转换码和所述第四转换码，对所述第四转换码和所述第三转换码进行减法运算，输出所述第二控制码。
在一些实施例中，所述第二脉冲处理模块，包括：所述第三脉冲模块，配置为接收所述第三目标时钟信号和第四同步时钟信号，对所述第三目标时钟信号和所述第四同步时钟信号进行异或处理得到第三检测信号，对所述第三检测信号进行脉冲截取及拓宽处理得到第三中间信号，对所述第三中间信号和所述第三检测信号进行与处理，输出所述第三脉冲信号；其中，所述第三检测信号包括多个脉冲，且所述第三检测信号的脉冲宽度指示所述第三目标时钟信号和所述第四同步时钟信号之间的相位差，所述第三中间信号包括一个脉冲，且所述第三中间信号的脉冲宽度大于所述第三检测信号的脉冲宽度；所述第四脉冲模块，配置为接收所述第三目标时钟信号的反相信号和第四同步时钟信号，对所述第三目标时钟信号的反相信号和所述第四同步时钟信号进行异或处理得到第四检测信号，对所述第四检测信号进行脉冲截取及拓宽处理得到第四中间信号，对所述第四中间信号和所述第四检测信号进行与处理，输出所述第四脉冲信号；其中，所述第四检测信号包括多个脉冲，且所述第四检测信号的脉冲宽度指示所述第三目标时钟信号的反相信号和所述第四同步时钟信号之间的相位差，所述第四中间信号包括一个脉冲，且所述第四中间信号的脉冲宽度大于所述第四检测信号的脉冲宽度。
在一些实施例中，所述第二时间转换模块包括：第三转换模块，配置为接收第三脉冲信号，将所述第三脉冲信号进行采样和延迟处理以得到多个第三采样时钟信号，利用多个所述第三采样时钟信号对所述第三脉冲信号进行采样处理，输出所述第三转换码；第四转换模块，配置为接收第四脉冲信号，将所述第四脉冲信号进行采样和延迟处理以得到多个第四采样时钟信号，利用多个所述第四采样时钟信号对所述第四脉冲信号进行采样处理，输出所述第四转换码。
在一些实施例中，所述第一脉冲模块包括：第一触发器、第二触发器、第一非门、第四延迟单元、第一与门、第一异或门、第二与门；所述第二脉冲模块、所述第三脉冲模块、所述第四脉冲模块与所述第一脉冲模块的结构对应相同；其中，在所述第一脉冲模块中，所述第一异或门的第一输入端接收所述第一目标时钟信号，所述第一异或门的第二输入端接收所述第二同步时钟信号，所述第一异或门的输出端用于输出所述第一检测信号；所述第一触发器的输入端接收第一电源信号，所述第一触发器的时钟端与所述第一异或门的输出端连接；所述第一非门的输入端与所述第一异或门的输出端连接，所述第二触发器的输入端接收地信号，所述第二触发器的输出端与所述第一非门的输出端连接；所述第四延迟单元的输入端与所述第二触发器的输出端连接，所述第一与门的第一输入端与所述第一触发器的输出端连接，所述第一与门的第二输入端与所述第四延迟单元的输出端连接，所述第一与门的输出端用于输出所述第一中间信号；所述第二与门的第一输入端与所述第一与门的输出端连接，所述第二与门的第二输入端与所述第一异或门的输出端连接，所述第二与门的输出端用于输出所述第一脉冲信号。
在一些实施例中，所述第一转换码、所述第二转换码、所述第三转换码、所述第四转换码均各自包括多位子信号；所述第一转换模块包括第三触发器、第三延迟链、多个第四触发器，且所述第二转换模块、所述第三转换模块、所述第四转换模块均与所述第一转换模块的结构对应相同；其中，在所述第一转换模块中，所述第三触发器的输入端接收第二电源信号，所述第三触发器的时钟端接收所述第一脉冲信号，所述第三触发器的输出端与所述第三延迟链的输入端连接；所有的第四触发器的输入端均用于接收所述第一脉冲信号；所述第三延迟链包括串联设置的多个第三延迟单元，一个所述第四触发器的时钟端与一个第三延迟单元的输出端对应连接，一个所述第四触发器的输出端输出所述第一转换码的一位子信号。
在一些实施例中，所述第一延迟链包括多个串联设置的第一延迟单元、所述第二延迟链包括多个第二延迟单元；所述第一延迟链中的第一延迟单元、所述第二延迟链中的第二延迟单元、所述第三延迟链中的第三延迟单元对应相同。
在一些实施例中，所述第一控制码的第i位子信号用于控制第i个第一延迟单元处于开启状 态或者关闭状态，所述第二控制码的第i位子信号用于控制第i个第二延迟单元处于开启状态或者关闭状态；所述第一延迟链，具体配置为利用处于开启状态的所述第一延迟单元对所述第二同步时钟信号进行延迟，输出所述第二目标时钟信号；所述第二延迟链，具体配置为利用处于开启状态的所述第二延迟单元对所述第四同步时钟信号进行延迟，输出所述第四目标时钟信号。
在一些实施例中，所述第一控制码的前a位子信号为第一状态，所述第一控制码的后(A-a)位子信号为第二状态；所述第二控制码的前b位子信号为第一状态，所述第二控制码的后(B-b)位子信号为第二状态；A、B、a、b均为正整数，且a小于或等于A，A是指第一控制码中的子信号的总位数，b小于或等于B，B是指第二控制码中的子信号的总位数；所述第一延迟链，具体配置为利用第1个～第a个所述第一延迟单元对所述第二同步时钟信号进行延迟处理，并将第a个所述第一延迟单元的输出信号确定为所述第二目标时钟信号；所述第二延迟链，具体配置为利用第1个～第b个所述第二延迟单元对所述第四同步时钟信号进行延迟处理，并将第b个所述第二延迟单元的输出信号确定为所述第四目标时钟信号。
在一些实施例中，所述第一目标时钟信号、所述第二目标时钟信号、所述第三目标时钟信号和所述第四目标时钟信号在经过对应的信号传输路径后用于数据采样处理；所述延迟锁相环还还包括：反馈模块，配置为接收所述第一时钟信号，输出模拟时钟信号，且所述模拟时钟信号用于模拟所述第一目标时钟信号经过所述信号传输路径后的波形；检测模块，配置为接收所述第一时钟信号和所述模拟时钟信号，对所述第一时钟信号和所述模拟时钟信号进行相位检测，得到相位检测信号；调参模块，配置为接收所述相位检测信号，基于所述相位检测信号输出延迟线控制信号；所述第一可调延迟线，具体配置为接收所述延迟线控制信号，基于所述延迟线控制信号对所述第一时钟信号进行调整及传输，输出所述第一目标时钟信号；所述第二可调延迟线，具体配置为接收所述延迟线控制信号，基于所述延迟线控制信号对所述第二时钟信号进行调整及传输，输出所述第二同步时钟信号。
在一些实施例中，所述反馈模块包括：第五可调延迟线，配置为接收所述第一时钟信号和所述延迟线控制信号，基于所述延迟线控制信号对所述第一时钟信号进行调整及传输，输出复制时钟信号；其中，所述第五可调延迟线与所述第一可调延迟线的结构相同，所述复制时钟信号用于模拟所述第一目标时钟信号的波形；复制延迟模块，配置为接收所述复制时钟信号，对所述复制时钟信号进行延迟处理，输出模拟时钟信号；其中，所述复制延迟模块配置为模拟所述信号传输路径的延时。
第二方面，本公开实施例提供了一种存储器，所述存储器至少包括如第一方面所述的延迟锁相环。
本公开实施例提供了一种延迟锁相环和存储器，该延迟锁相环包括：该延迟锁相环包括：预处理模块，配置为接收初始时钟信号，对初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；第一可调延迟线，配置为接收第一时钟信号，对第一时钟信号进行调整及传输，输出第一目标时钟信号；第二可调延迟线，配置为接收第二时钟信号，对第二时钟信号进行调整及传输，输出第二同步时钟信号；第一调整模块，配置为基于第一目标时钟信号对第二同步时钟信号进行延迟调整，输出第二目标时钟信号；其中，第一目标时钟信号和第二目标时钟信号之间的相位差为预设值。这样，通过第一调整模块可以对第一同步时钟信号和第二目标时钟信号之间的相位差进行校正，改善目标时钟信号之间的相位偏差。
附图说明
图1为一种延迟锁相环的结构示意图；
图2为一种信号时序示意图一；
图3为一种信号时序示意图二；
图4为本公开实施例提供的一种延迟锁相环的结构示意图一；
图5为本公开实施例提供的一种延迟锁相环的结构示意图二；
图6为本公开实施例提供的一种信号时序示意图一；
图7为本公开实施例提供的一种延迟锁相环的结构示意图三；
图8为本公开实施例提供的一种信号时序示意图二；
图9为本公开实施例提供的一种延迟锁相环的局部结构示意图一；
图10为本公开实施例提供的一种延迟锁相环的局部结构示意图二；
图11为本公开实施例提供的一种信号时序示意图三；
图12为本公开实施例提供的一种时钟同步电路的结构示意图；
图13为本公开实施例提供的一种存储器的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
动态随机存取存储器(Dynamic Random Access Memory，DRAM)
同步动态随机存取存储器(Synchronous Dynamic Random Access Memory，SDRAM)
双倍数据速率内存(Double Data Rate SDRAM，DDR)
低功率DDR(Low Power DDR，LPDDR)
第n代DDR标准(DDRn Specification，DDRn)，例如DDR3、DDR4、DDR5、DDR6
第n代LPDDR标准(LPDDRn Specification，LPDDRn)，例如LPDDR3、LPDDR4、LPDDR5、LPDDR6
目前，存储器逐渐向着高速化发展。以DDR5为例，由于其速度提升和工艺的限制，接口处的高速时钟信号需要在内部转为低速时钟信号。举例来说，存储器中的延迟锁相环(Delay Locked Loop，DLL)需要通过大量的反相器链来动态调整时钟信号的延迟以及执行延迟匹配处理。如果在高频速度下，这些反相器链可能会造成信号偏差(Jitter)的大量累计，最终导致信号丢失。因此，在DDR5的高频速度下，为了保证信号质量，来自于外部的初始时钟信号CLK在内部会分频/分相得到四相位时钟信号，四相位时钟信号分别送入延迟锁相环进行相位同步及锁定，然后通过数据选择模块(Mux)利用调整后的四相位时钟信号对数据信号DQ进行采样及选择输出，得到目标数据信号。
参见图1，其示出了一种延迟锁相环的结构示意图。参见图2，其示出了一种信号时序示意图一。如图1和图2所示，初始时钟信号CLK经过接收模块进入延迟锁相环，然后被分相模块处理为四相位时钟信号(即clk0、clk90、clk180和clk270)，且四相位时钟信号的频率降低为初始时钟信号CLK的一半；其次，通过4条可调延迟线分别对四相位时钟信号进行延迟以及占空比方面的调整。这样，在延迟锁相环进行相位锁定之后，获得四相位的目标时钟信号(即DLL0、DLL90、DLL180和DLL270)，且目标时钟信号DLL0、DLL90、DLL180和DLL270经由相应的信号传输路径传输到数据选择模块，数据选择模块将四相位的目标时钟信号DLL0、DLL90、DLL180和DLL270转化为数据采样时钟信号DQS，后续利用数据采样时钟信号DQS对数据信号DQ进行采样得到目标数据信号。另外，延迟锁相环还包括第5条可调延迟线、复制延迟模块、检测模块和调参模块，第5条可调延迟线和复制延迟模块构成回路，第5条可调延迟线接收时钟信号clk0，复制延迟模块输出模拟时钟信号，模拟时钟信号用于模拟目标时钟信号DLL0传输到数据选择模块时的波形，检测模块对模拟时钟信号和时钟信号clk0之间的相位差进行检测，调参模块根据检测模块的检测结果输出延迟线控制信号，延迟线控制信号用于控制所有可 调延迟线的工作参数。这样，延迟锁相环存在闭环反馈机制，保证最终处理得到的目标时钟信号DLL0/DLL90/DLL180/DLL270符合要求。
由上述可知，初始时钟信号CLK分为四路进入延迟锁相环，为了保证初始时钟信号CLK的上升沿和下降沿信息不被丢失，所以延迟锁相环内部需要准备4路主要的可调延迟线，以便对四相位时钟信号进行相位同步和锁定处理，最终传输到数据选择模块(Mux)。然而，由于4条可调延迟线存在错配，同时转换模块输出的四相位时钟信号(clk0、clk90、clk180和clk270)本身也存在一定的误差，所以目标时钟信号DLL0/DLL90/DLL180/DLL270之间也存在一定的相位偏差。参见图3，其示出了一种信号时序示意图二。如图3所示，最终送入数据选择模块的目标时钟信号DLL0DLL90/DLL180/DLL270之间的相位差(体现为T1、T2、T3和T4)并不相同，此时数据采样时钟信号DQS中脉冲周期(体现为t1、t2)的长度并不相同，即数据采样时钟信号的有效窗口较小，限制了存储器性能的提高。
基于此，本公开实施例提供了一种延迟锁相环，用于改善延迟锁相环输出的时钟信号之间的相位偏差，以便提高存储器的性能得到进一步提高。
下面将结合附图对本公开各实施例进行详细说明。
在本公开的一实施例中，参见图4，其示出了本公开实施例提供的一种延迟锁相环10的结构示意图一。如图4所示，延迟锁相环10包括：
预处理模块11，配置为接收初始时钟信号，对初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；
第一可调延迟线12，配置为接收第一时钟信号，对第一时钟信号进行调整及传输，输出第一目标时钟信号；
第二可调延迟线13，配置为接收第二时钟信号，对第二时钟信号进行调整及传输，输出第二同步时钟信号；
第一调整模块14，配置为接收第一目标时钟信号和第二同步时钟信号，基于第一目标时钟信号对第二同步时钟信号进行延迟调整，输出第二目标时钟信号，且第一目标时钟信号和第二目标时钟信号之间的相位差为预设值。
需要说明的是，本公开实施例的延迟锁相环10可以应用但不限于存储器，例如DRAM、SDRAM等。另外，在其他模拟电路/数字电路中，均可通过本公开实施例提供的延迟锁相环10来产生一组不同相位的时钟信号。
在延迟锁相环10中，通过第一可调延迟线12和第二可调延迟线13分别获得第一目标时钟信号和第二同步时钟信号，然后利用第一调整模块14对第二同步时钟信号进行延迟调整以得到第二目标时钟信号，保证第一目标时钟信号和第二目标时钟信号之间的相位差为预设值。这样，通过引入第一调整模块14，可以对第一同步时钟信号和第二目标时钟信号之间的相位差进行校正，改善由于延迟线不匹配或者预处理过程而产生的相位偏差。
需要说明的是，预设值可以根据实际应用场景进行设定，例如180度、90度。另外，本公开实施例对于相位差的限定均允许一定的误差，即第一目标时钟信号和第二目标时钟信号之间的相位差在误差允许的范围内为预设值。如无特别说明，后续关于相位差、时钟周期的限定均可进行相应理解。
本公开实施例后续以预设值为90度进行说明，此时第一目标时钟信号可以表示为DLL0，第二目标时钟信号可以表示为DLL90，其他情况请参照理解。
在一些实施例中，参见图5，其示出了本公开实施例提供的一种延迟锁相环10的结构示意图二。如图5所示，预处理模块11包括：
接收模块111，配置为接收初始时钟信号CLK，输出待处理时钟信号；其中，待处理时钟信号的时钟周期与初始时钟信号CLK的时钟周期相同；
分相模块112，配置为接收待处理时钟信号，对待处理时钟信号进行分频和分相处理，输出第一时钟信号clk0和第二时钟信号clk90；其中，第一时钟信号clk0和第二时钟信号clk90的时钟周期相同，且第一时钟信号clk0的时钟周期是初始时钟信号CLK的时钟周期的2倍。
需要说明的是，在理想情况下，第一时钟信号clk0和第二时钟信号clk90之间的相位差为90度，然而，由于实际工艺参数的偏差以及错配问题，分相模块112的工作参数可能存在偏差，导致第一时钟信号clk0和第二时钟信号clk90之间的相位差并非为90度且超出了误差允许的范 围，这也是需要引入第一调整模块14的部分原因。
在一些实施例中，请参考图4和图5，第一调整模块14，包括：
第一控制模块141，配置为接收第一目标时钟信号DLL0和第二同步时钟信号DL90，基于第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差，输出第一控制码DLLCode1<N：0>；
第一延迟链142，包括多个第一延迟单元，配置为接收第一控制码DLLCode1<N：0>和第二同步时钟信号DL90；基于第一控制码DLLCode1<N：0>，利用多个第一延迟单元对第二同步时钟信号DL90的进行延迟调整，输出第二目标时钟信号DLL90。
需要说明的是，第一控制码DLLCode1<N：0>是根据第二同步时钟信号DL90与理想情况(即第一目标时钟信号DLL0延迟90度)的相位偏差转化得到的。进一步地，第一延迟链142能够基于第一控制码DLLCode1<N：0>控制第二同步时钟信号DL90的相位向前或者向后调整，得到第二目标时钟信号DLL90，以保证第一目标时钟信号DLL0和第二目标时钟信号DLL90之间的相位差为90度。
在一些实施例中，如图5所示，第一控制模块141，包括：
第一脉冲处理模块21，配置为接收第一目标时钟信号DLL0和第二同步时钟信号DL90，输出第一脉冲信号IN0和第二脉冲信号IN1；其中，第一脉冲信号IN0和第二脉冲信号IN1均各自包括1个脉冲，且第一脉冲信号IN0的脉冲宽度指示第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差，第二脉冲信号IN1的脉冲宽度指示第二同步时钟信号DL90和第一目标时钟信号的反相信号之间的相位差；
第一时间数字转换模块22，配置为接收第一脉冲信号IN0和第二脉冲信号IN1；对第一脉冲信号IN0进行转换，输出第一转换码TDCCode0<N：0>，并对第二脉冲信号IN1进行转换，输出第二转换码TDCCode1<N：0>；其中，第一转换码TDCCode0<N：0>用于表征第一脉冲信号IN0的宽度，第二转换码TDCCode1<N：0>用于表征第二脉冲信号IN1的宽度；
第一逻辑模块23，配置为接收第一转换码TDCCode0<N：0>和第二转换码TDCCode1<N：0>，对第二转换码TDCCode1<N：0>和第一转换码TDCCode0<N：0>进行减法运算，输出第一控制码DLLCode1<N：0>。
这样，如果第一脉冲信号IN0的脉冲宽度大于第二脉冲信号IN1的脉冲宽度，说明第二同步时钟信号DL90过于滞后；如果第一脉冲信号IN0的脉冲宽度小于第二脉冲信号IN1的脉冲宽度，说明第二同步时钟信号DL90过于提前。同时，第一转换码TDCCode0<N：0>的数值和第一脉冲信号IN0的脉冲宽度是对应的，第二转换码TDCCode1<N：0>的数值和第二脉冲信号IN1的脉冲宽度是对应的，因此将第二转换码TDCCode1<N：0>减去第一转换码TDCCode0<N：0>能够得到第一控制码DLLCode1<N：0>。
特别地，根据电路中各参数定义以及信号连接关系的不同，也可能采用第一转换码TDCCode0<N：0>减去第二转换码TDCCode1<N：0>得到第一控制码DLLCode1<N：0>，具体机制需要根据实际电路进行确定。
在一些实施例中，参见图6，其示出了本公开实施例提供的一种信号时序示意图一。请参考图5和图6，第一脉冲处理模块21，包括：
第一脉冲模块211，配置为接收第一目标时钟信号DLL0和第二同步时钟信号DL90，对第一目标时钟信号DLL0和第二同步时钟信号DL90进行异或处理得到第一检测信号D0，对第一检测信号D0进行脉冲截取及拓宽处理得到第一中间信号S0，对第一中间信号S0和第一检测信号D0进行与处理，输出第一脉冲信号IN0；其中，第一检测信号D0包括多个脉冲，且第一检测信号D0的脉冲宽度指示第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差，第一中间信号S0包括一个脉冲，第一中间信号S0的脉冲宽度大于第一检测信号D0的脉冲宽度；
第二脉冲模块212，配置为接收第一目标时钟信号的反相信号和第二同步时钟信号DL90，对第一目标时钟信号的反相信号和第二同步时钟信号DL90进行异或处理得到第二检测信号D1，对第二检测信号D1进行脉冲截取及拓宽处理得到第二中间信号S1，对第二中间信号S1和第二检测信号D1进行与处理，输出第二脉冲信号IN1；其中，第二检测信号D1包括多个脉冲，且第二检测信号D1的脉冲宽度指示第一目标时钟信号的反相信号和第二同步时钟信号DL90之间 的相位差，第二中间信号S1包括一个脉冲，第二中间信号S1的脉冲宽度大于第二检测信号D1的脉冲宽度。
在这里，第一中间信号S0的脉冲至少覆盖第一检测信号D0中的一个完整脉冲，第二中间信号S1的脉冲至少覆盖第二检测信号D1中的一个完整脉冲。在图6中，“△”表示拓宽处理中的拓宽量。
需要说明的是，第一脉冲模块211和第二脉冲模块212的结构可以利用多种电学器件组合而成，本公开实施例后续将提供一种具体示例。
在一些实施例中，请参考图5和图6，第一时间转换模块22包括：
第一转换模块221，配置为接收第一脉冲信号IN0，利用第一脉冲信号IN0进行采样和延迟处理以得到多个第一采样时钟信号，利用多个第一采样时钟信号对第一脉冲信号IN0进行采样处理，输出第一转换码TDCCode0<N：0>；
第二转换模块222，配置为接收第二脉冲信号IN1，利用第二脉冲信号IN1进行采样和延迟处理以得到多个第二采样时钟信号，利用多个第二采样时钟信号对第二脉冲信号IN1进行采样处理，输出第二转换码TDCCode1<N：0>。
需要说明的是，第一转换模块221和第二转换模块222的结构是相似的，具体可以利用多种电学器件组合而成，本公开实施例后续将提供一种具体示例。
在一些实施例中，参见图7，其示出了本公开实施例提供的一种延迟锁相环10的结构示意图三。如图7所示，延迟锁相环10的输出信号还可以包括第三目标时钟信号DLL180和第四目标时钟信号DLL270。也就是说，延迟锁相环10输出第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270，且相邻的目标时钟信号之间的相位差为90度。
此时，预处理模块11，还配置为对初始时钟信号CLK进行预处理，输出第一时钟信号clk0、第二时钟信号clk90、第三时钟信号clk180和第四时钟信号clk270。相应的，延迟锁相环10还包括：
第三可调延迟线15，配置为接收第三时钟信号clk180，对第三时钟信号clk180进行调整及传输，输出第三目标时钟信号DLL180；其中，第一目标时钟信号DLL0和第三目标时钟信号DLL180的相位差为180度；
第四可调延迟线16，配置为接收第四时钟信号clk270，对第四时钟信号clk270进行调整及传输，输出第四同步时钟信号DL270；
第二调整模块17，配置为接收第三目标时钟信号DLL180和第四同步时钟信号DL270，基于第三目标时钟信号DLL180对第四同步时钟信号DL270进行延迟调整，输出第四目标时钟信号DLL270。
需要说明的是，由于延迟锁相环10的电路原理，第一可调延迟线12输出的第一目标时钟信号DLL0和第三可调延迟线15输出的第三目标时钟信号DLL180的错配较小，参见前面的图3。也就是说，可以认为第一目标时钟信号DLL0和第三目标时钟信号DLL180的相位差稳定为180度，即第一目标时钟信号DLL0和第三目标时钟信号DLL180互为反相信号。但是，第四可调延迟线16直接输出的第四同步时钟信号DL270的相位可能因为错配等原因发生偏移，因此引入第二调整模块17对第四同步时钟信号DL270进行延迟调整，能够使得第三目标时钟信号DLL180和第四目标时钟信号DLL270之间的相位差为90度，改善由于延迟线不匹配或者预处理过程而产生的相位偏差。
还需要说明的是，如图7所示，分相模块112，还配置为对待处理时钟信号进行分频和分相处理，输出第一时钟信号clk0、第二时钟信号clk90、第三时钟信号clk180和第四时钟信号clk270；其中，第一时钟信号clk0、第二时钟信号clk90、第三时钟信号clk180和第四时钟信号clk270的时钟周期相同，且第一时钟信号clk0的时钟周期是初始时钟信号CLK的时钟周期的2倍。
应理解，第二调整模块17的组成与第一调整模块14的组成类似，以下为具体说明。
在一些实施例中，如图7所示，第二调整模块17，包括：
第二控制模块171，配置为接收第三目标时钟信号DLL180和第四同步时钟信号DL270，基于第三目标时钟信号DLL180和第四同步时钟信号DL270之间的相位差，输出第二控制码 DLLCode2<N：0>；
第二延迟链172，包括多个第二延迟单元，配置为接收第二控制码DLLCode2<N：0>和第四同步时钟信号DL270，基于第二控制码DLLCode2<N：0>，利用多个第二延迟单元对第四同步时钟信号DL270的进行延迟调整，输出第四目标时钟信号DLL270。
需要说明的是，第二控制码DLLCode2<N：0>是根据第四同步时钟信号DL270与理想情况(即第三目标时钟信号DLL180延迟90度)的相位偏差转化得到的。进一步地，第二延迟链172能够基于第二控制码DLLCode2<N：0>控制第四同步时钟信号DL270的相位向前或者向后调整，得到第四目标时钟信号DLL270，以保证第三目标时钟信号DLL180和第四目标时钟信号DLL270之间的相位差为90度。
在一些实施例中，参见图8，其示出了本公开实施例提供的一种信号时序示意图二。请参考图7和图8，第二控制模块171，包括：
第二脉冲处理模块24，配置为接收第三目标时钟信号DLL180和第四同步时钟信号DL270，输出第三脉冲信号IN2和第四脉冲信号IN3；其中，第三脉冲信号IN2和第四脉冲信号IN3均各自包括1个脉冲，且第三脉冲信号IN2的脉冲宽度指示第三目标时钟信号DLL180和第四同步时钟信号DL270之间的相位差，第四脉冲信号IN3的脉冲宽度指示第四同步时钟信号DL270和第三目标时钟信号的反相信号之间的相位差；
第二时间数字转换模块25，配置为接收第三脉冲信号IN2和第三脉冲信号IN2；对第三脉冲信号IN2进行转换，输出第三转换码TDCCode2<N：0>，并对第四脉冲信号IN3进行转换，输出第四转换码TDCCode3<N：0>；其中，第三转换码TDCCode2<N：0>用于表征第三脉冲信号IN2的宽度，第四转换码TDCCode3<N：0>用于表征第四脉冲信号IN3的宽度；
第二逻辑模块26，配置为接收第三转换码TDCCode2<N：0>和第四转换码TDCCode3<N：0>，对第四转换码TDCCode3<N：0>和第三转换码TDCCode2<N：0>进行减法运算，输出第二控制码DLLCode2<N：0>。
这样，如果第三脉冲信号IN2的脉冲宽度大于第四脉冲信号IN3的脉冲宽度，说明第四同步时钟信号DL270过于滞后；如果第三脉冲信号IN2的脉冲宽度小于第四脉冲信号IN3的脉冲宽度，说明第四同步时钟信号DL270过于提前。同时，第三转换码TDCCode2<N：0>的数值和第三脉冲信号IN2的脉冲宽度是对应的，第四转换码TDCCode3<N：0>的数值和第四脉冲信号IN3的脉冲宽度是对应的，因此将第四转换码TDCCode3<N：0>减去第三转换码TDCCode2<N：0>能够得到第二控制码DLLCode2<N：0>。
在一些实施例中，如图7所示，第二脉冲处理模块24，包括：
第三脉冲模块213，配置为接收第三目标时钟信号DLL180和第四同步时钟信号DL270，对第三目标时钟信号DLL180和第四同步时钟信号DL270进行异或处理得到第三检测信号D2，对第三检测信号D2进行脉冲截取及拓宽处理得到第三中间信号S2，对第三中间信号S2和第三检测信号D2进行与处理，输出第三脉冲信号IN2；其中，第三检测信号D2包括多个脉冲，且第三检测信号D2的脉冲宽度指示第三目标时钟信号DLL180和第四同步时钟信号DL270之间的相位差，第三中间信号S2包括一个脉冲，第三中间信号S2的脉冲宽度大于第三检测信号D2的脉冲宽度；
第四脉冲模块214，配置为接收第三目标时钟信号的反相信号和第四同步时钟信号DL270，对第三目标时钟信号的反相信号和第四同步时钟信号DL270进行异或处理得到第四检测信号D3，对第四检测信号D3进行脉冲截取及拓宽处理得到第四中间信号S3，对第四中间信号S3和第四检测信号D3进行与处理，输出第四脉冲信号IN3；其中，第四检测信号D3包括多个脉冲，且第四检测信号D3的脉冲宽度指示第三目标时钟信号的反相信号和第四同步时钟信号DL270之间的相位差，第四中间信号S3包括一个脉冲，第四中间信号S3的脉冲宽度大于第四检测信号D3的脉冲宽度。
在这里，第三中间信号S2的脉冲至少覆盖第三检测信号D2中的一个完整脉冲，第四中间信号S3的脉冲至少覆盖第四检测信号D3中的一个完整脉冲。同时，第三脉冲模块213和第四脉冲模块214可以利用多种电学器件组合而成，本公开实施例后续将提供一种具体示例。
在一些实施例中，如图7所示，第二时间转换模块25包括：
第三转换模块223，配置为接收第三脉冲信号IN2，将第三脉冲信号IN2进行采样和延迟处 理以得到多个第三采样时钟信号，利用多个第三采样时钟信号对第三脉冲信号IN2进行采样处理，输出第三转换码TDCCode2<N：0>；
第四转换模块224，配置为接收第四脉冲信号IN3，将第四脉冲信号IN3进行采样和延迟处理以得到多个第四采样时钟信号，利用多个第四采样时钟信号对第四脉冲信号IN3进行采样处理，输出第四转换码TDCCode3<N：0>。
需要说明的是，第三转换模块和第四转换模块的结构是相似的，具体可以利用多种电学器件组合而成，本公开实施例后续将提供一种具体示例。
从以上可以看出，对于延迟锁相环10，由于利用第一调整模块对第二可调延迟线输出的第二同步时钟信号DL90进行额外调整，且利用第二调整模块对第四可调延迟线输出的第四同步时钟信号DL270进行延迟调整，因此能够保证最终得到的四相位时钟信号的相位差为预设值，改善由于延迟线不匹配或者预处理过程而产生的相位偏差，提高数据采样的效果。
如前述，第一脉冲模块211～第四脉冲模块214的结构相同，第一转换模块221～第四转换模块224的结构相同，以下以第一脉冲模块211、第一转换模块221为例，提供可行的电路元件组成。
在一些实施例中，参见图9，其示出了本公开实施例提供的一种延迟锁相环10的局部结构示意图一。如图9所示，第一脉冲模块211(图9中包括211a和211b两个部分)包括：第一触发器301、第二触发器302、第一非门303、第四延迟单元304、第一与门305、第一异或门306、第二与门307；在第一脉冲模块211中，第一异或门306的第一输入端接收第一目标时钟信号DLL0，第一异或门306的第二输入端接收第二同步时钟信号DL90，第一异或门306的输出端用于输出第一检测信号D0；第一触发器301的输入端接收第一电源信号VDD，第一触发器301的时钟端与第一异或门306的输出端连接；第一非门303的输入端与第一异或门306的输出端连接，第二触发器302的输入端接收地信号VSS，第二触发器302的输出端与第一非门303的输出端连接；第四延迟单元304的输入端与第二触发器302的输出端连接，第一与门305的第一输入端与第一触发器301的输出端连接，第一与门305的第二输入端与第四延迟单元304的输出端连接，第一与门305的输出端用于输出第一中间信号S0；第二与门307的第一输入端与第一与门305的输出端连接，第二与门307的第二输入端与第一异或门306的输出端连接，第二与门307的输出端用于输出第一脉冲信号IN0。
需要说明的是，如前述的图8所示，第一检测信号D0包括多个脉冲，每一脉冲的脉冲宽度指示第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差；第一中间信号S0仅包括一个脉冲信号，且第一中间信号S0的脉冲宽度为(第一检测信号D0的脉冲宽度+第四延迟单元304的延迟值△)，同时第一中间信号S0的脉冲覆盖且仅覆盖第一检测信号D0的一个脉冲。这样，将第一中间信号S0和第一检测信号D0进行与运算，刚好保留第一检测信号D0的一个脉冲，从而得到能够指示第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差的第一脉冲信号IN0。
为了避免混乱，图9仅针对第一脉冲模块211中的各个器件进行编号，即虚线框部分，第二脉冲模块～第四脉冲模块中的器件并未编号，请对应理解。
在第二脉冲模块212(图9中包括212a和212b两个部分)中，第一异或门的第一输入端为第二同步时钟信号DL90，第一异或门的第二输入端为第三目标时钟信号DLL180(相当于第一目标时钟信号的反相信号)，第一异或门的输出端用于输出第二检测信号D1，第一与门的输出端用于输出第二中间信号S1，第二与门的输出端用于输出第一脉冲信号IN0，其余器件的连接关系与第一脉冲模块211相同。
在第三脉冲模块213(图9中包括213a和213b两个部分)中，第一异或门的第一输入端为第三目标时钟信号DLL180，第一异或门的第二输入端为第四同步时钟信号DL270，第一异或门的输出端用于输出第三检测信号D2，第一与门的输出端用于输出第三中间信号S2，第二与门的输出端用于输出第三脉冲信号IN2，其余器件的连接关系与第一脉冲模块211相同。
在第四脉冲模块214(图9中包括214a和214b两个部分)中，第一异或门的第一输入端为第四同步时钟信号DL270，第一异或门的第二输入端为第一目标时钟信号DLL0(相当于第三目标时钟信号的反相信号)，第一异或门的输出端用于输出第四检测信号D3，第一与门的输出端用于输出第四中间信号S3，第二与门的输出端用于输出第四脉冲信号IN3，其余器件的连接 关系与第一脉冲模块211相同。
这样，如图8和图9所示，通过第一脉冲模块211～第四脉冲模块214，得到第一脉冲信号IN0、第二脉冲信号IN1、第三脉冲信号IN2、第四脉冲信号IN3，从而获得第二同步时钟信号DL90和第四同步时钟信号DL270的偏移情况。
在一些实施例中，第一转换码TDCCode0<N：0>、第二转换码TDCCode1<N：0>、第三转换码TDCCode2<N：0>、第四转换码TDCCode3<N：0>均各自包括多位子信号。以第一转换码TDCCode0<N：0>为例，其包括TDCcode0：<0>、TDCcode0:<1>……TDCcode0<N>这些子信号。
参见图10，其示出了本公开实施例提供的一种延迟锁相环10的局部结构示意图二。如图10所示，第一转换模块221包括第三触发器308、第三延迟链309、多个第四触发器310；其中，第三触发器308的输入端接收第二电源信号VDD，第三触发器308的时钟端接收第一脉冲信号IN0，第三触发器308的输出端与第三延迟链309的输入端连接；所有的第四触发器310的输入端均用于接收第一脉冲信号IN0；第三延迟链309包括串联设置的多个第三延迟单元，一个第四触发器310的时钟端与一个第三延迟单元的输出端对应连接，一个第四触发器310的输出端输出第一转换码TDCCode0<N：0>的一位子信号。
需要说明的是，为了方便说明，第三触发器308的输出信号记为信号Clk_start_0，参见图11，其示出了本公开实施例提供的一种信号时序示意图三。如图11所示，在第一脉冲信号IN0的上升沿，信号Clk_start_0由低电平状态变化为高电平状态，信号Clk_start_0在经过多个第三延迟单元的过程中依次得到信号Clk_start0(用作第1个第四触发器310的时钟信号)、信号Clk_start1(用作第2个第四触发器310的时钟信号)……信号Clk_startN(用作最后一个第四触发器310的时钟信号)，利用信号Clk_start0对第一脉冲信号IN0进行采样得到TDC0code<0>、利用信号Clk_start1对第一脉冲信号IN0进行采样得到TDCcode0<1>……利用信号Clk_startN对第一脉冲信号IN0进行采样得到TDCcode0<N>，从而得到第一转换码TDCCode0<N：0>。
类似的，图10仅针对第一转换模块221中的各个器件进行编号，第二转换模块～第四转换模块中的器件并未编号，请对应理解。
特别地，在第二转换模块222中，第三触发器的时钟端、所有的第四触发器的输入端均用于接收第二脉冲信号IN1，一个第四触发器的输出端输出述第二转换码TDCCode1<N：0>的一位子信号。在第三转换模块223中，第三触发器的时钟端、所有的第四触发器的输入端均用于接收第三脉冲信号IN2，一个第四触发器的输出端输出第三转换码TDCCode2<N：0>的一位子信号。在第四转换模块224中，第三触发器的时钟端、所有的第四触发器的输入端均用于接收第四脉冲信号IN3，一个第四触发器的输出端输出第四转换码TDCCode3<N：0>的一位子信号。
这样，将第一目标时钟信号DLL0和第二同步时钟信号DL90之间的相位差转换得到第一转换码TDCCode0<N：0>，将第二同步时钟信号DL90和第一目标时钟信号DLL0的反相信号之间的相位差转换得到第二转换码TDCCode1<N：0>，将第三目标时钟信号DLL180和第四同步时钟信号DL270之间的相位差转换得到第三转换码TDCCode2<N：0>，将第四同步时钟信号DL270和第三目标时钟信号的反相信号之间的相位差转换得到第四转换码TDCCode3<N：0>。
需要说明的是，第一延迟链142、第二延迟链172、第三延迟链309的结构对应相同。也就是说，第一延迟链142包括多个串联设置的第一延迟单元、第二延迟链172包括多个第二延迟单元；第一延迟链142中的第一延迟单元、第二延迟链172中的第二延迟单元、第三延迟链309中的第三延迟单元对应相同。
在一些实施例中，对于第一延迟链142和第二延迟链172来说，第一控制码DLLCode1<N：0>的第i位子信号用于控制第i个第一延迟单元处于开启状态或者关闭状态，第二控制码DLLCode2<N：0>的第i位子信号用于控制第i个第二延迟单元处于开启状态或者关闭状态；
第一延迟链142，具体配置为利用处于开启状态的第一延迟单元对第二同步时钟信号DL90进行延迟，输出第二目标时钟信号DLL90；
第二延迟链172，具体配置为利用处于开启状态的第二延迟单元对第四同步时钟信号DL270进行延迟，输出第四目标时钟信号DLL270。
这样，通过减少或增减延迟单元的开启数量可以调整延迟链的延迟值，其输出的目标时钟信号可以提前或者延后处理。
或者，在另一些实施例中，第一控制码DLLCode1<N：0>的前a位子信号为第一状态，第一控制码DLLCode1<N：0>的后(A-a)位子信号为第二状态；第二控制码DLLCode2<N：0>的前b位子信号为第一状态，第二控制码DLLCode2<N：0>的后(B-b)位子信号为第二状态；A、B、a、b均为正整数，且a小于或等于A，A是指第一控制码中的子信号的总位数，b小于或等于B，B是指第二控制码中的子信号的总位数。在这里，A＝B＝N+1。
第一延迟链142，具体配置为利用第1个～第a个第一延迟单元对第二同步时钟信号DL90进行延迟处理，并将第a个第一延迟单元的输出信号确定为第二目标时钟信号DLL90；
第二延迟链172，具体配置为利用第1个～第b个第二延迟单元对第四同步时钟信号DL270进行延迟处理，并将第b个第二延迟单元的输出信号确定为第四目标时钟信号DLL270。
以第一延迟链142为例，假设第一控制码DLLCode1<N：0>＝110000，此时第2个第一延迟单元的输出端输出第二目标时钟信号DLL90，即第二目标时钟信号DLL90不会通过最后4个第二延迟单元；假设DLLCode1<N：0>＝111100，此时第4个第二延迟单元的输出端输出第二目标时钟信号DLL90，即第二目标时钟信号DLL90不会通过最后2个第二延迟单元。
这样，由于延迟锁相环10引入了第一调整模块14和第二调整模块17，能够改善由于延迟线不匹配或者预处理过程而产生的相位偏差。
在一些实施例中，如图9所示，第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270在经过对应的信号传输路径后用于数据采样处理。具体来说，第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270在经过对应的信号传输路径后到达数据选择模块(Mux)，数据选择模块利用四相位的目标时钟信号对数据信号DQ进行采样及选择输出，得到目标数据信号。在这里，每一信号传输路径上可以设置一定数量的缓冲器，用于增加信号的驱动能力，且4条信号传输路径上的缓冲器的设置数目均是相同。
如图9所示，延迟锁相环10还包括：
反馈模块(包括第五可调延迟线411和复制延迟模块412)，配置为接收第一时钟信号clk0，输出模拟时钟信号，且模拟时钟信号用于模拟第一目标时钟信号DLL0经过信号传输路径后的波形；
检测模块42，配置为接收第一时钟信号clk0和模拟时钟信号，对第一时钟信号clk0和模拟时钟信号进行相位检测，得到相位检测信号；
调参模块43，配置为接收相位检测信号，基于相位检测信号输出延迟线控制信号；
第一可调延迟线12，具体配置为接收延迟线控制信号，基于延迟线控制信号对第一时钟信号clk0进行调整及传输，输出第一目标时钟信号DLL0；
第二可调延迟线13，具体配置为接收延迟线控制信号，基于延迟线控制信号对第二时钟信号clk90进行调整及传输，输出第二同步时钟信号DL90。
类似地，第三可调延迟线15，具体配置为接收延迟线控制信号，基于延迟线控制信号对第三时钟信号clk180进行调整及传输，输出第三目标时钟信号DLL180；第四可调延迟线16，具体配置为接收延迟线控制信号，基于延迟线控制信号对第四时钟信号clk270进行调整及传输，输出第四同步时钟信号DL270。
需要说明的是，第一目标时钟信号DLL0在到达数据选择模块时的波形和第一时钟信号clk0的波形需要保持一致，因此需要构建反馈调整机制。具体来说第一时钟信号clk0在经过反馈模块151后产生模拟时钟信号，由于模拟时钟信号能够模拟第一目标时钟信号DLL0在到达数据选择模块时的波形，所以根据模拟时钟信号和第一时钟信号clk0之间的差别来调整延迟线控制信号，以便对第一可调延迟线的工作参数进行调整。
另外，模拟时钟信号的波形与第一目标时钟信号DLL0经过信号传输路径后的波形并非是完全相同的。在实际工作场景中，在存储器进入稳定工作状态之后，模拟时钟信号可以进行分频处理，从而降低延迟线调整信号的更新频次，避免信号毛刺带来的信号抖动，同时降低电力消耗。
在一种具体的实施例中，如图9所示，反馈模块包括：
第五可调延迟线411，配置为接收第一时钟信号clk0和延迟线控制信号，基于延迟线控制信号对第一时钟信号clk0进行调整及传输，输出复制时钟信号；其中，第五可调延迟线与第一 可调延迟线的结构相同，复制时钟信号用于模拟第一目标时钟信号DLL0的波形；
复制延迟模块412，配置为接收复制时钟信号，对复制时钟信号进行延迟处理，输出模拟时钟信号；其中，复制延迟模块配置为模拟信号传输路径的延时。
这样，第五可调延迟线411用于复制第一可调延迟线的处理过程，复制延迟模块412至少配置为复制第一目标时钟信号DLL0经由信号传输路径进行传输时的延时，从而构成反馈调整的闭环。
综上所述，针对延迟锁相环，为了减小由于布图错配(Layout Mismatch)、工艺误差、电压、温度(Process Voltage Temperature，PVT)等引起的信号偏差，首先，通过对第一目标时钟信号、第二同步时钟信号、第三目标时钟信号和第四同步时钟信号各自的上升沿信息进行逻辑处理，形成第一脉冲信号IN0～第四脉冲信号IN3，将第一脉冲信号IN0～第四脉冲信号IN3分别输入到4个独立的时间数字转换模块(即第一转换模块～第四转换模块)，对应得到第一转换码TDCcode0<N：0>～第四转换码TDCcode3<N：0>；然后，将第二转换码TDCcode1<N：0>减去第一转换码TDCcode0<N：0>以得到第一控制码DLLCode1<N：0>，将第四转换码TDCcode3<N：0>减去第三转换码TDCcode2<N：0>以得到第二控制码DLLCode2<N：0>；最后，利用第一控制码DLLCode1<N：0>对第二同步时钟信号进行延迟调节，利用第二控制码DLLCode2<N：0>对第四同步时钟信号进行延迟调节，最终得到相位偏差较小的四相位目标时钟信号，提高数据采样的效果。
在本公开的另一实施例中，参见图12，其示出了本公开实施例提供的一种时钟同步电路50的结构示意图。如图12所示，该时钟同步电路50包括前述的延迟锁相环10和数据选择模块51，且所述延迟锁相环10和数据选择模块51之间设置信号传输路径；其中，
延迟锁相环10，配置为接收初始时钟信号，输出第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270；其中，第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270之间的相位依次相差90度；
数据选择模块51，配置为经由对应的信号传输路径分别接收第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270，并利用第一目标时钟信号DLL0、第二目标时钟信号DLL90、第三目标时钟信号DLL180和第四目标时钟信号DLL270对数据信号DQ进行采样及选择输出，得到目标数据信号进行选择输出处理，得到目标数据信号。
特别地，如图12所示，对所有的信号传输路径来说，每一信号传输路径均设置了相同数目的缓冲器，以起到信号延迟和驱动增强的作用。图8中以每一信号传输路径设置2个缓冲器为例进行示出，但在实际应用过程中可以更多或者更少。
需要说明的是，延迟锁相环10的结构请参见前述说明，其在第二可调延迟线的输出一侧设置第一调整模块，在第四可调延迟线的输出一侧设置第二调整模块，然后利用第一调整模块对第二可调延迟线输出的信号进行延迟调整，且利用第二调整模块对第四可调延迟线输出的信号进行延迟调整，因此能够保证最终得到的四相位时钟信号的相位差为预设值，改善由于延迟线不匹配或者预处理过程而产生的相位偏差，提高数据采样的效果。
在本公开的又一实施例中，参见图13，其示出了本公开实施例提供的一种存储器60组成结构示意图。如图13所示，存储器60至少包括前述的延迟锁相环10。
在一些实施例中，存储器至少符合以下规范之一：DDR3、DDR4、DDR5、DDR6、LPDDR3、LPDDR4、LPDDR5、LPDDR6。
以上，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围。需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任 意组合，得到新的产品实施例。本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种延迟锁相环和存储器，该延迟锁相环包括：该延迟锁相环包括：预处理模块，配置为接收初始时钟信号，对初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；第一可调延迟线，配置为接收第一时钟信号，对第一时钟信号进行调整及传输，输出第一目标时钟信号；第二可调延迟线，配置为接收第二时钟信号，对第二时钟信号进行调整及传输，输出第二同步时钟信号；第一调整模块，配置为基于第一目标时钟信号对第二同步时钟信号进行延迟调整，输出第二目标时钟信号；其中，第一目标时钟信号和第二目标时钟信号之间的相位差为预设值。这样，通过第一调整模块可以对第一同步时钟信号和第二目标时钟信号之间的相位差进行校正，改善目标时钟信号之间的相位偏差。

Claims (20)

  1. 一种延迟锁相环，所述延迟锁相环包括：
    预处理模块，配置为接收初始时钟信号，对所述初始时钟信号进行预处理，输出第一时钟信号和第二时钟信号；
    第一可调延迟线，配置为接收所述第一时钟信号，对所述第一时钟信号进行调整及传输，输出第一目标时钟信号；
    第二可调延迟线，配置为接收所述第二时钟信号，对所述第二时钟信号进行调整及传输，输出第二同步时钟信号；
    第一调整模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，基于所述第一目标时钟信号对所述第二同步时钟信号进行延迟调整，输出第二目标时钟信号；
    其中，所述第一目标时钟信号和所述第二目标时钟信号之间的相位差为预设值。
  2. 根据权利要求1所述的延迟锁相环，其中，所述预处理模块包括：
    接收模块，配置为接收所述初始时钟信号，输出待处理时钟信号；其中，所述待处理时钟信号的时钟周期与所述初始时钟信号的时钟周期相同；
    分相模块，配置为接收所述待处理时钟信号，对所述待处理时钟信号进行分频和分相处理，输出所述第一时钟信号和所述第二时钟信号；
    其中，所述第一时钟信号和所述第二时钟信号的时钟周期相同，且所述第一时钟信号的时钟周期是所述初始时钟信号的时钟周期的2倍。
  3. 根据权利要求2所述的延迟锁相环，其中，所述第一调整模块，包括：
    第一控制模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，基于所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，输出第一控制码；
    第一延迟链，包括多个第一延迟单元，配置为接收所述第一控制码和所述第二同步时钟信号；基于所述第一控制码，利用多个第一延迟单元对所述第二同步时钟信号的进行延迟调整，输出所述第二目标时钟信号。
  4. 根据权利要求3所述的延迟锁相环，其中，所述第一控制模块，包括：
    第一脉冲处理模块，配置为接收所述第一目标时钟信号和所述第二同步时钟信号，输出第一脉冲信号和第二脉冲信号；其中，所述第一脉冲信号和所述第二脉冲信号均各自包括1个脉冲，且所述第一脉冲信号的脉冲宽度指示所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，所述第二脉冲信号的脉冲宽度指示所述第二同步时钟信号和所述第一目标时钟信号的反相信号之间的相位差；
    第一时间数字转换模块，配置为接收所述第一脉冲信号和所述第二脉冲信号；对所述第一脉冲信号进行转换，输出第一转换码，并对所述第二脉冲信号进行转换，输出第二转换码；其中，所述第一转换码用于表征所述第一脉冲信号的宽度，所述第二转换码用于表征所述第二脉冲信号的宽度；
    第一逻辑模块，配置为接收所述第一转换码和所述第二转换码，对所述第二转换码和所述第一转换码进行减法运算，输出所述第一控制码。
  5. 根据权利要求4所述的延迟锁相环，其中，第一脉冲处理模块，包括：
    所述第一脉冲模块，配置为接收所述第一目标时钟信号和第二同步时钟信号，对所述第一目标时钟信号和所述第二同步时钟信号进行异或处理得到第一检测信号，对所述第一检测信号进行脉冲截取及拓宽处理得到第一中间信号，对所述第一中间信号和所述第一检测信号进行与处理，输出所述第一脉冲信号；其中，所述第一检测信号包括多个脉冲，且所述第一检测信号的脉冲宽度指示所述第一目标时钟信号和所述第二同步时钟信号之间的相位差，所述第一中间信号包括一个脉冲，第一中间信号的脉冲宽度大于所述第一检测信号的脉冲宽度；
    所述第二脉冲模块，配置为接收所述第一目标时钟信号的反相信号和第二同步时钟信号，对所述第一目标时钟信号的反相信号和所述第二同步时钟信号进行异或处理得到第二检测信号，对所述第二检测信号进行脉冲截取及拓宽处理得到第二中间信号，对所述第二中间信号和所述 第二检测信号进行与处理，输出所述第二脉冲信号；其中，所述第二检测信号包括多个脉冲，且所述第二检测信号的脉冲宽度指示所述第一目标时钟信号的反相信号和所述第二同步时钟信号之间的相位差，所述第二中间信号包括一个脉冲，第二中间信号的脉冲宽度大于所述第二检测信号的脉冲宽度。
  6. 根据权利要求5所述的延迟锁相环，其中，所述第一时间转换模块包括：
    第一转换模块，配置为接收第一脉冲信号，利用所述第一脉冲信号进行采样和延迟处理以得到多个第一采样时钟信号，利用多个所述第一采样时钟信号对所述第一脉冲信号进行采样处理，输出所述第一转换码；
    第二转换模块，配置为接收第二脉冲信号，利用所述第二脉冲信号进行采样和延迟处理以得到多个第二采样时钟信号，利用多个所述第二采样时钟信号对所述第二脉冲信号进行采样处理，输出所述第二转换码。
  7. 根据权利要求6所述的延迟锁相环，其中，
    所述预处理模块，还配置为对所述初始时钟信号进行预处理，输出第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    所述延迟锁相环还包括：
    第三可调延迟线，配置为接收所述第三时钟信号，对所述第三时钟信号进行调整及传输，输出第三目标时钟信号；其中，所述第一目标时钟信号和所述第三目标时钟信号的相位差为180度；
    第四可调延迟线，配置为接收所述第四时钟信号，对所述第四时钟信号进行调整及传输，输出第四同步时钟信号；
    第二调整模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，基于所述第三目标时钟信号对所述第四同步时钟信号进行延迟调整，输出第四目标时钟信号；
    其中，所述第一目标时钟信号、所述第二目标时钟信号、所述第三目标时钟信号和所述第四目标时钟信号之间的相邻相位差均为90度。
  8. 根据权利要求7所述的延迟锁相环，其中，
    所述分相模块，还配置为对所述待处理时钟信号进行分频和分相处理，输出第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号；
    其中，所述第一时钟信号、所述第二时钟信号、所述第三时钟信号和所述第四时钟信号的时钟周期相同，且所述第一时钟信号的时钟周期是所述初始时钟信号的时钟周期的2倍。
  9. 根据权利要求8所述的延迟锁相环，其中，所述第二调整模块，包括：
    第二控制模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，基于所述第三目标时钟信号和所述第四同步时钟信号之间的相位差，输出第二控制码；
    第二延迟链，包括多个第二延迟单元，配置为接收所述第二控制码和所述第四同步时钟信号，基于所述第二控制码，利用多个第二延迟单元对所述第四同步时钟信号的进行延迟调整，输出所述第四目标时钟信号。
  10. 根据权利要求9所述的延迟锁相环，其中，所述第二控制模块，包括：
    第二脉冲处理模块，配置为接收所述第三目标时钟信号和所述第四同步时钟信号，输出第三脉冲信号和第四脉冲信号；其中，所述第三脉冲信号和所述第四脉冲信号均各自包括1个脉冲，且所述第三脉冲信号的脉冲宽度指示所述第三目标时钟信号和所述第四同步时钟信号之间的相位差，所述第四脉冲信号的脉冲宽度指示所述第四同步时钟信号和所述第三目标时钟信号的反相信号之间的相位差；
    第二时间数字转换模块，配置为接收所述第三脉冲信号和所述第三脉冲信号；对所述第三脉冲信号进行转换，输出第三转换码，并对所述第四脉冲信号进行转换，输出第四转换码；其中，所述第三转换码用于表征所述第三脉冲信号的宽度，所述第四转换码用于表征所述第四脉冲信号的宽度；
    第二逻辑模块，配置为接收所述第三转换码和所述第四转换码，对所述第四转换码和所述第三转换码进行减法运算，输出所述第二控制码。
  11. 根据权利要求10所述的延迟锁相环，其中，所述第二脉冲处理模块，包括：
    所述第三脉冲模块，配置为接收所述第三目标时钟信号和第四同步时钟信号，对所述第三 目标时钟信号和所述第四同步时钟信号进行异或处理得到第三检测信号，对所述第三检测信号进行脉冲截取及拓宽处理得到第三中间信号，对所述第三中间信号和所述第三检测信号进行与处理，输出所述第三脉冲信号；其中，所述第三检测信号包括多个脉冲，且所述第三检测信号的脉冲宽度指示所述第三目标时钟信号和所述第四同步时钟信号之间的相位差，所述第三中间信号包括一个脉冲，且所述第三中间信号的脉冲宽度大于所述第三检测信号的脉冲宽度；
    所述第四脉冲模块，配置为接收所述第三目标时钟信号的反相信号和第四同步时钟信号，对所述第三目标时钟信号的反相信号和所述第四同步时钟信号进行异或处理得到第四检测信号，对所述第四检测信号进行脉冲截取及拓宽处理得到第四中间信号，对所述第四中间信号和所述第四检测信号进行与处理，输出所述第四脉冲信号；其中，所述第四检测信号包括多个脉冲，且所述第四检测信号的脉冲宽度指示所述第三目标时钟信号的反相信号和所述第四同步时钟信号之间的相位差，所述第四中间信号包括一个脉冲，且所述第四中间信号的脉冲宽度大于所述第四检测信号的脉冲宽度。
  12. 根据权利要求11所述的延迟锁相环，其中，所述第二时间转换模块包括：
    第三转换模块，配置为接收第三脉冲信号，将所述第三脉冲信号进行采样和延迟处理以得到多个第三采样时钟信号，利用多个所述第三采样时钟信号对所述第三脉冲信号进行采样处理，输出所述第三转换码；
    第四转换模块，配置为接收第四脉冲信号，将所述第四脉冲信号进行采样和延迟处理以得到多个第四采样时钟信号，利用多个所述第四采样时钟信号对所述第四脉冲信号进行采样处理，输出所述第四转换码。
  13. 根据权利要求11所述的延迟锁相环，其中，所述第一脉冲模块包括：第一触发器、第二触发器、第一非门、第四延迟单元、第一与门、第一异或门、第二与门；所述第二脉冲模块、所述第三脉冲模块、所述第四脉冲模块与所述第一脉冲模块的结构对应相同；
    其中，在所述第一脉冲模块中，所述第一异或门的第一输入端接收所述第一目标时钟信号，所述第一异或门的第二输入端接收所述第二同步时钟信号，所述第一异或门的输出端用于输出所述第一检测信号；所述第一触发器的输入端接收第一电源信号，所述第一触发器的时钟端与所述第一异或门的输出端连接；所述第一非门的输入端与所述第一异或门的输出端连接，所述第二触发器的输入端接收地信号，所述第二触发器的输出端与所述第一非门的输出端连接；所述第四延迟单元的输入端与所述第二触发器的输出端连接，所述第一与门的第一输入端与所述第一触发器的输出端连接，所述第一与门的第二输入端与所述第四延迟单元的输出端连接，所述第一与门的输出端用于输出所述第一中间信号；所述第二与门的第一输入端与所述第一与门的输出端连接，所述第二与门的第二输入端与所述第一异或门的输出端连接，所述第二与门的输出端用于输出所述第一脉冲信号。
  14. 根据权利要求12所述的延迟锁相环，其中，所述第一转换码、所述第二转换码、所述第三转换码、所述第四转换码均各自包括多位子信号；
    所述第一转换模块包括第三触发器、第三延迟链、多个第四触发器，且所述第二转换模块、所述第三转换模块、所述第四转换模块均与所述第一转换模块的结构对应相同；其中，
    在所述第一转换模块中，所述第三触发器的输入端接收第二电源信号，所述第三触发器的时钟端接收所述第一脉冲信号，所述第三触发器的输出端与所述第三延迟链的输入端连接；所有的第四触发器的输入端均用于接收所述第一脉冲信号；所述第三延迟链包括串联设置的多个第三延迟单元，一个所述第四触发器的时钟端与一个第三延迟单元的输出端对应连接，一个所述第四触发器的输出端输出所述第一转换码的一位子信号。
  15. 根据权利要求14所述的延迟锁相环，其中，所述第一延迟链包括多个串联设置的第一延迟单元、所述第二延迟链包括多个第二延迟单元；
    所述第一延迟链中的第一延迟单元、所述第二延迟链中的第二延迟单元、所述第三延迟链中的第三延迟单元对应相同。
  16. 根据权利要求15所述的延迟锁相环，其中，所述第一控制码的第i位子信号用于控制第i个第一延迟单元处于开启状态或者关闭状态，所述第二控制码的第i位子信号用于控制第i个第二延迟单元处于开启状态或者关闭状态；
    所述第一延迟链，具体配置为利用处于开启状态的所述第一延迟单元对所述第二同步时钟 信号进行延迟，输出所述第二目标时钟信号；
    所述第二延迟链，具体配置为利用处于开启状态的所述第二延迟单元对所述第四同步时钟信号进行延迟，输出所述第四目标时钟信号。
  17. 根据权利要求16所述的延迟锁相环，其中，所述第一控制码的前a位子信号为第一状态，所述第一控制码的后(A-a)位子信号为第二状态；所述第二控制码的前b位子信号为第一状态，所述第二控制码的后(B-b)位子信号为第二状态；A、B、a、b均为正整数，且a小于或等于A，A是指第一控制码中的子信号的总位数，b小于或等于B，B是指第二控制码中的子信号的总位数；
    所述第一延迟链，具体配置为利用第1个～第a个所述第一延迟单元对所述第二同步时钟信号进行延迟处理，并将第a个所述第一延迟单元的输出信号确定为所述第二目标时钟信号；
    所述第二延迟链，具体配置为利用第1个～第b个所述第二延迟单元对所述第四同步时钟信号进行延迟处理，并将第b个所述第二延迟单元的输出信号确定为所述第四目标时钟信号。
  18. 根据权利要求1-17任一项所述的延迟锁相环，其中，所述第一目标时钟信号、所述第二目标时钟信号、所述第三目标时钟信号和所述第四目标时钟信号在经过对应的信号传输路径后用于数据采样处理；
    所述延迟锁相环还还包括：
    反馈模块，配置为接收所述第一时钟信号，输出模拟时钟信号，且所述模拟时钟信号用于模拟所述第一目标时钟信号经过所述信号传输路径后的波形；
    检测模块，配置为接收所述第一时钟信号和所述模拟时钟信号，对所述第一时钟信号和所述模拟时钟信号进行相位检测，得到相位检测信号；
    调参模块，配置为接收所述相位检测信号，基于所述相位检测信号输出延迟线控制信号；
    所述第一可调延迟线，具体配置为接收所述延迟线控制信号，基于所述延迟线控制信号对所述第一时钟信号进行调整及传输，输出所述第一目标时钟信号；
    所述第二可调延迟线，具体配置为接收所述延迟线控制信号，基于所述延迟线控制信号对所述第二时钟信号进行调整及传输，输出所述第二同步时钟信号。
  19. 根据权利要求18所述的延迟锁相环，其中，所述反馈模块包括：
    第五可调延迟线，配置为接收所述第一时钟信号和所述延迟线控制信号，基于所述延迟线控制信号对所述第一时钟信号进行调整及传输，输出复制时钟信号；其中，所述第五可调延迟线与所述第一可调延迟线的结构相同，所述复制时钟信号用于模拟所述第一目标时钟信号的波形；
    复制延迟模块，配置为接收所述复制时钟信号，对所述复制时钟信号进行延迟处理，输出模拟时钟信号；其中，所述复制延迟模块配置为模拟所述信号传输路径的延时。
  20. 一种存储器，所述存储器包括如权利要求1-19任一项所述的延迟锁相环。
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