WO2024040645A1 - 半导体结构及其制造方法、存储器 - Google Patents

半导体结构及其制造方法、存储器 Download PDF

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Publication number
WO2024040645A1
WO2024040645A1 PCT/CN2022/118639 CN2022118639W WO2024040645A1 WO 2024040645 A1 WO2024040645 A1 WO 2024040645A1 CN 2022118639 W CN2022118639 W CN 2022118639W WO 2024040645 A1 WO2024040645 A1 WO 2024040645A1
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trench
active
layer
word line
semiconductor
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English (en)
French (fr)
Inventor
邵光速
肖德元
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure, a manufacturing method thereof, and a memory.
  • embodiments of the present disclosure propose a semiconductor structure, a manufacturing method thereof, and a memory.
  • a semiconductor structure including:
  • Active pillars are located on the surface of the substrate.
  • a plurality of the active pillars form an active pillar array having several columns arranged along the first direction and several rows arranged along the second direction.
  • the active pillars Comprising a top active area, a channel area and a bottom active area, the first direction intersects the second direction and are both parallel to the substrate surface;
  • a word line extending along the second direction and covering the channel region of the active pillars of the same column arranged along the first direction;
  • a dielectric layer located between the word line and the active pillar and covering at least the surface of the channel region;
  • a bit line extends along the first direction and is electrically connected to the bottom active area of the active pillars of the same row arranged along the second direction;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • the word line is embedded in the sidewall of the active pillar located in the channel region and covers the first sidewall and the second sidewall of the channel region that are oppositely arranged along the first direction. side wall;
  • the length of the part of the word line covering the first sidewall along the third direction is different from the length of the part of the word line covering the second sidewall along the third direction; wherein, the third direction perpendicular to the substrate surface.
  • the active pillar array includes a plurality of first active pillar rows and second active pillar rows alternately arranged along the first direction;
  • the word line corresponding to the first active pillar column and the word line corresponding to the second active pillar column are arranged symmetrically with respect to the second direction.
  • the interface between the channel region and the top active region, and/or the interface between the channel region and the bottom active region is a right angle, an oblique angle or a rounded angle.
  • the semiconductor structure further includes an isolation structure, and the isolation structure is located between adjacent active pillars, between adjacent word lines, and between adjacent bit lines.
  • the material of the bit line includes a metal compound, or a combination of a metal compound and a metal.
  • a memory including: at least one semiconductor structure as described in any one of the above solutions, a storage structure located on the semiconductor structure, and a memory structure located around or around the semiconductor structure. Peripheral circuitry above the memory structure.
  • a memory manufacturing method including:
  • An array of active pillars is formed on the surface of the substrate with several columns arranged along the first direction and several rows arranged along the second direction.
  • the active pillars include a top active area, a channel area and a bottom active area. region, the first direction and the second direction intersect and are both parallel to the substrate surface;
  • word line Forming a word line, the word line extending along the second direction and covering the channel region of the active pillars of the same column arranged along the first direction;
  • the dielectric layer is located between the word line and the active pillar and covers at least the surface of the channel region;
  • bit line extending along the first direction and electrically connected to the bottom active region of the active pillars of the same row arranged along the second direction;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • forming the active pillar array includes:
  • a plurality of second trenches and third trenches arranged alternately along the first direction are formed, and the second trenches and the third trenches both penetrate the first semiconductor layer and the second trench.
  • the remaining second semiconductor layer forms the top active region of the active pillar
  • the third semiconductor layer forms the channel region of the active pillar and the remaining active layer forming the bottom active region of the active pillar;
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench.
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench, including:
  • the remaining conductive layer forms the word line.
  • the method also includes:
  • a portion of the second insulating material in the third trench is removed.
  • the top surface of the remaining second insulating material in the trench is not higher than the top surface of the active layer.
  • a fourth trench including:
  • a portion of the first semiconductor layer is removed along the first direction.
  • forming a third semiconductor layer in the fourth trench includes:
  • a third semiconductor layer is formed in the fourth trench by epitaxial growth.
  • the first semiconductor layer and the second semiconductor layer have different etching selectivity ratios.
  • the material of the third semiconductor layer and the material of the second semiconductor layer are the same.
  • bit line includes:
  • the bottoms of the second trench and the third trench are etched to form grooves so that the depths of parts of the second trench and the third trench are increased and the grooves are formed along the edges.
  • the width dimension in the first direction is greater than the width dimension of the second groove or the third groove;
  • the first metal layer reacts with the active layer of the groove sidewall to form a metal compound layer, and the groove is filled with a second metal layer.
  • the second metal layer and the The metal compound layer collectively forms the bit line.
  • the second trench and the third trench have the same depth, and the depth of the first trench is greater than the depth of the second trench and the third trench.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the sum of the size of the top active region and the size of the dielectric layer. That is to say, the word line in the semiconductor structure
  • the active pillars are embedded in and cover the channel region of the active pillars.
  • the corresponding active pillars have a dumbbell-like shape. In this way, the distance between adjacent word lines can be increased in the first aspect, so that the word lines can be increased.
  • the coupling between lines is smaller, and the electrical properties of the word lines are better; secondly, the overall feature size of the word lines and active pillars can be made smaller, thereby further shrinking the semiconductor structure.
  • Figure 1 is a schematic diagram of a control circuit using an 1T1C architecture provided in an embodiment of the present disclosure
  • Figure 2a is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2b is a schematic three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2c is a schematic three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2d is a schematic three-dimensional structural diagram of yet another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 4a to 4s are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure
  • 5a to 5j are schematic three-dimensional structural diagrams of the manufacturing process of another semiconductor structure provided by embodiments of the present disclosure.
  • 6a to 6e are schematic three-dimensional structural diagrams of another manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7a to 7e are schematic three-dimensional structural diagrams of the manufacturing process of yet another semiconductor structure provided by embodiments of the present disclosure.
  • FIGS. 8a to 8c are schematic three-dimensional structural diagrams of another manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • the dynamic random access memory is composed of multiple memory cell structures.
  • Each memory cell structure mainly consists of a transistor and a memory cell controlled by the transistor.
  • Figure 1 is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of the present disclosure; as shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source region of the transistor T is connected to One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line). Connection; applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
  • the size of DRAM (taking DRAM as an example) is constantly shrinking.
  • the word line WL is arranged around the channel of the transistor T. At this time, the spacing between the word line WL and the word line WL If it is too small, the coupling will be too large; moreover, the size of the word line WL and the size of the channel of the transistor T are too large, making it difficult to continue shrinking; the transistors in related technologies are limited in size, and it is difficult for DRAM to balance high performance.
  • embodiments of the present disclosure provide a semiconductor structure.
  • FIGS. 2a to 2d are schematic three-dimensional structural diagrams of some semiconductor structures provided by embodiments of the present disclosure.
  • a semiconductor structure 10a, 10b, 10c, 10d provided by an embodiment of the present disclosure includes:
  • Active pillars AP are located on the surface of the substrate 100.
  • a plurality of active pillars AP are formed into several columns (first active pillar array CA1, second active pillar array CA2...) arranged along the first direction. ) and an active pillar array of several rows (first active pillar row RA1, second active pillar column RA2...) arranged along the second direction, the active pillar AP includes a top active area TA, In the channel area CH and the bottom active area BA, the first direction intersects the second direction and are both parallel to the surface of the substrate 100;
  • the word line WL extends along the second direction and covers the channel region CH of the active pillars of the same column arranged along the first direction;
  • the dielectric layer 109 is located between the word line WL and the active pillar AP and covers at least the surface of the channel region CH;
  • Bit line BL extends along the first direction and is electrically connected to the bottom active area BA of the active pillars AP in the same row arranged along the second direction;
  • the size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the size of the top active region and the size of the medium.
  • the sum of the layer dimensions is W4.
  • dimensions W1 to W6 can be understood as width dimensions or thickness dimensions along the first direction; lengths H1 to H6 can be understood as height dimensions or thickness dimensions along the third direction. .
  • semiconductor structures shown in the embodiments of the present disclosure are not exclusive, and the structural features shown can also be interchanged between semiconductor structures in different embodiments; each structural feature of the semiconductor structures shown in the embodiments of the present disclosure The structure, size, location, etc. can be adjusted according to actual needs.
  • the first direction and the second direction are expressed as two intersecting directions parallel to the surface of the substrate;
  • the third direction is a direction perpendicular to the surface of the substrate, that is, the third direction is the The extension direction of the active pillar; wherein, the surface of the substrate can be understood as a plane perpendicular to the extension direction of the active pillar.
  • the descriptions of the first direction, the second direction, and the third direction in the following embodiments are only used to illustrate the present disclosure and are not used to limit the scope of the present disclosure.
  • the angle between the first direction and the second direction ranges from 0 to 90 degrees.
  • the first direction may be perpendicular to the second direction. It can be understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the active pillars along the first direction and the second direction.
  • the material of the substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe) substrate, etc., or may also be silicon-on-insulator (SOI, Silicon-on-insulator) or Germanium-on-Insulator (GOI, Germanium-on-Insulator).
  • the bottom active area BA includes a material doped with certain impurity ions in the top of the substrate.
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doping includes well region doping and source and drain region doping.
  • the top active region TA and the channel region CH are made of the same material, and both include semiconductor materials with certain impurity ions.
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doping includes well region doping and source and drain region doping.
  • the material of the dielectric layer 109 includes but is not limited to silicon dioxide.
  • the materials of the word line WL and the bit line BL include but are not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.
  • the word line WL is embedded in the active pillar AP in the sidewall of the channel region CH and covers the edge of the channel region CH. a first side wall and a second side wall arranged oppositely in the first direction;
  • the length H1 along the third direction of the partial word line covering the first sidewall is different from the length H2 along the third direction of the partial word line covering the second sidewall; wherein, the third Three directions are perpendicular to the surface of the substrate 100 .
  • the length H1 of the part of the word line covering the first sidewall along the third direction is different from the length H1 of the part of the word line covering the second sidewall along the third direction.
  • the length H2 in the third direction is different.
  • the length H1 is smaller than the length H2.
  • the bottom surface of the partial word line covering the first side wall is higher than the bottom surface of the partial word line covering the second side wall
  • the top surface of the partial word line covering the first side wall is lower than the bottom surface of the partial word line covering the first side wall. on the top surface of part of the word lines covering the second sidewall.
  • the length H3 of the partial word line covering the first sidewall along the third direction is different from the length H3 of the partial word line covering the second sidewall along the third direction.
  • the length H4 in the third direction is different.
  • the length H3 is smaller than the length H4.
  • the bottom surface of the part of the word line covering the first sidewall and the bottom surface of the part of the word line covering the second sidewall are substantially flush with the top surface of the bottom active area BA, and cover all the word lines.
  • the top surface of the partial word line of the first side wall is lower than the top surface of the partial word line covering the second side wall.
  • the length of the part of the word line covering the first sidewall along the third direction is the same as the length of the part of the word line covering the second sidewall along the third direction.
  • the lengths in the three directions are the same, for example, they are all length H5.
  • the bottom surface of the partial word line covering the first sidewall and the bottom surface of the partial word line covering the second sidewall are higher than the top surface of the bottom active area BA.
  • the size of the part of the word line covering the first sidewall along the first direction is the same as the size of the part of the word line covering the second sidewall along the first direction.
  • both are the size W5; and the sum of twice the size W5 and the size of the trench region CH is less than or equal to the size of the top active region TA.
  • the length of the part of the word line covering the first sidewall along the third direction is the same as the length of the part of the word line covering the second sidewall along the third direction.
  • the lengths in the three directions are the same, for example, they are all length H6.
  • the bottom surface of the partial word line covering the first sidewall and the bottom surface of the partial word line covering the second sidewall are substantially flush with the top surface of the bottom active area BA.
  • the size of the part of the word line covering the first sidewall along the first direction is the same as the size of the part of the word line covering the second sidewall along the first direction.
  • both are the size W6; and the sum of twice the size W6 and the size of the trench region CH is less than or equal to the size of the top active region TA.
  • the word line in the first direction since the word line extends along the second direction and includes a portion surrounding the channel region and a portion between the channel regions, the word line is in the first direction.
  • the directional dimensions are not equal everywhere along the second direction. It can be understood that for the part of the word line surrounding the channel region, the size in the first direction does not include the size of the channel region and the dielectric layer surrounded by the word line in the first direction, but only Refers to the sum of the dimensions of the word lines on both sides of the surrounding channel region in the first direction; for the partial word lines between the channel regions along the second direction, the dimensions along the first direction are, Refers to the size of the word line in the first direction.
  • the active pillar array includes a plurality of first active pillar arrays CA1 and second active pillar arrays CA2 alternately arranged along the first direction;
  • the word line WL1 corresponding to the first active pillar array CA1 and the word line WL2 corresponding to the second active pillar array CA2 are arranged symmetrically with respect to the second direction.
  • the word line WL1 and the word line WL2 are symmetrically arranged with respect to the second direction, which can be understood as the adjacent word line WL1 and the word line WL2 with respect to the second direction between the adjacent word lines.
  • the vertical center plane of the isolation structure 204 extending in two directions is symmetrical.
  • the word line WL1 corresponding to the first active pillar column CA1 and the word line WL2 corresponding to the second active pillar column CA2 are separated with respect to the partial isolation structure 204 ( The isolation structure 204) between word line WL1 and word line WL2 is symmetrically arranged.
  • the word line WL1 corresponding to the first active pillar column CA1 and the word line WL2 corresponding to the second active pillar column CA2 are separated with respect to the partial isolation structure 204 ( The isolation structure 204) between the word line WL1 and the word line WL2 is symmetrically arranged.
  • the word line WL1 corresponding to the first active pillar column CA1 is arranged symmetrically with respect to the first active pillar array CA1, and is symmetrically arranged with the first active pillar column CA1.
  • the word line WL2 corresponding to the second active pillar array CA2 is symmetrically arranged with respect to the second active pillar array CA2.
  • the interface between the channel region CH and the top active region TA, and/or the interface between the channel region CH and the bottom active region BA is at a right angle or an oblique angle. or rounded corners.
  • the bevel angle and the rounded corner can be understood as shapes obtained by chamfering and rounding the right angle respectively.
  • each active pillar in the active pillar array is perpendicular to the third direction and passes through the top active area TA, the channel area CH, the
  • the cross-sectional shape of the bottom active area BA may be a rectangle, an octagon or a rounded rectangle.
  • the octagon and the rounded rectangle can be understood as shapes obtained by chamfering and rounding the four right angles of the rectangle respectively.
  • the semiconductor structure further includes an isolation structure 204.
  • the isolation structure 204 is located between adjacent active pillars AP, between adjacent word lines WL, and between adjacent word lines WL. between bit lines BL.
  • the part of the isolation structure 204 between the adjacent active pillars serves as the first sub-isolation structure that isolates the word line from the outside in the Z direction; the part between the adjacent word lines
  • the isolation structure 204 serves as a second sub-isolation structure for isolating word lines; a portion of the isolation structure 204 between adjacent bit lines serves as a third sub-isolation structure for isolating bit lines.
  • the materials of the first sub-isolation structure, the second sub-isolation structure, and the third sub-isolation structure may be the same or different.
  • the materials of the first sub-isolation structure, the second sub-isolation structure, and the third sub-isolation structure include any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon nitride. Silicon oxide.
  • the top surface of the bit line BL is flat (as shown in Figures 2a and 2b) or arcuate (as shown in Figures 2c and 2d).
  • the material of the bit line BL includes a metal compound, or a combination of a metal compound and a metal. It can be understood that the bit line BL includes a metal compound layer 111, or a combination of the metal compound layer 111 and the second metal layer 112, wherein the material of the metal compound layer 111 includes a metal compound, and the second metal The material of layer 112 includes metal.
  • the bit line BL includes a combination of a metal compound layer 111 and a second metal layer 112 .
  • the material of the metal compound layer 111 includes metal cobalt (Co) compound and/or metal nickel (Ni) compound
  • the material of the second metal layer 112 includes tungsten (W).
  • the word line in the semiconductor structure has the following structural characteristics: 1.
  • the word line is embedded in the active pillar and covers the channel region of the active pillar, and the corresponding active pillar has a similar Dumbbell shape; in this way, the distance between adjacent word lines is increased, and the coupling between word lines is smaller, making the word lines electrically better; at the same time, the contact area between the channel area and the word line can be increased, thereby It can reduce the height of the channel area and increase the structural stability of the channel area.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer. In this way, the overall feature sizes of the word lines and active pillars are smaller, and a further shrinkable semiconductor structure can be obtained.
  • a memory provided by an embodiment of the present disclosure includes: at least one semiconductor structure according to any one of the above solutions, a storage structure located on the semiconductor structure, and a storage structure located around the semiconductor structure or above the storage structure. Peripheral circuits.
  • the semiconductor structure is coupled to the memory unit and the peripheral circuit; wherein the peripheral circuit is configured to: receive a read or write command; in response to the read or write command, read or rewrite the The information stored in the storage structure.
  • the memory includes: DRAM
  • the storage structure includes: a capacitor; more specifically, the capacitor may include a cup-shaped capacitor, a barrel-shaped capacitor, or a columnar capacitor.
  • the capacitor includes a columnar second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric.
  • the second electrode terminal may be connected to the top active area TA in the active pillar, and the first electrode terminal may be connected to a reference voltage.
  • the reference voltage may be ground voltage, or may include other voltages.
  • the capacitor represents logical "1"s and "0s" by the amount of charge stored in it.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 3, a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • the active pillars include a top active region, a channel region and a bottom In the active area, the first direction and the second direction intersect and are both parallel to the substrate surface;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • FIG. 4a to 4s are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 3 and FIG. 4 a to FIG. 4 s.
  • Steps S301 and S302 are executed, and with reference to FIGS. 4a to 4e and 4j to 4l, a substrate is provided and an active pillar array is formed.
  • the material of the substrate 100 may include silicon, germanium, silicon germanium substrate, etc.; the material of the substrate 100 may also be silicon on insulator or germanium on insulator.
  • forming the active pillar array includes the following steps:
  • the remaining second semiconductor layer forms the top active region of the active pillar
  • the third semiconductor layer forms the channel region of the active pillar and the remaining active layer forming the bottom active region of the active pillar;
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench.
  • Step a is performed, referring to FIG. 4b, to form an active layer, a first semiconductor layer and a second semiconductor layer.
  • an ion implantation process is used to dope a material with certain impurity ions into the top of the substrate 100 to form the active layer 101 .
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doped source and drain regions are doped.
  • the material of the substrate 100 includes silicon, and the top of the substrate 100 is heavily doped with N-type to form the active layer 101 with N-type heavy doping.
  • a thin film deposition process is used to sequentially deposit the first semiconductor layer 102 and the second semiconductor layer 103 on the surface of the active layer 101 .
  • the thin film deposition process includes but is not limited to physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) and other processes.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD Atomic Layer Deposition
  • the first semiconductor layer 102 can be formed on the surface of the active layer 101 through an epitaxial growth process (EGP); the second semiconductor layer 103 can be formed on the first surface.
  • the surface of the semiconductor layer 102 is formed by EGP.
  • the second semiconductor layer 103 adopts an in-situ doping process, which can include but is not limited to PVD, CVD process or ALD process. While epitaxially growing silicon, gas containing N-type doping atoms is introduced while depositing the epitaxial growth silicon. N-type heavy doping was also performed.
  • the first semiconductor layer 102 and the second semiconductor layer 103 have different etching selectivity ratios.
  • the material of the first semiconductor layer 102 is silicon germanium
  • the material of the second semiconductor layer 103 is N-type heavily doped silicon.
  • the material of the second semiconductor layer 103 is N-type heavily doped silicon, and the second semiconductor layer 103 is formed using an in-situ doping process.
  • a process including, but not limited to, PVD, CVD or ALD can be used.
  • Gas containing N-type doping atoms is introduced while epitaxially growing silicon.
  • N-type heavy doping is also performed while epitaxially growing silicon while depositing it.
  • Step b refer to Figure 4c and Figure 4d, to form a first trench and fill the first trench.
  • the top surface of the second semiconductor layer 103 is first etched through a photolithography-etching process (LE, Lithography-Etch) to form a plurality of first trenches T1 spaced apart along the second direction.
  • each first trench T1 extends along the first direction.
  • the first trench T1 penetrates the active layer 101 , the first semiconductor layer 102 and the second semiconductor layer 103 and extends into the substrate 100 .
  • the first trench T1 divides the active layer 101, the first semiconductor layer 102 and the second semiconductor layer 103 into a plurality of strip structures extending along the first direction.
  • the first trench T1 is filled with a first insulating material 201; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the second semiconductor layer 103.
  • the constituent material of the first insulating material 201 includes but is not limited to silicon dioxide (SiO 2 ).
  • the first etching includes but is not limited to a dry plasma etching process.
  • the first trench T1 includes but is not limited to a Shallow Trench Isolation (STI) structure.
  • STI Shallow Trench Isolation
  • Step c is performed, referring to Figure 4e, to form the second trench and the third trench.
  • a second etching is performed on the top surface of the second semiconductor layer 103 through a photolithography-etching process to form a plurality of second trenches T2 and third trenches T3 alternately arranged along the first direction.
  • each of the second trench T2 and the third trench T3 extends along the second direction.
  • the second trench T2 and the third trench T3 both penetrate the first semiconductor layer 102 and the second semiconductor layer 103 and extend into the active layer 101 .
  • the second trench T2 and the third trench T3 divide the plurality of strip-shaped active layers 101, the first semiconductor layer 102 and the second semiconductor layer 103 into multiple strips along the first direction. and a plurality of columnar structures arranged in an array in the second direction.
  • the second etching includes but is not limited to a dry plasma etching process.
  • a hard mask layer 104 is added before dry plasma etching to protect the top surface of the second semiconductor layer 103 and reduce the thickness of the second semiconductor layer 103 . of the top is consumed.
  • the material of the hard mask layer 104 includes but is not limited to silicon dioxide.
  • step S305 is executed to form bit lines.
  • the formed bit lines BL extend along the first direction and are electrically connected to the bottoms of the active pillars AP (refer to FIG. 4l ) arranged in the same row along the first direction.
  • Active area BA (refer to Figure 4l).
  • bit lines includes:
  • a protective layer 105 is formed on the sidewalls of the second trench T2 and the third trench T3;
  • the bottoms of the second trench T2 and the third trench T3 are etched to form a groove T11 so that part of the second trench T2 and the third trench
  • the depth of T3 increases and the width dimension of the groove T11 along the first direction is greater than the width dimension of the second groove T2 or the third groove T3;
  • a first metal layer is formed in the groove
  • the first metal layer reacts with the active area of the groove sidewall to form a metal compound layer 111, and the groove is filled with a second metal layer 112.
  • the second metal layer 112 and The metal compound layer 111 collectively forms the bit line BL.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the protective layer 105 is used as a mask, and the etchant is passed into the bottoms of the second trench T2 and the third trench T3. Isotropic etching increases the diameter width of the bottoms of the second trench T2 and the third trench T3 along the X-axis direction, and the width dimension of the groove T11 along the first direction is larger than the The width dimension of the second groove T2 or the third groove T3 results in a groove T11 having a bowl-shaped space.
  • the grooves T11 can be understood as a plurality of grooves T11 corresponding one-to-one with the second grooves T2 and the third grooves T3 along the first direction.
  • the metal compound layer 111 is formed in the groove and the second metal layer 112 is filled, to obtain the second metal layer 112 and the metal compound layer 111.
  • the bit lines BL, and the metal compound layer 111 both extend along the first direction, and the second metal layer 112 is spaced apart by parts of the metal compound layer 111 along the first direction.
  • the protective layer 105 is used as a mask to pass the etchant into the bottoms of the second trench T2 and the third trench T3. Isotropic etching by the etchant etches open the middle part of the active layer 101 through over-etching, so that the bottoms of the second trench T2 and the third trench T3 are connected to each other along the X-axis direction.
  • the resulting groove T11 is integral and extends along the X-Y plane.
  • the metal compound layer 111 is formed in the groove and the second metal layer 112 is filled to obtain the second metal layer 112 and the metal compound layer 111.
  • the bit line BL is formed, and the second metal layer 112 and the metal compound layer 111 both extend along the first direction.
  • the material of the first metal layer and the material of the second metal layer may be the same or different.
  • the material of the first metal layer is different from the material of the second metal layer.
  • the material of the first metal layer may include at least one of cobalt, nickel, chromium, tin, silver, and gold. 1.
  • the material of the second metal layer 112 may include tungsten.
  • the material of the first metal layer and the second metal layer are the same, and the constituent materials of the first metal layer and the second metal layer 112 both include cobalt.
  • the first metal layer can be deposited on the exposed active layer 101 in the groove T11 through PVD, CVD, ALD and other processes; a heat treatment process, such as a rapid thermal annealing process (RTP), can be used. , Rapid Thermal Process), causing the first metal layer to react with the active layer 101 in contact with its surroundings to form a metal compound layer 111; here, the metal compound layer 111 extends along the first direction.
  • the metal compound layer 111 is used as a bit line.
  • the second metal layer 112 may be further deposited in the groove T11 where the metal compound is formed through processes such as PVD, CVD, and ALD. In this way, the second metal layer 112 and the metal compound layer 111 together form the bit line BL.
  • the bit line BL and the active layer 101 can be Ohmic contact is formed between them, which is beneficial to reducing contact resistance.
  • the top surface of the bit line BL is lower than the top surface of the active layer 101 .
  • the bit line BL completely fills the groove T11, that is, the top surface of the bit line BL is flush with the top of the groove T11.
  • the top surface of the bit line BL is flat (as shown in Figures 2a and 2b) or arcuate (as shown in Figures 2c and 2d).
  • the method before filling the second metal layer 112 in the groove, the method further includes: forming a diffusion barrier layer (not shown) in the groove where the metal compound layer 111 is formed.
  • a diffusion barrier layer (not shown) may be formed in the groove where the metal compound layer 111 is formed through processes such as PVD, CVD, ALD, etc.
  • the diffusion barrier layer is used to prevent the material of the second metal layer 112 from diffusing to the metal compound layer 111 after the second metal layer 112 is formed in the groove where the diffusion barrier layer (not shown) is formed. , in the active layer 101.
  • the diffusion barrier layer is made of titanium nitride (TiN).
  • the second trench T2 and the third trench T3 in which the protective layer 105 is formed are filled with the second insulating material 106.
  • the second insulating material 106 includes, but is not limited to, silicon dioxide.
  • the depths of the second trench T2 and the third trench T3 are the same, and the depth of the first trench T1 is greater than that of the second trench T2 and the third trench T3.
  • the second trench T2 and the third trench T3 penetrate the first semiconductor layer 102 and the second semiconductor layer 103 and extend into the active layer 101 , and the groove T11 Also located in the active layer 101; the first trench T1 penetrates the first semiconductor layer 102, the second semiconductor layer 103 and the active layer 101, and extends into the substrate. That is, referring to FIG. 4i, the bottom surface of the bit line BL is higher than the bottom surface of the first insulating material 201.
  • bit lines BL and the first insulating material 201 are alternately arranged at intervals along the second direction; it is ensured that a plurality of bit lines BL are separated by the first insulating material 201 and are independent of each other.
  • Perform step d refer to Figure 4j to Figure 4k, to form a fourth trench.
  • a selective etching process is used to remove part of the first semiconductor layer 102 in the second trench along the first direction.
  • the selective etching process may include Atomic-Layer Etching (ALE).
  • the selective etching process may include quasi-Atomic-Layer Etching (qALE). Layer Etching).
  • the sidewall at the position of the first semiconductor layer 102 in the second trench T2 is removed to form a fourth trench T4, including:
  • a portion of the first semiconductor layer 102 is removed along the first direction.
  • ALE or qALE can be used to remove part of the first semiconductor layer 102 finely, ensuring that the fourth groove T4 is recessed along the first direction into the characteristic size and sidewall shape of the first semiconductor layer 102.
  • the appearance is precisely controlled to prepare for the precise positioning of the formation position of the channel region in subsequent processes.
  • a third semiconductor layer is formed in the fourth trench T4, including:
  • a third semiconductor layer is formed in the fourth trench T4 by epitaxial growth.
  • the third semiconductor layer is deposited by EGP, and the fifth trench T5 is also obtained (which can be understood as the fourth trench T4 having the third semiconductor layer).
  • the third semiconductor layers are arranged in an array along the first direction and the second direction, and each third semiconductor layer connects the first semiconductor layer 102 and the third semiconductor layer along the third direction.
  • Two semiconductor layers 103 are arranged in an array along the first direction and the second direction, and each third semiconductor layer connects the first semiconductor layer 102 and the third semiconductor layer along the third direction.
  • the remaining second semiconductor layer 103 forms the top active area TA of the active pillar AP
  • the third semiconductor layer forms the channel area CH of the active pillar
  • the remaining The active layer 101 forms the bottom active area BA of the active pillar.
  • the material of the third semiconductor layer and the second semiconductor layer are the same.
  • the second semiconductor layer 103 and the third semiconductor layer are both made of N-type heavily doped silicon (Si).
  • the remaining first insulating material and the remaining first semiconductor layer are removed from the third trench to form a sixth trench.
  • removing the remaining first insulating material may be understood to include at least removing the first insulating material located between the channel regions CH and the top active region TA.
  • the third trench is filled with an insulating material (for example, refer to the second insulating material 106 and the protective layer 105 in FIG. 4n), and all remaining materials are removed from the third trench.
  • the first insulating material and the remaining first semiconductor layer 102 are also removed, and part of the insulating material in the third trench is also removed.
  • the part of the insulating material at least includes between the channel region CH and the Insulating material between the top active areas TA (for example, refer to the second insulating material 106 and the protective layer 105 between the channel areas CH and the top active areas TA in FIG. 4n).
  • the bottom surface of the sixth trench T6 is flush with or not flush with the bottom surface of the fifth trench T5 (refer to FIG. 4m).
  • the bottom surface of the sixth trench T6 is flush with the bottom surface of the fifth trench T5 (refer to FIG. 4m).
  • the active pillars AP are arranged in an array along the first direction and the second direction, and each active pillar AP includes the top active area TA, the bottom active area BA and The third direction connects the channel regions CH of each top active area TA and each bottom active area BA.
  • the fifth trench and the sixth trench are used to sequentially form the dielectric layer and the word line in the fifth trench and the sixth trench in a subsequent process (details Refer to Figures 4m to 4n, and Figures 4o to 4s) described below.
  • step S303 and step S304 refer to FIGS. 4m to 4n, and 4o to 4s to form word lines and dielectric layers.
  • forming the dielectric layer and the word line sequentially in the fifth trench and the sixth trench includes:
  • the remaining conductive layer forms the word line.
  • part of the dielectric layer and part of the conductive layer may be formed in the fifth trench first, and then the sixth trench may be formed, part of the dielectric layer and part of the conductive layer may be formed in the sixth trench, and then the fifth and part of the conductive layer may be removed simultaneously.
  • Part of the conductive layer in the six trenches forms word lines located in the fifth and sixth trenches respectively.
  • a dielectric layer and a conductive layer are formed in the fifth and sixth trenches at the same time, and then part of the conductive layer in the fifth and sixth trenches is removed simultaneously to form a word line.
  • a dielectric layer and a conductive layer are formed in the fifth trench.
  • the dielectric layer 109 can be formed through an in-situ oxidation process (ISSG, In Situ Steam Generation).
  • ISSG In situ Steam Generation
  • at least part of the sidewall of each channel region CH is exposed in the fifth trench (refer to FIG. 4l), and in the fifth trench T5, by heating or pressurizing, At least the exposed sidewalls of each channel region CH are oxidized in situ to form the dielectric layer 109 .
  • the material of the dielectric layer 109 includes but is not limited to silicon dioxide. It should be noted that here, the dielectric layer 109 covers part of the channel region CH, but does not surround all sidewalls of the channel region CH.
  • the dielectric layer 109 is formed by performing in-situ oxidation on the exposed portion of each active pillar AP (including the channel region CH) and the sidewall in the fifth trench.
  • the conductive layer 110 may be deposited in the fifth trench T5 having the dielectric layer 109 through a PVD process, a CVD process or an ALD process. It should be noted that here, the conductive layer 110 covers part of the channel region CH, but does not surround all sidewalls of the channel region CH.
  • the material of the conductive layer 110 may be a metal material or a semiconductor conductive material, such as copper, cobalt, nickel, tungsten, molybdenum, doped silicon, polysilicon or any combination thereof.
  • a dielectric layer and a conductive layer are formed in the sixth trench.
  • each channel region CH is exposed in the sixth trench T6 (which can be understood as other sidewalls that are not exposed by the fifth trench T5).
  • the finally formed dielectric layer 109 can at least surround the sidewalls of the channel region CH.
  • the conductive layer 110 may at least surround the sidewalls of the dielectric layer 109 .
  • an isolation structure is formed and a word line is formed.
  • part of the conductive layer 110 can be removed through a photolithography-etching process to form a plurality of seventh trenches T7 spaced apart along the first direction, and the seventh trenches T7 penetrate along the third direction. the conductive layer 110 .
  • the word line WL (understood with reference to the remaining conductive material after removing part of the conductive layer 110 ) is exposed to the sidewalls of the seventh trench T7 and the top active area TA of the cladding dielectric layer 109 The side walls of the seventh trench T7 are flush in the third direction.
  • the dielectric layer 109 covering the top active area TA is also removed simultaneously (not shown in FIG. 4q ).
  • the word line WL (understood with reference to the remaining conductive material after removing part of the conductive layer 110) is exposed to the sidewalls of the seventh trench T7 and the top active area TA is exposed to the sidewalls of the seventh trench T7.
  • the third direction is flush.
  • the first etching includes but is not limited to a dry plasma etching process.
  • a hard mask layer (not shown in Figure 4q) is added before dry plasma etching to protect the top surface of the active pillar AP and reduce the damage to the top surface of the active pillar AP. consumption, the height of the top active area TA in the active pillar AP in the third direction may also be increased.
  • the isolation structure 204 extending along the second direction may be formed in the seventh trench T7 (refer to FIG. 4q) through a PVD process, a CVD process or an ALD process.
  • the material of the isolation structure 204 includes, but is not limited to, silicon dioxide.
  • part of the conductive layer is removed through an etching back process, and an isolation structure extending along the second direction is formed at the location where the part of the conductive layer is removed; wherein the remaining conductive layer forms the word line.
  • the depth of the etching back along the third direction is substantially consistent with the height of the top active area TA in the active pillar AP along the third direction.
  • the basic agreement can be understood as the depth of etching back along the third direction is the same as the height of the top active area TA in the active pillar AP along the third direction, or, Within the process error range, the depth of the etching back along the third direction is slightly less than or greater than the height of the top active area TA in the active pillar AP along the third direction.
  • the material of the isolation structure includes, but is not limited to, silicon dioxide.
  • the word line WL is formed, the word line WL extends along the second direction, and covers the channel region CH of the active pillars AP arranged in the same column along the second direction; forming The dielectric layer 109 is located between the word line WL and the active pillar AP and at least covers the surface of the channel region CH; wherein, in the first direction, the The size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the sum W4 of the size of the top active region and the size of the dielectric layer. In other specific embodiments, in the first direction, the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region.
  • the method further includes:
  • a portion of the second insulating material in the third trench is removed.
  • the top surface of the remaining second insulating material in the trench is lower than the top surface of the active layer.
  • the top surface of the remaining second insulating material in the second trench may be lower than the top surface of the active layer.
  • the remaining second insulating material in the second trench may be lower than the top surface of the active layer.
  • the remaining top surface of the second insulating material may be flush with the top surface of the active layer.
  • flush solution please refer to the description of the manufacturing process of the relevant semiconductor structure in Figures 5a to 5j below.
  • a portion of the second insulating material 106 in the second trench is removed, and the top surface of the remaining second insulating material 106 in the second trench is lower than the top of the active layer 101 .
  • a portion of the second semiconductor layer 102 in the third trench is removed. Insulating material 106 , the top surface of the remaining second insulating material 106 in the third trench is lower than the top surface of the active layer 101 .
  • a protective layer 105 is formed on the sidewalls of the second trench and the third trench; When part of the second insulating material 106 in the second trench is removed, the protective layer 105 is also removed simultaneously. The remaining protective layer 105 and the top surface of the second insulating material 106 are lower than The top surface of the active layer 101 .
  • a protective layer 105 on the sidewalls of the second trench and the third trench and filling the second insulating material 106 covering the protective layer 105 are described as examples.
  • materials of the protective layer 105 and the second insulating material 106 include but are not limited to silicon dioxide.
  • part of the top surface of the active layer 101 can be exposed in the fifth trench and the sixth trench, and part of the sidewalls of the active layer 101 can also be exposed to facilitate formation of the active layer 101 in the subsequent process.
  • Different forms of word lines for example, part of the bottom surface of the word line WL formed in FIGS. 2 a and 2 c are not flush with the top surface of the active layer 101 .
  • word line formation scheme 1 The word line formation method shown in FIGS. 4 h to 4 s is hereinafter referred to as word line formation scheme 1.
  • the method further includes:
  • a portion of the second insulating material in the third trench is removed.
  • the remaining top surface of the second insulating material in the trench is flush with the top surface of the active layer.
  • FIG. 5a to 5j are schematic three-dimensional structural views of another manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figures 5a to 5j can replace Figures 4j to 4s in Figures 4a to 4s. That is to say, Figures 4a to 4i and Figures 5a to 5j are another semiconductor structure provided by an embodiment of the present disclosure. Schematic diagram of the three-dimensional structure of the manufacturing process.
  • word line forming solution 2 a word line is formed (hereinafter referred to as word line forming solution 2).
  • part of the first semiconductor layer 102 is removed, exposing part of the top surface of the active layer 101, part of the top surface of the active layer 101 and the second trench The top surface of the remaining second insulating material 106 is flush.
  • the channel region CH is formed.
  • the bottoms of the two opposite channel regions CH (the channel region CH and the bottom The distance between the junctions of the active areas BA) is smaller than the distance between the tops of the two opposite channel areas CH (the junctions of the channel areas CH and the top active areas TA).
  • the remaining first semiconductor layer 102 is removed (refer to FIG. 5e), exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the bottom surface.
  • the top surface of the source area BA is removed (refer to FIG. 5e), exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the bottom surface.
  • the word line WL is formed, and the bottom surface of the word line WL is at least partially flush with the top surface of the bottom active area BA.
  • the specific differences between the word lines WL in Figure 5j and Figure 4s can be understood with reference to the differences between the word lines WL in Figures 2a and 2b, and will not be described again here.
  • the height of the word line WL formed in the third direction is different.
  • the word line WL formed in the word line forming scheme 2 is in The higher height in the third direction can increase the contact area between the channel region and the word line, thereby reducing the height of the channel region and increasing the structural stability of the channel region.
  • forming the dielectric layer and the word line sequentially in the fifth trench and the sixth trench includes:
  • the remaining conductive layer forms the word line.
  • FIG. 6a to 6e are schematic three-dimensional structural diagrams of yet another manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • Figures 6a to 6e can replace Figures 4l to 4s in Figures 4a to 4s. That is to say, Figures 4a to 4k and Figures 6a to 6e are yet another semiconductor structure provided by an embodiment of the present disclosure. Schematic diagram of the three-dimensional structure of the manufacturing process.
  • a dielectric layer and a conductive layer are simultaneously formed in the fifth trench and the sixth trench. Details will be described below in conjunction with FIGS. 4a to 4k and 6a to 6e.
  • the solution of simultaneously forming a dielectric layer and a conductive layer in the fifth trench and the sixth trench to form a word line (hereinafter referred to as word line formation solution 3) will be described.
  • the remaining first semiconductor layer 102 is removed to expose all the sidewalls of the channel region CH, all the sidewalls of the top active area TA, part of the top surface of the bottom active area BA and The side walls, that is to say, the gap between the active pillars AP penetrates into an overall gap space T12, which is equivalent to the fifth trench T5 and the sixth trench in FIGS. 4l to 4p formed together and mutually. The penetration forms an integral gap space T12.
  • the dielectric layer 109 at least surrounding the active region CH can be formed through an in-situ oxidation process.
  • the conductive layer 110 at least surrounding the dielectric layer 109 can be formed through a single deposition process.
  • the dielectric layer at least surrounding the active region CH is formed by performing an in-situ oxidation process in the fifth trench T5 and the sixth trench T6 respectively. 109 and perform a deposition process each to form the conductive layer 110 that at least surrounds the dielectric layer 109 .
  • the method of forming the isolation structure 204 and the word line is the same as that of FIGS. 4q to 4s and will not be described again here.
  • the word line WL is formed through an in-situ oxidation process to form the dielectric layer 109 at least surrounding the active region CH and A deposition process forms the conductive layer 110 at least surrounding the dielectric layer 109 . It has the advantage of simplifying the process flow.
  • FIGS. 6a to 6e are modified examples of the manufacturing process of the same type of semiconductor structure (hereinafter referred to as word line formation scheme 4).
  • the top surface of the remaining second insulating material 106 in the third trench is flush with the top surface of the remaining second insulating material 106 in the second trench and is The top surface of the active layer 101 is flush.
  • the lengths of the word lines formed in the fifth trench and the sixth trench along the third direction are different. In other embodiments, the lengths of the word lines formed in the fifth trench and the sixth trench are different.
  • the lengths of the word lines formed in the sixth trench along the third direction may be the same, specifically:
  • the method before forming the dielectric layer 109, the method further includes:
  • part of the second insulating material 106 (refer to FIG. 4n ) in the third trench T3 (refer to FIG. 4n ) is removed, and the remaining first semiconductor layer 102 is removed (refer to FIG. 4n ). , exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the top surface of the bottom active area BA;
  • the third semiconductor layer is deposited by EGP.
  • a dielectric layer 109 is formed in the sixth trench to make the channel region CH symmetrical.
  • the symmetry of the channel region CH means that the channel region CH is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the dielectric layer 109 may also be symmetrical.
  • the symmetry of the dielectric layer 109 means that the dielectric layer 109 is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the semiconductor structure that can finally be formed is as shown in FIG. 2c and FIG. 2d.
  • the word line WL is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the difference between FIG. 2c and FIG. 2d is that the height of the word line WL shown in FIG. 2c along the third direction is smaller than the height of the word line WL shown in FIG. 2d along the third direction.
  • the manufacturing method of the semiconductor structure uses an epitaxial growth process to form a first semiconductor layer as a sacrificial layer; and by removing the first semiconductor layer, epitaxial growth forms a channel at the location where the first semiconductor layer is removed. area; and then form a word line covering the channel area through a self-alignment process.
  • the word line WL manufactured by the manufacturing method of the semiconductor structure has the following structural characteristics: 1.
  • the word line WL is embedded in the active pillar AP, and the corresponding active pillar AP is similar to a dumbbell shape, that is, In the first direction, the size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • the sum of the sizes is W4, so that the distance between adjacent word lines WL is increased, the parasitic capacitance is smaller, and the electrical properties are better; 2.
  • the word lines WL that fully surround the channel region CH along the third direction can be unequal or equal, with an asymmetric structure (as shown in Figures 2a and 2b) or a symmetrical structure (as shown in Figures 2c and 2d).
  • the length, width and other dimensions of the word line covering the first side wall and the word line covering the second side wall exist in the word line WL that fully surrounds the channel region CH. They can be set independently, so that the word line WL is embedded in the side wall of the channel region CH, increasing the contact area between the channel region CH and the word line WL, and reducing the height of the channel region CH.
  • the overall size of the word line WL and the channel of the transistor T is used to achieve continuous shrinkage of the transistor size, thereby improving the performance of DRAM; at the same time, the structure and size of the word line WL are adjustable and have good Process suitability.
  • the semiconductor structure manufactured by the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
  • For technical features that are not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding. Here, no further details will be given. Repeat.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the sum of the size of the top active region and the size of the dielectric layer. That is to say, the word line in the semiconductor structure
  • the active pillars are embedded in and cover the channel area of the active pillars.
  • the corresponding active pillars have a dumbbell-like shape.
  • the first aspect can increase the distance between adjacent word lines, so that the word lines The coupling between lines is smaller, and the electrical properties of the word lines are better; secondly, the overall feature size of the word lines and active pillars can be made smaller, thereby further shrinking the semiconductor structure.

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Abstract

本公开实施例提出了一种半导体结构及其制造方法、存储器，其中，半导体结构包括：衬底；有源柱，位于衬底表面，多个有源柱构成具有沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，有源柱包括顶部有源区、沟道区以及底部有源区，第一方向与第二方向相交且均平行于衬底表面；字线，沿第二方向延伸，包覆沿第一方向排布的同一列的有源柱的沟道区；介质层，位于字线与有源柱之间且至少覆盖道区的表面；位线，沿第一方向延伸，且电连接沿第二方向排布的同一行的有源柱的底部有源区；其中，沿第一方向上，沟道区的尺寸小于顶部有源区的尺寸，字线的尺寸不超过顶部有源区的尺寸与介质层的尺寸之和。

Description

半导体结构及其制造方法、存储器
相关申请的交叉引用
本公开基于申请号为202211006092.5、申请日为2022年08月22日、发明名称为“半导体结构及其制造方法、存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其制造方法、存储器。
背景技术
随着半导体器件，如存储器尺寸的不断缩小，半导体器件中的晶体管尺寸也在被不断缩小，缩小的尺寸对晶体管的性能带来了更大的挑战。相关技术中的晶体管受限于尺寸，难以兼顾高性能。
发明内容
为解决相关技术问题，本公开实施例提出了一种半导体结构及其制造方法、存储器。
根据本公开的第一方面，提供了一种半导体结构，包括：
衬底；
有源柱，位于所述衬底表面，多个所述有源柱构成具有沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，所述有源柱包括顶部有源区、沟道区以及底部有源区，所述第一方向与所述第二方向相交且均平行于所述衬底表面；
字线，沿所述第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区；
介质层，位于所述字线与所述有源柱之间且至少覆盖所述沟道区的表面；
位线，沿所述第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱的所述底部有源区；
其中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和。
上述方案中，所述字线内嵌在所述有源柱位于所述沟道区的侧壁中且包覆所述沟道区沿所述第一方向相对设置的第一侧壁和第二侧壁；
包覆所述第一侧壁的部分字线在沿第三方向上的长度与包覆所述第二侧壁的部分字线在沿所述第三方向的长度不同；其中，所述第三方向垂直于所述衬底表面。
上述方案中，所述有源柱阵列包括沿所述第一方向交替间隔排布的若干第一有源柱列和第二有源柱列；
与所述第一有源柱列对应的字线和与所述第二有源柱列对应的字线关于所述第二方向对称设置。
上述方案中，所述沟道区与所述顶部有源区的交界处，和/或，所述沟道区与所述底部有源区的交界处为直角、斜角或圆角。
上述方案中，所述半导体结构还包括隔离结构，所述隔离结构位于相邻的所述有源柱之间、相邻的所述字线之间以及相邻的所述位线之间。
上述方案中，所述位线的材料包括金属化合物，或，金属化合物与金属的组合。
根据本公开的第二方面，提供了一种存储器，包括：至少一个如上述方案中任一项所述的半导体结构、位于所述半导体结构上的存储结构以及位于所述半导体结构周边或所述存储结构上方的外围电路。
根据本公开的第三方面，提供了一种存储器的制造方法，包括：
提供衬底；
在所述衬底表面形成沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，所述有源柱包括顶部有源区、沟道区以及底部有源区，所述第一方向与所述第二方向相交且均平行于所述衬 底表面；
形成字线，所述字线沿第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区；
形成介质层，所述介质层位于所述字线与所述有源柱之间且至少覆盖所述沟道区的表面；
形成位线，所述位线沿第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱的所述底部有源区；
其中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和。
上述方案中，形成所述有源柱阵列包括：
对所述衬底顶部进行掺杂形成有源层；以及在所述有源层表面依次形成第一半导体层和第二半导体层；
形成多条沿所述第二方向间隔排布的第一沟槽并在所述第一沟槽中填充第一绝缘材料；
形成多条沿所述第一方向交替间隔排布的第二沟槽和第三沟槽，所述第二沟槽、所述第三沟槽均贯穿所述第一半导体层和所述第二半导体层且延伸至所述有源层中；
去除所述第二沟槽中所述第一半导体层位置处的侧壁，形成第四沟槽；
在所述第四沟槽的侧壁形成第三半导体层，并形成第五沟槽；
从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层，形成第六沟槽；
其中，剩余的所述第二半导体层形成所述有源柱的所述顶部有源区、所述第三半导体层形成所述有源柱的所述沟道区以及剩余的所述有源层形成所述有源柱的所述底部有源区；
在所述第五沟槽和所述第六沟槽中依次形成所述介质层和所述字线。
上述方案中，在所述第五沟槽和所述第六沟槽中依次形成所述介质层和字线，包括：
在形成所述第六沟槽之前，在所述第五沟槽中形成介质层和导电层；以及在形成所述第六沟槽之后，在所述第六沟槽中形成介质层和导电层；或者，在形成所述第六沟槽之后，在所述第五沟槽和所述第六沟槽中同时形成介质层和导电层；
去除部分导电层，并在去除所述部分导电层的位置处形成沿所述第二方向延伸的隔离结构；
其中，剩余的导电层形成所述字线。
上述方案中，所述方法还包括：
在去除所述第二沟槽中所述第一半导体层位置处的侧壁之前，在所述第二沟槽和所述第三沟槽中填充第二绝缘材料；以及
去除所述第二沟槽中的部分所述第二绝缘材料，所述第二沟槽中剩余的所述第二绝缘材料的顶面不高于所述有源层的顶面；
从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层之前，去除所述第三沟槽中的部分所述第二绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料的顶面不高于所述有源层的顶面。
上述方案中，去除所述第二沟槽中所述第一半导体层位置处的侧壁，形成第四构槽，包括：
通过选择性蚀刻工艺，沿所述第一方向去除部分所述第一半导体层。
上述方案中，在所述第四沟槽中形成第三半导体层，包括：
通过外延生长的方式，在所述第四沟槽中形成第三半导体层。
上述方案中，所述第一半导体层与所述第二半导体层的刻蚀选择比不同。
上述方案中，所述第三半导体层的材料和所述第二半导体层的材料相同。
上述方案中，形成所述位线，包括：
在形成第四沟槽之前，在所述第二沟槽及所述第三沟槽的侧壁均形成保护层；
对所述第二沟槽及所述第三沟槽的底部进行刻蚀，以形成凹槽使部分所述第二沟槽及所述第三沟槽的深度增大且所述凹槽在沿所述第一方向上的宽度尺寸大于所述第二沟槽或所述第三沟槽的宽度尺寸；
在所述凹槽中形成第一金属层；
采用热处理工艺，使得所述第一金属层与所述凹槽侧壁的所述有源层反应形成金属化合物层，在所述凹槽中填充第二金属层，所述第二金属层及所述金属化合物层共用形成所述位线。
上述方案中，所述第二沟槽和所述第三沟槽的深度相同，所述第一沟槽的深度大于所述第二沟槽和所述第三沟槽的深度。
本公开各实施例中，沟道区的尺寸小于顶部有源区的尺寸，字线的尺寸不超过顶部有源区的尺寸与介质层的尺寸之和，也就是说，半导体结构中的字线嵌入有源柱且包覆所述有源柱的所述沟道区，相应的有源柱具有类似哑铃型的形状，这样，第一方面可以使得相邻字线之间的距离增加，从而字线之间的耦合更小，字线电性更好；第二方面可以使得字线和有源柱的整体特征尺寸更小，从而进一步 微缩的半导体结构。
附图说明
图1为本公开实施例中提供的一种采用1T1C的架构的控制电路示意图；
图2a为本公开实施例提供的一种半导体结构的立体结构示意图；
图2b为本公开实施例提供的另一种半导体结构的立体结构示意图；
图2c为本公开实施例提供的又一种半导体结构的立体结构示意图；
图2d为本公开实施例提供的再一种半导体结构的立体结构示意图；
图3为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图；
图4a至图4s为本公开实施例提供的一种半导体结构的制造过程的立体结构示意图；
图5a至图5j为本公开实施例提供的另一种半导体结构的制造过程的立体结构示意图；
图6a至图6e为本公开实施例提供的又一种半导体结构的制造过程的立体结构示意图；
图7a至图7e为本公开实施例提供的再一种半导体结构的制造过程的立体结构示意图；
图8a至图8c为本公开实施例提供的又一种半导体结构的制造过程的立体结构示意图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里，所述最终的器件可以包括存储器，所述存储器包括但不限于动态随机存取存储器(DRAM，Dynamic Random Access Memory)，以下仅以动态随机存取存储器为例进行说明。
但需要说明的是，以下实施例关于动态随机存取存储器的描述仅用来说明本公开，并不用来限制本公开的范围。
随着动态随机存取存储器技术的发展，存储单元的尺寸越来越小，其阵列架构由8F 2到6F 2再到4F 2；另外，基于动态随机存取存储器中对离子和漏电流的需求，存储器的架构从平面阵列晶体管(Planar Array Transistor)到凹栅阵列晶体管(Recess Gate Array Transistor)，又从凹栅阵列晶体管到掩埋式沟道阵列晶体管(Buried Channel Array Transistor)，再从掩埋式沟道阵列晶体管到垂直沟道阵列晶体管(Vertical Channel Array Transistor)。
本公开的一些实施例中，不论是平面晶体管还是掩埋式晶体管，动态随机存取存储器均由多个存储单元结构构成，每一个存储单元结构主要是由一个晶体管与一个由晶体管所操控的存储单元(存储电容)构成，即动态随机存取存储器包括1个晶体管(T，Transistor)和1个电容(C，Capacitor)(1T1C)的架构；其主要的作用原理是利用电容内存储电荷的多少来代表一个二进制比特是l还是0。
图1为本公开实施例中提供的一种采用1T1C的架构的控制电路示意图；如图1所示，晶体管T的漏极与位线(BL，Bit Line)电连接，晶体管T的源区与电容C的其中一个电极板电连接，电容C的另外一个电极板可以连接参考电压，所述参考电压可以是地电压也可以是其他电压，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL用于在晶体管T导通时，对所述晶体管T执行读取或写入操作。
然而，为了实现小型化发展，DRAM(以DRAM为例)的尺寸在不断缩小，相关技术中字线WL环绕晶体管T的沟道(Channel)设置，此时，字线WL与字线WL之间间距太小，耦合太大；并且，字线WL的尺寸加上晶体管T的沟道的尺寸太大，很难持续微缩；相关技术中的晶体管受限于尺寸，DRAM难以兼顾高性能。
基于此，为解决上述问题中的一个或多个，本公开实施例提供了一种半导体结构。
图2a至图2d为本公开实施例提供的一些半导体结构的立体结构示意图。
如图2a至图2d所示，本公开实施例提供的一种半导体结构10a、10b、10c、10d，包括：
衬底100；
有源柱AP，位于所述衬底100表面，多个所述有源柱构AP成具有沿第一方向排布的若干列(第一有源柱列CA1、第二有源柱列CA2……)和沿第二方向排布的若干行(第一有源柱行RA1、第二有源柱列RA2……)的有源柱阵列，所述有源柱AP包括顶部有源区TA、沟道区CH以及底部有源区BA，所述第一方向与所述第二方向相交且均平行于所述衬底100表面；
字线WL，沿所述第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区CH；
介质层109，位于所述字线WL与所述有源柱AP之间且至少覆盖所述沟道区CH的表面；
位线BL，沿所述第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱AP的所述底部有源区BA；
其中，在所述第一方向上，所述沟道区的尺寸W1小于所述顶部有源区的尺寸W2，所述字线的尺寸W3不超过所述顶部有源区的尺寸与所述介质层的尺寸之和W4。
需要说明的是，这里及下文中，尺寸W1～W6可以理解为沿所述第一方向上的宽度尺寸或厚度尺寸；长度H1～H6可以理解为沿所述第三方向上的高度尺寸或厚度尺寸。
应当理解，本公开实施例中所示的半导体结构并非排他的，也可以在所示结构特征在不同实施例中的半导体结构之间相互替换；本公开实施例中所示的半导体结构各结构特征可以根据实际需求进行结构、尺寸、位置等的调整。
这里及下文中，所述第一方向和所述第二方向表示为与衬底的表面平行的两个相交方向；第三方向为垂直于衬底的表面的方向，也就是第三方向为所述有源柱的延伸方向；其中，所述衬底的表面可以理解为与所述有源柱的延伸方向垂直的平面。
示例性地，所述第一方向可以表示为附图中的位线BL延伸的方向；所述第二方向可以表示为附图中的字线WL延伸的方向；所述第三方向可以表示为附图中的所述有源柱的延伸方向。但需要说明的是，以下实施例关于所述第一方向、所述第二方向、所述第三方向的描述仅用来说明本公开，并不用来限制本公开的范围。
在一些实施例中，所述第一方向与所述第二方向之间的夹角范围为0-90度。在一些具体实施例中，所述第一方向可以垂直于所述第二方向。可以理解的是，所述第一方向与所述第二方向之间的夹角构建了所述有源柱的沿所述第一方向与所述第二方向的阵列排布的位置关系。
示例性地，所述第一方向可以表示为附图中的X方向；所述第二方向可以表示为附图中的Y方向；所述第三方向可以表示为附图中的Z方向。
本公开实施例中，所述衬底100的材料可以包括硅(Si)、锗(Ge)、硅锗(SiGe)衬底等，还可以为绝缘体上硅(SOI，Silicon-on-insulator)或者绝缘体上锗(GOI，Germanium-on-Insulator)。
本公开实施例中，所述底部有源区BA包括所述衬底的顶部中掺杂有一定的杂质离子的材料。其中，所述杂质离子可以为N型杂质离子或P型杂质离子；在一实施例中，所述掺杂包括阱区掺杂和源漏区掺杂。
本公开实施例中，所述顶部有源区TA和所述沟道区CH的材料相同，均包括具有一定的杂质离子的半导体材料。其中，所述杂质离子可以为N型杂质离子或P型杂质离子；在一实施例中，所述掺杂包括阱区掺杂和源漏区掺杂。
本公开实施例中，所述介质层109的材料包括但不限于二氧化硅。
本公开实施例中，所述字线WL和所述位线BL的材料包括但不限于钨、钴、镍、铜、铝、多晶硅、掺杂硅、硅化物或其任何组合。
继续参考上述图2a至图2d，在一些实施例中，所述字线WL内嵌在所述有源柱AP位于所述沟道区CH的侧壁中且包覆所述沟道区CH沿所述第一方向相对设置的第一侧壁和第二侧壁；
包覆所述第一侧壁的部分字线在沿第三方向上的长度H1与包覆所述第二侧壁的部分字线在沿所述第三方向的长度H2不同；其中，所述第三方向垂直于所述衬底100表面。
如图2a所示，在一些具体实施例中，包覆所述第一侧壁的部分字线在沿第三方向上的长度H1与包覆所述第二侧壁的部分字线在沿所述第三方向的长度H2不同，示例性地，长度H1小于长度H2。这里，包覆所述第一侧壁的部分字线的底面高于包覆所述第二侧壁的部分字线的底面，且包覆所述第一侧壁的部分字线的顶面底于包覆所述第二侧壁的部分字线的顶面。
如图2b所示，在一些具体实施例中，包覆所述第一侧壁的部分字线在沿第三方向上的长度H3与包覆所述第二侧壁的部分字线在沿所述第三方向的长度H4不同，示例性地，长度H3小于长度H4。这里，包覆所述第一侧壁的部分字线的底面和包覆所述第二侧壁的部分字线的底面与所述底部有源区BA的顶面基本齐平，且包覆所述第一侧壁的部分字线的顶面底于包覆所述第二侧壁的部分字线的顶面。
如图2c所示，在一些具体实施例中，包覆所述第一侧壁的部分字线在沿第三方向上的长度与包覆所述第二侧壁的部分字线在沿所述第三方向的长度相同，示例性地，均为长度H5。这里，包覆所述第一侧壁的部分字线的底面和包覆所述第二侧壁的部分字线的底面高于所述底部有源区BA的顶面。在另一些具体实施例中，包覆所述第一侧壁的部分字线在沿第一方向上的尺寸与包覆所述第二侧壁的部分字线在沿所述第一方向的尺寸相同，示例性地，均为尺寸W5；且两倍的尺寸W5与所述沟槽区CH的尺寸之和小于等于所述顶部有源区TA的尺寸。
如图2d所示，在一些具体实施例中，包覆所述第一侧壁的部分字线在沿第三方向上的长度与包覆所述第二侧壁的部分字线在沿所述第三方向的长度相同，示例性地，均为长度H6。这里，包覆所述第一侧壁的部分字线的底面和包覆所述第二侧壁的部分字线的底面与所述底部有源区BA的顶面基本齐平。在另一些具体实施例中，包覆所述第一侧壁的部分字线在沿第一方向上的尺寸与包覆所述第二侧壁的部分字线在沿所述第一方向的尺寸相同，示例性地，均为尺寸W6；且两倍的尺寸W6与所述沟槽区CH的尺寸之和小于等于所述顶部有源区TA的尺寸。
需要说明的是，关于字线在第一方向上的尺寸，由于字线沿所述第二方向延伸且包括环绕所述沟道区的部分和沟道区之间的部分，字线在第一方向上的尺寸沿所述第二方向上并不是处处相等。可以理解的是，对于环绕所述沟道区的部分字线，在沿第一方向上的尺寸不包括被字线环绕的沟道区和介质层在所述第一方向上的尺寸，而仅指的是环绕的沟道区两侧的字线在所述第一方向上的尺寸之和；对于沟道区沿所述第二方向之间的部分字线，在沿第一方向上尺寸，指字线在所述第一方向上的尺寸。
如图2a至图2d所示，在一些实施例中，所述有源柱阵列包括沿所述第一方向交替间隔排布的若干第一有源柱列CA1和第二有源柱列CA2；
与所述第一有源柱列CA1对应的字线WL1和与所述第二有源柱列CA2对应的字线WL2关于所述第二方向对称设置。
这里，所述字线WL1和所述字线WL2关于所述第二方向对称设置可以理解为相邻的所述字线WL1和所述字线WL2关于所述相邻字线之间的沿第二方向延伸的隔离结构204的竖直中心面对称。
示例性地，如图2a和图2b所示，与所述第一有源柱列CA1对应的字线WL1和与所述第二有源柱列CA2对应的字线WL2关于部分隔离结构204(字线WL1和字线WL2之间的隔离结构204)对称设置。
示例性地，如图2c和图2d所示，与所述第一有源柱列CA1对应的字线WL1和与所述第二有源柱列CA2对应的字线WL2关于部分隔离结构204(字线WL1和字线WL2之间的隔离结构204)对称设置，同时，与所述第一有源柱列CA1对应的字线WL1关于所述第一有源柱列CA1对称设置，且与所述第二有源柱列CA2对应的字线WL2关于所述第二有源柱列CA2对称设置。
在一些实施例中，所述沟道区CH与所述顶部有源区TA的交界处，和/或，所述沟道区CH与所述底部有源区BA的交界处为直角、斜角或圆角。这里，所述斜角、所述圆角可以理解为将所述直角分别进行倒角、倒圆角后得到的形状。
在另一些具体实施例中，所述有源柱阵列中的每一有源柱沿垂直于所述第三方向且分别穿过所述顶部有源区TA、所述沟道区CH、所述底部有源区BA的横截面形状可以是矩形、八边形或圆角矩形。这里，所述八边形、所述圆角矩形可以理解为将矩形的四个直角分别进行倒角、倒圆角后得到的形状。
在一些实施例中，所述半导体结构还包括隔离结构204，所述隔离结构204位于相邻的所述有源柱AP之间、相邻的所述字线WL之间以及相邻的所述位线BL之间。
这里，相邻的所述有源柱之间的部分所述隔离结构204作为字线在Z方向上的与外部隔离的第一 子隔离结构；相邻的所述字线之间的部分所述隔离结构204作为隔离字线的第二子隔离结构；相邻的所述位线之间的部分所述隔离结构204作为隔离位线的第三子隔离结构。
如图2a和图2d所示，在一些具体实施例中，所述第一子隔离结构、所述第二子隔离结构、所述第三子隔离结构的材料可以相同或不同。示例性地，所述第一子隔离结构、所述第二子隔离结构、所述第三子隔离结构的材料包括任意一种绝缘材料，例如，氮化硅、氮氧化硅、碳化硅或者二氧化硅。
在一些实施例中，所述位线BL的顶面为平面状(如图2a和图2b所示)或者弧面状(如图2c和图2d所示)。
在一些实施例中，所述位线BL的材料包括金属化合物，或，金属化合物与金属的组合。可以理解的是，所述位线BL包括金属化合物层111，或，金属化合物层111与第二金属层112的组合，其中，所述金属化合物层111的材料包括金属化合物，所述第二金属层112的材料包括金属。
如图2a至图2d所示，在一些具体实施例中，所述位线BL包括金属化合物层111与第二金属层112的组合。示例性地，所述金属化合物层111的材料包括金属钴(Co)化物和/或金属镍(Ni)化物，第二金属层112的材料包括钨(W)。
本公开各实施例中，所述半导体结构中的字线具有如下结构特征：1、字线嵌入有源柱且包覆所述有源柱的所述沟道区，相应的有源柱具有类似哑铃型的形状；这样，相邻字线之间的距离增加，字线之间的耦合更小，使得字线电性更好；同时，可以增大沟道区与字线的接触面积，从而可降低沟道区的高度、增加沟道区的结构稳定性。2、在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和；这样，字线和有源柱的整体特征尺寸更小，可以得到进一步微缩的半导体结构。
本公开实施例提供的一种存储器，包括：至少一个如上述方案中任一项所述的半导体结构、位于所述半导体结构上的存储结构以及位于所述半导体结构周边或所述存储结构上方的外围电路。
这里，所述半导体结构与所述存储单元和所述外围电路耦接；其中，所述外围电路被配置为：接收读或写命令；响应于所述读或写命令，读取或改写所述存储结构所存储的信息。
在一些具体实施例中，所述存储器包括：DRAM，所述存储结构包括：电容；更具体地，所述电容可以包括杯状电容、筒状电容或者柱状电容。
示例性地，所述电容包括柱状的第二电极，覆盖所述第二电极侧壁及底部的电介质，以及覆盖所述电介质的第一电极。实际应用中，可以是所述第二电极端所述有源柱中的所述顶部有源区TA连接，所述第一电极端接参考电压，所述参考电压可以为地电压，也可以包括其它电压。所述电容通过存储在其中的电荷的多和少，来表示逻辑上的“1”和“0”。
图3为本公开实施例提供的一种半导体结构的制造方法的实现流程示意图。如图3所示，本公开实施例提供的一种半导体结构的制造方法，包括以下步骤：
S301、提供衬底；
S302、在所述衬底表面形成沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，所述有源柱包括顶部有源区、沟道区以及底部有源区，所述第一方向与所述第二方向相交且均平行于所述衬底表面；
S303、形成字线，所述字线沿第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区；
S304、形成介质层，所述介质层位于所述字线与所述有源柱之间且至少覆盖所述沟道区的表面；
S305、形成位线，所述位线沿第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱的所述底部有源区；
其中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和。
应当理解，图3中所示的步骤并非排他的，也可以在所示操作中的任何步骤之前、之后或之间执行其他步骤；图3中所示的各步骤可以根据实际需求进行顺序调整。
图4a至图4s为本公开实施例提供的一种半导体结构的制造过程的立体结构示意图。下面结合图3、图4a至图4s，对本公开实施例提供的半导体结构的制作方法进行详细地说明。
执行步骤S301、步骤S302，参考图4a至图4e、图4j至图4l，提供衬底以及形成有源柱阵列。
参考图4a，所述衬底100的材料可以包括硅、锗、硅锗衬底等；所述衬底100的材料还可以为绝缘体上硅或者绝缘体上锗。
参考图4a至图4e、图4j至图4l，在一些实施例中，形成所述有源柱阵列包括以下步骤：
a、对所述衬底顶部进行掺杂形成有源层；以及在所述有源层表面依次形成第一半导体层和第二半导体层；
b、形成多条沿所述第二方向间隔排布的第一沟槽并在所述第一沟槽中填充第一绝缘材料；
c、形成多条沿所述第一方向交替间隔排布的第二沟槽和第三沟槽，所述第二沟槽、所述第三沟 槽均贯穿所述第一半导体层和所述第二半导体层且延伸至所述有源层中；
d、去除所述第二沟槽中所述第一半导体层位置处的侧壁，形成第四沟槽；
e、在所述第四沟槽的侧壁形成第三半导体层，并形成第五沟槽；
f、从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层，形成第六沟槽；
其中，剩余的所述第二半导体层形成所述有源柱的所述顶部有源区、所述第三半导体层形成所述有源柱的所述沟道区以及剩余的所述有源层形成所述有源柱的所述底部有源区；
在所述第五沟槽和所述第六沟槽中依次形成所述介质层和所述字线。
执行步骤a，参考图4b，形成有源层、第一半导体层和第二半导体层。
参考图4b，采用离子注入工艺，对所述衬底100的顶部中掺入一定的杂质离子的材料，形成所述有源层101。其中，所述杂质离子可以为N型杂质离子或P型杂质离子；在一实施例中，所述掺杂源漏区掺杂。示例性地，所述衬底100的材料包括硅，对所述衬底100顶部进行N型重掺杂，形成具有N型重掺杂的有源层101。
继续参考图4b，采用薄膜沉积工艺，在所述有源层101表面依次沉积第一半导体层102和第二半导体层103。
这里，薄膜沉积工艺包括但不限于物理气相沉积(PVD，Physical Vapor Deposition)工艺、化学气相沉积(CVD，Chemical Vapor Deposition)工艺、原子层沉积(ALD，Atomic Layer Deposition)等工艺。
在一些实施例中，所述第一半导体层102可以选择在所述有源层101表面通过外延生长工艺(EGP，Epitaxial Growth Process)形成；所述第二半导体层103可以选择在所述第一半导体层102的表面通过EGP形成。
所述第二半导体层103采用原位掺杂工艺，可以采用包括但不限于PVD、CVD工艺或ALD工艺，在外延生长硅的同时通入含有N型掺杂原子的气体，边沉积外延生长硅同时也进行了N型重掺杂。
在一些实施例中，第一半导体层102与第二半导体层103的刻蚀选择比不同。示例性地，第一半导体层102的材料为硅锗，第二半导体层103的材料为N型重掺杂硅。
在一些具体实施例中，第二半导体层103的材料为N型重掺杂硅，采用原位掺杂工艺形成所述第二半导体层103。可以采用包括但不限于PVD、CVD工艺或ALD工艺，在外延生长硅的同时通入含有N型掺杂原子的气体，边沉积外延生长硅同时也进行了N型重掺杂。
执行步骤b，参考图4c和图4d，形成第一沟槽并填充第一沟槽。
参考图4c，通过光刻-蚀刻工艺(LE，Lithography-Etch)对所述第二半导体层103的顶面进行第一刻蚀，形成多个沿第二方向间隔排布的第一沟槽T1，每一所述第一沟槽T1沿第一方向延伸。这里，在所述第三方向上，所述第一沟槽T1贯穿所述有源层101、所述第一半导体层102和第二半导体层103且延伸至所述衬底100中。所述第一沟槽T1将所述有源层101、所述第一半导体层102和所述第二半导体层103划分为多个沿第一方向延伸的条状结构。
参考图4d，在所述第一沟槽T1中填充第一绝缘材料201；其中，所述第一绝缘材料201的顶面与所述第二半导体层103的顶面基本齐平。
在一些实施例中，所述第一绝缘材料201的组成材料包括但不限于二氧化硅(SiO 2)。
所述第一刻蚀包括但不限于干法等离子体刻蚀工艺。
在一些实施例中，所述第一沟槽T1包括但不限于浅槽隔离(STI，Shallow Trench Isolation)结构。
执行步骤c，参考图4e，形成第二沟槽和第三沟槽。
参考图4e，通过光刻-蚀刻工艺对所述第二半导体层103的顶面进行第二刻蚀，形成多个沿第一方向交替间隔排布的第二沟槽T2和第三沟槽T3，每一所述第二沟槽T2和所述第三沟槽T3沿第二方向延伸。这里，在所述第三方向上，所述第二沟槽T2和所述第三沟槽T3均贯穿所述第一半导体层102和第二半导体层103且延伸至所述有源层101中。所述第二沟槽T2和所述第三沟槽T3将多个条状所述有源层101、所述第一半导体层102和所述第二半导体层103划分为多个沿第一方向和第二方向阵列排布的多个柱状结构。
所述第二刻蚀包括但不限于干法等离子体刻蚀工艺。
在一些具体实施例中，在一些具体实施例中，干法等离子体刻蚀前加硬掩膜层104，用以保护所述第二半导体层103的顶面，减少所述第二半导体层103的顶部被消耗。
所述硬掩膜层104的材料包括但不限于二氧化硅。
在执行步骤c之后，执行步骤d之前，执行步骤S305，形成位线。
参考图4e至图4i，形成的所述位线BL沿第一方向延伸，且电连接沿所述第一方向排布的同一行的所述有源柱AP(参考图4l)的所述底部有源区BA(参考图4l)。
在一些实施例中，形成所述位线，包括：
参考图4e至图4f，在形成第四沟槽之前，在所述第二沟槽T2及第三沟槽T3的侧壁均形成保护层105；
参考图4f至图4g，对所述第二沟槽T2及所述第三沟槽T3的底部进行刻蚀，以形成凹槽T11使部分所述第二沟槽T2及所述第三沟槽T3的深度增大且所述凹槽T11在沿所述第一方向上的宽度尺寸大于所述第二沟槽T2或所述第三沟槽T3的宽度尺寸；
参考图4h，在所述凹槽中形成第一金属层；
采用热处理工艺，使得第一金属层与所述凹槽侧壁的所述有源区反应形成金属化合物层111，在所述凹槽中填充第二金属层112，所述第二金属层112及所述金属化合物层111共用形成所述位线BL。
这里，所采用的刻蚀工艺可以包括湿法刻蚀工艺、干法刻蚀工艺等。
示例性的，所述湿法刻蚀工艺中，以所述保护层105为掩膜，将刻蚀剂通入所述第二沟槽T2及第三沟槽T3的底部，通过刻蚀剂的各向同性刻蚀，增大所述第二沟槽T2及第三沟槽T3的底部沿X轴方向的径宽，所述凹槽T11在沿所述第一方向上的宽度尺寸大于所述第二沟槽T2或所述第三沟槽T3的宽度尺寸，得到具有碗状空间的凹槽T11。这里，可以参考图2c，所述凹槽T11可以理解为沿所述第一方向与所述第二沟槽T2及第三沟槽T3一一对应的多个。这样，参考图2c，在后续的工艺制程中，所述凹槽中形成所述金属化合物层111以及填充第二金属层112，得到由所述第二金属层112和所述金属化合物层111构成的位线BL，且所述金属化合物层111均沿所述第一方向延伸，所述第二金属层112沿所述第一方向被部分所述金属化合物层111间隔。
在另一些具体实施例中，所述湿法刻蚀工艺中，以所述保护层105为掩膜，将刻蚀剂通入所述第二沟槽T2及第三沟槽T3的底部，通过刻蚀剂的各向同性刻蚀，通过过蚀刻方式将所述有源层101的中部蚀开，使得所述第二沟槽T2与第三沟槽T3的底部沿X轴方向上相互连通，得到的凹槽T11为一个整体且沿X-Y平面延伸。这样，可以参考图2d，在后续的工艺制程中，所述凹槽中形成所述金属化合物层111以及填充第二金属层112，得到由所述第二金属层112和所述金属化合物层111构成的位线BL，且所述第二金属层112和所述金属化合物层111均沿所述第一方向延伸。
在一些具体实施例中，所述第一金属层的材料与所述第二金属层的材料可以相同或不同。
示例性地，所述第一金属层的材料与所述第二金属层的材料不同，所述第一金属层的材料可以包括包括：钴、镍、铬、锡、银、金中的至少之一；所述第二金属层112的材料可以包括钨。
示例性地，所述第一金属层的材料与所述第二金属层的材料相同，所述第一金属层和第二金属层112的组成材料均包括钴。
在一些具体实施例中，可以通过PVD、CVD、ALD等工艺在所述凹槽T11中的暴露的所述有源层101上沉积第一金属层；采用热处理工艺，如快速热退火工艺(RTP，Rapid Thermal Process)，使得所述第一金属层与其周围接触的所述有源层101反应形成金属化合物层111；这里，所述金属化合物层111沿第一方向延伸。所述金属化合物层111用于作为位线。
在一些具体实施例中，还可以进一步通过PVD、CVD、ALD等工艺在形成有所述金属化合物的所述凹槽T11中沉积第二金属层112。这样，所述第二金属层112及所述金属化合物层111共用形成所述位线BL。
可以理解的是，所述金属化合物层111用于作为位线BL或者金属化合物层111与第二金属层112共同用于作为位线BL时，均可以使得位线BL与所述有源层101之间形成欧姆接触，利于减小接触电阻。
在一些具体实施例中，位线BL的顶面低于所述有源层101的顶面。示例性地，位线BL全填充凹槽T11，也即所述位线BL的顶面与所述凹槽T11的顶部位置齐平。在一些具体实施例中，所述位线BL的顶面为平面状(如图2a和图2b所示)或者弧面状(如图2c和图2d所示)。
在一些实施例中，在所述凹槽中填充第二金属层112之前，所述方法还包括：在形成有金属化合物层111的所述凹槽中形成扩散阻挡层(未示出)。
这里可以通过PVD、CVD、ALD等工艺在形成有金属化合物层111的所述凹槽中形成扩散阻挡层(未示出)。所述扩散阻挡层用于在形成有扩散阻挡层(未示出)的所述凹槽中形成第二金属层112之后，阻挡所述第二金属层112的材料扩散至所述金属化合物层111、所述有源层101中。
示例性地，所述扩散阻挡层的材料包括氮化钛(TiN)。
参考图4i，在一些实施例中，在凹槽T11中形成位线BL之后，在形成有保护层105的所述第二沟槽T2及第三沟槽T3中填充第二绝缘材料106。
在一些具体实施例中，所述第二绝缘材料106包括但不限于二氧化硅。
继续参考图4h，在一些实施例中，所述第二沟槽T2和所述第三沟槽T3的深度相同，所述第一沟槽T1的深度大于所述第二沟槽T2和所述第三沟槽T3的深度。其中，所述第二沟槽T2和所述第三沟槽T3贯穿所述第一半导体层102和所述第二半导体层103并延伸至所述有源层101中，且所述凹槽T11也位于所述有源层101中；所述第一沟槽T1贯穿所述第一半导体层102和所述第二半导体 层103以及所述有源层101，并延伸至所述衬底中。也就是说，参考图4i，所述位线BL的底面高于所述第一绝缘材料201的底面。这样，所述位线BL与所述第一绝缘材料201沿所述第二方向交替间隔排布；可以保证形成多条被所述第一绝缘材料201隔开而相互独立的位线BL。执行步骤d，参考图4j至图4k，形成第四沟槽。
参考图4j至图4k，采用选择性蚀刻工艺，在所述第二沟槽中沿所述第一方向去除部分所述第一半导体层102。这里，所述选择性蚀刻工艺可以包括原子层蚀刻工艺(ALE，Atomic-Layer Etching)，在一些具体实施例中，所述选择性蚀刻工艺可以包括准原子层蚀刻工艺(qALE，quasi-Atomic-Layer Etching)。
参考图4k，在一些实施例中，去除所述第二沟槽T2中所述第一半导体层102位置处的侧壁，形成第四构槽T4，包括：
通过原子层蚀刻工艺，沿所述第一方向去除部分所述第一半导体层102。
这里，采用ALE或qALE可以精细的去除部分所述第一半导体层102，保证所述第四构槽T4沿所述第一方向上凹进所述第一半导体层102的特征尺寸以及侧壁形貌精准控制，以备后续制程中精准定位所述沟道区的形成位置。
执行步骤e，参考图4l，形成第三半导体层。
参考图4k和图4l，在一些实施例中，在所述第四沟槽T4中形成第三半导体层，包括：
通过外延生长的方式，在所述第四沟槽T4中形成第三半导体层。
这里，依托暴露于所述第四沟槽中的部分所述有源层101的顶面、部分所述第一半导体层102的侧壁、部分所述第二半导体层103的底面和侧壁，通过EGP沉积所述第三半导体层，也得到所述第五沟槽T5(可以理解为具有所述第三半导体层的所述第四沟槽T4)。其中，所述第三半导体层沿所述第一方向和所述第二方向阵列排布，每一所述第三半导体层沿所述第三方向连接所述第一半导体层102和所述第二半导体层103。
其中，剩余的所述第二半导体层103形成所述有源柱AP的所述顶部有源区TA、所述第三半导体层形成所述有源柱的所述沟道区CH以及剩余的所述有源层101形成所述有源柱的所述底部有源区BA。
在一些实施例中，第三半导体层的材料和第二半导体层的材料相同。示例性地，所述第二半导体层103和所述第三半导体层的材料均为N型重掺杂硅(Si)。
执行步骤f，参考图4o，形成第六沟槽。
参考图4o，从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层，形成第六沟槽。需要说明的是，所述去除剩余的所述第一绝缘材料可以理解为至少还包括去除位于沟道区CH之间和所述顶部有源区TA之间的所述第一绝缘材料。在一些具体实施例中，所述第三沟槽中填充绝缘材料(示例性地，参考图4n中的第二绝缘材料106和保护层105)，从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层102，同时也一并去除了所述第三沟槽中部分绝缘材料，所述部分绝缘材料至少包括位于沟道区CH之间和所述顶部有源区TA之间的绝缘材料(示例性地，参考图4n中位于沟道区CH之间和所述顶部有源区TA之间的第二绝缘材料106和保护层105)。
在一些具体实施例中，所述第六沟槽T6的底面与所述第五沟槽T5(参考图4m)的底面齐平或者不齐平。示例性地，所述第六沟槽T6的底面与所述第五沟槽T5(参考图4m)的底面齐平。
这样，所述有源柱AP沿所述第一方向和所述第二方向阵列排布，每一所述有源柱AP包括所述顶部有源区TA、所述底部有源区BA以及沿所述第三方向连接每一所述顶部有源区TA和每一所述底部有源区BA的所述沟道区CH。
这里，所述第五沟槽和所述第六沟槽用于在后续制程中，在所述第五沟槽和所述第六沟槽中依次形成所述介质层和所述字线(详情参考下述图4m至图4n，以及图4o至图4s)。
执行步骤S303、步骤S304，参考图4m至图4n，以及图4o至图4s，形成字线和形成介质层。
在一些实施例中，在所述第五沟槽和所述第六沟槽中依次形成所述介质层和字线，包括：
在形成所述第六沟槽之前，在所述第五沟槽中形成介质层和导电层；以及在形成所述第六沟槽之后，在所述第六沟槽中形成介质层和导电层；
去除部分导电层，并在去除所述部分导电层的位置处形成沿所述第二方向延伸的隔离结构；
其中，剩余的导电层形成所述字线。
这里，可以先在第五沟槽中形成部分介质层和部分导电层，之后再形成第六沟槽，并在第六沟槽中形成部分介质层和部分导电层，然后同步去除第五和第六沟槽中的部分导电层，形成分别位于第五和第六沟槽中的字线。在另一些实施例中，在第五和第六沟槽中同时形成介质层和导电层，然后同步去除第五和第六沟槽中的部分导电层，形成字线。其中，同时形成介质层和导电层，再去除部分导电层之后形成字线的方案具体可以参见后文图6a至图6e，图7a至图7e相关半导体结构的制造过程的 说明。
参考图4m至图4n，在形成所述第六沟槽之前，在所述第五沟槽中形成介质层和导电层。
参考图4m，可以通过原位氧化工艺(ISSG，In Situ Steam Generation)形成所述介质层109。这里，在所述第五沟槽中至少暴露出每一所述沟道区CH的部分侧壁(参考图4l)，可以通过加热或者加压的方式，在所述第五沟槽T5中，至少对每一所述沟道区CH的裸露的侧壁进行原位氧化，形成所述介质层109。所述介质层109的材料包括但不限于二氧化硅。需要说明的是，这里，所述介质层109覆盖部分所述沟道区CH，并非环绕所述沟道区CH的所有侧壁。
示例性地，对每一所述有源柱AP(包括所述沟道区CH)的裸露与所述第五沟槽中的侧壁进行原位氧化，形成所述介质层109。
参考图4n，可以通过PVD工艺、CVD工艺或ALD等工艺在形成了具有介质层109的第五沟槽T5中沉积导电层110。需要说明的是，这里，所述导电层110覆盖部分所述沟道区CH，并非环绕所述沟道区CH的所有侧壁。
这里，所述导电层110的材料可以是金属材料或者半导体导电材料，例如，铜、钴、镍、钨、钼、掺杂硅、多晶硅或其任何组合等。
参考图4o至图4p，在形成所述第六沟槽之后，在所述第六沟槽中形成介质层和导电层。
这里，所述第六沟槽T6中至少暴露出每一所述沟道区CH的另一部分侧壁(可以理解为未被所述第五沟槽T5暴露的其他侧壁)。
在所述第六沟槽中形成介质层和导电层的详细过程可以参考图4m至图4n中在所述第五沟槽中形成介质层和导电层的具体过程，这里不再赘述。
这样，通过在所述第五沟槽和所述第六沟槽中分别形成介质层和导电层，最终形成的所述介质层109可以至少环绕所述沟道区CH的侧壁，形成的所述导电层110可以至少环绕所述介质层109的侧壁。
参考图4q至图4s，形成隔离结构和形成字线。
参考图4q，可以通过光刻-蚀刻工艺去除部分导电层110，形成多个沿所述第一方向间隔排布的第七沟槽T7，所述第七沟槽T7沿所述第三方向贯穿所述导电层110。
这里，如图4q所示，字线WL(参考去除部分导电层110后剩余的导电材料理解)暴露于所述第七沟槽T7的侧壁与包覆介质层109的顶部有源区TA暴露于所述第七沟槽T7的侧壁在所述第三方向上齐平。
在另一些具体实施例中，通过光刻-蚀刻工艺去除部分导电层110的同时，也同步去除了包覆于顶部有源区TA的介质层109(图4q未示出)。这样，字线WL(参考去除部分导电层110后剩余的导电材料理解)暴露于所述第七沟槽T7的侧壁与顶部有源区TA暴露于所述第七沟槽T7的侧壁在所述第三方向上齐平。
所述第一刻蚀包括但不限于干法等离子体刻蚀工艺。
在一些具体实施例中，干法等离子体刻蚀前加硬掩膜层(图4q未示出)，用以保护所述有源柱AP的顶面，减少所述有源柱AP的顶部被消耗，也可增加所述有源柱AP中所述顶部有源区TA的在所述第三方向上的高度。
参考图4r，可以通过PVD工艺、CVD工艺或ALD等工艺在所述第七沟槽T7(参考图4q)中形成沿所述第二方向延伸的隔离结构204。
在一些具体实施例中，所述隔离结构204的材料包括但不限于二氧化硅。
参考图4s，通过回蚀刻工艺，去除部分导电层，并在去除所述部分导电层的位置处形成沿所述第二方向延伸的隔离结构；其中，剩余的导电层形成所述字线。这里，沿所述第三方向回蚀刻的深度与所述有源柱AP中的所述顶部有源区TA沿所述第三方向的高度基本一致。实际应用中，所述基本一致可以理解均为沿所述第三方向回蚀刻的深度与所述有源柱AP中的所述顶部有源区TA沿所述第三方向的高度相同，或者，在工艺误差范围内，沿所述第三方向回蚀刻的深度略微小于或大于所述有源柱AP中的所述顶部有源区TA沿所述第三方向的高度。
在一些具体实施例中，所述隔离结构的材料包括但不限于二氧化硅。
这样，形成的所述字线WL，所述字线WL沿第二方向延伸，包覆沿所述第二方向排布的同一列的所述有源柱AP的所述沟道区CH；形成的所述介质层109，所述介质层109位于所述字线WL与所述有源柱AP之间且至少覆盖所述沟道区CH的表面；其中，在所述第一方向上，所述沟道区的尺寸W1小于所述顶部有源区的尺寸W2，所述字线的尺寸W3不超过所述顶部有源区的尺寸与所述介质层的尺寸之和W4。在另一些具体实施例中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸。
在一些实施例中，所述方法还包括：
在去除所述第二沟槽中所述第一半导体层位置处的侧壁之前，在所述第二沟槽和所述第三沟槽中 填充第二绝缘材料；以及
去除所述第二沟槽中的部分所述第二绝缘材料，所述第二沟槽中剩余的所述第二绝缘材料的顶面低于所述有源层的顶面；
从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层之前，去除所述第三沟槽中的部分所述第二绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料的顶面低于所述有源层的顶面。
需要说明的是，这里，所述第二沟槽中剩余的所述第二绝缘材料的顶面可以低于所述有源层的顶面在另一些实施例中，所述第二沟槽中剩余的所述第二绝缘材料的顶面可以与所述有源层的顶面齐平。其中，齐平的方案具体可以参见后文图5a至图5j相关半导体结构的制造过程的说明。
参考图4i，在去除所述第二沟槽中所述第一半导体层位置处的侧壁之前，在所述第二沟槽和所述第三沟槽中填充第二绝缘材料106；以及
参考图4j去除所述第二沟槽中的部分所述第二绝缘材料106，所述第二沟槽中剩余的所述第二绝缘材料106的顶面低于所述有源层101的顶面；
参考图4n至图4o，从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层102之前，去除所述第三沟槽中的部分所述第二绝缘材料106，所述第三沟槽中剩余的所述第二绝缘材料106的顶面低于所述有源层101的顶面。
在一些实施例中，在所述第二沟槽和所述第三沟槽中填充第二绝缘材料106之前，在所述第二沟槽及第三沟槽的侧壁均形成保护层105；在去除所述第二沟槽中的部分所述第二绝缘材料106的同时也同步去除了所述保护层105，剩余的所述保护层105和所述第二绝缘材料106的顶面低于所述有源层101的顶面。
这里及以下，在所述第二沟槽及第三沟槽的侧壁均形成保护层105以及填充覆盖所述保护层105的第二绝缘材料106为示例进行说明。
在一些具体实施例中，所述保护层105和所述第二绝缘材料106的材料包括但不限于二氧化硅。
这样，可以在所述第五沟槽和所述第六沟槽中暴露出部分所述有源层101顶面的同时也暴露出部分所述有源层101侧壁，以便于后续制程中形成不同形态的字线，例如参考图2a和图2c中形成的字线WL的部分底面不与所述有源层101的顶面齐平。
以上图4h至图4s中示出的字线的形成方式在后文中简称为字线形成方案一。
在一些实施例中，所述方法还包括：
在去除所述第二沟槽中所述第一半导体层位置处的侧壁之前，在所述第二沟槽和所述第三沟槽中填充第二绝缘材料；以及
去除所述第二沟槽中的部分所述第二绝缘材料，所述第二沟槽中剩余的所述第二绝缘材料的顶面与所述有源层的顶面齐平；
从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层之前，去除所述第三沟槽中的部分所述第二绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料的顶面与所述有源层的顶面齐平。
图5a至图5j为本公开实施例提供的另一种半导体结构的制造过程的立体结构示意图。这里，图5a至图5j可以替换图4a至图4s中的图4j至图4s，也就是说，图4a至图4i以及图5a至图5j为本公开实施例提供的另一种半导体结构的制造过程的立体结构示意图。
这里，所述第二沟槽中剩余的所述第二绝缘材料的顶面与所述有源层的顶面齐平，以下结合图4a至图4i以及图5a至图5j，详细说明所述第三沟槽中剩余的所述第二绝缘材料的顶面与所述有源层的顶面齐平时，形成字线的方案(以下简称字线形成方案二)。
图5a至图5j中的制造过程详情与图4j至图4s中的制造过程相似的部分，这里不再赘述；这里及下文着重说明图5a至图5j与图4j至图4s中的区别。
参考图5a，相较于图4j，去除所述第二沟槽中的部分所述第二绝缘材料106，所述第二沟槽中剩余的所述第二绝缘材料106的顶面与所述有源层101的顶面齐平。
参考图5b，相较于图4k，去除部分所述第一半导体层102，暴露出部分所述有源层101的顶面，部分所述有源层101的顶面与所述第二沟槽中剩余的所述第二绝缘材料106的顶面齐平。
参考图5c，相较于图4l，形成所述沟道区CH，在所述第五沟槽T5中，相对的两个所述沟道区CH底部(所述沟道区CH与所述底部有源区BA交界处)之间的距离小于相对的两个所述沟道区CH顶部(所述沟道区CH与所述顶部有源区TA交界处)之间的距离。
参考图5d至图5e，相较于图4m和图4n，形成所述介质层109和所述导电层110的方法相同。
参考图5f，相较于图4o，去除所述第三沟槽中的部分所述第二绝缘材料106，所述第三沟槽中剩余的所述第二绝缘材料106的顶面与所述有源层101的顶面齐平。
以及，去除剩余的所述第一半导体层102(参考图5e)，暴露出剩余的所述沟道区CH的顶面、 剩余的所述顶部有源区TA的顶面、部分所述底部有源区BA的顶面。
参考图5f至图5g，相较于图4o和图4p，形成所述介质层109和所述导电层110的方法相同。
参考图5h至图5j，相较于图4q至图4s，形成所述字线WL，所述字线WL的底面至少部分与所述底部有源区BA的顶面齐平。其中，图5j与图4s中所述字线WL具体区别可以参照上述图2a和图2b中的字线WL的区别进行理解，这里不再赘述。
这里，形成字线方案二，相较于形成字线方案一，形成的所述字线WL在所述第三方向上的高度不同，相对而言形成字线方案二形成的所述字线WL在所述第三方向上的高度更高，可以增大沟道区与字线的接触面积，从而降低沟道区的高度、增加沟道区的结构稳定性。
在一些实施例中，在所述第五沟槽和所述第六沟槽中依次形成所述介质层和字线，包括：
在形成所述第六沟槽之后，在所述第五沟槽和所述第六沟槽中同时形成介质层和导电层；
去除部分导电层，并在去除所述部分导电层的位置处形成沿所述第二方向延伸的隔离结构；
其中，剩余的导电层形成所述字线。
图6a至图6e为本公开实施例提供的又一种半导体结构的制造过程的立体结构示意图。这里，图6a至图6e可以替换图4a至图4s中的图4l至图4s，也就是说，图4a至图4k以及图6a至图6e为本公开实施例提供的又一种半导体结构的制造过程的立体结构示意图。
这里，在形成所述第六沟槽之后，在所述第五沟槽和所述第六沟槽中同时形成介质层和导电层，以下结合图4a至图4k以及图6a至图6e，详细说明在所述第五沟槽和所述第六沟槽中同时形成介质层和导电层，形成字线的方案(以下简称字线形成方案三)。
在前述图4k的基础上，继续参考图6a至图6b，在所述第四沟槽T4中形成所述沟道区CH之后，去除所述第三沟槽中的部分所述第二绝缘材料106、部分所述第一绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料106的顶面低于所述有源层101的顶面且与所述第二沟槽中剩余的所述第二绝缘材料106的顶面齐平。
以及，去除剩余的所述第一半导体层102，暴露出全部所述沟道区CH的侧壁、全部所述顶部有源区TA的侧壁、部分所述底部有源区BA的顶面和侧壁，也就是说所述有源柱AP之间的间隙贯通为一个整体间隙空间T12，相当于图4l至图4p中所述第五沟槽T5和所述第六沟槽一起形成且相互贯通形成为一个整体间隙空间T12。
参考图6c，在所述间隙空间T12中，可以通过一次原位氧化工艺就形成至少环绕所述有源区CH的所述介质层109。
参考图6d，在形成有所述介质层109的所述间隙空间T12中，可以通过一次沉积工艺就形成至少环绕所述介质层109的所述导电层110。而在图4l至图4p中，是通过分别在所述第五沟槽T5和所述第六沟槽T6中各进行一次原位氧化工艺形成至少环绕所述有源区CH的所述介质层109以及各进行一次沉积工艺形成至少环绕所述介质层109的所述导电层110。
参考图6d至图6e，与图4q至图4s中形成所述隔离结构204和所述字线的方法相同，这里不再赘述。
这里，形成字线方案三，相较于形成字线方案一或方案二，形成的所述字线WL通过一次原位氧化工艺就形成至少环绕所述有源区CH的所述介质层109以及一次沉积工艺形成至少环绕所述介质层109的所述导电层110。具有工艺流程简化的优点。
图7a至图7e为本公开实施例提供的再一种半导体结构的制造过程的立体结构示意图。图7a至图7e与图6a至图6e为相同类型的半导体结构的制造过程的变形示例(以下简称字线形成方案四)。
参考图7a，相较于参考图6a，在所述第四沟槽T4中形成所述沟道区CH之后，去除所述第三沟槽中的部分所述第二绝缘材料106、部分所述第一绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料106的顶面与所述第二沟槽中剩余的所述第二绝缘材料106的顶面齐平且与所述有源层101的顶面齐平。
这里，方案三和方案四均在形成所述第六沟槽之后，在所述第五沟槽和第六沟槽中同时形成介质层和导电层；而方案四与方案三的区别包括：所述第二沟槽和所述第三沟槽中剩余的所述第二绝缘材料106的顶面所述有源层101的顶面的相对位置不同。
图7a至图7e提供的半导体结构的制造方法制造得到的半导体结构与图6a至图6e提供的半导体结构的制造方法制造得到的半导体结构的具体差别可以参考图2a与图2b的具体差别进行理解，这里不再赘述。
前述的实施例中，在所述第五沟槽和所述第六沟槽中形成的字线沿所述第三方向的长度不相同，在另一些实施例，在所述第五沟槽和所述第六沟槽中形成的字线沿所述第三方向的长度可以相同，具体地：
在前述图4a至图4n的基础上，继续参考图8a至图8c，在另一些实施例中，在形成所述介质层109之前，所述方法还包括：
参考图8a，去除所述第三沟槽T3(参考图4n)中的部分所述第二绝缘材料106(参考图4n)，以及，去除剩余的所述第一半导体层102(参考图4n)，暴露出剩余的所述沟道区CH的顶面、剩余的所述顶部有源区TA的顶面、部分所述底部有源区BA的顶面；
参考图8b，依托暴露于所述第六沟槽中的部分所述底部有源区BA的顶面、部分所述沟道区CH的侧壁、部分所述顶部有源区TA的底面和侧壁，通过EGP沉积所述第三半导体层。
参考图8c，在所述第六沟槽之中过EGP沉积所述第三半导体层之后，在所述第六沟槽中形成介质层109，使得所述沟道区CH对称。
这里，所述沟道区CH对称是指所述沟道区CH关于经过沟道区CH中心的Y-Z平面对称，和/或，关于经过沟道区CH中心的X-Y平面对称。所述介质层109也可以对称，所述介质层109对称是指所述介质层109关于经过沟道区CH中心的Y-Z平面对称，和/或，关于经过沟道区CH中心的X-Y平面对称。
以及，在形成所述第六沟槽之后，在所述第六沟槽中形成介质层、导电层，以及去除部分导电层形成字线。具体详情可以继续参考图4o至图4s，这里不再赘述。
这里，最终可以形成的半导体结构如图2c和图2d所示，所述字线WL关于经过沟道区CH中心的Y-Z平面对称，和/或，关于经过沟道区CH中心的X-Y平面对称。图2c和图2d区别是，图2c所示的字线WL沿所述第三方向的高度小于所述图2d所示的字线WL沿所述第三方向的高度。
本公开各实施中，所述半导体结构的制造方法，采用外延生长工艺形成作为牺牲层的第一半导体层；以及通过去除第一半导体层，在去除第一半导体层的位置处外延生长形成沟道区；再由自对准工艺形成包覆所述沟道区的字线。所述半导体结构的制造方法制造得到的字线WL具有如下结构特征：1、如图2a至图2d所示，字线WL嵌入有源柱AP中，相应的有源柱AP类似哑铃型，即在所述第一方向上，所述沟道区的尺寸W1小于所述顶部有源区的尺寸W2，所述字线的尺寸W3不超过所述顶部有源区的尺寸与所述介质层的尺寸之和W4，这样相邻字线WL之间的距离增加，寄生电容更小，电性更好；2、全包围式环绕所述沟道区CH的字线WL沿所述第三方向上的长度可以不相等或者相等，具有非对称结构(如图2a和图2b所示)或对称结构(如图2c和图2d所示)。
也就是说，全包围式环绕所述沟道区CH的字线WL中，包覆所述第一侧壁的字线和包覆所述第二侧壁的字线的长度、宽度等存尺寸可以分别独立设置，这样所述字线WL内嵌在所述沟道区CH的侧壁中，增大沟道区CH与字线WL的接触面积，可降低所述沟道区CH高度，降低字线WL与晶体管T的沟道的整体尺寸，用以实现晶体管尺寸的持续微缩，从而提DRAM的性能；与此同时，所述字线WL的结构、尺寸具有可调节性，具有较好的工艺适用性。
本公开实施例提供的半导体结构的制造方法制造得到的半导体结构与上述实施例中的半导体结构类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开各实施例中，沟道区的尺寸小于顶部有源区的尺寸，字线的尺寸不超过顶部有源区的尺寸与介质层的尺寸之和，也就是说，半导体结构中的字线嵌入有源柱且包覆所述有源柱的所述沟道区，相应的有源柱具有类似哑铃型的形状，这样，第一方面可以使得相邻字线之间的距离增加，从而字线之间的耦合更小，字线电性更好；第二方面可以使得字线和有源柱的整体特征尺寸更小，从而进一步微缩的半导体结构。

Claims (17)

  1. 一种半导体结构，包括：
    衬底；
    有源柱，位于所述衬底表面，多个所述有源柱构成具有沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，所述有源柱包括顶部有源区、沟道区以及底部有源区，所述第一方向与所述第二方向相交且均平行于所述衬底表面；
    字线，沿所述第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区；
    介质层，位于所述字线与所述有源柱之间且至少覆盖所述沟道区的表面；
    位线，沿所述第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱的所述底部有源区；
    其中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和。
  2. 根据权利要求1所述的半导体结构，其中，所述字线内嵌在所述有源柱位于所述沟道区的侧壁中且包覆所述沟道区沿所述第一方向相对设置的第一侧壁和第二侧壁；
    包覆所述第一侧壁的部分字线在沿第三方向上的长度与包覆所述第二侧壁的部分字线在沿所述第三方向的长度不同；其中，所述第三方向垂直于所述衬底表面。
  3. 根据权利要求2所述的半导体结构，其中，所述有源柱阵列包括沿所述第一方向交替间隔排布的若干第一有源柱列和第二有源柱列；
    与所述第一有源柱列对应的字线和与所述第二有源柱列对应的字线关于所述第二方向对称设置。
  4. 根据权利要求1所述的半导体结构，其中，所述沟道区与所述顶部有源区的交界处，和/或，所述沟道区与所述底部有源区的交界处为直角、斜角或圆角。
  5. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括隔离结构，所述隔离结构位于相邻的所述有源柱之间、相邻的所述字线之间以及相邻的所述位线之间。
  6. 根据权利要求1所述的半导体结构，其中，所述位线的材料包括金属化合物，或，金属化合物与金属的组合。
  7. 一种存储器，包括：至少一个如权利要求1至6中任一项所述的半导体结构、位于所述半导体结构上的存储结构以及位于所述半导体结构周边或所述存储结构上方的外围电路。
  8. 一种半导体结构的制造方法，包括：
    提供衬底；
    在所述衬底表面形成沿第一方向排布的若干列和沿第二方向排布的若干行的有源柱阵列，所述有源柱包括顶部有源区、沟道区以及底部有源区，所述第一方向与所述第二方向相交且均平行于所述衬底表面；
    形成字线，所述字线沿第二方向延伸，包覆沿所述第一方向排布的同一列的所述有源柱的所述沟道区；
    形成介质层，所述介质层位于所述字线与所述有源柱之间且至少覆盖所述沟道区的表面；
    形成位线，所述位线沿第一方向延伸，且电连接沿所述第二方向排布的同一行的所述有源柱的所述底部有源区；
    其中，在所述第一方向上，所述沟道区的尺寸小于所述顶部有源区的尺寸，所述字线的尺寸不超过所述顶部有源区的尺寸与所述介质层的尺寸之和。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，形成所述有源柱阵列包括：
    对所述衬底顶部进行掺杂形成有源层；以及在所述有源层表面依次形成第一半导体层和第二半导体层；
    形成多条沿所述第二方向间隔排布的第一沟槽并在所述第一沟槽中填充第一绝缘材料；
    形成多条沿所述第一方向交替间隔排布的第二沟槽和第三沟槽，所述第二沟槽、所述第三沟槽均贯穿所述第一半导体层和所述第二半导体层且延伸至所述有源层中；
    去除所述第二沟槽中所述第一半导体层位置处的侧壁，形成第四沟槽；
    在所述第四沟槽的侧壁形成第三半导体层，并形成第五沟槽；
    从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层，形成第六沟槽；
    其中，剩余的所述第二半导体层形成所述有源柱的所述顶部有源区、所述第三半导体层形成所述有源柱的所述沟道区以及剩余的所述有源层形成所述有源柱的所述底部有源区；
    在所述第五沟槽和所述第六沟槽中依次形成所述介质层和所述字线。
  10. 根据权利要求9所述的半导体结构的制造方法，其中，在所述第五沟槽和所述第六沟槽中依次形成所述介质层和字线，包括：
    在形成所述第六沟槽之前，在所述第五沟槽中形成介质层和导电层；以及在形成所述第六沟槽之后，在所述第六沟槽中形成介质层和导电层；或者，在形成所述第六沟槽之后，在所述第五沟槽和所述第六沟槽中同时形成介质层和导电层；
    去除部分导电层，并在去除所述部分导电层的位置处形成沿所述第二方向延伸的隔离结构；
    其中，剩余的导电层形成所述字线。
  11. 根据权利要求9所述的半导体结构的制造方法，其中，所述方法还包括：
    在去除所述第二沟槽中所述第一半导体层位置处的侧壁之前，在所述第二沟槽和所述第三沟槽中填充第二绝缘材料；以及
    去除所述第二沟槽中的部分所述第二绝缘材料，所述第二沟槽中剩余的所述第二绝缘材料的顶面不高于所述有源层的顶面；
    从所述第三沟槽中去除剩余的所述第一绝缘材料以及剩余的所述第一半导体层之前，去除所述第三沟槽中的部分所述第二绝缘材料，所述第三沟槽中剩余的所述第二绝缘材料的顶面不高于所述有源层的顶面。
  12. 根据权利要求9所述的半导体结构的制造方法，其中，去除所述第二沟槽中所述第一半导体层位置处的侧壁，形成第四构槽，包括：
    通过选择性蚀刻工艺，沿所述第一方向去除部分所述第一半导体层。
  13. 根据权利要求9所述的半导体结构的制造方法，其中，在所述第四沟槽中形成第三半导体层，包括：
    通过外延生长的方式，在所述第四沟槽中形成第三半导体层。
  14. 根据权利要求9所述的半导体结构的制造方法，其中，所述第一半导体层与所述第二半导体层的刻蚀选择比不同。
  15. 根据权利要求9所述的半导体结构的制造方法，其中，所述第三半导体层的材料和所述第二半导体层的材料相同。
  16. 根据权利要求9所述的半导体结构的制造方法，其中，形成所述位线，包括：
    在形成所述第四沟槽之前，在所述第二沟槽及所述第三沟槽的侧壁均形成保护层；
    对所述第二沟槽及所述第三沟槽的底部进行刻蚀，以形成凹槽使部分所述第二沟槽及所述第三沟槽的深度增大且所述凹槽在沿所述第一方向上的宽度尺寸大于所述第二沟槽或所述第三沟槽的宽度尺寸；
    在所述凹槽中形成第一金属层；
    采用热处理工艺，使得所述第一金属层与所述凹槽侧壁的所述有源层反应形成金属化合物层，在所述凹槽中填充第二金属层，所述第二金属层及所述金属化合物层共用形成所述位线。
  17. 根据权利要求16所述的半导体结构的制造方法，其中，所述第二沟槽和所述第三沟槽的深度相同，所述第一沟槽的深度大于所述第二沟槽和所述第三沟槽的深度。
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