WO2022048217A1 - 半导体结构及其制作方法、控制方法 - Google Patents

半导体结构及其制作方法、控制方法 Download PDF

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Publication number
WO2022048217A1
WO2022048217A1 PCT/CN2021/097909 CN2021097909W WO2022048217A1 WO 2022048217 A1 WO2022048217 A1 WO 2022048217A1 CN 2021097909 W CN2021097909 W CN 2021097909W WO 2022048217 A1 WO2022048217 A1 WO 2022048217A1
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WIPO (PCT)
Prior art keywords
insulator
source
base substrate
semiconductor structure
bit line
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Application number
PCT/CN2021/097909
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English (en)
French (fr)
Inventor
陈涛
施志成
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21773442.5A priority Critical patent/EP3985672B1/en
Priority to US17/391,195 priority patent/US11871554B2/en
Publication of WO2022048217A1 publication Critical patent/WO2022048217A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present disclosure relates to the field of storage technologies, and in particular, to a semiconductor structure, a fabrication method and a control method thereof.
  • a memory is usually composed of a plurality of storage cells, and each storage cell includes a switching transistor and a capacitor.
  • a memory typically provides an off signal to the gate of the switching transistor through a word line, and the source/drain of the switching transistor is connected through a bit line to provide a logic "1" or "0" to the capacitor through the switching transistor.
  • the memory integrates word lines, bit lines, switching transistors, and capacitors on the same semiconductor structure.
  • the integration density of the switching transistors in the semiconductor structure is low, which affects the memory cells in the unit-size semiconductor structure. number of.
  • a semiconductor structure including: a base substrate, a plurality of bit lines, a plurality of active bodies, an insulator, and a plurality of word lines.
  • the insulator is located on one side of the base substrate; a plurality of bit lines are arranged in the insulator, and the plurality of bit lines are spaced along the first direction and extend in the second direction; a plurality of active bodies are located in the insulator , the active body is located on the side of the bit line away from the base substrate, the orthographic projection of the active body on the base substrate at least partially coincides with the orthographic projection of the bit line on the base substrate, and along the second direction spaced distribution; a plurality of word lines are located in the insulator and located on the side of the bit line away from the base substrate, the word lines are spaced apart along the second direction and extend along the first direction, and Only one word line is arranged between two adjacent active bodies in the second direction.
  • the active body includes: a first source/drain part, an active part, and a second source/drain part.
  • the first source/drain part is located at the side of the bit line away from the base substrate; the active part is located at the side of the first source/drain part away from the base substrate; the second source/drain part is located at the side of the first source/drain part away from the base substrate A side of the active portion facing away from the base substrate.
  • the insulator further includes: the insulator includes: a first insulator, a second insulator, and a third insulator.
  • a first insulator is located between the word line and the active body; a second insulator is located on a side of the word line away from the base substrate; and a third insulator is located between the word line and the bit line.
  • the material of the first insulator is silicon oxide
  • the material of the second insulator is silicon nitride
  • the first direction and the second direction are perpendicular.
  • bit line and the base substrate are insulated by a part of the insulator.
  • the material of the first source/drain portion and the second source/drain portion is a doped polysilicon conductor, and the material of the active portion is polysilicon.
  • the semiconductor structure further includes a first conductor part and a second conductor part, the first conductor part is located between the bit line and the first source/drain part; the second conductor part The second source/drain portion is located on a side of the second source/drain portion away from the base substrate.
  • a method for fabricating a semiconductor structure comprising:
  • the body to be etched includes a base substrate, an insulator located on one side of the base substrate, and a plurality of bit lines, the bit lines are located in the insulator and a plurality of the bit lines spaced apart along the first direction and extending along the second direction;
  • a word line and a fourth insulating layer are sequentially formed in the second groove, and the fourth insulating layer is located on the side of the word line away from the bottom of the second groove;
  • a plurality of through holes distributed in an array are formed on the side of the insulator facing away from the base substrate, and the orthographic projection of the through holes on the base substrate and the orthographic projection of the bit lines on the base substrate are at least at least Partly coincident, the through hole extends to the surface of the bit line facing the through hole, and the orthographic projection of the through hole on the base substrate is located in two adjacent word lines on the substrate Between the orthographic projections of the substrate, and in the second direction, there is only one orthographic projection of the word line on the substrate substrate between the two adjacent through holes on the substrate substrate. ;
  • a first source/drain part, an active part, and a second source/drain part are formed in the through hole, the first source/drain part is located on one side of the bit line, and the active part is located on the The first source/drain portion is located at a side away from the bit line, and the second source/drain portion is located at a side of the active portion away from the bit line.
  • forming a body to be etched includes:
  • one side of the substrate material layer is formed with a plurality of first grooves distributed along the first direction and extending along the second direction;
  • a first insulating layer, a bit line, and a second insulating layer are formed in the first groove, the bit line is located on the side of the first insulating layer away from the bottom of the first groove, and the second insulating layer the layer is located on the side of the bit line away from the bottom of the first groove;
  • first source/drain part, an active part, and a second source/drain part in the through hole before forming a first source/drain part, an active part, and a second source/drain part in the through hole, it further includes:
  • first conductor portion in the through hole, the first conductor portion being located between the bit line and the first source/drain portion;
  • a first source/drain part, an active part, and a second source/drain part are formed in the through hole, and the following further includes:
  • a second conductor portion is formed in the through hole, and the second conductor portion is located on a side of the second source/drain portion away from the base substrate.
  • a semiconductor structure control method for controlling the above-mentioned semiconductor structure comprising:
  • the active body located between the two word lines is turned on.
  • FIG. 1 is a top perspective view of an exemplary embodiment of the disclosed semiconductor structure
  • Fig. 2 is a sectional view along the dotted line A-A in Fig. 1;
  • Fig. 3 is a sectional view along the dotted line end B-B in Fig. 1;
  • FIG. 4 is a top perspective view of another exemplary embodiment of the disclosed semiconductor structure
  • Fig. 5 is a sectional view along the dotted line A-A in Fig. 1;
  • Fig. 6 is a sectional view along the dotted line end B-B in Fig. 1;
  • FIG. 7 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Fig. 8 is the sectional view of dotted line A-A in Fig. 7;
  • Fig. 9 is the sectional view of dotted line B-B in Fig. 7;
  • 10, 13, 16, 19, 22, and 25 are top views of semi-finished semiconductor structures in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 11 is a sectional view of the broken line A-A in Figure 10;
  • Figure 12 is a sectional view of the dotted line B-B in Figure 10;
  • Figure 14 is a cross-sectional view of the dotted line A-A in Figure 13;
  • Figure 15 is a cross-sectional view of the broken line B-B in Figure 13;
  • Figure 17 is a cross-sectional view of the broken line A-A in Figure 16;
  • Figure 18 is a cross-sectional view taken along the dotted line B-B in Figure 16;
  • Figure 20 is a cross-sectional view of the broken line A-A in Figure 19;
  • Figure 21 is a cross-sectional view of the broken line B-B in Figure 19;
  • Figure 23 is a cross-sectional view of the broken line A-A in Figure 22;
  • Figure 24 is a cross-sectional view of the broken line B-B in Figure 22;
  • Figure 26 is a cross-sectional view of the broken line A-A in Figure 25;
  • Figure 27 is a cross-sectional view of the broken line B-B in Figure 25;
  • 28 and 31 are top views of semi-finished semiconductor structures in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 29 is a cross-sectional view of the broken line A-A in Figure 28;
  • Figure 30 is a cross-sectional view of the dotted line B-B in Figure 28;
  • Figure 32 is a cross-sectional view of the broken line A-A in Figure 31;
  • Figure 33 is a cross-sectional view of the broken line B-B in Figure 31;
  • 34 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 35 is a cross-sectional view of the broken line A-A in Figure 34;
  • Figure 36 is a sectional view taken along the dotted line B-B in Figure 34;
  • FIG. 37 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 38 is a sectional view taken along the dotted line A-A in Figure 37;
  • Figure 39 is a cross-sectional view of the broken line B-B in Figure 37;
  • FIG. 40 is a top perspective view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 41 is a cross-sectional view of the dotted line A-A in Figure 40;
  • Figure 42 is a cross-sectional view of the broken line B-B in Figure 40;
  • FIG. 43 is a top perspective view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 44 is a cross-sectional view of the broken line A-A in Figure 43;
  • Figure 45 is a cross-sectional view of the broken line B-B in Figure 43;
  • 46 is a top perspective view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method
  • Figure 47 is a cross-sectional view of the broken line A-A in Figure 46;
  • FIG. 48 is a cross-sectional view taken along the dotted line B-B in FIG. 46 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a top perspective view of an exemplary embodiment of the disclosed semiconductor structure
  • FIG. 2 is a cross-sectional view along the dotted line AA in FIG. 1
  • FIG. 3 is a cross-sectional view along the BB dotted line in FIG. 1
  • the semiconductor structure may include: a base substrate 1 , a plurality of bit lines 2 , a plurality of active bodies 5 , an insulator 3 , and a plurality of word lines 4 .
  • the insulator 3 is located on one side of the base substrate 1; a plurality of bit lines 2 are arranged in the insulator 3, and the plurality of bit lines 2 are distributed along the first direction X and extend along the second direction Y; Each active body 5 is located in the insulator 3 , the active body 5 is located on the side of the bit line 2 away from the base substrate 1 , and the orthographic projection of the active body 5 on the base substrate 1 is on the side of the bit line 2 .
  • the orthographic projections of the base substrate at least partially overlap, and are spaced along the second direction Y; a plurality of word lines 4 are located in the insulator 3 and are located at a position of the bit line 2 away from the base substrate 1 .
  • the word lines 4 are distributed along the second direction Y at intervals and extend along the first direction X, and only one word line 4 is disposed between two adjacent active bodies 5 in the second direction Y .
  • the word line 4 may be insulated from the active body 5 and the bit line 2 by part of the insulator 3 .
  • the active body 5 may include: a first source/drain part 51 , an active part 52 , and a second source/drain part 53 .
  • the first source/drain portion 51 may be located on the side of the bit line 2 away from the base substrate 1 ; the active portion 52 may be located at the side of the first source/drain portion 51 away from the base substrate 1 ;
  • the second source/drain portion 53 may be located on the side of the active portion 52 away from the base substrate 1 .
  • the active body 5 may form the source/drain and channel regions of a switching transistor, and part of the word line 4 may form the gate of the switching transistor.
  • each memory cell may include a switching transistor and a capacitor.
  • the semiconductor structure provided by the present disclosure only one word line 4 is disposed between two adjacent active bodies 5 in the second direction Y, and by simultaneously inputting a turn-on signal to two adjacent word lines 4, A conductive channel is formed on the active part 52 of the active body 5 between the two word lines, so as to conduct the first source/drain part 51 and the second source/drain part 53 at both ends of the active body 5, that is, to conduct A switching transistor formed through the active body 5 .
  • the semiconductor structure provided by the present disclosure can reduce the distance between two adjacent active bodies in the second direction, thereby improving the active body of the semiconductor structure.
  • the integration density of the body 5, that is, the integration density of the memory cells on the semiconductor structure is increased.
  • the orthographic projection of the active portion 52 on the plane where the word line 4 is located may be located on the word line 4 .
  • the plane where the word line 4 is located means parallel to the extending direction of the word line 4 , that is, the plane parallel to the BB section line in Figure 1. Part of the word line 4 can thus be used to form the gate of the switching transistor.
  • the bit line 2 may be in contact with the base substrate 1 .
  • the insulator 3 may include: a first insulator 31 , a second insulator 32 , and a third insulator 33 .
  • the first insulator 31 can be located between the word line 4 and the active body 5; the second insulator 32 can be located on the side of the word line 4 away from the base substrate 1; the third insulator 33 can be located on the word line 4 and the bit line.
  • the hardness of the second insulator 32 may be greater than the hardness of the first insulator 31 and the third insulator 33 .
  • the second insulator 32 is located on the upper surface of the semiconductor structure.
  • the second insulator 32 can protect the structure of bit lines, word lines and switching transistors inside the semiconductor structure.
  • the second insulator 32 is set to a hardness of A larger material can improve the protection capability of the second insulator 32 .
  • the first insulator 31 may serve as a gate insulating layer of the switching transistor.
  • the third insulator 33 is used to electrically isolate the word lines and bit lines.
  • the material of the first insulator 31 and the third insulator 33 may be silicon oxide, and the material of the second insulator 32 may be silicon nitride.
  • the first insulator 31, the second insulator 32, and the third insulator 33 may also be formed of other insulating materials, for example, the first insulator 31, the second insulator 32, the third insulator 33 33 may be formed of one material.
  • the active bodies 5 are distributed in an array along the first direction X and the second direction Y.
  • the active bodies 5 can be distributed in rows and columns, so as to achieve the maximum integration density.
  • the first direction X and the second direction Y may be vertical, so that the integration density of the memory cells on the semiconductor structure can be further increased.
  • the material of the bit line and the word line may be metal tungsten.
  • the material of the first source/drain portion and the second source/drain portion may be doped polysilicon conductors, and the material of the active portion may be polysilicon.
  • the materials of the bit line, the word line, the first source/drain portion, the second source/drain portion, and the active portion may also be other materials.
  • the bit lines and word lines may be metals such as titanium nitride, copper, silver, and the like.
  • the material of the active part can also be metal oxide semiconductor, germanium, gallium arsenide, amorphous silicon semiconductor, etc.
  • the first source/drain part and the second source/drain part can be made of the semiconductor material forming the active part doping formation.
  • the doping type can be N-type doping or P-type doping
  • the doping ions can be boron ions, bismuth ions, germanium ions, cobalt ions, phosphorus ions, and the like.
  • the resistance value of the active part can also be adjusted by lightly doping the active part.
  • FIG. 4 is a top perspective view of another exemplary embodiment of the disclosed semiconductor structure
  • FIG. 5 is a cross-sectional view along the dashed line AA in FIG. 1
  • FIG. 6 is a dashed line BB in FIG. 1 . End cutaway view.
  • the bit line 2 and the base substrate 1 may be insulated by a part of the insulator 3 .
  • the method for forming the first source/drain portion 51 and the second source/drain portion 53 is generally to form a semiconductor material first, and perform ion doping on both sides of the semiconductor material to form the first source/drain portion part 51 and second source/drain part 53 .
  • the doped ions may affect the dielectric constant of the insulating layers on both sides of the semiconductor material.
  • the doped ions may increase the dielectric constant of the insulator 3 .
  • the semiconductor structure may further include a first conductor portion 71 and a second conductor portion 72 , and the first conductor portion 71 may be located between the bit line 2 and the first conductor portion 71 . Between a source/drain portion 51 ; the second conductor portion 72 may be located on the side of the second source/drain portion 53 away from the base substrate 1 . As shown in FIG. 5 , this arrangement can reduce the size of the first source/drain portion 51 and the second source/drain portion 53 in the stacking direction, thereby reducing the range of particle doping of the insulator.
  • the first conductor portion 71 can be used as a bit line contact plug, and the second conductor portion 72 can be used as a capacitor contact plug.
  • the present exemplary embodiment also provides a method for fabricating a semiconductor structure, which can form the above-mentioned semiconductor structure.
  • the method can include:
  • Step S1 forming a to-be-etched body, the to-be-etched body includes a base substrate, an insulator located on one side of the base substrate, and a plurality of bit lines, the bit lines are located in the insulator and a plurality of all the bit lines are formed. the bit lines are spaced along the first direction and extend along the second direction;
  • Step S2 forming a plurality of second grooves spaced along the second direction and extending along the first direction on the side of the insulator facing away from the bit line;
  • Step S3 forming a word line and a fourth insulating layer in sequence in the second groove, and the fourth insulating layer is located on the side of the word line away from the bottom of the second groove;
  • Step S4 forming a plurality of through-holes distributed in an array on the side of the insulator away from the base substrate, the through-holes are on the orthographic projection of the base substrate and the bit lines are on the base substrate.
  • the orthographic projections at least partially overlap, the through hole extends to the surface of the bit line facing the through hole, and the orthographic projection of the through hole on the base substrate may be located between two adjacent word lines. Between the orthographic projections of the base substrate, and in the second direction, there is only one word line on the substrate between the orthographic projections of the two adjacent through holes on the base substrate orthographic projection of the substrate;
  • Step S5 forming a fifth insulating layer on the side of the word line exposed to the through hole;
  • Step S6 forming a first source/drain portion, an active portion, and a second source/drain portion in the through hole, the first source/drain portion is located on one side of the bit line, and the active portion The first source/drain portion is located on the side of the first source/drain portion away from the bit line, and the second source/drain portion is located on the side of the active portion away from the bit line.
  • forming a body to be etched may include:
  • Step S11 forming a substrate material layer, one side of the substrate material layer is formed with a plurality of first grooves spaced along the first direction and extending along the second direction;
  • Step S12 forming a first insulating layer, a bit line, and a second insulating layer in the first groove, the bit line is located on the side of the first insulating layer away from the bottom of the first groove, and the The second insulating layer is located on the side of the bit line away from the bottom of the first groove;
  • Step S13 Remove the substrate material layer on the plane where the bottom of the first groove is located facing the side of the opening of the first groove, so that the remaining substrate material layer is formed into a substrate substrate, and the removed substrate material layer is removed.
  • the third insulating layer is filled in position to form the insulator with the third insulating layer, the first insulating layer and the second insulating layer.
  • FIG. 7 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the method for fabricating a semiconductor structure of the present disclosure.
  • FIG. 8 is a cross-sectional view taken along the dotted line A-A in FIG. 7
  • FIG. 9 is a cross-sectional view taken along the dotted line B-B in FIG. 7 .
  • Step S11 forming a substrate material layer 01 , a side surface of the substrate material layer 01 is formed with a plurality of first grooves 11 distributed along the first direction X and extending along the second direction Y at intervals.
  • the material of the substrate material layer 01 may be other materials such as silicon, SOI, germanium, and gallium arsenide.
  • a plurality of first grooves 11 are formed on one side of the substrate material layer 01 and are distributed along the first direction X and extend along the second direction Y at intervals.
  • FIGS. 10 , 13 , 16 , 19 , 22 , and 25 are top views of semi-finished semiconductor structures in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 11 is a cross-sectional view along the dotted line AA in FIG. 10 .
  • Figure 12 is a cross-sectional view of dotted line BB in Figure 10;
  • Figure 14 is a cross-sectional view of dotted line AA in Figure 13;
  • Figure 15 is a cross-sectional view of dotted line BB in Figure 13;
  • Figure 17 is a cross-sectional view of dotted line AA in Figure 16;
  • Figure 18 is a cross-sectional view of Figure 16
  • Figure 20 is a cross-sectional view of the dotted line AA in Figure 19;
  • Figure 21 is a cross-sectional view of the dotted line BB in Figure 19;
  • Figure 23 is a cross-sectional view of the dotted line AA in Figure 22;
  • Figure 24 is a cross-sectional view of the dotted line BB in Figure 22;
  • Step S12 forming a first insulating layer, a bit line, and a second insulating layer in the first groove 11 , and the bit line is located on the side of the first insulating layer away from the bottom of the first groove, so The second insulating layer is located on the side of the first insulating layer away from the bottom of the first groove, and may include:
  • a first insulating material layer 02 may be deposited on the side of the substrate material layer 01 where the first grooves 11 are provided by a deposition process, so as to fill the first grooves 11 .
  • the material of the first insulating material layer 02 may be silicon oxide.
  • the first insulating material layer 02 in the first groove 11 may be partially etched through an etching process to form the first insulating layer 21 in the first groove 11 .
  • the upper surface of the first insulating layer 21 is lower than the upper surface of the first groove 11 .
  • the bit line material layer 03 may then be coated on the side of the substrate material layer 01 where the first grooves 11 are provided through a deposition process, so as to fill the first grooves 11 .
  • the material of the bit line material layer 03 may be metal tungsten.
  • the bit line material layer 03 in the first groove 11 may be partially etched through an etching process to form the bit line 2 in the first groove 11 .
  • the upper surface of the bit line 2 is lower than the upper surface of the first groove 11 .
  • a second insulating material layer 04 may then be deposited on the side of the substrate material layer 01 provided with the first grooves 11 by a deposition process to fill the first grooves 11.
  • the material of the second insulating material layer 04 may be silicon oxide.
  • CMP chemical mechanical polishing
  • FIGS. 28 and 31 are top views of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 29 is a cross-sectional view of the dotted line AA in FIG. 28 ;
  • FIG. 30 is the dotted line in FIG. 28 .
  • FIG. 32 is a cross-sectional view of the dotted line AA in FIG. 31 ;
  • FIG. 33 is a cross-sectional view of the dotted line BB in FIG. 31 .
  • FIGS. 29 is a cross-sectional view of the dotted line AA in FIG. 28 .
  • FIG. 30 is the dotted line in FIG. 28 .
  • FIG. 32 is a cross-sectional view of the dotted line AA in FIG. 31
  • FIG. 33 is a cross-sectional view of the dotted line BB in FIG. 31 .
  • first step S13 may include: removing the substrate material layer on the plane where the bottom of the first groove is located facing the side of the opening of the first groove through an etching process, so as to remove the remaining The base material layer forms the base substrate 1 .
  • step S13 may further include: filling the third insulating layer 05 at the position of the removed substrate material layer by a deposition process, so that the third insulating layer 05 , the first insulating layer 21.
  • the second insulating layer 41 forms the insulator 3 .
  • FIG. 34 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 35 is a cross-sectional view of the dotted line AA in FIG. 34 ;
  • FIG. 36 is the dotted line BB of FIG. Cutaway view.
  • Step S2 A plurality of second grooves 051 spaced along the second direction Y and extending along the first direction X may be formed on the side of the insulator 3 away from the bit line 2 by an etching process.
  • FIG. 37 is a top view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 38 is a cross-sectional view of the dotted line AA in FIG. 37;
  • FIG. 39 is the dotted line BB of FIG. 37. Cutaway view.
  • Step S3 A word line 4 and a fourth insulating layer 7 may be sequentially formed in the second recess 051 through deposition and etching processes, and the fourth insulating layer 7 is located on the word line 4 away from the second recess.
  • FIG. 40 is a top perspective view of a semi-finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 41 is a cross-sectional view of the dotted line AA in FIG. 40;
  • FIG. 42 is the dotted line in FIG. 40. Cutaway view of BB.
  • Step S4 A plurality of through holes 8 distributed in an array may be formed on the insulator 3 through an etching process, and the orthographic projection of the through holes 8 on the base substrate 1 and the bit line 2 on the substrate The orthographic projections of the substrate 1 at least partially overlap, the through hole 8 extends to the surface of the bit line 2 facing the through hole 8, and the orthographic projection of the through hole 8 on the base substrate 1 may be located at Two adjacent word lines 4 are between the orthographic projections of the base substrate 1 , and in the second direction Y, two adjacent through holes 8 are between the orthographic projections of the base substrate 1 . There is only one orthographic projection of the word line 4 on the base substrate 1 .
  • Step S5 A fifth insulating layer 9 may be formed on the side of the word line 4 exposed to the through hole 8 by an atomic layer deposition process.
  • the fifth insulating layer 9 can be used for the gate oxide layer of the word line 4 .
  • an atomic layer deposition process may be used to deposit an insulating layer on the through hole, etch the insulating layer at the bottom of the through hole, and retain the insulating layer on the sidewall of the through hole to form the fifth insulating layer.
  • FIG. 43 is a top perspective view of a finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 44 is a cross-sectional view along the dotted line AA in FIG. 43 ;
  • FIG. 45 is the dotted line in FIG. 43 . Cutaway view of BB.
  • Step S6 forming a first source/drain portion 51 , an active portion 52 , and a second source/drain portion 53 in the through hole 8 , the first source/drain portion 51 is located on the bit line 2 away from the substrate On one side of the substrate 1 , the active part 52 is located on the side of the first source/drain part 51 away from the bit line 2 , and the second source/drain part 53 is located on the side of the active part 52 away from the bit line 2 . the side of the bit line 2.
  • forming the first source/drain portion 51 , the active portion 52 , and the second source/drain portion 53 in the through hole 8 may include: filling the through hole 8 with a semiconductor material, The two sides in the extending direction of the through hole 8 are doped to form the first source/drain portion 51 and the second source/drain portion 53 respectively. The undoped portion between the first source/drain portion 51 and the second source/drain portion 53 forms the active portion 52 .
  • the semiconductor material may be polysilicon, and the first source/drain portion 51 and the second source/drain portion 53 are formed by N-type doping or P-type doping.
  • the doping ions can be boron ions, bismuth ions, germanium ions, cobalt ions, phosphorus ions and the like.
  • the resistance value of the active part can also be adjusted by lightly doping the active part.
  • the orthographic projection of the active portion 52 on the plane where the word line 4 is located may be located on the word line 4 .
  • the first source/drain portion 51 and the second source/drain portion 53 may form the source/drain of the switching transistor in the memory cell, the active portion 52 may form the active portion of the switching transistor, and part of the word lines 4 may be formed
  • the fifth insulating layer 9 may form the gate insulating layer of the switching transistor.
  • FIG. 46 is a top perspective view of a finished semiconductor structure in an exemplary embodiment of the disclosed semiconductor structure fabrication method;
  • FIG. 47 is a cross-sectional view of the dotted line AA in FIG. 46 ;
  • FIG. 48 is a cross-sectional view taken along the dotted line BB in FIG. 46 .
  • first source/drain part, an active part, and a second source/drain part in the through hole 8 may further include: forming a first conductor part 71 in the through hole 8, the first conductor The part 71 is located between the bit line 2 and the first source/drain part 51; the first source/drain part 51, the active part 52 and the second source/drain part 53 are formed in the through hole 8, Afterwards, the method may further include: forming a second conductor portion 72 in the through hole 8 , and the second conductor portion 72 is located on the side of the second source/drain portion 53 away from the base substrate 1 .
  • the materials of the first conductor portion 71 and the second conductor portion 72 may be conductive polysilicon or metal silicide.
  • the present exemplary embodiment also provides a semiconductor structure control method for controlling the above-mentioned semiconductor structure, which includes:
  • the active body located between the two word lines is gated, thereby accessing its capacitance.
  • the PN junction sandwiched in the active body source and drain regions in the middle forms an inversion path and is turned on, while the PN junction in the adjacent active body source and drain regions is due to insufficient gate voltage.
  • the PN junction cannot be inverted to form a complete path, thereby ensuring that two word lines and one bit line correspond to one capacitor to achieve the purpose of addressing.

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Abstract

本公开涉及存储技术领域，提出一种半导体结构及其制作方法、控制方法，该半导体结构包括衬底基板、多条位线、多个主动体、绝缘体、多条字线。绝缘体位于所述衬底基板的一侧；多条位线设置于所述绝缘体内，多条所述位线沿第一方向间隔分布且沿第二方向延伸；多个所述主动体位于所述位线背离所述衬底基板的一侧，主动体在衬底基板的正投影与位线在衬底基板的正投影至少部分重合，且沿所述第二方向上间隔分布；多条字线位于所述绝缘体内，且位于所述位线背离所述衬底基板的一侧，所述字线沿所述第二方向间隔分布且沿第一方向延伸，且在第二方向上的两相邻所述主动体之间仅设置一条所述字线。该半导体结构能够在有限的空间集成较多的存储单元。 (图2)

Description

半导体结构及其制作方法、控制方法
相关申请的交叉引用
本申请要求于2020年09月04日递交的、名称为《半导体结构及其制作方法、控制方法》的中国专利申请第202010921763.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及存储技术领域，尤其涉及一种半导体结构及其制作方法、控制方法。
背景技术
存储器通常由多个存储单元组成，每个存储单元包括有开关晶体管、电容。存储器通常通过字线向开关晶体管的栅极提供断通信号，通过位线连接开关晶体管的源/漏极以通过开关晶体管向电容提供逻辑“1”或“0”。
相关技术中，存储器将字线、位线、开关晶体管、电容集成于同一半导体结构上，然而，在相关技术中，半导体结构中开关晶体管的集成密度较低，从而影响单位尺寸半导体结构中存储单元的个数。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种半导体结构，其包括：衬底基板、多条位线、多个主动体、绝缘体、多条字线。绝缘体位于所述衬底基板的一侧；多条位线设置于所述绝缘体内，多条所述位线沿第一方向间隔分布且沿第二方向延伸；多个主动体位于所述绝缘体内，所述主动体位于所述位线背离所述衬底基板的一侧，主动体在衬底基板的正投影与位线在衬底基板的正投影至少部分重合，且沿所述第二方向上间隔分布；多条字线位于所述绝缘体内，且位于所述位线背离所述衬底基板的一侧，所述字线沿所述第二方向间隔分布且沿第一方向延伸，且在第二方向上的两相邻所述主动体之间仅设置一条所述字线。本公开一种示例性实施例中，所述主动体包括：第一源/漏部、有源部、第二源/漏部。第一源/漏部位于所述位线背离所述衬底基板的一侧；有源部位于所述第一源/漏部背离所述衬底基板的一侧；第二源/漏部位于所述有源部背离所述衬底基板的一侧。
本公开一种示例性实施例中，还包括：所述绝缘体包括：第一绝缘体、第二绝缘体、第三绝缘体。第一绝缘体位于所述字线和所述主动体之间；第二绝缘体位于所述字线背离所述衬底基板的一侧；第三绝缘体位于所述字线和所述位线之间。
本公开一种示例性实施例中，所述第一绝缘体的材料为氧化硅，所述第二绝缘体 的材料为氮化硅。
本公开一种示例性实施例中，所述第一方向和所述第二方向垂直。
本公开一种示例性实施例中，所述位线和所述衬底基板通过部分所述绝缘体绝缘设置。
本公开一种示例性实施例中，所述第一源/漏部和所述第二源/漏部的材料为掺杂多晶硅导体，所述有源部的材料为多晶硅。
本公开一种示例性实施例中，所述半导体结构还包括第一导体部、第二导体部，第一导体部位于所述位线与所述第一源/漏部之间；第二导体部位于所述第二源/漏部背离所述衬底基板的一侧。
根据本公开的一个方面，提供一种半导体结构制作方法，其包括：
形成一待刻蚀体，所述待刻蚀体包括衬底基板、位于所述衬底基板一侧绝缘体，以及多条位线，所述位线位于所述绝缘体内且多条所述位线沿第一方向间隔分布且沿第二方向延伸；
在所述绝缘体背离所述位线的一侧形成沿所述第二方向间隔分布且沿第一方向延伸的多条第二凹槽；
在所述第二凹槽内依次形成字线和第四绝缘层，所述第四绝缘层位于所述字线背离所述第二凹槽槽底的一侧；
在所述绝缘体背离所述衬底基板的一侧形成多个阵列分布的通孔，所述通孔在所述衬底基板的正投影与所述位线在所述衬底基板的正投影至少部分重合，所述通孔延伸至所述位线面向所述通孔一侧的表面，且所述通孔在所述衬底基板的正投影位于两相邻所述字线在所述衬底基板的正投影之间，且在所述第二方向上，两相邻所述通孔在所述衬底基板的正投影之间仅有一条所述字线在所述衬底基板的正投影；
在所述字线裸露于所述通孔的一侧形成第五绝缘层；
在所述通孔内形成第一源/漏部、有源部、第二源/漏部，所述第一源/漏部位于所述位线的一侧，所述有源部位于所述第一源/漏部背离所述位线的一侧，所述第二源/漏部位于所述有源部背离所述位线的一侧。
本公开一种示例性实施例中，形成一待刻蚀体，包括：
形成一衬底材料层，所述衬底材料层的一侧面形成有沿第一方向间隔分布且沿第二方向延伸的多条第一凹槽；
在所述第一凹槽内形成第一绝缘层、位线、第二绝缘层，所述位线位于所述第一绝缘层背离所述第一凹槽底部的一侧，所述第二绝缘层位于所述位线背离所述第一凹槽底部的一侧；
去除所述第一凹槽槽底所在平面面向第一凹槽开口一侧的衬底材料层，以将剩余所述衬底材料层形成衬底基板，并在去除的衬底材料层位置填充第三绝缘层，以将所述第三绝缘层和所述第一绝缘层、第二绝缘层形成所述绝缘体。
本公开一种示例性实施例中，在所述通孔内形成第一源/漏部、有源部、第二源/漏部，之前还包括：
在所述通孔内形成第一导体部，所述第一导体部位于所述位线与所述第一源/漏部之间；
在所述通孔内形成第一源/漏部、有源部、第二源/漏部，之后还包括：
在所述通孔内形成第二导体部，所述第二导体部位于所述第二源/漏部背离所述衬底基板的一侧。
根据本公开的一个方面，提供一种半导体结构控制方法，用于控制上述的半导体结构，其包括：
通过同时向相邻两条字线输入导通信号，以导通位于该两条字线之间的主动体。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开半导体结构一种示例性实施例的俯视透视图；
图2为沿图1中A-A虚线的剖视图；
图3为沿图1中B-B虚线端剖视图；
图4为本公开半导体结构另一种示例性实施例的俯视透视图；
图5为沿图1中A-A虚线的剖视图；
图6为沿图1中B-B虚线端剖视图；
图7为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；
图8为图7中虚线A-A的剖视图；
图9为图7中虚线B-B的剖视图；
图10、13、16、19、22、25为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；
图11为图10中虚线A-A的剖视图；
图12为图10中虚线B-B的剖视图；
图14为图13中虚线A-A的剖视图；
图15为图13中虚线B-B的剖视图；
图17为图16中虚线A-A的剖视图；
图18为图16中虚线B-B的剖视图；
图20为图19中虚线A-A的剖视图；
图21为图19中虚线B-B的剖视图；
图23为图22中虚线A-A的剖视图；
图24为图22中虚线B-B的剖视图；
图26为图25中虚线A-A的剖视图；
图27为图25中虚线B-B的剖视图；
图28、31为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；
图29为图28中虚线A-A的剖视图；
图30为图28中虚线B-B的剖视图；
图32为图31中虚线A-A的剖视图；
图33为图31中虚线B-B的剖视图；
图34为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；
图35为图34中虚线A-A的剖视图；
图36为图34中虚线B-B的剖视图；
图37为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；
图38为图37中虚线A-A的剖视图；
图39为图37中虚线B-B的剖视图；
图40为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视透视图；
图41为图40中虚线A-A的剖视图；
图42为图40中虚线B-B的剖视图；
图43为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视透视图；
图44为图43中虚线A-A的剖视图；
图45为图43中虚线B-B的剖视图；
图46为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视透视图；
图47为图46中虚线A-A的剖视图；
图48为图46中虚线B-B的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施， 且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例提供一种半导体结构，如图1、2、3所示，图1为本公开半导体结构一种示例性实施例的俯视透视图，图2为沿图1中A-A虚线的剖视图，图3为沿图1中B-B虚线端剖视图。该半导体结构可以包括：衬底基板1、多条位线2、多个主动体5、绝缘体3、多条字线4。绝缘体3位于所述衬底基板1的一侧；多条位线2设置于所述绝缘体3内，多条所述位线2沿第一方向间X隔分布且沿第二方向Y延伸；多个主动体5，位于所述绝缘体3内，所述主动体5位于所述位线2背离所述衬底基板1的一侧，主动体5在衬底基板1的正投影与位线2在衬底基板的正投影至少部分重合，且沿所述第二方向Y上间隔分布；多条字线4位于所述绝缘体3内，且位于所述位线2背离所述衬底基板1的一侧，所述字线4沿所述第二方向Y间隔分布且沿第一方向X延伸，且在第二方向Y上的两相邻所述主动体5之间仅设置一条所述字线4。所述字线4可以通过部分所述绝缘体3与所述主动体5、位线2绝缘。
本示例性实施例中，所述主动体5可以包括：第一源/漏部51、有源部52、第二源/漏部53。第一源/漏部51可以位于所述位线2背离所述衬底基板1的一侧；有源部52可以位于所述第一源/漏部51背离所述衬底基板1的一侧；第二源/漏部53可以位于所述有源部52背离所述衬底基板1的一侧。主动体5可以形成一开关晶体管的源/漏极和沟道区，部分字线4可以形成该开关晶体管的栅极。第二源/漏部53背离衬底基板1的一侧可以裸露于绝缘体外，第二源/漏部53背离衬底基板1的一侧还可以设置电容，以在该半导体结构上形成多个阵列分布的存储单元。其中，每个存储单元可以包括一个开关晶体管和一个电容。
本公开提供的半导体结构中，在第二方向Y上的两相邻所述主动体5之间仅设置一条所述字线4，可以通过同时向相邻两条字线4输入导通信号，以在该两条字线之间主动体5的有源部52上形成导电沟道，从而导通该主动体5两端的第一源/漏部51和第二源/漏部53，即导通该主动体5形成的开关晶体管。相较于相关技术中，两相邻 所述主动体之间设置一条字线，本公开提供的半导体结构可以减小第二方向上两相邻主动体之间的间距，从而提高该半导体结构主动体5的集成密度，即增加了半导体结构上存储单元的集成密度。
本示例性实施例中，如图2所示，有源部52在字线4所在平面的正投影可以位于字线4上，此处，字线4所在平面是指与字线4延伸方向平行的平面，即与图1中B-B剖切线平行的平面。从而部分所述字线4可以用于形成所述开关晶体管的栅极。位线2可以与衬底基板1抵接。
本示例性实施例中，如图2所示，所述绝缘体3可以包括：第一绝缘体31、第二绝缘体32、第三绝缘体33。第一绝缘体31可以位于所述字线4和主动体5之间；第二绝缘体32可以位于所述字线4背离所述衬底基板1的一侧；第三绝缘体33可以位于所述字线4和位线之间。其中，所述第二绝缘体32的硬度可以大于所述第一绝缘体31、第三绝缘体33的硬度。如图2所示，第二绝缘体32位于半导体结构的上表面，第二绝缘体32可以对半导体结构内部的位线、字线、开关晶体管的结构起到保护作用，将第二绝缘体32设置成硬度较大的材料，可以提高第二绝缘体32的保护能力。第一绝缘体31可以作为开关晶体管的栅极绝缘层。第三绝缘体33用于电隔离字线和位线。本示例性实施例中，所述第一绝缘体31、第三绝缘体33的材料可以为氧化硅，所述第二绝缘体32的材料可以为氮化硅。
应该理解的是，在其他示例性实施例中，第一绝缘体31、第二绝缘体32、第三绝缘体33还可以由其他绝缘材料形成，例如，第一绝缘体31、第二绝缘体32、第三绝缘体33可以由一种材料形成。
如图1所示，主动体5的沿第一方向X和所述第二方向Y阵列分布。当第一方向X和第二方向Y垂直时，主动体5可以行列分布，从而实现其最大的集成密度。本示例性实施例中，第一方向X和所述第二方向Y可以垂直，从而可以进一步增加半导体结构上存储单元的集成密度。
本示例性实施例中，所述位线和所述字线的材料可以为金属钨。所述第一源/漏部和所述第二源/漏部的材料可以为掺杂多晶硅导体，所述有源部的材料为多晶硅。其中，在第一源/漏部和所述第二源/漏部中，一个为开关晶体管的源极，另一个为开关晶体管的漏极。应该理解的是，在其他示例性实施例中，位线、字线、第一源/漏部、第二源/漏部、有源部的材料还可以为其他材料。例如，位线、字线可以为金属氮化钛、铜、银等。有源部的材料还可以为金属氧化物半导体、锗、砷化镓、非晶硅半导体等，相应的，第一源/漏部、第二源/漏部可以由形成有源部的半导体材料掺杂形成。掺杂类型可以为N型掺杂或P型掺杂，掺杂离子可以为硼离子、铋离子、锗离子及钴离子、磷离子等。此外，还可以通过对有源部进行轻掺杂以调节有源部的阻值。
如图4、5、6所示，图4为本公开半导体结构另一种示例性实施例的俯视透视图，图5为沿图1中A-A虚线的剖视图，图6为沿图1中B-B虚线端剖视图。相较于图1、 2、3所示的半导体结构，本示例性实施例中，所述位线2和所述衬底基板1可以通过部分所述绝缘体3绝缘设置。
本示例性实施例中，形成第一源/漏部51、第二源/漏部53的方法通常是，首先形成半导体材料，在半导体材料的两侧进行离子掺杂以形成第一源/漏部51、第二源/漏部53。然而，在离子掺杂过程中，掺杂的离子可能会对半导体材料两侧绝缘层的介电常数造成影响。例如，如图2所示，掺杂的离子可能会增加绝缘体3的介电常数。本示例性实施例中，如图4、5所示，所述半导体结构还可以包括第一导体部71、第二导体部72，第一导体部71可以位于所述位线2与所述第一源/漏部51之间；第二导体部72可以位于所述第二源/漏部53背离所述衬底基板1的一侧。如图5所示，该设置可以减小第一源/漏部51、第二源/漏部53在层叠方向上的尺寸，从而可以减小绝缘体受粒子掺杂的范围。其中，第一导体部71可以作为位线接触插塞，第二导体部72可以作为电容接触插塞。
本示例性实施例还提供一种半导体结构制作方法，该方法可以形成上述半导体结构。该方法可以包括：
步骤S1：形成一待刻蚀体，所述待刻蚀体包括衬底基板、位于所述衬底基板一侧绝缘体，以及多条位线，所述位线位于所述绝缘体内且多条所述位线沿第一方向间隔分布且沿第二方向延伸；
步骤S2：在所述绝缘体背离所述位线的一侧形成沿所述第二方向间隔分布且沿第一方向延伸的多条第二凹槽；
步骤S3：在所述第二凹槽内依次形成字线和第四绝缘层，所述第四绝缘层位于所述字线背离所述第二凹槽槽底的一侧；
步骤S4：在所述绝缘体背离所述衬底基板的一侧形成多个阵列分布的通孔，所述通孔在所述衬底基板的正投影与所述位线在所述衬底基板的正投影至少部分重合，所述通孔延伸至所述位线面向所述通孔一侧的表面，且所述通孔在所述衬底基板的正投影可以位于两相邻所述字线在所述衬底基板的正投影之间，且在所述第二方向上，两相邻所述通孔在所述衬底基板的正投影之间仅有一条所述字线在所述衬底基板的正投影；
步骤S5：在所述字线裸露于所述通孔的一侧形成第五绝缘层；
步骤S6：在所述通孔内形成第一源/漏部、有源部、第二源/漏部，所述第一源/漏部位于所述位线的一侧，所述有源部位于所述第一源/漏部背离所述位线的一侧，所述第二源/漏部位于所述有源部背离所述位线的一侧。
其中，形成一待刻蚀体，可以包括：
步骤S11：形成一衬底材料层，所述衬底材料层的一侧面形成有沿第一方向间隔分布且沿第二方向延伸的多条第一凹槽；
步骤S12：在所述第一凹槽内形成第一绝缘层、位线、第二绝缘层，所述位线位 于所述第一绝缘层背离所述第一凹槽底部的一侧，所述第二绝缘层位于所述位线背离所述第一凹槽底部的一侧；
步骤S13：去除所述第一凹槽槽底所在平面面向第一凹槽开口一侧的衬底材料层，以将剩余所述衬底材料层形成衬底基板，并在去除的衬底材料层位置填充第三绝缘层，以将所述第三绝缘层和所述第一绝缘层、第二绝缘层形成所述绝缘体。
以下对上述步骤进行详细说明：
如图7、8、9所示，图7为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图。图8为图7中虚线A-A的剖视图，图9为图7中虚线B-B的剖视图。步骤S11：形成一衬底材料层01，所述衬底材料层01的一侧面形成有沿第一方向X间隔分布且沿第二方向Y延伸的多条第一凹槽11。其中，衬底材料层01的材料可以为硅、SOI、锗、砷化镓等其它材料。其中，在衬底材料层01的一侧面形成有沿第一方向X间隔分布且沿第二方向Y延伸的多条第一凹槽11。
如图10-27所示，图10、13、16、19、22、25为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；图11为图10中虚线A-A的剖视图；图12为图10中虚线B-B的剖视图；图14为图13中虚线A-A的剖视图；图15为图13中虚线B-B的剖视图；图17为图16中虚线A-A的剖视图；图18为图16中虚线B-B的剖视图；图20为图19中虚线A-A的剖视图；图21为图19中虚线B-B的剖视图；图23为图22中虚线A-A的剖视图；图24为图22中虚线B-B的剖视图；图26为图25中虚线A-A的剖视图；图27为图25中虚线B-B的剖视图。步骤S12：在所述第一凹槽11内形成第一绝缘层、位线、第二绝缘层，所述位线位于所述第一绝缘层背离所述第一凹槽底部的一侧，所述第二绝缘层位于所述第一绝缘层背离所述第一凹槽底部的一侧，可以包括：
如图10、11、12所示，首先可以通过沉积工艺在衬底材料层01设置有第一凹槽11的一侧沉积第一绝缘材料层02，以填充第一凹槽11。第一绝缘材料层02的材料可以为氧化硅。
如图13、14、15所示，然后可以通过刻蚀工艺对第一凹槽11内的第一绝缘材料层02进行部分刻蚀，以形成位于第一凹槽11内的第一绝缘层21。其中，第一绝缘层21的上表面低于第一凹槽11的上表面。
如图16、17、18所示，然后可以通过沉积工艺在衬底材料层01设置有第一凹槽11的一侧涂覆位线材料层03，以填充第一凹槽11。位线材料层03的材料可以为金属钨。
如图19、20、21所示，然后可以通过刻蚀工艺对第一凹槽11内的位线材料层03进行部分刻蚀，以形成位于第一凹槽11内的位线2。其中，位线2的上表面低于第一凹槽11的上表面。
如图22、23、24所示，然后可以通过沉积工艺在衬底材料层01设置有第一凹槽 11的一侧沉积第二绝缘材料层04，以填充第一凹槽11。其中，第二绝缘材料层04的材料可以为氧化硅。
如图25、26、27所示，然后可以对衬底材料层01设置有第一凹槽11的一侧进行化学机械抛光(CMP)，以使第二绝缘材料层04的上表面与第一凹槽11的上表面齐平，从而将第二绝缘材料层04形成第二绝缘层41。
如图28-33所示，图28、31为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；图29为图28中虚线A-A的剖视图；图30为图28中虚线B-B的剖视图；图32为图31中虚线A-A的剖视图；图33为图31中虚线B-B的剖视图。如图28、29、30所示，首先步骤S13可以包括：通过刻蚀工艺去除所述第一凹槽槽底所在平面面向第一凹槽开口一侧的衬底材料层，以将剩余所述衬底材料层形成衬底基板1。如图31、32、33所示，然后，步骤S13还可以包括：通过沉积工艺在去除的衬底材料层位置填充第三绝缘层05，以将所述第三绝缘层05、第一绝缘层21、所述第二绝缘层41形成绝缘体3。
如图34-36所示，图34为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；图35为图34中虚线A-A的剖视图；图36为图34中虚线B-B的剖视图。步骤S2：可以通过刻蚀工艺在所述绝缘体3背离所述位线2的一侧形成沿所述第二方向Y间隔分布且沿第一方向X延伸的多条第二凹槽051。
如图37-39所示，图37为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视图；图38为图37中虚线A-A的剖视图；图39为图37中虚线B-B的剖视图。步骤S3：可以通过沉积、刻蚀工艺在所述第二凹槽051内依次形成字线4和第四绝缘层7，所述第四绝缘层7位于所述字线4背离所述第二凹槽051槽底的一侧。
如图40-42所示，图40为本公开半导体结构制作方法一种示例性实施例中半导体结构半成品的俯视透视图；图41为图40中虚线A-A的剖视图；图42为图40中虚线B-B的剖视图。步骤S4：可以通过刻蚀工艺在所述绝缘体3上形成多个阵列分布的通孔8，所述通孔8在所述衬底基板1的正投影与所述位线2在所述衬底基板1的正投影至少部分重合，所述通孔8延伸至所述位线2面向所述通孔8一侧的表面，且所述通孔8在所述衬底基板1的正投影可以位于两相邻所述字线4在所述衬底基板1的正投影之间，且在所述第二方向Y上，两相邻所述通孔8在所述衬底基板1的正投影之间仅有一条所述字线4在所述衬底基板1的正投影。
步骤S5：可以通过原子层沉积工艺在所述字线4裸露于所述通孔8的一侧形成第五绝缘层9。所述第五绝缘层9可以用于字线4的栅极氧化层。具体的可以通过原子层沉积工艺在所述通孔沉积一层绝缘层，刻蚀通孔底部的绝缘层，保留通孔侧壁绝缘层形成所述第五绝缘层。
如图43-45所示，图43为本公开半导体结构制作方法一种示例性实施例中半导体 结构成品的俯视透视图；图44为图43中虚线A-A的剖视图；图45为图43中虚线B-B的剖视图。步骤S6：在所述通孔8内形成第一源/漏部51、有源部52、第二源/漏部53，所述第一源/漏部51位于所述位线2背离衬底基板1的一侧，所述有源部52位于所述第一源/漏部51背离所述位线2的一侧，所述第二源/漏部53位于所述有源部52背离所述位线2的一侧。具体的，在所述通孔8内形成第一源/漏部51、有源部52、第二源/漏部53可以包括：在通孔8内填充半导体材料，对通孔8内半导体沿通孔8延伸方向的两侧进行掺杂以分别形成第一源/漏部51和第二源/漏部53。位于第一源/漏部51和第二源/漏部53之间的未掺杂部分形成有源部52。其中，该半导体材料可以为多晶硅，第一源/漏部51和第二源/漏部53通过N型掺杂或P型掺杂形成。掺杂离子可以为硼离子、铋离子、锗离子及钴离子、磷离子等。此外，还可以通过对有源部进行轻掺杂以调节有源部的阻值。有源部52在字线4所在平面的正投影可以位于字线4上。其中，第一源/漏部51、第二源/漏部53可以形成存储单元中开关晶体管的源/漏极，有源部52可以形成该开关晶体管的有源部，部分字线4可以形成该开关晶体管的栅极，第五绝缘层9可以形成该开关晶体管的栅极绝缘层。
本示例性实施例中，如图46-48所示，图46为本公开半导体结构制作方法一种示例性实施例中半导体结构成品的俯视透视图；图47为图46中虚线A-A的剖视图；图48为图46中虚线B-B的剖视图。
在所述通孔8内形成第一源/漏部、有源部、第二源/漏部，之前还可以包括：在所述通孔8内形成第一导体部71，所述第一导体部71位于所述位线2与所述第一源/漏部51之间；在所述通孔8内形成第一源/漏部51、有源部52、第二源/漏部53，之后还可以包括：在所述通孔8内形成第二导体部72，所述第二导体部72位于所述第二源/漏部53背离所述衬底基板1的一侧。其中，第一导体部71和第二导体部72的材料可以为导体化的多晶硅或金属硅化物。
本示例性实施例还提供一种半导体结构控制方法，用于控制上述的半导体结构，其包括：
通过同时向相邻两条字线输入导通信号，以选通位于该两条字线之间的主动体，从而对其电容进行存取。当两条字线同时打开的时候，夹在中间主动体源漏区中的PN结反型形成通路从而导通，而旁边主动体源漏区中的PN结因为栅极电压不够，导致其中的PN结不能反型而无法形成完成的通路，从而保证两条字线一条位线对应一个电容达到选址目的。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (12)

  1. 一种半导体结构，其中，包括：
    衬底基板；
    绝缘体，位于所述衬底基板的一侧；
    多条位线，设置于所述绝缘体内，多条所述位线沿第一方向间隔分布且沿第二方向延伸；
    多个主动体，位于所述绝缘体内，所述主动体位于所述位线背离所述衬底基板的一侧，所述主动体在所述衬底基板的正投影与所述位线在所述衬底基板的正投影至少部分重合，且沿所述第二方向上间隔分布；
    多条字线，位于所述绝缘体内，且位于所述位线背离所述衬底基板的一侧，所述字线沿所述第二方向间隔分布且沿第一方向延伸，且在第二方向上的两相邻所述主动体之间仅设置一条所述字线。
  2. 根据权利要求1所述的半导体结构，其中，所述绝缘体包括：
    第一绝缘体，位于所述字线和所述主动体之间；
    第二绝缘体，位于所述字线背离所述衬底基板的一侧；
    第三绝缘体，位于所述字线和所述位线之间；
    所述第二绝缘体的硬度大于所述第一绝缘体、第三绝缘体的硬度。
  3. 根据权利要求2所述的半导体结构，其中，所述第一绝缘体的材料为氧化硅，所述第二绝缘体的材料为氮化硅。
  4. 根据权利要求1所述的半导体结构，其中，所述第一方向和所述第二方向垂直。
  5. 根据权利要求1所述的半导体结构，其中，所述位线和所述衬底基板通过部分所述绝缘体绝缘设置。
  6. 根据权利要求1所述的半导体结构，其中，所述主动体包括：
    第一源/漏部，位于所述位线背离所述衬底基板的一侧；
    有源部，位于所述第一源/漏部背离所述衬底基板的一侧；
    第二源/漏部，位于所述有源部背离所述衬底基板的一侧。
  7. 根据权利要求6所述的半导体结构，其中，所述第一源/漏部和所述第二源/漏部的材料为掺杂多晶硅导体，所述有源部的材料为多晶硅。
  8. 根据权利要求6所述的半导体结构，其中，所述半导体结构还包括：
    第一导体部，位于所述位线与所述第一源/漏部之间；
    第二导体部，位于所述第二源/漏部背离所述衬底基板的一侧。
  9. 一种半导体结构制作方法，其中，包括：
    形成一待刻蚀体，所述待刻蚀体包括衬底基板、位于所述衬底基板一侧绝缘体，以及多条位线，所述位线位于所述绝缘体内且多条所述位线沿第一方向间隔分布且沿第二方向延伸；
    在所述绝缘体背离所述位线的一侧形成沿所述第二方向间隔分布且沿第一方向延伸的多条第二凹槽；
    在所述第二凹槽内依次形成字线和第四绝缘层，所述第四绝缘层位于所述字线背离所述第二凹槽槽底的一侧；
    在所述绝缘体背离所述衬底基板的一侧形成多个阵列分布的通孔，所述通孔在所述衬底基板的正投影与所述位线在所述衬底基板的正投影至少部分重合，所述通孔延伸至所述位线的表面，且在所述第二方向上，两相邻所述通孔在所述衬底基板的正投影之间仅有一条字线在所述衬底基板的正投影；
    在所述字线裸露于所述通孔的一侧形成第五绝缘层；
    在所述通孔内形成第一源/漏部、有源部、第二源/漏部，所述第一源/漏部位于所述位线的一侧，所述有源部位于所述第一源/漏部背离所述位线的一侧，所述第二源/漏部位于所述有源部背离所述位线的一侧。
  10. 根据权利要求9所述的半导体结构制作方法，其中，形成一待刻蚀体，包括：
    形成一衬底材料层，所述衬底材料层的一侧面形成有沿第一方向间隔分布且沿第二方向延伸的多条第一凹槽；
    在所述第一凹槽内形成第一绝缘层、位线、第二绝缘层，所述位线位于所述第一绝缘层背离所述第一凹槽底部的一侧，所述第二绝缘层位于所述位线背离所述第一凹槽底部的一侧；
    去除所述第一凹槽槽底所在平面面向第一凹槽开口一侧的衬底材料层，以将剩余所述衬底材料层形成衬底基板，并在去除的衬底材料层位置填充第三绝缘层，以将所述第三绝缘层和所述第一绝缘层、第二绝缘层形成所述绝缘体。
  11. 根据权利要求9所述的半导体结构制作方法，其中，在所述通孔内形成第一源/漏部、有源部、第二源/漏部，之前还包括：
    在所述通孔内形成第一导体部，所述第一导体部位于所述位线与所述第一源/漏部 之间；
    在所述通孔内形成第一源/漏部、有源部、第二源/漏部，之后还包括：
    在所述通孔内形成第二导体部，所述第二导体部位于所述第二源/漏部背离所述衬底基板的一侧。
  12. 一种半导体结构控制方法，用于控制权利要求1-8任一项所述的半导体结构，其中，包括：
    同时向相邻两条字线输入导通信号，以导通位于该两条字线之间的主动体。
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