WO2024040645A1 - Structure semi-conductrice et son procédé de fabrication, et mémoire - Google Patents

Structure semi-conductrice et son procédé de fabrication, et mémoire Download PDF

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Publication number
WO2024040645A1
WO2024040645A1 PCT/CN2022/118639 CN2022118639W WO2024040645A1 WO 2024040645 A1 WO2024040645 A1 WO 2024040645A1 CN 2022118639 W CN2022118639 W CN 2022118639W WO 2024040645 A1 WO2024040645 A1 WO 2024040645A1
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trench
active
layer
word line
semiconductor
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PCT/CN2022/118639
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English (en)
Chinese (zh)
Inventor
邵光速
肖德元
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长鑫存储技术有限公司
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Publication of WO2024040645A1 publication Critical patent/WO2024040645A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure, a manufacturing method thereof, and a memory.
  • embodiments of the present disclosure propose a semiconductor structure, a manufacturing method thereof, and a memory.
  • a semiconductor structure including:
  • Active pillars are located on the surface of the substrate.
  • a plurality of the active pillars form an active pillar array having several columns arranged along the first direction and several rows arranged along the second direction.
  • the active pillars Comprising a top active area, a channel area and a bottom active area, the first direction intersects the second direction and are both parallel to the substrate surface;
  • a word line extending along the second direction and covering the channel region of the active pillars of the same column arranged along the first direction;
  • a dielectric layer located between the word line and the active pillar and covering at least the surface of the channel region;
  • a bit line extends along the first direction and is electrically connected to the bottom active area of the active pillars of the same row arranged along the second direction;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • the word line is embedded in the sidewall of the active pillar located in the channel region and covers the first sidewall and the second sidewall of the channel region that are oppositely arranged along the first direction. side wall;
  • the length of the part of the word line covering the first sidewall along the third direction is different from the length of the part of the word line covering the second sidewall along the third direction; wherein, the third direction perpendicular to the substrate surface.
  • the active pillar array includes a plurality of first active pillar rows and second active pillar rows alternately arranged along the first direction;
  • the word line corresponding to the first active pillar column and the word line corresponding to the second active pillar column are arranged symmetrically with respect to the second direction.
  • the interface between the channel region and the top active region, and/or the interface between the channel region and the bottom active region is a right angle, an oblique angle or a rounded angle.
  • the semiconductor structure further includes an isolation structure, and the isolation structure is located between adjacent active pillars, between adjacent word lines, and between adjacent bit lines.
  • the material of the bit line includes a metal compound, or a combination of a metal compound and a metal.
  • a memory including: at least one semiconductor structure as described in any one of the above solutions, a storage structure located on the semiconductor structure, and a memory structure located around or around the semiconductor structure. Peripheral circuitry above the memory structure.
  • a memory manufacturing method including:
  • An array of active pillars is formed on the surface of the substrate with several columns arranged along the first direction and several rows arranged along the second direction.
  • the active pillars include a top active area, a channel area and a bottom active area. region, the first direction and the second direction intersect and are both parallel to the substrate surface;
  • word line Forming a word line, the word line extending along the second direction and covering the channel region of the active pillars of the same column arranged along the first direction;
  • the dielectric layer is located between the word line and the active pillar and covers at least the surface of the channel region;
  • bit line extending along the first direction and electrically connected to the bottom active region of the active pillars of the same row arranged along the second direction;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • forming the active pillar array includes:
  • a plurality of second trenches and third trenches arranged alternately along the first direction are formed, and the second trenches and the third trenches both penetrate the first semiconductor layer and the second trench.
  • the remaining second semiconductor layer forms the top active region of the active pillar
  • the third semiconductor layer forms the channel region of the active pillar and the remaining active layer forming the bottom active region of the active pillar;
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench.
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench, including:
  • the remaining conductive layer forms the word line.
  • the method also includes:
  • a portion of the second insulating material in the third trench is removed.
  • the top surface of the remaining second insulating material in the trench is not higher than the top surface of the active layer.
  • a fourth trench including:
  • a portion of the first semiconductor layer is removed along the first direction.
  • forming a third semiconductor layer in the fourth trench includes:
  • a third semiconductor layer is formed in the fourth trench by epitaxial growth.
  • the first semiconductor layer and the second semiconductor layer have different etching selectivity ratios.
  • the material of the third semiconductor layer and the material of the second semiconductor layer are the same.
  • bit line includes:
  • the bottoms of the second trench and the third trench are etched to form grooves so that the depths of parts of the second trench and the third trench are increased and the grooves are formed along the edges.
  • the width dimension in the first direction is greater than the width dimension of the second groove or the third groove;
  • the first metal layer reacts with the active layer of the groove sidewall to form a metal compound layer, and the groove is filled with a second metal layer.
  • the second metal layer and the The metal compound layer collectively forms the bit line.
  • the second trench and the third trench have the same depth, and the depth of the first trench is greater than the depth of the second trench and the third trench.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the sum of the size of the top active region and the size of the dielectric layer. That is to say, the word line in the semiconductor structure
  • the active pillars are embedded in and cover the channel region of the active pillars.
  • the corresponding active pillars have a dumbbell-like shape. In this way, the distance between adjacent word lines can be increased in the first aspect, so that the word lines can be increased.
  • the coupling between lines is smaller, and the electrical properties of the word lines are better; secondly, the overall feature size of the word lines and active pillars can be made smaller, thereby further shrinking the semiconductor structure.
  • Figure 1 is a schematic diagram of a control circuit using an 1T1C architecture provided in an embodiment of the present disclosure
  • Figure 2a is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2b is a schematic three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2c is a schematic three-dimensional structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 2d is a schematic three-dimensional structural diagram of yet another semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic flow diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure
  • 4a to 4s are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure
  • 5a to 5j are schematic three-dimensional structural diagrams of the manufacturing process of another semiconductor structure provided by embodiments of the present disclosure.
  • 6a to 6e are schematic three-dimensional structural diagrams of another manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 7a to 7e are schematic three-dimensional structural diagrams of the manufacturing process of yet another semiconductor structure provided by embodiments of the present disclosure.
  • FIGS. 8a to 8c are schematic three-dimensional structural diagrams of another manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures. The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the size of memory cells is getting smaller and smaller, and its array architecture has changed from 8F 2 to 6F 2 to 4F 2 ; in addition, based on the demand for ions and leakage current in dynamic random access memory , the memory architecture has changed from Planar Array Transistor to Recess Gate Array Transistor, then from Recess Gate Array Transistor to Buried Channel Array Transistor, and then from Buried Channel Array Transistor. channel array transistor to vertical channel array transistor (Vertical Channel Array Transistor).
  • the dynamic random access memory is composed of multiple memory cell structures.
  • Each memory cell structure mainly consists of a transistor and a memory cell controlled by the transistor.
  • Figure 1 is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of the present disclosure; as shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source region of the transistor T is connected to One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line). Connection; applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
  • the size of DRAM (taking DRAM as an example) is constantly shrinking.
  • the word line WL is arranged around the channel of the transistor T. At this time, the spacing between the word line WL and the word line WL If it is too small, the coupling will be too large; moreover, the size of the word line WL and the size of the channel of the transistor T are too large, making it difficult to continue shrinking; the transistors in related technologies are limited in size, and it is difficult for DRAM to balance high performance.
  • embodiments of the present disclosure provide a semiconductor structure.
  • FIGS. 2a to 2d are schematic three-dimensional structural diagrams of some semiconductor structures provided by embodiments of the present disclosure.
  • a semiconductor structure 10a, 10b, 10c, 10d provided by an embodiment of the present disclosure includes:
  • Active pillars AP are located on the surface of the substrate 100.
  • a plurality of active pillars AP are formed into several columns (first active pillar array CA1, second active pillar array CA2...) arranged along the first direction. ) and an active pillar array of several rows (first active pillar row RA1, second active pillar column RA2...) arranged along the second direction, the active pillar AP includes a top active area TA, In the channel area CH and the bottom active area BA, the first direction intersects the second direction and are both parallel to the surface of the substrate 100;
  • the word line WL extends along the second direction and covers the channel region CH of the active pillars of the same column arranged along the first direction;
  • the dielectric layer 109 is located between the word line WL and the active pillar AP and covers at least the surface of the channel region CH;
  • Bit line BL extends along the first direction and is electrically connected to the bottom active area BA of the active pillars AP in the same row arranged along the second direction;
  • the size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the size of the top active region and the size of the medium.
  • the sum of the layer dimensions is W4.
  • dimensions W1 to W6 can be understood as width dimensions or thickness dimensions along the first direction; lengths H1 to H6 can be understood as height dimensions or thickness dimensions along the third direction. .
  • semiconductor structures shown in the embodiments of the present disclosure are not exclusive, and the structural features shown can also be interchanged between semiconductor structures in different embodiments; each structural feature of the semiconductor structures shown in the embodiments of the present disclosure The structure, size, location, etc. can be adjusted according to actual needs.
  • the first direction and the second direction are expressed as two intersecting directions parallel to the surface of the substrate;
  • the third direction is a direction perpendicular to the surface of the substrate, that is, the third direction is the The extension direction of the active pillar; wherein, the surface of the substrate can be understood as a plane perpendicular to the extension direction of the active pillar.
  • the descriptions of the first direction, the second direction, and the third direction in the following embodiments are only used to illustrate the present disclosure and are not used to limit the scope of the present disclosure.
  • the angle between the first direction and the second direction ranges from 0 to 90 degrees.
  • the first direction may be perpendicular to the second direction. It can be understood that the angle between the first direction and the second direction establishes the positional relationship of the array arrangement of the active pillars along the first direction and the second direction.
  • the material of the substrate 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe) substrate, etc., or may also be silicon-on-insulator (SOI, Silicon-on-insulator) or Germanium-on-Insulator (GOI, Germanium-on-Insulator).
  • the bottom active area BA includes a material doped with certain impurity ions in the top of the substrate.
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doping includes well region doping and source and drain region doping.
  • the top active region TA and the channel region CH are made of the same material, and both include semiconductor materials with certain impurity ions.
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doping includes well region doping and source and drain region doping.
  • the material of the dielectric layer 109 includes but is not limited to silicon dioxide.
  • the materials of the word line WL and the bit line BL include but are not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, or any combination thereof.
  • the word line WL is embedded in the active pillar AP in the sidewall of the channel region CH and covers the edge of the channel region CH. a first side wall and a second side wall arranged oppositely in the first direction;
  • the length H1 along the third direction of the partial word line covering the first sidewall is different from the length H2 along the third direction of the partial word line covering the second sidewall; wherein, the third Three directions are perpendicular to the surface of the substrate 100 .
  • the length H1 of the part of the word line covering the first sidewall along the third direction is different from the length H1 of the part of the word line covering the second sidewall along the third direction.
  • the length H2 in the third direction is different.
  • the length H1 is smaller than the length H2.
  • the bottom surface of the partial word line covering the first side wall is higher than the bottom surface of the partial word line covering the second side wall
  • the top surface of the partial word line covering the first side wall is lower than the bottom surface of the partial word line covering the first side wall. on the top surface of part of the word lines covering the second sidewall.
  • the length H3 of the partial word line covering the first sidewall along the third direction is different from the length H3 of the partial word line covering the second sidewall along the third direction.
  • the length H4 in the third direction is different.
  • the length H3 is smaller than the length H4.
  • the bottom surface of the part of the word line covering the first sidewall and the bottom surface of the part of the word line covering the second sidewall are substantially flush with the top surface of the bottom active area BA, and cover all the word lines.
  • the top surface of the partial word line of the first side wall is lower than the top surface of the partial word line covering the second side wall.
  • the length of the part of the word line covering the first sidewall along the third direction is the same as the length of the part of the word line covering the second sidewall along the third direction.
  • the lengths in the three directions are the same, for example, they are all length H5.
  • the bottom surface of the partial word line covering the first sidewall and the bottom surface of the partial word line covering the second sidewall are higher than the top surface of the bottom active area BA.
  • the size of the part of the word line covering the first sidewall along the first direction is the same as the size of the part of the word line covering the second sidewall along the first direction.
  • both are the size W5; and the sum of twice the size W5 and the size of the trench region CH is less than or equal to the size of the top active region TA.
  • the length of the part of the word line covering the first sidewall along the third direction is the same as the length of the part of the word line covering the second sidewall along the third direction.
  • the lengths in the three directions are the same, for example, they are all length H6.
  • the bottom surface of the partial word line covering the first sidewall and the bottom surface of the partial word line covering the second sidewall are substantially flush with the top surface of the bottom active area BA.
  • the size of the part of the word line covering the first sidewall along the first direction is the same as the size of the part of the word line covering the second sidewall along the first direction.
  • both are the size W6; and the sum of twice the size W6 and the size of the trench region CH is less than or equal to the size of the top active region TA.
  • the word line in the first direction since the word line extends along the second direction and includes a portion surrounding the channel region and a portion between the channel regions, the word line is in the first direction.
  • the directional dimensions are not equal everywhere along the second direction. It can be understood that for the part of the word line surrounding the channel region, the size in the first direction does not include the size of the channel region and the dielectric layer surrounded by the word line in the first direction, but only Refers to the sum of the dimensions of the word lines on both sides of the surrounding channel region in the first direction; for the partial word lines between the channel regions along the second direction, the dimensions along the first direction are, Refers to the size of the word line in the first direction.
  • the active pillar array includes a plurality of first active pillar arrays CA1 and second active pillar arrays CA2 alternately arranged along the first direction;
  • the word line WL1 corresponding to the first active pillar array CA1 and the word line WL2 corresponding to the second active pillar array CA2 are arranged symmetrically with respect to the second direction.
  • the word line WL1 and the word line WL2 are symmetrically arranged with respect to the second direction, which can be understood as the adjacent word line WL1 and the word line WL2 with respect to the second direction between the adjacent word lines.
  • the vertical center plane of the isolation structure 204 extending in two directions is symmetrical.
  • the word line WL1 corresponding to the first active pillar column CA1 and the word line WL2 corresponding to the second active pillar column CA2 are separated with respect to the partial isolation structure 204 ( The isolation structure 204) between word line WL1 and word line WL2 is symmetrically arranged.
  • the word line WL1 corresponding to the first active pillar column CA1 and the word line WL2 corresponding to the second active pillar column CA2 are separated with respect to the partial isolation structure 204 ( The isolation structure 204) between the word line WL1 and the word line WL2 is symmetrically arranged.
  • the word line WL1 corresponding to the first active pillar column CA1 is arranged symmetrically with respect to the first active pillar array CA1, and is symmetrically arranged with the first active pillar column CA1.
  • the word line WL2 corresponding to the second active pillar array CA2 is symmetrically arranged with respect to the second active pillar array CA2.
  • the interface between the channel region CH and the top active region TA, and/or the interface between the channel region CH and the bottom active region BA is at a right angle or an oblique angle. or rounded corners.
  • the bevel angle and the rounded corner can be understood as shapes obtained by chamfering and rounding the right angle respectively.
  • each active pillar in the active pillar array is perpendicular to the third direction and passes through the top active area TA, the channel area CH, the
  • the cross-sectional shape of the bottom active area BA may be a rectangle, an octagon or a rounded rectangle.
  • the octagon and the rounded rectangle can be understood as shapes obtained by chamfering and rounding the four right angles of the rectangle respectively.
  • the semiconductor structure further includes an isolation structure 204.
  • the isolation structure 204 is located between adjacent active pillars AP, between adjacent word lines WL, and between adjacent word lines WL. between bit lines BL.
  • the part of the isolation structure 204 between the adjacent active pillars serves as the first sub-isolation structure that isolates the word line from the outside in the Z direction; the part between the adjacent word lines
  • the isolation structure 204 serves as a second sub-isolation structure for isolating word lines; a portion of the isolation structure 204 between adjacent bit lines serves as a third sub-isolation structure for isolating bit lines.
  • the materials of the first sub-isolation structure, the second sub-isolation structure, and the third sub-isolation structure may be the same or different.
  • the materials of the first sub-isolation structure, the second sub-isolation structure, and the third sub-isolation structure include any insulating material, such as silicon nitride, silicon oxynitride, silicon carbide, or silicon nitride. Silicon oxide.
  • the top surface of the bit line BL is flat (as shown in Figures 2a and 2b) or arcuate (as shown in Figures 2c and 2d).
  • the material of the bit line BL includes a metal compound, or a combination of a metal compound and a metal. It can be understood that the bit line BL includes a metal compound layer 111, or a combination of the metal compound layer 111 and the second metal layer 112, wherein the material of the metal compound layer 111 includes a metal compound, and the second metal The material of layer 112 includes metal.
  • the bit line BL includes a combination of a metal compound layer 111 and a second metal layer 112 .
  • the material of the metal compound layer 111 includes metal cobalt (Co) compound and/or metal nickel (Ni) compound
  • the material of the second metal layer 112 includes tungsten (W).
  • the word line in the semiconductor structure has the following structural characteristics: 1.
  • the word line is embedded in the active pillar and covers the channel region of the active pillar, and the corresponding active pillar has a similar Dumbbell shape; in this way, the distance between adjacent word lines is increased, and the coupling between word lines is smaller, making the word lines electrically better; at the same time, the contact area between the channel area and the word line can be increased, thereby It can reduce the height of the channel area and increase the structural stability of the channel area.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer. In this way, the overall feature sizes of the word lines and active pillars are smaller, and a further shrinkable semiconductor structure can be obtained.
  • a memory provided by an embodiment of the present disclosure includes: at least one semiconductor structure according to any one of the above solutions, a storage structure located on the semiconductor structure, and a storage structure located around the semiconductor structure or above the storage structure. Peripheral circuits.
  • the semiconductor structure is coupled to the memory unit and the peripheral circuit; wherein the peripheral circuit is configured to: receive a read or write command; in response to the read or write command, read or rewrite the The information stored in the storage structure.
  • the memory includes: DRAM
  • the storage structure includes: a capacitor; more specifically, the capacitor may include a cup-shaped capacitor, a barrel-shaped capacitor, or a columnar capacitor.
  • the capacitor includes a columnar second electrode, a dielectric covering the sidewalls and bottom of the second electrode, and a first electrode covering the dielectric.
  • the second electrode terminal may be connected to the top active area TA in the active pillar, and the first electrode terminal may be connected to a reference voltage.
  • the reference voltage may be ground voltage, or may include other voltages.
  • the capacitor represents logical "1"s and "0s" by the amount of charge stored in it.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 3, a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:
  • the active pillars include a top active region, a channel region and a bottom In the active area, the first direction and the second direction intersect and are both parallel to the substrate surface;
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • FIG. 4a to 4s are schematic three-dimensional structural diagrams of a manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 3 and FIG. 4 a to FIG. 4 s.
  • Steps S301 and S302 are executed, and with reference to FIGS. 4a to 4e and 4j to 4l, a substrate is provided and an active pillar array is formed.
  • the material of the substrate 100 may include silicon, germanium, silicon germanium substrate, etc.; the material of the substrate 100 may also be silicon on insulator or germanium on insulator.
  • forming the active pillar array includes the following steps:
  • the remaining second semiconductor layer forms the top active region of the active pillar
  • the third semiconductor layer forms the channel region of the active pillar and the remaining active layer forming the bottom active region of the active pillar;
  • the dielectric layer and the word line are sequentially formed in the fifth trench and the sixth trench.
  • Step a is performed, referring to FIG. 4b, to form an active layer, a first semiconductor layer and a second semiconductor layer.
  • an ion implantation process is used to dope a material with certain impurity ions into the top of the substrate 100 to form the active layer 101 .
  • the impurity ions may be N-type impurity ions or P-type impurity ions; in one embodiment, the doped source and drain regions are doped.
  • the material of the substrate 100 includes silicon, and the top of the substrate 100 is heavily doped with N-type to form the active layer 101 with N-type heavy doping.
  • a thin film deposition process is used to sequentially deposit the first semiconductor layer 102 and the second semiconductor layer 103 on the surface of the active layer 101 .
  • the thin film deposition process includes but is not limited to physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) and other processes.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD Atomic Layer Deposition
  • the first semiconductor layer 102 can be formed on the surface of the active layer 101 through an epitaxial growth process (EGP); the second semiconductor layer 103 can be formed on the first surface.
  • the surface of the semiconductor layer 102 is formed by EGP.
  • the second semiconductor layer 103 adopts an in-situ doping process, which can include but is not limited to PVD, CVD process or ALD process. While epitaxially growing silicon, gas containing N-type doping atoms is introduced while depositing the epitaxial growth silicon. N-type heavy doping was also performed.
  • the first semiconductor layer 102 and the second semiconductor layer 103 have different etching selectivity ratios.
  • the material of the first semiconductor layer 102 is silicon germanium
  • the material of the second semiconductor layer 103 is N-type heavily doped silicon.
  • the material of the second semiconductor layer 103 is N-type heavily doped silicon, and the second semiconductor layer 103 is formed using an in-situ doping process.
  • a process including, but not limited to, PVD, CVD or ALD can be used.
  • Gas containing N-type doping atoms is introduced while epitaxially growing silicon.
  • N-type heavy doping is also performed while epitaxially growing silicon while depositing it.
  • Step b refer to Figure 4c and Figure 4d, to form a first trench and fill the first trench.
  • the top surface of the second semiconductor layer 103 is first etched through a photolithography-etching process (LE, Lithography-Etch) to form a plurality of first trenches T1 spaced apart along the second direction.
  • each first trench T1 extends along the first direction.
  • the first trench T1 penetrates the active layer 101 , the first semiconductor layer 102 and the second semiconductor layer 103 and extends into the substrate 100 .
  • the first trench T1 divides the active layer 101, the first semiconductor layer 102 and the second semiconductor layer 103 into a plurality of strip structures extending along the first direction.
  • the first trench T1 is filled with a first insulating material 201; wherein the top surface of the first insulating material 201 is substantially flush with the top surface of the second semiconductor layer 103.
  • the constituent material of the first insulating material 201 includes but is not limited to silicon dioxide (SiO 2 ).
  • the first etching includes but is not limited to a dry plasma etching process.
  • the first trench T1 includes but is not limited to a Shallow Trench Isolation (STI) structure.
  • STI Shallow Trench Isolation
  • Step c is performed, referring to Figure 4e, to form the second trench and the third trench.
  • a second etching is performed on the top surface of the second semiconductor layer 103 through a photolithography-etching process to form a plurality of second trenches T2 and third trenches T3 alternately arranged along the first direction.
  • each of the second trench T2 and the third trench T3 extends along the second direction.
  • the second trench T2 and the third trench T3 both penetrate the first semiconductor layer 102 and the second semiconductor layer 103 and extend into the active layer 101 .
  • the second trench T2 and the third trench T3 divide the plurality of strip-shaped active layers 101, the first semiconductor layer 102 and the second semiconductor layer 103 into multiple strips along the first direction. and a plurality of columnar structures arranged in an array in the second direction.
  • the second etching includes but is not limited to a dry plasma etching process.
  • a hard mask layer 104 is added before dry plasma etching to protect the top surface of the second semiconductor layer 103 and reduce the thickness of the second semiconductor layer 103 . of the top is consumed.
  • the material of the hard mask layer 104 includes but is not limited to silicon dioxide.
  • step S305 is executed to form bit lines.
  • the formed bit lines BL extend along the first direction and are electrically connected to the bottoms of the active pillars AP (refer to FIG. 4l ) arranged in the same row along the first direction.
  • Active area BA (refer to Figure 4l).
  • bit lines includes:
  • a protective layer 105 is formed on the sidewalls of the second trench T2 and the third trench T3;
  • the bottoms of the second trench T2 and the third trench T3 are etched to form a groove T11 so that part of the second trench T2 and the third trench
  • the depth of T3 increases and the width dimension of the groove T11 along the first direction is greater than the width dimension of the second groove T2 or the third groove T3;
  • a first metal layer is formed in the groove
  • the first metal layer reacts with the active area of the groove sidewall to form a metal compound layer 111, and the groove is filled with a second metal layer 112.
  • the second metal layer 112 and The metal compound layer 111 collectively forms the bit line BL.
  • the etching process used may include a wet etching process, a dry etching process, etc.
  • the protective layer 105 is used as a mask, and the etchant is passed into the bottoms of the second trench T2 and the third trench T3. Isotropic etching increases the diameter width of the bottoms of the second trench T2 and the third trench T3 along the X-axis direction, and the width dimension of the groove T11 along the first direction is larger than the The width dimension of the second groove T2 or the third groove T3 results in a groove T11 having a bowl-shaped space.
  • the grooves T11 can be understood as a plurality of grooves T11 corresponding one-to-one with the second grooves T2 and the third grooves T3 along the first direction.
  • the metal compound layer 111 is formed in the groove and the second metal layer 112 is filled, to obtain the second metal layer 112 and the metal compound layer 111.
  • the bit lines BL, and the metal compound layer 111 both extend along the first direction, and the second metal layer 112 is spaced apart by parts of the metal compound layer 111 along the first direction.
  • the protective layer 105 is used as a mask to pass the etchant into the bottoms of the second trench T2 and the third trench T3. Isotropic etching by the etchant etches open the middle part of the active layer 101 through over-etching, so that the bottoms of the second trench T2 and the third trench T3 are connected to each other along the X-axis direction.
  • the resulting groove T11 is integral and extends along the X-Y plane.
  • the metal compound layer 111 is formed in the groove and the second metal layer 112 is filled to obtain the second metal layer 112 and the metal compound layer 111.
  • the bit line BL is formed, and the second metal layer 112 and the metal compound layer 111 both extend along the first direction.
  • the material of the first metal layer and the material of the second metal layer may be the same or different.
  • the material of the first metal layer is different from the material of the second metal layer.
  • the material of the first metal layer may include at least one of cobalt, nickel, chromium, tin, silver, and gold. 1.
  • the material of the second metal layer 112 may include tungsten.
  • the material of the first metal layer and the second metal layer are the same, and the constituent materials of the first metal layer and the second metal layer 112 both include cobalt.
  • the first metal layer can be deposited on the exposed active layer 101 in the groove T11 through PVD, CVD, ALD and other processes; a heat treatment process, such as a rapid thermal annealing process (RTP), can be used. , Rapid Thermal Process), causing the first metal layer to react with the active layer 101 in contact with its surroundings to form a metal compound layer 111; here, the metal compound layer 111 extends along the first direction.
  • the metal compound layer 111 is used as a bit line.
  • the second metal layer 112 may be further deposited in the groove T11 where the metal compound is formed through processes such as PVD, CVD, and ALD. In this way, the second metal layer 112 and the metal compound layer 111 together form the bit line BL.
  • the bit line BL and the active layer 101 can be Ohmic contact is formed between them, which is beneficial to reducing contact resistance.
  • the top surface of the bit line BL is lower than the top surface of the active layer 101 .
  • the bit line BL completely fills the groove T11, that is, the top surface of the bit line BL is flush with the top of the groove T11.
  • the top surface of the bit line BL is flat (as shown in Figures 2a and 2b) or arcuate (as shown in Figures 2c and 2d).
  • the method before filling the second metal layer 112 in the groove, the method further includes: forming a diffusion barrier layer (not shown) in the groove where the metal compound layer 111 is formed.
  • a diffusion barrier layer (not shown) may be formed in the groove where the metal compound layer 111 is formed through processes such as PVD, CVD, ALD, etc.
  • the diffusion barrier layer is used to prevent the material of the second metal layer 112 from diffusing to the metal compound layer 111 after the second metal layer 112 is formed in the groove where the diffusion barrier layer (not shown) is formed. , in the active layer 101.
  • the diffusion barrier layer is made of titanium nitride (TiN).
  • the second trench T2 and the third trench T3 in which the protective layer 105 is formed are filled with the second insulating material 106.
  • the second insulating material 106 includes, but is not limited to, silicon dioxide.
  • the depths of the second trench T2 and the third trench T3 are the same, and the depth of the first trench T1 is greater than that of the second trench T2 and the third trench T3.
  • the second trench T2 and the third trench T3 penetrate the first semiconductor layer 102 and the second semiconductor layer 103 and extend into the active layer 101 , and the groove T11 Also located in the active layer 101; the first trench T1 penetrates the first semiconductor layer 102, the second semiconductor layer 103 and the active layer 101, and extends into the substrate. That is, referring to FIG. 4i, the bottom surface of the bit line BL is higher than the bottom surface of the first insulating material 201.
  • bit lines BL and the first insulating material 201 are alternately arranged at intervals along the second direction; it is ensured that a plurality of bit lines BL are separated by the first insulating material 201 and are independent of each other.
  • Perform step d refer to Figure 4j to Figure 4k, to form a fourth trench.
  • a selective etching process is used to remove part of the first semiconductor layer 102 in the second trench along the first direction.
  • the selective etching process may include Atomic-Layer Etching (ALE).
  • the selective etching process may include quasi-Atomic-Layer Etching (qALE). Layer Etching).
  • the sidewall at the position of the first semiconductor layer 102 in the second trench T2 is removed to form a fourth trench T4, including:
  • a portion of the first semiconductor layer 102 is removed along the first direction.
  • ALE or qALE can be used to remove part of the first semiconductor layer 102 finely, ensuring that the fourth groove T4 is recessed along the first direction into the characteristic size and sidewall shape of the first semiconductor layer 102.
  • the appearance is precisely controlled to prepare for the precise positioning of the formation position of the channel region in subsequent processes.
  • a third semiconductor layer is formed in the fourth trench T4, including:
  • a third semiconductor layer is formed in the fourth trench T4 by epitaxial growth.
  • the third semiconductor layer is deposited by EGP, and the fifth trench T5 is also obtained (which can be understood as the fourth trench T4 having the third semiconductor layer).
  • the third semiconductor layers are arranged in an array along the first direction and the second direction, and each third semiconductor layer connects the first semiconductor layer 102 and the third semiconductor layer along the third direction.
  • Two semiconductor layers 103 are arranged in an array along the first direction and the second direction, and each third semiconductor layer connects the first semiconductor layer 102 and the third semiconductor layer along the third direction.
  • the remaining second semiconductor layer 103 forms the top active area TA of the active pillar AP
  • the third semiconductor layer forms the channel area CH of the active pillar
  • the remaining The active layer 101 forms the bottom active area BA of the active pillar.
  • the material of the third semiconductor layer and the second semiconductor layer are the same.
  • the second semiconductor layer 103 and the third semiconductor layer are both made of N-type heavily doped silicon (Si).
  • the remaining first insulating material and the remaining first semiconductor layer are removed from the third trench to form a sixth trench.
  • removing the remaining first insulating material may be understood to include at least removing the first insulating material located between the channel regions CH and the top active region TA.
  • the third trench is filled with an insulating material (for example, refer to the second insulating material 106 and the protective layer 105 in FIG. 4n), and all remaining materials are removed from the third trench.
  • the first insulating material and the remaining first semiconductor layer 102 are also removed, and part of the insulating material in the third trench is also removed.
  • the part of the insulating material at least includes between the channel region CH and the Insulating material between the top active areas TA (for example, refer to the second insulating material 106 and the protective layer 105 between the channel areas CH and the top active areas TA in FIG. 4n).
  • the bottom surface of the sixth trench T6 is flush with or not flush with the bottom surface of the fifth trench T5 (refer to FIG. 4m).
  • the bottom surface of the sixth trench T6 is flush with the bottom surface of the fifth trench T5 (refer to FIG. 4m).
  • the active pillars AP are arranged in an array along the first direction and the second direction, and each active pillar AP includes the top active area TA, the bottom active area BA and The third direction connects the channel regions CH of each top active area TA and each bottom active area BA.
  • the fifth trench and the sixth trench are used to sequentially form the dielectric layer and the word line in the fifth trench and the sixth trench in a subsequent process (details Refer to Figures 4m to 4n, and Figures 4o to 4s) described below.
  • step S303 and step S304 refer to FIGS. 4m to 4n, and 4o to 4s to form word lines and dielectric layers.
  • forming the dielectric layer and the word line sequentially in the fifth trench and the sixth trench includes:
  • the remaining conductive layer forms the word line.
  • part of the dielectric layer and part of the conductive layer may be formed in the fifth trench first, and then the sixth trench may be formed, part of the dielectric layer and part of the conductive layer may be formed in the sixth trench, and then the fifth and part of the conductive layer may be removed simultaneously.
  • Part of the conductive layer in the six trenches forms word lines located in the fifth and sixth trenches respectively.
  • a dielectric layer and a conductive layer are formed in the fifth and sixth trenches at the same time, and then part of the conductive layer in the fifth and sixth trenches is removed simultaneously to form a word line.
  • a dielectric layer and a conductive layer are formed in the fifth trench.
  • the dielectric layer 109 can be formed through an in-situ oxidation process (ISSG, In Situ Steam Generation).
  • ISSG In situ Steam Generation
  • at least part of the sidewall of each channel region CH is exposed in the fifth trench (refer to FIG. 4l), and in the fifth trench T5, by heating or pressurizing, At least the exposed sidewalls of each channel region CH are oxidized in situ to form the dielectric layer 109 .
  • the material of the dielectric layer 109 includes but is not limited to silicon dioxide. It should be noted that here, the dielectric layer 109 covers part of the channel region CH, but does not surround all sidewalls of the channel region CH.
  • the dielectric layer 109 is formed by performing in-situ oxidation on the exposed portion of each active pillar AP (including the channel region CH) and the sidewall in the fifth trench.
  • the conductive layer 110 may be deposited in the fifth trench T5 having the dielectric layer 109 through a PVD process, a CVD process or an ALD process. It should be noted that here, the conductive layer 110 covers part of the channel region CH, but does not surround all sidewalls of the channel region CH.
  • the material of the conductive layer 110 may be a metal material or a semiconductor conductive material, such as copper, cobalt, nickel, tungsten, molybdenum, doped silicon, polysilicon or any combination thereof.
  • a dielectric layer and a conductive layer are formed in the sixth trench.
  • each channel region CH is exposed in the sixth trench T6 (which can be understood as other sidewalls that are not exposed by the fifth trench T5).
  • the finally formed dielectric layer 109 can at least surround the sidewalls of the channel region CH.
  • the conductive layer 110 may at least surround the sidewalls of the dielectric layer 109 .
  • an isolation structure is formed and a word line is formed.
  • part of the conductive layer 110 can be removed through a photolithography-etching process to form a plurality of seventh trenches T7 spaced apart along the first direction, and the seventh trenches T7 penetrate along the third direction. the conductive layer 110 .
  • the word line WL (understood with reference to the remaining conductive material after removing part of the conductive layer 110 ) is exposed to the sidewalls of the seventh trench T7 and the top active area TA of the cladding dielectric layer 109 The side walls of the seventh trench T7 are flush in the third direction.
  • the dielectric layer 109 covering the top active area TA is also removed simultaneously (not shown in FIG. 4q ).
  • the word line WL (understood with reference to the remaining conductive material after removing part of the conductive layer 110) is exposed to the sidewalls of the seventh trench T7 and the top active area TA is exposed to the sidewalls of the seventh trench T7.
  • the third direction is flush.
  • the first etching includes but is not limited to a dry plasma etching process.
  • a hard mask layer (not shown in Figure 4q) is added before dry plasma etching to protect the top surface of the active pillar AP and reduce the damage to the top surface of the active pillar AP. consumption, the height of the top active area TA in the active pillar AP in the third direction may also be increased.
  • the isolation structure 204 extending along the second direction may be formed in the seventh trench T7 (refer to FIG. 4q) through a PVD process, a CVD process or an ALD process.
  • the material of the isolation structure 204 includes, but is not limited to, silicon dioxide.
  • part of the conductive layer is removed through an etching back process, and an isolation structure extending along the second direction is formed at the location where the part of the conductive layer is removed; wherein the remaining conductive layer forms the word line.
  • the depth of the etching back along the third direction is substantially consistent with the height of the top active area TA in the active pillar AP along the third direction.
  • the basic agreement can be understood as the depth of etching back along the third direction is the same as the height of the top active area TA in the active pillar AP along the third direction, or, Within the process error range, the depth of the etching back along the third direction is slightly less than or greater than the height of the top active area TA in the active pillar AP along the third direction.
  • the material of the isolation structure includes, but is not limited to, silicon dioxide.
  • the word line WL is formed, the word line WL extends along the second direction, and covers the channel region CH of the active pillars AP arranged in the same column along the second direction; forming The dielectric layer 109 is located between the word line WL and the active pillar AP and at least covers the surface of the channel region CH; wherein, in the first direction, the The size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the sum W4 of the size of the top active region and the size of the dielectric layer. In other specific embodiments, in the first direction, the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the size of the top active region.
  • the method further includes:
  • a portion of the second insulating material in the third trench is removed.
  • the top surface of the remaining second insulating material in the trench is lower than the top surface of the active layer.
  • the top surface of the remaining second insulating material in the second trench may be lower than the top surface of the active layer.
  • the remaining second insulating material in the second trench may be lower than the top surface of the active layer.
  • the remaining top surface of the second insulating material may be flush with the top surface of the active layer.
  • flush solution please refer to the description of the manufacturing process of the relevant semiconductor structure in Figures 5a to 5j below.
  • a portion of the second insulating material 106 in the second trench is removed, and the top surface of the remaining second insulating material 106 in the second trench is lower than the top of the active layer 101 .
  • a portion of the second semiconductor layer 102 in the third trench is removed. Insulating material 106 , the top surface of the remaining second insulating material 106 in the third trench is lower than the top surface of the active layer 101 .
  • a protective layer 105 is formed on the sidewalls of the second trench and the third trench; When part of the second insulating material 106 in the second trench is removed, the protective layer 105 is also removed simultaneously. The remaining protective layer 105 and the top surface of the second insulating material 106 are lower than The top surface of the active layer 101 .
  • a protective layer 105 on the sidewalls of the second trench and the third trench and filling the second insulating material 106 covering the protective layer 105 are described as examples.
  • materials of the protective layer 105 and the second insulating material 106 include but are not limited to silicon dioxide.
  • part of the top surface of the active layer 101 can be exposed in the fifth trench and the sixth trench, and part of the sidewalls of the active layer 101 can also be exposed to facilitate formation of the active layer 101 in the subsequent process.
  • Different forms of word lines for example, part of the bottom surface of the word line WL formed in FIGS. 2 a and 2 c are not flush with the top surface of the active layer 101 .
  • word line formation scheme 1 The word line formation method shown in FIGS. 4 h to 4 s is hereinafter referred to as word line formation scheme 1.
  • the method further includes:
  • a portion of the second insulating material in the third trench is removed.
  • the remaining top surface of the second insulating material in the trench is flush with the top surface of the active layer.
  • FIG. 5a to 5j are schematic three-dimensional structural views of another manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figures 5a to 5j can replace Figures 4j to 4s in Figures 4a to 4s. That is to say, Figures 4a to 4i and Figures 5a to 5j are another semiconductor structure provided by an embodiment of the present disclosure. Schematic diagram of the three-dimensional structure of the manufacturing process.
  • word line forming solution 2 a word line is formed (hereinafter referred to as word line forming solution 2).
  • part of the first semiconductor layer 102 is removed, exposing part of the top surface of the active layer 101, part of the top surface of the active layer 101 and the second trench The top surface of the remaining second insulating material 106 is flush.
  • the channel region CH is formed.
  • the bottoms of the two opposite channel regions CH (the channel region CH and the bottom The distance between the junctions of the active areas BA) is smaller than the distance between the tops of the two opposite channel areas CH (the junctions of the channel areas CH and the top active areas TA).
  • the remaining first semiconductor layer 102 is removed (refer to FIG. 5e), exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the bottom surface.
  • the top surface of the source area BA is removed (refer to FIG. 5e), exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the bottom surface.
  • the word line WL is formed, and the bottom surface of the word line WL is at least partially flush with the top surface of the bottom active area BA.
  • the specific differences between the word lines WL in Figure 5j and Figure 4s can be understood with reference to the differences between the word lines WL in Figures 2a and 2b, and will not be described again here.
  • the height of the word line WL formed in the third direction is different.
  • the word line WL formed in the word line forming scheme 2 is in The higher height in the third direction can increase the contact area between the channel region and the word line, thereby reducing the height of the channel region and increasing the structural stability of the channel region.
  • forming the dielectric layer and the word line sequentially in the fifth trench and the sixth trench includes:
  • the remaining conductive layer forms the word line.
  • FIG. 6a to 6e are schematic three-dimensional structural diagrams of yet another manufacturing process of a semiconductor structure provided by embodiments of the present disclosure.
  • Figures 6a to 6e can replace Figures 4l to 4s in Figures 4a to 4s. That is to say, Figures 4a to 4k and Figures 6a to 6e are yet another semiconductor structure provided by an embodiment of the present disclosure. Schematic diagram of the three-dimensional structure of the manufacturing process.
  • a dielectric layer and a conductive layer are simultaneously formed in the fifth trench and the sixth trench. Details will be described below in conjunction with FIGS. 4a to 4k and 6a to 6e.
  • the solution of simultaneously forming a dielectric layer and a conductive layer in the fifth trench and the sixth trench to form a word line (hereinafter referred to as word line formation solution 3) will be described.
  • the remaining first semiconductor layer 102 is removed to expose all the sidewalls of the channel region CH, all the sidewalls of the top active area TA, part of the top surface of the bottom active area BA and The side walls, that is to say, the gap between the active pillars AP penetrates into an overall gap space T12, which is equivalent to the fifth trench T5 and the sixth trench in FIGS. 4l to 4p formed together and mutually. The penetration forms an integral gap space T12.
  • the dielectric layer 109 at least surrounding the active region CH can be formed through an in-situ oxidation process.
  • the conductive layer 110 at least surrounding the dielectric layer 109 can be formed through a single deposition process.
  • the dielectric layer at least surrounding the active region CH is formed by performing an in-situ oxidation process in the fifth trench T5 and the sixth trench T6 respectively. 109 and perform a deposition process each to form the conductive layer 110 that at least surrounds the dielectric layer 109 .
  • the method of forming the isolation structure 204 and the word line is the same as that of FIGS. 4q to 4s and will not be described again here.
  • the word line WL is formed through an in-situ oxidation process to form the dielectric layer 109 at least surrounding the active region CH and A deposition process forms the conductive layer 110 at least surrounding the dielectric layer 109 . It has the advantage of simplifying the process flow.
  • FIGS. 6a to 6e are modified examples of the manufacturing process of the same type of semiconductor structure (hereinafter referred to as word line formation scheme 4).
  • the top surface of the remaining second insulating material 106 in the third trench is flush with the top surface of the remaining second insulating material 106 in the second trench and is The top surface of the active layer 101 is flush.
  • the lengths of the word lines formed in the fifth trench and the sixth trench along the third direction are different. In other embodiments, the lengths of the word lines formed in the fifth trench and the sixth trench are different.
  • the lengths of the word lines formed in the sixth trench along the third direction may be the same, specifically:
  • the method before forming the dielectric layer 109, the method further includes:
  • part of the second insulating material 106 (refer to FIG. 4n ) in the third trench T3 (refer to FIG. 4n ) is removed, and the remaining first semiconductor layer 102 is removed (refer to FIG. 4n ). , exposing the remaining top surface of the channel region CH, the remaining top surface of the top active area TA, and part of the top surface of the bottom active area BA;
  • the third semiconductor layer is deposited by EGP.
  • a dielectric layer 109 is formed in the sixth trench to make the channel region CH symmetrical.
  • the symmetry of the channel region CH means that the channel region CH is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the dielectric layer 109 may also be symmetrical.
  • the symmetry of the dielectric layer 109 means that the dielectric layer 109 is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the semiconductor structure that can finally be formed is as shown in FIG. 2c and FIG. 2d.
  • the word line WL is symmetrical about the Y-Z plane passing through the center of the channel region CH, and/or is symmetrical about the X-Y plane passing through the center of the channel region CH.
  • the difference between FIG. 2c and FIG. 2d is that the height of the word line WL shown in FIG. 2c along the third direction is smaller than the height of the word line WL shown in FIG. 2d along the third direction.
  • the manufacturing method of the semiconductor structure uses an epitaxial growth process to form a first semiconductor layer as a sacrificial layer; and by removing the first semiconductor layer, epitaxial growth forms a channel at the location where the first semiconductor layer is removed. area; and then form a word line covering the channel area through a self-alignment process.
  • the word line WL manufactured by the manufacturing method of the semiconductor structure has the following structural characteristics: 1.
  • the word line WL is embedded in the active pillar AP, and the corresponding active pillar AP is similar to a dumbbell shape, that is, In the first direction, the size W1 of the channel region is smaller than the size W2 of the top active region, and the size W3 of the word line does not exceed the size of the top active region and the size of the dielectric layer.
  • the sum of the sizes is W4, so that the distance between adjacent word lines WL is increased, the parasitic capacitance is smaller, and the electrical properties are better; 2.
  • the word lines WL that fully surround the channel region CH along the third direction can be unequal or equal, with an asymmetric structure (as shown in Figures 2a and 2b) or a symmetrical structure (as shown in Figures 2c and 2d).
  • the length, width and other dimensions of the word line covering the first side wall and the word line covering the second side wall exist in the word line WL that fully surrounds the channel region CH. They can be set independently, so that the word line WL is embedded in the side wall of the channel region CH, increasing the contact area between the channel region CH and the word line WL, and reducing the height of the channel region CH.
  • the overall size of the word line WL and the channel of the transistor T is used to achieve continuous shrinkage of the transistor size, thereby improving the performance of DRAM; at the same time, the structure and size of the word line WL are adjustable and have good Process suitability.
  • the semiconductor structure manufactured by the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above-mentioned embodiments.
  • For technical features that are not disclosed in detail in the embodiments of the present disclosure please refer to the above-mentioned embodiments for understanding. Here, no further details will be given. Repeat.
  • the size of the channel region is smaller than the size of the top active region, and the size of the word line does not exceed the sum of the size of the top active region and the size of the dielectric layer. That is to say, the word line in the semiconductor structure
  • the active pillars are embedded in and cover the channel area of the active pillars.
  • the corresponding active pillars have a dumbbell-like shape.
  • the first aspect can increase the distance between adjacent word lines, so that the word lines The coupling between lines is smaller, and the electrical properties of the word lines are better; secondly, the overall feature size of the word lines and active pillars can be made smaller, thereby further shrinking the semiconductor structure.

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Abstract

Des modes de réalisation de la présente divulgation concernent une structure semi-conductrice et son procédé de fabrication, ainsi qu'une mémoire. La structure semi-conductrice comprend : un substrat ; des piliers actifs, qui sont situés sur une surface du substrat, la pluralité de piliers actifs formant un réseau de piliers actifs ayant plusieurs colonnes agencées dans une première direction et plusieurs rangées agencées dans une seconde direction, et chaque pilier actif comprenant une région active supérieure, une région de canal et une région active inférieure, la première direction et la seconde direction se croisant et étant toutes deux parallèles à la surface du substrat ; des lignes de mots, qui s'étendent dans la seconde direction et recouvrent les régions de canal des piliers actifs dans la même colonne agencée dans la première direction ; une couche diélectrique, qui est située entre les lignes de mots et les piliers actifs et recouvre au moins une surface de la région de canal ; et des lignes de bits, qui s'étendent dans la première direction et sont électriquement connectées aux régions actives inférieures des piliers actifs dans la même rangée agencée dans la seconde direction, et dans la première direction, la taille de la région de canal étant inférieure à celle de la région active supérieure, et la taille des lignes de mots ne dépassant pas la somme de la taille de la région active supérieure et de la taille de la couche diélectrique.
PCT/CN2022/118639 2022-08-22 2022-09-14 Structure semi-conductrice et son procédé de fabrication, et mémoire WO2024040645A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034759A (zh) * 2009-09-30 2011-04-27 海力士半导体有限公司 具有掩埋位线的半导体器件及其制造方法
US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
CN112185961A (zh) * 2019-07-03 2021-01-05 美光科技公司 集成式组合件以及形成集成式组合件的方法
CN114141715A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114141713A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034759A (zh) * 2009-09-30 2011-04-27 海力士半导体有限公司 具有掩埋位线的半导体器件及其制造方法
US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
CN112185961A (zh) * 2019-07-03 2021-01-05 美光科技公司 集成式组合件以及形成集成式组合件的方法
CN114141715A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114141713A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

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