WO2024036744A1 - 电源电路与芯片 - Google Patents

电源电路与芯片 Download PDF

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Publication number
WO2024036744A1
WO2024036744A1 PCT/CN2022/126376 CN2022126376W WO2024036744A1 WO 2024036744 A1 WO2024036744 A1 WO 2024036744A1 CN 2022126376 W CN2022126376 W CN 2022126376W WO 2024036744 A1 WO2024036744 A1 WO 2024036744A1
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Prior art keywords
voltage
unit
output
resistor
circuit
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PCT/CN2022/126376
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English (en)
French (fr)
Inventor
秦建勇
尚为兵
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长鑫存储技术有限公司
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Publication of WO2024036744A1 publication Critical patent/WO2024036744A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and specifically, to a power supply circuit and a chip using the power supply circuit.
  • the purpose of this disclosure is to provide a power supply circuit and a chip using the power supply circuit, so as to further reduce the power consumption of the integrated circuit at least to a certain extent.
  • a power supply circuit including: a reference voltage generation circuit for generating a substrate reference voltage with a negative temperature coefficient; a voltage generation circuit for reducing the substrate voltage according to an enable signal; enabling A signal generation circuit connected to the reference voltage generation circuit and the voltage generation circuit, configured to output the voltage generation circuit to the voltage generation circuit when the substrate reference voltage is less than a conversion voltage proportional to the substrate voltage. enable signal.
  • the voltage generation circuit includes: an oscillation module, an input end is used to receive the enable signal, an output end is used to output an oscillation signal, and the oscillation module is used according to the An enable signal generates the oscillation signal; a charge pump module, an input end is connected to the oscillation module, an output end is used to output the substrate voltage, and the charge pump module is used to reduce the substrate voltage according to the oscillation signal.
  • the charge pump module includes: a first capacitor, a first end of the first capacitor is coupled to the output end of the oscillation module; a first diode, the cathode of which is grounded , the anode is connected to the second end of the first capacitor; the second diode, the cathode is connected to the second end of the first capacitor, and the anode is used to output the substrate voltage.
  • the charge pump module further includes a drive circuit connected between the output end of the oscillation module and the first end of the first capacitor, where the drive circuit is used to Increase the amplitude of the oscillation signal.
  • the charge pump module further includes a second capacitor, a first terminal of the second capacitor is connected to the anode of the second diode, and a third terminal of the second capacitor is connected to the anode of the second diode. Two ends are connected to ground, and the second capacitor is used to maintain the output voltage of the charge pump module.
  • the enable signal generation circuit includes: a voltage follower, a non-inverting input terminal of the voltage follower is used to receive the substrate reference voltage, an inverting input terminal and an output terminals are connected; the first voltage dividing unit has two input terminals respectively connected to the output terminal of the voltage follower and the power supply voltage, and the output terminal is used to output the first divided voltage generated based on the substrate reference voltage and the power supply voltage.
  • a second voltage dividing unit with two input terminals respectively connected to the output terminal of the voltage generating circuit and the power supply voltage, and the output terminal is used to output the second divided voltage generated based on the substrate voltage and the power supply voltage;
  • a comparator the non-inverting input end is connected to the output end of the first voltage dividing unit, and the inverting input end is connected to the output end of the second voltage dividing unit;
  • an inverter the input end of the inverter is connected to the comparator.
  • An output terminal the output terminal of the inverter is connected to the voltage generating circuit and is used to output the enable signal.
  • the first voltage dividing unit includes a first voltage dividing resistor unit and a second voltage dividing resistor unit connected in series, and the first end of the first voltage dividing resistor unit is connected to The power supply voltage, the first end of the second voltage dividing resistor unit is connected to the second end of the first voltage dividing resistor unit, and the second end of the second voltage dividing resistor unit is connected to the output of the voltage follower terminal; wherein, the resistance ratio of the first voltage dividing resistor unit and the second voltage dividing resistor unit is 1: (K1-1), and K1 is the first preset value.
  • the second voltage dividing unit includes a third voltage dividing resistor unit and a fourth voltage dividing resistor unit connected in series, and the first end of the third voltage dividing resistor unit is connected to The power supply voltage, the first end of the fourth voltage dividing resistor unit is connected to the second end of the third voltage dividing resistor unit, and the second end of the fourth voltage dividing resistor unit is connected to the output of the voltage generating circuit terminal; wherein, the resistance ratio of the third voltage dividing resistor unit and the fourth voltage dividing resistor unit is 1: (K2-1), and K2 is the second preset value.
  • the resistance values of the second voltage dividing resistor unit and the fourth voltage dividing resistor unit are adjustable.
  • the second voltage dividing resistor unit and the fourth voltage dividing resistor unit each include a plurality of resistor sub-units connected in series, and each of the resistor sub-units includes one or more Each resistor sub-unit is connected in parallel with a resistance adjustment switch tube, and the control end of each resistance adjustment switch tube receives a control signal.
  • the resistance value of each of the sub-resistors is equal.
  • the reference voltage generating circuit includes: a constant current generating module configured to generate a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, and generate the current according to the first The current and the second current generate a constant current; a substrate reference voltage generation module includes a transistor, the voltage generation module is coupled to the constant current generation module and is used to generate all negative temperature coefficients according to the constant current and transistor characteristics. The substrate reference voltage.
  • the constant current generation module includes: a positive temperature coefficient current generation unit for generating the first current; a negative temperature coefficient current generation unit connected to the positive temperature coefficient current A generating unit configured to generate the second current.
  • the positive temperature coefficient current generating unit includes: a first amplifier; a first feedback transistor, the source of the first feedback transistor is connected to the power supply voltage, and the gate is connected to the first feedback transistor.
  • the second bridge arm the second bridge arm includes a second resistor in series, a third resistor and a plurality of second PN junction units in parallel, the first end of the second resistor is connected to the first node, and the second end is connected to the The non-inverting input terminal of the first amplifier; the first terminal of the third resistor is
  • the resistance values of the first resistor and the second resistor are equal.
  • the negative temperature coefficient current generating unit includes: a second amplifier, the inverting input terminal of the second amplifier is connected to the inverting input terminal of the first amplifier; A feedback transistor, the source of the second feedback transistor is connected to the power supply voltage, the gate is connected to the output terminal of the second amplifier, and the drain is connected to the non-inverting input terminal of the second amplifier; a fourth resistor has one end connected to the The non-inverting input terminal of the second amplifier is connected to the ground at the other end; the source of the second output transistor is connected to the power supply voltage, the gate is connected to the output terminal of the second amplifier, and the drain is used to output the second current.
  • both the third resistor and the fourth resistor are adjustable resistors, and the resistance values of the third resistor and the fourth resistor satisfy (kT/q)*
  • the derivative of lnZ/R3+(kT/q*lnZ+VBE2)/R4 with respect to temperature T is zero, where R3 is the resistance of the third resistor, R4 is the resistance of the fourth resistor, and K is Bohr Zemann constant, q is the electron charge, T is the operating temperature of the power circuit, VBE2 is the voltage difference between the two ends of the second PN junction unit, Z is the second PN junction unit and the first PN junction number of units.
  • the substrate reference voltage generating module includes: a first N-type transistor, a drain and a gate of the first N-type transistor are connected to the second node, and the first N-type transistor has a drain and a gate connected to the second node. Two nodes are connected to the drain of the first output transistor and the drain of the second output transistor, the source of the first N-type transistor is grounded, and the second node is used to output the substrate reference voltage.
  • a chip including the power circuit as described in any one of the above.
  • Embodiments of the present disclosure provide a substrate reference voltage with a negative temperature coefficient and an enable signal output module that outputs an enable signal according to the reduction of the substrate reference voltage.
  • the enable signal can be controlled.
  • the voltage output module automatically reduces the substrate voltage of the transistor and reduces the leakage current of the transistor, thereby reducing the power consumption of the integrated circuit.
  • the power circuit can automatically reduce the substrate voltage of the N-type transistor in the integrated circuit when the temperature rises, thereby reducing the leakage current of the N-type transistor and reducing the temperature of the integrated circuit. Overall power consumption.
  • FIG. 1 is a schematic diagram of a power supply circuit 100 in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the voltage generation circuit 2 in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the voltage generating circuit 2 in another embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of the enable signal generation circuit 3 in an embodiment of the present disclosure.
  • 5A and 5B are respectively schematic diagrams of an adjustable resistance unit in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the reference voltage generating circuit 1 in an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of the constant current generation module 11 in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the substrate reference voltage generation module 12 in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • FIG. 1 is a schematic diagram of a power supply circuit in an exemplary embodiment of the present disclosure.
  • power circuit 100 may include:
  • Reference voltage generation circuit 1 used to generate a substrate reference voltage Vref with a negative temperature coefficient
  • Voltage generation circuit 2 used to reduce the substrate voltage VBN according to the enable signal
  • the enable signal generation circuit 3 is connected to the reference voltage generation circuit 1 and the voltage generation circuit 2, and is used to output the enable signal EN to the voltage generation circuit 2 when the substrate reference voltage Vref is less than the conversion voltage proportional to the substrate voltage VBN. .
  • embodiments of the present disclosure can automatically reduce the substrate voltage of the transistor and reduce the leakage current of the transistor when the temperature rises and the leakage current of the transistor increases, thereby reducing the power consumption of the integrated circuit.
  • the power circuit 100 When the power circuit 100 is used to provide the substrate voltage of the N-type transistor, it can automatically reduce the substrate voltage of the N-type transistor in the integrated circuit when the temperature rises, thereby reducing the leakage current of the N-type transistor and reducing the cost of the integrated circuit. overall power consumption.
  • Figure 2 is a schematic diagram of a voltage generation circuit in one embodiment of the present disclosure.
  • the voltage generation circuit 2 may include:
  • the input terminal is used to receive the enable signal EN
  • the output terminal is used to output the oscillation signal OSC
  • the oscillation module 21 is used to generate the oscillation signal OSC according to the enable signal EN;
  • the charge pump module 22 has an input terminal connected to the oscillation module 21 and an output terminal for outputting the substrate voltage VBN.
  • the charge pump module 22 is used for reducing the substrate voltage VBN according to the oscillation signal OSC.
  • the oscillation module 21 may be implemented by a controlled ring oscillator, and the ring oscillator may include an odd number of input-output ring-series elements with signal inversion functions, such as inverters or NAND gates.
  • the oscillation module 21 outputs the oscillation signal OSC when receiving the enable signal EN, and may stop outputting the oscillation signal OSC when the enable signal EN is not received.
  • the charge pump module 22 When the charge pump module 22 does not receive the oscillation signal OSC, it can output the substrate voltage required for the normal operation of the transistor, such as the ground voltage (0V). When receiving the oscillation signal OSC, the charge pump function can be started to reduce the output voltage, that is, to reduce the substrate voltage VBN.
  • the charge pump module 22 includes:
  • the first terminal of the first capacitor C1 is coupled to the output terminal of the oscillation module 21;
  • the cathode of the first diode D1 is connected to ground, and the anode is connected to the second terminal of the first capacitor C1;
  • the cathode of the second diode D2 is connected to the second terminal of the first capacitor C1, and the anode is used to output the substrate voltage VBN.
  • the charge pump module 22 can extract negative charges from the ground terminal to the anode of the second diode D2 according to the oscillation signal OSC, and pull down the voltage of the anode of the second diode D2, thereby generating the substrate voltage VBN.
  • the oscillation module 21 stops outputting the oscillation signal OSC, the voltage at the output terminal of the charge pump module 22 , that is, the voltage at the anode of the second diode D2 no longer decreases.
  • FIG. 3 is a schematic diagram of a voltage generating circuit in another embodiment of the present disclosure.
  • the charge pump module 22 in order to adjust the output voltage reduction amplitude of the charge pump module 22 , the charge pump module 22 further includes a driver connected between the output end of the oscillation module 21 and the first end of the first capacitor C1 Circuit DR, drive circuit DR can be used to increase the amplitude of the oscillation signal OSC.
  • the charge pump module 22 may also include a second capacitor C2.
  • the first terminal of the second capacitor C2 is connected to the anode of the second diode D2.
  • the second terminal of the second capacitor C2 is connected to ground.
  • the second capacitor C2 is used to maintain charge.
  • the second voltage C2 can be used as a filter voltage to further smooth the output voltage of the charge pump module 22 and maintain the cathode voltage of the second diode D2 at a nearly stable DC voltage during the output process of the oscillation signal OSC.
  • Figure 4 is a schematic diagram of an enable signal generating circuit in an embodiment of the present disclosure.
  • the enable signal generation circuit 3 may include:
  • the non-inverting input terminal of the voltage follower 30 is used to receive the substrate reference voltage Vref, and the inverting input terminal is connected to the output terminal;
  • the first voltage dividing unit 31 has two input terminals respectively connected to the output terminal of the voltage follower 30 and the power supply voltage VCC, and the output terminal is used to output the first divided voltage V1 generated based on the substrate reference voltage Vref and the power supply voltage VCC;
  • the second voltage dividing unit 32 has two input terminals respectively connected to the output terminal of the voltage generation circuit 2 and the power supply voltage VCC, and the output terminal is used to output the second divided voltage V2 generated based on the substrate voltage VBN and the power supply voltage VCC;
  • Comparator COMP the non-inverting input terminal is connected to the output terminal of the first voltage dividing unit 31, and the inverting input terminal is connected to the output terminal of the second voltage dividing unit 32;
  • the input terminal of the inverter OP is connected to the output terminal of the comparator COMP, and the output terminal of the inverter OP is connected to the voltage generating circuit 2 for outputting the enable signal EN.
  • the voltage follower 30 is used to compensate for the weak current driving capability of the substrate reference voltage Vref with a negative temperature coefficient.
  • the first voltage dividing unit 31 includes a first voltage dividing resistor unit RZ1 and a second voltage dividing resistor unit RZ2 connected in series.
  • the first end of the first voltage dividing resistor unit RZ1 is connected to the power supply voltage VCC.
  • the first end of the second voltage dividing resistor unit RZ2 is connected to the second end of the first voltage dividing resistor unit RZ1, and the second end of the second voltage dividing resistor unit RZ2 is connected to the output end of the voltage follower 30; wherein, the first voltage dividing resistor unit RZ2
  • the resistance ratio of the resistor unit RZ1 and the second voltage dividing resistor unit RZ2 is 1: (K1-1), and K1 is the first preset value.
  • the second voltage dividing unit 32 includes a third voltage dividing resistor unit RZ3 and a fourth voltage dividing resistor unit RZ4 connected in series.
  • the first end of the third voltage dividing resistor unit RZ3 is connected to the power supply voltage VCC.
  • the fourth voltage dividing resistor unit RZ4 has a first end connected to the power supply voltage VCC. One end is connected to the second end of the third voltage dividing resistor unit RZ3, and the second end of the fourth voltage dividing resistor unit RZ4 is connected to the output end of the voltage generating circuit 2; wherein, the third voltage dividing resistor unit RZ3 and the fourth voltage dividing resistor
  • the resistance ratio of unit RZ4 is 1: (K2-1), and K2 is the second preset value.
  • the resistance value of the second voltage dividing resistor unit RZ2 is (K1-1)R
  • the resistance value of the fourth voltage dividing resistor unit RZ4 is The resistance value is (K2-1)R.
  • the voltage of the non-inverting input terminal of the comparator COMP is equal to VCC-(VCC-Vref)/K1
  • the voltage of the inverting input terminal of the comparator COMP is equal to VCC-(VCC-VBN)/K2.
  • the comparator COMP flips and outputs a low level
  • the inverter OP outputs a high level
  • the enable signal EN is a high level. level
  • the voltage generating circuit 2 starts to reduce the substrate voltage VBN.
  • the substrate reference voltage Vref with a negative temperature coefficient when the temperature increases and the transistor leakage current increases, the substrate reference voltage Vref decreases.
  • the enable signal generation circuit 3 outputs a valid enable signal EN, and the control voltage generation circuit 2 starts to reduce the substrate voltage VBN , thereby automatically reducing transistor leakage current.
  • the resistance values of the second voltage dividing resistor unit RZ2 and the fourth voltage dividing resistor unit RZ4 are adjustable.
  • the second voltage dividing resistor unit RZ2 and the fourth voltage dividing resistor unit RZ4 can be implemented by the adjustable resistor unit shown in FIG. 5A and FIG. 5B .
  • 5A and 5B are schematic diagrams of an adjustable resistance unit in an embodiment of the present disclosure.
  • the adjustable resistance unit may include multiple resistance sub-units connected in series. Each resistance sub-unit includes one or more sub-resistors. Each resistance sub-unit is connected in parallel with a resistance adjustment switch tube. The control end of each resistance adjustment switch tube is used to Receive control signals. The resistance value of each sub-resistor can be set to be equal. At this time, the adjustable resistance unit can be implemented by the resistor string 501 shown in Figure 5A.
  • the resistor string 501 includes a plurality of series-connected sub-resistors R01, R02, R03, R04, R05, and R06, and controllable resistance-adjusting switch tubes Con1, Con2, and Con3 connected to the first or second ends of the sub-resistors.
  • the first end and the second end of the resistance adjustment switch Con1 are respectively connected to the two ends of the sub-resistor R01; the first end and the second end of the resistance adjustment switch Con2 are respectively connected to the second end of the sub-resistor R01/the second end of the sub-resistor R02.
  • sub-resistor R01 constitutes a resistance sub-unit
  • the sub-circuits R02 and R03 constitute a resistance sub-unit
  • the sub-resistors R04, R05 and R06 constitute a resistance sub-unit.
  • the control terminals of the resistance adjustment switch tubes Con1, Con2, and Con3 all receive control signals.
  • the control signal comes from, for example, a processor or a one-time programmable controller, which is not specifically limited in this disclosure.
  • the resistance adjustment switch tube is implemented by an N-type transistor, and the gate of the N-type transistor serves as the control terminal.
  • the resistance adjustment switch transistor can also be implemented by other components, and the present disclosure places no special limitations on this.
  • the above resistance table varies according to the number of resistors connected across the resistance adjustment switch tubes Con1, Con2, and Con3. Those skilled in the art can adjust the number, resistance value, number of switching elements, and switching elements according to the principle shown in Figure 5A The connection relationship with the sub-resistor enables a variety of resistance settings.
  • another resistor string can be used to implement an adjustable resistor unit.
  • the resistor string 502 includes a plurality of series-connected sub-resistors R01, R02, R03, and R04.
  • the first end of the sub-resistor R01 serves as the first end of the resistor string 502, and the first ends of the sub-resistors R02, R03, and R04 are respectively
  • the second terminals of the sub-resistors R01, R02, and R03 are connected, and the second terminals of the sub-resistors R01, R02, and R03 are respectively connected to the second terminals of the resistance adjustment switch tubes Con1, Con2, and Con3.
  • the first end and the second end of the resistance adjustment switch Con1 are respectively connected to the two ends of the sub-resistor R01; the first end and the second end of the resistance adjustment switch Con2 are respectively connected to the first end of the resistor string 502 and the second end of the sub-resistor R02. terminal; the first terminal and the second terminal of the resistance adjustment switch Con3 are respectively connected to the first terminal of the resistor string 502 and the second terminal of the sub-resistor R03.
  • FIG. 6 is a schematic diagram of a reference voltage generating circuit in an embodiment of the present disclosure.
  • the reference voltage generating circuit 1 includes:
  • the constant current generation module 11 is used to generate a first current I1 with a positive temperature coefficient and a second current I2 with a negative temperature coefficient, and generate a constant current I according to the first current I1 and the second current I2;
  • the substrate reference voltage generation module 12 includes a transistor.
  • the substrate reference voltage generation module 12 is coupled to the constant current generation module 11 and is used to generate a substrate reference voltage Vref with a positive temperature coefficient according to the constant current I and the transistor characteristics.
  • the substrate reference voltage Vref generated in the embodiment shown in FIG. 6 is related to the temperature characteristics of the transistor.
  • the threshold voltage of a transistor is related to temperature.
  • the threshold voltage of an N-type transistor decreases as the temperature increases.
  • the absolute value of the threshold voltage of a P-type transistor decreases as the temperature increases. Since the threshold voltage of a P-type transistor is negative, P The threshold voltage of a transistor decreases with increasing temperature. Therefore, in the substrate reference voltage generation module 12, when a constant current I is input to the transistor, the threshold voltage Vth of the transistor changes with the temperature, and the voltage finally output by the transistor has nothing to do with the current and is only related to the temperature.
  • FIG. 7 is a schematic diagram of the constant current generation module 11 in an embodiment of the present disclosure.
  • the constant current generation module 11 may include:
  • the positive temperature coefficient current generating unit 111 is used to generate the first current I1;
  • the negative temperature coefficient current generating unit 112 is connected to the positive temperature coefficient current generating unit 111 and is used to generate the second current I2.
  • the first current I1 and the second current I2 together form the constant current I.
  • the substrate reference voltage generating module 12 is configured to output a substrate reference voltage Vref with a positive temperature coefficient according to the constant current I.
  • the substrate reference voltage Vref with a positive temperature coefficient is, for example, a voltage output based on the temperature characteristics of the P-type transistor.
  • the positive temperature coefficient current generating unit 11 may include:
  • the first amplifier AMP1 The first amplifier AMP1;
  • the first feedback transistor MB1 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the first amplifier AMP1, and its drain connected to the first node N1;
  • the first bridge arm B1 includes a first resistor R1 connected in series and a plurality of first PN junction units J1 connected in parallel.
  • the first end of the first resistor R1 is connected to the first node N1, and the second end is connected to the first node N1.
  • the inverting input terminal of the amplifier AMP1 is connected to the positive electrode of the first PN junction unit J1, and the negative electrode of the first PN junction unit J1 is grounded;
  • the second bridge arm B2 includes a second resistor R2, a third resistor R3 and a second PN junction unit J2 connected in series.
  • the first end of the second resistor R2 is connected to the first node N1, and the second end is connected to the first node N1.
  • the non-inverting input terminal of an amplifier AMP1; the first end of the third resistor R3 is connected to the non-inverting input terminal of the first amplifier AMP1, the second end is connected to the positive electrode of the second PN junction unit J2, and the negative electrode of the second PN junction unit J2 is grounded;
  • the source of the first output transistor MO1 is connected to the power supply voltage VCC, the gate is connected to the output terminal of the first amplifier AMP1, and the drain is used to output the first current I1.
  • both the first feedback transistor MB1 and the first output transistor MO1 may be P-type transistors.
  • the number of the first PN junction unit J1 is 1
  • the first PN junction unit J1 and the The two PN junction units J2 are arranged in a 3*3 array.
  • the number of the first PN junction unit J1 is 4
  • the first PN junction unit J1 and the second PN junction unit are The junction units J2 are arranged in a 4*4 array.
  • the first PN junction unit J1 is 9
  • the first PN junction unit J1 and the second PN junction unit are The junction units J2 are arranged in a 5*5 array. And so on.
  • the first resistor R1 and the second resistor R2 are the same. Due to the virtual short characteristic of the amplifier, the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the first The first resistance R1 between the node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the second resistance R2 between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, then the first bridge arm B1 and the first bridge arm B1 are equal to the non-inverting input terminal of the first amplifier AMP1. The currents on the two bridge arms B2 are the same.
  • the voltage difference between the first node N1 and the inverting input terminal of the first amplifier AMP1 is equal to the voltage difference between the first node N1 and the non-inverting input terminal of the first amplifier AMP1, and the first node N1 and the first amplifier AMP1
  • the voltage difference between the inverting input terminals of an amplifier AMP1 is equal to the PN junction voltage V BE1 of the first PN junction unit J1, then the voltage at the first terminal of the third resistor R1 is V BE1 .
  • the second end of the third resistor R3, that is, the anode voltage of the second PN junction unit J2 is V BE2 .
  • I D is the current of the PN junction unit
  • I S is the reverse saturation current of the PN junction unit (it is related to the temperature and is constant when the temperature is determined)
  • V T is the thermal voltage
  • V T kT/q
  • K is Boltzmann's constant
  • q is the electron charge
  • k 1.38 ⁇ 10 -23 J/K (Joule/Kelvin)
  • q 1.6 ⁇ 10 -19 C (Coulomb)
  • T is the absolute temperature
  • the unit is Kelvin.
  • VT is also called the voltage equivalent of temperature, which refers to the potential difference that occurs due to the temperature difference between two points in a closed circuit.
  • T 300K (normal temperature)
  • V T kT/q ⁇ 0.026V
  • n is the emission coefficient, which is related to the size, material and current of the PN junction, and is between 1 and 2.
  • the currents on the eight second PN junction units J2 connected in parallel are equal to the current on the first PN junction unit J1. Assume that each second PN junction unit The current on J2 is I 0 , then the current on the first PN junction unit J1 is 8I 0 .
  • R3 is the resistance value of the third resistor R3. Since when N is determined, V BE1 -V BE2 is proportional to V T , and V T is proportional to the temperature T. Therefore, the current I112 on the second bridge arm B2 is proportional to the temperature T and is a positive temperature coefficient current.
  • the number 8 in the formulas (2) to (7) can be replaced by the second PN junction unit J2 and the first PN junction unit J2.
  • the number of PN junction units J1 is greater than Z.
  • the current of the first feedback transistor MB1 is equal to twice the current on the second bridge arm B2, which is 2V T lnN/R3.
  • the first feedback transistor MB1 and the first output transistor MO1 form a current mirror.
  • the ratio of the channel width to length ratio of the first feedback transistor MB1 and the first output transistor MO1 is 2:1. Therefore, the first current I1 output by the drain of the first output transistor MO1 is equal to one-half The current on the first feedback transistor MB1 is equal to the current I112 on the second bridge arm B2.
  • the third resistor R3 can be set as an adjustable resistor to adjust the value of the first current I1.
  • the first PN junction unit J1 and the second PN junction unit J2 are implemented by self-biased transistors.
  • the self-biased transistors are N-type transistors, and the gates and sources of the self-biased transistors are both grounded.
  • the first PN junction unit J1 and the second PN junction unit J2 may be implemented in a variety of ways, or may be directly implemented by diodes, and the present disclosure does not place special limitations on this.
  • the negative temperature coefficient current generating unit 12 may include:
  • the inverting input terminal of the second amplifier AMP2 is connected to the inverting input terminal of the first amplifier AMP1;
  • the second feedback transistor MB2 has its source connected to the power supply voltage VCC, its gate connected to the output terminal of the second amplifier AMP2, and its drain connected to the non-inverting input terminal of the second amplifier AMP2;
  • the fourth resistor R4 has one end connected to the non-inverting input end of the second amplifier AMP2 and the other end connected to ground;
  • the source of the second output transistor MO2 is connected to the power supply voltage VCC, the gate is connected to the output terminal of the second amplifier AMP2, and the drain is used to output the second current I2.
  • the second output transistor MO2 and the second feedback transistor MB2 form a current mirror.
  • the voltages at the non-inverting input terminal and the inverting input terminal of the second amplifier AMP2 are equal, the voltage on the fourth resistor R4 is equal to the junction voltage V BE1 of the first PN junction unit J1, then the current on the second feedback transistor MB2 is equal to V BE1 /R4 , assuming that the ratio of the channel width to length ratio of the second feedback transistor MB2 and the second output transistor MO2 is 1:1, the second current I2 output by the drain of the second output transistor MO2 is:
  • V BE1 V BE2 +V T ln 8 (9)
  • V BE2 is the negative temperature coefficient voltage
  • I2 is the negative temperature coefficient current
  • I1 is the positive temperature coefficient current
  • I2 is the negative temperature coefficient current
  • V T and V BE2 are both values related to the temperature T. Adjust the resistance values of the third resistor R3 and the fourth resistor R4.
  • formula (11) changes to the temperature
  • the constant current I is a zero temperature coefficient current.
  • both the third resistor R3 and the fourth resistor R4 are adjustable resistors, which can be implemented through the embodiment shown in FIG. 5A or FIG. 5B , and will not be described again here.
  • FIG. 8 is a schematic diagram of a substrate reference voltage generation module in an embodiment of the present disclosure.
  • the substrate reference voltage generation module 12 may include:
  • the drain and gate of the first N-type transistor MN1 are connected to the second node N2.
  • the second node N2 is connected to the drain of the first output transistor MO1 and the drain of the second output transistor MO2.
  • the source of an N-type transistor MN1 is grounded, and the second node N2 is used to output the substrate reference voltage Vref with a negative temperature coefficient.
  • the substrate reference voltage Vref is due to the negative temperature coefficient. It is only affected by the constant current I and the characteristics of the first N-type transistor MN1, and the constant current I has nothing to do with temperature, so the substrate reference voltage Vref with a negative temperature coefficient is only related to the characteristics of the first N-type transistor MN1.
  • the threshold voltage (Vth) of the first N-type transistor MN1 decreases as the temperature increases, and the current flowing through the first N-type transistor MN1 is a constant current I, which is equal to the gate-source voltage of the first N-type transistor MN1 (Vgs) is proportional to the difference between the threshold voltage (Vth). Therefore, when the constant current I, the source voltage remains unchanged and the threshold voltage (Vth) decreases, the gate-source voltage (Vgs) of the first N-type transistor MN1 is Vref is lowered. Therefore, the substrate reference voltage Vref has a negative temperature coefficient, that is, the higher the temperature, the smaller the voltage of the substrate reference voltage Vref. In addition, the faster the first N-type transistor MN1 turns on, the smaller the threshold voltage Vth, that is, the smaller the voltage of the substrate reference voltage Vref.
  • the substrate reference voltage generating module 12 can automatically output the substrate reference voltage Vref with a negative temperature coefficient when the temperature changes.
  • a chip including the power circuit of any of the above embodiments.
  • the power supply circuit that provides the substrate voltage for the transistor can be switched according to the working mode of the chip through the switching circuit. For example, when the chip is operating normally, the power supply circuit that provides the substrate voltage for the transistor is controlled to be the power supply voltage.
  • VCC when the chip enters Deep Sleep Mode (DSM), switches the power circuit of any of the above embodiments to provide the substrate voltage VBN to the chip.
  • DSM Deep Sleep Mode
  • the temperature is, for example, the operating temperature (environmental temperature) of the chip.
  • the chip uses a fixed power supply voltage VCC as the substrate voltage of the N-type transistor during normal operation. Since the substrate voltage of the chip in normal operating mode is the power supply voltage VCC that does not change with temperature, leakage current will cause The power consumption is negligible compared to the power consumption of the chip.
  • the operation of the power supply circuit 100 of the embodiment of the present disclosure can be controlled through the switching circuit to switch the substrate voltage of the N-type transistor to a negative temperature coefficient
  • the substrate voltage VBN because VBN decreases as Vref decreases, and Vref is a negative temperature coefficient, the substrate voltage VBN will decrease with the ambient temperature or remain unchanged, thereby reducing the leakage current caused by the temperature rise, thereby reducing Power consumption of the chiplet in DSM mode.
  • the power supply circuit that provides the substrate voltage for the chip can be switched in various ways.
  • the DSM signal can be used to control the enable of the driver DR, or a control switch can be made between the oscillation module 21 and the charge pump module 22, or the DSM signal can be directly used to control the enable of the reference voltage generation circuit 1, on the substrate.
  • Embodiments of the present disclosure provide a substrate reference voltage with a negative temperature coefficient and an enable signal output module that outputs an enable signal according to the reduction of the substrate reference voltage.
  • the enable signal can be controlled.
  • the voltage output module automatically reduces the substrate voltage of the transistor and reduces the leakage current of the transistor, thereby reducing the power consumption of the integrated circuit.
  • the power circuit can automatically reduce the substrate voltage of the N-type transistor in the integrated circuit when the temperature rises, thereby reducing the leakage current of the N-type transistor and reducing the temperature of the integrated circuit. Overall power consumption.

Abstract

一种电源电路以及应用该电源电路的芯片。电源电路包括：参考电压产生电路（1），用于生成负温度系数的衬底参考电压（Vref）；电压生成电路（2），用于根据使能信号（EN）降低衬底电压（VBN）；使能信号（EN）生成电路（3），连接参考电压产生电路（1）和电压生成电路（2），用于在衬底参考电压（Vref）小于与衬底电压(VBP）成正比的转换电压时，向电压生成电路（2）输出使能信号（EN）。可以在温度升高时降低晶体管的衬底电压，降低芯片功耗。

Description

电源电路与芯片
交叉引用
本公开要求于2022年8月15日提交的申请号为202210981533.7、名称为“电源电路与芯片”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种电源电路以及应用该电源电路的芯片。
背景技术
随着科技发展，对集成电路的低功耗需求日益提升。相关技术通常对集成电路在信号传输过程中和信号处理过程中的功耗进行优化，但是在集成电路的待机或者休眠过程中，几乎没有信号传输和信号处理，因此集成电路的功耗存在进一步降低的可能。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种电源电路以及应用该电源电路的芯片，用于至少在一定程度上进一步降低集成电路的功耗。
根据本公开的第一方面，提供一种电源电路，包括：参考电压产生电路，用于生成负温度系数的衬底参考电压；电压生成电路，用于根据使能信号降低衬底电压；使能信号生成电路，连接所述参考电压产生电路和所述电压生成电路，用于在所述衬底参考电压小于与所述衬底电压成正比的转换电压时，向所述电压生成电路输出所述使能信号。
在本公开的一种示例性实施例中，所述电压生成电路包括：振荡模块，输入端用于接收所述使能信号，输出端用于输出振荡信号，所述振荡模块用于根据所述使能信号生成所述振荡信号；电荷泵模块，输入端连接所述振荡模块，输出端用于输出所述衬底电压，所述电荷泵模块用于根据所述振荡信号降低所述衬底电压。
在本公开的一种示例性实施例中，所述电荷泵模块包括：第一电容，所述第一电容的第一端耦接所述振荡模块的输出端；第一二极管，负极接地，正极连接所述第一电容的第二端；第二二极管，负极连接所第一电容的第二端，正极用于输出所述衬底电压。
在本公开的一种示例性实施例中，所述电荷泵模块还包括连接于所述振荡模块的输出端和所述第一电容的第一端之间的驱动电路，所述驱动电路用于增加所述振荡信号的振幅。
在本公开的一种示例性实施例中，所述电荷泵模块还包括第二电容，所述第二电容的 第一端连接所述第二二极管的正极，所述第二电容的第二端接地，所述第二电容用于维持所述电荷泵模块的输出电压。
在本公开的一种示例性实施例中，所述使能信号生成电路包括：电压跟随器，所述电压跟随器的同相输入端用于接收所述衬底参考电压，反相输入端与输出端相连；第一分压单元，两个输入端分别连接所述电压跟随器的输出端和电源电压，输出端用于输出基于所述衬底参考电压和所述电源电压生成的第一分压电压；第二分压单元，两个输入端分别连接所述电压生成电路的输出端和电源电压，输出端用于输出基于所述衬底电压和所述电源电压生成的第二分压电压；比较器，同相输入端连接所述第一分压单元的输出端，反相输入端连接第二分压单元的输出端；反相器，所述反相器的输入端连接所述比较器的输出端，所述反相器的输出端连接所述电压生成电路，用于输出所述使能信号。
在本公开的一种示例性实施例中，所述第一分压单元包括串联的第一分压电阻单元和第二分压电阻单元，所述第一分压电阻单元的第一端连接所述电源电压，所述第二分压电阻单元的第一端连接所述第一分压电阻单元的第二端，所述第二分压电阻单元的第二端连接所述电压跟随器的输出端；其中，所述第一分压电阻单元和所述第二分压电阻单元的阻值比为1：(K1-1)，K1为第一预设值。
在本公开的一种示例性实施例中，所述第二分压单元包括串联的第三分压电阻单元和第四分压电阻单元，所述第三分压电阻单元的第一端连接所述电源电压，所述第四分压电阻单元的第一端连接所述第三分压电阻单元的第二端，所述第四分压电阻单元的第二端连接所述电压生成电路的输出端；其中，所述第三分压电阻单元和所述第四分压电阻单元的阻值比为1：(K2-1)，K2为第二预设值。
在本公开的一种示例性实施例中，所述第二分压电阻单元和所述第四分压电阻单元的阻值可调。
在本公开的一种示例性实施例中，所述第二分压电阻单元和所述第四分压电阻单元均包括串联的多个电阻子单元，每个所述电阻子单元包括一或多个子电阻，每个所述电阻子单元并联一个电阻调节开关管，每个所述电阻调节开关管的控制端均接收控制信号。
在本公开的一种示例性实施例中，每个所述子电阻的阻值均相等。
在本公开的一种示例性实施例中，所述参考电压产生电路包括：恒定电流生成模块，用于生成正温度系数的第一电流和负温度系数的第二电流，并根据所述第一电流和所述第二电流生成恒定电流；衬底参考电压生成模块，包括晶体管，所述电压生产模块耦接所述恒定电流产生模块并用于根据所述恒定电流以及晶体管特性生成负温度系数的所述衬底参考电压。
在本公开的一种示例性实施例中，所述恒定电流生成模块包括：正温度系数电流生成单元，用于生成所述第一电流；负温度系数电流生成单元，连接所述正温度系数电流生成单元，用于生成所述第二电流。
在本公开的一种示例性实施例中，所述正温度系数电流生成单元包括：第一放大器； 第一反馈晶体管，所述第一反馈晶体管的源极连接电源电压，栅极连接所述第一放大器的输出端，漏极连接第一节点；第一桥臂，所述第一桥臂包括串联的第一电阻和多个并联的第一PN结单元，所述第一电阻的第一端连接所述第一节点，第二端连接所述第一放大器的反相输入端，所述第一PN结单元的正极连接所述第一放大器的反相输入端，负极接地；第二桥臂，所述第二桥臂包括串联的第二电阻、第三电阻和多个并联的第二PN结单元，所述第二电阻的第一端连接所述第一节点，第二端连接所述第一放大器的同相输入端；所述第三电阻的第一端连接所述第一放大器的同相输入端，第二端连接所述第二PN结单元的正极，所述第二PN结单元的负极接地；第一输出晶体管，源极连接所述电源电压，栅极连接所述第一放大器的输出端，漏极用于输出所述第一电流。
在本公开的一种示例性实施例中，所述第一电阻和所述第二电阻的阻值相等。
在本公开的一种示例性实施例中，所述第二PN结单元的数量为N个，N＝(M+2) 2-M 2，所述第一PN结单元的数量为M 2个，其中M为大于等于1的整数。
在本公开的一种示例性实施例中，所述负温度系数电流生成单元包括：第二放大器，所述第二放大器的反相输入端连接所述第一放大器的反相输入端；第二反馈晶体管，所述第二反馈晶体管的源极连接所述电源电压，栅极连接所述第二放大器的输出端，漏极连接所述第二放大器的同相输入端；第四电阻，一端连接所述第二放大器的同相输入端，另一端接地；第二输出晶体管，源极连接所述电源电压，栅极连接所述第二放大器的输出端，漏极用于输出所述第二电流。
在本公开的一种示例性实施例中，所述第三电阻和所述第四电阻均为可调电阻，所述第三电阻和所述第四电阻的阻值满足(kT/q)*lnZ/R3+(kT/q*lnZ+VBE2)/R4对温度T的导数为零，其中，R3是所述第三电阻的阻值，R4是所述第四电阻的阻值，K是玻尔兹曼常数，q是电子带电量，T是所述电源电路的工作温度，VBE2是所述第二PN结单元两端的电压差，Z是所述第二PN结单元与所述第一PN结单元的数量比。
在本公开的一种示例性实施例中，所述衬底参考电压生成模块包括：第一N型晶体管，所述第一N型晶体管的漏极和栅极连接于第二节点，所述第二节点连接所述第一输出晶体管的漏极和所述第二输出晶体管的漏极，所述第一N型晶体管的源极接地，所述第二节点用于输出所述衬底参考电压。
根据本公开的第二方面，提供一种芯片，包括如上任一项所述的电源电路。
本公开实施例通过提供负温度系数的衬底参考电压以及根据衬底参考电压的降低输出使能信号的使能信号输出模块，可以在温度升高、晶体管漏电流上升时，通过使能信号控制电压输出模块自动降低晶体管的衬底电压，降低晶体管漏电流，从而降低集成电路的功耗。当将该电源电路用于提供N型晶体管的衬底电压时，可以自动在温度升高时降低集成电路中的N型晶体管的衬底电压，从而降低N型晶体管的漏电流、降低集成电路的整体功耗。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限 制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中电源电路100的示意图。
图2是本公开一个实施例中电压生成电路2的示意图。
图3是本公开另一个实施例中电压生成电路2的示意图。
图4是本公开一个实施例中使能信号生成电路3的示意图。
图5A和图5B分别是本公开实施例中可调电阻单元的示意图。
图6是本公开一个实施例中参考电压产生电路1的示意图。
图7是本公开一个实施例中恒定电流生成模块11的示意图。
图8是本公开一个实施例中衬底参考电压生成模块12的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中电源电路的示意图。
参考图1，电源电路100可以包括：
参考电压产生电路1，用于生成负温度系数的衬底参考电压Vref；
电压生成电路2，用于根据使能信号降低衬底电压VBN；
使能信号生成电路3，连接参考电压产生电路1和电压生成电路2，用于在衬底参考电压Vref小于与衬底电压VBN成正比的转换电压时，向电压生成电路2输出使能信号EN。
本公开实施例通过提供正温度系数的衬底参考电压，可以在温度升高、晶体管漏电流上升时，自动降低晶体管的衬底电压，降低晶体管漏电流，从而降低集成电路的功耗。当将该电源电路100用于提供N型晶体管的衬底电压时，可以自动在温度升高时降低集成电路中的N型晶体管的衬底电压，从而降低N型晶体管的漏电流、降低集成电路的整体功耗。
图2是本公开一个实施例中电压生成电路的示意图。
参考图2，在一个实施例中，电压生成电路2可以包括：
振荡模块21，输入端用于接收使能信号EN，输出端用于输出振荡信号OSC，振荡模块21用于根据使能信号EN生成振荡信号OSC；
电荷泵模块22，输入端连接振荡模块21，输出端用于输出衬底电压VBN，电荷泵模块22用于根据振荡信号OSC降低衬底电压VBN。
其中，振荡模块21可以通过受控的环形振荡器实现，环形振荡器可以包括奇数个输入输出环形串联的具有信号反相功能的元件，例如反相器或者与非门。振荡模块21在接收到使能信号EN时输出振荡信号OSC，在未接收到使能信号EN时可以停止输出振荡信号OSC。
电荷泵模块22在未接收到振荡信号OSC时，可以输出晶体管正常工作时所需的衬底电压，例如接地电压(0V)。在接收到振荡信号OSC时，可以启动电荷泵功能，降低输出电压，即降低衬底电压VBN。
在图2所示实施例中，电荷泵模块22包括：
第一电容C1，第一电容C1的第一端耦接振荡模块21的输出端；
第一二极管D1，负极接地，正极连接第一电容C1的第二端；
第二二极管D2，负极连接第一电容C1的第二端，正极用于输出衬底电压VBN。
电荷泵模块22能够根据振荡信号OSC从接地端抽取负电荷至第二二极管D2的正极，拉低第二二极管D2正极的电压，从而生成衬底电压VBN。
当振荡模块21停止输出振荡信号OSC时，电荷泵模块22的输出端电压即第二二极管D2正极的电压不再下降。
图3是本公开另一个实施例中电压生成电路的示意图。
参考图3，在另一个实施例中，为了调节电荷泵模块22的输出电压降低幅度，电荷泵模块22还包括连接于振荡模块21的输出端和第一电容C1的第一端之间的驱动电路DR，驱动电路DR可以用于增加振荡信号OSC的振幅。
此外，电荷泵模块22还可以包括第二电容C2，第二电容C2的第一端连接第二二极管D2的正极，第二电容C2的第二端接地，第二电容C2用于维持电荷泵模块22的输出 电压。第二电压C2可以作为滤波电压进一步平滑电荷泵模块22的输出电压，维持第二二极管D2的负极电压在振荡信号OSC输出过程中为接近平稳的直流电压。
图4是本公开一个实施例中使能信号生成电路的示意图。
参考图4，在一个实施例中，使能信号生成电路3可以包括：
电压跟随器30，电压跟随器30的同相输入端用于接收衬底参考电压Vref，反相输入端与输出端相连；
第一分压单元31，两个输入端分别连接电压跟随器30的输出端和电源电压VCC，输出端用于输出基于衬底参考电压Vref和电源电压VCC生成的第一分压电压V1；
第二分压单元32，两个输入端分别连接电压生成电路2的输出端和电源电压VCC，输出端用于输出基于衬底电压VBN和电源电压VCC生成的第二分压电压V2；
比较器COMP，同相输入端连接第一分压单元31的输出端，反相输入端连接第二分压单元32的输出端；
反相器OP，反相器OP的输入端连接比较器COMP的输出端，反相器OP的输出端连接电压生成电路2，用于输出使能信号EN。
其中，电压跟随器30用于弥补负温度系数的衬底参考电压Vref的弱电流驱动能力。
在图4所示实施例中，第一分压单元31包括串联的第一分压电阻单元RZ1和第二分压电阻单元RZ2，第一分压电阻单元RZ1的第一端连接电源电压VCC，第二分压电阻单元RZ2的第一端连接第一分压电阻单元RZ1的第二端，第二分压电阻单元RZ2的第二端连接电压跟随器30的输出端；其中，第一分压电阻单元RZ1和第二分压电阻单元RZ2的阻值比为1：(K1-1)，K1为第一预设值。
第二分压单元32包括串联的第三分压电阻单元RZ3和第四分压电阻单元RZ4，第三分压电阻单元RZ3的第一端连接电源电压VCC，第四分压电阻单元RZ4的第一端连接第三分压电阻单元RZ3的第二端，第四分压电阻单元RZ4的第二端连接电压生成电路2的输出端；其中，第三分压电阻单元RZ3和第四分压电阻单元RZ4的阻值比为1：(K2-1)，K2为第二预设值。
设第一分压电阻单元RZ1和第三分压电阻单元RZ3的阻值均为R，则第二分压电阻单元RZ2的阻值为(K1-1)R，第四分压电阻单元RZ4的阻值为(K2-1)R。
通过分析可得，比较器COMP的同相输入端的电压等于VCC-(VCC-Vref)/K1，比较器COMP的反相输入端的电压等于VCC-(VCC-VBN)/K2。当比较器COMP的同相输入端的电压大于反相输入端的电压，即Vref＞K1*VBN/K2-(K1-K2)VCC/K2时，比较器COMP输出高电平，反相器OP输出低电平，即使能信号EN为低电平。当设置使能信号EN为高电平有效时，电压生成电路2不降低衬底电压VBN。
当衬底参考电压Vref逐渐降低小于K1*VBN/K2-(K1-K2)VCC/K2时，比较器COMP翻转输出低电平，反相器OP输出高电平，使能信号EN为高电平，电压生成电路2开始降低衬底电压VBN。
因此，当负温度系数的衬底参考电压Vref应用在对P型晶体管的衬底电压控制时，当温度升高，晶体管漏电流升高时，衬底参考电压Vref下降。当衬底参考电压Vref下降到小于K1*VBN/K2-(K1-K2)VCC/K2时，使能信号生成电路3输出有效的使能信号EN，控制电压生成电路2开始降低衬底电压VBN，进而自动降低晶体管漏电流。
在一个实施例中，第二分压电阻单元RZ2和第四分压电阻单元RZ4的阻值可调。
第二分压电阻单元RZ2和第四分压电阻单元RZ4可以通过图5A和图5B所示的可调电阻单元实现。
图5A和图5B是本公开实施例中可调电阻单元的示意图。
可调电阻单元可以包括串联的多个电阻子单元，每个电阻子单元包括一或多个子电阻，每个电阻子单元并联一个电阻调节开关管，每个电阻调节开关管的控制端均用于接收控制信号。可以设置每个子电阻的阻值均相等。此时，可调电阻单元可以通过图5A所示的电阻串501来实现。
参考图5A，电阻串501包括多个串联的子电阻R01、R02、R03、R04、R05、R06，以及连接子电阻第一端或第二端的可控的电阻调节开关管Con1、Con2、Con3。电阻调节开关管Con1的第一端和第二端分别连接子电阻R01的两端；电阻调节开关管Con2的第一端和第二端分别连接子电阻R01的第二端/子电阻R02的第一端和子电阻R03的第二端/子电阻R04的第一端；电阻调节开关管Con3的第一端和第二端分别连接子电阻R03的第二端/子电阻R04的第一端和子电阻R06的第二端。从而，子电阻R01构成一个电阻子单元，子电路R02和R03构成一个电阻子单元，子电阻R04、R05、R06构成一个电阻子单元。
电阻调节开关管Con1、Con2、Con3的控制端均接收控制信号。该控制信号例如来自处理器或者一次性可编程控制器，本公开对此不作特殊限定。
在图5A所示实施例中，电阻调节开关管通过N型晶体管实现，N型晶体管的栅极作为控制端。在本公开的其他实施例中，电阻调节开关管也可以由其他元件实现，本公开对此不作特殊限制。
设子电阻R01、R02、R03、R04、R05、R06的阻值均为R0，则电阻串501的阻值与电阻调节开关管Con1、Con2、Con3的开启状态如表1所示：
Con1 Con2 Con3 电阻串501的阻值
关闭 关闭 关闭 6R0
开启 关闭 关闭 5R0
开启 开启 关闭 3R0
开启 关闭 开启 2R0
关闭 开启 开启 R0
关闭 开启 关闭 4R0
关闭 关闭 开启 3R0
表1
上述阻值表根据电阻调节开关管Con1、Con2、Con3跨接的电阻数量不同而不同，本领域技术人员可以根据图5A所示原理调节子电阻的数量、阻值、开关元件的数量、开关元件与子电阻的连接关系，从而实现多种阻值设置。
此外，还可以通过另一种电阻串以实现可调电阻单元。
参考图5B，电阻串502包括多个串联的子电阻R01、R02、R03、R04，子电阻R01的第一端作为电阻串502的第一端，子电阻R02、R03、R04的第一端分别连接子电阻R01、R02、R03的第二端，子电阻R01、R02、R03的第二端分别连接电阻调节开关管Con1、Con2、Con3的第二端。
电阻调节开关管Con1的第一端和第二端分别连接子电阻R01的两端；电阻调节开关管Con2的第一端和第二端分别连接电阻串502的第一端和子电阻R02的第二端；电阻调节开关管Con3的第一端和第二端分别连接电阻串502的第一端和子电阻R03的第二端。
设子电阻R01、R02、R03、R04的阻值均为R，则电阻串502的阻值与电阻调节开关管Con1、Con2、Con3的开启状态如表2所示：
Con1 Con2 Con3 电阻串502的阻值
关闭 关闭 关闭 4R
开启 关闭 关闭 3R
关闭 开启 关闭 2R
关闭 关闭 开启 R
表2
由表2可知，在图5B所示实施例中最多控制一个开关元件开启，以调节电阻串502的阻值。虽然在图5B所示实施例中，两个电阻调节开关管的第二端之间仅间隔一个子电阻，但是在本公开的其他实施例中，两个电阻调节开关管的第二端之间还可以间隔不同数量的子电阻，或者间隔不同阻值的子电阻，或者不同数量、不同阻值的子电阻。需要注意的是，两端跨接最多数量的子电阻的电阻调节开关管，其第二端需要连接一个子电阻，以防止电阻串502的阻值为0。
图6是本公开一个实施例中参考电压产生电路的示意图。
参考图6，在一个实施例中，参考电压产生电路1包括：
恒定电流生成模块11，用于生成正温度系数的第一电流I1和负温度系数的第二电流I2，并根据第一电流I1和第二电流I2生成恒定电流I；
衬底参考电压生成模块12，包括晶体管，衬底参考电压生成模块12耦接恒定电流产生模块11并用于根据恒定电流I以及晶体管特性生成正温度系数的衬底参考电压Vref。
图6所示实施例中生成的衬底参考电压Vref与晶体管的温度特性相关。
晶体管的阈值电压与温度相关，N型晶体管的阈值电压随温度升高而降低，P型晶体管的阈值电压的绝对值随温度升高而降低，由于P型晶体管的阈值电压为负值，因此P 型晶体管的阈值电压随温度升高而降低。因此，在衬底参考电压生成模块12，对晶体管输入恒定电流I时，晶体管的阈值电压Vth随温度变化，则最终通过该晶体管输出的电压与电流无关，仅与温度相关。
图7是本公开一个实施例中恒定电流生成模块11的示意图。
参考图7，在一个实施例中，恒定电流生成模块11可以包括：
正温度系数电流生成单元111，用于生成第一电流I1；
负温度系数电流生成单元112，连接正温度系数电流生成单元111，用于生成第二电流I2。
第一电流I1和第二电流I2共同形成恒定电流I。
衬底参考电压生成模块12用于根据恒定电流I以输出正温度系数的衬底参考电压Vref。正温度系数的衬底参考电压Vref例如为根据P型晶体管的温度特性输出的电压。
在图7所示实施例中，正温度系数电流生成单元11可以包括：
第一放大器AMP1；
第一反馈晶体管MB1，第一反馈晶体管MB1的源极连接电源电压VCC，栅极连接第一放大器AMP1的输出端，漏极连接第一节点N1；
第一桥臂B1，第一桥臂B1包括串联的第一电阻R1和多个并联的第一PN结单元J1，第一电阻R1的第一端连接第一节点N1，第二端连接第一放大器AMP1的反相输入端和第一PN结单元J1的正极，第一PN结单元J1的负极接地；
第二桥臂B2，第二桥臂B2包括串联的第二电阻R2、第三电阻R3和第二PN结单元J2，第二电阻R2的第一端连接第一节点N1，第二端连接第一放大器AMP1的同相输入端；第三电阻R3的第一端连接第一放大器AMP1的同相输入端，第二端连接第二PN结单元J2的正极，第二PN结单元J2的负极接地；
第一输出晶体管MO1，源极连接电源电压VCC，栅极连接第一放大器AMP1的输出端，漏极用于输出第一电流I1。
其中，第一反馈晶体管MB1和第一输出晶体管MO1均可以为P型晶体管。
第二PN结单元J2的数量可以为多个。多个第二PN结单元J2并联，每个第二PN结单元的正极均连接第三电阻R3的第二端，负极均接地。在一个实施例中，第二PN结单元的数量可以为N＝(M+2) 2-M 2个，第一PN结单元的数量为M 2个，其中M为大于等于1的整数。这样设置可以在制造时使第二PN结单元J2环绕第一PN结单元J1，形成(M+2)*(M+2)的PN结单元阵列。
例如，当M＝1时，N＝3，第一PN结单元J1的数量为1个，第二PN结单元J2的数量为3*3-1＝8个，第一PN结单元J1和第二PN结单元J2排列成3*3阵列。
当M＝2时，N＝4，第一PN结单元J1的数量为4个，第二PN结单元J2的数量为4*4-4＝12个，第一PN结单元J1和第二PN结单元J2排列成4*4阵列。
当M＝3时，N＝5，第一PN结单元J1的数量为9个，第二PN结单元J2的数量为 5*5-9＝16个，第一PN结单元J1和第二PN结单元J2排列成5*5阵列。以此类推。
在图7所示实施例中，为了简化分析，设M＝1，N＝3，第一PN结单元J1的数量为1个，第二PN结单元J2的数量为8个。
在图7所示实施例中，第一电阻R1和第二电阻R2相同。由于放大器的虚短特性，第一节点N1和第一放大器AMP1的反相输入端之间的电压差与第一节点N1和第一放大器AMP1的同相输入端之间的电压差相等，且第一节点N1和第一放大器AMP1的反相输入端之间的第一电阻R1和第一节点N1和第一放大器AMP1的同相输入端之间的第二电阻R2相等，则第一桥臂B1和第二桥臂B2上的电流相同。
继续推论，第一节点N1和第一放大器AMP1的反相输入端之间的电压差与第一节点N1和第一放大器AMP1的同相输入端之间的电压差相等，且第一节点N1和第一放大器AMP1的反相输入端之间的电压差等于第一PN结单元J1的PN结电压V BE1，则第三电阻R1的第一端的电压为V BE1。设第三电阻R3的第二端即第二PN结单元J2的正极电压为V BE2，根据PN结V-I特性表达式有：
Figure PCTCN2022126376-appb-000001
其中，I D是PN结单元的电流，I S是PN结单元的反向饱和电流(与温度相关，在温度确定时为常量)，V T是热电压，有V T＝kT/q，K是玻尔兹曼常数，q是电子电荷，有k＝1.38×10 -23J/K(焦耳/开尔文)，q＝1.6×10 -19C(库伦)；T是绝对温度，单位是开尔文。V T也称温度的电压当量，是指闭合电路中由于两点间存在温差而出现的电位差。当T＝300K(常温)时，V T＝kT/q≈0.026V。n是发射系数，与PN结的尺寸、材料以及通过的电流有关，在1～2之间。
由于第一桥臂B1和第二桥臂B2上的电流相等，并联的8个第二PN结单元J2上的电流与第一PN结单元J1上的电流相等，设每个第二PN结单元J2上的电流为I 0，则第一PN结单元J1上的电流为8I 0。
当第一PN结单元J1和第二PN结单元J2的数量为其他值时，设每个第二PN结单元J2的电流为I 0，则第一PN结单元J1上的电流为ZI 0。Z为第二PN结单元J2和第一PN结单元J1的数量比。
当V BE远大于V T时，公式(1)的括号中的1可以忽略，设n＝1，从而有：
Figure PCTCN2022126376-appb-000002
从而，
Figure PCTCN2022126376-appb-000003
同理，得到V BE2的公式：
Figure PCTCN2022126376-appb-000004
根据同样的假设和推导，得到：
Figure PCTCN2022126376-appb-000005
因此，第三电阻R3上的电压V BE1-V BE2有：
Figure PCTCN2022126376-appb-000006
从而，第二桥臂B2上的电流I112有：
Figure PCTCN2022126376-appb-000007
其中，R3是第三电阻R3的阻值。由于在N确定的情况下，V BE1-V BE2与V T成正比，V T与温度T成正比，因此，第二桥臂B2上的电流I112与温度T成正比，为正温度系数电流。
在上述公式中，当第一PN结单元J1和第二PN结单元J2的数量为其他值时，公式(2)～(7)中的数字8可以替换为第二PN结单元J2和第一PN结单元J1的数量比Z。
由于第一桥臂B1和第二桥臂B2上的电流相同，第一反馈晶体管MB1的电流等于二倍的第二桥臂B2上的电流，为2V TlnN/R3。
第一反馈晶体管MB1和第一输出晶体管MO1构成电流镜。在一个实施例中，第一反馈晶体管MB1和第一输出晶体管MO1的沟道宽长比的比值是2：1，因此，第一输出晶体管MO1漏极输出的第一电流I1等于二分之一的第一反馈晶体管MB1上的电流，等于第二桥臂B2上的电流I112。
可见，第一输出晶体管MO1漏极输出的电流I1与第三电阻R3的阻值负相关，因此，可以设置第三电阻R3为可调电阻，以调节第一电流I1的值。
在图7所示实施例中，第一PN结单元J1和第二PN结单元J2通过自偏置晶体管实现，自偏置晶体管为N型晶体管，自偏置晶体管的栅极和源极均接地。在本公开的其他实施例中，第一PN结单元J1和第二PN结单元J2的实现方式还可以有多种，也可以直接通过二极管实现，本公开对此不作特殊限制。
继续参考图7所示实施例，负温度系数电流生成单元12可以包括：
第二放大器AMP2，第二放大器AMP2的反相输入端连接第一放大器AMP1的反相输入端；
第二反馈晶体管MB2，第二反馈晶体管MB2的源极连接电源电压VCC，栅极连接第二放大器AMP2的输出端，漏极连接第二放大器AMP2的同相输入端；
第四电阻R4，一端连接第二放大器AMP2的同相输入端，另一端接地；
第二输出晶体管MO2，源极连接电源电压VCC，栅极连接第二放大器AMP2的输出端，漏极用于输出第二电流I2。
由分析可知，第二输出晶体管MO2与第二反馈晶体管MB2构成电流镜。第二放大器AMP2的同相输入端和反相输入端电压相等，第四电阻R4上的电压等于第一PN结单元J1的结电压V BE1，则第二反馈晶体管MB2上的电流等于V BE1/R4，设第二反馈晶体管 MB2和第二输出晶体管MO2的沟道宽长比的比值是1：1，第二输出晶体管MO2的漏极输出的第二电流I2有：
I2＝V BE1/R4         (8)
根据公式(6)得到：
V BE1＝V BE2+V T ln 8         (9)
从而，有：
Figure PCTCN2022126376-appb-000008
PN结在有电流流经时产生的压降和正向电流以及温度有关，电流越大、压降越大，温度越高、压降越小。即PN结具有负温度系数电压。因此，V BE2是负温度系数电压，则I2是负温度系数电流。
且最终输出的恒定电流I＝I1+I2，则得到恒定电流I的公式为：
Figure PCTCN2022126376-appb-000009
其中，I1是正温度系数电流，I2是负温度系数电流，V T和V BE2均是与温度T相关的值，调整第三电阻R3和第四电阻R4的阻值，当公式(11)对温度T的导数为零时，恒定电流I为零温度系数电流。
在本公开的一种示例性实施例中，第三电阻R3和第四电阻R4均为可调电阻，均可以通过图5A或图5B所示实施例实现，于此不再赘述。
图8是本公开一个实施例中衬底参考电压生成模块的示意图。
参考图8，在一个实施例中，衬底参考电压生成模块12可以包括：
第一N型晶体管MN1，第一N型晶体管MN1的漏极和栅极连接于第二节点N2，第二节点N2连接第一输出晶体管MO1的漏极和第二输出晶体管MO2的漏极，第一N型晶体管MN1的源极接地，第二节点N2用于输出负温度系数的衬底参考电压Vref。
在图8所示实施例中，由于负温度系数的衬底参考电压Vref。仅受恒定电流I和第一N型晶体管MN1的特性的影响，且恒定电流I与温度无关，因此负温度系数的衬底参考电压Vref仅与第一N型晶体管MN1的特性相关。
根据前面描述，第一N型晶体管MN1的阈值电压(Vth)随温度升高而降低，而流经第一N型晶体管MN1的电流为恒定电流I，与第一N型晶体管MN1的栅源电压(Vgs)和阈值电压(Vth)之差成比例关系，因此，在恒定电流I、源极电压不变且阈值电压(Vth)降低时，第一N型晶体管MN1的栅源电压(Vgs)即Vref降低。因此，衬底参考电压Vref为负温度系数的电压，即温度越高，衬底参考电压Vref的电压越小。此外，第一N型晶体管MN1开启速度越快，阈值电压Vth越小，即衬底参考电压Vref的电压越小。
因此衬底参考电压生成模块12可以在温度发生变化时自动输出负温度系数的衬底参考电压Vref。
根据本公开第二方面，提供一种芯片，包括如上任一实施例的电源电路。
在本公开的一个实施例中，可以通过切换电路根据芯片的工作模式切换为晶体管提供衬底电压的电源电路，例如，在芯片正常工作时，控制为晶体管提供衬底电压的电源电路为电源电压VCC，在芯片进入深度睡眠模式(Deep Sleep Mode，DSM)时，切换上述任意实施例的电源电路为芯片提供衬底电压VBN。
在本公开实施例中，温度例如为芯片的工作温度(环境温度)。假设在高温环境下，芯片正常工作时使用固定的电源电压VCC作为N型晶体管的衬底电压，由于正常工作模式时芯片的衬底电压是不随温度变化的电源电压VCC，因为此时漏电流造成的功耗相对于芯片的功耗可以忽略不计。在芯片进入DSM模式时，漏电流造成的功耗占比更大，所以此时可以通过切换电路控制本公开实施例的电源电路100工作，将N型晶体管的衬底电压切换为负温度系数的衬底电压VBN(因为VBN随Vref下降而下降，Vref为负温度系数)，则衬底电压VBN会随环境温度下降或者维持不变，进而能够减小因温度上升而产生的漏电流，从而减小芯片在DSM模式下的功耗。
在本公开实施例中，可以通过多种方式切换为芯片提供衬底电压的电源电路。例如，可以通过是DSM信号控制驱动器DR的使能，或者，在振荡模块21和电荷泵模块22之间做一个控制开关，或者直接用DSM信号控制参考电压产生电路1的使能，在衬底端做一个用于选择衬底电压来源的选择电路等等。实现衬底电压切换的方式可以有多种，本公开对此不作特殊限制。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过提供负温度系数的衬底参考电压以及根据衬底参考电压的降低输出使能信号的使能信号输出模块，可以在温度升高、晶体管漏电流上升时，通过使能信号控制电压输出模块自动降低晶体管的衬底电压，降低晶体管漏电流，从而降低集成电路的功耗。当将该电源电路用于提供N型晶体管的衬底电压时，可以自动在温度升高时降低集成电路中的N型晶体管的衬底电压，从而降低N型晶体管的漏电流、降低集成电路的整体功耗。

Claims (20)

  1. 一种电源电路，包括：
    参考电压产生电路，用于生成负温度系数的衬底参考电压；
    电压生成电路，用于根据使能信号降低衬底电压；
    使能信号生成电路，连接所述参考电压产生电路和所述电压生成电路，用于在所述衬底参考电压小于与所述衬底电压成正比的转换电压时，向所述电压生成电路输出所述使能信号。
  2. 如权利要求1所述的电源电路，其中，所述电压生成电路包括：
    振荡模块，输入端用于接收所述使能信号，输出端用于输出振荡信号，所述振荡模块用于根据所述使能信号生成所述振荡信号；
    电荷泵模块，输入端连接所述振荡模块，输出端用于输出所述衬底电压，所述电荷泵模块用于根据所述振荡信号降低所述衬底电压。
  3. 如权利要求1所述的电源电路，其中，所述电荷泵模块包括：
    第一电容，所述第一电容的第一端耦接所述振荡模块的输出端；
    第一二极管，负极接地，正极连接所述第一电容的第二端；
    第二二极管，负极连接所第一电容的第二端，正极用于输出所述衬底电压。
  4. 如权利要求3所述的电源电路，其中，所述电荷泵模块还包括连接于所述振荡模块的输出端和所述第一电容的第一端之间的驱动电路，所述驱动电路用于增加所述振荡信号的振幅。
  5. 如权利要求3所述的电源电路，其中，所述电荷泵模块还包括第二电容，所述第二电容的第一端连接所述第二二极管的正极，所述第二电容的第二端接地，所述第二电容用于维持所述电荷泵模块的输出电压。
  6. 如权利要求1所述的电源电路，其中，所述使能信号生成电路包括：
    电压跟随器，所述电压跟随器的同相输入端用于接收所述衬底参考电压，反相输入端与输出端相连；
    第一分压单元，两个输入端分别连接所述电压跟随器的输出端和电源电压，输出端用于输出基于所述衬底参考电压和所述电源电压生成的第一分压电压；
    第二分压单元，两个输入端分别连接所述电压生成电路的输出端和电源电压，输出端用于输出基于所述衬底电压和所述电源电压生成的第二分压电压；
    比较器，同相输入端连接所述第一分压单元的输出端，反相输入端连接第二分压单元的输出端；
    反相器，所述反相器的输入端连接所述比较器的输出端，所述反相器的输出端连接所述电压生成电路，用于输出所述使能信号。
  7. 如权利要求6所述的电源电路，其中，所述第一分压单元包括串联的第一分压电阻 单元和第二分压电阻单元，所述第一分压电阻单元的第一端连接所述电源电压，所述第二分压电阻单元的第一端连接所述第一分压电阻单元的第二端，所述第二分压电阻单元的第二端连接所述电压跟随器的输出端；其中，所述第一分压电阻单元和所述第二分压电阻单元的阻值比为1：(K1-1)，K1为第一预设值。
  8. 如权利要求7所述的电源电路，其中，所述第二分压单元包括串联的第三分压电阻单元和第四分压电阻单元，所述第三分压电阻单元的第一端连接所述电源电压，所述第四分压电阻单元的第一端连接所述第三分压电阻单元的第二端，所述第四分压电阻单元的第二端连接所述电压生成电路的输出端；其中，所述第三分压电阻单元和所述第四分压电阻单元的阻值比为1：(K2-1)，K2为第二预设值。
  9. 如权利要求8所述的电源电路，其中，所述第二分压电阻单元和所述第四分压电阻单元的阻值可调。
  10. 如权利要求9所述的电源电路，其中，所述第二分压电阻单元和所述第四分压电阻单元均包括串联的多个电阻子单元，每个所述电阻子单元包括一或多个子电阻，每个所述电阻子单元并联一个电阻调节开关管，每个所述电阻调节开关管的控制端均接收控制信号。
  11. 如权利要求10所述的电源电路，其中，每个所述子电阻的阻值均相等。
  12. 如权利要求1所述的电源电路，其中，所述参考电压产生电路包括：
    恒定电流生成模块，用于生成正温度系数的第一电流和负温度系数的第二电流，并根据所述第一电流和所述第二电流生成恒定电流；
    衬底参考电压生成模块，包括晶体管，所述电压生产模块耦接所述恒定电流产生模块并用于根据所述恒定电流以及晶体管特性生成负温度系数的所述衬底参考电压。
  13. 如权利要求12所述的电源电路，其中，所述恒定电流生成模块包括：
    正温度系数电流生成单元，用于生成所述第一电流；
    负温度系数电流生成单元，连接所述正温度系数电流生成单元，用于生成所述第二电流。
  14. 如权利要求13所述的电源电路，其中，所述正温度系数电流生成单元包括：
    第一放大器；
    第一反馈晶体管，所述第一反馈晶体管的源极连接电源电压，栅极连接所述第一放大器的输出端，漏极连接第一节点；
    第一桥臂，所述第一桥臂包括串联的第一电阻和多个并联的第一PN结单元，所述第一电阻的第一端连接所述第一节点，第二端连接所述第一放大器的反相输入端，所述第一PN结单元的正极连接所述第一放大器的反相输入端，负极接地；
    第二桥臂，所述第二桥臂包括串联的第二电阻、第三电阻和多个并联的第二PN结单元，所述第二电阻的第一端连接所述第一节点，第二端连接所述第一放大器的同相输入端；所述第三电阻的第一端连接所述第一放大器的同相输入端，第二端连接所述第二PN结单 元的正极，所述第二PN结单元的负极接地；
    第一输出晶体管，源极连接所述电源电压，栅极连接所述第一放大器的输出端，漏极用于输出所述第一电流。
  15. 如权利要求14所述的电源电路，其中，所述第一电阻和所述第二电阻的阻值相等。
  16. 如权利要求15所述的电源电路，其中，所述第二PN结单元的数量为N个，N＝(M+2) 2-M 2，所述第一PN结单元的数量为M 2个，其中M为大于等于1的整数。
  17. 如权利要求14所述的电源电路，其中，所述负温度系数电流生成单元包括：
    第二放大器，所述第二放大器的反相输入端连接所述第一放大器的反相输入端；
    第二反馈晶体管，所述第二反馈晶体管的源极连接所述电源电压，栅极连接所述第二放大器的输出端，漏极连接所述第二放大器的同相输入端；
    第四电阻，一端连接所述第二放大器的同相输入端，另一端接地；
    第二输出晶体管，源极连接所述电源电压，栅极连接所述第二放大器的输出端，漏极用于输出所述第二电流。
  18. 如权利要求17所述的电源电路，其中，所述第三电阻和所述第四电阻均为可调电阻，所述第三电阻和所述第四电阻的阻值满足(kT/q)*lnZ/R3+(kT/q*lnZ+VBE2)/R4对温度T的导数为零，其中，R3是所述第三电阻的阻值，R4是所述第四电阻的阻值，K是玻尔兹曼常数，q是电子带电量，T是所述电源电路的工作温度，VBE2是所述第二PN结单元两端的电压差，Z是所述第二PN结单元与所述第一PN结单元的数量比。
  19. 如权利要求12所述的电源电路，其中，所述衬底参考电压生成模块包括：
    第一N型晶体管，所述第一N型晶体管的漏极和栅极连接于第二节点，所述第二节点连接所述第一输出晶体管的漏极和所述第二输出晶体管的漏极，所述第一N型晶体管的源极接地，所述第二节点用于输出所述衬底参考电压。
  20. 一种芯片，包括如权利要求1～19任一项所述的电源电路。
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