WO2024032108A1 - 半导体结构、半导体结构的制备方法和半导体存储器 - Google Patents

半导体结构、半导体结构的制备方法和半导体存储器 Download PDF

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WO2024032108A1
WO2024032108A1 PCT/CN2023/097849 CN2023097849W WO2024032108A1 WO 2024032108 A1 WO2024032108 A1 WO 2024032108A1 CN 2023097849 W CN2023097849 W CN 2023097849W WO 2024032108 A1 WO2024032108 A1 WO 2024032108A1
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metal layer
doped region
insulating isolation
semiconductor structure
channel
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PCT/CN2023/097849
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English (en)
French (fr)
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唐怡
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长鑫存储技术有限公司
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Publication of WO2024032108A1 publication Critical patent/WO2024032108A1/zh

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    • H01L29/78—
    • H01L29/401—
    • H01L29/42356—
    • H01L29/42372—
    • H01L29/66477—

Definitions

  • the present disclosure relates to the field of memory technology, and in particular, to a semiconductor structure, a preparation method of the semiconductor structure, and a semiconductor memory.
  • GDL Gate Induced Drain Leakage
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Embodiments of the present disclosure provide a semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor memory:
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • Drain doped regions and source doped regions formed on both sides of the channel doped region
  • the insulating isolation layer includes a first insulating isolation part and a second insulating isolation part.
  • the first insulating isolation part is formed on the surface of the channel doped region, and the second insulating isolation part is formed on the drain doped region. Part of the surface of the complex area;
  • a second metal layer is formed on the surface of the second insulating isolation part.
  • the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold.
  • the preset work function threshold is 4.6 electron volts.
  • the material of the first metal layer includes at least one of the following: iridium, nickel, platinum, cobalt.
  • the semiconductor structure further includes a third metal layer, and the material of the third metal layer is the same as the material of the second metal layer; wherein,
  • the third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer.
  • the channel doping region, the drain doping region and the source doping region have the same doping ion type.
  • the channel doped region is a lightly doped region
  • the drain doped region and the source doped region are both heavily doped regions
  • the doping ion concentration of the heavily doped region is greater than the doping ion concentration of the lightly doped region.
  • the drain doped region includes a first sub-doped region and a second sub-doped region, and the first sub-doped region is located between the channel doped region and the second sub-doped region. between the sub-doped regions; wherein the second insulating isolation portion is formed on the surface of the first sub-doped region.
  • the insulating isolation layer further includes a third insulating isolation portion, the third insulating isolation portion is formed on part of the surface of the source doped region;
  • the semiconductor structure further includes a fourth metal layer formed on a surface of the third insulating isolation portion.
  • the source doping region includes a third sub-doping region and a fourth sub-doping region, and the third sub-doping region is located between the channel doping region and the fourth sub-doping region. Between the sub-doped regions, the third insulating isolation part is formed on the surface of the third sub-doped region; wherein,
  • the channel doped region is a lightly doped region
  • the first sub-doped region and the third sub-doped region are both medium doped regions
  • the second sub-doped region and the fourth sub-doped region are both heavily doped regions
  • the doping ion concentration of the medium doping region is greater than the doping ion concentration of the lightly doped region, and the doping ion concentration of the medium doping region is less than the doping ion concentration of the heavily doped region.
  • the semiconductor structure further includes a fifth metal layer; wherein,
  • the fifth metal layer is formed on the surface of the first metal layer, and both ends of the fifth metal layer are connected to the second metal layer and the fourth metal layer respectively.
  • the semiconductor structure further includes a bit line and a capacitor; wherein,
  • the bit line is connected to a side of the source doped region away from the channel doped region;
  • the capacitor is connected to a side of the drain doped region away from the channel doped region.
  • the semiconductor structure further includes control leads; wherein,
  • the first metal layer and the second metal layer are connected;
  • One end of the control lead is connected to the first metal layer and/or the second metal layer, and the other end of the control lead is connected to the control terminal.
  • the semiconductor structure further includes a metal isolation layer, a first control lead and a second control lead; wherein,
  • the metal isolation layer is formed between the first metal layer and the second metal layer to insulate and isolate the first metal layer and the second metal layer;
  • One end of the first control lead is connected to the first metal layer, and the other end of the first control lead is One end is connected to the first control end;
  • One end of the second control lead is connected to the second metal layer, and the other end of the second control lead is connected to the second control terminal.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including:
  • the substrate is doped to form a channel doping region, a drain doping region and a source doping region in the substrate, and the drain doping region and the source doping region formed on both sides of the channel doped region;
  • An insulating isolation layer is formed, the insulating isolation layer includes a first insulating isolation part and a second insulating isolation part, the first insulating isolation part is formed on the surface of the channel doping region, and the second insulating isolation part is formed On part of the surface of the drain doped region;
  • a second metal layer is formed on the surface of the second insulating isolation part.
  • forming a first metal layer on the surface of the first insulating isolation part includes:
  • the method when forming the second metal layer on the surface of the second insulating isolation part, the method further includes:
  • a third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer; wherein the material of the third metal layer and the material of the second metal layer same.
  • the method further includes:
  • bit line is connected to a side of the drain doped region away from the channel doped region; the capacitor is connected to a side of the source doped region away from the channel One side of the channel doped region is connected.
  • the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than a preset work function threshold; wherein, the preset Let the work function threshold be 4.6 electron volts.
  • embodiments of the present disclosure provide a semiconductor memory, including the semiconductor structure according to any one of the first aspects.
  • Figure 1 is a schematic diagram of the composition and structure of a junctionless transistor
  • Figure 2 is a schematic diagram of the composition and structure of an accumulation mode junctionless transistor
  • Figure 3 is a schematic diagram of the relationship between channel length and electric field strength
  • Figure 4 is a schematic diagram of an energy band profile
  • Figure 5 is a schematic structural diagram 1 of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic three-dimensional structural diagram of a transistor provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram 2 of the composition of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram 3 of the composition of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram 4 of the composition of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram 5 of the composition of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram 6 of the composition of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram comparing the relationship between channel length and electric field intensity provided by an embodiment of the present disclosure
  • Figure 13 is a schematic diagram of an energy band profile comparison provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a control lead connection for independent control of a metal layer provided by an embodiment of the present disclosure
  • Figure 15 is a schematic diagram of a control lead connection for joint control of metal layers provided by an embodiment of the present disclosure
  • Figure 16 is a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a channel doped region, a drain doped region and a source doped region obtained according to an embodiment of the present disclosure
  • Figure 18 is a schematic structural diagram obtained after forming an insulating isolation layer according to an embodiment of the present disclosure.
  • Figure 19 is a schematic structural diagram obtained after forming a mask layer according to an embodiment of the present disclosure.
  • Figure 20 is a schematic structural diagram obtained after forming the first metal layer according to an embodiment of the present disclosure.
  • Figure 21 is a schematic structural diagram obtained after removing the mask layer according to an embodiment of the present disclosure.
  • Figure 22 is a schematic structural diagram obtained after forming a second metal layer according to an embodiment of the present disclosure.
  • Figure 23 is a schematic structural diagram obtained after forming a third metal layer according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first ⁇ second ⁇ third” Where permitted, the specific order or sequence may be interchanged so that the disclosed embodiments described herein can be practiced in other sequences than illustrated or described herein.
  • junctionless transistors Compared with junction transistors, junctionless transistors eliminate the steep concentration gradient distribution between the channel (Channel) and the source (Source, S)/drain (Drain, D) in the transistor, reducing the thermal budget. , simplifying the manufacturing process and also eliminating the influence of short channel effect.
  • Junctionless transistors can be mainly divided into junction less transistors (JLT) and accumulation mode junction less transistors (Accumulation Mode Junction Less Transistor, JLAMT).
  • Figure 1 is a schematic diagram of the composition and structure of a junctionless transistor JLT. As shown in Figure 1, for JLT In other words, it may include a channel 101, a drain electrode 102 and a source electrode 103 located on both sides of the channel, a gate dielectric layer 104 formed on the surface of the channel 101, and a gate electrode 105 formed on the surface of the gate dielectric layer 104, where D represents a device connected to the drain electrode 102, and S represents a device connected to the source electrode 103.
  • the doping types of the channel 101, the drain 102 and the source 103 are all N type medium dopant (N type medium dopant, represented by N), for example, N type medium dopant
  • N N type medium dopant
  • the ion concentration is: e 19 per cubic centimeter (e 19 /cm 3 ).
  • the transistor has a better off state, but the on current of the transistor is low.
  • FIG 2 is a schematic diagram of the composition and structure of an accumulation mode junctionless transistor JLAMT.
  • a JLAMT may include a channel 201, a drain electrode 202 and a source electrode 203 located on both sides of the channel, a gate dielectric layer 204 formed on the surface of the channel 201, and a gate dielectric layer 204 formed on the surface of the channel 201.
  • the doping type of channel 201 is N-type light dopant (N-type light dopant, represented by N-).
  • the ion concentration of N-type light dopant is: e 18 / cm 3
  • the doping types of the drain 202 and the source 203 are both N-type heavy dopant (N type heave dopant, represented by N+).
  • the ion concentration of N-type heavy dopant is: e 20 /cm 3 .
  • Figure 3 is a schematic diagram of the relationship between channel length and electric field intensity
  • Figure 4 is a schematic diagram of the energy band profile.
  • Figure 3 and Figure 4 both correspond to the JLAMT shown in Figure 2.
  • the horizontal axis is the channel length (unit: nanometer (nm))
  • the vertical axis is the electric field intensity (unit: millivolts per centimeter (mV/cm)).
  • the electric field intensity is relatively strong. , resulting in large leakage current of the transistor.
  • eV electron volt
  • embodiments of the present disclosure provide a semiconductor structure, including: a channel doping region; a drain doping region and a source doping region formed on both sides of the channel doping region; and an insulating isolation layer, including a third An insulating isolation part and a second insulating isolation part, the first insulating isolation part is formed on the surface of the channel doping region, the second insulating isolation part is formed on part of the surface of the drain doping region; the first metal layer is formed on the surface of the drain doping region.
  • the second metal layer can reduce the concentration gradient of the impurity distribution from the drain doped region to the channel doped region, reducing the drain doping.
  • the number of carriers near the region is effectively reduced, thereby effectively reducing the electric field intensity in the channel doped region and suppressing the gate-induced drain leakage current (GIDL) caused by the band-to-band tunneling effect (BTBT).
  • GIDL gate-induced drain leakage current
  • FIG. 5 shows a schematic structural diagram 1 of a semiconductor structure 300 provided by an embodiment of the present disclosure.
  • the semiconductor structure 300 may include:
  • Drain doped regions 302 and source doped regions 303 are formed on both sides of the channel doped region 301;
  • the insulating isolation layer 304 includes a first insulating isolation part and a second insulating isolation part.
  • the first insulating isolation layer part is formed on the surface of the channel doped region 301, and the second insulating isolation part is formed on the drain doped region. part of the surface of area 302;
  • the first metal layer 305 is formed on the surface of the first insulating isolation part
  • the second metal layer 306 is formed on the surface of the second insulating isolation part.
  • the semiconductor structure 300 may be formed in an active area of a substrate, and the substrate is not shown in the drawings.
  • the semiconductor structure can be applied to dynamic random access memory (Dynamic Random Access Memory, DRAM), such as three-dimensional DRAM (three Dimensional DRAM, 3D DRAM), in which multiple spatially stacked semiconductor structures 300 are formed in the 3D DRAM.
  • DRAM Dynamic Random Access Memory
  • 3D DRAM three Dimensional DRAM
  • the semiconductor structure 300 includes three doping regions: a channel doping region 301, a drain doping region 302 and a source doping region 303, and the drain doping region 302 and the source doping region
  • the extremely doped regions 303 are distributed on both sides of the channel doped region 301 .
  • the insulating isolation layer 304 is formed on the surface of the channel doped region 301 and part of the surface of the drain doped region 302 , and a second insulating isolation portion is formed on a side of the drain doped region 302 close to the channel doped region 301 , the insulating isolation layer 304 formed on the surface of the channel doped region 301 is referred to as the first insulating isolation part, and the insulating isolation layer 304 formed on part of the surface of the drain doped region 302 is referred to as the second insulating isolation part,
  • the first insulating isolation part and the second insulating isolation part constitute a complete insulating isolation layer 304. It can be understood that the insulating isolation layer 304 is a complete whole, and is divided into a first insulating isolation part and a second insulating isolation part only for convenience of description.
  • a metal layer is formed on the surface of the insulating isolation layer 304.
  • the metal layer specifically includes a first metal layer 305 and a second metal layer 306; wherein the first metal layer 305 is formed on the surface of the first insulating isolation part, and the second metal layer 306 formed on the surface of the second insulating isolation portion.
  • the length of the drain doped region 302 and the source doped region 303 may be the same, and the length of the second metal layer 306 may be the length of the drain doped region 302 or the source doped region 303 .
  • the channel doped region 301, the drain doped region 302, the source doped region 303, the insulating isolation layer 304, the first metal layer 305 and the second metal layer 306 are composed of One transistor (MOS tube).
  • the channel doping region 301 forms the channel of the transistor
  • the drain doping region 302 forms the drain of the transistor
  • the source doping region 303 forms the source of the transistor
  • the first metal layer 305 may form the gate of the transistor.
  • the insulating isolation layer 304 is equivalent to the gate dielectric layer of the transistor
  • the second metal layer 306 can also be regarded as a part of the gate electrode.
  • the transistor may be a junctionless transistor, specifically a JLAMT, that is, in the semiconductor structure 300, the channel doping region 301, the drain doping region 302 and the source doping region 303 are doped
  • the ion types are the same.
  • the channel doping region 301, the drain doping region 302 and the source doping region 303 can all be doped with N-type ions, thereby forming an N-type metal oxide semiconductor field effect transistor (Negative channel Metal Oxide Semiconductor, NMOS transistor), or the channel doping region 301, the drain doping region 302 and the source doping region 303 can all be doped with P-type ions, thereby forming a P-type metal oxide semiconductor field effect transistor (Positive channel). Metal Oxide Semiconductor, PMOS tube).
  • the doping of N-type ions is taken as an example for description.
  • the channel doped region 301 may be a lightly doped region (N-); the drain doped region 302 and the source doped region 303 may both be heavily doped.
  • the embodiment of the present disclosure forms a second metal layer 306 at one end of the drain (drain doped region 302) of the junctionless transistor close to the channel (channel doped region 301).
  • the second metal layer 306 can reduce leakage.
  • the concentration gradient of impurity distribution from pole to channel can effectively reduce the electric field intensity of the channel, reduce the leakage current generated by the transistor in the off state, effectively suppress the GIDL effect, and reduce the off current of the transistor; in addition, at the gate When the transistor is turned on, the gate voltage will also increase the amount of carriers, reduce the resistance, and increase the turn-on current of the transistor.
  • the length of the second metal layer can be one-fifth to one-half the length of the drain doped region or the source doped region. In this way, the GIDL effect can be suppressed while ensuring the normal operation of the transistor. will not be affected.
  • FIG. 5 shows a schematic cross-sectional view of the semiconductor structure 300.
  • FIG. 6 which shows a schematic three-dimensional structural view of a transistor provided by an embodiment of the present disclosure.
  • the gate of the transistor may be a surround gate. That is, the insulating isolation layer 304 is formed around the surface of the channel doped region 301 and part of the surface of the drain doped region 302 , and the first metal layer 305 and the second metal layer 306 are formed around the surface of the insulating isolation layer 304 .
  • the work function of the second metal layer 306 is less than or equal to the work function of the first metal layer 305, and the work function of the second metal layer 306 is greater than the preset work function threshold.
  • the first metal layer 305 (also known as the control gate, Control Gate) is a switch that controls the channel.
  • the material of the first metal layer 305 can be a metal material with a large work function, such as: iridium ( Ir), Nickel (Ni), Platinum (Pt), Cobalt (Co).
  • Ir iridium
  • Ni Nickel
  • Platinum Pt
  • Co Cobalt
  • the work function of iridium is 5.27eV
  • the work function of nickel is 5.15eV
  • the work function of platinum is 5.65eV
  • cobalt is 5eV.
  • the second metal layer 306 is used to adjust the impurity distribution in the portion of the channel close to the drain and reduce the concentration gradient of the impurity distribution from the drain to the channel, thereby effectively reducing the channel electric field.
  • the work function of the second metal layer 306 is greater than the preset work function threshold and less than or equal to the work function of the first metal layer 305.
  • the preset work function threshold can be 4.6 eV to ensure that the second metal layer 306 can reduce the channel. The effect of electric field.
  • the work function refers to the minimum energy required to move an electron from the interior of the solid to the surface of the object.
  • the size of the work function is approximately one-half of the ionization energy of the metal free atom.
  • the work function The size of represents the strength of electron binding in the metal. The larger the work function, the less likely it is for electrons to leave the metal. Since the work function of the second metal layer 306 is large (greater than 4.6 eV), the number of carriers in the drain doped region 302 (drain) can be effectively reduced.
  • the number of carriers in the channel doped region 301 (channel ) and the drain doped region 302 (drain) forms a gradient concentration junction, which ultimately reduces the electric field intensity, thereby reducing the leakage current generated by the drain of the transistor in the off state, improving the BTBT effect, and suppressing the GIDL effect.
  • the gate voltage will increase the amount of carriers and reduce the resistance, thus increasing the turn-on current of the transistor.
  • FIG. 7 shows a schematic diagram 2 of the composition of a semiconductor structure 300 provided by an embodiment of the present disclosure.
  • the semiconductor structure 300 may also include a third metal.
  • Layer 307 where,
  • the third metal layer 307 is formed on the surface of the first metal layer 305, and the third metal layer 307 is connected to the second metal layer 306.
  • the semiconductor structure 300 can also be It includes a third metal layer 307 formed on the surface of the first metal layer 305, and the third metal layer 307 and the second metal layer 306 are connected, that is to say, the third metal layer 307 is also formed on a part of the second metal layer 306.
  • the third metal layer 307 can also be regarded as a part of the gate.
  • the material of the third metal layer 307 may be the same as the material of the second metal layer 306 .
  • the third metal layer 307 and the second metal layer 306 work together to effectively reduce the leakage current of the transistor, reduce the GIDL effect caused by BTBT, reduce the off-current of the transistor, and increase the on-current of the transistor.
  • the materials of the first metal layer 305 and the second metal layer 306 may be the same.
  • FIG. 8 a schematic diagram 3 of the composition of a semiconductor structure 300 provided by an embodiment of the present disclosure is shown.
  • the drain doping region may include a first sub-doping region. 3021 and the second sub-doped region 3022, and the first sub-doped region 3021 is located between the channel doped region 301 and the second sub-doped region 3022; wherein, the second insulating isolation portion is formed in the first sub-doped region 3021 and the second sub-doped region 3022. Surface of area 3021.
  • the drain doped region can be specifically divided into a first sub-doped region 3021 and a second sub-doped region 3022.
  • the first sub-doped region 3021 is a portion isolated by the second insulation.
  • the covered part of the drain doped region, the second sub-doped region 3022 is the part of the drain doped region that is not covered by the second insulating isolation part.
  • the channel doped region 301 is a lightly doped region
  • the first sub-doped region 3021 is a medium doped region
  • the second sub-doped region 3022 and the source doped region 303 are heavily doped regions
  • the medium doped region The doping ion concentration of the region is greater than that of the lightly doped region and smaller than that of the heavily doped region.
  • the embodiment of the present disclosure can divide the drain doping region into a heavily doped second sub-doping region 3022 and a medium-doped first sub-doping region 3021, and the medium-doped first sub-doping region 3021 Region 3021 is connected to the low-doped channel doping region 301, so that the concentration gradient between the second sub-doped region 3022 and the channel doping region 301 becomes gentle, which is beneficial to reducing the leakage current of the transistor and reducing GIDL. effect.
  • FIG. 9 shows a schematic diagram 4 of the composition of a semiconductor structure 300 provided by an embodiment of the present disclosure
  • FIG. 10 shows a schematic diagram 5 of the composition of a semiconductor structure 300 provided by an embodiment of the present disclosure.
  • the insulating isolation layer 304 may also include a third insulating isolation part, and the third insulating isolation part is formed on part of the surface of the source doping region; the semiconductor structure 300 also includes a fourth metal layer. 308.
  • the fourth metal layer 308 is formed on the surface of the third insulating isolation part.
  • the fourth metal layer 308 can also be regarded as a part of the gate electrode.
  • the source doping region may include a third sub-doping region 3031 and a fourth sub-doping region 3032, and the third sub-doping region 3031 is located between the channel doping region 301 and the fourth sub-doping region. Between regions 3032, a third insulating isolation portion is formed on the surface of the third sub-doped region 3031; wherein,
  • the channel doped region 301 is a lightly doped region
  • the first sub-doped region 3021 and the third sub-doped region 3031 are both medium doped regions;
  • the second sub-doped region 3022 and the fourth sub-doped region 3032 are both heavily doped regions;
  • the doping ion concentration of the medium doping region is greater than the doping ion concentration of the lightly doped region, and the doping ion concentration of the medium doping region is less than the doping ion concentration of the heavily doped region.
  • the insulating isolation layer 304 can also be formed on part of the surface of the source doping region, specifically formed between the source doping region and the channel doping region 301 . Part of the surface of the connection, and the insulating isolation layer 304 formed on part of the surface of the source doping region is referred to as the third insulating isolation part. It can be understood that the first insulating isolation part, the second insulating isolation part and the third insulating isolation part The insulating isolation layer 304 is composed of separate parts and is divided into three parts only for convenience of description. The insulating isolation layer 304 is a complete whole. In addition, correspondingly, a third metal layer 308 is formed on the surface of the third insulation isolation part.
  • the source doping region can be divided into a third sub-doping region 3031 and a fourth sub-doping region 3032, and the third sub-doping region 3031 is located in the channel Between the doped region 301 and the fourth sub-doped region 3032, that is, the third sub-doped region 3031 is connected to the channel doped region 301, and a third insulating isolation portion is formed on the surface of the third sub-doped region 3031.
  • the channel doped region 301 can be a lightly doped region
  • the first sub-doped region 3021 and the third sub-doped region 3031 can both be medium-doped regions
  • the second sub-doped region 3022 and the fourth sub-doped region can be
  • the impurity regions 3032 are all heavily doped regions. That is to say, the embodiment of the present disclosure can also divide the source doping region into a heavily doped fourth sub-doping region 3032 and a medium-doped third sub-doping region 3031, and the medium-doped third sub-doping region 3031
  • the impurity region 3031 is connected to the low-doped channel doping region 301 .
  • the doping ion concentration of the medium doping region is greater than the doping ion concentration of the lightly doped region, and the doping ion concentration of the medium doping region is less than that of the heavily doped region.
  • Impurity ion concentration that is to say, for the three doping modes of the heavily doped region, the medium doped region and the lightly doped region involved in the embodiments of the present disclosure, they are sorted in order from high to low doping ion concentration, as follows: The heavily doped region has the highest doping ion concentration, the medium doping region has the second highest doping ion concentration, and the lightly doped region has the lowest doping ion concentration.
  • the doping ion concentration of the heavily doped region may be e 20 /cm 3
  • the doping ion concentration of the medium doping region may be e 19 /cm 3
  • the doping ion concentration of the heavily doped region may be e 18 /cm 3 .
  • the materials of the first metal layer 305, the second metal layer 306 and the fourth metal layer 308 may be the same material (as shown in FIG. 9), or the second metal layer 306 and the fourth metal layer 308 may be made of the same material.
  • the material may also be different from the material of the first metal layer 305 (as shown in Figure 10). Since the embodiments of the present disclosure have metal layers formed on both the source electrode (source doped region) and the drain electrode (drain doped region), it can weaken both the source electrode and the drain electrode and reduce the number of carriers. , thereby reducing the electric field strength, improving the BTBT effect, suppressing the GIDL effect, and reducing the leakage current of the transistor in the off state. The weakening of the source can also reduce the leakage during the precharge process of the transistor, providing a more comprehensive leakage protection. Effect.
  • Figure 11 shows a schematic diagram 6 of the composition of a semiconductor structure 300 provided by an embodiment of the present disclosure.
  • the semiconductor structure 300 may further include a fifth metal layer 309; wherein,
  • the fifth metal layer 309 is formed on the surface of the first metal layer 305, and both ends of the fifth metal layer 309 are connected to the second metal layer 306 and the fourth metal layer 308 respectively.
  • the semiconductor structure 300 can also include a fifth metal layer 309.
  • the fifth metal layer 309 is formed on the surface of the first metal layer 305, and further They are connected to the second metal layer 306 and the fourth metal layer 308 respectively. That is to say, the fifth metal layer 309 is also formed on part of the surfaces of the second metal layer 306 and the fourth metal layer 308 .
  • the fifth metal layer 309 can also be regarded as a part of the gate electrode.
  • the material of the fifth metal layer 309 can be the same as that of the second metal layer.
  • 306 and the fourth metal layer 308 are made of the same material.
  • the second metal layer 306 can have a weakening effect on the drain doped region (drain), and the fourth metal layer 308 can have a weakening effect on the source doped region (source).
  • the weakened part can be used as
  • the lightly doped drain LDD in the semiconductor structure that is, the first sub-doped region 3021 and the third sub-doped region 3031, can be used as a lightly doped drain, thereby making the weakening effect on the source/drain adjustable.
  • High doping of source and drain can reduce resistance, provide carriers for transistor conduction, and reduce Schottky barrier width.
  • lightly doping the drain can weaken the electric field in the drain region in the transistor, thereby improving a series of short channel effects such as hot electron degradation effects.
  • FIG. 12 is a comparative schematic diagram of the relationship between channel length and electric field intensity provided by an embodiment of the present disclosure.
  • FIG. 13 is a comparative schematic diagram of the energy band profile provided by an embodiment of the present disclosure.
  • JLAMT is a schematic diagram of the relationship between the electric field intensity and the channel length of a conventional accumulation mode junctionless transistor, represented by a solid line;
  • WF-JLAMT is a junctionless transistor including a second metal layer provided by an embodiment of the present disclosure.
  • Schematic diagram of the relationship between the electric field strength and channel length of a junction transistor represented by a dotted line. As shown in FIG.
  • the second insulating isolation part of the insulating isolation layer 304 is formed on part of the surface of the drain doped region 302 , in the third A second metal layer 306 is formed on the surface of the two insulating isolation parts.
  • the second metal layer 306 is made of a material with a work function greater than 4.6 eV and less than or equal to the work function of the first metal layer 305. Compared with the conventional JLAMT with only a separate metal gate , the electric field intensity of the WF-JLAMT channel is significantly reduced.
  • This step pulls up the part of the energy band where the drain and channel meet, so that the conduction band (Ec) of the drain is consistent with
  • the overlap of the valence band (Ev) of the channel (shown as the dotted elliptical box in Figure 13) is reduced or even disappeared; ultimately, the BTBT effect can be effectively improved, the leakage current of the drain is reduced, and the turn-off current of the transistor is effectively reduced. Inhibits GIDL effects.
  • the semiconductor structure 300 may also include a bit line 310 and a capacitor 311; wherein,
  • the bit line 310 is connected to the side of the source doped region 303 away from the channel doped region 301;
  • the capacitor 311 is connected to a side of the drain doped region 302 away from the channel doped region 301 .
  • bit line 310 (BL in the figure) is connected to the source doped region 303, and the capacitor 311 (CAP in the figure) is connected to the drain doped region 302. connect. Therefore, the transistor, bit line 310 and capacitor 311 can implement operations such as accessing and reading data.
  • the semiconductor structure may further include a metal isolation layer, a first control lead and a second control lead; wherein,
  • a metal isolation layer is formed between the first metal layer and the second metal layer, and is used to insulate and isolate the first metal layer and the second metal layer;
  • One end of the first control lead is connected to the first metal layer, and the other end of the first control lead is connected to the first control terminal;
  • One end of the second control lead is connected to the second metal layer, and the other end of the second control lead is connected to the second control terminal.
  • the first metal layer and the second metal layer can be controlled by the first control lead and the second control lead respectively.
  • the first metal layer and the second metal layer can be controlled by the first control lead and the second control lead respectively.
  • a metal isolation layer is added between the second metal layers to insulate them.
  • FIG. 14 shows a schematic diagram of control lead connection for individual control of metal layers provided by an embodiment of the present disclosure.
  • (a) is a schematic three-dimensional structural diagram of the semiconductor structure 300. Structures such as the bit line 310 and the capacitor 311 are not shown in (b) and (c).
  • the meanings of the serial numbers in Figure 14 are the same as those in the previous figures.
  • one end of the first control lead 313a is connected to the first metal layer 305, the other end is connected to the first control terminal (not shown in the figure), and one end of the second control lead 313b is connected to the first control terminal 305.
  • the two metal layers 306 are connected, and the other end is connected to the second control terminal (not shown in the figure).
  • a metal isolation layer 312 is provided between the first metal layer 305 and the second metal layer 306 to insulate them.
  • the first control lead 313a and the second control lead 313b may be located on different sides of the transistor as shown in (a) of Figure 14, or may be located on the same side of the transistor as shown in (b) of Figure 14.
  • the semiconductor structure may also include a third control lead 313c.
  • One end of the third control lead 313c is connected to the fourth metal layer 308, and the other end is connected to the third control terminal (not shown in the figure). shows) connection, there is also a metal isolation layer 312 between the fourth metal layer 308 and the first metal layer 305 for insulation isolation.
  • three control leads are distributed on different sides of the transistor. In addition , the three control leads can also be on the same side of the transistor.
  • first control end, the second control end and the third control end can be the same control end or different control ends, and can be external power supplies, word lines, other devices in the semiconductor memory, etc.
  • the first metal layer and the second metal layer can also be controlled through the same control lead. In this case, there is no need for insulation isolation between the first metal layer and the second metal layer.
  • the semiconductor structure may also include control leads; wherein,
  • the first metal layer and the second metal layer are connected;
  • One end of the control lead is connected to the first metal layer and/or the second metal layer, and the other end of the control lead is connected to the control terminal.
  • FIG. 15 is a schematic diagram of a control lead connection for joint control of metal layers provided by an embodiment of the present disclosure.
  • structures such as the bit line 310 and the capacitor 311 are not shown.
  • one end of the control lead 313 is connected to the first metal layer 305, and the other end is connected to the control terminal, or, as shown in (b) of Figure 15, one end of the control lead 313 is connected to the first metal layer 305.
  • the second metal layer 306 is connected, and the other end is connected to the control terminal, or the control lead 313 can also be connected to the first metal layer 305 and the second metal layer 306 at the same time, for simultaneously connecting the first metal layer 305 and the second metal layer 306 Control; in addition, as shown in (c) of FIG. 15 , the control lead 313 may be connected to the first metal layer 305 as shown in the figure, or may be connected to the second metal layer 306 or the fourth metal layer 308 .
  • the control terminal can be an external power supply, a word line, other devices in the semiconductor memory, etc.
  • the first metal layer and the second metal layer can be controlled individually or jointly, for example, they can be controlled individually or jointly from the same side of the transistor, or they can be drawn from both sides of the transistor in opposite directions. individually controlled. In this way, embodiments of the present disclosure can achieve flexible control of the first metal layer, the second metal layer, and the fourth metal layer in various ways.
  • embodiments of the present disclosure use metal materials with different work functions as gates to control the doping distribution of the channel, thereby reducing the channel electric field, reducing the turn-off current, and suppressing the GIDL effect produced by BTBT.
  • the method of using work function metal to weaken part of the drain can weaken the part of the drain close to the channel without changing the doping, thereby reducing the turn-off current and suppressing the GIDL effect.
  • the turn-on current can also be enhanced.
  • Embodiments of the present disclosure provide a semiconductor structure, including: a channel doping region; a drain doping region and a source doping region formed on both sides of the channel doping region; and an insulating isolation layer, including a first insulating isolation layer. and a second insulating isolation part, the first insulating isolation part is formed on the surface of the channel doped region, the second insulating isolation part is formed on part of the surface of the drain doped region; the first metal layer is formed on the first insulating isolation part. the surface of the part; the second metal layer is formed on the surface of the second insulating isolation part.
  • the channel doping region, the drain doping region, the source doping region, the insulating isolation layer, the first metal layer and the second metal layer may constitute a transistor.
  • a second metal layer is formed near the drain doped region.
  • the second metal layer can reduce the concentration gradient of the impurity distribution from the drain doped region to the channel doped region, reducing the drain doping.
  • the number of carriers near the region is effectively reduced, thereby effectively reducing the electric field intensity in the channel doped region.
  • the transistor is turned off, the leakage current of the transistor is reduced, thereby reducing the off-current of the transistor and suppressing GIDL caused by BTBT. Effect; in addition, when the transistor is turned on, the gate voltage will increase the amount of carriers, reduce the resistance, and also increase the turn-on current of the transistor.
  • FIG. 16 shows a schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. As shown in Figure 16, the method may include:
  • FIG. 17 is a schematic structural diagram after forming the channel doping region 301, the drain doping region 302, and the source doping region 303. In FIG. 17, only the active region part is shown.
  • the drain doped region 302 and the source doped region 303 are respectively located on both sides of the channel doped region 301 .
  • these three doping regions may be the three doping regions of a junctionless transistor. Therefore, in some embodiments, the channel doping region 301 , the drain doping region 302 and the source doping region 303
  • the doping ion types are the same; for example, the doping ion types of the three doping regions can all be N-type ion doping or P-type ion doping.
  • the channel doped region 301 may be a lightly doped region (N-), and the drain doped region 302 and the source doped region 303 may be a heavily doped region (N+). .
  • the drain doped region 302 and the source doped region 303 can also be as shown in the aforementioned Figures 7 to 11.
  • the drain doped region 302 includes a first sub-doped region 3021 and a second sub-doped region 3022.
  • the source doped region 303 includes a third sub-doped region 3031 and a fourth sub-doped region 3032. At this time, only the doping concentration needs to be changed.
  • the insulating isolation layer includes a first insulating isolation part and a second insulating isolation part.
  • the first insulating isolation part is formed on the surface of the channel doping region, and the second insulating isolation part is formed on part of the surface of the drain doping region.
  • FIG. 18 is a schematic diagram of the structure obtained after forming the insulating isolation layer 304.
  • an insulating isolation layer 304 is formed on the surface of the channel doped region 301 and part of the surface of the drain doped region 302 .
  • the insulating isolation layer 304 formed on the surface of the channel doped region 301 is referred to as the third an insulating isolation part
  • the insulating isolation layer 304 formed on part of the surface of the drain doped region 302 is referred to as a second insulating isolation part.
  • the length of the second insulating isolation part may be one-fifth to one-half of the length of the drain doped region 302 or the source doped region 303 .
  • a first metal layer and a second metal layer are respectively formed on the surfaces of the first insulating isolation part and the second insulating isolation part, thereby obtaining a junctionless transistor.
  • forming the first metal layer on the surface of the first insulating isolation part may include:
  • FIG. 19 is a schematic structural diagram after the mask layer 316 is formed. As shown in FIG. 19 , when forming the first metal layer, a mask layer 316 is first formed on the surface of the second insulating isolation part. The material of the mask layer 316 may be photoresist or the like.
  • FIG. 20 is a schematic structural diagram of the first metal layer 305 after the formation of the first metal layer 305 .
  • the mask layer 316 is removed to obtain the structure shown in Figure 21.
  • a first metal layer 305 is formed on the surface of the first insulating isolation part, and the second insulating isolation part is exposed.
  • a second metal layer 306 is formed on the surface of the second insulating isolation part, resulting in a structure as shown in FIG. 22 .
  • the work function of the second metal layer is less than or equal to the work function of the first metal layer, and the work function of the second metal layer is greater than the preset work function threshold.
  • the second metal layer 306 is used to adjust the impurity distribution in the part of the channel close to the drain, reduce the concentration gradient of the impurity distribution from the drain to the channel, and can effectively reduce the channel electric field.
  • the work function of the second metal layer 306 is greater than the preset work function threshold and less than or equal to the work function of the first metal layer 305.
  • the preset work function threshold may be 4.6 eV to ensure that the second metal layer 306 can reduce Effect of channel electric field.
  • the method when forming the second metal layer on the surface of the second insulating isolation part, the method may further include:
  • a third metal layer is formed on the surface of the first metal layer, and the third metal layer is connected to the second metal layer.
  • the material of the third metal layer is the same as the material of the second metal layer.
  • Figure 23 is a schematic structural diagram after forming the third metal layer 307. At this time, the semiconductor structure as shown in Figure 7 can be formed, and the second metal layer 305 and the third metal layer 307 can work together. Achieve reduction of GIDL effect.
  • the method may also include:
  • bit line and a capacitor are formed; the bit line is connected to a side of the drain doped region away from the channel doped region; the capacitor is connected to a side of the source doped region away from the channel doped region.
  • FIG. 5 or FIG. 7 the structure obtained after forming the capacitor and the bit line can be shown in FIG. 5 or FIG. 7 .
  • the embodiments of the present disclosure only take the formation of the semiconductor structure shown in Figure 5 or Figure 7 as an example to illustrate the preparation method of the semiconductor structure. Based on similar methods, the semiconductor structure shown in any of the aforementioned Figures 8 to 11 can also be formed. The semiconductor structure will not be described in detail here.
  • Embodiments of the present disclosure provide a method for preparing a semiconductor structure.
  • a second metal layer is formed near the drain doped region.
  • the second metal layer can reduce the drain doped region to
  • the concentration gradient of the impurity distribution in the channel doped region reduces the number of carriers near the drain doped region, thereby effectively reducing the electric field intensity in the channel doped region and suppressing gate-induced leakage due to band-to-band tunneling effect. Extreme leakage current.
  • FIG. 24 shows a schematic structural diagram of a semiconductor memory 400 provided by an embodiment of the present disclosure.
  • the semiconductor memory 400 includes the semiconductor structure 300 described in any of the previous embodiments.
  • the semiconductor memory 400 may include 3D DRAM.
  • the gate-induced drain leakage current caused by the band-to-band tunneling effect can be effectively suppressed.
  • Embodiments of the present disclosure provide a semiconductor structure, a preparation method of the semiconductor structure, and a semiconductor memory.
  • the semiconductor structure includes: a channel doping region; a drain doping region and a source doping region formed on both sides of the channel doping region. Impurity region; insulating isolation layer, including a first insulating isolation part and a second insulating isolation part, the first insulating isolation part is formed on the surface of the channel doping region, and the second insulating isolation part is formed on part of the surface of the drain doping region ;
  • the first metal layer is formed on the surface of the first insulating isolation part; the second metal layer, formed on the surface of the second insulating isolation portion.
  • the second metal layer can reduce the concentration gradient of the impurity distribution from the drain doped region to the channel doped region, reduce the number of carriers near the drain doped region, thereby effectively reducing the channel doping
  • the electric field strength of the hybrid region suppresses the gate-induced drain leakage current caused by the band-to-band tunneling effect.

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Abstract

本公开实施例提供了一种半导体结构、半导体结构的制备方法和半导体存储器，该半导体结构包括：沟道掺杂区；形成在沟道掺杂区两侧的漏极掺杂区和源极掺杂区；绝缘隔离层，包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离部分形成在沟道掺杂区的表面，第二绝缘隔离部分形成在漏极掺杂区的部分表面；第一金属层，形成在第一绝缘隔离部分的表面；第二金属层，形成在第二绝缘隔离部分的表面。

Description

半导体结构、半导体结构的制备方法和半导体存储器
相关申请的交叉引用
本申请要求在2022年08月12日提交中国专利局、申请号为202210966053.3、申请名称为“半导体结构、半导体结构的制备方法和半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及存储器技术领域，尤其涉及一种半导体结构、半导体结构的制备方法和半导体存储器。
背景技术
栅诱导漏极泄露电流(Gate Induced Drain Leakage，GIDL)是金属-氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，MOSFET，MOS管)的主要断态漏电机理，严重影响着MOS管器件的可靠性。在MOS管栅极关断而漏极接电压时，漏极杂质扩散层与栅极重叠部分靠近界面处的能带发生强烈的弯曲，表面形成反型层，而耗尽层非常窄，导带电子和价带空穴发生带-带隧穿效应(Band-to-Band Tunneling，BTBT)，从而形成漏极漏电流，随着器件尺寸的不断缩小，器件内横向电场不断增强，热载流子效应引起断态漏电的几率随之变大。
发明内容
本公开实施例提供了一种半导体结构、半导体结构的制备方法和半导体存储器：
第一方面，本公开实施例提供了一种半导体结构，包括：
沟道掺杂区；
形成在所述沟道掺杂区两侧的漏极掺杂区和源极掺杂区；
绝缘隔离层，包括第一绝缘隔离部分和第二绝缘隔离部分，所述第一绝缘隔离部分形成在所述沟道掺杂区的表面，所述第二绝缘隔离部分形成在所述漏极掺杂区的部分表面；
第一金属层，形成在所述第一绝缘隔离部分的表面；
第二金属层，形成在所述第二绝缘隔离部分的表面。
在一些实施例中，所述第二金属层的功函数小于或者等于所述第一金属层的功函数，且所述第二金属层的功函数大于预设功函数阈值。
在一些实施例中，所述预设功函数阈值为4.6电子伏特。
在一些实施例中，所述第一金属层的材料包括下述至少之一：铱、镍、铂、 钴。
在一些实施例中，所述半导体结构还包括第三金属层，所述第三金属层的材料与所述第二金属层的材料相同；其中，
所述第三金属层形成在所述第一金属层的表面，且所述第三金属层与所述第二金属层连接。
在一些实施例中，所述沟道掺杂区、所述漏极掺杂区以及所述源极掺杂区的掺杂离子类型相同。
在一些实施例中，所述沟道掺杂区为轻掺杂区；
所述漏极掺杂区和所述源极掺杂区均为重掺杂区；
其中，所述重掺杂区的掺杂离子浓度大于所述轻掺杂区的掺杂离子浓度。
在一些实施例中，所述漏极掺杂区包括第一子掺杂区和第二子掺杂区，且所述第一子掺杂区位于所述沟道掺杂区与所述第二子掺杂区之间；其中，所述第二绝缘隔离部分形成在所述第一子掺杂区的表面。
在一些实施例中，所述绝缘隔离层还包括第三绝缘隔离部分，所述第三绝缘隔离部分形成在所述源极掺杂区的部分表面；
所述半导体结构还包括第四金属层，所述第四金属层形成在所述第三绝缘隔离部分的表面。
在一些实施例中，所述源极掺杂区包括第三子掺杂区和第四子掺杂区，且所述第三子掺杂区位于所述沟道掺杂区与所述第四子掺杂区之间，所述第三绝缘隔离部分形成在所述第三子掺杂区的表面；其中，
所述沟道掺杂区为轻掺杂区；
所述第一子掺杂区和所述第三子掺杂区均为中掺杂区；
所述第二子掺杂区和所述第四子掺杂区均为重掺杂区；
其中，所述中掺杂区的掺杂离子浓度大于所述轻掺杂区的掺杂离子浓度，且所述中掺杂区的掺杂离子浓度小于所述重掺杂区的掺杂离子浓度。
在一些实施例中，所述半导体结构还包括第五金属层；其中，
所述第五金属层形成在所述第一金属层的表面，且所述第五金属层的两端与所述第二金属层和所述第四金属层分别连接。
在一些实施例中，所述半导体结构还包括位线和电容；其中，
所述位线与所述源极掺杂区的远离所述沟道掺杂区的一侧连接；
所述电容与所述漏极掺杂区的远离所述沟道掺杂区的一侧连接。
在一些实施例中，所述半导体结构还包括控制引线；其中，
所述第一金属层和所述第二金属层连接；
所述控制引线的一端与所述第一金属层和/或所述第二金属层连接，所述控制引线的另一端与控制端连接。
在一些实施例中，所述半导体结构还包括金属隔离层、第一控制引线和第二控制引线；其中，
所述金属隔离层形成于所述第一金属层和所述第二金属层之间，用于将所述第一金属层和所述第二金属层进行绝缘隔离；
所述第一控制引线的一端与所述第一金属层连接，所述第一控制引线的另 一端与第一控制端连接；
所述第二控制引线的一端与所述第二金属层连接，所述第二控制引线的另一端与第二控制端连接。
第二方面，本公开实施例提供了一种半导体结构的制备方法，包括：
提供衬底；
对所述衬底进行掺杂，于所述衬底中形成沟道掺杂区、漏极掺杂区和源极掺杂区，且所述漏极掺杂区和所述源极掺杂区形成在所述沟道掺杂区的两侧；
形成绝缘隔离层，所述绝缘隔离层包括第一绝缘隔离部分和第二绝缘隔离部分，所述第一绝缘隔离部分形成在所述沟道掺杂区的表面，所述第二绝缘隔离部分形成在所述漏极掺杂区的部分表面；
于所述第一绝缘隔离部分的表面形成第一金属层；
于所述第二绝缘隔离部分的表面形成第二金属层。
在一些实施例中，所述于所述第一绝缘隔离部分的表面形成第一金属层，包括：
于所述第二绝缘隔离部分的表面形成掩膜层；
以所述掩膜层为掩膜，于所述第一绝缘隔离部分的表面形成第一金属层；
去除所述掩膜层。
在一些实施例中，在所述于所述第二绝缘隔离部分的表面形成第二金属层时，所述方法还包括：
于所述第一金属层的表面形成第三金属层，且所述第三金属层与所述第二金属层连接；其中，所述第三金属层的材料与所述第二金属层的材料相同。
在一些实施例中，该方法还包括：
形成位线和电容；其中，所述位线与所述漏极掺杂区的远离所述沟道掺杂区的一侧连接；所述电容与所述源极掺杂区的远离所述沟道掺杂区的一侧连接。
在一些实施例中，所述第二金属层的功函数小于或者等于所述第一金属层的功函数，且所述第二金属层的功函数大于预设功函数阈值；其中，所述预设功函数阈值为4.6电子伏特。
第三方面，本公开实施例提供了一种半导体存储器，包括如第一方面任一项所述的半导体结构。
附图说明
图1为一种无结晶体管的组成结构示意图；
图2为一种累积模式无结晶体管的组成结构示意图；
图3为一种沟道长度与电场强度的关系示意图；
图4为一种能带轮廓示意图；
图5为本公开实施例提供的一种半导体结构的组成结构示意图一；
图6为本公开实施例提供的一种晶体管的立体结构示意图；
图7为本公开实施例提供的一种半导体结构的组成结构示意图二；
图8为本公开实施例提供的一种半导体结构的组成结构示意图三；
图9为本公开实施例提供的一种半导体结构的组成结构示意图四；
图10为本公开实施例提供的一种半导体结构的组成结构示意图五；
图11为本公开实施例提供的一种半导体结构的组成结构示意图六；
图12为本公开实施例提供的一种沟道长度与电场强度的关系对比示意图；
图13为本公开实施例提供的一种能带轮廓对比示意图；
图14为本公开实施例提供的一种金属层单独控制的控制引线连接示意图；
图15为本公开实施例提供的一种金属层共同控制的控制引线连接示意图；
图16为本公开实施例提供的一种半导体结构的制备方法的流程示意图；
图17为本公开实施例提供的一种形成沟道掺杂区、漏极掺杂区和源极掺杂区后所得的结构示意图；
图18为本公开实施例提供的一种形成绝缘隔离层后所得的结构示意图；
图19为本公开实施例提供的一种形成掩膜层后所得的结构示意图；
图20为本公开实施例提供的一种形成第一金属层后所得的结构示意图；
图21为本公开实施例提供的一种去除掩膜层后所得的结构示意图；
图22为本公开实施例提供的一种形成第二金属层后所得的结构示意图；
图23为本公开实施例提供的一种形成第三金属层后所得的结构示意图；
图24为本公开实施例提供的一种半导体存储器的组成结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
无结型晶体管相对于有结型晶体管来说，消除了晶体管中沟道(Channel)与源极(Source，S)/漏极(Drain，D)之间陡峭的浓度梯度分布，降低了热预算，简化制作工艺，同时也消除了短沟道效应的影响。无结型晶体管主要可以分为无结晶体管(Junction Less Transistor，JLT)和累积模式无结晶体管(Accumulation Mode Junction Less Transistor，JLAMT)。
图1为一种无结晶体管JLT的组成结构示意图。如图1所示，对于JLT而 言，其可以包括沟道101、位于沟道两侧的漏极102和源极103，形成在沟道101表面的栅介质层104和形成在栅介质层104表面的栅极105，其中，D表示与漏极102连接的器件，S表示与源极103连接的器件。如图1所示，在JLT中，沟道101、漏极102和源极103的掺杂类型均为N型中掺杂(N type medium dopant，用N表示)，例如，N型中掺杂的离子浓度为：e19个每立方厘米(e19/cm3)。这时候，由于轻掺杂的扩展，晶体管具有更好的关断状态，但是晶体管的开启电流低。
图2为一种累积模式无结晶体管JLAMT的组成结构示意图。如图2所示，对于JLAMT而言，其可以包括沟道201、位于沟道两侧的漏极202和源极203，形成在沟道201表面的栅介质层204和形成在栅介质层204表面的栅极205，其中，D表示与漏极202连接的器件，S表示与源极203连接的器件。如图2所示，在JLAMT中，沟道201的掺杂类型为N型轻掺杂(N type light dopant，用N-表示)，例如，N型轻掺杂的离子浓度为：e18/cm3，漏极202和源极203的掺杂类型均为N型重掺杂(N type heave dopant，用N+表示)，例如，N型重掺杂的离子浓度为：e20/cm3。这时候，晶体管的开启电压高，但是由于BTBT的影响，电流泄露更严重。
图3为一种沟道长度与电场强度的关系示意图，图4为一种能带轮廓示意图。其中，图3和图4均对应图2所示的JLAMT。在图3中，横轴为沟道长度(单位为：纳米(nm))，纵轴为电场强度(单位为：毫伏每厘米(mV/cm))，在该JLAMT中，电场强度较强，导致晶体管的漏电流大。在图4中，横轴对应JLAMT中源极、沟道和漏极所处位置，纵轴为能量(单位为：电子伏特(eV))；如图4所示，该能带轮廓是在源漏电压Vd＝1V，栅源电压Vg＝0V时获取的。由于电场强度较强，能带的弯曲程度大，漏极的导带(Ec)和沟道的价带(Ev)的重叠区域大。这些均会导致JLAMT中电流泄露严重。
基于此，本公开实施例提供了一种半导体结构，包括：沟道掺杂区；形成在沟道掺杂区两侧的漏极掺杂区和源极掺杂区；绝缘隔离层，包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离部分形成在沟道掺杂区的表面，第二绝缘隔离部分形成在漏极掺杂区的部分表面；第一金属层，形成在第一绝缘隔离部分的表面；第二金属层，形成在第二绝缘隔离部分的表面。这样，在半导体结构中，在漏极掺杂区的附近形成第二金属层，第二金属层能够降低漏极掺杂区到沟道掺杂区的杂质分布的浓度梯度，降低漏极掺杂区附近的载流子数量，从而有效降低沟道掺杂区的电场强度，抑制由于带-带隧穿效应(BTBT)导致的栅诱导漏极泄露电流(GIDL)。
下面将结合附图对本公开各实施例进行详细说明。
本公开的一实施例中，参见图5，其示出了本公开实施例提供的一种半导体结构300的组成结构示意图一。如图5所示，该半导体结构300可以包括：
沟道掺杂区301；
形成在沟道掺杂区301两侧的漏极掺杂区302和源极掺杂区303；
绝缘隔离层304，包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离层部分形成在沟道掺杂区301的表面，第二绝缘隔离部分形成在漏极掺杂 区302的部分表面；
第一金属层305，形成在第一绝缘隔离部分的表面；
第二金属层306，形成在第二绝缘隔离部分的表面。
需要说明的是，该半导体结构300可以形成在衬底的有源区中，附图中未示出衬底。另外，该半导体结构可以应用于动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，例如三维DRAM(three Dimensional DRAM，3D DRAM)，在3D DRAM中形成有多个空间堆叠的半导体结构300。
如图5所示，在该半导体结构300中，包括三个掺杂区：沟道掺杂区301、漏极掺杂区302和源极掺杂区303，且漏极掺杂区302和源极掺杂区303分布在沟道掺杂区301的两侧。绝缘隔离层304形成在沟道掺杂区301的表面和漏极掺杂区302的部分表面，且第二绝缘隔离部分形成在漏极掺杂区302的靠近沟道掺杂区301的一侧，将形成在沟道掺杂区301的表面的绝缘隔离层304记作第一绝缘隔离部分，将形成在漏极掺杂区302的部分表面的绝缘隔离层304记作第二绝缘隔离部分，第一绝缘隔离部分和第二绝缘隔离部分组成完整的绝缘隔离层304。可以理解的是，绝缘隔离层304是一个完整的整体，划分为第一绝缘隔离部分和第二绝缘隔离部分只是为了便于描述。
在绝缘隔离层304的表面形成有金属层，金属层具体包括第一金属层305和第二金属层306；其中，第一金属层305形成在第一绝缘隔离部分的表面，第二金属层306形成在第二绝缘隔离部分的表面。
需要说明的是，漏极掺杂区302和源极掺杂区303的长度可以是相同的，第二金属层306的长度可以为漏极掺杂区302或者源极掺杂区303的长度的五分之一到二分之一。
还需要说明的是，在半导体结构300中，沟道掺杂区301、漏极掺杂区302、源极掺杂区303、绝缘隔离层304、第一金属层305和第二金属层306组成一晶体管(MOS管)。其中，沟道掺杂区301形成晶体管的沟道，漏极掺杂区302形成晶体管的漏极，源极掺杂区303形成晶体管的源极，第一金属层305可以形成晶体管的栅极。其中，绝缘隔离层304相当于晶体管的栅介质层，第二金属层306也可以视作栅极的一部分。
还需要说明的是，该晶体管可以为无结型晶体管，具体可以是JLAMT，即在半导体结构300中，沟道掺杂区301、漏极掺杂区302以及源极掺杂区303的掺杂离子类型相同。例如，沟道掺杂区301、漏极掺杂区302和源极掺杂区303可以均为N型离子的掺杂，从而形成N型金属氧化物半导体场效应管(Negative channel Metal Oxide Semiconductor，NMOS管)，或者，沟道掺杂区301、漏极掺杂区302和源极掺杂区303可以均为P型离子的掺杂，从而形成P型金属氧化物半导体场效应管(Positive channel Metal Oxide Semiconductor，PMOS管)。在本公开实施例中，以N型离子的掺杂为例进行描述。
进一步地，如图5所示，在本公开实施例中，沟道掺杂区301可以为轻掺杂区(N-)；漏极掺杂区302和源极掺杂区303可以均为重掺杂区(N+)。即沟道掺杂区301、漏极掺杂区302和源极掺杂区303的掺杂离子类型相同，但是掺杂离子的浓度不同，其中，重掺杂区的掺杂离子浓度大于轻掺杂区的掺杂 离子浓度。
这样，本公开实施例在无结型晶体管的漏极(漏极掺杂区302)靠近沟道(沟道掺杂区301)的一端形成第二金属层306，第二金属层306能够降低漏极到沟道的杂质分布的浓度梯度，从而能够有效降低沟道的电场强度，减少晶体管在关断状态下产生的漏电流，有效抑制GIDL效应，降低了晶体管的关断电流；另外，在栅极开启的时候，栅极电压还会增加载流子量，降低电阻，还可以提高晶体管的开启电流。
另外，第二金属层的长度可以为漏极掺杂区或者源极掺杂区的长度的五分之一到二分之一，这样，还能够在抑制GIDL效应的同时，保证晶体管的正常工作不会受到影响。
还需要说明的是，图5示出的是半导体结构300的剖面示意图，对于半导体结构300中的晶体管，参见图6，其示出了本公开实施例提供的一种晶体管的立体结构示意图。如图6所示，晶体管的栅极可以为环绕栅。也就是说，绝缘隔离层304环绕沟道掺杂区301的表面和漏极掺杂区302的部分表面形成，第一金属层305和第二金属层306环绕绝缘隔离层304的表面形成。
在一些实施例中，第二金属层306的功函数小于或者等于第一金属层305的功函数，且第二金属层306的功函数大于预设功函数阈值。
需要说明的是，第一金属层305(也可以称作控制栅极、Control Gate)为控制沟道的开关，第一金属层305的材料可以为功函数较大的金属材料，例如：铱(Ir)、镍(Ni)、铂(Pt)、钴(Co)。其中，铱的功函数为5.27eV，镍的功函数为5.15eV，铂的功函数为5.65eV，钴的功函数为5eV。
第二金属层306用于调节沟道靠近漏极部分的杂质分布，降低漏极到沟道的杂质分布的浓度梯度，从而能够有效降低沟道电场。第二金属层306的功函数大于预设功函数阈值并小于或者等于第一金属层305的功函数，其中，预设功函数阈值可以为4.6eV，保证第二金属层306能够起到降低沟道电场的效果。
其中，功函数(Work Function，WF)是指把一个电子从固体内部刚刚移到此物体表面所需的最少的能量，功函数的大小大概为金属自由原子电离能的二分之一，功函数的大小标志着电子在金属中束缚的强弱，功函数越大，电子越不容易离开金属。由于第二金属层306的功函数较大(大于4.6eV)，则能够有效降低漏极掺杂区302(漏极)的载流子数量，这样，会在沟道掺杂区301(沟道)和漏极掺杂区302(漏极)之间形成浓度缓变结，最终降低电场强度，从而减少晶体管的漏极在关断状态下产生的漏电流，改善BTBT效应，抑制GIDL效应。另外，在栅极开启的时候，栅极电压会使得载流子量增加，降低电阻，从而提高晶体管的开启电流。
进一步地，参见图7，其示出了本公开实施例提供的一种半导体结构300的组成结构示意图二，如图7所示，在一些实施例中，该半导体结构300还可以包括第三金属层307；其中，
第三金属层307形成在第一金属层305的表面，且第三金属层307与第二金属层306连接。
需要说明的是，如图7所示，在本公开实施例中，半导体结构300还可以 包括形成在第一金属层305的表面的第三金属层307，而且第三金属层307和第二金属层306连接，也就是说，第三金属层307还形成在第二金属层306的部分表面，第三金属层307也可视作栅极的一部分。其中，第三金属层307的材料可以与第二金属层306的材料相同。这时候，第三金属层307和第二金属层306共同作用，也能够有效减少晶体管的漏电流，降低由于BTBT导致的GIDL效应，降低晶体管的关断电流，并提高晶体管的开启电流。
进一步地，第一金属层305和第二金属层306的材料可以是相同的。参见图8，其示出了本公开实施例提供的一种半导体结构300的组成结构示意图三，如图8所示，在一些实施例中，漏极掺杂区可以包括第一子掺杂区3021和第二子掺杂区3022，且第一子掺杂区3021位于沟道掺杂区301与第二子掺杂区3022之间；其中，第二绝缘隔离部分形成在第一子掺杂区3021的表面。
需要说明的是，如图8所示，漏极掺杂区可以具体分为第一子掺杂区3021和第二子掺杂区3022，第一子掺杂区3021即被第二绝缘隔离部分所覆盖的部分漏极掺杂区，第二子掺杂区3022即未被第二绝缘隔离部分所覆盖的部分漏极掺杂区。其中，沟道掺杂区301为轻掺杂区，第一子掺杂区3021为中掺杂区，第二子掺杂区3022和源极掺杂区303为重掺杂区，中掺杂区的掺杂离子浓度大于轻掺杂区的掺杂离子浓度且小于重掺杂区的掺杂离子浓度。也就是说，本公开实施例可以将漏极掺杂区分为重掺杂的第二子掺杂区3022和中掺杂的第一子掺杂区3021，且中掺杂的第一子掺杂区3021与低掺杂的沟道掺杂区301连接，从而使得第二子掺杂区3022和沟道掺杂区301之间的浓度梯度变得平缓，有利于减少晶体管的漏电流，降低GIDL效应。
进一步地，图9示出了本公开实施例提供的一种半导体结构300的组成结构示意图四，图10示出了本公开实施例提供的一种半导体结构300的组成结构示意图五，如图9或者图10所示，在一些实施例中，绝缘隔离层304还可以包括第三绝缘隔离部分，第三绝缘隔离部分形成在源极掺杂区的部分表面；半导体结构300还包括第四金属层308，第四金属层308形成在第三绝缘隔离部分的表面。
其中，第四金属层308也可视作栅极的一部分。
在一些实施例中，源极掺杂区可以包括第三子掺杂区3031和第四子掺杂区3032，且第三子掺杂区3031位于沟道掺杂区301与第四子掺杂区3032之间，第三绝缘隔离部分形成在第三子掺杂区3031的表面；其中，
沟道掺杂区301为轻掺杂区；
第一子掺杂区3021和第三子掺杂区3031均为中掺杂区；
第二子掺杂区3022和第四子掺杂区3032均为重掺杂区；
其中，中掺杂区的掺杂离子浓度大于轻掺杂区的掺杂离子浓度，且中掺杂区的掺杂离子浓度小于重掺杂区的掺杂离子浓度。
需要说明的是，如图9或者图10所示，绝缘隔离层304还可以形成在源极掺杂区的部分表面，具体是形成在源极掺杂区的靠近与沟道掺杂区301的连接处的部分表面，将形成在源极掺杂区的部分表面的绝缘隔离层304记作第三绝缘隔离部分。可以理解，第一绝缘隔离部分、第二绝缘隔离部分和第三绝缘隔 离部分组成完成的绝缘隔离层304，划分为三个部分仅是为了便于描述，绝缘隔离层304是一个完整的整体。另外，对应地，在第三绝缘隔离部分的表面形成有第三金属层308。
还需要说明的是，如图9或者图10所示，源极掺杂区可以分为第三子掺杂区3031和第四子掺杂区3032，且第三子掺杂区3031位于沟道掺杂区301和第四子掺杂区3032之间，即第三子掺杂区3031与沟道掺杂区301连接，第三绝缘隔离部分形成在第三子掺杂区3031的表面。
其中，沟道掺杂区301可以为轻掺杂区，第一子掺杂区3021和第三子掺杂区3031可以均为中掺杂区，第二子掺杂区3022和第四子掺杂区3032均为重掺杂区。也就是说，本公开实施例还可以将源极掺杂区分为重掺杂的第四子掺杂区3032和中掺杂的第三子掺杂区3031，且中掺杂的第三子掺杂区3031与低掺杂的沟道掺杂区301连接。
还需要说明的是，在本公开实施例中，中掺杂区的掺杂离子浓度大于轻掺杂区的掺杂离子浓度，且中掺杂区的掺杂离子浓度小于重掺杂区的掺杂离子浓度。也就是说，对于本公开实施例中涉及到的重掺杂区、中掺杂区和轻掺杂区三种掺杂方式，按照掺杂离子浓度由高至低的顺序进行排序，依次为：重掺杂区的掺杂离子浓度最高，中掺杂区的掺杂离子浓度次之，轻掺杂区的掺杂离子浓度最低。示例性地，重掺杂区的掺杂离子浓度可以为e20/cm3，中掺杂区的掺杂离子浓度可以为e19/cm3，重掺杂区的掺杂离子浓度可以为e18/cm3。
这样，不仅使得沟道掺杂区301(沟道)和漏极掺杂区(漏极)之间的浓度梯度呈缓慢变化，还使得沟道掺杂区301(沟道)和源极掺杂区(源极)之间的浓度梯度呈缓慢变化，从而减小晶体管的漏电流。
还需要说明的是，第一金属层305、第二金属层306以及第四金属层308的材料可以为相同材料(如图9所示)，或者第二金属层306以及第四金属层308的材料也可以与第一金属层305的材料不同(如图10所示)。由于本公开实施例在源极(源极掺杂区)和漏极(漏极掺杂区)都形成有金属层，从而对源极和漏极都能够起到弱化效果，降低载流子数量，从而降低电场强度，改善BTBT效应，抑制GIDL效应，减少晶体管在关断状态下的漏电流，对源极的弱化还能够降低在晶体管的预充电过程中的漏电，起到更全面的漏电保护效果。
进一步地，在图10所示的半导体结构的基础上，参见图11，其示出了本公开实施例提供的一种半导体结构300的组成结构示意图六，如图11所示，在一些实施例中，半导体结构300还可以包括第五金属层309；其中，
第五金属层309形成在第一金属层305的表面，且第五金属层309的两端与第二金属层306和第四金属层308分别连接。
需要说明的是，如图11所示，在图10所示结构的基础上，半导体结构300还可以包括第五金属层309，第五金属层309形成在第一金属层305的表面，而且还与第二金属层306和第四金属层308分别连接，也就是说，第五金属层309还形成在第二金属层306和第四金属层308的部分表面。其中，第五金属层309也可视作栅极的一部分。
还需要说明的是，如图11所示，第五金属层309的材料可以与第二金属层 306和第四金属层308的材料相同。第二金属层306可以对漏极掺杂区(漏极)起到弱化效果，第四金属层308可以对源极掺杂区(源极)起到弱化效果，同时，被弱化的部分可以作为半导体结构中的轻掺杂漏极LDD，即第一子掺杂区3021和第三子掺杂区3031可以作为轻掺杂漏极，从而使得对源极/漏极的弱化效果具有可调节性；源极和漏极的高掺杂能够降低电阻，提供晶体管导通的载流子，减小肖特基势垒宽度。另外，轻掺杂漏极能够减弱晶体管中的漏区电场，从而能够改进热电子退化效应等一系列的短沟道效应。
示例性的，参见图12和图13，图12为本公开实施例提供的一种沟道长度与电场强度的关系对比示意图，图13为本公开实施例提供的一种能带轮廓对比示意图。在图12和图13中，JLAMT为常规的累积模式无结晶体管的电场强度与沟道长度的关系示意图，用实线表示；WF-JLAMT为本公开实施例提供的包含第二金属层的无结型晶体管的电场强度与沟道长度的关系示意图，用虚线表示。如图12所示，与常规的JLAMT相比，在本公开实施例提供的半导体结构中，由于在漏极掺杂区302的部分表面形成有绝缘隔离层304的第二绝缘隔离部分，在第二绝缘隔离部分的表面形成有第二金属层306，第二金属层306采用功函数大于4.6eV并小于等于第一金属层305的功函数的材料，相较于只有单独金属栅极的常规JLAMT，WF-JLAMT的沟道的电场强度明显降低。
如图13所示，与常规的JLAMT相比，由于在WF-JLAMT中，漏极靠近沟道部分的电场降低，使得能带弯曲减小，在第二金属层306的作用下，如图13中的虚线方框所示，WF-JLAMT的漏极的能带中多出了一个台阶，这个台阶将漏极和沟道交接的部分能带拉高，从而漏极的导带(Ec)与沟道的价带(Ev)的重叠(如图13中的虚线椭圆框所示)减小甚至消失；最终能够有效改善BTBT效应，减少漏极的漏电流，从而有效减少晶体管的关断电流，抑制GIDL效应。
进一步地，如前述图4或者图7至11的任一附图所示，在一些实施例中，该半导体结构300还可以包括位线310和电容311；其中，
位线310与源极掺杂区303的远离沟道掺杂区301的一侧连接；
电容311与漏极掺杂区302的远离沟道掺杂区301的一侧连接。
需要说明的是，以图5为例，如图5所示，位线310(图中的BL)与源极掺杂区303连接，电容311(图中的CAP)与漏极掺杂区302连接。从而晶体管、位线310和电容311能够实现对数据的存取读出等操作。
进一步地，在一些实施例中，半导体结构还可以包括金属隔离层、第一控制引线和第二控制引线；其中，
金属隔离层形成于第一金属层和第二金属层之间，用于将第一金属层和第二金属层进行绝缘隔离；
第一控制引线的一端与第一金属层连接，第一控制引线的另一端与第一控制端连接；
第二控制引线的一端与第二金属层连接，第二控制引线的另一端与第二控制端连接。
需要说明的是，在本公开实施例中，第一金属层和第二金属层可以分别通过第一控制引线和第二控制引线分别进行控制，这时候，可以在第一金属层和 第二金属层之间增加金属隔离层将两者进行绝缘隔离。示例性地，参见图14，其示出了本公开实施例提供的一种金属层单独控制的控制引线连接示意图。其中，(a)为半导体结构300的立体结构示意图，(b)和(c)中未示出位线310、电容311等结构，图14中各序号的含义与前述附图均相同。
如图14中的各图所示，第一控制引线313a的一端与第一金属层305连接，另一端与第一控制端(图中未示出)连接，第二控制引线313b的一端与第二金属层306连接，另一端与第二控制端(图中未示出)连接，在第一金属层305和第二金属层306之间设有金属隔离层312将两者进行绝缘隔离。第一控制引线313a和第二控制引线313b可以如图14中的(a)所示，位于晶体管不同侧，也可以如图14中的(b)所示，位于晶体管相同侧。另外，如图14中的(c)所示，半导体结构还可以包括第三控制引线313c，第三控制引线313c的一端与第四金属层308连接，另一端与第三控制端(图中未示出)连接，第四金属层308和第一金属层305之间也存在金属隔离层312进行绝缘隔离，在图14中的(c)中，三个控制引线分布于晶体管的不同侧，另外，三个控制引线也可以位于晶体管的同侧。
还需要说明的是，第一控制端、第二控制端和第三控制端可以为同一控制端或者不同的控制端，可以为外部电源、字线、半导体存储器中的其它器件等。
进一步地，第一金属层和第二金属层还可以通过同一控制引线进行控制，这时候，第一金属层和第二金属层之间无需进行绝缘隔离。在一些实施例中，半导体结构还可以包括控制引线；其中，
第一金属层和第二金属层连接；
控制引线的一端与第一金属层和/或第二金属层连接，控制引线的另一端与控制端连接。
需要说明的是，图15为本公开实施例提供的一种金属层共同控制的控制引线连接示意图，在图15中，未示出位线310、电容311等结构。如图15中的(a)所示，控制引线313的一端与第一金属层305连接，另一端与控制端连接，或者，如图15中的(b)所示，控制引线313的一端与第二金属层306连接，另一端与控制端连接，或者控制引线313还可以同时与第一金属层305和第二金属层306连接，用于同时对第一金属层305和第二金属层306进行控制；另外，如图15中的(c)所示，控制引线313可以如图所示与第一金属层305连接，也可以与第二金属层306或者第四金属层308连接。其中，控制端可以为外部电源、字线、半导体存储器中的其它器件等等。
也就是说，在本公开实施例中，第一金属层和第二金属层可以分别单独控制也可以共同控制，例如从晶体管的同一侧单独或共同控制，或者从晶体管的两侧相反的方向引出单独控制。这样，本公开实施例可以通过多种方式实现对第一金属层、第二金属层以及第四金属层的灵活控制。
简言之，本公开实施例利用不同功函数的金属材料作为栅极，用于控制沟道的掺杂分布，从而达到降低沟道电场，减小关断电流，抑制BTBT所产生的GIDL效应。采用功函数金属弱化部分漏极的方法，可以在不改变掺杂的前提下，弱化漏极接近沟道的部分，从而在达到降低关断电流，抑制GIDL效应的 同时，还可以增强开启电流。
本公开实施例提供了一种半导体结构，包括：沟道掺杂区；形成在沟道掺杂区两侧的漏极掺杂区和源极掺杂区；绝缘隔离层，包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离部分形成在沟道掺杂区的表面，第二绝缘隔离部分形成在漏极掺杂区的部分表面；第一金属层，形成在第一绝缘隔离部分的表面；第二金属层，形成在第二绝缘隔离部分的表面。其中，沟道掺杂区、漏极掺杂区、源极掺杂区、绝缘隔离层、第一金属层和第二金属层可以组成晶体管。这样，在半导体结构中，在漏极掺杂区的附近形成第二金属层，第二金属层能够降低漏极掺杂区到沟道掺杂区的杂质分布的浓度梯度，降低漏极掺杂区附近的载流子数量，从而有效降低沟道掺杂区的电场强度，在晶体管断开的情况下，减小晶体管的漏电流，从而减小晶体管的关断电流，抑制由于BTBT导致的GIDL效应；另外，在晶体管开启时，栅压会增加载流子量，降低电阻，还能够增加晶体管的开启电流。
本公开的另一实施例中，参见图16，其示出了本公开实施例提供的一种半导体结构的制备方法的流程示意图。如图16所示，该方法可以包括：
S1001、提供衬底。
S1002、对衬底进行掺杂，于衬底中形成沟道掺杂区、漏极掺杂区和源极掺杂区，且漏极掺杂区和源极掺杂区形成在沟道掺杂区的两侧。
需要说明的是，首先提供一衬底，且衬底中形成有多个有源区，对于3D半导体结构而言，多个有源区可以呈空间阵列排布。然后对有源区进行掺杂，以形成多个掺杂区。具体地，图17为形成沟道掺杂区301、漏极掺杂区302和源极掺杂区303后所得的结构示意图，在图17中，仅示出了有源区部分。
如图17所示，漏极掺杂区302和源极掺杂区303分别位于沟道掺杂区301的两侧。另外，这三个掺杂区可以为无结型晶体管的三个掺杂区，因此，在一些实施例中，沟道掺杂区301、漏极掺杂区302以及源极掺杂区303的掺杂离子类型相同；例如，三个掺杂区的掺杂离子类型可以均为N型离子掺杂或者P型离子掺杂。
在一些实施例中，如图17所示，沟道掺杂区301可以为轻掺杂区(N-)，漏极掺杂区302和源极掺杂区303为重掺杂区(N+)。另外，漏极掺杂区302和源极掺杂区303还可以如前述图7至图11所示，漏极掺杂区302包括第一子掺杂区3021和第二子掺杂区3022，和/或，源极掺杂区303包括第三子掺杂区3031和第四子掺杂区3032。这时候，只需要改变掺杂浓度即可。
S1003、形成绝缘隔离层。
其中，绝缘隔离层包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离部分形成在沟道掺杂区的表面，第二绝缘隔离部分形成在漏极掺杂区的部分表面。
需要说明的是，图18为形成绝缘隔离层304后所得结构示意图。如图18所示，在沟道掺杂区301的表面以及漏极掺杂区302的部分表面形成绝缘隔离层304，将形成在沟道掺杂区301的表面的绝缘隔离层304记作第一绝缘隔离 部分，将形成在漏极掺杂区302的部分表面的绝缘隔离层304记作第二绝缘隔离部分。且第二绝缘隔离部分的长度可以为漏极掺杂区302或者源极掺杂区303的长度的五分之一至二分之一。
S1004、于第一绝缘隔离部分的表面形成第一金属层。
S1005、于第二绝缘隔离部分的表面形成第二金属层。
在第一绝缘隔离部分和第二绝缘隔离部分的表面分别形成第一金属层和第二金属层，从而得到无结型晶体管。
在一些实施例中，于第一绝缘隔离部分的表面形成第一金属层，可以包括：
于第二绝缘隔离部分的表面形成掩膜层；
以掩膜层为掩膜，于第一绝缘隔离部分的表面形成第一金属层；
去除掩膜层。
需要说明的是，图19为形成掩膜层316后所得的结构示意图。如图19所示，在形成第一金属层时，首先在第二绝缘隔离部分的表面形成掩膜层316。其中，掩膜层316的材料可以为光刻胶等。
然后以掩膜层316为掩膜，在第一绝缘隔离部分的表面形成第一金属层305，图20为形成第一金属层305后所得的结构示意图。
将掩膜层316去除，得到如图21所示的结构。如图21所示，在第一绝缘隔离部分的表面形成有第一金属层305，第二绝缘隔离部分暴露。在第二绝缘隔离部分的表面形成第二金属层306，得到如图22所示的结构。
在一些实施例中，第二金属层的功函数小于或者等于第一金属层的功函数，且第二金属层的功函数大于预设功函数阈值。
需要说明的是，第二金属层306用于调节沟道靠近漏极部分的杂质分布，降低漏极到沟道的杂质分布的浓度梯度，能够有效降低沟道电场。第二金属层306的功函数大于预设功函数阈值并小于或者等于第一金属层305的功函数，其中，预设功函数阈值可以为4.6eV，以保证第二金属层306能够起到降低沟道电场的效果。
在一些实施例中，在于第二绝缘隔离部分的表面形成第二金属层时，该方法还可以包括：
于第一金属层的表面形成第三金属层，且第三金属层与第二金属层连接，第三金属层的材料与第二金属层的材料相同。
需要说明的是，图23为形成第三金属层307后所得的结构示意图，这时候，能够形成如前述图7所示的半导体结构，第二金属层305和第三金属层307可以共同作用，实现降低GIDL效应。
进一步地，在一些实施例中，该方法还可以包括：
形成位线和电容；其中，位线与漏极掺杂区的远离沟道掺杂区的一侧连接；电容与源极掺杂区的远离沟道掺杂区的一侧连接。
需要说明的是，形成电容和位线后所得的结构可以参照前述图5或者图7所示。另外，本公开实施例仅以形成图5或者图7所示的半导体结构为例对半导体结构的制备方法进行说明，基于相似的方法，还可以形成前述图8至图11任一项所示的半导体结构，这里不再赘述。
对于本公开实施例未披露的细节，可以参照前述实施例的描述而理解。
本公开实施例提供了一种半导体结构的制备方法，利用该方法制得的半导体结构中，在漏极掺杂区的附近形成第二金属层，第二金属层能够降低漏极掺杂区到沟道掺杂区的杂质分布的浓度梯度，降低漏极掺杂区附近的载流子数量，从而有效降低沟道掺杂区的电场强度，抑制由于带-带隧穿效应导致的栅诱导漏极泄露电流。
本公开的再一实施例中，参见图24，其示出了本公开实施例提供的一种半导体存储器400的组成结构示意图。如图24所示，该半导体存储器400包括前述实施例任一项所述的半导体结构300。
其中，该半导体存储器400可以包括3D DRAM。
对于该半导体存储器400而言，由于其包括前述实施例所述的半导体结构300，从而能够有效抑制由于带-带隧穿效应导致的栅诱导漏极泄露电流。
以上所述，仅为本公开的较佳实施例，并非用于限定本公开的保护范围。
需要说明的是，在本公开中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本公开所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本公开所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种半导体结构、半导体结构的制备方法和半导体存储器，该半导体结构包括：沟道掺杂区；形成在沟道掺杂区两侧的漏极掺杂区和源极掺杂区；绝缘隔离层，包括第一绝缘隔离部分和第二绝缘隔离部分，第一绝缘隔离部分形成在沟道掺杂区的表面，第二绝缘隔离部分形成在漏极掺杂区的部分表面；第一金属层，形成在第一绝缘隔离部分的表面；第二金属层， 形成在第二绝缘隔离部分的表面。这样，在半导体结构中，第二金属层能够降低漏极掺杂区到沟道掺杂区的杂质分布的浓度梯度，降低漏极掺杂区附近的载流子数量，从而有效降低沟道掺杂区的电场强度，抑制由于带-带隧穿效应导致的栅诱导漏极泄露电流。

Claims (20)

  1. 一种半导体结构(300)，所述半导体结构(300)包括：
    沟道掺杂区(301)；
    形成在所述沟道掺杂区(301)两侧的漏极掺杂区(302)和源极掺杂区(303)；
    绝缘隔离层(304)，包括第一绝缘隔离部分和第二绝缘隔离部分，所述第一绝缘隔离部分形成在所述沟道掺杂区(301)的表面，所述第二绝缘隔离部分形成在所述漏极掺杂区(302)的部分表面；
    第一金属层(305)，形成在所述第一绝缘隔离部分的表面；
    第二金属层(306)，形成在所述第二绝缘隔离部分的表面。
  2. 根据权利要求1所述的半导体结构(300)，其中，所述第二金属层(306)的功函数小于或者等于所述第一金属层(305)的功函数，且所述第二金属层(306)的功函数大于预设功函数阈值。
  3. 根据权利要求2所述的半导体结构(300)，其中，所述预设功函数阈值为4.6电子伏特。
  4. 根据权利要求1至3任一项所述的半导体结构(300)，其中，所述第一金属层(305)的材料包括下述至少之一：铱、镍、铂、钴。
  5. 根据权利要求1至4任一项所述的半导体结构(300)，其中，所述半导体结构(300)还包括第三金属层(307)，所述第三金属层(307)的材料与所述第二金属层(306)的材料相同；其中，
    所述第三金属层(307)形成在所述第一金属层(305)的表面，且所述第三金属层(307)与所述第二金属层(306)连接。
  6. 根据权利要求1至5任一项所述的半导体结构(300)，其中，所述沟道掺杂区(301)、所述漏极掺杂区(302)以及所述源极掺杂区(303)的掺杂离子类型相同。
  7. 根据权利要求1至6任一项所述的半导体结构(300)，其中，
    所述沟道掺杂区(301)为轻掺杂区；
    所述漏极掺杂区(302)和所述源极掺杂区(303)均为重掺杂区；
    其中，所述重掺杂区的掺杂离子浓度大于所述轻掺杂区的掺杂离子浓度。
  8. 根据权利要求1至7任一项所述的半导体结构(300)，其中，
    所述漏极掺杂区(302)包括第一子掺杂区(3021)和第二子掺杂区(3022)，且所述第一子掺杂区(3021)位于所述沟道掺杂区(301)与所述第二子掺杂区(3022)之间；其中，所述第二绝缘隔离部分形成在所述第一子掺杂区(3021)的表面。
  9. 根据权利要求8所述的半导体结构(300)，其中，
    所述绝缘隔离层(304)还包括第三绝缘隔离部分，所述第三绝缘隔离部分形成在所述源极掺杂区(303)的部分表面；
    所述半导体结构(300)还包括第四金属层(308)，所述第四金属层(308)形成在所述第三绝缘隔离部分的表面。
  10. 根据权利要求9所述的半导体结构(300)，其中，所述源极掺杂区(303)包括第三子掺杂区(3031)和第四子掺杂区(3032)，且所述第三子掺杂区(3031)位于所述沟道掺杂区(301)与所述第四子掺杂区(3032)之间，所述第三绝缘隔离部分形成在所述第三子掺杂区(3031)的表面；其中，
    所述沟道掺杂区(301)为轻掺杂区；
    所述第一子掺杂区(3021)和所述第三子掺杂区(3031)均为中掺杂区；
    所述第二子掺杂区(3022)和所述第四子掺杂区(3032)均为重掺杂区；
    其中，所述中掺杂区的掺杂离子浓度大于所述轻掺杂区的掺杂离子浓度，且所述中掺杂区的掺杂离子浓度小于所述重掺杂区的掺杂离子浓度。
  11. 根据权利要求9或10所述的半导体结构(300)，其中，所述半导体结构(300)还包括第五金属层(309)；其中，
    所述第五金属层(309)形成在所述第一金属层(305)的表面，且所述第五金属层(309)的两端与所述第二金属层(306)和所述第四金属层(308)分别连接。
  12. 根据权利要求1至11任一项所述的半导体结构(300)，其中，所述半导体结构(300)还包括位线(310)和电容(311)；其中，
    所述位线(310)与所述源极掺杂区(303)的远离所述沟道掺杂区(301)的一侧连接；
    所述电容(311)与所述漏极掺杂区(302)的远离所述沟道掺杂区(301)的一侧连接。
  13. 根据权利要求1至12任一项所述的半导体结构(300)，其中，所述半导体结构(300)还包括控制引线(313)；其中，
    所述第一金属层(305)和所述第二金属层(306)连接；
    所述控制引线(313)的一端与所述第一金属层(305)和/或所述第二金属层(306)连接，所述控制引线(313)的另一端与控制端连接。
  14. 根据权利要求1至13任一项所述的半导体结构(300)，其中，所述半导体结构还包括金属隔离层(312)、第一控制引线(313a)和第二控制引线(313b)；其中，
    所述金属隔离层(312)形成于所述第一金属层(305)和所述第二金属层(306)之间，用于将所述第一金属层(305)和所述第二金属层(306)进行绝缘隔离；
    所述第一控制引线(313a)的一端与所述第一金属层(305)连接，所述第一控制引线(313a)的另一端与第一控制端连接；
    所述第二控制引线(313b)的一端与所述第二金属层(306)连接，所述第二控制引线(313b)的另一端与第二控制端连接。
  15. 一种半导体结构(300)的制备方法，所述方法包括：
    提供衬底；
    对所述衬底进行掺杂，于所述衬底中形成沟道掺杂区(301)、漏极掺杂区(302)和源极掺杂区(303)，且所述漏极掺杂区(302)和所述源极掺杂区(303)形成在所述沟道掺杂区(301)的两侧；
    形成绝缘隔离层(304)，所述绝缘隔离层(304)包括第一绝缘隔离部分和第二绝缘隔离部分，所述第一绝缘隔离部分形成在所述沟道掺杂区(301)的表面，所述第二绝缘隔离部分形成在所述漏极掺杂区(302)的部分表面；
    于所述第一绝缘隔离部分的表面形成第一金属层(305)；
    于所述第二绝缘隔离部分的表面形成第二金属层(306)。
  16. 根据权利要求15所述的方法，其中，所述于所述第一绝缘隔离部分的表面形成第一金属层(305)，包括：
    于所述第二绝缘隔离部分的表面形成掩膜层；
    以所述掩膜层为掩膜，于所述第一绝缘隔离部分的表面形成第一金属层(305)；
    去除所述掩膜层。
  17. 根据权利要求15或16所述的方法，其中，在所述于所述第二绝缘隔离部分的表面形成第二金属层(306)时，所述方法还包括：
    于所述第一金属层(305)的表面形成第三金属层(307)，且所述第三金属层(307)与所述第二金属层(306)连接；其中，所述第三金属层(307)的材料与所述第二金属层(306)的材料相同。
  18. 根据权利要求15至17任一项所述的方法，其中，所述方法还包括：
    形成位线(310)和电容(311)；其中，所述位线(310)与所述漏极掺杂区(302)的远离所述沟道掺杂区(301)的一侧连接；所述电容(311)与所述源极掺杂区(303)的远离所述沟道掺杂区(301)的一侧连接。
  19. 根据权利要求15至18任一项所述的方法，其中，
    所述第二金属层(306)的功函数小于或者等于所述第一金属层(305)的功函数，且所述第二金属层(306)的功函数大于预设功函数阈值；其中，所述预设功函数阈值为4.6电子伏特。
  20. 一种半导体存储器(400)，所述半导体存储器(400)包括如权利要求1至14任一项所述的半导体结构(300)。
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