WO2024031818A1 - 半导体结构及其形成方法、存储器 - Google Patents

半导体结构及其形成方法、存储器 Download PDF

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Publication number
WO2024031818A1
WO2024031818A1 PCT/CN2022/124203 CN2022124203W WO2024031818A1 WO 2024031818 A1 WO2024031818 A1 WO 2024031818A1 CN 2022124203 W CN2022124203 W CN 2022124203W WO 2024031818 A1 WO2024031818 A1 WO 2024031818A1
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WIPO (PCT)
Prior art keywords
conductive layer
word line
layer
substrate
peripheral
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PCT/CN2022/124203
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English (en)
French (fr)
Inventor
李冉
臧标
林志成
段蕾蕾
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/511,914 priority Critical patent/US20240090207A1/en
Publication of WO2024031818A1 publication Critical patent/WO2024031818A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor structure, a method of forming the same, and a memory.
  • DRAM Dynamic Random Access Memory
  • mobile devices such as mobile phones and tablet computers due to its advantages such as small size, high degree of integration, and fast transmission speed.
  • the word line structure plays a vital role in the electrical performance of the device.
  • word line contact plugs In DRAM, it is usually necessary to electrically lead out the word line structure through word line contact plugs. In this process, the word line contact plugs need to penetrate the second conductive layer on the surface of the word line structure to connect to the word line structure. However, during etching The substrate is easily damaged during the process of forming the second conductive layer, and the product yield is low.
  • the present disclosure provides a semiconductor structure, a method for forming the same, and a memory, which can reduce process difficulty and improve product yield.
  • a semiconductor structure including:
  • Substrate including array area and peripheral area
  • a word line structure including a first conductive layer located inside the substrate, the first conductive layer penetrating the array area along a first direction and extending to the peripheral area; in a direction perpendicular to the substrate , the height of the first conductive layer located on the surface of the peripheral area is higher than the height of the first conductive layer located on the surface of the array area.
  • the semiconductor structure further includes:
  • a word line contact plug is located in the peripheral area, and a bottom surface of the word line contact plug is connected to the first conductive layer.
  • the word line structure further includes:
  • a second conductive layer, the second conductive layer is located on top of the first conductive layer, and the orthographic projection of the second conductive layer on the substrate is consistent with the word line contact plug on the substrate. Orthographic projection has no overlap.
  • the first distance is smaller than the first distance.
  • the conductive layer is located along the length of the peripheral region in the first direction.
  • a surface of the first conductive layer located in the peripheral region is flush with a surface of the second conductive layer.
  • the material of the first conductive layer is a metal material
  • the material of the second conductive layer is a semiconductor material
  • the semiconductor structure further includes:
  • a peripheral contact plug is located in the peripheral area and is electrically connected to the word line contact plug, and in a direction perpendicular to the substrate, the top surface of the peripheral contact plug is in contact with the word line
  • the top surfaces of the plugs are the same height.
  • the word line structure further includes an inter-gate dielectric layer, and the inter-gate dielectric layer conformally covers at least the first conductive layer and the second conductive layer. side wall surface.
  • a method for forming a semiconductor structure including:
  • the substrate including an array region and a peripheral region
  • a plurality of word line structures are formed in the substrate.
  • the word line structures include a first conductive layer located inside the substrate.
  • the first conductive layer penetrates the array area along a first direction and extends to The peripheral area; in a direction perpendicular to the substrate, the height of the first conductive layer on the surface of the peripheral area is higher than the height of the first conductive layer on the surface of the array area.
  • the forming method further includes:
  • a word line contact plug is formed in the peripheral area, and a bottom surface of the word line contact plug is connected to the first conductive layer.
  • the forming method further includes:
  • a second conductive layer is formed on the upper part of the first conductive layer, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the word line contact plug on the substrate. .
  • the first distance is smaller than the first distance.
  • the conductive layer is located along the length of the peripheral region in the first direction.
  • a surface of the first conductive layer located in the peripheral region is flush with a surface of the second conductive layer.
  • the material of the first conductive layer is a metal material
  • the material of the second conductive layer is a semiconductor material
  • the forming method further includes:
  • a peripheral contact plug is formed in the peripheral area, the peripheral contact plug is electrically connected to the word line contact plug, and in a direction perpendicular to the substrate, a top surface of the peripheral contact plug is connected to The top surfaces of the word line contact plugs have the same height.
  • the word line structure further includes an inter-gate dielectric layer, and the inter-gate dielectric layer conformally covers at least the first conductive layer and the second conductive layer. side wall surface.
  • a plurality of word line structures are formed in the substrate, including:
  • the second conductive layer is formed on the surface of the first conductive layer.
  • forming the first conductive layer in the word line trench having the inter-gate dielectric layer includes:
  • a conductive material layer is formed on the surface of the substrate, and the conductive material layer fills the word line trench with the inter-gate dielectric layer;
  • a second photoresist layer is formed on the surface of the conductive material layer, and the orthographic projection of the second photoresist layer on the substrate coincides with the peripheral area;
  • the remaining conductive material layer is etched until the surface of the conductive material layer located in the peripheral area is lower than the surface of the substrate and higher than the surface of the conductive material layer located in the array area.
  • forming the second conductive layer on the surface of the first conductive layer includes:
  • a memory including the semiconductor structure described in any one of the above.
  • the subsequently formed second conductive layer can be formed on the surface located in the array area.
  • the surface of the first conductive layer in the array area there is no need to form a second conductive layer in the peripheral area at this time.
  • the via holes used to accommodate the word line contact plugs do not need to be Through the second conductive layer, there is no need to use an etching solution or etching gas with a relatively large etching rate for the second conductive layer, which can avoid damage to the substrate during the etching of the second conductive layer, and can also avoid The etching damage extends to the interior of the array area, reducing the source of defects in the substrate and improving product yield.
  • Figure 1 is a schematic diagram of a word line structure in the related art
  • Figure 2 is a top view of a semiconductor structure in an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view of the semiconductor structure in an embodiment of the present disclosure cut along the bb' direction in Figure 2;
  • Figure 4 is a top view of a substrate in an embodiment of the present disclosure.
  • Figure 5 is a cross-sectional view cut along the aa' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 6 is a cross-sectional view cut along the bb' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 7 is a cross-sectional view of the first conductive layer cut along the aa' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 8 is a cross-sectional view of the first conductive layer cut along the bb' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 9 is a cross-sectional view of the insulating layer cut along the aa' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 10 is a cross-sectional view of the insulating layer cut along the bb' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 11 is a cross-sectional view of the word line contact plug cut along the aa' direction in Figure 4 in an embodiment of the present disclosure
  • Figure 12 is a cross-sectional view of the word line contact plug cut along the bb' direction in Figure 4 in an embodiment of the present disclosure
  • FIG. 13 is a cross-sectional view of a peripheral contact plug in the peripheral region in an embodiment of the present disclosure
  • Figure 14 is a flow chart of a method of forming a semiconductor structure in an embodiment of the present disclosure.
  • Figure 15 is a cross-sectional view cut along the aa' direction in Figure 4 after step S2301 is completed in the embodiment of the present disclosure
  • Figure 16 is a cross-sectional view cut along the bb’ direction in Figure 4 after step S2301 is completed in the embodiment of the present disclosure
  • Figure 17 is a cross-sectional view cut along the aa' direction in Figure 4 after step S2302 is completed in the embodiment of the present disclosure
  • Figure 18 is a cross-sectional view cut along the bb' direction in Figure 4 after step S2302 is completed in the embodiment of the present disclosure
  • Figure 19 is a cross-sectional view cut along the bb' direction in Figure 4 after step S2303 is completed in the embodiment of the present disclosure
  • Figure 20 is a cross-sectional view cut along the aa' direction in Figure 4 after step S320 is completed in the embodiment of the present disclosure
  • Figure 21 is a cross-sectional view cut along the bb’ direction in Figure 4 after step S320 is completed in the embodiment of the present disclosure
  • Figure 22 is a cross-sectional view cut along the aa' direction in Figure 4 after step S1401 is completed in the embodiment of the present disclosure
  • Figure 23 is a cross-sectional view cut along the bb’ direction in Figure 4 after step S1401 is completed in the embodiment of the present disclosure
  • 24 is a cross-sectional view of the second contact hole in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the word line structure is one of the core components of dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • the word line structure is usually buried inside the substrate 100.
  • the word line The structure generally includes a first conductive layer 200 and a second conductive layer 300 arranged in a stack, and the word line structure is electrically led out through leads connected to the word line structure.
  • the second conductive layer 300 In the process of forming the leads, in order to reduce the resistance, when forming the via holes 400 to accommodate the leads, the second conductive layer 300 needs to be carved through to expose the first conductive layer 200 underneath it.
  • the second conductive layer 300 The physical and chemical properties of the material are usually similar to the material of the active area in the substrate 100. During the process of etching the second conductive layer 300, the active area is easily damaged, and the product yield is low.
  • FIG. 2 shows a top view of the semiconductor structure in the embodiment of the present disclosure.
  • FIG. 3 shows a cross-sectional view of the semiconductor structure in the embodiment of the present disclosure along the bb' direction in FIG. 2 ;
  • the semiconductor structure may include a substrate 1 and a word line structure 2, where:
  • the substrate 1 may include an array area 101 and a peripheral area 102;
  • the word line structure 2 may include a first conductive layer 21 located inside the substrate 1.
  • the first conductive layer 21 penetrates the array area 101 along the first direction A and extends to the peripheral area 102; in the direction perpendicular to the substrate 1, the first conductive layer 21
  • the height of the conductive layer 21 on the surface of the peripheral area 102 is higher than the height of the first conductive layer 21 on the surface of the array area 102 .
  • the subsequently formed second conductive layer 22 can be formed on the surface of the array area.
  • the surface of the first conductive layer 21 in the region 101 does not need to form the second conductive layer 22 in the peripheral region 102 at this time, and is used to accommodate the word line contact plugs when the word line contact plugs connected to the word line structure 2 are subsequently formed.
  • the via hole does not need to pass through the second conductive layer 22, and there is no need to use an etching solution or etching gas with a high etching rate for the second conductive layer 22 to etch, which can avoid damaging the substrate during the process of etching the second conductive layer 22. 1 can also prevent the etching damage from extending into the array area 101, reduce the source of defects in the substrate 1, and improve the product yield. And during the above process, since there is no second conductive layer 22 on the surface of the word line structure 2 in the peripheral area 102, there is no need to etch the second conductive layer 22 in the subsequent process of forming via holes, which can reduce the number of etched layers, thereby simplifying the process.
  • the process of etching the second conductive layer 22 is reduced, thereby reducing the manufacturing cost; at the same time, due to the increase in the height of the first conductive layer 21, the via hole etching height is reduced, which can reduce the process difficulty.
  • the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but It is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specifically limited here.
  • the substrate 1 can be a silicon substrate with a shallow trench isolation structure 11 formed inside it.
  • the shallow trench isolation structure 11 can be formed by forming a trench in the substrate 1 After the groove is formed, a layer of isolation material is filled in the groove to form.
  • the material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, and is not specifically limited here.
  • the cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs.
  • the shallow trench isolation structure 11 can separate several active areas 12 on the substrate 1 .
  • the substrate 1 may include an array area 101 and a peripheral area 102 .
  • the array area 101 and the peripheral area 102 may be adjacently distributed, and the peripheral area 102 may be located at one side of the array area 101 .
  • the array area 101 can be used to form a capacitor array, a transistor array, a word line structure 2 and a bit line structure connecting transistors and capacitors, and the peripheral area 102 can be used to form word line contact plugs.
  • the word line contact plug can connect the word line driver, sense amplifier, row decoder and column decoder located in the peripheral area 102 as well as the special function control circuit.
  • the control circuit can realize the control of the transistor and capacitor by controlling the word line and bit line. Storage and reading functions.
  • the array area 101 can be a circular area, a rectangular area or an irregular pattern area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area 102 may be an annular area and may surround the outer periphery of the array area 101. It may be a circular annular area, a rectangular annular area or annular areas of other shapes, which are not listed here.
  • Each active area 12 can be located in the array area 101 , and each active area 12 can be distributed in an array in the array area 101 .
  • the boundary between the peripheral area 102 and the array area 101 is not clearly divided.
  • the boundary between the peripheral area 102 and the array area 101 is distinguished by the endpoint connection lines of each second conductive layer 22.
  • the peripheral area There is a certain distance between the edge of 102 and the side of the active area 12, and the area within this distance can belong to the array area 101.
  • a plurality of word line trenches 201 extending along the first direction A may be provided in the substrate 1 , and each word line trench 201 They may be distributed at intervals along the second direction B.
  • the word line trench 201 may be a trench-like structure formed by an inward depression on the surface of the substrate 1 , and its bottom end is connected to the substrate 1 .
  • the word line trench 201 can penetrate the array area 101 and the peripheral area 102 , and the portion of the word line trench 201 located in the array area 101 can penetrate the plurality of active areas 12 .
  • the first direction A may intersect the second direction B.
  • the first direction A and the second direction B may be perpendicular to each other.
  • verticality can be absolutely vertical or approximately vertical, and there will inevitably be deviations during the manufacturing process.
  • angle deviations may occur due to limitations in the manufacturing process, such that the first direction A and the second direction There is a certain deviation in the angle between B. As long as the angle deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered to be perpendicular.
  • the preset range may be 10°, that is, when the angle between the first direction A and the second direction B is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction A and the second direction B are equal to or greater than 80°.
  • the second direction B is vertical.
  • word line structures 2 can be formed in each word line trench 201 , that is, multiple word line structures 2 can be formed in the substrate 1 , and each word line structure 2 can be formed along the The first direction A extends, and the plurality of word line structures 2 may be spaced apart along the second direction B.
  • the word line structure 2 can penetrate the array area 101 and the peripheral area 102.
  • each word line structure 2 can extend from the peripheral area 102 to the array area 101, and it is located between the array area 101 and the array area 101.
  • a portion may penetrate multiple active areas 12 .
  • the word line structure 2 may include a first conductive layer 21 , and the first conductive layer 21 may penetrate the array area 101 and extend to the peripheral area 102 .
  • the height of the surface of the layer 21 in the peripheral region 102 may be higher than the height of the first conductive layer 21 in the array region 101 to facilitate subsequent formation of word line contact plugs in the peripheral region 102 .
  • the material of the first conductive layer 21 may be a metal material.
  • the material may be one of tungsten, titanium, and tantalum.
  • the word line structure 2 may further include a second conductive layer 22 , and the second conductive layer 22 may be located on top of the first conductive layer 21 . And in contact with the first conductive layer 21 .
  • the material of the second conductive layer 22 may be a semiconductor material, and the semiconductor material may be a material with a lower work function.
  • the material thereof may be polysilicon.
  • a second conductive layer 22 with a lower work function can be provided on the surface of the first conductive layer 21 to reduce the gate-induced drain leakage current (Gate- Induced Drain Leakage, GIDL).
  • the word line structure 2 may further include an inter-gate dielectric layer 23 , and the inter-gate dielectric layer 23 may at least conformally cover the first conductive layer. 21 and the surface of the sidewalls of the second conductive layer 22 , which may be a thin film layer formed on the surfaces of the sidewalls of the first conductive layer 21 and the second conductive layer 22 .
  • a conformally attached inter-gate dielectric layer 23 can be formed on the sidewalls and surfaces of each word line trench 201 .
  • the material of 23 may include silicon oxide, silicon nitride, silicon oxynitride, etc., or may be a combination of the aforementioned materials, and its thickness may be 1 nm to 9 nm. For example, it may be 1 nm, 2 nm, 4 nm, 6 nm, 8 nm or 9nm, of course, can also be other thicknesses, which will not be listed here.
  • the conformally attached inter-gate dielectric layer 23 can be formed on the sidewalls and bottom of each word line trench 201 through chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation or thermal oxidation.
  • the inter-gate dielectric layer 23 can also be formed by other methods, and is not specifically limited here.
  • the inter-gate dielectric layer 23 can completely cover the top surface of the substrate 1, and then the inter-gate dielectric layer 23 on the surface of the substrate 1 can be removed, leaving only the inter-gate dielectric layer 23 on each side.
  • a thermal oxidation process can be used to treat the surface of the inter-gate dielectric layer 23 to improve the density of the film layer of the inter-gate dielectric layer 23, thereby reducing leakage current and improving gate control capability. It can also enhance the blocking effect of the inter-gate dielectric layer 23 on the impurities in the substrate 1, prevent the impurities in the substrate 1 from diffusing into the word line trench 201, and improve the structural stability.
  • a diffusion barrier layer may be formed on the surface of the inter-gate dielectric layer 23 to prevent metal materials from diffusing to the substrate 1 and increasing the risk of leakage current.
  • the diffusion barrier layer can be conformally attached to the surface of the inter-gate dielectric layer 23 , that is, the inter-gate dielectric layer 23 can be located between the diffusion barrier layer and the inner wall of the word line trench 201 , and the material of the diffusion barrier layer can be titanium nitride. , its thickness can be 0.5nm ⁇ 2nm, for example, it can be 0.5nm, 1nm, 1.5nm or 2nm.
  • a diffusion barrier layer can be formed on the surface of the inter-gate dielectric layer 23 through processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The formation process of the diffusion barrier layer is not particularly limited here.
  • chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation can be used to form the word lines with the inter-gate dielectric layer 23
  • the trench 201 is filled with conductive material to form the first conductive layer 21 in the word line trench 201. It should be noted that in the direction perpendicular to the substrate 1, the first conductive layer 21 is located in the portion of the peripheral area 102. The height of the surface is higher than the height of the surface of its portion located in the array area 101 .
  • the first conductive layer 21 can be formed on the surface of the diffusion barrier layer, that is, the first conductive layer 21 can be formed on the surface where the inter-gate dielectric layer 23 and the diffusion barrier layer are formed.
  • the word line trench 201 is filled with conductive material to form a first conductive layer 21 in the word line trench 201 .
  • the second conductive layer 22 can be formed on the surface of the first conductive layer 21 using physical vapor deposition, chemical vapor deposition, atomic layer deposition, vacuum evaporation or magnetron sputtering.
  • the second conductive layer 22 can cover the array area.
  • the orthographic projection of the second conductive layer 22 on the substrate 1 does not overlap with the peripheral area 102, and the orthographic projection of the second conductive layer 22 on the substrate 1 can overlap with the array area 101 The boundaries overlap.
  • the thickness of the second conductive layer 22 may be the same as that of the first conductive layer 21 of the array region 101 and the first conductive layer 21 of the peripheral region 102 .
  • the height difference is equal, that is, the surface of the second conductive layer 22 can be flush with the surface of the first conductive layer 21 in the peripheral area 102, and the second conductive layer 22 only covers the portion of the first conductive layer 21 located in the array area 101. surface.
  • the proportion of the first conductive layer 21 in the word line structure 2 in the present disclosure increases. Since the material of the first conductive layer 21 is a metal material, the proportion of the metal material in the word line structure 2 can be increased, which is helpful to Reduce the resistance of word line structure 2.
  • the semiconductor structure of the present disclosure may further include an insulating layer 5 , and the insulating layer 5 may be a thin film formed on the top of the word line structure 2 , or It may be a coating formed on the top of the word line structure 2, and the form of the insulating layer 5 is not particularly limited here.
  • the orthographic projection of the insulating layer 5 on the substrate 1 can cover the orthographic projection of each word line structure 2 on the substrate 1 .
  • the surface of the word line structure 2 can be insulated and protected through the insulating layer 5 to avoid surface damage to the word line structure 2; at the same time, the word line structure 2 can also be isolated from other structures through the insulating layer 5 to prevent the word line structure 2 from being damaged. Coupling or short circuiting with other structures can improve product yield.
  • the insulating layer 5 may simultaneously cover the surface of the second conductive layer 22 and the surface of the first conductive layer 21 located on the surface of the peripheral region 102 , that is, the insulating layer 5 may cover the first conductive layer 21 and
  • the second conductive layer 22 together constitutes the surface of the structure.
  • the first conductive layer 21 and the second conductive layer 22 can be insulated and protected through the insulating layer 5 to avoid surface damage of the first conductive layer 21 and the second conductive layer 22; at the same time, the first conductive layer 21 and the second conductive layer 22 can also be insulated through the insulating layer 5.
  • the layer 21 and the second conductive layer 22 are isolated from other structures to avoid coupling or short circuit between the first conductive layer 21 and the second conductive layer 22 and other structures, thereby improving product yield.
  • the material of the insulating layer 5 can be silicon nitride or other insulating materials, and can be formed on the first conductive layer through chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering.
  • the insulating layer 5 is formed on the surface of the structure formed by the layer 21 and the second conductive layer 22.
  • the insulating layer 5 can also be formed by other methods, and the formation method of the insulating layer 5 is not particularly limited here.
  • the semiconductor structure of the present disclosure may further include word line contact plugs 6 , and the word line contact plugs 6 may be formed in the peripheral region 102 , that is, , the orthographic projection of the second conductive layer 22 on the substrate 1 does not overlap with the orthographic projection of the word line contact plug 6 on the substrate 1 . And the second conductive layer 22 may be spaced apart from the word line contact plugs 6.
  • an end of the second conductive layer 22 close to the peripheral region 102 may have a first distance from the word line contact plug 6, and the first distance may be less than
  • the length of the first conductive layer 21 located in the peripheral area 102 in the first direction A helps to isolate the word line conductive plug 6 and the portion of the first conductive layer 21 located in the peripheral area 102 from the second conductive layer 22 to avoid The formation of the word line conductive plug 6 causes damage to the second conductive layer 22 .
  • the bottom surface of the word line contact plug 6 can be in contact with the surface of the first conductive layer 21 located in the peripheral area 102 , so that the word line structure 2 can be electrically drawn out through the word line contact plug 6 , and then the word line structure 2 can be electrically led out.
  • the data signals in the word line structure 2 can be brought out through the word line contact plugs 6 .
  • one side of the word line contact plug 6 is connected to the word line structure 2, and the other side can be connected to the word line driver, sense amplifier, row decoder and column structure through the peripheral contact plug 7.
  • the decoder is connected to a control circuit with special functions. The control circuit transmits current through the word line contact plug 6 to control the word line structure 2 and the bit line structure to realize the storage and reading functions of the transistor and the capacitor.
  • the word line contact plug 6 may penetrate the insulating layer 5 in a direction perpendicular to the substrate 1 , that is, the word line contact plug 6 may be buried in the insulating layer 5 Inside, the word line contact plug 6 can be insulated and protected through the insulating layer 5. In this process, coupling or short circuit between the word line contact plug 6 and other surrounding structures can be avoided, which can further improve the product yield.
  • the semiconductor structure of the present disclosure may further include a peripheral contact plug 7 , the peripheral contact plug 7 may be located in the peripheral area 102 , and one end of the peripheral contact plug 7 It can be connected to the source and drain electrode 110 of the transistor in the peripheral area 102; in the direction perpendicular to the substrate 1, the peripheral contact plug 7 can penetrate the insulating layer 5, and can be spaced apart from the word line contact plug 6.
  • the peripheral contact The top surface of plug 7 may be at the same height as the top surface of word line contact plug 6 .
  • the peripheral contact plug 7 can be electrically connected to the word line contact plug 6 through a connection line located on the surface of the insulating layer 5 , thereby enabling the peripheral circuit to control each component in the array area 101 .
  • Embodiments of the present disclosure also provide a method of forming a semiconductor structure.
  • Figure 14 shows a flow chart of the method of forming a semiconductor structure of the present disclosure. Referring to Figure 14, the forming method of the present disclosure may include step S110 and step S120. ,in:
  • Step S110 providing a substrate, the substrate including an array area and a peripheral area;
  • Step S120 Form multiple word line structures in the substrate.
  • the word line structures include a first conductive layer located inside the substrate.
  • the first conductive layer penetrates the array area along a first direction and Extending to the peripheral area; in a direction perpendicular to the substrate, the height of the first conductive layer on the surface of the peripheral area is higher than the height of the first conductive layer on the surface of the array area.
  • the subsequently formed second conductive layer 22 can be formed On the surface of the first conductive layer 21 located in the array area 101, there is no need to form the second conductive layer 22 in the peripheral area 102 at this time, which is used to accommodate the words when the word line contact plugs 6 connected to the word line structure 2 are subsequently formed.
  • the via hole of the line contact plug 6 does not need to pass through the second conductive layer 22 , and there is no need to use an etching solution or etching gas with a high etching rate for the second conductive layer 22 to etch, thereby avoiding the need to etch the second conductive layer 22 during etching. Damage to the substrate 1 caused during the process can also prevent the etching damage from extending into the array area 101, thereby reducing the source of defects in the substrate 1 and improving product yield.
  • a substrate is provided, and the substrate includes an array area and a peripheral area.
  • the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but It is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specifically limited here.
  • the substrate 1 can be a silicon substrate with a shallow trench isolation structure 11 formed inside it.
  • the shallow trench isolation structure 11 can be formed by forming a trench in the substrate 1 After the groove is formed, a layer of isolation material is filled in the groove to form.
  • the material of the shallow trench isolation structure 11 may include silicon nitride or silicon oxide, and is not specifically limited here.
  • the cross-sectional shape of the shallow trench isolation structure 11 can be set according to actual needs.
  • the shallow trench isolation structure 11 can separate several active areas 12 on the substrate 1 .
  • the substrate 1 may include an array area 101 and a peripheral area 102 .
  • the array area 101 and the peripheral area 102 may be adjacently distributed, and the peripheral area 102 may be located at one side of the array area 101 . side, it can also surround the periphery of the array area 101.
  • the array area 101 can be used to form a capacitor array, a transistor array, a word line structure 2 and a bit line structure connecting transistors and capacitors.
  • the peripheral area 102 can be used to form word lines connected to peripheral circuits. Wire contact plug 6.
  • Peripheral circuits can include word line drivers, sense amplifiers, row decoders and column decoders, and special function control circuits.
  • the peripheral circuits can realize the storage and reading functions of transistors and capacitors by controlling word lines and bit lines.
  • the array area 101 can be a circular area, a rectangular area or an irregular pattern area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area 102 may be an annular area and may surround the outer periphery of the array area 101. It may be a circular annular area, a rectangular annular area or annular areas of other shapes, which are not listed here.
  • Each active area 12 can be located in the array area 101 , and each active area 12 can be distributed in an array in the array area 101 .
  • peripheral area 102 there is no obvious division between the peripheral area 102 and the array area 101.
  • the boundary of the peripheral area 102 and the boundary of the array area 101 are distinguished by the endpoint connections of each second conductive layer 22.
  • the peripheral area There is a certain distance between the edge of 102 and the side of the active area 12, and the area within this distance can belong to the array area 101.
  • a plurality of word line structures are formed in the substrate.
  • the word line structures include a first conductive layer located inside the substrate.
  • the first conductive layer is along a first conductive layer.
  • One direction runs through the array area and extends to the peripheral area; in a direction perpendicular to the substrate, the height of the first conductive layer located on the surface of the peripheral area is higher than the height of the first conductive layer located on the surface of the peripheral area. The height of the surface of the array area.
  • the word line structure 2 may include a first conductive layer 21 , and the first conductive layer 21 may penetrate the array area 101 and extend to the peripheral area 102 , thereby making the first conductive layer 21 step-shaped to facilitate Subsequently, word line contact plugs 6 are formed in the peripheral area 102 .
  • the material of the first conductive layer 21 may be a metal material.
  • the material may be one of tungsten, titanium, and tantalum.
  • the word line structure 2 may further include a second conductive layer 22 , and the second conductive layer 22 may be located on top of the first conductive layer 21 . And in contact with the first conductive layer 21 .
  • the material of the second conductive layer 22 may be a semiconductor material, and the semiconductor material may be a material with a lower work function.
  • the material thereof may be polysilicon.
  • a second conductive layer 22 with a lower work function can be provided on the surface of the first conductive layer 21 to reduce the gate-induced drain leakage current (Gate- Induced Drain Leakage, GIDL).
  • the word line structure 2 may further include an inter-gate dielectric layer 23 , and the inter-gate dielectric layer 23 may at least conformally cover the first conductive layer. 21 and the surface of the sidewalls of the second conductive layer 22 , which may be a thin film layer formed on the surfaces of the sidewalls of the first conductive layer 21 and the second conductive layer 22 .
  • forming a plurality of word line structures 2 in the substrate 1 may include steps S210 to S240, wherein:
  • step S210 a plurality of word line trenches 201 are formed in the substrate 1, and the word line trenches 201 penetrate the array area 101 and the peripheral area 102.
  • each word line trench 201 may extend along the first direction A, and the plurality of word line trenches 201 may be spaced apart along the second direction B.
  • the word line trench 201 may be a trench-like structure formed by an inward depression on the surface of the substrate 1 , and its bottom end is connected to the substrate 1 .
  • the word line trench 201 can penetrate the array area 101 and the peripheral area 102 , and the portion of the word line trench 201 located in the array area 101 can penetrate the plurality of active areas 12 .
  • the first direction A may intersect the second direction B.
  • the first direction A and the second direction B may be perpendicular to each other.
  • verticality can be absolutely vertical or approximately vertical, and there will inevitably be deviations during the manufacturing process.
  • angle deviations may occur due to limitations in the manufacturing process, such that the first direction A and the second direction There is a certain deviation in the angle between B. As long as the angle deviation between the first direction A and the second direction B is within a preset range, the first direction A and the second direction B can be considered to be perpendicular.
  • the preset range may be 10°, that is, when the angle between the first direction A and the second direction B is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction A and the second direction B are equal to or greater than 80°.
  • the second direction B is vertical.
  • a plurality of word line trenches 201 are formed in the substrate 1, and the word line trenches 201 penetrate the array area 101 and the peripheral area 102 (ie, step S210). It includes steps S2101 to S2104, where:
  • Step S2101 Form a mask layer on the surface of the substrate 1.
  • a mask layer can be formed on the surface of the substrate 1 by chemical vapor deposition, physical vapor deposition, vacuum evaporation, magnetron sputtering, atomic layer deposition or other methods.
  • the mask layer can be multiple
  • the layer-by-layer structure may also be a single-layer structure, and the material may be at least one of polymer, SiO 2 , SiN, polysilicon, and SiCN. Of course, it may also be other materials, which are not listed here.
  • the mask layer may be multiple layers, which may include a polymer layer, an oxide layer and a hard mask layer, wherein the polymer layer may be formed on the surface of the substrate 1 and the oxide layer may be located on the hard mask layer. layer and the polymer layer.
  • a polymer layer can be formed on the surface of the substrate 1 through a chemical vapor deposition process, an oxide layer can be formed on the surface of the polymer layer through a vacuum evaporation process, and a hard mask layer can be formed on the surface of the oxide layer through an atomic layer deposition process.
  • Step S2102 Form a first photoresist layer on the surface of the mask layer.
  • the first photoresist layer can be formed on the surface of the mask layer facing away from the substrate 1 by spin coating or other methods.
  • the material of the first photoresist layer can be positive photoresist or negative photoresist, and is not specifically limited here. .
  • Step S2103 Expose and develop the first photoresist layer to form a plurality of development areas extending along the first direction A and spaced apart along the second direction B.
  • the development areas are located on the substrate 1
  • the orthographic projection passes through the array area 101 and the peripheral area 102 .
  • the first photoresist layer can be exposed using a mask, and the pattern of the mask can match the desired pattern of the word line trenches 201 . Subsequently, the exposed first photoresist layer can be developed to form a plurality of developed areas extending along the first direction A and spaced apart along the second direction B. Each of the developed areas can respectively expose the surface of the mask layer.
  • the pattern of the developed area can be the same as the required pattern of the word line trench 201, and the size of the developed area can be the same as the required size of the word line trench 201, that is, the developed area can be in a strip shape, and it can be formed on the substrate 1
  • the orthographic projection on can penetrate the array area 101 and the peripheral area 102. In some embodiments of the present disclosure, the orthographic projection of the development area on the substrate 1 may penetrate the peripheral area 102 and the plurality of active areas 12 .
  • step S2104 the mask layer and the substrate 1 are etched in the development area to form a plurality of word line trenches 201 extending along the first direction A and spaced apart along the second direction B.
  • the mask layer can be etched in each development area through an anisotropic etching process, and the etching area can expose the substrate 1, thereby forming multiple mask patterns on the mask layer.
  • the mask patterns can be in a strip shape, and each mask layer
  • the orthographic projection of the film pattern on the substrate 1 may penetrate the array area 101 and the peripheral area 102 respectively.
  • the orthographic projection of the development area on the substrate 1 may extend through multiple active areas 12 .
  • the mask pattern may be a strip pattern extending along the first direction A, and the plurality of mask patterns may be spaced apart along the second direction B.
  • each film layer can be etched in layers, that is, a one-time etching process.
  • One layer can be etched, and multiple etching processes can be used to etch the mask layer through to form a mask pattern.
  • the shape and size of the mask pattern can be consistent with the required pattern and size of each word line trench 201. Dimensions are the same.
  • the first photoresist layer can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the mask layer with the mask pattern is no longer covered by the first photoresist layer.
  • a mask layer with a mask pattern can be used as a mask, and then the substrate 1 can be anisotropically etched to form a plurality of word line trenches 201 extending along the first direction A and spaced apart along the second direction B.
  • Step S220 Form an inter-gate dielectric layer 23 conformally attached to the sidewalls of the word line trench 201 in the word line trench 201.
  • word line structures 2 can be formed in each word line trench 201 , that is, multiple word line structures 2 can be formed in the substrate 1 , and each word line structure 2 can be formed along the The first direction A extends, and the plurality of word line structures 2 may be spaced apart along the second direction B.
  • the word line structure 2 can penetrate the array area 101 and the peripheral area 102.
  • each word line structure 2 can extend from the peripheral area 102 to the array area 101, and it is located between the array area 101 and the array area 101.
  • a portion may penetrate multiple active areas 12 .
  • a conformally attached inter-gate dielectric layer 23 can be formed on the sidewalls and surfaces of each word line trench 201 .
  • the material of the inter-gate dielectric layer 23 can include silicon oxide and silicon nitride. , silicon nitride oxide, etc., can also be a combination of the aforementioned materials, and its thickness can be 1nm to 9nm. For example, it can be 1nm, 2nm, 4nm, 6nm, 8nm or 9nm. Of course, it can also be other thicknesses. This will not be listed one by one.
  • the conformally attached inter-gate dielectric layer 23 can be formed on the sidewalls and bottom of each word line trench 201 through chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation or thermal oxidation.
  • the inter-gate dielectric layer 23 can also be formed by other methods, and is not specifically limited here.
  • the inter-gate dielectric layer 23 can completely cover the top surface of the substrate 1, and then the inter-gate dielectric layer 23 located on the top surface of the substrate 1 can be removed, leaving only The inter-gate dielectric layer 23 is located on the sidewalls and bottom of each word line trench 201.
  • a thermal oxidation process can be used to treat the surface of the inter-gate dielectric layer 23 to improve the density of the film layer of the inter-gate dielectric layer 23, thereby reducing leakage current and improving gate control capability. It can also enhance the blocking effect of the inter-gate dielectric layer 23 on the impurities in the substrate 1, prevent the impurities in the substrate 1 from diffusing into the word line trench 201, and improve the structural stability.
  • a diffusion barrier layer may be formed on the surface of the inter-gate dielectric layer 23 to prevent metal materials from diffusing to the substrate 1 and increasing the risk of leakage current.
  • the diffusion barrier layer can be conformally attached to the surface of the inter-gate dielectric layer 23 , that is, the inter-gate dielectric layer 23 can be located between the diffusion barrier layer and the inner wall of the word line trench 201 , and the material of the diffusion barrier layer can be titanium nitride. , its thickness can be 0.5nm ⁇ 2nm, for example, it can be 0.5nm, 1nm, 1.5nm or 2nm.
  • a diffusion barrier layer can be formed on the surface of the inter-gate dielectric layer 23 through processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The formation process of the diffusion barrier layer is not particularly limited here.
  • step S230 the first conductive layer 21 is formed in the word line trench 201 with the inter-gate dielectric layer 23.
  • chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation can be used to form the word lines with the inter-gate dielectric layer 23
  • the trench 201 is filled with conductive material to form the first conductive layer 21 in the word line trench 201 .
  • the first conductive layer 21 can be formed on the surface of the diffusion barrier layer, that is, the first conductive layer 21 can be formed on the surface where the inter-gate dielectric layer 23 and the diffusion barrier layer are formed.
  • the word line trench 201 is filled with conductive material to form a first conductive layer 21 in the word line trench 201 .
  • forming the first conductive layer 21 in the word line trench 201 having the inter-gate dielectric layer 23 may include steps S2301 to S2305, in:
  • a conductive material layer 210 is formed on the surface of the substrate 1, and the conductive material layer 210 fills the word line trench 201 with the inter-gate dielectric layer 23.
  • each word line trench 201 having an inter-gate dielectric layer 23 can be formed by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation. Conductive materials are respectively filled in each word line trench 201 having an inter-gate dielectric layer 23 . Of course, other methods can also be used to fill conductive materials in each word line trench 201 having an inter-gate dielectric layer 23 . The conductive material can fill each word line trench 201, thereby forming a conductive material layer 210.
  • Step S2302 Form a second photoresist layer 4 on the surface of the conductive material layer 210, and the orthographic projection of the second photoresist layer 4 on the substrate 1 coincides with the peripheral area 102.
  • the second photoresist layer 4 can be formed on the surface of the conductive material layer 210 by spin coating or other methods.
  • the material of the second photoresist layer 4 can be positive photoresist or negative photolithography. Glue is not specifically limited here. It should be noted that the second photoresist layer 4 can cover the surface of the peripheral area 102 , and its orthographic projection on the substrate 1 can coincide with the boundary of the peripheral area 102 .
  • Step S2303 Use the second photoresist layer 4 as a mask to etch part of the conductive material layer 210 located in the array area 101 until the surface of the conductive material layer 210 in the array area 101 is in contact with the lining. The surface of bottom 1 is flush.
  • a dry etching process can be used to etch the conductive material layer 210 that is not covered by the second photoresist layer 4 , and the surface of the conductive material layer 210 that is not covered by the second photoresist layer 4 is etched with the lining. Stop etching when the surface of the bottom 1 is flush. At this time, the surface of the conductive material layer 210 in the area not covered by the photoresist layer is lower than the surface of the conductive material layer 210 in the area covered by the second photoresist layer 4, that is, located at The surface of the conductive material layer 210 in the array area 101 is lower than the surface of the conductive material layer 210 in the peripheral area 102 .
  • the etching gas for dry etching can be carbon tetrafluoride.
  • the etching gas can also be other gases, as long as the conductive material layer 210 can be removed without damaging other structures. This will not be listed one by one.
  • Step S2304 remove the second photoresist layer 4.
  • the second photoresist layer 4 can be removed by cleaning with a cleaning solution or by ashing or other processes, so that the etched conductive material layer 210 is no longer covered by the second photoresist layer 4 .
  • Step S2305 Etch the remaining conductive material layer 210 until the surface of the conductive material layer 210 located in the peripheral region 102 is lower than the surface of the substrate 1 .
  • the remaining conductive material layer 210 can be etched back until the conductive material layer 210 on the surface of the substrate 1 in the peripheral region 102 is completely removed, and during the etching back process, the conductive material layer 210 in the word line trench 201 can be removed.
  • the surface is lower than the surface of the substrate 1 to facilitate subsequent insulating isolation of the surface of the first conductive layer 21 to avoid coupling or short circuit between the second conductive layer 22 and other surrounding structures.
  • the conductive material layer 210 remaining after etching back may be defined as the first conductive layer 21 .
  • dry etching may be used to etch back, and the gas may be carbon tetrafluoride or other gases that can remove the conductive material layer 210 without damaging other structures.
  • Step S240 forming the second conductive layer 22 on the surface of the first conductive layer 21.
  • the second conductive layer 22 can be formed on the surface of the first conductive layer 21 using physical vapor deposition, chemical vapor deposition, atomic layer deposition, vacuum evaporation or magnetron sputtering.
  • the second conductive layer 22 can cover the array area.
  • the orthographic projection of the second conductive layer 22 on the substrate 1 does not overlap with the peripheral area 102, and the orthographic projection of the second conductive layer 22 on the substrate 1 can overlap with the array area 101 The boundaries overlap.
  • the thickness of the second conductive layer 22 may be the same as that of the first conductive layer 21 of the array region 101 and the first conductive layer 21 of the peripheral region 102 .
  • the height difference is equal, that is, the surface of the second conductive layer 22 can be flush with the surface of the first conductive layer 21 in the peripheral area 102, and the second conductive layer 22 only covers the portion of the first conductive layer 21 located in the array area 101. surface.
  • the proportion of the first conductive layer 21 in the word line structure 2 in the present disclosure increases. Since the material of the first conductive layer 21 is a metal material, the proportion of the metal material in the word line structure 2 can be increased, which is helpful to Reduce the resistance of word line structure 2.
  • step S240 forming the second conductive layer 22 on the surface of the first conductive layer (ie, step S240) may include step S310 and step S320, wherein:
  • Step S310 Form a semiconductor material layer 310 on the surface of the structure formed by the word line structure 2 and the substrate 1.
  • processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, vacuum evaporation or magnetron sputtering can be used to form semiconductors on the surface of the structure formed by the word line structure 2 and the substrate 1
  • Material layer 310 the thickness of the semiconductor material layer 310 can be greater than the height difference between the surface of the word line structure 2 located in the array area 101 and the surface of the substrate 1, that is, the semiconductor material layer 310 can fill each word line trench 201 and can be paved. covering the entire surface of substrate 1.
  • Step S320 remove the semiconductor material layer 310 located outside the word line trench 201, and continue to remove part of the semiconductor material layer 310 until the surface of the semiconductor material layer 310 located in the array area 101 is in contact with the surface of the semiconductor material layer 310 located in the array area 101.
  • the surface of the word line structure 2 in the peripheral area 102 is flush.
  • the semiconductor material layer 310 can be etched back until the semiconductor material layer 310 located on the surface of the peripheral region 102 is completely removed, and during the etching back process, the semiconductor material located in the array region 101 can be The surface of the material layer 310 is flush with the surface of the word line structure 2 located in the peripheral area 102 .
  • the remaining semiconductor material layer 310 after etching back may be defined as the second conductive layer 22 .
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • Step S130 Form an insulating layer 5 on the top of the word line structure 2.
  • the orthographic projection of the insulating layer 5 on the substrate 1 covers the orthographic projection of each word line structure 2 on the substrate 1. .
  • the insulating layer 5 can be a thin film formed on the surface of the word line structure 2 , or it can be a coating formed on the surface of the word line structure 2 .
  • the form of the insulating layer 5 is not specified here. Special restrictions.
  • the orthographic projection of the insulating layer 5 on the substrate 1 can cover the orthographic projection of each word line structure 2 on the substrate 1 .
  • the surface of the word line structure 2 can be insulated and protected through the insulating layer 5 to avoid surface damage to the word line structure 2; at the same time, the word line structure 2 can also be isolated from other structures through the insulating layer 5 to prevent the word line structure 2 from being damaged. Coupling or short circuiting with other structures can improve product yield.
  • the insulating layer 5 may simultaneously cover the surface of the second conductive layer 22 and the surface of the first conductive layer 21 located on the surface of the peripheral region 102 , that is, the insulating layer 5 may cover the first conductive layer 21 and
  • the second conductive layer 22 together constitutes the surface of the structure.
  • the first conductive layer 21 and the second conductive layer 22 can be insulated and protected through the insulating layer 5 to avoid surface damage of the first conductive layer 21 and the second conductive layer 22; at the same time, the first conductive layer 21 and the second conductive layer 22 can also be insulated through the insulating layer 5.
  • the layer 21 and the second conductive layer 22 are isolated from other structures to avoid coupling or short circuit between the first conductive layer 21 and the second conductive layer 22 and other structures, thereby improving product yield.
  • the material of the insulating layer 5 can be silicon nitride or other insulating materials, and can be formed on the first conductive layer through chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal evaporation, vacuum evaporation or magnetron sputtering.
  • the insulating layer 5 is formed on the surface of the structure formed by the layer 21 and the second conductive layer 22.
  • the insulating layer 5 can also be formed by other methods, and the formation method of the insulating layer 5 is not particularly limited here.
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • Step S140 form a word line contact plug 6 in the peripheral area 102 , and the bottom surface of the word line contact plug 6 is connected to the first conductive layer 21 .
  • the word line contact plug 6 may be formed in the peripheral area 102 , that is, the orthographic projection of the second conductive layer 22 on the substrate 1 and the word line contact plug 6 on the substrate 1 The orthographic projection of has no overlap. And the second conductive layer 22 may be spaced apart from the word line contact plugs 6.
  • an end of the second conductive layer 22 close to the peripheral region 102 may have a first distance from the word line contact plug 6, and the first distance may be less than
  • the length of the first conductive layer 21 located in the peripheral area 102 in the first direction A helps to isolate the word line conductive plug 6 and the portion of the first conductive layer 21 located in the peripheral area 102 from the second conductive layer 22 to avoid The formation of the word line conductive plug 6 causes damage to the second conductive layer 22 .
  • the bottom surface of the word line contact plug 6 can be in contact with the surface of the first conductive layer 21 located in the peripheral area 102 , so that the word line structure 2 can be electrically drawn out through the word line contact plug 6 , and then the word line structure 2 can be electrically led out.
  • the data signals in the word line structure 2 can be brought out through the word line contact plugs 6 .
  • one side of the word line contact plug 6 is connected to the word line structure 2, and the other side can be connected to the word line driver, sense amplifier, row decoder and column decoding through the peripheral contact plug 7
  • the control circuit is connected with the control circuit of the special function. The control circuit transmits current through the word line contact plug 6 to control the word line structure 2 and the bit line structure to realize the storage and reading functions of the transistor and the capacitor.
  • the word line contact plug 6 may penetrate the insulating layer 5 in a direction perpendicular to the substrate 1 , that is, the word line contact plug 6 may be buried in the insulating layer 5 Inside, the word line contact plug 6 can be insulated and protected through the insulating layer 5. In this process, coupling or short circuit between the word line contact plug 6 and other surrounding structures can be avoided, which can further improve the product yield.
  • forming a word line contact plug 6 in the peripheral area 102, and the bottom surface of the word line contact plug 6 being connected to the first conductive layer 21 may include Step S1401 and step S1402, wherein:
  • Step S1401 Form a first contact hole 601 penetrating the insulating layer 5, and the first contact hole 601 exposes the word line structure 2.
  • the first contact hole 601 can be formed in the peripheral area 102 through an etching process.
  • the first contact hole 601 can expose the word line structure 2.
  • the first contact hole 601 can also be formed in other ways.
  • the formation method of the first contact hole 601 is not particularly limited here.
  • first contact hole 601 is formed in the peripheral area 102 and the surface of the part of the word line structure 2 located in the peripheral area 102 is not covered by the second conductive layer 22, during the etching process to form the first contact hole 601 , there is no need to pass through the second conductive layer 22, and there is no need to use an etching solution or etching gas with a relatively large etching rate for the second conductive layer 22 to etch, which can avoid causing damage to the substrate 1 during the process of etching the second conductive layer 22. damage, it can also prevent etching damage from extending into the array area 101, reduce the source of defects in the substrate 1, and improve product yield.
  • the first contact hole 601 may be a circular hole, an elliptical hole, a rectangular hole or a hole-like structure of other shapes.
  • the shape of the first contact hole 601 is not particularly limited here, as long as the word line structure 2 can be exposed.
  • the number of first contact holes 601 may be multiple.
  • the number of first contact holes 601 may be equal to the number of word line structures 2 , and each first contact hole 601 may expose each word line structure 2 in one-to-one correspondence.
  • Step S1402 Fill the first contact hole 601 with a metal conductive material to form the word line contact plug 6.
  • each first contact hole 601 can be filled with a first conductive material through a process such as electroplating, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation, and then formed.
  • the metal conductive material may be titanium nitride or tungsten. Of course, it may also be other materials with strong conductive properties, which are not listed here.
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • Step S150 form a peripheral contact plug 7 in the peripheral area 102, the peripheral contact plug 7 is electrically connected to the word line contact plug 6, and in a direction perpendicular to the substrate 1, the peripheral contact plug 7 is electrically connected to the word line contact plug 6.
  • the top surface of the peripheral contact plug 7 is at the same height as the top surface of the word line contact plug 6 .
  • the peripheral contact plug 7 can be located in the peripheral area 102, and one end of the peripheral contact plug 7 can be connected to the source and drain electrode 110 of the transistor in the peripheral area 102; in the direction perpendicular to the substrate 1,
  • the peripheral contact plugs 7 can penetrate the insulating layer 5 and can be spaced apart from the word line contact plugs 6 .
  • the top surface of the peripheral contact plugs 7 can be at the same height as the top surface of the word line contact plugs 6 .
  • the peripheral contact plug 7 can be electrically connected to the word line contact plug 6 through a connection line located on the surface of the insulating layer 5 , thereby enabling the peripheral circuit to control each component in the array area 101 .
  • a peripheral contact plug 7 is formed in the peripheral area 102 , the peripheral contact plug 7 is electrically connected to the word line contact plug 6 , and is perpendicular to the substrate 1 In the direction of , the top surface of the peripheral contact plug 7 is at the same height as the top surface of the word line contact plug 6 (ie, step S150) may include step S1501 and step S1502, wherein:
  • Step S1501 form a second contact hole 701 penetrating the insulating layer 5 , and the second contact hole 701 exposes the source and drain electrode 110 of the transistor in the peripheral region 102 .
  • the insulating layer 5 located in the peripheral region 2 can be etched through an etching process, and then a second contact hole 701 is formed in the peripheral region 102 .
  • the second contact hole 701 can expose the source and drain of the transistor in the peripheral region 102 . 110.
  • the second contact hole 701 can also be formed in other ways, and the formation method of the second contact hole 701 is not specifically limited here.
  • the second contact hole 701 can be a circular hole, an elliptical hole, a rectangular hole, or a hole-like structure of other shapes.
  • the shape of the second contact hole 701 is not particularly limited here, as long as the source and drain of the transistor in the peripheral region 102 can be exposed. Extremely 100 is enough.
  • the number of second contact holes 701 may be multiple.
  • the number of second contact holes 701 may be equal to the number of transistors in the peripheral area 102 .
  • Each second contact hole 701 may expose each transistor in the peripheral area 102 in a one-to-one correspondence. source and drain 110.
  • Step S1402 Fill the second contact hole 701 with a second conductive material to form the peripheral contact plug 7.
  • each second contact hole 701 can be filled with a second conductive material through a process such as electroplating, vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition or thermal evaporation, and then formed. Peripheral contact plug 7.
  • the second conductive material and the first conductive material may be the same or different, and are not specifically limited here.
  • the second conductive material can be titanium nitride or tungsten.
  • it can also be other materials with strong conductive properties, which are not listed here.
  • Embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments.
  • a memory which may include the semiconductor structure in any of the above embodiments.
  • the specific details, formation processes and beneficial effects have been detailed in the corresponding semiconductor structure and the method for forming the semiconductor structure. Description will not be repeated here.
  • the memory can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • other storage devices may also be used, which are not listed here.

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Abstract

本公开是关于半导体技术领域，涉及一种半导体结构及其形成方法、存储器，本公开的半导体结构包括衬底及字线结构，其中：衬底包括阵列区和外围区；字线结构包括位于衬底内部的第一导电层，第一导电层沿第一方向贯穿阵列区并延伸至外围区；在垂直于衬底的方向上，第一导电层位于外围区表面的高度高于第一导电层位于阵列区表面的高度。本公开的半导体结构可降低工艺难度，提高产品良率。 (图3)

Description

半导体结构及其形成方法、存储器
交叉引用
本公开要求于2022年8月9日提交的申请号为202210952952.8名称为“半导体结构及其形成方法、存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体结构及其形成方法、存储器。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。字线结构作为DRAM的核心部件，对器件的电性能有着至关重要的作用。
在DRAM中通常需要通过字线接触插塞将字线结构电学引出，在此过程中，字线接触插塞需要贯穿字线结构表面的第二导电层才能与字线结构连接，然而，在蚀刻第二导电层的过程中易对衬底造成损伤，产品良率较低。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种半导体结构及其形成方法、存储器，可降低工艺难度，提高产品良率。
根据本公开的一个方面，提供一种半导体结构，包括：
衬底，包括阵列区和外围区；
字线结构，包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
在本公开的一种示例性实施例中，所述半导体结构还包括：
字线接触插塞，位于所述外围区，且所述字线接触插塞的底面与所述第一导电层连接。
在本公开的一种示例性实施例中，所述字线结构还包括：
第二导电层，所述第二导电层位于所述第一导电层上部，所述第二导电层在所述衬底上的正投影与所述字线接触插塞在所述衬底上的正投影无交叠。
在本公开的一种示例性实施例中，所述第二导电层靠近所述外围区的一端与所述字线接触插塞之间具有第一距离，所述第一距离小于所述第一导电层在所述第一方向上位于所述外围区的长度。
在本公开的一种示例性实施例中，所述第一导电层位于所述外围区的表面与所述第二导电层的表面齐平。
在本公开的一种示例性实施例中，所述第一导电层的材料为金属材料，所述第二导电层的材料为半导体材料。
在本公开的一种示例性实施例中，所述半导体结构还包括：
外围接触插塞，位于所述外围区，并与所述字线接触插塞电连接，且在垂直于所述衬底的方向上，所述外围接触插塞的顶面与所述字线接触插塞的顶面高度相同。
在本公开的一种示例性实施例中，所述字线结构还包括栅间介质层，所述栅间介质层至少随形包覆于所述第一导电层和所述第二导电层的侧壁表面。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供衬底，所述衬底包括阵列区和外围区；
在所述衬底内形成多个字线结构，所述字线结构包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
在本公开的一种示例性实施例中，所述形成方法还包括：
在所述外围区形成字线接触插塞，所述字线接触插塞的底面与所述第一导电层连接。
在本公开的一种示例性实施例中，所述形成方法还包括：
在所述第一导电层的上部形成第二导电层，所述第二导电层在所述衬底上的正投影与所述字线接触插塞在所述衬底上的正投影无交叠。
在本公开的一种示例性实施例中，所述第二导电层靠近所述外围区的一端与所述字线接触插塞之间具有第一距离，所述第一距离小于所述第一导电层在所述第一方向上位于所述外围区的长度。
在本公开的一种示例性实施例中，所述第一导电层位于所述外围区的表面与所述第二导电层的表面齐平。
在本公开的一种示例性实施例中，所述第一导电层的材料为金属材料，所述第二导电层的材料为半导体材料。
在本公开的一种示例性实施例中，所述形成方法还包括：
在所述外围区形成外围接触插塞，所述外围接触插塞与所述字线接触插塞电连接，且在垂直于所述衬底的方向上，所述外围接触插塞的顶面与所述字线接触插塞的顶面高度相同。
在本公开的一种示例性实施例中，所述字线结构还包括栅间介质层，所述栅间介质层至少随形包覆于所述第一导电层和所述第二导电层的侧壁表面。
在本公开的一种示例性实施例中，在所述衬底内形成多个字线结构，包括：
在所述衬底内形成多个字线沟槽，所述字线沟槽贯穿所述阵列区和所述外围区；
在所述字线沟槽内形成随形贴附于所述字线沟槽的侧壁的栅间介质层；
在具有所述栅间介质层的所述字线沟槽内形成所述第一导电层；
在所述第一导电层的表面形成所述第二导电层。
在本公开的一种示例性实施例中，在具有所述栅间介质层的所述字线沟槽内形成所述第一导电层，包括：
在所述衬底的表面形成导电材料层，所述导电材料层填满具有所述栅间介质层的所述字线沟槽；
在所述导电材料层的表面形成第二光阻层，所述第二光阻层在所述衬底上的正投影与所述外围区重合；
以所述第二光阻层为掩膜蚀刻部分位于所述阵列区的所述导电材料层，至所述阵列区的所述导电材料层的表面与所述衬底的表面齐平；
去除所述第二光阻层；
蚀刻剩余的所述导电材料层，直至位于所述外围区的所述导电材料层的表面低于所述衬底的表面且高于位于所述阵列区的所述导电材料层的表面。
在本公开的一种示例性实施例中，在所述第一导电层的表面形成所述第二导电层，包括：
在所述栅间介质层、所述第一导电层及所述衬底共同构成的结构的表面形成半导体材料层；
去除位于所述字线沟槽外的所述半导体材料层，并继续去除部分所述半导体材料层，至位于所述阵列区的所述半导体材料层的表面与位于所述外围区的所述第一导电层的表面齐平。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述的半导体结构。
本公开的半导体结构及其形成方法、存储器，由于第一导电层位于外围区的表面的高度高于第一导电层位于阵列区的表面的高度，可将后续形成的第二导电层形成于位于阵列区的第一导电层的表面，此时无需在外围区形成第二导电层，在后续形成与字线结构连接的字线接触插塞时，用于容纳字线接触插塞的过孔无需穿过第二导电层，进而无需采用对第二导电层的蚀刻速率较大的蚀刻溶液或蚀刻气体进行蚀刻，可避免在蚀刻第二导电层的过程中对衬底造成的损伤，也可避免蚀刻损伤延伸至阵列区内部，减小衬底中的缺陷来源，提高产品良率。且在上述过程中，由于外围区的字线结构的表面没有第二导电层，在后续形成过孔的过程中，无需蚀刻第二导电层，可减少蚀刻的层数，进而简化工艺(即，减少了蚀刻第二导电层的工艺)，降低制造成本；同时，由于第一导电层的高度提高，减小过孔蚀刻高度，降低工艺难度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中字线结构的示意图；
图2为本公开实施方式中半导体结构的俯视图；
图3为本公开实施方式中半导体结构沿图2中bb’方向切开的剖面图；
图4为本公开实施方式中衬底的俯视图；
图5为本公开实施方式中沿图4中aa’方向切开的剖面图；
图6为本公开实施方式中沿图4中bb’方向切开的剖面图；
图7为本公开实施方式中第一导电层沿图4中aa’方向切开的剖面图；
图8为本公开实施方式中第一导电层沿图4中bb’方向切开的剖面图；
图9为本公开实施方式中绝缘层沿图4中aa’方向切开的剖面图；
图10为本公开实施方式中绝缘层沿图4中bb’方向切开的剖面图；
图11为本公开实施方式中字线接触插塞沿图4中aa’方向切开的剖面图；
图12为本公开实施方式中字线接触插塞沿图4中bb’方向切开的剖面图；
图13为本公开实施方式中外围区的外围接触插塞的剖面图；
图14为本公开实施方式中半导体结构的形成方法的流程图；
图15为本公开实施方式中完成步骤S2301后沿图4中aa’方向切开的剖面图；
图16为本公开实施方式中完成步骤S2301后沿图4中bb’方向切开的剖面图；
图17为本公开实施方式中完成步骤S2302后沿图4中aa’方向切开的剖面图；
图18为本公开实施方式中完成步骤S2302后沿图4中bb’方向切开的剖面图；
图19为本公开实施方式中完成步骤S2303后沿图4中bb’方向切开的剖面图；
图20为本公开实施方式中完成步骤S320后沿图4中aa’方向切开的剖面图；
图21为本公开实施方式中完成步骤S320后沿图4中bb’方向切开的剖面图；
图22为本公开实施方式中完成步骤S1401后沿图4中aa’方向切开的剖面图；
图23为本公开实施方式中完成步骤S1401后沿图4中bb’方向切开的剖面图；
图24为本公开实施方式中第二接触孔的剖面图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
字线结构是动态随机存储器(Dynamic Random Access Memory，DRAM)的核心部件之一，在制程过程中，如图1所示，为了节省空间，通常将字线结构埋入衬底100内部，字线结构通常包括堆叠设置的第一导电层200和第二导电层300，通过与字线结构连接的引线将字线结构电学引出。在形成引线的过程中，为了降低电阻，在形成容纳引线的过孔400时，需要将第二导电层300刻透，进而露出其下方的第一导电层200，然而，第二导电层300的材料的物理及化学性能通常与衬底100中的有源区的材料类似，在蚀刻第二导电层300的过程中易对有源区造成损伤，产品良率较低。
本公开实施方式提供了一种半导体结构，图2示出了本公开实施方式中半导体结构的俯视图，图3示出了本公开实施方式中半导体结构沿图2中bb’方向切开的剖面图；参见图2及图3所示，该半导体结构可包括衬底1及字线结构2，其中：
衬底1可包括阵列区101和外围区102；
字线结构2可包括位于衬底1内部的第一导电层21，第一导电层21沿第一方向A贯穿阵列区101并延伸至外围区102；在垂直于衬底1的方向上，第一导电层21位于外围区102表面的高度高于第一导电层21位于阵列区102表面的高度。
本公开的半导体结构，由于第一导电层21位于外围区102的表面的高度高于第一导电层21位于阵列区101的表面的高度，可将后续形成的第二导电层22形成于位于阵列区101的第一导电层21的表面，此时无需在外围区102形成第二导电层22，在后续形成与字线结构2连接的字线接触插塞时，用于容纳字线接触插塞的过孔无需穿过第二导电层22，进而无需采用对第二导电层22的蚀刻速率较大的蚀刻溶液或蚀刻气体进行蚀刻，可避免在蚀刻第二导电层22的过程中对衬底1造成的损 伤，也可避免蚀刻损伤延伸至阵列区101内部，减小衬底1中的缺陷来源，提高产品良率。且在上述过程中，由于外围区102的字线结构2的表面没有第二导电层22，在后续形成过孔的过程中，无需蚀刻第二导电层22，可减少蚀刻的层数，进而简化工艺(即，减少了蚀刻第二导电层22的工艺)，降低制造成本；同时，由于第一导电层21的高度提高，减小过孔蚀刻高度，可降低工艺难度。
下面对本公开的半导体结构的各部分进行详细说明：
如图4-图6所示，衬底1可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可为硅，但是不限于硅或其他半导体材料，在此不对衬底1的形状及材料做特殊限定。
在本公开的一些实施方式中，如图4所示，衬底1可为硅衬底，其内部形成有浅沟槽隔离结构11，浅沟槽隔离结构11可以通过在衬底1内形成沟槽后，再在沟槽内填充隔离材料层而形成。浅沟槽隔离结构11的材料可以包括氮化硅或氧化硅等，在此不做特殊限定。浅沟槽隔离结构11的截面形状可以根据实际需要进行设定。浅沟槽隔离结构11能在衬底1上分隔出若干个有源区12。
在本公开的一些实施方式中，继续参见图6所示，衬底1可包括阵列区101及外围区102，阵列区101与外围区102可邻接分布，外围区102可位于阵列区101的一侧，也可环绕于阵列区101的外周，阵列区101可用于形成电容阵列、晶体管阵列、连接晶体管以及电容的字线结构2和位线结构，外围区102可用于形成字线接触插塞。字线接触插塞可以连接位于外围区102的字线驱动器、感测放大器、行解码器和列解码器以及特殊功能的控制电路，控制电路可通过控制字线及位线来实现晶体管及电容的存储及读取功能。举例而言，阵列区101可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区102可为环形区域，并可环绕于阵列区101的外周，其可以是圆环区域、矩形环区域或其他形状的环形区域，在此不再一一列举。各有源区12均可位于阵列区101内，各有源区12可在阵列区101内呈阵列分布。
需要说明的是，外围区102与阵列区101的边界没有明显划分，在本实施例中，外围区102与阵列区101的边界以各条第二导电层22的端点连线作为区分，外围区102的边缘与有源区12侧边之间具有一定距离，该距离范围内的区域可属于阵列区101。
在本公开的一种示例性实施方式中，参见图4及图5所示，衬底1内可设有多个沿第一方向A延伸的字线沟槽201，且各字线沟槽201可沿第二方向B间隔分布。字线沟槽201可以是由衬底1表面向内凹陷所构成的槽状结构，其底端与衬底1贯通。在第一方向A上，字线沟槽201可贯穿阵列区101及外围区102，且字线沟槽201中位于阵列区101的部分可贯穿多个有源区12。
第一方向A可与第二方向B相交，例如，第一方向A与第二方向B可相互垂直。需要说明的是，垂直可以是绝对垂直，也可以是大致垂直，在制造过程中难免会有偏差，在本公开中，可能由于制作工艺限制引起角度的偏差，使得第一方向A和第二方向B的夹角有一定的偏差，只要第一方向A和第二方向B的角度偏差在预设范围内，均可认为第一方向A与第二方向B垂直。举例而言，预设范围可为10°，即：第一方向A和第二方向B的夹角在大于或等于80°，小于或等于100°的范围内时均可认为第一方向A和第二方向B垂直。
继续参见图2及图3所示，可在各字线沟槽201内均形成字线结构2，即，可在衬底1内形成多个字线结构2，各字线结构2均可沿第一方向A延伸，多个字线结构2可沿第二方向B间隔分布。
在本公开的一些实施方式中，字线结构2可贯穿阵列区101和外围区102，举 例而言，各字线结构2均可由外围区102向阵列区101延伸，且其在阵列区101的部分可贯穿多个有源区12。
在本公开的一些实施方式中，参见图7及图8所示，字线结构2可包括第一导电层21，第一导电层21可贯穿阵列区101并延伸至外围区102，第一导电层21位于外围区102的表面的高度可高于第一导电层21位于阵列区101的表面的高度，以便于后续在外围区102形成字线接触插塞。
在本公开的一种示例性实施方式中，第一导电层21的材料可为金属材料，举例而言，其材料可为钨、钛、钽中的一种。
在本公开的一种示例性实施方式中，继续参见图2及图3所示，字线结构2还可包括第二导电层22，第二导电层22可位于第一导电层21的上部，并与第一导电层21接触连接。
在本公开的一种示例性实施方式中，第二导电层22的材料可为半导体材料，该半导体材料可具有较低功函数的材料，举例而言，其材料可为多晶硅。在保证字线结构2的开启电压的情况下，可在第一导电层21的表面设置功函数较低的第二导电层22，通过第二导电层22降低栅诱导漏极泄漏电流(Gate-Induced Drain Leakage，GIDL)。
在本公开的一些示例性实施方式中，继续参见图2-图8所示，字线结构2还可包括栅间介质层23，栅间介质层23可至少随形包覆于第一导电层21和第二导电层22的侧壁的表面，其可以是形成于第一导电层21和第二导电层22的侧壁的表面的薄膜层。
在本公开的一种示例性实施方式中，参见图5-图7所示，可在各字线沟槽201的侧壁及表面形成随形贴附的栅间介质层23，栅间介质层23的材料可以包括氧化硅、氮化硅、氮氧化硅等，也可为前述材料的组合，其厚度可以是1nm～9nm，举例而言，其可以是1nm、2nm、4nm、6nm、8nm或9nm，当然，也可以是其他厚度，在此不再一一列举。
举例而言，可通过化学气相沉积、物理气相沉积、原子层沉积、热蒸发或热氧化等方式在各字线沟槽201的侧壁及底部形成随形贴附的栅间介质层23，当然，也可通过其他方式形成栅间介质层23，在此不做特殊限定。为了工艺方便，在形成栅间介质层23的过程中，可使栅间介质层23完全覆盖衬底1的顶表面，随后可去除位于衬底1表面的栅间介质层23，只保留位于各字线沟槽201的侧壁及底部的栅间介质层23。
在本公开的一些实施方式中，可采用热氧化工艺对栅间介质层23的表面进行处理，以提高栅间介质层23的膜层的致密性，进而减小漏电流，提高栅控能力，还可增强栅间介质层23对衬底1中杂质的阻隔效果，避免衬底1中的杂质扩散至字线沟槽201内，可提高结构稳定性。
在本公开的一些实施方式中，可在栅间介质层23表面形成扩散阻挡层，用于避免金属材料向衬底1扩散，增大漏电流风险。扩散阻挡层可随形贴附于栅间介质层23的表面，即，栅间介质层23可位于扩散阻挡层与字线沟槽201的内壁之间，扩散阻挡层的材料可以是氮化钛，其厚度可以是0.5nm～2nm，例如，其可以是0.5nm、1nm、1.5nm或2nm。在一些实施方式中，可以通过化学气相沉积、物理气相沉积或原子层沉积等工艺在栅间介质层23的表面形成扩散阻挡层，在此不对扩散阻挡层的成型工艺做特殊限定。
在本公开的一种示例性实施方式中，可采用化学气相沉积、物理气相沉积、原子层沉积、真空蒸镀、磁控溅射或热蒸发等方式在形成有栅间介质层23的字线沟槽201内填充导电材料，以在字线沟槽201内形成第一导电层21，需要说明的是，在 垂直于衬底1的方向上，第一导电层21位于外围区102的部分的表面的高度高于其位于阵列区101的部分的表面的高度。
需要说明的是，在栅间介质层23的表面形成有扩散阻挡层时，第一导电层21可形成于扩散阻挡层的表面，即，可在形成有栅间介质层23及扩散阻挡层的字线沟槽201内填充导电材料，以在字线沟槽201内形成第一导电层21。
可采用物理气相沉积、化学气相沉积、原子层沉积、真空蒸镀或磁控溅射等工艺在第一导电层21的表面形成第二导电层22，第二导电层22可覆盖于位于阵列区101的第一导电层21的表面，第二导电层22在衬底1上的正投影与外围区102无交叠，且第二导电层22在衬底1上的正投影可与阵列区101的边界重合。
在本公开的一种示例性实施方式中，继续参见图2及图3所示，第二导电层22的厚度可与阵列区101的第一导电层21和外围区102的第一导电层21的高度差相等，即，第二导电层22的表面可与外围区102的第一导电层21的表面齐平，第二导电层22只覆盖于第一导电层21位于阵列区101的部分的表面。此时，相比于现有技术(第二导电层22覆盖第一导电层21的全部表面)，在第二导电层22和第一导电层21组成的整体结构所占的空间相同的情况下，本公开中的字线结构2中的第一导电层21的占比增多，由于第一导电层21的材料为金属材料，可提高金属材料在字线结构2中的占比，有助于减小字线结构2的电阻。
在本公开的一种示例性实施方式中，如图9及图10所示，本公开的半导体结构还可包括绝缘层5，绝缘层5可以是形成于字线结构2的顶部的薄膜，也可以是形成于字线结构2的顶部的涂层，在此不对绝缘层5的形式做特殊限定。绝缘层5在衬底1上的正投影可覆盖各字线结构2在衬底1上的正投影。可通过绝缘层5对字线结构2的表面进行绝缘保护，以避免字线结构2的表面损伤；同时，还可通过绝缘层5将字线结构2与其他结构隔绝开，避免字线结构2与其他结构之间发生耦合或短路，可提高产品良率。
在本公开的一些实施方式中，绝缘层5可同时覆盖第二导电层22的表面和位于外围区102表面的第一导电层21的表面，即，绝缘层5可覆盖第一导电层21和第二导电层22共同构成的结构的表面。可通过绝缘层5对第一导电层21和第二导电层22进行绝缘保护，以避免第一导电层21和第二导电层22的表面损伤；同时，还可通过绝缘层5将第一导电层21和第二导电层22与其他结构隔绝开，避免第一导电层21和第二导电层22与其他结构之间发生耦合或短路，可提高产品良率。
举例而言，绝缘层5的材料可为氮化硅或其他绝缘材料，可通过化学气相沉积、物理气相沉积、原子层沉积、热蒸发、真空蒸镀或磁控溅射等方式在第一导电层21和第二导电层22共同构成的结构的表面形成绝缘层5，当然，也可通过其他方式形成绝缘层5，在此不对绝缘层5的形成方式做特殊限定。
在本公开的一种示例性实施方式中，如图11及图12所示，本公开的半导体结构还可包括字线接触插塞6，字线接触插塞6可形成于外围区102，即，第二导电层22在衬底1上的正投影与字线接触插塞6在衬底1上的正投影无交叠。且第二导电层22可与字线接触插塞6间隔分布，例如，第二导电层22靠近外围区102的一端可与字线接触插塞6之间具有第一距离，第一距离可小于第一导电层21在第一方向A上位于外围区102的长度，有助于使字线导电插塞6与第一导电层21位于外围区102的部分与第二导电层22隔离设置，避免字线导电插塞6的形成对第二导电层22造成损伤。
继续参见图12所示，字线接触插塞6的底面可与位于外围区102的第一导电层21的表面接触连接，以便于通过字线接触插塞6将字线结构2电学引出，进而可通过字线接触插塞6将字线结构2中的数据信号引出。
在本公开的一些实施方式中，字线接触插塞6的一侧与字线结构2连接，另一侧可通过外围接触插塞7与包括字线驱动器、感测放大器、行解码器和列解码器以及特殊功能的控制电路连接，控制电路通过字线接触插塞6电流传送可实现控制字线结构2及位线结构，实现晶体管及电容的存储及读取功能。
在本公开的一些实施方式中，继续参见图12所示，字线接触插塞6可沿垂直于衬底1的方向贯穿绝缘层5，即，字线接触插塞6可埋于绝缘层5内，可通过绝缘层5对字线接触插塞6进行绝缘保护，在此过程中，可避免字线接触插塞6与周围其他结构之间发生耦合或短路，可进一步提高产品良率。
在本公开的一种示例性实施方式中，如图13所示，本公开的半导体结构还可包括外围接触插塞7，外围接触插塞7可位于外围区102，外围接触插塞7的一端可与外围区102内的晶体管的源漏极110连接；在垂直于衬底1的方向上，外围接触插塞7可贯穿绝缘层5，并可与字线接触插塞6间隔分布，外围接触插塞7的顶面可与字线接触插塞6的顶面高度相同。
在本公开的一些实施方式中，外围接触插塞7可通过位于绝缘层5表面的连接线与字线接触插塞6电连接，进而实现外围电路对阵列区101中的各部件的控制。
本公开实施方式还提供了一种半导体结构的形成方法，图14示出了本公开的半导体结构的形成方法的流程图，参见图14所示，本公开的形成方法可包括步骤S110及步骤S120，其中：
步骤S110，提供衬底，所述衬底包括阵列区和外围区；
步骤S120，在所述衬底内形成多个字线结构，所述字线结构包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
本公开的半导体结构的形成方法，由于第一导电层21位于外围区102的表面的高度高于第一导电层21位于阵列区101的表面的高度，可将后续形成的第二导电层22形成于位于阵列区101的第一导电层21的表面，此时无需在外围区102形成第二导电层22，在后续形成与字线结构2连接的字线接触插塞6时，用于容纳字线接触插塞6的过孔无需穿过第二导电层22，进而无需采用对第二导电层22的蚀刻速率较大的蚀刻溶液或蚀刻气体进行蚀刻，可避免在蚀刻第二导电层22的过程中对衬底1造成的损伤，也可避免蚀刻损伤延伸至阵列区101内部，减少衬底1中的缺陷来源，提高产品良率。且在上述过程中，由于外围区102的字线结构2的表面没有第二导电层22，在后续形成过孔的过程中，无需蚀刻第二导电层22，可减少蚀刻的层数，进而简化工艺(即，减少了蚀刻第二导电层22的工艺)，降低制造成本；同时，由于第一导电层21的高度提高，减小过孔蚀刻高度，可降低工艺难度。
下面对本公开实施方式中的半导体结构的形成方法的各步骤及其具体细节进行详细说明：
如图14所示，在步骤S110中，提供衬底，所述衬底包括阵列区和外围区。
如图4-图6所示，衬底1可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可为硅，但是不限于硅或其他半导体材料，在此不对衬底1的形状及材料做特殊限定。
在本公开的一些实施方式中，如图4所示，衬底1可为硅衬底，其内部形成有浅沟槽隔离结构11，浅沟槽隔离结构11可以通过在衬底1内形成沟槽后，再在沟槽内填充隔离材料层而形成。浅沟槽隔离结构11的材料可以包括氮化硅或氧化硅等，在此不做特殊限定。浅沟槽隔离结构11的截面形状可以根据实际需要进行设定。浅沟槽隔离结构11能在衬底1上分隔出若干个有源区12。
在本公开的一些实施方式中，继续参见图6所示，衬底1可包括阵列区101及外围区102，阵列区101与外围区102可邻接分布，外围区102可位于阵列区101的一侧，也可环绕于阵列区101的外周，阵列区101可用于形成电容阵列、晶体管阵列、连接晶体管以及电容的字线结构2和位线结构，外围区102可用于形成与外围电路连接的字线接触插塞6。外围电路可以包括字线驱动器、感测放大器、行解码器和列解码器以及特殊功能的控制电路，外围电路可通过控制字线及位线来实现晶体管及电容的存储及读取功能。举例而言，阵列区101可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区102可为环形区域，并可环绕于阵列区101的外周，其可以是圆环区域、矩形环区域或其他形状的环形区域，在此不再一一列举。各有源区12均可位于阵列区101内，各有源区12可在阵列区101内呈阵列分布。
需要说明的是，外围区102与阵列区101没有明显划分，在本实施例中，外围区102的边界与阵列区101的边界以各条第二导电层22的端点连线作为区分，外围区102的边缘与有源区12侧边之间具有一定距离，该距离范围内的区域可属于阵列区101。
如图14所示，在步骤S120中，在所述衬底内形成多个字线结构，所述字线结构包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
参见7及图8所示，字线结构2可包括第一导电层21，第一导电层21可贯穿阵列区101并延伸至外围区102，进而使得第一导电层21成台阶状，以便于后续在外围区102形成字线接触插塞6。
在本公开的一种示例性实施方式中，第一导电层21的材料可为金属材料，举例而言，其材料可为钨、钛、钽中的一种。
在本公开的一种示例性实施方式中，继续参见图2及图3所示，字线结构2还可包括第二导电层22，第二导电层22可位于第一导电层21的上部，并与第一导电层21接触连接。
在本公开的一种示例性实施方式中，第二导电层22的材料可为半导体材料，该半导体材料可具有较低功函数的材料，举例而言，其材料可为多晶硅。在保证字线结构2的开启电压的情况下，可在第一导电层21的表面设置功函数较低的第二导电层22，通过第二导电层22降低栅诱导漏极泄漏电流(Gate-Induced Drain Leakage，GIDL)。
在本公开的一些示例性实施方式中，继续参见图2-图8所示，字线结构2还可包括栅间介质层23，栅间介质层23可至少随形包覆于第一导电层21和第二导电层22的侧壁的表面，其可以是形成于第一导电层21和第二导电层22的侧壁的表面的薄膜层。
在本公开的一种示例性实施方式中，在衬底1内形成多个字线结构2可包括步骤S210-步骤S240，其中：
步骤S210，在所述衬底1内形成多个字线沟槽201，所述字线沟槽201贯穿所述阵列区101和所述外围区102。
继续参见图4及图5所示，各字线沟槽201均可沿第一方向A延伸，且多个字线沟槽201可沿第二方向B间隔分布。字线沟槽201可以是由衬底1表面向内凹陷所构成的槽状结构，其底端与衬底1的贯通。在第一方向A上，字线沟槽201可贯穿阵列区101及外围区102，且字线沟槽201中位于阵列区101的部分可贯穿多个有源区12。
第一方向A可与第二方向B相交，例如，第一方向A与第二方向B可相互垂直。需要说明的是，垂直可以是绝对垂直，也可以是大致垂直，在制造过程中难免会有偏差，在本公开中，可能由于制作工艺限制引起角度的偏差，使得第一方向A和第二方向B的夹角有一定的偏差，只要第一方向A和第二方向B的角度偏差在预设范围内，均可认为第一方向A与第二方向B垂直。举例而言，预设范围可为10°，即：第一方向A和第二方向B的夹角在大于或等于80°，小于或等于100°的范围内时均可认为第一方向A和第二方向B垂直。
在本公开的一些实施方式中，在所述衬底1内形成多个字线沟槽201，所述字线沟槽201贯穿所述阵列区101和所述外围区102(即步骤S210)可包括步骤S2101-步骤S2104，其中：
步骤S2101，在所述衬底1表面形成掩膜层。
本公开的一些实施方式中，可通过化学气相沉积、物理气相沉积、真空蒸镀、磁控溅射、原子层沉积或其它方式在衬底1的表面形成掩膜层，掩膜层可为多层膜层结构，也可以为单层膜层结构，其材料可以是聚合物、SiO 2、SiN、多晶硅和SiCN中至少一种，当然，也可以是其它材料，在此不再一一列举。
在一些实施方式中，掩膜层可为多层，其可以包括聚合物层、氧化层和硬掩膜层，其中，聚合物层可形成于衬底1的表面，氧化层可位于硬掩膜层和聚合物层之间。可通过化学气相沉积工艺在衬底1的表面形成聚合物层，通过真空蒸镀工艺在聚合物层的表面形成氧化层，通过原子层沉积工艺在氧化层的表面形成硬掩膜层。
步骤S2102，在所述掩膜层的表面形成第一光阻层。
可通过旋涂或其它方式在掩膜层背离衬底1的表面形成第一光阻层，第一光阻层的材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。
步骤S2103，对所述第一光阻层进行曝光并显影，以形成多个沿第一方向A延伸并沿第二方向B间隔分布的显影区，所述显影区在所述衬底1上的正投影贯穿所述阵列区101和所述外围区102。
可采用掩膜版对第一光阻层进行曝光，该掩膜版的图案可与字线沟槽201所需的图案匹配。随后，可对曝光后的第一光阻层进行显影，从而形成多个沿第一方向A延伸并沿第二方向B间隔分布的显影区，每个显影区均可分别露出掩膜层的表面，显影区的图案可与字线沟槽201所需的图案相同，显影区的尺寸可与字线沟槽201所需的尺寸相同，即，显影区可呈条状，且其在衬底1上的正投影可贯穿阵列区101和外围区102。在本公开的一些实施方式中，显影区在衬底1上的正投影可贯穿外围区102及多个有源区12。
步骤S2104，在所述显影区对所述掩膜层及所述衬底1进行蚀刻，以形成多个沿第一方向A延伸并沿第二方向B间隔分布的字线沟槽201。
可通过非等向蚀刻工艺在各显影区对掩膜层进行蚀刻，蚀刻区域可露出衬底1，从而在掩膜层上形成多个掩膜图案，掩膜图案可呈条形，且各掩膜图案在衬底1上的正投影可分别贯穿阵列区101和外围区102。在本公开的一些实施方式中，显影区在衬底1上的正投影可贯穿多个有源区12。举例而言，掩膜图案可为沿第一方向A延伸的条形图案，多个掩膜图案可沿第二方向B间隔分布。
需要说明的是，当掩膜层为单层结构时，可采用一次蚀刻工艺形成掩膜图案，当掩膜层为多层结构时，可对各膜层进行分层蚀刻，即：一次蚀刻工艺可蚀刻一层，可采用多次蚀刻工艺将掩膜层刻透，以形成掩膜图案，在一实施方式中，掩膜图案的形状和尺寸可与各字线沟槽201所需的图案和尺寸相同。
需要说明的是，在完成上述蚀刻工艺后，可通过清洗液清洗或通过灰化等工艺去除第一光阻层，使具有掩膜图案的掩膜层不再被第一光阻层覆盖。
可采用具有掩膜图案的掩膜层为掩膜，进而对衬底1进行非等向蚀刻，以便形成多个沿第一方向A延伸且沿第二方向B间隔分布的字线沟槽201。
步骤S220，在所述字线沟槽201内形成随形贴附于所述字线沟槽201的侧壁的栅间介质层23。
继续参见图2及图3所示，可在各字线沟槽201内均形成字线结构2，即，可在衬底1内形成多个字线结构2，各字线结构2均可沿第一方向A延伸，多个字线结构2可沿第二方向B间隔分布。
在本公开的一些实施方式中，字线结构2可贯穿阵列区101和外围区102，举例而言，各字线结构2均可由外围区102向阵列区101延伸，且其在阵列区101的部分可贯穿多个有源区12。
继续参见图5-图7所示，可在各字线沟槽201的侧壁及表面形成随形贴附的栅间介质层23，栅间介质层23的材料可以包括氧化硅、氮化硅、氮氧化硅等，也可为前述材料的组合，其厚度可以是1nm～9nm，举例而言，其可以是1nm、2nm、4nm、6nm、8nm或9nm，当然，也可以是其他厚度，在此不再一一列举。
举例而言，可通过化学气相沉积、物理气相沉积、原子层沉积、热蒸发或热氧化等方式在各字线沟槽201的侧壁及底部形成随形贴附的栅间介质层23，当然，也可通过其他方式形成栅间介质层23，在此不做特殊限定。为了工艺方便，在形成栅间介质层23的过程中，可使栅间介质层23完全覆盖衬底1的顶表面，随后可去除位于衬底1的顶表面的栅间介质层23，只保留位于各字线沟槽201的侧壁及底部的栅间介质层23。
在本公开的一些实施方式中，可采用热氧化工艺对栅间介质层23的表面进行处理，以提高栅间介质层23的膜层的致密性，进而减小漏电流，提高栅控能力，还可增强栅间介质层23对衬底1中杂质的阻隔效果，避免衬底1中的杂质扩散至字线沟槽201内，可提高结构稳定性。
在本公开的一些实施方式中，可在栅间介质层23表面形成扩散阻挡层，用于避免金属材料向衬底1扩散，增大漏电流风险。扩散阻挡层可随形贴附于栅间介质层23的表面，即，栅间介质层23可位于扩散阻挡层与字线沟槽201的内壁之间，扩散阻挡层的材料可以是氮化钛，其厚度可以是0.5nm～2nm，例如，其可以是0.5nm、1nm、1.5nm或2nm。在一些实施方式中，可以通过化学气相沉积、物理气相沉积或原子层沉积等工艺在栅间介质层23的表面形成扩散阻挡层，在此不对扩散阻挡层的成型工艺做特殊限定。
步骤S230，在具有所述栅间介质层23的所述字线沟槽201内形成所述第一导电层21。
在本公开的一种示例性实施方式中，可采用化学气相沉积、物理气相沉积、原子层沉积、真空蒸镀、磁控溅射或热蒸发等方式在形成有栅间介质层23的字线沟槽201内填充导电材料，以在字线沟槽201内形成第一导电层21。
需要说明的是，在栅间介质层23的表面形成有扩散阻挡层时，第一导电层21可形成于扩散阻挡层的表面，即，可在形成有栅间介质层23及扩散阻挡层的字线沟槽201内填充导电材料，以在字线沟槽201内形成第一导电层21。
在本公开的一种示例性实施方式中，在具有所述栅间介质层23的所述字线沟槽201内形成第一导电层21(即，步骤S230)可包括步骤S2301-步骤S2305，其中：
步骤S2301，在所述衬底1的表面形成导电材料层210，所述导电材料层210填满具有所述栅间介质层23的所述字线沟槽201。
参见图15及图16所示，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、原子层沉积或热蒸发等方式在各具有栅间介质层23的字线沟槽201内分别 填充导电材料，当然，也可采用其他方式在各具有栅间介质层23的字线沟槽201内分别填充导电材料。导电材料可填满各字线沟槽201，进而形成导电材料层210。
步骤S2302，在所述导电材料层210的表面形成第二光阻层4，所述第二光阻层4在所述衬底1上的正投影与所述外围区102重合。
参见图17及图18所示，可通过旋涂或其它方式在导电材料层210的表面形成第二光阻层4，第二光阻层4的材料可以是正性光刻胶或负性光刻胶，在此不做特殊限定。需要说明的是，第二光阻层4可覆盖于外围区102的表面，且其在衬底1上的正投影可与外围区102的边界重合。
步骤S2303，以所述第二光阻层4为掩膜蚀刻部分位于所述阵列区101的所述导电材料层210，至所述阵列区101的所述导电材料层210的表面与所述衬底1的表面齐平。
参见图19所示，可采用干法蚀刻工艺对未被第二光阻层4覆盖的导电材料层210进行蚀刻，并在未被第二光阻层4覆盖的导电材料层210的表面与衬底1的表面齐平时停止蚀刻，此时，未被光阻层覆盖的区域的导电材料层210的表面低于被第二光阻层4覆盖的区域的导电材料层210的表面，即，位于阵列区101的导电材料层210的表面低于位于外围区102的导电材料层210的表面。在本公开的一些实施方式中，干法蚀刻的蚀刻气体可为四氟化碳，当然，蚀刻气体还可以是其他气体，只要能将导电材料层210去除，且不损伤其他结构即可，在此不再一一列举。
步骤S2304，去除所述第二光阻层4。
可通过清洗液清洗或通过灰化等工艺去除第二光阻层4，使经过蚀刻后的导电材料层210不再被第二光阻层4覆盖。
步骤S2305，蚀刻剩余的所述导电材料层210，直至位于所述外围区102的所述导电材料层210的表面低于所述衬底1的表面。
可对剩余的导电材料层210进行回蚀刻，直至位于外围区102的衬底1表面的导电材料层210被完全清除，且在回蚀刻过程中可使字线沟槽201中的导电材料层210的表面低于衬底1的表面，以便于后续对第一导电层21表面进行绝缘隔离，避免第二导电层22与周围其他结构之间发生耦合或短路。可将回蚀刻后剩余的导电材料层210定义为第一导电层21。
在本公开的一些实施方式中，可采用干法蚀刻的方式进行回蚀刻，其实可气体可为四氟化碳或其他可将导电材料层210去除且不损伤其他结构的气体。
步骤S240，在所述第一导电层21的表面形成所述第二导电层22。
可采用物理气相沉积、化学气相沉积、原子层沉积、真空蒸镀或磁控溅射等工艺在第一导电层21的表面形成第二导电层22，第二导电层22可覆盖于位于阵列区101的第一导电层21的表面，第二导电层22在衬底1上的正投影与外围区102无交叠，且第二导电层22在衬底1上的正投影可与阵列区101的边界重合。
在本公开的一种示例性实施方式中，继续参见图2及图3所示，第二导电层22的厚度可与阵列区101的第一导电层21和外围区102的第一导电层21的高度差相等，即，第二导电层22的表面可与外围区102的第一导电层21的表面齐平，第二导电层22只覆盖于第一导电层21位于阵列区101的部分的表面。此时，相比于现有技术(第二导电层22覆盖第一导电层21的全部表面)，在第二导电层22和第一导电层21组成的整体结构所占的空间相同的情况下，本公开中的字线结构2中的第一导电层21的占比增多，由于第一导电层21的材料为金属材料，可提高金属材料在字线结构2中的占比，有助于减小字线结构2的电阻。
在本公开的一种示例性实施方式中，在所述第一导电层的表面形成所述第二导电层22(即，步骤S240)可包括步骤S310及步骤S320，其中：
步骤S310，在所述字线结构2与所述衬底1共同构成的结构的表面形成半导体材料层310。
参见图20及图21所示，可采用物理气相沉积、化学气相沉积、原子层沉积、真空蒸镀或磁控溅射等工艺在字线结构2和衬底1共同构成的结构的表面形成半导体材料层310，半导体材料层310的厚度可大于位于阵列区101的字线结构2的表面与衬底1表面的高度差，即，半导体材料层310可填满各字线沟槽201并可铺满衬底1的整个表面。
步骤S320，去除位于所述字线沟槽201外的所述半导体材料层310，并继续去除部分所述半导体材料层310，至位于所述阵列区101的所述半导体材料层310的表面与位于所述外围区102的所述字线结构2的表面齐平。
继续参见图2及图3所示，可对半导体材料层310进行回蚀刻，直至位于外围区102表面的半导体材料层310被完全清除，且在回蚀刻过程中，可使位于阵列区101的半导体材料层310的表面与位于外围区102的字线结构2的表面齐平。可将回蚀刻后剩余的半导体材料层310定义为第二导电层22。
在本公开的一种示例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S130，在所述字线结构2的顶部形成绝缘层5，所述绝缘层5在所述衬底1上的正投影覆盖各所述字线结构2在所述衬底1上的正投影。
继续参见图9及图10所示，绝缘层5可以是形成于字线结构2的表面的薄膜，也可以是形成于字线结构2的表面的涂层，在此不对绝缘层5的形式做特殊限定。绝缘层5在衬底1上的正投影可覆盖各字线结构2在衬底1上的正投影。可通过绝缘层5对字线结构2的表面进行绝缘保护，以避免字线结构2的表面损伤；同时，还可通过绝缘层5将字线结构2与其他结构隔绝开，避免字线结构2与其他结构之间发生耦合或短路，可提高产品良率。
在本公开的一些实施方式中，绝缘层5可同时覆盖第二导电层22的表面和位于外围区102表面的第一导电层21的表面，即，绝缘层5可覆盖第一导电层21和第二导电层22共同构成的结构的表面。可通过绝缘层5对第一导电层21和第二导电层22进行绝缘保护，以避免第一导电层21和第二导电层22的表面损伤；同时，还可通过绝缘层5将第一导电层21和第二导电层22与其他结构隔绝开，避免第一导电层21和第二导电层22与其他结构之间发生耦合或短路，可提高产品良率。
举例而言，绝缘层5的材料可为氮化硅或其他绝缘材料，可通过化学气相沉积、物理气相沉积、原子层沉积、热蒸发、真空蒸镀或磁控溅射等方式在第一导电层21和第二导电层22共同构成的结构的表面形成绝缘层5，当然，也可通过其他方式形成绝缘层5，在此不对绝缘层5的形成方式做特殊限定。
在本公开的一种示例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S140，在所述外围区102形成字线接触插塞6，所述字线接触插塞6的底面与所述第一导电层21连接。
继续参见图11及图12所示，字线接触插塞6可形成于外围区102，即，第二导电层22在衬底1上的正投影与字线接触插塞6在衬底1上的正投影无交叠。且第二导电层22可与字线接触插塞6间隔分布，例如，第二导电层22靠近外围区102的一端可与字线接触插塞6之间具有第一距离，第一距离可小于第一导电层21在第一方向A上位于外围区102的长度，有助于使字线导电插塞6与第一导电层21位于外围区102的部分与第二导电层22隔离设置，避免字线导电插塞6的形成对第二导电层22造成损伤。
继续参见图12所示，字线接触插塞6的底面可与位于外围区102的第一导电层21的表面接触连接，以便于通过字线接触插塞6将字线结构2电学引出，进而可通过字线接触插塞6将字线结构2中的数据信号引出。
在本公开的一些实施方式中，字线接触插塞6的一侧与字线结构2连接，另一侧可通过外围接触插塞7与字线驱动器、感测放大器、行解码器和列解码器以及特殊功能的控制电路连接，控制电路通过字线接触插塞6电流传送可实现控制字线结构2及位线结构，实现晶体管及电容的存储及读取功能。
在本公开的一些实施方式中，继续参见图12所示，字线接触插塞6可沿垂直于衬底1的方向贯穿绝缘层5，即，字线接触插塞6可埋于绝缘层5内，可通过绝缘层5对字线接触插塞6进行绝缘保护，在此过程中，可避免字线接触插塞6与周围其他结构之间发生耦合或短路，可进一步提高产品良率。
在本公开的一些实施方式中，在所述外围区102形成字线接触插塞6，所述字线接触插塞6的底面与所述第一导电层21连接(即，步骤S140)可包括步骤S1401及步骤S1402，其中：
步骤S1401，形成贯穿所述绝缘层5的第一接触孔601，所述第一接触孔601露出所述字线结构2。
参见图22及图23所示，可通过蚀刻工艺在外围区102形成第一接触孔601，第一接触孔601可露出字线结构2，当然，也可通过其他方式形成第一接触孔601，在此不对第一接触孔601的形成方式做特殊限定。
需要说明的是，由于第一接触孔601形成于外围区102，而字线结构2位于外围区102的部分的表面未被第二导电层22覆盖，在蚀刻形成第一接触孔601的过程中，无需穿过第二导电层22，进而无需采用对第二导电层22的蚀刻速率较大的蚀刻溶液或蚀刻气体进行蚀刻，可避免在蚀刻第二导电层22的过程中对衬底1造成的损伤，也可避免蚀刻损伤延伸至阵列区101内部，减小衬底1中的缺陷来源，提高产品良率。且在上述过程中，由于外围区102的字线结构2的表面没有第二导电层22，在形成第一接触孔601的过程中，无需蚀刻第二导电层22，可减少蚀刻的层数，进而简化工艺(即，减少了蚀刻第二导电层22的工艺)，降低制造成本；同时，由于第一导电层21的高度提高，减小过孔蚀刻高度，可降低工艺难度。
第一接触孔601可为圆形孔、椭圆形孔、矩形孔或其他形状的孔状结构，在此不对第一接触孔601的形状做特殊限定，只要能露出字线结构2即可。第一接触孔601的数量可为多个，例如，第一接触孔601的数量可与字线结构2的数量相等，各第一接触孔601可一一对应的露出各字线结构2。
步骤S1402，在所述第一接触孔601内填充金属导电材料，以形成所述字线接触插塞6。
可分别向各第一接触孔601内填充金属导电材料，进而在各第一接触孔601内分别形成子电路，各子电路共同构成字线接触插塞6。举例而言，可通过电镀、真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、原子层沉积或热蒸发等工艺在各第一接触孔601内分别填充第一导电材料，进而形成字线接触插塞6。
在本公开的一些实施方式中，金属导电材料可为氮化钛或钨，当然也可以是其他导电性能较强的材料，在此不再一一列举。
在本公开的一种示例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S150，在所述外围区102形成外围接触插塞7，所述外围接触插塞7与所述字线接触插塞6电连接，且在垂直于所述衬底1的方向上，所述外围接触插塞7的顶面与所述字线接触插塞6的顶面高度相同。
继续参见图13所示，外围接触插塞7可位于外围区102，外围接触插塞7的一 端可与外围区102内的晶体管的源漏极110连接；在垂直于衬底1的方向上，外围接触插塞7可贯穿绝缘层5，并可与字线接触插塞6间隔分布，外围接触插塞7的顶面可与字线接触插塞6的顶面高度相同。
在本公开的一些实施方式中，外围接触插塞7可通过位于绝缘层5表面的连接线与字线接触插塞6电连接，进而实现外围电路对阵列区101中的各部件的控制。
在本公开的一些实施方式中，在所述外围区102形成外围接触插塞7，所述外围接触插塞7与所述字线接触插塞6电连接，且在垂直于所述衬底1的方向上，所述外围接触插塞7的顶面与所述字线接触插塞6的顶面高度相同(即，步骤S150)可包括步骤S1501及步骤S1502，其中：
步骤S1501，形成贯穿所述绝缘层5的第二接触孔701，所述第二接触孔701露出所述外围区102的晶体管的源漏极110。
如图24所示，可通过蚀刻工艺对位于外围区2的绝缘层5进行蚀刻，进而在外围区102形成第二接触孔701，第二接触孔701可露出外围区102的晶体管的源漏极110，当然，也可通过其他方式形成第二接触孔701，在此不对第二接触孔701的形成方式做特殊限定。
第二接触孔701可为圆形孔、椭圆形孔、矩形孔或其他形状的孔状结构，在此不对第二接触孔701的形状做特殊限定，只要能露出外围区102的晶体管的源漏极100即可。第二接触孔701的数量可为多个，例如，第二接触孔701的数量可与外围区102的晶体管的数量相等，各第二接触孔701可一一对应的露出外围区102的各晶体管的源漏极110。
步骤S1402，在所述第二接触孔701内填充第二导电材料，以形成所述外围接触插塞7。
可分别向各第二接触孔701内填充第二导电材料，进而在各第二接触孔701内分别形成子电路，各子电路共同构成外围接触插塞7。举例而言，可通过电镀、真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积、原子层沉积或热蒸发等工艺在各第二接触孔701内分别填充第二导电材料，进而形成外围接触插塞7。
在本公开的一些实施方式中，第二导电材料与第一导电材料可以相同，也可以不同，在此不做特殊限定。举例而言，第二导电材料可为氮化钛或钨，当然，也可以是其他导电性能较强的材料，在此不再一一列举。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体结构的形成方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施例还提供一种存储器，该存储器可包括由上述任一实施例中的半导体结构，其具体细节、形成工艺以及有益效果已经在对应的半导体结构及半导体结构的形成方法中进行了详细说明，此处不再赘述。
举例而言，该存储器可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。当然，还可以是其它存储装置，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种半导体结构，其中，包括：
    衬底，包括阵列区和外围区；
    字线结构，包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
  2. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    字线接触插塞，位于所述外围区，且所述字线接触插塞的底面与所述第一导电层连接。
  3. 根据权利要求2所述的半导体结构，其中，所述字线结构还包括：
    第二导电层，所述第二导电层位于所述第一导电层上部，所述第二导电层在所述衬底上的正投影与所述字线接触插塞在所述衬底上的正投影无交叠。
  4. 根据权利要求3所述的半导体结构，其中，所述第二导电层靠近所述外围区的一端与所述字线接触插塞之间具有第一距离，所述第一距离小于所述第一导电层在所述第一方向上位于所述外围区的长度。
  5. 根据权利要求3所述的半导体结构，其中，所述第一导电层位于所述外围区的表面与所述第二导电层的表面齐平。
  6. 根据权利要求3所述的半导体结构，其中，所述第一导电层的材料为金属材料，所述第二导电层的材料为半导体材料。
  7. 根据权利要求3所述的半导体结构，其中，所述半导体结构还包括：
    外围接触插塞，位于所述外围区，并与所述字线接触插塞电连接，且在垂直于所述衬底的方向上，所述外围接触插塞的顶面与所述字线接触插塞的顶面高度相同。
  8. 根据权利要求3-7任一项所述的半导体结构，其中，所述字线结构还包括栅间介质层，所述栅间介质层至少随形包覆于所述第一导电层和所述第二导电层的侧壁表面。
  9. 一种半导体结构的形成方法，其中，包括：
    提供衬底，所述衬底包括阵列区和外围区；
    在所述衬底内形成多个字线结构，所述字线结构包括位于所述衬底内部的第一导电层，所述第一导电层沿第一方向贯穿所述阵列区并延伸至所述外围区；在垂直于所述衬底的方向上，所述第一导电层位于所述外围区表面的高度高于所述第一导电层位于所述阵列区表面的高度。
  10. 根据权利要求9所述的形成方法，其中，所述形成方法还包括：
    在所述外围区形成字线接触插塞，所述字线接触插塞的底面与所述第一导电层连接。
  11. 根据权利要求10所述的形成方法，其中，所述形成方法还包括：
    在所述第一导电层的上部形成第二导电层，所述第二导电层在所述衬底上的正投影与所述字线接触插塞在所述衬底上的正投影无交叠。
  12. 根据权利要求11所述的形成方法，其中，所述第二导电层靠近所述外围区的一端与所述字线接触插塞之间具有第一距离，所述第一距离小于所述第一导电层在所述第一方向上位于所述外围区的长度。
  13. 根据权利要求11所述的形成方法，其中，所述第一导电层位于所述外围区的表面与所述第二导电层的表面齐平。
  14. 根据权利要求11所述的形成方法，其中，所述第一导电层的材料为金属材料，所述第二导电层的材料为半导体材料。
  15. 根据权利要求11所述的形成方法，其中，所述形成方法还包括：
    在所述外围区形成外围接触插塞，所述外围接触插塞与所述字线接触插塞电连接，且在垂直于所述衬底的方向上，所述外围接触插塞的顶面与所述字线接触插塞的顶面高度相同。
  16. 根据权利要求11-15任一项所述的形成方法，其中，所述字线结构还包括栅间介质层，所述栅间介质层至少随形包覆于所述第一导电层和所述第二导电层的侧壁表面。
  17. 根据权利要求16所述的形成方法，其中，在所述衬底内形成多个字线结构，包括：
    在所述衬底内形成多个字线沟槽，所述字线沟槽贯穿所述阵列区和所述外围区；
    在所述字线沟槽内形成随形贴附于所述字线沟槽的侧壁的栅间介质层；
    在具有所述栅间介质层的所述字线沟槽内形成所述第一导电层；
    在所述第一导电层的表面形成所述第二导电层。
  18. 根据权利要求17所述的形成方法，其中，在具有所述栅间介质层的所述字线沟槽内形成所述第一导电层，包括：
    在所述衬底的表面形成导电材料层，所述导电材料层填满具有所述栅间介质层的所述字线沟槽；
    在所述导电材料层的表面形成第二光阻层，所述第二光阻层在所述衬底上的正投影与所述外围区重合；
    以所述第二光阻层为掩膜蚀刻部分位于所述阵列区的所述导电材料层，至所述阵列区的所述导电材料层的表面与所述衬底的表面齐平；
    去除所述第二光阻层；
    蚀刻剩余的所述导电材料层，直至位于所述外围区的所述导电材料层的表面低于所述衬底的表面且高于位于所述阵列区的所述导电材料层的表面。
  19. 根据权利要求17所述的形成方法，其中，在所述第一导电层的表面形成所述第二导电层，包括：
    在所述栅间介质层、所述第一导电层及所述衬底共同构成的结构的表面形成半导体材料层；
    去除位于所述字线沟槽外的所述半导体材料层，并继续去除部分所述半导体材料层，至位于所述阵列区的所述半导体材料层的表面与位于所述外围区的所述第一导电层的表面齐平。
  20. 一种存储器，包括权利要求1-8任一项所述的半导体结构。
PCT/CN2022/124203 2022-08-09 2022-10-09 半导体结构及其形成方法、存储器 Ceased WO2024031818A1 (zh)

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