Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/419—Read-write [R-W] circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/418—Address circuits

Definitions

• the present disclosure relates to a semiconductor memory device.
• Patent Document 1 discloses a semiconductor memory device having a multi-bank SRAM divided into multiple banks and an assist circuit commonly connected to the multiple banks.
• the write assist level (negative potential) is optimized by changing the number of banks when writing to SRAM.
• the present disclosure aims to achieve an optimal write assist level and normal writing with a small area circuit in a semiconductor memory device with a multi-bank configuration, even if the bank sizes are different.
• One aspect of the present disclosure includes a first memory bank and a second memory bank each having a plurality of memory cells, and the plurality of memory cells are connected to corresponding word lines and bit line pairs, respectively, and the first memory bank and the second memory bank each have a plurality of memory cells.
• a memory cell array in which the number of word lines in the first memory bank is smaller than the number of word lines in the second memory bank, and a function of lowering the potential of one bit line of a bit line pair connected to the memory cell to be written.
• a write circuit that sets the bit line on the low potential side to a negative potential by a capacitor connected to the internal ground line in response to a negative potential boost signal, and the capacitor is respectively connected to the internal ground line.
• the bit line on the low potential side is brought to a negative potential only by the first capacitive element;
• the bit line on the low potential side is brought to a negative potential by the first capacitor and the second capacitor.
• the bit line on the low potential side is brought to a negative potential only by the first capacitor, and the bit line on the low potential side is set to a negative potential.
• the bit line on the low potential side is set to a negative potential by both the first capacitor and the second capacitor.
• Functional block diagram showing a configuration example of a semiconductor memory device A diagram showing an example of the circuit configuration of the memory cell in FIG. 1. Diagram showing an example of the circuit configuration of the write circuit Timing chart showing an example of operation of a semiconductor storage device
• the semiconductor memory device 1 includes a memory cell array 2 and a read/write circuit 3.
• the memory cell array 2 includes a first memory bank 21 and a second memory bank 22.
• the first memory bank 21 includes a plurality of memory cells arranged in an array of [number of columns c (c is a natural number) x number of rows w-mr (w is a natural number) x number of sets b (b is a natural number)]. It includes a memory cell MC. That is, the first memory bank 21 has a configuration in which b sets of c columns of memory cells are lined up in the column direction, and there are [c ⁇ b] columns in total, and [c ⁇ (w-mr) ⁇ b] memory cells. It includes a memory cell MC. Further, in the first memory bank 21, [w ⁇ mr] is the number of rows.
• the first memory bank 21 includes a plurality of word lines WL ([w-mr] in FIG. 1) extending in the row direction and a plurality ([c ⁇ b] in FIG. 1) of bit line pairs TBLT( bit lines BLT, NBLT). Each memory cell MC is connected to a word line WL and a bit line pair TBLT at a position corresponding to the arrangement position.
• the second memory bank 22 includes a plurality of memory cells arranged in an array of [number of columns c (c is a natural number) x number of rows mr (mr is a natural number) x number of groups b (b is a natural number)]. Equipped with MC. That is, the second memory bank 22 has a configuration in which b sets of c columns of memory cells are lined up in the column direction, and there are a total of [c ⁇ b] columns and [c ⁇ mr ⁇ b] memory cells MC. Be prepared. Furthermore, in the second memory bank 22, mr is the number of rows.
• the second memory bank 22 includes a plurality of word lines WL extending in the row direction (mr in FIG. 1) and a plurality of bit line pairs TBLB ([c ⁇ b] in FIG. 1) extending in the column direction crossing the row direction. Equipped with Each memory cell MC is connected to a word line WL and a bit line pair TBLB (bit lines BLB, NBLB) at a position corresponding to the arrangement position.
• the number of word lines in the first memory bank 21 is smaller than the number of word lines in the second memory bank 22. That is, in the example of FIG. 1, the number of memory cells MC has a relationship of [mr>(w-mr)], and the number of rows in the first memory bank 21 is equal to the number of rows in the second memory bank 22. Fewer. In other words, the load capacitance of the bit line pair TBLT of the first memory bank 21 is smaller than the load capacitance of the bit line pair TBLB of the second memory bank 22.
• the word line WL is connected to a row decoder (not shown).
• the row decoder activates the word line WL of the row including the memory cell MC to be operated in accordance with a row address specified by the CPU (not shown).
• the bit line pair TBLT of the first memory bank 21 and the bit line pair TBLB of the second memory bank 22 are connected to read/write circuits 3 provided at corresponding positions, respectively.
• the read/write circuit 3 will be explained later.
• bit lines BLB and BLT may be simply referred to as “bit lines BL” without distinguishing them.
• bit lines NBLB and NBLT may be simply referred to as “bit line NBL” without distinction
• bit line pair TBLB and TBLT may be simply referred to as “bit line pair TBL” without distinction.
• FIG. 2 is a circuit diagram showing the internal configuration of memory cell MC in FIG. 1.
• memory cell MC includes N-type transistors NA1 and NA2, P-type transistors PL1 and PL2, and N-type transistors ND1 and ND2.
• the N-type transistor NA1 has a gate connected to the word line WL and a source connected to the bit line BL.
• the N-type transistor NA2 has a gate connected to the word line WL and a source connected to the bit line NBL.
• the P-type transistor PL1 has a source supplied with the power supply voltage VDD, and a drain connected to the drain of the N-type transistor NA1.
• the N-type transistor ND1 has a gate connected to the gate of the P-type transistor PL1, a drain connected to the drain of the P-type transistor PL1, and a source connected to the ground potential VSS.
• the P-type transistor PL2 has a gate connected to the drain of the N-type transistor NA1, a source supplied with the power supply voltage VDD, and a drain connected to the drain of the N-type transistor NA2.
• the N-type transistor ND2 has a gate connected to the gate of the P-type transistor PL2, a drain connected to the drain of the P-type transistor PL2, and a source connected to the ground potential VSS.
• a connection node between the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 is connected to the drain of the N-type transistor NA2.
• the first inverter is configured by the P-type transistor PL1 and the N-type transistor ND1.
• a second inverter is configured by the P-type transistor PL2 and the N-type transistor ND2.
• a latch circuit is configured by connecting the input terminal of the first inverter to the output terminal of the second inverter, and connecting the output terminal of the first inverter to the input terminal of the second inverter.
• a read/write circuit 3 is provided between the first memory bank 21 and the second memory bank 22.
• the read/write circuit 3 is provided for each memory cell in column c, and there are b in total.
• the read/write circuit 3 includes a write circuit 30.
• the write circuit 30 has a first function of lowering the potential of one bit line (BL or NBL) of the bit line pair TBL connected to the memory cell MC to be written, and a negative potential boost signal NWACP0, NWACP1, which will be described later. Accordingly, it has a second function of setting the bit line (BL or NBL) on the low potential side to a negative potential by a capacitor connected to the internal ground line WGND.
• FIG. 3 is a circuit diagram showing a configuration example of the write circuit 30. Note that the configuration of the write circuit 30 is not limited to the configuration shown in FIG. 3, and may be any other circuit configuration having the above-described first function and second function.
• the write circuit 30 includes a write circuit for the first memory bank 21 (precharge circuit 31T, write driver 32T, column selection circuit 33T) and a write circuit for the second memory bank 22 (precharge circuit 31T, write driver 32T, column selection circuit 33T).
• a charge circuit 31B, a write driver 32B, a column selection circuit 33B), and a write assist circuit 36 are provided.
• the precharge circuit 31T precharges the bit lines BLT and NBLT using a precharge signal PCGT (hereinafter referred to as "PCGT signal”).
• PCGT signal a precharge signal
• PCGB signal a precharge signal PCGB
• the write driver 32T outputs write data WD[x] or NWD[x] (x is an integer greater than or equal to 0) based on a write control signal WRITET (hereinafter referred to as "WRITET signal”).
• the write driver 32B outputs write data WD[x] or NWD[x] (x is an integer greater than or equal to 0) based on a write control signal WRITEB (hereinafter referred to as "WRITEB signal”).
• NWD[x] is an inverted signal of WD[x]. In the following description, the write data signal WD will be simply written as "WD”, and the write data signal NWD will be simply written as "NWD”.
• the column selection circuits 33T and 33B have a function of selecting a column to be written, based on the column selection signal CAD[0:c-1].
• the column selection circuit 33T operates the transistor TN0 based on the output of the write driver 32T and the column selection signal CAD[0:c-1], which is connected between the bit line BLT and the internal ground line WGND. transistors TP3 and TN2.
• the column selection circuit 33B operates the transistor TN10 based on the output of the write driver 32B and the column selection signal CAD[0:c-1], which is connected between the bit line BLB and the internal ground line WGND. transistors TP8 and TN4.
• the write assist circuit 36 uses a capacitor to set the bit line on the low potential side to a negative potential in response to negative potential boost signals NWACP0 and NWACP1 generated based on the write assist control signal NWTA (hereinafter referred to as "NWTA signal").
• NWTA signal the write assist control signal
• the capacitance is determined by a first capacitive element PCAP0 that functions when writing to the first memory bank 21 and a second capacitive element that functions when writing to both the first memory bank 21 and the second memory bank 22. and a capacitive element PCAP1.
• the first capacitive element PCAP0 is a MOS type capacitive element provided between the negative potential boost signal line NWACP0 and the internal ground line WGND.
• Negative potential boost signal NWACP0 is a signal that similarly changes according to the NWTA signal.
• the second capacitive element PCAP1 is a MOS type capacitive element provided between the negative potential boost signal line NWACP1 and the internal ground line WGND.
• the negative potential boost signal NWACP1 is a signal that changes so as to cause the second capacitive element PCAP1 to function only when the NWTA signal is 'L' and the WRITEB signal is 'H'.
• both the first capacitive element PCAP0 and the second capacitive element PCAP1 are connected to the internal ground. Charges are discharged so that the line WGND has a negative potential.
• the capacitance value of the first capacitive element PCAP0 can be adjusted so that the bit line BLT or bit line NBLT has an optimal negative potential when writing to the first memory bank 21.
• the capacitance value of the second capacitive element PCAP1 is determined by adding the capacitance value of the first capacitive element PCAP0 and the capacitive value of the second capacitive element PCAP1 when writing to the second memory bank 22.
• the bit line BLB or bit line NBLB can be adjusted to have an optimal negative potential. That is, the transistors forming the first capacitive element PCAP0 and the second capacitive element PCAP1 can be optimized according to the number of rows of the first memory bank 21 and the second memory bank 22, respectively.
• the first capacitive element PCAP0 and the second capacitive element PCAP1 have a combined capacity sufficient to optimize the negative potential of the mr row of the second memory bank 22. Thereby, the area of the semiconductor memory device 1 can be reduced.
• PMOS is used as the first capacitive element PCAP0 and the second capacitive element PCAP1, but the present invention is not limited to this.
• NMOS or other capacitive elements may be used.
• the gate side of the first capacitive element PCAP0 and the second capacitive element PCAP1 is connected to the internal ground line WGND, the source/drain side may be connected to the internal ground line WGND.
• the NWTA signal is 'H'. Further, in the initial state, the WRITET signal, WRITEB signal, PCGT signal, PCGB signal, and CAD[0] are 'L'.
• both BLT[0] and NBLT[0] are precharged to 'H'.
• BLT[0] is shown by a thick solid line
• NBLT[0] is shown by a thin solid line.
• the NWTA signal is 'H'
• the internal ground signal WGND becomes 'L (0V)' by the transistor TDN0, and the sources/drains of the first capacitive element PCAP0 and the second capacitive element PCAP1 are charged to 'H'.
• control signals WL[w-1], PCGT signal, WRITET signal, and CAD[0] rise from 'L' to 'H'.
• the timing of the NWTA signal is adjusted so that it falls from 'H' to 'L' when the bit line BLT[0] has sufficiently fallen to the ground potential VSS. Therefore, after the bit line BLT[0] falls to the ground potential VSS, the NWTA signal changes from 'H' to 'L', the transistor TDN0 is turned off, and the internal ground signal WGND is in a floating state at the ground potential VSS. become.
• the NWTA signal changes from 'H' to 'L'
• the NWACP0 signal changes from 'H' to 'L'
• the source/drain of the first capacitive element PCAP0 is discharged, and the internal ground signal WGND becomes negative. Becomes electric potential.
• the WRITEB signal remains 'L'
• the NWACP1 signal remains 'H', and the source/drain of the second capacitive element PCAP1 is not discharged.
• the capacitance value of the first capacitive element PCAP0 is adjusted so that the bit line (here, BLT) of the first memory bank 21 has an optimal negative potential. Writing to the target memory cell MC is performed normally. Furthermore, it is possible to prevent erroneous writing to memory cells MC that are not targeted for writing.
• the NWTA signal is 'H'. Further, in the initial state, the WRITET signal, WRITEB signal, PCGT signal, PCGB signal, and CAD[0] are 'L'.
• both BLB[0] and NBLB[0] are precharged to 'H'.
• BLB[0] is shown by a thick solid line
• NBLB[0] is shown by a thin solid line.
• the NWTA signal is 'H'
• control signals WL[0], PCGB signal, WRITEB signal, and CAD[0] rise from 'L' to 'H'.
• the timing of the NWTA signal is adjusted so that it falls from 'H' to 'L' when the bit line BLB[0] has sufficiently fallen to the ground potential VSS. Therefore, after the bit line BLB[0] falls to the ground potential VSS, the NWTA signal changes from 'H' to 'L', the transistor TDN0 is turned off, and the internal ground signal WGND is in a floating state at the ground potential VSS. become.
• the NWACP0 signal changes from 'H' to 'L', and the source/drain of the first capacitive element PCAP0 is discharged. Furthermore, since the WRITEB signal is 'H', when the NWTA signal changes from 'H' to 'L', the NWACP1 signal also changes from 'H' to 'L', and the source/drain of the second capacitive element PCAP1 is discharged. . That is, the sources/drains of the first capacitive element PCAP0 and the second capacitive element PCAP1 are discharged, and thereby the internal ground signal WGND becomes a negative potential.
• the capacitance value of the second capacitive element PCAP1 is the sum of the capacitance value of the first capacitive element PCAP0 and the capacitance value of the second capacitive element PCAP1
• the capacitance value of the second capacitive element PCAP1 is the sum of the capacitance value of the first capacitive element PCAP0 and the capacitance value of the second capacitive element PCAP1. Since the line (in this case, BLB) is adjusted to have an optimal negative potential, writing to the memory cell MC to be written in the second memory bank 22 is performed normally. Furthermore, it is possible to prevent erroneous writing to memory cells MC that are not targeted for writing.
• the bit line on the low potential side (as shown in FIG. In the example, BLT) is set to a negative potential.
• both the first capacitive element PCAP0 and the second capacitive element PCAP1 are connected to the low potential side.
• the bit line (BLB in the example of FIG. 4) is set to a negative potential.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Static Random-Access Memory (AREA)

Priority Applications (3)

Applications Claiming Priority (1)

Related Child Applications (1)

Publications (1)

Family

ID=89848743

Family Applications (1)

Country Status (3)

Citations (2)

• 2022
  • 2022-08-05 WO PCT/JP2022/030078 patent/WO2024029067A1/ja not_active Ceased
  • 2022-08-05 JP JP2024538786A patent/JPWO2024029067A1/ja active Pending
• 2025
  • 2025-01-15 US US19/022,682 patent/US20250157532A1/en active Pending

Patent Citations (2)

Also Published As

Similar Documents

Legal Events