WO2024027736A1 - 压电层设置导电通孔的石英谐振器及其制造方法、电子器件 - Google Patents

压电层设置导电通孔的石英谐振器及其制造方法、电子器件 Download PDF

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Publication number
WO2024027736A1
WO2024027736A1 PCT/CN2023/110650 CN2023110650W WO2024027736A1 WO 2024027736 A1 WO2024027736 A1 WO 2024027736A1 CN 2023110650 W CN2023110650 W CN 2023110650W WO 2024027736 A1 WO2024027736 A1 WO 2024027736A1
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electrode
quartz
piezoelectric layer
hole
packaging substrate
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PCT/CN2023/110650
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English (en)
French (fr)
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庞慰
张孟伦
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天津大学
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Publication of WO2024027736A1 publication Critical patent/WO2024027736A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/19—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/027—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the microelectro-mechanical [MEMS] type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0421—Modification of the thickness of an element
    • H03H2003/0428—Modification of the thickness of an element of an electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H3/04—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient
    • H03H2003/0414—Resonance frequency
    • H03H2003/0421—Modification of the thickness of an element
    • H03H2003/0435—Modification of the thickness of an element of a piezoelectric layer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H2009/155—Constructional features of resonators consisting of piezoelectric or electrostrictive material using MEMS techniques

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a quartz resonator in which a piezoelectric layer is provided with conductive vias, a manufacturing method thereof, and an electronic device.
  • the fundamental frequency of the chip is mainly determined by the thickness of the resonance area of the chip.
  • Wafer-level manufacturing can significantly reduce the manufacturing cost of a single resonator and achieve consistent quality control between resonators; generally speaking, the larger the wafer size, the lower the manufacturing cost of a single resonator.
  • precise control of the quartz thickness at each location is a huge challenge, which directly leads to changes in the frequency of the wafers on the entire wafer. Accuracy and consistency cannot be guaranteed. Therefore, there are great challenges in wafer-level chip frequency modulation.
  • the current methods adopted by existing technologies mainly focus on using grinding technology with ultra-high-precision film thickness monitoring systems to prepare quartz films with a thickness uniformity within a few nanometers. This frequency control and regulation technology has significant impact on materials and manufacturing processes.
  • the technology puts forward extremely high requirements, and the larger the wafer area, the higher the difficulty of manufacturing, which hinders the creation of low-cost, high-efficiency manufacturing solutions.
  • one of the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode extends through the edge of the piezoelectric layer to a position on the same side as the other electrode lead-out portion, and the electrodes are arranged across the piezoelectric layer.
  • the lead-out method is prone to the problem of unstable electrode connection resistance (too high or even disconnection of the electrical connection).
  • a quartz resonator including:
  • the resonant structure includes a quartz piezoelectric layer, a bottom electrode and a top electrode.
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode.
  • the first electrode is located on one side of the piezoelectric layer, so The second electrode is located on the other side of the piezoelectric layer;
  • the first packaging substrate and the second packaging substrate are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second electrode.
  • the first packaging substrate and the second packaging substrate are bonded to each other and define an accommodation space for accommodating the resonant structure
  • the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer so as to be on the same side of the piezoelectric layer as the second electrode.
  • the second packaging substrate is provided with an electrode lead-out portion connected to the first electrode.
  • a conductive hole penetrates the substrate for electrical connection.
  • a manufacturing method of a quartz resonator including the steps:
  • a quartz wafer including a resonant region for forming a plurality of quartz resonators
  • a resonant structure is formed.
  • the resonant structure includes a quartz piezoelectric layer, a bottom electrode and a top electrode.
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode.
  • the first electrode is in the piezoelectric layer. on one side of the piezoelectric layer, the second electrode is on the other side of the piezoelectric layer, and the piezoelectric layer of each resonance structure includes The resonance area;
  • the packaging structure includes a first packaging substrate and a second packaging substrate, which are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second packaging substrate.
  • the electrodes face each other,
  • the first packaging substrate and the second packaging substrate are bonded to each other and define an accommodation space for accommodating the resonant structure
  • the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer so as to be on the same side of the piezoelectric layer as the second electrode.
  • the second packaging substrate is provided with an electrode lead-out portion connected to the first electrode.
  • a conductive hole penetrates the substrate for electrical connection.
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned quartz resonator.
  • 1-16 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention
  • 17-25 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention.
  • Figure 26 is a schematic flow chart of fundamental frequency adjustment in the resonance area of a quartz wafer
  • Figure 27 is a schematic flow chart of the resonant frequency adjustment of the quartz resonator.
  • Top electrode the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the electrical connection part of the top electrode The material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys.
  • the top electrode and its electrical connections, the bottom electrode and its electrical connections may be the same metal material.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • Metal bonding layer which can be gold-gold, gold-tin, copper-tin bonding, etc.
  • each part is described using a feasible material as an example, but is not limited thereto.
  • FIGS. 1-16 are sections of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • Surface diagram The following is an example of the manufacturing process of a quartz resonator with reference to Figures 1-16, which includes the following steps:
  • Step 1 Make mask 20A.
  • a mask 20A is made on one side (for example, the front) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 ⁇ m to 1 mm) using micro/nano electromechanical system photolithography.
  • the mask 20A is patterned to form mask openings 22. Specifically, the area used to prepare the via hole, that is, the via hole etching area 14, and the profile etching area 18 used to form the outline are exposed.
  • a mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
  • the mask can be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal;
  • the mask can be SU-8 glue, or other photoresists suitable for dry etching.
  • the material of the mask 20A can also be applied to other embodiments, which will not be described again below.
  • FIGS. 1 to 16 only the area corresponding to a single quartz resonator on the wafer is shown. As can be understood, there are multiple quartz resonators shown in FIGS. 1 to 16 on the wafer 10 area. In other embodiments, similar understanding should be made, which will not be described again.
  • Step 2 Wet etching.
  • the mask 20A is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer. 10 is etched, and the etching depth is d 1 (d 1 is equal to the quartz film thickness d 0 corresponding to the set frequency of the quartz resonator).
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • d 1 is equal to the quartz film thickness d 0 corresponding to the set frequency of the quartz resonator.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in FIG. 3 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 4 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the top electrode 30 covers the via etching area 14, and optionally, covers a partial area between the via etching area and the frame.
  • Step 5 Join the auxiliary substrate.
  • the side of the structure in FIG. 4 where the top electrode is provided and the auxiliary substrate 80 can be joined together by, for example, adhesion or bonding.
  • the auxiliary substrate 80 may be quartz based
  • the board can also be a substrate of other materials, such as silicon, glass, sapphire, etc.
  • the bonding in step 5 is a temporary bonding, and the temporary bonding forms the temporary bonding layer 90 .
  • Step 6 Quartz wafer thinning. As shown in FIG. 6 , the quartz wafer 10 is thinned by grinding and polishing processes until the remaining thickness is within, for example, 1 ⁇ m compared to the design value (ie, the film thickness d 0 mentioned above).
  • Step 7 Wafer-level film thickness measurement.
  • the optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 7, the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 8 Adjust quartz film thickness. As shown in Figure 8, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 7 and Figure 8 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 26.
  • Step 9 Set a mask 20B on the upper surface of the structure shown in Figure 8. As shown in Figure 9, the mask 20B is patterned to provide a mask at a position corresponding to the through hole etching area 14 and the contour etching area 18. Membrane openings.
  • Step 10 For example, use dry etching to etch the portion of the quartz wafer 10 located at the through hole etching area 14 and the contour etching area 18 to penetrate the through hole etching area 14 and the contour etching area 18 , as shown in Figure 10.
  • Step 11 Remove mask 20B. After step 10, the mask 20B can be removed by wet etching to obtain the structure as shown in FIG. 11.
  • Step 12 Make the bottom electrode 40 and the electrical connection portion 32 for disposing the top electrode.
  • the electrical connection portion 32 and the bottom electrode 40 are disposed on the same side of the quartz wafer 10 and are spaced apart from each other.
  • the resonator bottom electrode 40 and the electrical connection portion 32 are fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 13 Join the second package substrate. As shown in FIG. 13 , align the quartz wafer 10 in step 12 with the quartz wafer or the second packaging substrate 60 with the second cavity 62 pre-etched, so that the bottom electrode 40 is exactly located between the second cavity 62 Inside.
  • the second packaging substrate 60 is provided with a conductive through hole 64, which can be electrically connected to the electrical connection portion 32 of the top electrode 30 through metal bonding.
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • Step 14 Remove the auxiliary substrate 80.
  • the auxiliary substrate can be removed by removing the temporary bonding layer 90 80.
  • the piezoelectric layer frame 16 is also removed, finally forming the structure as shown in Figure 14.
  • the temporary bonding layer 90 can be UV adhesive, which can be deglued and removed by UV light; or a temporary bonding technology with weak bonding force, such as oxygen plasma surface bonding, can be used after the split resonator and the substrate are metal bonded. Simply remove the temporary auxiliary base plate.
  • the resonant region of the formed resonator is a cantilever structure. More specifically, the non-electrode connection end of the main body part of the resonator is a free end.
  • This structure can produce the following technical effects: reduce the lateral leakage of energy, improve the performance of the resonator, and at the same time reduce/isolate the impact of external vibration, heat and other factors on the performance of the resonator.
  • Step 15 Frequency measurement and frequency modulation.
  • the measured resonant frequency f of the quartz resonator is smaller than the predetermined resonant frequency f 0 .
  • the quality of the top electrode 30 can be changed using particle beams to improve the quartz resonator.
  • the resonant frequency of the resonator when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 27.
  • Step 16 Join the first package substrate. As shown in FIG. 16 , align the second packaging substrate 60 in step 15 with the quartz wafer or the first packaging substrate 50 with the first cavity 52 pre-etched, so that the top electrode 30 is exactly located in the first cavity 52 within.
  • the second packaging substrate 60 and the first packaging substrate 50 can be bonded together using metal diffusion bonding (a metal bonding layer 72 is formed as shown in FIG. 16 ), which can be gold-gold, gold-tin, copper-tin bonding, etc. Way. They can also be joined together in other ways, which are not limited here.
  • a segmentation operation can be performed to form the final packaged quartz resonator into individual devices.
  • the bottom electrode can be prepared on the structure shown in Figure 8 first, and the bottom electrode 40 can be made on the quartz wafer 10 by metal sputtering or evaporation; then, the through-hole etching area 14 and Contour etching region 18; then, electrical connections 32 for the top electrode are prepared.
  • the present invention provides a wafer-level wafer manufacturing solution.
  • the above process uses a combination of wet and dry methods to thin quartz, and adopts a wafer-level frequency/thickness monitoring and control method, which reduces the requirements for uniformity of quartz wafer thickness processing and reduces processing difficulty.
  • This solution is universally applicable to the manufacturing of quartz wafers in different frequency bands, and is not limited by the area of the quartz wafer, so it has obvious advantages.
  • Figures 17-25 illustrate a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention.
  • Cross-sectional diagram The following is an example of the manufacturing process of a quartz resonator with reference to Figures 17-25, which includes the following steps:
  • Step 1 Make the mask.
  • masks 20A are made on both sides of a quartz wafer (for example, 1-8 inches in diameter and 100 ⁇ m to 1 mm in thickness) using micro/nano electromechanical system photolithography, and the masks 20A on both sides are Patterning, the part corresponding to the resonance region 12 is exposed, and the remaining parts are covered with the mask layer 20A.
  • Step 2 Wet splitting.
  • a plurality of shot particles are formed by wet etching.
  • lobed channels 18 ′ are shown.
  • Step 3 Remove mask 20A. As shown in FIG. 20 , the mask 20A is removed layer by layer using an etching solution to form particles. Optionally, the wafer after the mask 20 is removed is cleaned.
  • Step 4 Test and FM.
  • the frequency of the shot (as shown in Figure 20) is tested one by one, and then the shot is wet-etched according to the difference from the design frequency, and the thickness of the resonance area of the shot is changed to form a structure as shown in Figure 21. to adjust the shot frequency. Repeat the test-etch step several times to adjust the shot frequency.
  • Step 5 Set up the electrodes to form the shot of the resonator.
  • a top electrode 30 and a bottom electrode 40 are plated on the shot to form a quartz resonator.
  • the shot particles 10A are disposed between the bottom electrode 40 and the top electrode 30 , where: the bottom electrode is on the lower side of the shot particles, the top electrode is on the upper side of the shot particles 10A, and the electrode lead-out portion 42 of the bottom electrode 40 It covers the end surface of the shot particle 10A and extends to the upper side of the shot particle 10A so that it is located on the upper side of the shot particle 10A together with the top electrode 30 .
  • the bottom electrode 40 and the top electrode 30 and the electrode lead-out part are formed by sputtering or evaporation. More specifically, they can be first set on the shot particles shown in FIG. 21 by a mechanical mask method. A mask (not shown) having a pattern to expose areas corresponding to the bottom electrode 40 and the top electrode 30 and the electrode lead-out portions on the shot, and then the bottom electrode 40 and the top electrode are formed by sputtering or evaporation. The electrode 30 and the electrode lead-out part.
  • the above steps 1 to 5 only show a specific embodiment of the shot structure forming the resonator.
  • the shot structure of the resonator is not limited to the flat structure shown in Figure 22, but may also include a single-sided or double-sided counter-plateau structure.
  • Step 6 Arrange the shot particles formed in Step 5 onto the second packaging substrate 60 provided with the second cavity 62 and the substrate through conductive hole 64, as shown in FIG. 23 .
  • Step 7 As shown in Figure 24, a conductive part 66 is provided in the second cavity 62, and the conductive part connects the The electrode lead-out portion 32 of the first electrode is electrically connected to the substrate through conductive hole 64; the conductive portion 66 may be in the form of a ball.
  • Step 8 As shown in Figure 25, the first packaging substrate 50 provided with the first cavity 52 is joined to the second packaging substrate 60 to form a package.
  • the packaging substrate may be a quartz substrate or a substrate made of other materials, such as silicon, glass, sapphire, etc. No further details will be given in the following embodiments.
  • the packaging substrate when it is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the packaging substrate is made of transparent material. Therefore, frequency modulation can also occur after the packaging is completed, using laser to directly adjust the frequency through the transparent quartz packaging cover to adjust the frequency changes caused by packaging stress. No further details will be given in the following embodiments.
  • the first packaging substrate and the second packaging substrate are directly bonded and connected. Compared with the sandwich structure formed by the first packaging substrate, the piezoelectric layer, and the second packaging substrate, since the two packages are There is no thickness of the piezoelectric layer between the substrates, which is conducive to further achieving a low profile resonator.
  • connection between the piezoelectric layer of the finally formed resonator and the packaging substrate on both sides of the piezoelectric layer is reduced (compared to the sandwich structure in which the packaging substrate and the piezoelectric layer are bonded), so that it can Reduce the conduction of stress caused by the mechanical deformation of the wafer to the resonator to improve the anti-interference performance of the resonator.
  • the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode of the quartz resonator are on the same side of the piezoelectric layer, which is beneficial to: reducing/avoiding possible problems when the electrodes cross the piezoelectric layer.
  • the technical problem of unstable electrode resistance is beneficial to: reducing/avoiding possible problems when the electrodes cross the piezoelectric layer. The technical problem of unstable electrode resistance.
  • the piezoelectric layer of the formed resonator is provided with electrical connection through holes or through holes 14 in the non-resonant area, and the lead-out portion of the electrode on the piezoelectric layer side passes through the The electrical connection via extends to the other side of the piezoelectric layer so as to be on the same side of the piezoelectric layer as the electrode on the other side.
  • the resonance area of the piezoelectric layer is mechanically isolated from the packaging structure in the lateral direction, that is, there is no mechanical physical connection, which reduces the lateral leakage of energy and improves the resonance. It improves the performance of the resonator and reduces the interference of external vibration, heat and other factors on the resonator.
  • the present invention proposes a quartz wafer manufacturing process based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which can be used to produce small-sized, precise frequency, and low-profile quartz resonators.
  • M/NEMS micro/nano electromechanical systems
  • a wafer-level frequency/thickness monitoring and control method is adopted, which reduces the requirements for the uniformity of quartz wafer thickness processing and reduces the processing difficulty.
  • the present invention's wafer manufacturing solution based on micro-nano electromechanical systems makes full use of the advantages of MEMS photolithography technology and wafer-level process manufacturing methods, and uses the method of wet etching wafer contours to get rid of the impact of cutting technology on wafer size. Limitation, can realize the processing of smaller size wafers of 1210, 1008 and below.
  • wafer processing solutions for wafer manufacturing can improve dimensional processing accuracy and improve wafer processing efficiency.
  • micro/nano electromechanical systems (M/NEMS) photolithography technology is used in combination with wet etching/dry etching to: make the size of the particles less than 1 mm ⁇ 1 mm; and/or The thickness of the resonant region of the shot particles is less than 40 ⁇ m or the fundamental frequency of the resonator formed based on the shot particles is above 40 MHz.
  • M/NEMS micro/nano electromechanical systems
  • micro/nano electromechanical system photolithography technology it is possible to obtain fine patterns for subsequent etching that facilitate the formation of particle sizes less than 1 mm ⁇ 1 mm, while based on wet etching/dry etching, it is possible to Obtain particles with a size less than 1mm ⁇ 1mm; based on wet etching/dry etching, it can replace the mechanical mask to obtain a quartz piezoelectric layer thickness less than 40 ⁇ m.
  • the present invention proposes a wafer-level wafer manufacturing and frequency control process, which eliminates the need for ultra-high-precision grinding technology for quartz wafers, and at the same time greatly reduces the difficulty of frequency modulation, making frequency modulation completely unconstrained by wafer area expansion.
  • this solution meets the requirements for miniaturized manufacturing of wafers from low frequency to high frequency (30-300MHz) and ultra-high frequency (300MHz-3GHz), and is of great significance to promoting the development of the quartz wafer field.
  • At least a part of the electrical connection through hole or the through hole 14 is a tapered hole, or more specifically, the cross section of the electrical connection through hole is from the upper and lower directions of the boss in the non-resonant region of the piezoelectric layer.
  • the reduced shape in the middle is beneficial to the uniformity of electrode distribution and thus obtains a stable resistance value.
  • the resonant region refers to the overlapping region of the top electrode, bottom electrode, piezoelectric layer, and cavity or gap in the thickness direction of the piezoelectric layer in the formed quartz resonator.
  • the resonance area of the wafer corresponds to the area in the wafer that needs to be formed as a resonance area of the resonator;
  • the resonance area of the piezoelectric layer corresponds to the area in the piezoelectric layer that needs to be formed as the resonance area of the resonator.
  • the non-resonant region is a portion outside the resonant region.
  • the non-resonant region of the piezoelectric layer refers to the region outside the resonant region of the piezoelectric layer in the horizontal or lateral direction.
  • each numerical range except that it is clearly stated that it does not include the endpoint value, can be the endpoint value or the median value of each numerical range, which are all within the protection scope of the present invention. .
  • the quartz resonator according to the present invention can be used to form a quartz crystal oscillator chip or an electronic device including a quartz resonator.
  • the electronic device here may be an electronic component such as an oscillator, a communication device such as a walkie-talkie or a mobile phone, or a large-scale product using a quartz resonator such as an automobile.
  • a quartz resonator including:
  • the resonant structure includes a quartz piezoelectric layer, a bottom electrode and a top electrode.
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode.
  • the first electrode is located on one side of the piezoelectric layer, so The second electrode is located on the other side of the piezoelectric layer;
  • the first packaging substrate and the second packaging substrate are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second electrode.
  • the first packaging substrate and the second packaging substrate are bonded to each other and define an accommodation space for accommodating the resonant structure
  • the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer so as to be on the same side of the piezoelectric layer as the second electrode.
  • the second packaging substrate is provided with an electrode lead-out portion connected to the first electrode.
  • the electrically connected substrate passes through conductive holes.
  • the piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer through the electrical connection through hole to communicate with the second electrode.
  • the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer through the electrical connection through hole to communicate with the second electrode.
  • the substrate is electrically connected to the electrical connection through hole through the conductive hole.
  • the substrate through conductive hole and the electrical connection through hole are staggered in the horizontal direction; or
  • the substrate through conductive hole and the electrical connection through hole are aligned in the thickness direction.
  • the electrode lead-out portion of the first electrode covers the end surface of the piezoelectric layer and extends to the other end of the piezoelectric layer. side thereby being on the same side of the piezoelectric layer as the second electrode;
  • a conductive portion is provided on one side of the end surface of the piezoelectric layer, and the conductive portion electrically connects the electrode lead-out portion of the first electrode and the substrate through conductive hole.
  • the conductive part is a spherical conductive part.
  • the piezoelectric layer has a single-sided reverse platform structure.
  • the piezoelectric layer has a double-sided reverse platform structure.
  • the piezoelectric layer has a flat structure.
  • At least a portion of the electrical connection through hole is a tapered hole.
  • the size of the piezoelectric layer is less than 1mm ⁇ 1mm; and/or
  • the thickness of the resonant region of the piezoelectric layer is less than 40 ⁇ m or the fundamental frequency of the resonator is above 40 MHz.
  • Both the first packaging substrate and the second packaging substrate are quartz substrates.
  • a cavity is provided on a side of the first packaging substrate and/or the second packaging substrate facing the piezoelectric layer, and the projection of the resonance area of the quartz resonator in the thickness direction falls into the cavity.
  • the side of the first packaging substrate and/or the second packaging substrate facing the resonator is a flat surface
  • the side of the piezoelectric layer of the resonator facing the flat surface has an inverted platform structure.
  • the conductive holes penetrating the substrate are straight holes, tapered holes, or holes with upper and lower sides narrowing toward the middle.
  • An electronic device including the quartz resonator according to any one of 1-14.
  • a method of manufacturing a quartz resonator including the steps:
  • a quartz wafer including a resonant region for forming a plurality of quartz resonators
  • a resonant structure is formed.
  • the resonant structure includes a quartz piezoelectric layer, a bottom electrode and a top electrode.
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode.
  • the first electrode is in the piezoelectric layer. on one side of the piezoelectric layer, the second electrode is on the other side of the piezoelectric layer, and the piezoelectric layer of each resonance structure includes the resonance region;
  • the packaging structure includes a first packaging substrate and a second packaging substrate, which are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second packaging substrate.
  • the electrodes face each other,
  • the first packaging substrate and the second packaging substrate are bonded to each other and define an accommodation space for accommodating the resonant structure
  • the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer so as to be on the same side of the piezoelectric layer as the second electrode.
  • the second packaging substrate is provided with an electrode lead-out portion connected to the first electrode.
  • the electrically connected substrate passes through conductive holes.
  • a quartz wafer including a resonant region for forming a plurality of quartz resonators
  • Etching At least using micro/nano electromechanical system photolithography technology to form a through-hole etching area and a contour etching area in the non-resonant area of the quartz wafer at a predetermined position on one side of the quartz wafer;
  • a first electrode layer including a first electrode, the first electrode layer covering the corresponding through hole etching area;
  • auxiliary substrate bonding the auxiliary substrate to the quartz wafer on one side of the quartz wafer;
  • Penetration After setting the auxiliary substrate, at least using micro/nano electromechanical system photolithography technology, etch through the through hole at the position corresponding to the through hole etching area and the contour etching area on the other side of the quartz wafer. hole etching area to expose the first electrode layer and etching through the contour etching area;
  • An electrical connection part and a second electrode layer are provided: An electrical connection part and a second electrode layer including a second electrode are provided on the other side of the quartz wafer, and the electrical connection part is electrically connected to the through-hole etching area at The first electrode on one side of the quartz wafer, the electrical connection portion is spaced apart from the second electrode layer provided on the other side of the quartz wafer;
  • the second packaging substrate provided with a substrate through conductive hole is bonded to the quartz wafer on the other side of the quartz wafer, and the substrate through conductive hole leads to the electrode of the first electrode. electrical connection;
  • a first packaging substrate is provided: the first packaging substrate is joined to the second packaging substrate on one side of the quartz wafer to complete the packaging, and defines an accommodation space for accommodating a resonant structure, the resonant structure including a resonator Quartz piezoelectric layer, bottom electrode and top electrode;
  • the etching steps include:
  • Setting a patterned first mask setting a first mask on one side and the other side of the quartz wafer, and using micro/nano electromechanical system photolithography technology to pattern the first mask on the side of the quartz wafer.
  • Mask patterning, the patterned first mask includes a plurality of first mask holes;
  • Forming a through-hole etching area forming a through-hole etching area on one side of the quartz wafer at a position corresponding to the first mask hole;
  • Set a patterned second mask set a second mask on the other side of the piezoelectric layer, and pattern the second mask to expose the other side of the piezoelectric layer corresponding to the through hole engraved Etched areas and portions of said profile etched areas;
  • the patterned first mask covers the resonance area of the quartz wafer
  • the patterned second mask covers the resonance area of the quartz wafer
  • the first packaging substrate is provided with a first cavity, and the first electrode layer faces the first cavity;
  • the second packaging substrate is provided with a second cavity, and the second electrode layer faces the second cavity.
  • First thinning Perform a thinning on the quartz wafer on the other side of the quartz wafer. There is a gap in the thickness direction between the other side of the quartz wafer after the first thinning and the through-hole etching area. The distance is within 1 ⁇ m;
  • Measurement or secondary thinning measure whether the thickness of the resonance area of the quartz wafer reaches a predetermined thickness, and perform secondary thinning on the other side of the quartz wafer to make the quartz wafer thin if the predetermined thickness is not reached. The thickness of the wafer in the resonance region reaches a predetermined thickness.
  • etching penetrates the via etching area, etching penetrates the profile etching area.
  • Measurement or frequency modulation measure the resonant frequency of the resonant area where the electrical connection part and the second electrode are set, and when the measured resonant frequency is less than the predetermined resonant frequency, raise the resonant frequency of the resonant area to the predetermined resonant frequency.
  • wet etching is used to form through-hole etching areas and profile etching areas;
  • dry etching is used to etch through the through hole etching area and the profile etching area.
  • Forming quartz shot forming quartz shot from a quartz wafer based on at least micro/nano electromechanical systems lithography techniques;
  • Form an electrode layer form a first electrode and a second electrode on both sides of the quartz particles to form the resonance structure, the first electrode is on one side of the quartz particles, and the second electrode is on the other side of the quartz particles, so The electrode lead-out portion of the first electrode covers the end surface of the quartz particles and extends to the other side of the quartz particles so as to be on the same side of the quartz particles as the second electrode.
  • the quartz granules have an inverted platform structure.
  • a second packaging substrate provided with a second cavity and a substrate through conductive hole
  • the resonant structure is arranged on the second packaging substrate, the second electrode is opposite to the second cavity, and the substrate through-conductive hole is provided on the end face side of the quartz shot;
  • a conductive part is provided in the second cavity, and the conductive part electrically connects the electrode lead-out part of the first electrode and the substrate through conductive hole;
  • a first packaging substrate is provided, the first packaging substrate is provided with a first cavity, the first packaging substrate is bonded to the second packaging substrate, and the first electrode is opposite to the first cavity.

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Abstract

本发明涉及一种石英谐振器及其制造方法，所述石英谐振器包括：谐振结构，包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，其中：所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。本发明还涉及一种电子器件。

Description

压电层设置导电通孔的石英谐振器及其制造方法、电子器件 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种压电层设置导电通孔的石英谐振器及其制造方法，以及一种电子器件。
背景技术
高基频、小型化和低矮化是石英晶振片(下文中简称为晶片)发展的趋势。传统晶片制造方案多采用研磨切片的方式获得一定频率的散粒薄片，然后进行后续的镀电极与调频。然而，切片所采用的线切割技术对1mm×1mm及以下尺寸难以实现，基本无法覆盖1.2mm×1.0mm及以下尺寸的晶片制造，更无法满足1.0mm×0.8mm及以下尺寸规格晶片制造。晶片的基频主要受晶片谐振区域的厚度决定，晶片的基频由以下公式支配：
f0(MHz)＝1670(MHz·μm)/d(μm)       (1)
晶圆级制造可以实现单颗谐振器制造成本的大幅降低，以及谐振器之间的品控一致性；通常来说，晶圆尺寸越大，单颗谐振器的制造成本越低。然而，对于晶圆级制造方案，几百至数千颗晶片排列在单片晶圆上，对各个位置点石英厚度的精确控制挑战巨大，这也就直接导致了整片晶圆上晶片频率的准确性与一致性难以得到保证。因此，晶圆级晶片调频存在极大的挑战。目前已有技术采取的办法主要集中在采用具有超高精度膜厚监控系统的研磨技术，制备厚度均一度在几纳米之内的石英薄膜。这种频率控制与调节技术对材料和制造工 艺提出了极高的要求，而且晶圆面积越大，制造难度越高，阻碍了低成本、高效率的制造方案的产生。
现有的石英谐振器的顶电极的电极引出部和底电极的电极引出部中的一个经由压电层的边缘延伸到与另一个电极引出部同侧的位置，这种跨压电层布置电极引出部的方式，容易出现电极连接电阻不稳定(偏大甚至电连接断开)的问题。
此外，还希望降低石英谐振器的尺寸，尤其是降低整个谐振器的厚度，进一步实现石英谐振器的低矮化。
发明内容
为缓解或解决现有技术中的上述问题的至少一个方面，提出本发明。
根据本发明的实施例的一个方面，提出了一种石英谐振器，包括：
谐振结构，包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
根据本发明的实施例的另一方面，提出了一种石英谐振器的制造方法，包括步骤：
提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
形成谐振结构，所述谐振结构包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧，每个谐振结构的压电层包括 所述谐振区域；
形成封装结构，所述封装结构包括第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
本发明的实施例还涉及一种电子器件，包括上述的石英谐振器。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1-16为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图；
图17-25为根据本发明的另一个示例性实施例的石英谐振器的制作过程的截面示意图；
图26为石英晶圆的谐振区域的基频调节的流程示意图；
图27为石英谐振器的谐振频率调节的流程示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
下面参照图1-27示例性说明根据本发明的石英谐振器的制作过程。本发明 中，附图标记示意性说明如下：
10：石英晶圆或晶圆。
10A:石英散粒或者散粒。
12：谐振区域。
14：通孔刻蚀区或通孔。
16：压电层边框。
18：轮廓刻蚀区。
18’；裂片通槽。
20A：第一掩膜层或掩膜。
20B：第二掩膜层或掩膜。
22：掩膜槽或掩膜开孔。
30：顶电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
32：顶电极的电连接部，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。在可选的实施例中，顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。
40：底电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
50：第一封装石英晶圆或第一封装基板。
52：第一空腔。
60：第二封装石英晶圆或第二封装基板。
62：第二空腔。
64：导电通孔。
66：导电部。
72：金属键合层，可以是金金、金锡、铜锡键合等方式。
80：辅助基板。
90：临时接合层。
在本发明的具体实施例中，各部分以其中可行的一种材料为例进行说明，但不限于此。
图1-图16为根据本发明的一个示例性实施例的石英谐振器的制作过程的截 面示意图。下面参照图1-图16示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图1所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20A，处于正面的掩膜20A被图案化，以形成掩膜开孔22，具体的，用于制备通孔的区域，即通孔刻蚀区14，以及用于形成轮廓的轮廓刻蚀区18，被露出。在石英晶圆10的另一侧(例如次面)也设置掩膜20A，其覆盖整个另一侧。
这里，对于后续使用湿法刻蚀(例如图1-图16所示实施例的步骤2)，掩膜可以是金属掩膜，例如铬金(上面一层金、下面一层铬)，或者其他惰性金属；对于后续使用干法刻蚀(例如图1-图18所示实施例的步骤2)，掩膜可以是SU-8胶，或者其他适合干法刻蚀的光刻胶。掩膜20A的材料也可以适用于其他实施例，后面不再赘述。
需要指出的是，在图1-图16中，仅仅示出了晶圆上的单个石英谐振器对应的区域，如能够理解的，在晶圆10上存在多个图1-图16所示的区域。在其他的实施例中，也应做相似的理解，后面不再赘述。
步骤2：湿法刻蚀。如图2所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀，刻蚀深度为d1(d1等于石英谐振器设定频率对应的石英膜厚d0)。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：去除掩膜20A。如图3所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤4：制作顶电极。如图4所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14，以及可选的，覆盖了通孔刻蚀区与边框之间的部分区域。
步骤5：接合辅助基板。可以采用例如粘合或者键合的方式将图4中的结构的设置了顶电极的一侧与辅助基板80接合在一起。辅助基板80可以是石英基 板，也可以其他材料的基板，如硅、玻璃、蓝宝石等。如后面看到，步骤5中的接合为临时接合，临时接合形成了临时接合层90。
步骤6：石英晶圆减薄。如图6所示，利用研磨与抛光工艺对石英晶圆10进行减薄，减薄至剩余厚度比设计值(即上述膜厚d0)富余值在例如1μm之内。
步骤7：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图7所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依据。
步骤8：调节石英薄膜厚度。如图8所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图7和图8操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图26。
步骤9：在图8所示结构的上表面设置掩膜20B，如图9所示，掩膜20B被图案化以在对应于通孔刻蚀区14和轮廓刻蚀区18的位置设置有掩膜开孔。
步骤10：例如，利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14和轮廓刻蚀区18处的部分，以贯穿通孔刻蚀区14和轮廓刻蚀区18，如图10所示。
步骤11：去除掩膜20B。步骤10之后，可以利用湿法刻蚀的方式去除掩膜20B，以得到如图11所示的结构。
步骤12：制作底电极40以及设置顶电极的电连接部32，电连接部32与底电极40设置在石英晶圆10的同一侧且彼此间隔开。
如图12所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40和电连接部32。底电极40至少由一层金属构成，其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。
步骤13：接合第二封装基板。如图13所示，将步骤12中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准，使得底电极40恰好位于第二空腔62之内。第二封装基板60设置有导电通孔64，其与顶电极30的电连接部32可以通过金属键合的方式电连接。
在本发明的实施例中，第二封装基板60是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
步骤14：移除辅助基板80。可以通过移除临时接合层90而移除辅助基板 80，相应的，压电层边框16也被移除，最终形成如图14所示的结构。临时接合层90可以是UV胶粘，利用UV光照解胶去除；亦或者使用键合力较弱的临时键合技术，例如氧气等离子表面键合，在分裂的谐振器与基板完成金属键合之后可以直接移除临时辅助基板。
如图14所示，所形成的谐振器的谐振区域为悬臂结构，更具体的，谐振器的主体部分的非电极连接端为自由端。该结构可以产生如下技术效果：减少了能量横向泄露，提升谐振器性能，同时可以减小/隔绝外界震动、热量等因素对谐振器性能的影响。
步骤15：测频与调频。如图15所示，测量所得的石英谐振器的谐振频率f，在测得的谐振频率小于预定谐振频率f0的情况下，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图27。
步骤16：接合第一封装基板。如图16所示，将步骤15中的第二封装基板60与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准，使得顶电极30恰好位于第一空腔52之内。第二封装基板60与第一封装基板50可以利用金属扩散键合方式键合(如图16所示形成了金属键合层72)在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。
步骤16之后，可以执行分割操作，以将最终封装形成的石英谐振器形成为单独的器件。
上述的步骤9-步骤12也可以予以调整，均在本发明的保护范围之内。具体的：可以先在图8所示结构上制备底电极，可以利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作底电极40；接着，刻蚀贯穿通孔刻蚀区14和轮廓刻蚀区18；然后，制备顶电极的电连接部32。
基于图1-图16，本发明提供了一种晶圆级晶片制造方案。上述工艺采用了湿法与干法结合方式对石英进行减薄，并且采用了晶圆级频率/厚度监测与调控方法，降低了对石英晶圆片厚度加工均一度的要求，降低了加工难度。本方案对不同频段的石英晶片的制造普遍适用，并且不受石英晶圆面积的限制，具有明显的优势。
图17-图25为根据本发明的另一个示例性实施例的石英谐振器的制作过程 的截面示意图。下面参照图17-图25示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜。如图17所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的两侧利用微/纳机电系统光刻的方式制作掩膜20A，两侧的掩膜20A被图案化，对应于谐振区域12的部分露出，其余部分均覆盖掩膜层20A。
步骤2：湿法裂片。在一个实施例中，以湿法刻蚀的方式形成多个散粒，在图18中示出了裂片通槽18’，在图18中，裂片通槽18’之间为带掩膜20A的初步散粒，初步散粒如图19所示。
步骤3：去除掩膜20A。如图20所示，利用刻蚀液逐层去除掩膜20A以形成散粒，可选的，对移除了掩膜20后的晶圆进行清洗。
步骤4：测试与调频。对散粒(如图20所示)逐个进行频率测试，然后根据与设计频率的差值对散粒进行湿法刻蚀，改变散粒的谐振区域的厚度以形成如图21所示的结构，以调节散粒频率。如此多次重复测试-刻蚀的步骤来调节散粒频率。
步骤5：设置电极以形成谐振器的散粒。如图22所示，在散粒上镀顶电极30和底电极40以形成石英谐振器。如图22所示，散粒10A设置在底电极40与顶电极30之间，其中：底电极处于散粒的下侧，顶电极处于散粒10A的上侧，底电极40的电极引出部42覆盖散粒10A的端面且延伸到散粒10A的上侧从而与顶电极30同处于散粒10A的上侧。在可选的实施例中，以溅射或蒸镀的方式形成底电极40和顶电极30以及电极引出部，更具体的，可以先在图21所示的散粒上以机械掩膜法设置掩膜(未示出)，该掩膜具有图案以在散粒上露出对应于底电极40和顶电极30以及电极引出部的区域，然后以溅射或蒸镀的方式形成底电极40和顶电极30以及电极引出部。
以上的步骤1-步骤5仅仅示出了形成谐振器的散粒结构的一个具体的实施例。谐振器的散粒结构不限于图22中所示的平坦结构，还可以是包括单面或双面反高台结构。
步骤6：将步骤5中形成的散粒布置到设置了第二空腔62和基板贯穿导电孔64的第二封装基板60，如图23所示。
步骤7：如图24所示，在第二空腔62内设置导电部66，所述导电部将所 述第一电极的电极引出部32与所述基板贯穿导电孔64电连接；导电部66可以是植球的形式。
步骤8：如图25所示，将设置有第一空腔52的第一封装基板50与第二封装基板60接合，以形成封装。
在本发明中，封装基板可以是石英基板，也可以其他材料的基板，如硅、玻璃、蓝宝石等。在后面的实施例中不再赘述。在本发明中，封装基板是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
在本发明中，在为全石英封装的情况下，封装基板为透明材料。因此，调频也可以发生在封装完成之后，利用激光透过透明的石英封装盖直接调节频率，用来调整因为封装应力带来的频率变动。在后面的实施例中不再赘述。
在本发明的实施例中，采用第一封装基板与第二封装基板直接接合连接的方式，相较于第一封装基板、压电层、第二封装基板形成的三明治结构，由于在两个封装基板之间不存在压电层的厚度，有利于进一步实现谐振器的低矮化。
此外，在本发明的实施例中，最终形成的谐振器的压电层与压电层上下两侧的封装基板的连接减少(相比于封装基板与压电层接合的三明治结构)，从而可以减小因晶片机械性形变导致的应力向谐振器的传导，以提高谐振器的抗干扰性能。
在本发明的实施例中，石英谐振器的顶电极的电极引出部和底电极的电极引出部处于压电层的同一侧，这有利于：减小/避免了电极跨越压电层时可能存在的电极阻值不稳定的技术问题。
在本发明中，如图16所示，所形成的谐振器的所述压电层在非谐振区域设置有电连接通孔或通孔14，压电层一侧的电极的引出部经由所述电连接通孔延伸到压电层的另一侧从而与另一侧的电极处于压电层的同一侧。这相对于现有技术中两个电极的引出部分别设置在压电层的两侧具有如下技术效果：减小封装复杂度；此外，这相对于现有技术中一个电极的引出部经由压电层的边缘而到达压电层的另一侧从而与另一电极的引出部同面设置具有如下技术效果：减小/避免了电极跨越压电层时可能存在的电极阻值不稳定的问题。
在本发明中，如图16所示，压电层的谐振区域与封装结构在横向上机械结构隔离开，即不存在机械上的物理连接，这减小了能量的横向泄露，提升了谐 振器性能，同时降低外界震动、热量等因素对谐振器的干扰。
本发明提出一种基于微/纳机电系统(M/NEMS)光刻技术的石英晶片制造工艺，可以用于制作小尺寸、频率精准、低矮化的石英谐振器。
本发明中，采用了晶圆级频率/厚度监测与调控方法，降低了对石英晶圆片厚度加工均一度的要求，降低了加工难度。
本发明基于微纳机电系统(M/NEMS)的晶片制造方案充分利用了MEMS光刻技术和晶圆级工艺制造方式的优势，利用湿法刻蚀晶片轮廓的方法，摆脱了切割技术对晶片尺寸的限制，可以实现1210、1008及以下更小尺寸晶片的加工。此外，晶圆制造的晶片加工方案能够提高尺寸加工精度，提高晶片加工效率。
在本发明的实施例中，采用微/纳机电系统(M/NEMS)光刻技术与湿法刻蚀/干法刻蚀相结合，可以：使得散粒的尺寸小于1mm×1mm；和/或使得散粒的谐振区域的厚度小于40μm或者基于该散粒形成的谐振器的基频在40MHz以上。具体的，基于微/纳机电系统光刻技术，可以获得用于后续刻蚀的、便于形成小于1mm×1mm的散粒尺寸的精细图案，而基于湿法刻蚀/干法刻蚀，则可以获得小于1mm×1mm尺寸的散粒；基于湿法刻蚀/干法刻蚀，可以替代机械掩膜获得小于40μm的石英压电层厚度。
本发明提出了一种晶圆级晶片制造与频率控制制程，摆脱了石英晶片对超高精度研磨技术的需求，同时大大降低了调频的难度，使得调频完全不受晶圆面积扩大的制约。同时，该方案满足了从低频到高频(30-300MHz)、超高频率(300MHz-3GHz)晶片的小型化制造，对推动石英晶片领域的发展具有重要意义。
在本发明中，电连接通孔或者通孔14的至少一部分为锥形孔，或者在更具体的，电连接通孔的截面为自处于压电层非谐振区域的凸台的上下两侧向中间缩小的形状，这有利于电极分布均一性进而获得稳定的电阻值。
在本发明中，谐振区域是指在形成的石英谐振器中，顶电极、底电极、压电层以及空腔或空隙在压电层的厚度方向上的重合区域。在本发明中，晶圆的谐振区域对应于在晶圆中需要形成为谐振器的谐振区域的区域；压电层的谐振区域对应于在压电层中需要形成为谐振器的谐振区域的区域。在本发明中，非谐振区域是谐振区域之外的部分，对于压电层的非谐振区域，指的是在压电层的谐振区域在水平方向或横向方向外侧的区域。
需要指出的是，在本发明中，各个数值范围，除了明确指出不包含端点值之外，除了可以为端点值，还可以为各个数值范围的中值，这些均在本发明的保护范围之内。
如本领域技术人员能够理解的，根据本发明的石英谐振器可以用于形成石英晶振芯片或包括石英谐振器的电子器件。这里的电子器件，可以是例如振荡器等电子元件，也可以例如对讲机、手机等的通信设备，还可以是汽车等应用了石英谐振器的大型产品。
基于以上，本发明提出了如下技术方案：
1、一种石英谐振器，包括：
谐振结构，包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
2、根据1所述的谐振器，其中：
所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧；
所述基板贯穿导电孔与所述电连接通孔电连接。
3、根据2所述的谐振器，其中：
所述基板贯穿导电孔与所述电连接通孔在水平方向上错开；或者
所述基板贯穿导电孔与所述电连接通孔在厚度方向上对齐。
4、根据1所述的谐振器，其中：
第一电极的电极引出部覆盖所述压电层的端面且延伸到所述压电层的另一 侧从而与所述第二电极处于所述压电层的同一侧；
在压电层的所述端面一侧设置有导电部，所述导电部将所述第一电极的电极引出部与所述基板贯穿导电孔电连接。
5、根据4所述的谐振器，其中：
所述导电部为球状导电部。
6、根据1所述的谐振器，其中：
所述压电层为单面反高台结构。
7、根据1所述的谐振器，其中：
所述压电层为双面反高台结构。
8、根据1所述的谐振器，其中：
所述压电层为平坦结构。
9、根据1所述的谐振器，其中：
所述电连接通孔的至少一部分为锥形孔。
10、根据1所述的谐振器，其中：
所述压电层的尺寸小于1mm×1mm；和/或
所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
11、根据1所述的谐振器，其中：
第一封装基板和第二封装基板均为石英基板。
12、根据1所述的谐振器，其中：
第一封装基板和/或第二封装基板面对所述压电层的一侧设置有空腔，所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
13、根据1所述的谐振器，其中：
第一封装基板和/或第二封装基板面对谐振器的一侧为平坦面；
所述谐振器的压电层面对所述平坦面的一侧为反高台结构。
14、根据1所述的谐振器，其中：
所述基板贯穿导电孔为直孔、锥形孔或者上下两侧向中间缩小的孔。
15、一种电子器件，包括根据1-14中任一项所述的石英谐振器。
16、一种石英谐振器的制造方法，包括步骤：
提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
形成谐振结构，所述谐振结构包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧，每个谐振结构的压电层包括所述谐振区域；
形成封装结构，所述封装结构包括第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
17、根据16所述的方法，包括步骤：
提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
刻蚀：至少利用微/纳机电系统光刻技术，在石英晶圆的一侧的预定位置，在石英晶圆的非谐振区域形成通孔刻蚀区以及轮廓刻蚀区；
设置第一电极层：对于每个石英谐振器，顶电极和底电极中的一个电极为第一电极，顶电极和底电极中的另一个电极为第二电极，在石英晶圆的一侧设置包括了第一电极的第一电极层，第一电极层覆盖对应的通孔刻蚀区；
设置辅助基板：将辅助基板在石英晶圆的所述一侧与石英晶圆接合；
贯穿：设置辅助基板后，至少利用微/纳机电系统光刻技术，在石英晶圆的另一侧的与所述通孔刻蚀区与轮廓刻蚀区对应的位置，刻蚀贯穿所述通孔刻蚀区以露出所述第一电极层以及刻蚀贯穿轮廓刻蚀区；
设置电连接部和第二电极层：在石英晶圆的另一侧设置电连接部和包括第二电极的第二电极层，所述电连接部经由贯穿的通孔刻蚀区电连接到处于石英晶圆的一侧的所述第一电极，所述电连接部与设置在石英晶圆的另一侧的第二电极层间隔开设置；
设置第二封装基板：将设置有基板贯穿导电孔的第二封装基板与在石英晶圆的另一侧与石英晶圆接合，所述基板贯穿导电孔与所述第一电极的电极引出 部电连接；
移除所述辅助基板，且与每个谐振器对应，移除所述轮廓刻蚀区外侧的压电层部分；
设置第一封装基板：所述第一封装基板在所述石英晶圆的一侧有所述第二封装基板接合以完成封装，且限定容纳谐振结构的容纳空间，所述谐振结构包括谐振器的石英压电层、底电极和顶电极；
分割：在上述步骤之后，执行切割或者裂片，以形成单独的石英谐振器。
18、根据17所述的方法，其中：
所述刻蚀步骤包括：
设置图案化的第一掩膜：在石英晶圆的一侧和另一侧均设置第一掩膜，以及利用微/纳机电系统光刻技术对在石英晶圆的所述一侧的第一掩膜图案化，图案化的第一掩膜包括多个第一掩膜孔；
形成通孔刻蚀区：在石英晶圆的一侧在所述第一掩膜孔对应的位置形成通孔刻蚀区；
移除石英晶圆两侧的第一掩膜。
19、根据17所述的方法，其中，所述贯穿步骤包括：
设置图案化的第二掩膜：在压电层的另一侧设置第二掩膜，对所述第二掩膜图案化以露出所述压电层的另一侧对应于所述通孔刻蚀区和所述轮廓刻蚀区的部分；
贯穿通孔刻蚀区和轮廓刻蚀区：对于所述压电层的另一侧对应于所述通孔刻蚀区和轮廓刻蚀区的部分刻蚀以贯穿通孔刻蚀区和轮廓刻蚀区；
移除第二掩膜。
20、根据19所述的方法，其中：
设置图案化的第一掩膜的步骤中，图案化的第一掩膜覆盖石英晶圆的谐振区域；
设置图案化的第二掩膜的步骤中，图案化的第二掩膜覆盖石英晶圆的谐振区域；
第一封装基板设置有第一空腔，所述第一电极层与所述第一空腔面对；
第二封装基板设置有第二空腔，所述第二电极层与所述第二空腔面对。
21、根据17所述的方法，其中：
在设置辅助基板之后和贯穿之前，还包括步骤：
第一次减薄：在石英晶圆的另一侧对石英晶圆执行一次减薄，一次减薄后的石英晶圆的另一侧与所述通孔刻蚀区之间在厚度方向上存在的距离在1μm以内；
测量或者二次减薄：测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度。
22、根据17所述的方法，其中：
在刻蚀贯穿所述通孔刻蚀区之后，刻蚀贯穿所述轮廓刻蚀区；或者
在刻蚀贯穿所述通孔刻蚀区的同时，刻蚀贯穿所述轮廓刻蚀区。
23、根据17所述的方法，还包括步骤：
测量或者调频：测量设置了电连接部和第二电极的谐振区域的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
24、根据17所述的方法，其中：
所述刻蚀步骤中采用湿法刻蚀以形成通孔刻蚀区和轮廓刻蚀区；和/或
所述贯穿步骤中采用干法刻蚀以刻蚀贯穿所述通孔刻蚀区和轮廓刻蚀区。
25、根据16所述的方法，其中，形成所述谐振结构包括步骤：
形成石英散粒：从石英晶圆至少基于微/纳机电系统光刻技术形成石英散粒；和
形成电极层：在石英散粒的两侧形成第一电极和第二电极以形成所述谐振结构，第一电极处于石英散粒的一侧，第二电极处于石英散粒的另一侧，所述第一电极的电极引出部覆盖所述石英散粒的端面且延伸到所述石英散粒的另一侧从而与所述第二电极处于所述石英散粒的同一侧。
26、根据25所述的方法，其中：
所述石英散粒为反高台结构。
27、根据25所述的方法，其中，形成封装结构的步骤包括：
提供设置了第二空腔和基板贯穿导电孔的第二封装基板；
将谐振结构布置在所述第二封装基板上，所述第二电极与所述第二空腔相对，所述基板贯穿导电孔设置在所述石英散粒的端面侧；
在所述第二空腔内设置导电部，所述导电部将所述第一电极的电极引出部与所述基板贯穿导电孔电连接；
提供第一封装基板，所述第一封装基板设置有第一空腔，第一封装基板与第二封装基板接合，第一电极与所述第一空腔相对。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (27)

  1. 一种石英谐振器，包括：
    谐振结构，包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
    第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
    其中：
    所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
    第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
  2. 根据权利要求1所述的谐振器，其中：
    所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧；
    所述基板贯穿导电孔与所述电连接通孔电连接。
  3. 根据权利要求2所述的谐振器，其中：
    所述基板贯穿导电孔与所述电连接通孔在水平方向上错开；或者
    所述基板贯穿导电孔与所述电连接通孔在厚度方向上对齐。
  4. 根据权利要求1所述的谐振器，其中：
    第一电极的电极引出部覆盖所述压电层的端面且延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧；
    在压电层的所述端面一侧设置有导电部，所述导电部将所述第一电极的电极引出部与所述基板贯穿导电孔电连接。
  5. 根据权利要求4所述的谐振器，其中：
    所述导电部为球状导电部。
  6. 根据权利要求1所述的谐振器，其中：
    所述压电层为单面反高台结构。
  7. 根据权利要求1所述的谐振器，其中：
    所述压电层为双面反高台结构。
  8. 根据权利要求1所述的谐振器，其中：
    所述压电层为平坦结构。
  9. 根据权利要求1所述的谐振器，其中：
    所述电连接通孔的至少一部分为锥形孔。
  10. 根据权利要求1所述的谐振器，其中：
    所述压电层的尺寸小于1mm×1mm；和/或
    所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
  11. 根据权利要求1所述的谐振器，其中：
    第一封装基板和第二封装基板均为石英基板。
  12. 根据权利要求1所述的谐振器，其中：
    第一封装基板和/或第二封装基板面对所述压电层的一侧设置有空腔，所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
  13. 根据权利要求1所述的谐振器，其中：
    第一封装基板和/或第二封装基板面对谐振器的一侧为平坦面；
    所述谐振器的压电层面对所述平坦面的一侧为反高台结构。
  14. 根据权利要求1所述的谐振器，其中：
    所述基板贯穿导电孔为直孔、锥形孔或者上下两侧向中间缩小的孔。
  15. 一种电子器件，包括根据权利要求1-14中任一项所述的石英谐振器。
  16. 一种石英谐振器的制造方法，包括步骤：
    提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
    形成谐振结构，所述谐振结构包括石英压电层、底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧，每个谐振结构 的压电层包括所述谐振区域；
    形成封装结构，所述封装结构包括第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
    其中：
    所述第一封装基板与所述第二封装基板彼此接合且限定容纳所述谐振结构的容纳空间；且
    第一电极的电极引出部延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧，所述第二封装基板设置有与第一电极的电极引出部电连接的基板贯穿导电孔。
  17. 根据权利要求16所述的方法，包括步骤：
    提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
    刻蚀：至少利用微/纳机电系统光刻技术，在石英晶圆的一侧的预定位置，在石英晶圆的非谐振区域形成通孔刻蚀区以及轮廓刻蚀区；
    设置第一电极层：对于每个石英谐振器，顶电极和底电极中的一个电极为第一电极，顶电极和底电极中的另一个电极为第二电极，在石英晶圆的一侧设置包括了第一电极的第一电极层，第一电极层覆盖对应的通孔刻蚀区；
    设置辅助基板：将辅助基板在石英晶圆的所述一侧与石英晶圆接合；
    贯穿：设置辅助基板后，至少利用微/纳机电系统光刻技术，在石英晶圆的另一侧的与所述通孔刻蚀区与轮廓刻蚀区对应的位置，刻蚀贯穿所述通孔刻蚀区以露出所述第一电极层以及刻蚀贯穿轮廓刻蚀区；
    设置电连接部和第二电极层：在石英晶圆的另一侧设置电连接部和包括第二电极的第二电极层，所述电连接部经由贯穿的通孔刻蚀区电连接到处于石英晶圆的一侧的所述第一电极，所述电连接部与设置在石英晶圆的另一侧的第二电极层间隔开设置；
    设置第二封装基板：将设置有基板贯穿导电孔的第二封装基板与在石英晶圆的另一侧与石英晶圆接合，所述基板贯穿导电孔与所述第一电极的电极引出部电连接；
    移除所述辅助基板，且与每个谐振器对应，移除所述轮廓刻蚀区外侧的压电层部分；
    设置第一封装基板：所述第一封装基板在所述石英晶圆的一侧有所述第二封装基板接合以完成封装，且限定容纳谐振结构的容纳空间，所述谐振结构包括谐振器的石英压电层、底电极和顶电极；
    分割：在上述步骤之后，执行切割或者裂片，以形成单独的石英谐振器。
  18. 根据权利要求17所述的方法，其中：
    所述刻蚀步骤包括：
    设置图案化的第一掩膜：在石英晶圆的一侧和另一侧均设置第一掩膜，以及利用微/纳机电系统光刻技术对在石英晶圆的所述一侧的第一掩膜图案化，图案化的第一掩膜包括多个第一掩膜孔；
    形成通孔刻蚀区：在石英晶圆的一侧在所述第一掩膜孔对应的位置形成通孔刻蚀区；
    移除石英晶圆两侧的第一掩膜。
  19. 根据权利要求17所述的方法，其中，所述贯穿步骤包括：
    设置图案化的第二掩膜：在压电层的另一侧设置第二掩膜，对所述第二掩膜图案化以露出所述压电层的另一侧对应于所述通孔刻蚀区和所述轮廓刻蚀区的部分；
    贯穿通孔刻蚀区和轮廓刻蚀区：对于所述压电层的另一侧对应于所述通孔刻蚀区和轮廓刻蚀区的部分刻蚀以贯穿通孔刻蚀区和轮廓刻蚀区；
    移除第二掩膜。
  20. 根据权利要求19所述的方法，其中：
    设置图案化的第一掩膜的步骤中，图案化的第一掩膜覆盖石英晶圆的谐振区域；
    设置图案化的第二掩膜的步骤中，图案化的第二掩膜覆盖石英晶圆的谐振区域；
    第一封装基板设置有第一空腔，所述第一电极层与所述第一空腔面对；
    第二封装基板设置有第二空腔，所述第二电极层与所述第二空腔面对。
  21. 根据权利要求17所述的方法，其中：
    在设置辅助基板之后和贯穿之前，还包括步骤：
    第一次减薄：在石英晶圆的另一侧对石英晶圆执行一次减薄，一次减薄后的石英晶圆的另一侧与所述通孔刻蚀区之间在厚度方向上存在的距离在1μm以内；
    测量或者二次减薄：利用光学方法在石英晶圆的另一侧测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度。
  22. 根据权利要求17所述的方法，其中：
    在刻蚀贯穿所述通孔刻蚀区之后，刻蚀贯穿所述轮廓刻蚀区；或者
    在刻蚀贯穿所述通孔刻蚀区的同时，刻蚀贯穿所述轮廓刻蚀区。
  23. 根据权利要求17所述的方法，还包括步骤：
    测量或者调频：测量设置了电连接部和第二电极的谐振区域的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
  24. 根据权利要求17所述的方法，其中：
    所述刻蚀步骤中采用湿法刻蚀以形成通孔刻蚀区和轮廓刻蚀区；和/或
    所述贯穿步骤中采用干法刻蚀以刻蚀贯穿所述通孔刻蚀区和轮廓刻蚀区。
  25. 根据权利要求16所述的方法，其中，形成所述谐振结构包括步骤：
    形成石英散粒：从石英晶圆至少基于微/纳机电系统光刻技术形成石英散粒；和
    形成电极层：在石英散粒的两侧形成第一电极和第二电极以形成所述谐振结构，第一电极处于石英散粒的一侧，第二电极处于石英散粒的另一侧，所述第一电极的电极引出部覆盖所述石英散粒的端面且延伸到所述石英散粒的另一侧从而与所述第二电极处于所述散粒的同一侧。
  26. 根据权利要求25所述的方法，其中：
    所述石英散粒为反高台结构。
  27. 根据权利要求25所述的方法，其中，形成封装结构的步骤包括：
    提供设置了第二空腔和基板贯穿导电孔的第二封装基板；
    将谐振结构布置在所述第二封装基板上，所述第二电极与所述第二空腔相对，所述基板贯穿导电孔设置在所述散粒的端面侧；
    在所述第二空腔内设置导电部，所述导电部将所述第一电极的电极引出部与所述基板贯穿导电孔电连接；
    提供第一封装基板，所述第一封装基板设置有第一空腔，第一封装基板与第二封装基板接合，第一电极与所述第一空腔相对。
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CN113395053A (zh) * 2021-03-02 2021-09-14 天津大学 石英薄膜谐振器及其制造方法
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US20180069521A1 (en) * 2016-09-08 2018-03-08 Murata Manufacturing Co., Ltd. Quartz crystal resonator and method for manufacturing the same, and quartz crystal resonator unit and method for manufacturing the same
CN112039467A (zh) * 2020-06-16 2020-12-04 中芯集成电路（宁波）有限公司上海分公司 一种薄膜体声波谐振器及其制造方法
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