WO2024027734A1 - 电极引出部处于同侧的石英谐振器及其制造方法、电子器件 - Google Patents

电极引出部处于同侧的石英谐振器及其制造方法、电子器件 Download PDF

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Publication number
WO2024027734A1
WO2024027734A1 PCT/CN2023/110648 CN2023110648W WO2024027734A1 WO 2024027734 A1 WO2024027734 A1 WO 2024027734A1 CN 2023110648 W CN2023110648 W CN 2023110648W WO 2024027734 A1 WO2024027734 A1 WO 2024027734A1
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Prior art keywords
electrode
mask
quartz wafer
etching
quartz
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PCT/CN2023/110648
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English (en)
French (fr)
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庞慰
张孟伦
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天津大学
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Publication of WO2024027734A1 publication Critical patent/WO2024027734A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/19—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a quartz resonator with electrode lead-out portions on the same side, a manufacturing method thereof, and an electronic device.
  • the fundamental frequency of the chip is mainly determined by the thickness of the resonance area of the chip.
  • Wafer-level manufacturing can significantly reduce the manufacturing cost of a single resonator and achieve consistent quality control between resonators; generally speaking, the larger the wafer size, the lower the manufacturing cost of a single resonator.
  • precise control of the quartz thickness at each location is a huge challenge, which directly leads to changes in the frequency of the wafers on the entire wafer. Accuracy and consistency cannot be guaranteed. Therefore, there are great challenges in wafer-level chip frequency modulation.
  • the current methods adopted by existing technologies mainly focus on using grinding technology with ultra-high-precision film thickness monitoring systems to prepare quartz films with a thickness uniformity within a few nanometers. This frequency control and regulation technology has significant impact on materials and manufacturing processes.
  • the technology puts forward extremely high requirements, and the larger the wafer area, the higher the difficulty of manufacturing, which hinders the creation of low-cost, high-efficiency manufacturing solutions.
  • one of the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode extends through the edge of the piezoelectric layer to a position on the same side as the other electrode lead-out portion, and the electrodes are arranged across the piezoelectric layer.
  • the lead-out method is prone to the problem of unstable electrode connection resistance (too high or even disconnection of the electrical connection).
  • the boundary conditions of the resonator can be optimized and the lateral leakage of acoustic waves can be reduced, thereby further improving the performance of the resonator.
  • a quartz resonator including:
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode, the first electrode is on one side of the piezoelectric layer, and the second electrode is on the other side of the piezoelectric layer;
  • the piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer through the electrical connection through hole to communicate with the second electrode. on the same side of the piezoelectric layer.
  • a manufacturing method of a quartz resonator including the steps:
  • a quartz wafer including a resonant region for forming a plurality of quartz resonators
  • Etching At least using micro/nano electromechanical system photolithography technology to form multiple through-hole etching areas in the non-resonant area of the quartz wafer at predetermined positions on one side of the quartz wafer based on wet etching;
  • a first electrode layer including a first electrode, the first electrode layer covering the corresponding through hole etching area;
  • Penetration At least using micro/nano electromechanical system photolithography technology, dry etching is used to penetrate the through-hole etching area at the position corresponding to the through-hole etching area on the other side of the quartz wafer to expose all the through-hole etching areas.
  • the first electrode layer At least using micro/nano electromechanical system photolithography technology, dry etching is used to penetrate the through-hole etching area at the position corresponding to the through-hole etching area on the other side of the quartz wafer to expose all the through-hole etching areas.
  • An electrical connection part is provided: an electrical connection part is provided on the other side of the quartz wafer, and the electrical connection part is electrically connected to the first electrode on one side of the quartz wafer via a through-hole etching area, the The electrical connection part is spaced apart from the same side as the electrode lead-out part of the second electrode provided on the other side of the quartz wafer; and
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned quartz resonator.
  • 1-18 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention
  • 19-32 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention.
  • FIG. 33 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • 34-53 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention.
  • 54-56 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • Figure 57 is a schematic flow chart of fundamental frequency adjustment in the resonance area of a quartz wafer
  • Figure 58 is a schematic flowchart of resonant frequency adjustment of a quartz resonator.
  • the present invention proposes a quartz wafer manufacturing process based on micro/nano electromechanical systems (M/NEMS) photolithography technology, which can be used to produce small-sized, frequency-accurate quartz resonators.
  • M/NEMS micro/nano electromechanical systems
  • a wafer-level frequency/thickness monitoring and control method is adopted, which reduces the requirements for the uniformity of quartz wafer thickness processing and reduces the processing difficulty.
  • This solution is universally applicable to the manufacturing of quartz wafers in different frequency bands, and is not limited by the area of the quartz wafer, so it has obvious advantages.
  • the present invention's wafer manufacturing solution based on micro-nano electromechanical systems makes full use of the advantages of MEMS photolithography technology and wafer-level process manufacturing methods, and uses the method of wet etching wafer contours to get rid of the impact of cutting technology on wafer size. Limitation, can realize the processing of smaller size wafers of 1210, 1008 and below.
  • wafer processing solutions for wafer manufacturing can improve dimensional processing accuracy and improve wafer processing efficiency.
  • the present invention proposes a wafer-level wafer manufacturing and frequency control process, which eliminates the need for ultra-high-precision grinding technology for quartz wafers, and at the same time greatly reduces the difficulty of frequency modulation, making frequency modulation completely unconstrained by wafer area expansion.
  • this solution meets the requirements for miniaturized manufacturing of wafers from low frequency to high frequency (30-300MHz) and ultra-high frequency (300MHz-3GHz), and is of great significance to promoting the development of the quartz wafer field.
  • Top electrode the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the electrical connection part of the top electrode The material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys.
  • the top electrode and its electrical connections, the bottom electrode and its electrical connections may be the same metal material.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • Metal bonding layer which can be gold-gold, gold-tin, copper-tin bonding, etc.
  • each part is described using a feasible material as an example, but is not limited thereto.
  • FIGS. 1-18 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • the following is an example of the manufacturing process of a quartz resonator with reference to Figures 1-18, which includes the following steps:
  • Step 1 Make mask 20A.
  • a mask 20A is made on one side (for example, the front) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 ⁇ m to 1 mm) using micro/nano electromechanical system photolithography.
  • the mask 20A is patterned to form mask openings 22. Specifically, the area used to prepare the via hole, that is, the via hole etching area 14, and the profile etching area 18 used to form the outline are exposed.
  • a mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
  • the profile etching area may not be provided.
  • the mask can be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal;
  • the mask can be SU-8 glue, or other photoresists suitable for dry etching.
  • the material of the mask 20A can also be applied to other embodiments, which will not be described again below.
  • Step 2 Wet etching.
  • the mask 20A is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer. 10 is etched, and the etching depth is d 1 (d 1 is equal to the quartz film thickness d 0 corresponding to the set frequency of the quartz resonator).
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • d 1 is equal to the quartz film thickness d 0 corresponding to the set frequency of the quartz resonator.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in FIG. 3 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 4 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the top electrode 30 covers the via etching area 14, and optionally, covers a partial area between the via etching area and the frame.
  • Step 5 Join the first package substrate.
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the junction between the first packaging substrate 50 and the quartz wafer 10 72A.
  • Step 6 Quartz wafer thinning. As shown in FIG. 6 , the quartz wafer 10 is thinned by grinding and polishing processes until the remaining thickness is within, for example, 1 ⁇ m compared to the design value (ie, the film thickness d 0 mentioned above).
  • Step 7 Wafer-level film thickness measurement.
  • the thickness of the polished quartz wafer in the resonant region was measured using optical methods. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the optical measurement method of transparent film thickness is used to measure the quartz film thickness in the resonance area of each wafer, and the difference between it and the design value d0 is obtained, which provides a basis for the next step of adjusting the film thickness of each wafer. according to.
  • Step 8 Adjust quartz film thickness. As shown in Figure 8, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 7 and Figure 8 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 57.
  • Step 9 Make the bottom electrode.
  • the resonator bottom electrode 40 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 10 Set a through-hole perforation mask 20B on the upper surface of the structure shown in Figure 9. As shown in Figure 10, the mask 20B is provided with a mask opening at a position corresponding to the through-hole etching area 14. The mask 20B The bottom electrode 40 is covered.
  • Step 11 For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14 to penetrate the through-hole etching area 14, as shown in FIG. 11 .
  • Step 12 Remove mask 20B. After step 11, the mask 20B can be removed by wet etching to obtain the structure as shown in FIG. 12.
  • Step 13 Set the electrical connection part 32 of the top electrode, which is set on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other, as shown in FIG. 13 .
  • Step 14 Make a frame mask 20C.
  • the opening pattern of the mask 20C is aligned with the frame pre-etched on the side of the quartz wafer. The accuracy needs to be controlled within 1 ⁇ m to ensure that the edge position of the wafer outline is consistent with the light. The positions of the edges of the unprotected areas of the resist mask coincide with each other.
  • the mask 20C is provided with mask openings at positions corresponding to the contour etched areas 18 at the frame.
  • Mask 20C covers the bottom electrode 40 and electrical connections 32 of the structure obtained in step 13.
  • Step 15 For example, dry etching is used to etch the portion of the quartz wafer 10 at the contour etching region 18 at the frame through the mask openings on the mask 20C to penetrate the contour etching region 18 , as shown in Figure 15.
  • Step 16 Remove mask 20C. After step 15, the mask 20C can be removed by wet etching to obtain the structure as shown in Figure 16.
  • Step 17 Frequency measurement and frequency modulation. If the measured resonant frequency of the quartz resonator is less than the predetermined resonant frequency, the mass of the top electrode 30 can be changed using, for example, a particle beam to increase the resonant frequency of the quartz resonator. As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 58.
  • Step 18 Bond the second package substrate.
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second package substrate 60 is provided with a conductive through hole 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • the resonant region of the formed resonator is a cantilever structure. More specifically, due to the presence of the contour etching hole 18 , the non-electrode connection end of the main body part of the resonator is a free end.
  • This structure can produce the following technical effects: reduce the lateral leakage of energy, improve the performance of the resonator, and at the same time reduce/isolate the impact of external vibration, heat and other factors on the performance of the resonator.
  • the electrical connection portion 32 and the bottom electrode 40 can also be prepared at the same time after the through-hole etching region 14.
  • a segmentation operation can be performed to form the final packaged quartz resonator into individual devices.
  • the packaging substrate may be a quartz substrate or a substrate made of other materials, such as silicon, glass, sapphire, etc. No further details will be given in the following embodiments.
  • the packaging substrate when it is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the packaging substrate is made of transparent material. Therefore, frequency modulation can also occur after the packaging is completed, using laser to directly adjust the frequency through the transparent quartz packaging cover to adjust the frequency changes caused by packaging stress. No further details will be given in the following embodiments.
  • the side of the first packaging substrate and/or the second packaging substrate facing the resonator is a flat surface.
  • the piezoelectric layer of the formed resonator is provided with electrical connection through holes or through holes 14 in the non-resonant area, and the lead-out portion of the electrode on the piezoelectric layer side extends to The other side of the piezoelectric layer is thus on the same side of the piezoelectric layer as the electrode on the other side.
  • the lead-out parts of the electrodes are respectively arranged on both sides of the piezoelectric layer, which has the following technical effects: reducing the packaging complexity; in addition, compared with the prior art, the lead-out part of an electrode reaches the edge of the piezoelectric layer through the edge of the piezoelectric layer.
  • the other side is arranged on the same plane as the lead-out part of the other electrode, which has the following technical effect: reducing/avoiding the problem of unstable electrode resistance that may exist when the electrode crosses the piezoelectric layer.
  • the through contour etching holes 18 constitute spaced through holes, which makes the part of the piezoelectric layer bonded to the packaging substrate (ie, the piezoelectric layer packaging part) and the resonance area of the piezoelectric layer
  • the spacer vias are mechanically separated, ie there is no mechanical physical connection.
  • FIGS. 1 to 18 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention.
  • the resonance structure of the quartz resonator adopts a single-sided reverse platform structure.
  • this structure has better structural stability and improves the chip's impact resistance.
  • the corresponding manufacturing process has changed.
  • the difference is that in step 1, as shown in Figure 19, the opening part of the mask 20A is a resonance area and a through hole area.
  • Subsequent steps 2-13 ( Figure 20-31) are consistent with the relevant process steps of steps 2-17 shown in Figures 1-18, and the bonding process is also consistent.
  • the embodiments shown in Figures 19 to 32 also provide a new packaging structure (as shown in Figure 32).
  • Step 1 Make mask 20A.
  • a mask 20A is made on one side (for example, the front) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 ⁇ m to 1 mm) using micro/nano-electromechanical system photolithography.
  • the mask 20A is patterned to form mask openings 22 , specifically, the areas used to prepare through holes and the resonant region 12 are exposed.
  • a mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
  • Step 2 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
  • the resonant region of the quartz wafer is partially etched.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in Figure 21, after the quartz wafer 10 is etched, it can be Cleaning and drying are performed, and then the mask 20A is removed by wet etching.
  • Step 4 Make the top electrode.
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the top electrode 30 covers the via etching area 14, and optionally, covers a partial area between the via etching area 14 and the frame.
  • Step 5 Join the first package substrate.
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • Step 6 Quartz wafer thinning. As shown in FIG. 24 , the quartz wafer 10 is thinned by grinding and polishing processes until the remaining thickness of the resonance region is within, for example, 1 ⁇ m compared with the design value (ie, the film thickness d 0 mentioned above).
  • Step 7 Wafer-level film thickness measurement.
  • the optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film. As shown in Figure 25, the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 8 Adjust quartz film thickness. As shown in Figure 26, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 25 and Figure 26 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 57.
  • Step 9 Set a through-hole perforation mask 20B on the upper surface of the structure shown in Figure 26. As shown in Figure 27, the mask 20B is provided with mask openings at positions corresponding to the through-hole etching areas 14.
  • Step 10 For example, dry etching is used to etch the portion of the quartz wafer 10 located at the through-hole etching area 14 to form the through-hole 14 through the through-hole etching area 14, as shown in FIG. 28 .
  • Step 11 Remove mask 20B. After step 10, the mask can be removed by wet etching 20B to obtain the structure shown in Figure 29.
  • Step 12 Make the bottom electrode and electrical connections.
  • the resonator bottom electrode 40 and the electrical connection portion 32 are fabricated on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the bottom electrode 40, the top electrode 30, and the quartz piezoelectric layer together form a sandwich structure.
  • the electrical connection portion 32 is electrically connected to the through-hole etching area 14 or the metal in the through-hole 14 , and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
  • Step 13 Frequency measurement and frequency modulation.
  • the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the quality of the quartz resonator.
  • Resonant frequency when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 58.
  • Step 14 Bond the second package substrate.
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second packaging substrate 60 is provided with a conductive through hole 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • FIG. 33 is a schematic cross-sectional view of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • the structure shown in FIG. 33 is different from the structure shown in FIG. 32 only in the position of the conductive through hole 64, and other structures will not be described again.
  • the conductive via 64 is aligned with the via 14
  • the conductive via 64 is offset from the via 14 .
  • Such misaligned packaging helps to improve the stability of the structure and reduce air-tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues.
  • through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes.
  • a segmentation operation can be performed to form the final packaged quartz resonator into separate device.
  • FIGS. 34 to 53 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to yet another exemplary embodiment of the present invention.
  • the resonance structure of the quartz resonator adopts a double-sided counter-elevation structure.
  • this structure has better structural stability and improves the impact resistance of the chip.
  • the structure shown in Figures 34 to 53 can improve the boundary of the resonance area of the chip and reduce the lateral leakage of sound waves; in addition, the double-sided reverse platform structure provides space for the vibration area, which can avoid digging grooves on the package cover and contribute to the stability of the chip. Thinner.
  • Step 1 Make mask 20A.
  • a mask 20A is made on one side (for example, the front) of a quartz wafer (for example, with a diameter of 1-8 inches and a thickness of 100 ⁇ m to 1 mm) using micro/nano-electromechanical system photolithography.
  • Mask 20A is patterned to form mask openings 22 and the area of resonant region 12 is covered.
  • a mask 20A is also provided on the other side of the quartz wafer 10 (for example, the secondary surface), covering the entire other side.
  • Step 2 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching For example, under the action of high-temperature and high-concentration etching solutions, higher etching rates and steeper crystal plane slopes can be obtained.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Further pattern the mask 20A to expose the resonant regions, as shown in Figure 36.
  • Step 4 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • Carry out etching In Figure 37, a part of the resonance area of the quartz wafer is etched, and at the same time, the through hole etching area 14 is further etched. In this way, in Figure 37, the depth of the through hole etching area 14 is greater than the etching depth of the resonance area. .
  • step 4 may also be replaced by dry etching, or wet etching may be combined with dry etching.
  • Step 5 Remove mask 20A. As shown in FIG. 38 , after the quartz wafer 10 is etched, the mask 20A can be removed by cleaning, drying, and then wet etching.
  • Step 6 Make the top electrode.
  • metal sputtering or evaporation is used to achieve the above
  • the resonator top electrode 30 is fabricated on the quartz wafer 10 .
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Top electrode 30 covers via etched area 14 .
  • Step 7 Join the first package substrate.
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the first packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • Step 8 Quartz wafer thinning. As shown in FIG. 41 , the quartz wafer 10 is thinned by grinding and polishing processes.
  • Step 9 Make mask 20D.
  • a mask 20D is fabricated using micro/nano electromechanical system photolithography on the structure shown in FIG. 41 , and is patterned to form mask openings 22 and expose the resonant region.
  • the material of mask 20D may be the same as that of mask 20A.
  • Step 10 Wet etching.
  • the mask 20D in Figure 42 is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to The quartz wafer 10 described above is etched.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • a double-sided reverse mesa structure is formed, and a through-hole etching area 14' opposite to the through-hole etching area 14 on one side is also formed on the other side of the quartz wafer 10, as shown in Figure 43.
  • the etching depth of the via etching region 14 ′ is consistent with the etching depth of the resonance region on the other side of the quartz wafer 10 .
  • the etching depth between the via etching region 14 ′ and the via Part of the quartz piezoelectric layer remains between the hole etching areas 14 .
  • step 10 may also be replaced by dry etching, or wet etching may be combined with dry etching.
  • Step 11 Remove mask 20D. As shown in FIG. 44 , the structure shown in FIG. 43 can be cleaned, dried, and then the mask 20D is removed by wet etching.
  • Step 12 Wafer-level film thickness measurement.
  • Optical methods were used to measure the quartz thickness in the resonance area after grinding. Perform thickness measurement. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 13 Adjust quartz film thickness.
  • the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 45 and Figure 46 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 57.
  • Step 14 Make the bottom electrode.
  • the resonator bottom electrode 40 is formed on the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • the bottom electrode 40, the top electrode 30, and the quartz piezoelectric layer together form a sandwich structure.
  • Step 15 Make mask 20E.
  • a mask 20E is produced on the structure shown in Figure 47 using micro/nano electromechanical system photolithography, and is patterned to form a mask opening 22, which is exposed in step 10.
  • the mask 20E covers the bottom electrode 40.
  • the material of mask 20E may be consistent with that of mask 20A.
  • Step 16 For example, use dry etching to etch the portion of the quartz wafer 10 located at the through-hole etching area 14' to penetrate the through-hole etching area 14', as shown in Figure 49.
  • Step 17 Remove mask 20E.
  • the structure shown in FIG. 49 can be cleaned, dried, and then the mask 20E is removed by wet etching.
  • Step 18 Make the electrical connection part 32.
  • the electrical connection portion 32 is formed on the quartz wafer 10 by metal sputtering or evaporation.
  • the electrical connection portion 32 is electrically connected to the metal in the via etching area 14, and is disposed on the same side of the quartz wafer 10 as the bottom electrode 40 and is spaced apart from each other.
  • Step 19 Frequency measurement and frequency modulation.
  • the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the quality of the quartz resonator.
  • Resonant frequency when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 58.
  • Step 20 Bond the second package substrate.
  • the second packaging substrate 60 and the quartz wafer 10 may utilize metal diffusion bonds. Bonded together, it can be gold-gold, gold-tin, copper-tin bonding, etc. They can also be joined together in other ways, which are not limited here.
  • the second packaging substrate 60 is provided with a conductive through hole 64 that is electrically connected to the electrical connection portion 32 of the top electrode 30 .
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it can be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • a segmentation operation may be performed to form the final packaged quartz resonator into individual devices.
  • FIGS. 54-56 are schematic cross-sectional views of a packaging structure of a quartz resonator according to another exemplary embodiment of the present invention.
  • the structure shown in Figures 54-56 is different from the structure shown in Figure 53 only in the position or structure of the conductive via 64, and other structures will not be described again.
  • conductive vias 64 are offset from vias 14 .
  • Such misaligned packaging helps to improve the stability of the structure and reduce air-tightness damage caused by through-hole damage caused by stress, mechanical deformation and other issues.
  • through-hole dislocation can shield to a certain extent the noise caused by interference such as stress, heat, and electromagnetic signals transmitted through the through-holes.
  • the structure shown in Figure 55 improves the through-hole manufacturing process and changes the cross-sectional shape of the through-hole to a vertical type, thereby improving the air tightness of the through-hole.
  • changing the package bottom plate to a flat plate helps reduce the total thickness of the chip and improves the mechanical stability of the resonance area.
  • micro/nano electromechanical systems (M/NEMS) photolithography technology is used in combination with wet etching/dry etching to: make the size of the particles less than 1 mm ⁇ 1 mm; and/or The thickness of the resonant region of the shot particles is less than 40 ⁇ m or the fundamental frequency of the resonator formed based on the shot particles is above 40 MHz.
  • M/NEMS micro/nano electromechanical systems
  • micro/nano electromechanical system photolithography technology it is possible to obtain fine patterns for subsequent etching that facilitate the formation of particle sizes less than 1 mm ⁇ 1 mm, while based on wet etching/dry etching, it is possible to Obtain particles with a size less than 1mm ⁇ 1mm; based on wet etching/dry etching, it can replace the mechanical mask to obtain a quartz piezoelectric layer thickness less than 40 ⁇ m.
  • the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode of the quartz resonator are on the same side of the piezoelectric layer, which is beneficial to: reducing/avoiding possible problems when the electrodes cross the piezoelectric layer.
  • the technical problem of unstable electrode resistance is beneficial to: reducing/avoiding possible problems when the electrodes cross the piezoelectric layer. The technical problem of unstable electrode resistance.
  • the electrical connection via or at least part of the via 14 is a tapered hole, or more specifically , the cross-section of the electrical connection through hole is a shape that shrinks from the upper and lower sides of the boss to the middle, which is beneficial to the uniformity of electrode distribution and thus obtains a stable resistance value.
  • the resonant region refers to the overlapping region of the top electrode, bottom electrode, piezoelectric layer, and cavity or gap in the thickness direction of the piezoelectric layer in the formed quartz resonator.
  • the resonance area of the wafer corresponds to the area in the wafer that needs to be formed as a resonance area of the resonator;
  • the resonance area of the piezoelectric layer corresponds to the area in the piezoelectric layer that needs to be formed as the resonance area of the resonator.
  • the non-resonant region is a portion outside the resonant region.
  • the non-resonant region of the piezoelectric layer refers to the region outside the resonant region of the piezoelectric layer in the horizontal or lateral direction. It should be pointed out that in the present invention, each numerical range, except that it is clearly stated that it does not include the endpoint value, can be the endpoint value or the median value of each numerical range, which are all within the protection scope of the present invention. .
  • the quartz resonator according to the present invention can be used to form a quartz crystal oscillator chip or an electronic device including a quartz resonator.
  • the electronic device here may be an electronic component such as an oscillator, a communication device such as a walkie-talkie or a mobile phone, or a large-scale product using a quartz resonator such as an automobile.
  • a quartz resonator including:
  • One of the top electrode and the bottom electrode is a first electrode and the other is a second electrode, the first electrode is on one side of the piezoelectric layer, and the second electrode is on the other side of the piezoelectric layer;
  • the piezoelectric layer is provided with an electrical connection through hole in the non-resonant region, and the electrode lead-out portion of the first electrode extends to the other side of the piezoelectric layer through the electrical connection through hole to communicate with the second electrode. on the same side of the piezoelectric layer.
  • the piezoelectric layer is an inverted platform structure including a boss, and the electrical connection through hole is provided through the boss.
  • the piezoelectric layer has a double-sided reverse platform structure.
  • the cross-section of the electrical connection through hole is a shape that shrinks from the upper and lower sides of the boss toward the middle.
  • the piezoelectric layer has a single-sided reverse platform structure.
  • the piezoelectric layer has a flat structure.
  • the resonator is a cantilever structure.
  • At least a portion of the electrical connection through hole is a tapered hole.
  • the size of the piezoelectric layer is less than 1mm ⁇ 1mm; and/or
  • the thickness of the resonant region of the piezoelectric layer is less than 40 ⁇ m or the fundamental frequency of the resonator is above 40 MHz.
  • the packaging structure includes a first substrate and a second substrate, and the piezoelectric layer is disposed between the first substrate and the second substrate;
  • the packaging structure includes a joint sealing layer, the joint sealing layer includes a piezoelectric layer packaging part, the piezoelectric layer packaging part is a part of the piezoelectric layer, and the piezoelectric layer packaging part is connected to the first substrate and the third substrate respectively. The two substrates are bonded.
  • Both the first substrate and the second substrate are quartz substrates.
  • a cavity is provided on a side of the first substrate and/or the second substrate facing the piezoelectric layer, and the projection of the resonance region of the quartz resonator in the thickness direction falls into the cavity.
  • Both the first substrate and the second substrate are quartz substrates, and the cavity has a right-angled trapezoidal cross-section.
  • the side of the first substrate and/or the second substrate facing the resonator is a flat surface
  • the side of the piezoelectric layer of the resonator facing the flat surface has an inverted platform structure.
  • the piezoelectric layer also includes spaced vias
  • the piezoelectric layer has a flat structure, and the piezoelectric layer encapsulation portion is mechanically isolated from the resonant region of the piezoelectric layer via the spacing through holes.
  • the piezoelectric layer includes a boss outside the resonance area, the electrical connection via penetrates the boss, and a portion of the boss outside the electrical connection through hole includes the piezoelectric layer encapsulation department.
  • the first substrate and the second substrate on the other side of the piezoelectric layer are provided with substrate through conductive holes;
  • the substrate through conductive hole is electrically connected to a portion of the electrode lead-out portion of the first electrode extending to the other side of the piezoelectric layer through the electrical connection through hole.
  • the substrate through conductive hole and the electrical connection through hole are staggered in the horizontal direction; or
  • the substrate through conductive hole and the electrical connection through hole are aligned in the thickness direction.
  • the conductive holes penetrating the substrate are straight holes, tapered holes, or holes with upper and lower sides narrowing toward the middle.
  • An electronic device including the quartz resonator according to any one of 1-20.
  • a method of manufacturing a quartz resonator including the steps:
  • a quartz wafer including a resonant region for forming a plurality of quartz resonators
  • Etching At least using micro/nano electromechanical system photolithography technology to form multiple through-hole etching areas in the non-resonant area of the quartz wafer at predetermined positions on one side of the quartz wafer;
  • a first electrode layer including a first electrode, the first electrode layer covering the corresponding through hole etching area;
  • Penetration At least using micro/nano electromechanical system photolithography technology, etching through the through-hole etching area at the position corresponding to the through-hole etching area on the other side of the quartz wafer to expose the first electrode layer;
  • An electrical connection part is provided: an electrical connection part is provided on the other side of the quartz wafer, and the electrical connection part is electrically connected to the first electrode on one side of the quartz wafer via a through-hole etching area, the Electrical connection part It is spaced apart from the same side as the electrode lead-out portion of the second electrode provided on the other side of the quartz wafer; and
  • the etching steps include:
  • Setting a patterned first mask setting a first mask on one side and the other side of the quartz wafer, and using micro/nano electromechanical system photolithography technology to pattern the first mask on the side of the quartz wafer.
  • Mask patterning, the patterned first mask includes a plurality of first mask holes;
  • Forming a through-hole etching area forming a through-hole etching area on one side of the quartz wafer at a position corresponding to the first mask hole;
  • Set a patterned second mask set a second mask on the other side of the piezoelectric layer, and pattern the second mask to expose the other side of the piezoelectric layer corresponding to the through hole engraved part of the erosion zone;
  • Through-hole etching area Etch the part corresponding to the through-hole etching area on the other side of the piezoelectric layer to penetrate through the through-hole etching area;
  • Providing the electrical connection is synchronized with providing the second electrode layer including the second electrode.
  • the steps further include:
  • First thinning Perform a thinning on the quartz wafer on the other side of the quartz wafer. There is a gap in the thickness direction between the other side of the quartz wafer after the first thinning and the through-hole etching area. The distance is within 1 ⁇ m;
  • Measurement or secondary thinning Use optical methods to measure whether the thickness of the resonance area of the quartz wafer reaches the predetermined thickness on the other side of the quartz wafer, and measure the thickness on the other side of the quartz wafer if the predetermined thickness is not reached.
  • the quartz wafer is subjected to secondary thinning so that the thickness of the quartz wafer in the resonance region reaches a predetermined thickness.
  • the etching step further includes forming a contour etching area of the quartz resonator on the side of the quartz wafer;
  • the method further includes the step of etching through the profile etching area after etching through the through hole etching area.
  • the method also includes the steps of:
  • Bonding the first packaging substrate bonding the first packaging substrate to the quartz wafer provided with the first electrode layer on the side of the quartz wafer, the first electrode facing the first packaging substrate;
  • Joining the second packaging substrate joining the second packaging substrate and the quartz wafer provided with the second electrode layer on the other side of the quartz wafer to form a composite structure, the second electrode and the second packaging substrate Oppositely, the second packaging substrate is provided with a plurality of substrate through conductive holes, and the plurality of substrate through conductive holes are electrically connected to corresponding electrical connection portions, and
  • the step of dividing includes dividing the composite structure to form individual quartz resonators.
  • the first packaging substrate and/or the second packaging substrate are quartz substrates.
  • the patterned first mask covers the resonance area of the quartz wafer
  • the patterned second mask covers the resonance area of the quartz wafer
  • the first packaging substrate pre-set with the first cavity is joined to the quartz wafer provided with the first electrode layer, the first electrode layer and the first cavity surface right;
  • the second packaging substrate pre-set with the second cavity is joined to the quartz wafer provided with the second electrode layer, and the second electrode layer is connected to the surface of the second cavity. right.
  • the patterned first mask further includes a second mask hole
  • etching step a plurality of contour etching areas are formed on one side of the quartz wafer at positions corresponding to the second mask holes based on wet etching;
  • the method further includes the step of: setting a third mask on the other side of the quartz wafer whose thickness in the resonant region reaches a predetermined thickness, and patterning the third mask to form a third mask corresponding to the contour etching area.
  • the first packaging substrate and the second packaging substrate are both bonded to portions of the quartz wafer outside the contour etching area.
  • the patterned first mask further includes a second mask hole
  • etching step a plurality of contour etching areas are formed on one side of the quartz wafer at positions corresponding to the second mask holes based on wet etching;
  • the first packaging substrate and the second packaging substrate are both bonded to portions of the quartz wafer outside the contour etching area.
  • the patterned first mask exposes the resonant area of the quartz wafer.
  • the first packaging substrate pre-set with the first cavity is Or the first packaging substrate including the first flat surface is bonded to the quartz wafer provided with the first electrode layer, the first electrode layer faces the first cavity or the first flat surface; and/or
  • the patterned second mask exposes the resonance area of the quartz wafer, and in the step of bonding the second packaging substrate, the second packaging substrate pre-set with the second cavity is Or the second packaging substrate including the second flat surface is bonded to the quartz wafer provided with the second electrode layer, and the second electrode layer faces the second cavity or the second flat surface.
  • Measurement or frequency modulation measure the resonant frequency of the resonant area where the electrical connection part and the second electrode are set, and when the measured resonant frequency is less than the predetermined resonant frequency, raise the resonant frequency of the resonant area to the predetermined resonant frequency.
  • wet etching is used to form multiple through-hole etching areas;
  • dry etching is used to etch through the through hole etching area.

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Abstract

本发明涉及一种石英谐振器及其制造方法，所述石英谐振器包括：底电极；顶电极；和石英压电层，其中：顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧。本发明还涉及一种电子器件。

Description

电极引出部处于同侧的石英谐振器及其制造方法、电子器件 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种电极引出部处于同侧的石英谐振器及其制造方法，以及一种电子器件。
背景技术
高基频、小型化和低矮化是石英晶振片(下文中简称为晶片)发展的趋势。传统晶片制造方案多采用研磨切片的方式获得一定频率的散粒薄片，然后进行后续的镀电极与调频。然而，切片所采用的线切割技术对1mm×1mm及以下尺寸难以实现，基本无法覆盖1.2mm×1.0mm及以下尺寸的晶片制造，更无法满足1.0mm×0.8mm及以下尺寸规格晶片制造。晶片的基频主要受晶片谐振区域的厚度决定，晶片的基频由以下公式支配：
f0(MHz)＝1670(MHz·μm)/d(μm)      (1)
晶圆级制造可以实现单颗谐振器制造成本的大幅降低，以及谐振器之间的品控一致性；通常来说，晶圆尺寸越大，单颗谐振器的制造成本越低。然而，对于晶圆级制造方案，几百至数千颗晶片排列在单片晶圆上，对各个位置点石英厚度的精确控制挑战巨大，这也就直接导致了整片晶圆上晶片频率的准确性与一致性难以得到保证。因此，晶圆级晶片调频存在极大的挑战。目前已有技术采取的办法主要集中在采用具有超高精度膜厚监控系统的研磨技术，制备厚度均一度在几纳米之内的石英薄膜。这种频率控制与调节技术对材料和制造工 艺提出了极高的要求，而且晶圆面积越大，制造难度越高，阻碍了低成本、高效率的制造方案的产生。
现有的石英谐振器的顶电极的电极引出部和底电极的电极引出部中的一个经由压电层的边缘延伸到与另一个电极引出部同侧的位置，这种跨压电层布置电极引出部的方式，容易出现电极连接电阻不稳定(偏大甚至电连接断开)的问题。
此外，还希望在晶圆级制造单颗谐振器的基础上，优化谐振器的边界条件、减少声波横向泄漏，从而进一步提高谐振器的性能。但是，通过现有的机械研磨减薄方式难以优化谐振器的边界条件。
发明内容
为缓解或解决现有技术中的上述问题的至少一个方面，提出本发明。
根据本发明的实施例的一个方面，提出了一种石英谐振器，包括：
底电极；
顶电极；和
石英压电层，
其中：
顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧。
根据本发明的实施例的另一方面，提出了一种石英谐振器的制造方法，包括步骤：
提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
刻蚀：至少利用微/纳机电系统光刻技术，在石英晶圆的一侧的预定位置，基于湿法刻蚀在石英晶圆的非谐振区域形成多个通孔刻蚀区；
设置第一电极层：对于每个石英谐振器，顶电极和底电极中的一个电极为第一电极，顶电极和底电极中的另一个电极为第二电极，在石英晶圆的一侧设置包括了第一电极的第一电极层，第一电极层覆盖对应的通孔刻蚀区；
贯穿：至少利用微/纳机电系统光刻技术，在石英晶圆的另一侧的与所述通孔刻蚀区对应的位置，基于干法刻蚀贯穿所述通孔刻蚀区以露出所述第一电极层；
设置电连接部：在石英晶圆的另一侧设置电连接部，所述电连接部经由贯穿的通孔刻蚀区电连接到处于石英晶圆的一侧的所述第一电极，所述电连接部与设置在石英晶圆的另一侧的第二电极的电极引出部同侧间隔开设置；和
分割：在上述步骤之后，至少将石英晶圆切割或者裂片，以形成石英谐振器。
本发明的实施例还涉及一种电子器件，包括上述的石英谐振器。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1-18为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图；
图19-32为根据本发明的另一个示例性实施例的石英谐振器的制作过程的截面示意图；
图33为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图；
图34-53为根据本发明的又一个示例性实施例的石英谐振器的制作过程的截面示意图；
图54-56为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图；
图57为石英晶圆的谐振区域的基频调节的流程示意图；
图58为石英谐振器的谐振频率调节的流程示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解 为对本发明的一种限制。发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
本发明提出一种基于微/纳机电系统(M/NEMS)光刻技术的石英晶片制造工艺，可以用于制作小尺寸、频率精准的石英谐振器。本发明中，采用了晶圆级频率/厚度监测与调控方法，降低了对石英晶圆片厚度加工均一度的要求，降低了加工难度。本方案对不同频段的石英晶片的制造普遍适用，并且不受石英晶圆面积的限制，具有明显的优势。
本发明基于微纳机电系统(M/NEMS)的晶片制造方案充分利用了MEMS光刻技术和晶圆级工艺制造方式的优势，利用湿法刻蚀晶片轮廓的方法，摆脱了切割技术对晶片尺寸的限制，可以实现1210、1008及以下更小尺寸晶片的加工。此外，晶圆制造的晶片加工方案能够提高尺寸加工精度，提高晶片加工效率。
本发明提出了一种晶圆级晶片制造与频率控制制程，摆脱了石英晶片对超高精度研磨技术的需求，同时大大降低了调频的难度，使得调频完全不受晶圆面积扩大的制约。同时，该方案满足了从低频到高频(30-300MHz)、超高频率(300MHz-3GHz)晶片的小型化制造，对推动石英晶片领域的发展具有重要意义。
下面参照图1-53示例性说明根据本发明的石英谐振器的制作过程。本发明中，附图标记示意性说明如下：
10：石英晶圆或晶圆或压电层。
12：谐振区域。
14：通孔刻蚀区或通孔。
14’：通孔刻蚀区
16：压电层封装部。
18：轮廓刻蚀区。
20A：第一掩膜层或掩膜。
20B：第二掩膜层或掩膜。
20C：第三掩膜层或掩膜。
20D：第四掩膜层或掩膜。
20E：第五掩膜层或掩膜。
22：掩膜槽或掩膜开孔。
30：顶电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
32：顶电极的电连接部，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。在可选的实施例中，顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。
40：底电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
50：第一封装基板或石英晶圆。
52：第一空腔。
60：第二封装基板或石英晶圆。
62：第二空腔。
64：导电通孔或导电孔。
72A、72B：金属键合层，可以是金金、金锡、铜锡键合等方式。在本发明的具体实施例中，各部分以其中可行的一种材料为例进行说明，但不限于此。
图1-图18为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图。下面参照图1-图18示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图1所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20A，处于正面的掩膜20A被图案化，以形成掩膜开孔22，具体的，用于制备通孔的区域，即通孔刻蚀区14，以及用于形成轮廓的轮廓刻蚀区18，被露出。在石英晶圆10的另一侧(例如次面)也设置掩膜20A，其覆盖整个另一侧。如能够理解的，在一个可选实施例中，可以不设置轮廓刻蚀区。
这里，对于后续使用湿法刻蚀(例如图1-图18所示实施例的步骤2)，掩膜可以是金属掩膜，例如铬金(上面一层金、下面一层铬)，或者其他惰性金属；对于后续使用干法刻蚀(例如图1-图18所示实施例的步骤2)，掩膜可以是SU-8胶，或者其他适合干法刻蚀的光刻胶。掩膜20A的材料也可以适用于其他实施例，后面不再赘述。
需要指出的是，在图1-图18中，仅仅示出了晶圆上的单个石英谐振器对应 的区域，如能够理解的，在石英晶圆10上存在多个图1-图18所示的区域。在其他的实施例中，也应做相似的理解，后面不再赘述。
步骤2：湿法刻蚀。如图2所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀，刻蚀深度为d1(d1等于石英谐振器设定频率对应的石英膜厚d0)。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：去除掩膜20A。如图3所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤4：制作顶电极。如图4所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14，以及可选的，覆盖了通孔刻蚀区与边框之间的部分区域。
步骤5：接合第一封装基板。如图5所示，将上述石英晶圆10与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准，使得顶电极30恰好位于第一空腔52之内。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。封装基板50也可以采用其他的封装材料。
在本发明的实施例中，第一封装基板50是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图5所示的实施例中，在第一封装基板50与石英晶圆10之间以金属键合的情况下，第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。
步骤6：石英晶圆减薄。如图6所示，利用研磨与抛光工艺对石英晶圆10进行减薄，减薄至剩余厚度比设计值(即上述膜厚d0)富余值在例如1μm之内。
步骤7：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英晶圆厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图7所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依 据。
步骤8：调节石英薄膜厚度。如图8所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图7和图8操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图57。
步骤9：制作底电极。如图9所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40。底电极40至少由一层金属构成，其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。
步骤10：在图9所示结构的上表面设置通孔穿孔掩膜20B，如图10所示，掩膜20B在对应于通孔刻蚀区14的位置设置有掩膜开孔，掩膜20B覆盖住了底电极40。
步骤11：例如，利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14处的部分，以贯穿通孔刻蚀区14，如图11所示。
步骤12：去除掩膜20B。步骤11之后，可以利用湿法刻蚀的方式去除掩膜20B，以得到如图12所示的结构。
步骤13：设置顶电极的电连接部32，其与底电极40设置在石英晶圆10的同一侧且彼此间隔开，如图13所示。
步骤14：制作边框掩膜20C，掩膜20C的开孔图案与在石英晶圆的所述一侧所预先刻蚀所得边框对齐，准精度需要控制在1μm之内，确保晶片轮廓边缘位置与光刻胶掩膜的未保护区域边缘的位置重合，在图14中，掩膜20C在与边框处的轮廓刻蚀区18对应的位置设置了掩膜开孔。掩膜20C覆盖住了步骤13中所得的结构的底电极40和电连接部32。
步骤15：例如，经由掩膜20C上的掩膜开孔利用干法刻蚀的方式刻蚀石英晶圆10的处于在边框处的轮廓刻蚀区18处的部分，以贯穿轮廓刻蚀区18，如图15所示。
步骤16：去除掩膜20C。步骤15之后，可以利用湿法刻蚀的方式去除掩膜20C，以得到如图16所示的结构。
步骤17：测频与调频。测量所得的石英谐振器的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图58。
步骤18：接合第二封装基板。如图18所示，将步骤17中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准，使得底电极40恰好位于第二空腔62之内。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。如图18所示，第二封装基板60设置有导电通孔64，其与顶电极30的电连接部32电连接。
在本发明的实施例中，第二封装基板60是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图18所示的实施例中，在第二封装基板60与石英晶圆10之间以金属键合的情况下，第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。
如图18所示，所形成的谐振器的谐振区域为悬臂结构，更具体的，由于轮廓刻蚀孔18的存在，使得谐振器的主体部分的非电极连接端为自由端。该结构可以产生如下技术效果：减少了能量横向泄露，提升谐振器性能，同时可以减小/隔绝外界震动、热量等因素对谐振器性能的影响。
在可选的实施例中，在上述的步骤9-步骤13中，也可以在贯穿通孔刻蚀区14之后，同时制备电连接部32以及底电极40。
步骤18之后，可以执行分割操作，以将最终封装形成的石英谐振器形成为单独的器件。
在本发明中，封装基板可以是石英基板，也可以其他材料的基板，如硅、玻璃、蓝宝石等。在后面的实施例中不再赘述。在本发明中，封装基板是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
在本发明中，在为全石英封装的情况下，封装基板为透明材料。因此，调频也可以发生在封装完成之后，利用激光透过透明的石英封装盖直接调节频率，用来调整因为封装应力带来的频率变动。在后面的实施例中不再赘述。
在本发明的实施例中，第一封装基板和/或第二封装基板面对谐振器的一侧为平坦面。
在本发明中，所形成的谐振器的所述压电层在非谐振区域设置有电连接通孔或通孔14，压电层一侧的电极的引出部经由所述电连接通孔延伸到压电层的另一侧从而与另一侧的电极处于压电层的同一侧。这相对于现有技术中两个电 极的引出部分别设置在压电层的两侧具有如下技术效果：减小封装复杂度；此外，这相对于现有技术中一个电极的引出部经由压电层的边缘而到达压电层的另一侧从而与另一电极的引出部同面设置具有如下技术效果：减小/避免了电极跨越压电层时可能存在的电极阻值不稳定的问题。
在本发明中，如图17所示，贯穿的轮廓刻蚀孔18构成间隔通孔，这使得压电层的与封装基板接合的部分(即压电层封装部)与压电层的谐振区域经由该间隔通孔在机械结构上隔离开，即不存在机械上的物理连接。以上方案可以产生如下技术效果：减小了能量的横向泄露，提升了谐振器性能，同时降低外界震动、热量等因素对谐振器的干扰。
图19-图32为根据本发明的另一个示例性实施例的石英谐振器的制作过程的截面示意图。本实施例中石英谐振器的谐振结构利用采用单面反高台的结构，该结构相比于图1-图18所示的实施例具有更好结构稳定性，提高了晶片抗冲击能力。相对应的制造过程有所改变，与图1-图18所示相比，不同之处在于：在步骤1，如图19所示，掩膜20A的开孔部分为谐振区域和通孔区域。后续步骤2-13(如图20-31)与图1-图18所示中的步骤2-17相关工艺步骤一致，键合过程也保持一致。相应的，图19-图32所示实施例同时提供了一种新的封装结构(如图32所示)。
下面参照图19-图32示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图19所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20A，处于正面的掩膜20A被图案化，以形成掩膜开孔22，具体的，用于制备通孔以及谐振区域12的区域被露出。在石英晶圆10的另一侧(例如次面)也设置掩膜20A，其覆盖整个另一侧。
步骤2：湿法刻蚀。如图20所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。在图20中，石英晶圆的谐振区域被刻蚀了一部分。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：去除掩膜20A。如图21所示，上述石英晶圆10刻蚀之后，可以进 行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤4：制作顶电极。如图22所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14，以及可选的，覆盖了通孔刻蚀区14与边框之间的部分区域。
步骤5：接合第一封装基板。如图23所示，将上述石英晶圆10与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准，使得顶电极30恰好位于第一空腔52之内。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。封装基板50也可以采用其他的封装材料。
在本发明的实施例中，第一封装基板50是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图23所示的实施例中，在第一封装基板50与石英晶圆10之间以金属键合的情况下，第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。
步骤6：石英晶圆减薄。如图24所示，利用研磨与抛光工艺对石英晶圆10进行减薄，减薄至谐振区域的剩余厚度比设计值(即上述膜厚d0)富余值在例如1μm之内。
步骤7：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图25所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依据。
步骤8：调节石英薄膜厚度。如图26所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图25和图26操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图57。
步骤9：在图26所示结构的上表面设置通孔穿孔掩膜20B，如图27所示，掩膜20B在对应于通孔刻蚀区14的位置设置有掩膜开孔。
步骤10：例如，利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14处的部分，以贯穿通孔刻蚀区14而形成通孔14，如图28所示。
步骤11：去除掩膜20B。步骤10之后，可以利用湿法刻蚀的方式去除掩膜 20B，以得到如图29所示的结构。
步骤12：制作底电极和电连接部。如图30所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40和电连接部32。底电极40至少由一层金属构成，其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。底电极40与顶电极30、石英压电层共同构成三明治结构。电连接部32与通孔刻蚀区14或通孔14内的金属电连接，其与底电极40设置在石英晶圆10的同一侧且彼此间隔开。
步骤13：测频与调频。如图31所示，测量所得的石英谐振器的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图58。
步骤14：接合第二封装基板。如图32所示，将步骤13中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准，使得底电极40恰好位于第二空腔62之内。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。如图32所示，第二封装基板60设置有导电通孔64，其与顶电极30的电连接部32电连接。
在本发明的实施例中，第二封装基板60是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图32所示的实施例中，在第二封装基板60与石英晶圆10之间以金属键合的情况下，第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。
图33为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图。图33所示结构与图32所示结构的不同仅仅在于导电通孔64的位置的不同，其他结构不再赘述。在图32中，导电通孔64与通孔14对齐，而在图33中，导电通孔64与通孔14错开。这样错位封装有助于提高结构的稳定性，减少因应力、机械变形等问题带来的通孔损伤导致的气密性破坏。与此同时，通孔错位可以一定程度上屏蔽通过通孔传递应力、热量以及电磁信号等干扰带来的噪声。
步骤14之后，可以执行分割操作，以将最终封装形成的石英谐振器形成为 单独的器件。
图34-图53为根据本发明的再一个示例性实施例的石英谐振器的制作过程的截面示意图。本实施例中石英谐振器的谐振结构利用采用双面反高台的结构，该结构相比于图1-图18所示的实施例具有更好结构稳定性，提高了晶片抗冲击能力。图34-图53所示结构可以改善晶片谐振区域的边界，减少声波横向泄露；并且，双面的反高台结构为振动区域提供了空间，可以避免在封装盖上挖槽，有助于晶片的薄型化。
下面参照图34-图53示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图34所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)利用微/纳机电系统光刻的方式制作掩膜20A，处于正面的掩膜20A被图案化，以形成掩膜开孔22，谐振区域12的区域被覆盖。在石英晶圆10的另一侧(例如次面)也设置掩膜20A，其覆盖整个另一侧。
步骤2：湿法刻蚀。如图35所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：对掩膜20A进一步图案化，以露出谐振区域，如图36所示。
步骤4：湿法刻蚀。如图37所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。在图37中，石英晶圆的谐振区域被刻蚀了一部分，同时通孔刻蚀区14被进一步刻蚀，如此，图37中，通孔刻蚀区14的深度大于谐振区域的刻蚀深度。
虽然没有示出，步骤4也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤5：去除掩膜20A。如图38所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤6：制作顶电极。如图39所示，利用金属溅射或者蒸镀的方式在上述 石英晶圆10上制作谐振器顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了通孔刻蚀区14。
步骤7：接合第一封装基板。如图40所示，将上述石英晶圆10与预先刻蚀了第一空腔52的石英晶圆或第一封装基板50对准，使得顶电极30恰好位于第一空腔52之内。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。第一封装基板50也可以采用其他的封装材料。
在本发明的实施例中，第一封装基板50是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图40所示的实施例中，在第一封装基板50与石英晶圆10之间以金属键合的情况下，第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。
步骤8：石英晶圆减薄。如图41所示，利用研磨与抛光工艺对石英晶圆10进行减薄。
步骤9：制作掩膜20D。如图42所示，图41所示结构上利用微/纳机电系统光刻的方式制作掩膜20D，其被图案化以形成掩膜开孔22和露出谐振区域。掩膜20D的材料可以与掩膜20A的一致。
步骤10：湿法刻蚀。如图43所示，以图42中的掩膜20D作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。最终形成双面反高台结构，也在石英晶圆10的另一侧形成了与在一侧的通孔刻蚀区14相对的通孔刻蚀区14’，如图43所示。在图43所示的结构中，通孔刻蚀区14’的刻蚀深度与石英晶圆10的另一侧的谐振区域的刻蚀深度一致，但是，在通孔刻蚀区14’与通孔刻蚀区14之间还留有部分石英压电层。
虽然没有示出，步骤10也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤11：去除掩膜20D。如图44所示，图43所示结构可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20D。
步骤12：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进 行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图45所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依据。
步骤13：调节石英薄膜厚度。如图46所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图45和图46操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图57。
步骤14：制作底电极。如图47所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作谐振器底电极40。底电极40至少由一层金属构成，其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。底电极40与顶电极30、石英压电层共同构成三明治结构。
步骤15：制作掩膜20E。如图48所示，在图47所示结构上利用微/纳机电系统光刻的方式制作掩膜20E，其被图案化以形成掩膜开孔22，该掩膜开孔露出在步骤10中刻蚀出的通孔刻蚀区14’，掩膜20E覆盖了底电极40。掩膜20E的材料可以与掩膜20A的一致。
步骤16：例如，利用干法刻蚀的方式刻蚀石英晶圆10的处于通孔刻蚀区14’处的部分，以贯穿通孔刻蚀区14’，如图49所示。
步骤17：去除掩膜20E。如图50所示，图49所示结构可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20E。
步骤18：制作电连接部32。如图51所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10上制作电连接部32。电连接部32与通孔刻蚀区14内的金属电连接，其与底电极40设置在石英晶圆10的同一侧且彼此间隔开。
步骤19：测频与调频。如图52所示，测量所得的石英谐振器的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图58。
步骤20：接合第二封装基板。如图53所示，将步骤52中的石英晶圆10与预先刻蚀了第二空腔62的石英晶圆或第二封装基板60对准，使得底电极40恰好位于第二空腔62之内。第二封装基板60与石英晶圆10可以利用金属扩散键 合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。如图53所示，第二封装基板60设置有导电通孔64，其与顶电极30的电连接部32电连接。
在本发明的实施例中，第二封装基板60是石英基板的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图52所示的实施例中，在第二封装基板60与石英晶圆10之间以金属键合的情况下，第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。
步骤20之后，可以执行分割操作，以将最终封装形成的石英谐振器形成为单独的器件。
图54-56为根据本发明的另外的示例性实施例的石英谐振器的封装结构的截面示意图。图54-56所示结构与图53所示结构的不同仅仅在于导电通孔64的位置或结构的不同，其他结构不再赘述。
在图54-图56中，导电通孔64与通孔14错开。这样错位封装有助于提高结构的稳定性，减少因应力、机械变形等问题带来的通孔损伤导致的气密性破坏。与此同时，通孔错位可以一定程度上屏蔽通过通孔传递应力、热量以及电磁信号等干扰带来的噪声。图55所示结构与图54所示结构相比，通过改善通孔制作工艺，将通孔的截面形状改为垂直型，提高了通孔的气密性。图56所示结构中，改封装底板为平板，有助于减少了晶片总厚度，并提高谐振区域的机械稳定性。
在本发明的实施例中，采用微/纳机电系统(M/NEMS)光刻技术与湿法刻蚀/干法刻蚀相结合，可以：使得散粒的尺寸小于1mm×1mm；和/或使得散粒的谐振区域的厚度小于40μm或者基于该散粒形成的谐振器的基频在40MHz以上。具体的，基于微/纳机电系统光刻技术，可以获得用于后续刻蚀的、便于形成小于1mm×1mm的散粒尺寸的精细图案，而基于湿法刻蚀/干法刻蚀，则可以获得小于1mm×1mm尺寸的散粒；基于湿法刻蚀/干法刻蚀，可以替代机械掩膜获得小于40μm的石英压电层厚度。
在本发明的实施例中，石英谐振器的顶电极的电极引出部和底电极的电极引出部处于压电层的同一侧，这有利于：减小/避免了电极跨越压电层时可能存在的电极阻值不稳定的技术问题。
在本发明中，电连接通孔或者通孔14的至少一部分为锥形孔，或者更具体 的，电连接通孔的截面为自凸台的上下两侧向中间缩小的形状，这有利于电极分布均一性进而获得稳定的电阻值。
在本发明中，谐振区域是指在形成的石英谐振器中，顶电极、底电极、压电层以及空腔或空隙在压电层的厚度方向上的重合区域。在本发明中，晶圆的谐振区域对应于在晶圆中需要形成为谐振器的谐振区域的区域；压电层的谐振区域对应于在压电层中需要形成为谐振器的谐振区域的区域。在本发明中，非谐振区域是谐振区域之外的部分，对于压电层的非谐振区域，指的是在压电层的谐振区域在水平方向或横向方向外侧的区域。需要指出的是，在本发明中，各个数值范围，除了明确指出不包含端点值之外，除了可以为端点值，还可以为各个数值范围的中值，这些均在本发明的保护范围之内。
如本领域技术人员能够理解的，根据本发明的石英谐振器可以用于形成石英晶振芯片或包括石英谐振器的电子器件。这里的电子器件，可以是例如振荡器等电子元件，也可以例如对讲机、手机等的通信设备，还可以是汽车等应用了石英谐振器的大型产品。
基于以上，本发明提出了如下技术方案：
1、一种石英谐振器，包括：
底电极；
顶电极；和
石英压电层，
其中：
顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧。
2、根据1所述的谐振器，其中：
所述压电层为包括凸台的反高台结构，所述电连接通孔贯穿所述凸台设置。
3、根据2所述的谐振器，其中：
所述压电层为双面反高台结构。
4、根据3所述的谐振器，其中：
所述电连接通孔的截面为自凸台的上下两侧向中间缩小的形状。
5、根据2所述的谐振器，其中：
所述压电层为单面反高台结构。
6、根据1所述的谐振器，其中：
所述压电层为平坦结构。
7、根据6所述的谐振器，其中：
所述谐振器为悬臂结构。
8、根据1所述的谐振器，其中：
所述电连接通孔的至少一部分为锥形孔。
9、根据1所述的谐振器，其中：
所述压电层的尺寸小于1mm×1mm；和/或
所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
10、根据1-9中任一项所述的谐振器，还包括：
封装结构。
11、根据10所述的谐振器，其中：
所述封装结构包括第一基板和第二基板，所述压电层设置在第一基板与第二基板之间；
所述封装结构包括接合密封层，所述接合密封层包括压电层封装部，所述压电层封装部为压电层的一部分，且所述压电层封装部分别与第一基板和第二基板接合。
12、根据11所述的谐振器，其中：
第一基板和第二基板均为石英基板。
13、根据11所述的谐振器，其中：
第一基板和/或第二基板面对所述压电层的一侧设置有空腔，所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
14、根据13所述的谐振器，其中：
第一基板和第二基板均为石英基板，且所述空腔的截面为直角梯形截面。
15、根据11所述的谐振器，其中：
第一基板和/或第二基板面对谐振器的一侧为平坦面；
所述谐振器的压电层面对所述平坦面的一侧为反高台结构。
16、根据11所述的谐振器，其中：
所述压电层还包括间隔通孔；
所述压电层为平坦结构，所述压电层封装部与压电层的谐振区域经由所述间隔通孔在机械结构上隔离开。
17、根据11所述的谐振器，其中：
所述压电层包括在谐振区域之外的凸台，所述电连接通孔贯穿所述凸台，且所述凸台的在所述电连接通孔外侧的部分包括所述压电层封装部。
18、根据11所述的谐振器，其中：
处于压电层的另一侧的第一基板和第二基板中的基板设置有基板贯穿导电孔；
所述基板贯穿导电孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧的部分电连接。
19、根据18所述的谐振器，其中：
所述基板贯穿导电孔与所述电连接通孔在水平方向上错开；或者
所述基板贯穿导电孔与所述电连接通孔在厚度方向上对齐。
20、根据18所述的谐振器，其中：
所述基板贯穿导电孔为直孔、锥形孔或者上下两侧向中间缩小的孔。
21、一种电子器件，包括根据1-20中任一项所述的石英谐振器。
22、一种石英谐振器的制造方法，包括步骤：
提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
刻蚀：至少利用微/纳机电系统光刻技术，在石英晶圆的一侧的预定位置，在石英晶圆的非谐振区域形成多个通孔刻蚀区；
设置第一电极层：对于每个石英谐振器，顶电极和底电极中的一个电极为第一电极，顶电极和底电极中的另一个电极为第二电极，在石英晶圆的一侧设置包括了第一电极的第一电极层，第一电极层覆盖对应的通孔刻蚀区；
贯穿：至少利用微/纳机电系统光刻技术，在石英晶圆的另一侧的与所述通孔刻蚀区对应的位置，刻蚀贯穿所述通孔刻蚀区以露出所述第一电极层；
设置电连接部：在石英晶圆的另一侧设置电连接部，所述电连接部经由贯穿的通孔刻蚀区电连接到处于石英晶圆的一侧的所述第一电极，所述电连接部 与设置在石英晶圆的另一侧的第二电极的电极引出部同侧间隔开设置；和
分割：在上述步骤之后，至少将石英晶圆切割或者裂片，以形成石英谐振器。
23、根据22所述的方法，其中：
所述刻蚀步骤包括：
设置图案化的第一掩膜：在石英晶圆的一侧和另一侧均设置第一掩膜，以及利用微/纳机电系统光刻技术对在石英晶圆的所述一侧的第一掩膜图案化，图案化的第一掩膜包括多个第一掩膜孔；
形成通孔刻蚀区：在石英晶圆的一侧在所述第一掩膜孔对应的位置形成通孔刻蚀区；
移除石英晶圆两侧的第一掩膜。
24、根据22所述的方法，其中，所述贯穿步骤包括：
设置图案化的第二掩膜：在压电层的另一侧设置第二掩膜，对所述第二掩膜图案化以露出所述压电层的另一侧对应于所述通孔刻蚀区的部分；
贯穿通孔刻蚀区：对于所述压电层的另一侧对应于所述通孔刻蚀区的部分刻蚀以贯穿通孔刻蚀区；
移除第二掩膜。
25、根据22所述的方法，其中：
设置电连接部与设置包括第二电极的第二电极层同步。
26、根据22所述的方法，其中：
在设置第一电极层之后贯穿之前，还包括步骤：
第一次减薄：在石英晶圆的另一侧对石英晶圆执行一次减薄，一次减薄后的石英晶圆的另一侧与所述通孔刻蚀区之间在厚度方向上存在的距离在1μm以内；
测量或者二次减薄：利用光学方法在石英晶圆的另一侧测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度。
27、根据26所述的方法，其中：
所述刻蚀步骤还包括在石英晶圆的所述一侧形成石英谐振器的轮廓刻蚀区；
所述方法还包括步骤：在刻蚀贯穿所述通孔刻蚀区之后，刻蚀贯穿所述轮廓刻蚀区。
28、根据23所述的方法，其中：
所述方法还包括步骤：
接合第一封装基板：将第一封装基板与设置了第一电极层的石英晶圆在石英晶圆的所述一侧接合，所述第一电极与所述第一封装基板面对；和
接合第二封装基板：将第二封装基板与设置了第二电极层的石英晶圆在石英晶圆的所述另一侧接合以形成复合结构，所述第二电极与所述第二封装基板面对，所述第二封装基板设置有多个基板贯穿导电孔，所述多个基板贯穿导电孔分别与对应的电连接部电连接，且
其中所述分割步骤包括：分割所述复合结构以形成单独的石英谐振器。
29、根据28所述的方法，其中：
所述第一封装基板和/或所述第二封装基板为石英基板。
30、根据28或29所述的方法，其中：
设置图案化的第一掩膜的步骤中，图案化的第一掩膜覆盖石英晶圆的谐振区域；
设置图案化的第二掩膜的步骤中，图案化的第二掩膜覆盖石英晶圆的谐振区域；
在接合第一封装基板的步骤中，将预先设置有第一空腔的第一封装基板与设置了第一电极层的石英晶圆接合，所述第一电极层与所述第一空腔面对；
在接合第二封装基板的步骤中，将预先设置有第二空腔的第二封装基板与设置了第二电极层的石英晶圆接合，所述第二电极层与所述第二空腔面对。
31、根据30所述的方法，其中：
设置图案化的第一掩膜的步骤中，图案化的第一掩膜还包括第二掩膜孔；
在刻蚀步骤中，基于湿法刻蚀在石英晶圆的一侧在所述第二掩膜孔对应的位置形成多个轮廓刻蚀区；且
所述方法还包括步骤：在谐振区域的厚度达到预定厚度的石英晶圆的另一侧设置第三掩膜，对所述第三掩膜图案化以形成对应于所述轮廓刻蚀区的第三掩膜孔；贯穿轮廓刻蚀区：在所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分执行干法刻蚀以贯穿轮廓刻蚀区；和移除第三掩膜；且
在第一封装基板和第二封装基板均与石英晶圆在所述轮廓刻蚀区外侧的部分接合。
32、根据30所述的方法，其中：
设置图案化的第一掩膜的步骤中，图案化的第一掩膜还包括第二掩膜孔；
在刻蚀步骤中，基于湿法刻蚀在石英晶圆的一侧在所述第二掩膜孔对应的位置形成多个轮廓刻蚀区；
在设置图案化的第二掩膜的步骤中，对所述第二掩膜图案化以露出所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分；
在贯穿通孔刻蚀区的同时，在所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分执行干法刻蚀以贯穿轮廓刻蚀区；且
在第一封装基板和第二封装基板均与石英晶圆在所述轮廓刻蚀区外侧的部分接合。
33、根据28或29所述的方法，其中：
设置图案化的第一掩膜的步骤中，图案化的第一掩膜露出石英晶圆的谐振区域，在接合第一封装基板的步骤中，将预先设置有第一空腔的第一封装基板或者包括第一平坦面的第一封装基板与设置了第一电极层的石英晶圆接合，所述第一电极层与所述第一空腔或第一平坦面面对；和/或
设置图案化的第二掩膜的步骤中，图案化的第二掩膜露出石英晶圆的谐振区域，在接合第二封装基板的步骤中，将预先设置有第二空腔的第二封装基板或者包括第二平坦面的第二封装基板与设置了第二电极层的石英晶圆接合，所述第二电极层与所述第二空腔或第二平坦面面对。
34、根据22所述的方法，还包括步骤：
测量或者调频：测量设置了电连接部和第二电极的谐振区域的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
35、根据22所述的方法，其中：
所述刻蚀步骤中采用湿法刻蚀以形成多个通孔刻蚀区；和/或
所述贯穿步骤中采用干法刻蚀以刻蚀贯穿所述通孔刻蚀区。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化， 本发明的范围由所附权利要求及其等同物限定。

Claims (35)

  1. 一种石英谐振器，包括：
    底电极；
    顶电极；和
    石英压电层，
    其中：
    顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
    所述压电层在非谐振区域设置有电连接通孔，所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧从而与所述第二电极处于所述压电层的同一侧。
  2. 根据权利要求1所述的谐振器，其中：
    所述压电层为包括凸台的反高台结构，所述电连接通孔贯穿所述凸台设置。
  3. 根据权利要求2所述的谐振器，其中：
    所述压电层为双面反高台结构。
  4. 根据权利要求3所述的谐振器，其中：
    所述电连接通孔的截面为自凸台的上下两侧向中间缩小的形状。
  5. 根据权利要求2所述的谐振器，其中：
    所述压电层为单面反高台结构。
  6. 根据权利要求1所述的谐振器，其中：
    所述压电层为平坦结构。
  7. 根据权利要求6所述的谐振器，其中：
    所述谐振器为悬臂结构。
  8. 根据权利要求1所述的谐振器，其中：
    所述电连接通孔的至少一部分为锥形孔。
  9. 根据权利要求1所述的谐振器，其中：
    所述压电层的尺寸小于1mm×1mm；和/或
    所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
  10. 根据权利要求1-9中任一项所述的谐振器，还包括：
    封装结构。
  11. 根据权利要求10所述的谐振器，其中：
    所述封装结构包括第一基板和第二基板，所述压电层设置在第一基板与第二基板之间；
    所述封装结构包括接合密封层，所述接合密封层包括压电层封装部，所述压电层封装部为压电层的一部分，且所述压电层封装部分别与第一基板和第二基板接合。
  12. 根据权利要求11所述的谐振器，其中：
    第一基板和第二基板均为石英基板。
  13. 根据权利要求11所述的谐振器，其中：
    第一基板和/或第二基板面对所述压电层的一侧设置有空腔，所述石英谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
  14. 根据权利要求13所述的谐振器，其中：
    第一基板和第二基板均为石英基板，且所述空腔的截面为直角梯形截面。
  15. 根据权利要求11所述的谐振器，其中：
    第一基板和/或第二基板面对谐振器的一侧为平坦面；
    所述谐振器的压电层面对所述平坦面的一侧为反高台结构。
  16. 根据权利要求11所述的谐振器，其中：
    所述压电层还包括间隔通孔；
    所述压电层为平坦结构，所述压电层封装部与压电层的谐振区域经由所述间隔通孔在机械结构上隔离开。
  17. 根据权利要求11所述的谐振器，其中：
    所述压电层包括在谐振区域之外的凸台，所述电连接通孔贯穿所述凸台，且所述凸台的在所述电连接通孔外侧的部分包括所述压电层封装部。
  18. 根据权利要求11所述的谐振器，其中：
    处于压电层的另一侧的第一基板和第二基板中的基板设置有基板贯 穿导电孔；
    所述基板贯穿导电孔与所述第一电极的电极引出部经由所述电连接通孔延伸到所述压电层的另一侧的部分电连接。
  19. 根据权利要求18所述的谐振器，其中：
    所述基板贯穿导电孔与所述电连接通孔在水平方向上错开；或者
    所述基板贯穿导电孔与所述电连接通孔在厚度方向上对齐。
  20. 根据权利要求18所述的谐振器，其中：
    所述基板贯穿导电孔为直孔、锥形孔或者上下两侧向中间缩小的孔。
  21. 一种电子器件，包括根据权利要求1-20中任一项所述的石英谐振器。
  22. 一种石英谐振器的制造方法，包括步骤：
    提供石英晶圆，所述石英晶圆包括用于形成多个石英谐振器的谐振区域；
    刻蚀：至少利用微/纳机电系统光刻技术，在石英晶圆的一侧的预定位置，在石英晶圆的非谐振区域形成多个通孔刻蚀区；
    设置第一电极层：对于每个石英谐振器，顶电极和底电极中的一个电极为第一电极，顶电极和底电极中的另一个电极为第二电极，在石英晶圆的一侧设置包括了第一电极的第一电极层，第一电极层覆盖对应的通孔刻蚀区；
    贯穿：至少利用微/纳机电系统光刻技术，在石英晶圆的另一侧的与所述通孔刻蚀区对应的位置，刻蚀贯穿所述通孔刻蚀区以露出所述第一电极层；
    设置电连接部：在石英晶圆的另一侧设置电连接部，所述电连接部经由贯穿的通孔刻蚀区电连接到处于石英晶圆的一侧的所述第一电极，所述电连接部与设置在石英晶圆的另一侧的第二电极的电极引出部同侧间隔开设置；和
    分割：在上述步骤之后，至少将石英晶圆切割或者裂片，以形成石英谐振器。
  23. 根据权利要求22所述的方法，其中：
    所述刻蚀步骤包括：
    设置图案化的第一掩膜：在石英晶圆的一侧和另一侧均设置第一掩膜，以及利用微/纳机电系统光刻技术对在石英晶圆的所述一侧的第一掩膜图案化，图案化的第一掩膜包括多个第一掩膜孔；
    形成通孔刻蚀区：在石英晶圆的一侧在所述第一掩膜孔对应的位置形成通孔刻蚀区；
    移除石英晶圆两侧的第一掩膜。
  24. 根据权利要求22所述的方法，其中，所述贯穿步骤包括：
    设置图案化的第二掩膜：在压电层的另一侧设置第二掩膜，对所述第二掩膜图案化以露出所述压电层的另一侧对应于所述通孔刻蚀区的部分；
    贯穿通孔刻蚀区：对于所述压电层的另一侧对应于所述通孔刻蚀区的部分刻蚀以贯穿通孔刻蚀区；
    移除第二掩膜。
  25. 根据权利要求22所述的方法，其中：
    设置电连接部与设置包括第二电极的第二电极层同步。
  26. 根据权利要求22所述的方法，其中：
    在设置第一电极层之后贯穿之前，还包括步骤：
    第一次减薄：在石英晶圆的另一侧对石英晶圆执行一次减薄，一次减薄后的石英晶圆的另一侧与所述通孔刻蚀区之间在厚度方向上存在的距离在1μm以内；
    测量或者二次减薄：利用光学方法在石英晶圆的另一侧测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度。
  27. 根据权利要求26所述的方法，其中：
    所述刻蚀步骤还包括在石英晶圆的所述一侧形成石英谐振器的轮廓刻蚀区；
    所述方法还包括步骤：在刻蚀贯穿所述通孔刻蚀区之后，刻蚀贯穿所述轮廓刻蚀区。
  28. 根据权利要求23所述的方法，其中：
    所述方法还包括步骤：
    接合第一封装基板：将第一封装基板与设置了第一电极层的石英晶圆在石英晶圆的所述一侧接合，所述第一电极与所述第一封装基板面对；和
    接合第二封装基板：将第二封装基板与设置了第二电极层的石英晶圆在石英晶圆的所述另一侧接合以形成复合结构，所述第二电极与所述第二封装基板面对，所述第二封装基板设置有多个基板贯穿导电孔，所述多个基板贯穿导电孔分别与对应的电连接部电连接，且
    其中所述分割步骤包括：分割所述复合结构以形成单独的石英谐振器。
  29. 根据权利要求28所述的方法，其中：
    所述第一封装基板和/或所述第二封装基板为石英基板。
  30. 根据权利要求28或29所述的方法，其中：
    设置图案化的第一掩膜的步骤中，图案化的第一掩膜覆盖石英晶圆的谐振区域；
    设置图案化的第二掩膜的步骤中，图案化的第二掩膜覆盖石英晶圆的谐振区域；
    在接合第一封装基板的步骤中，将预先设置有第一空腔的第一封装基板与设置了第一电极层的石英晶圆接合，所述第一电极层与所述第一空腔面对；
    在接合第二封装基板的步骤中，将预先设置有第二空腔的第二封装基板与设置了第二电极层的石英晶圆接合，所述第二电极层与所述第二空腔面对。
  31. 根据权利要求30所述的方法，其中：
    设置图案化的第一掩膜的步骤中，图案化的第一掩膜还包括第二掩膜孔；
    在刻蚀步骤中，基于湿法刻蚀在石英晶圆的一侧在所述第二掩膜孔对应的位置形成多个轮廓刻蚀区；且
    所述方法还包括步骤：在谐振区域的厚度达到预定厚度的石英晶圆的另一侧设置第三掩膜，对所述第三掩膜图案化以形成对应于所述轮廓刻蚀区的第三掩膜孔；贯穿轮廓刻蚀区：在所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分执行干法刻蚀以贯穿轮廓刻蚀区；和移除第三掩膜；且
    在第一封装基板和第二封装基板均与石英晶圆在所述轮廓刻蚀区外 侧的部分接合。
  32. 根据权利要求30所述的方法，其中：
    设置图案化的第一掩膜的步骤中，图案化的第一掩膜还包括第二掩膜孔；
    在刻蚀步骤中，基于湿法刻蚀在石英晶圆的一侧在所述第二掩膜孔对应的位置形成多个轮廓刻蚀区；
    在设置图案化的第二掩膜的步骤中，对所述第二掩膜图案化以露出所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分；
    在贯穿通孔刻蚀区的同时，在所述石英晶圆的另一侧对应于所述轮廓刻蚀区的部分执行干法刻蚀以贯穿轮廓刻蚀区；且
    在第一封装基板和第二封装基板均与石英晶圆在所述轮廓刻蚀区外侧的部分接合。
  33. 根据权利要求28或29所述的方法，其中：
    设置图案化的第一掩膜的步骤中，图案化的第一掩膜露出石英晶圆的谐振区域，在接合第一封装基板的步骤中，将预先设置有第一空腔的第一封装基板或者包括第一平坦面的第一封装基板与设置了第一电极层的石英晶圆接合，所述第一电极层与所述第一空腔或第一平坦面面对；和/或
    设置图案化的第二掩膜的步骤中，图案化的第二掩膜露出石英晶圆的谐振区域，在接合第二封装基板的步骤中，将预先设置有第二空腔的第二封装基板或者包括第二平坦面的第二封装基板与设置了第二电极层的石英晶圆接合，所述第二电极层与所述第二空腔或第二平坦面面对。
  34. 根据权利要求22所述的方法，还包括步骤：
    测量或者调频：测量设置了电连接部和第二电极的谐振区域的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
  35. 根据权利要求22所述的方法，其中：
    所述刻蚀步骤中采用湿法刻蚀以形成多个通孔刻蚀区；和/或
    所述贯穿步骤中采用干法刻蚀以刻蚀贯穿所述通孔刻蚀区。
PCT/CN2023/110648 2022-08-05 2023-08-02 电极引出部处于同侧的石英谐振器及其制造方法、电子器件 WO2024027734A1 (zh)

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