WO2024027735A1 - 封装基底的端面设置外连接部石英谐振器及其制造方法、电子器件 - Google Patents

封装基底的端面设置外连接部石英谐振器及其制造方法、电子器件 Download PDF

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Publication number
WO2024027735A1
WO2024027735A1 PCT/CN2023/110649 CN2023110649W WO2024027735A1 WO 2024027735 A1 WO2024027735 A1 WO 2024027735A1 CN 2023110649 W CN2023110649 W CN 2023110649W WO 2024027735 A1 WO2024027735 A1 WO 2024027735A1
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Prior art keywords
packaging substrate
electrode
quartz
layer
resonator
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PCT/CN2023/110649
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English (en)
French (fr)
Inventor
庞慰
张孟伦
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天津大学
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Publication of WO2024027735A1 publication Critical patent/WO2024027735A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/125—Driving means, e.g. electrodes, coils
    • H03H9/13—Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/19—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator consisting of quartz

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a quartz resonator with an external connection portion provided on the end surface of a packaging substrate, a manufacturing method thereof, and an electronic device.
  • the fundamental frequency of the chip is mainly determined by the thickness of the resonance area of the chip.
  • Wafer-level manufacturing can significantly reduce the manufacturing cost of a single resonator and achieve consistent quality control between resonators; generally speaking, the larger the wafer size, the lower the manufacturing cost of a single resonator.
  • precise control of the quartz thickness at each location is a huge challenge, which directly leads to changes in the frequency of the wafers on the entire wafer. Accuracy and consistency cannot be guaranteed. Therefore, there are great challenges in wafer-level chip frequency modulation.
  • the current methods adopted by existing technologies mainly focus on using grinding technology with ultra-high-precision film thickness monitoring systems to prepare quartz films with a thickness uniformity within a few nanometers. This frequency control and regulation technology has significant impact on materials and manufacturing processes.
  • the technology puts forward extremely high requirements, and the larger the wafer area, the higher the difficulty of manufacturing, which hinders the creation of low-cost, high-efficiency manufacturing solutions.
  • one of the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode extends through the edge of the piezoelectric layer to a position on the same side as the other electrode lead-out portion, and the electrodes are arranged across the piezoelectric layer.
  • the lead-out method is prone to the problem of unstable electrode connection resistance (too high or even disconnection of the electrical connection).
  • the boundary conditions of the resonator can be optimized and the lateral leakage of acoustic waves can be reduced, thereby further improving the performance of the resonator.
  • the present invention is proposed to alleviate or solve at least one aspect of the above-mentioned problems in the prior art.
  • a quartz resonator including:
  • the bottom electrode and the top electrode, one of the top electrode and the bottom electrode is a first electrode, the other is a second electrode, the first electrode is on one side of the piezoelectric layer, and the second electrode is on one side of the piezoelectric layer.
  • the first packaging substrate and the second packaging substrate are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second electrode.
  • the electrode lead-out end of the first electrode includes a first external connection portion extending at least through the end surface of the second packaging substrate to a side of the second package substrate away from the second electrode, or the electrode lead-out end of the second electrode includes at least one end through the first package substrate.
  • the end surface of the packaging substrate extends to the second external connection portion on a side of the first packaging substrate away from the first electrode.
  • a manufacturing method of a quartz resonator including the steps:
  • Forming a resonant structure on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, on one side of the quartz piezoelectric layer and on the other side of the quartz piezoelectric layer.
  • a first electrode layer including a first electrode and a second electrode layer including a second electrode are respectively provided on one side;
  • first packaging substrate and a second packaging substrate Provide a first packaging substrate and a second packaging substrate: the first packaging substrate and the second packaging substrate Plates are respectively disposed on both sides of the quartz piezoelectric layer to form a composite structure, the first packaging substrate is opposite to the first electrode layer, and the second packaging substrate is opposite to the second electrode layer; and
  • Segmentation at least cutting or splitting the composite structure to form a plurality of mechanically separated structural particles
  • Providing an external connection part for the structural particles including the step of: making the electrode lead-out end of the first electrode of each structural particle include a first external connection part, the first external connection part extending to at least via the end surface of the second packaging substrate.
  • the side of the second packaging substrate away from the second electrode, or the electrode lead-out end of the second electrode of each structural particle includes a second external connection portion, which is at least via the end surface of the first packaging substrate Extending to a side of the first package substrate away from the first electrode.
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned quartz resonator.
  • FIG. 1-11 are schematic cross-sectional views of the manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • FIGS. 12-30 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention.
  • Figure 31 is a schematic cross-sectional view of a quartz resonator according to an exemplary embodiment of the present invention.
  • Figure 32 is a schematic flow chart of fundamental frequency adjustment in the resonance area of a quartz wafer
  • Figure 33 is a schematic flowchart of resonant frequency adjustment of a quartz resonator.
  • the present invention proposes a quartz wafer manufacturing process based on micro/nano electromechanical systems (M/NEMS) photolithography technology.
  • M/NEMS micro/nano electromechanical systems
  • This technology can be used to make small-sized, frequency-accurate quartz resonators.
  • a wafer-level frequency/thickness monitoring and control method is adopted, which reduces the requirements for the uniformity of quartz wafer thickness processing and reduces the processing difficulty.
  • This solution is universally applicable to the manufacturing of quartz wafers in different frequency bands, and is not limited by the area of the quartz wafer, so it has obvious advantages.
  • the present invention's wafer manufacturing solution based on micro-nano electromechanical systems makes full use of the advantages of MEMS photolithography technology and wafer-level process manufacturing methods, and uses the method of wet etching wafer contours to get rid of the impact of cutting technology on wafer size. Limitation, can realize the processing of smaller size wafers of 1210, 1008 and below.
  • wafer processing solutions for wafer manufacturing can improve dimensional processing accuracy and improve wafer processing efficiency.
  • the present invention proposes a wafer-level wafer manufacturing and frequency control process, which eliminates the need for ultra-high-precision grinding technology for quartz wafers, and at the same time greatly reduces the difficulty of frequency modulation, making frequency modulation completely unconstrained by wafer area expansion.
  • this solution meets the requirements for miniaturized manufacturing of wafers from low frequency to high frequency (30-300MHz) and ultra-high frequency (300MHz-3GHz), and is of great significance to promoting the development of the quartz wafer field.
  • Top electrode the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the electrical connection part of the top electrode The material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys.
  • the top electrode and its electrical connections, the bottom electrode and its electrical connections may be the same metal material.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • the external connection part, the top electrode and its electrical connection part, the bottom electrode and its electrical connection part may be made of the same metal material.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or composites of the above metals or their alloys, etc.
  • Second package substrate conductive via hole Second package substrate conductive via hole.
  • 72A, 72B Metal bonding layer, which can be gold-gold, gold-tin, copper-tin bonding, etc.
  • 74A, 74B Filling metal layer.
  • the filling metal layer, the external connection part, the top electrode and its electrical connection part, the bottom electrode and its electrical connection part may be the same metal material.
  • each part is described using a feasible material as an example, but is not limited thereto.
  • FIG. 1-11 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to an exemplary embodiment of the present invention.
  • the following is an example of the manufacturing process of a quartz resonator with reference to Figures 1-11, which includes the following steps:
  • Step 1 Make mask 20A.
  • a mask 20A is fabricated on one side (eg, front side) and the other side (eg, subside) of a quartz wafer (eg, 1-8 inches in diameter, 100 ⁇ m to 1 mm thick), using micro/nano
  • the mask 20A on both sides is patterned by electromechanical photolithography to expose the resonance area of the quartz wafer.
  • the patterned mask 20A is in the form of a frame mask.
  • the mask can be a metal mask, such as chrome gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal;
  • the mask can be SU-8 glue, or other photoresists suitable for dry etching.
  • the material of the mask 20A can also be applied to other embodiments, which will not be described again below.
  • FIGS. 1 to 11 only the area corresponding to a single quartz resonator on the wafer is shown. As can be understood, there are multiple quartz resonators on the quartz wafer 10 as shown in FIGS. 1 to 10 Area. In other embodiments, similar understanding should be made, which will not be described again.
  • Step 2 Wet etching.
  • the mask 20A is used as a barrier layer, and an etching liquid (such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid) is used to etch the quartz wafer.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • d 1 is equal to the quartz film thickness d 0 corresponding to the set frequency of the quartz resonator.
  • the quartz wafer forms a double-sided reverse platform structure.
  • the counter-mountain structure can also be provided only on one side.
  • the substrate bonded to the quartz wafer needs to have a cavity.
  • FIG. 31 shows a resonator structure according to an exemplary embodiment of the present invention, in which cavities 54 and 64 are respectively provided on the sides of the first packaging substrate 50 and the second packaging substrate 60 facing the piezoelectric layer.
  • the projection of the resonant region of the resonator in the thickness direction falls into the cavity.
  • both sides of the piezoelectric layer are flat surfaces.
  • one or both sides of the piezoelectric layer can also be a reverse mesa structure, or, in Figure 31, In the case where one side of the piezoelectric layer has a reverse mesa structure, the corresponding side of the substrate facing it does not need to be provided with a cavity, and these are all within the scope of the present invention.
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in FIG. 3 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 4 Make the top electrode.
  • the top electrode 30 of the resonator is formed on one side of the quartz wafer 10 by metal sputtering or evaporation.
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Top electrode 30 covers resonant region 12 .
  • Step 5 Wafer-level film thickness measurement.
  • the optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference between it and the design value d0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 6 Adjust quartz film thickness. As shown in Figure 6, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 5 and Figure 6 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 32.
  • Step 7 Make the bottom electrode.
  • a resonator bottom electrode 40 is formed on the other side of the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, which The metals in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 8 Join the first package substrate.
  • the quartz wafer 10 on which the bottom electrode 40 is fabricated is aligned with the quartz wafer or the first packaging substrate 50 .
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the first packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the first packaging substrate 50 is provided with a first packaging substrate conductive through hole 52 , which is electrically connected to the electrode lead-out portion of the top electrode 30 .
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • a filling metal layer 74A is provided on the outside of the metal bonding layer 72A and is spaced apart from the metal bonding layer 72A.
  • the filling metal layer 74A only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • metal bonding layer 72A is spaced apart from fill metal layer 74A by a distance in the range of 2-100 microns.
  • the quartz wafer 10 and the first packaging substrate 50 may be bonded after the above-mentioned step 6 and before step 7.
  • Step 9 Frequency measurement and frequency modulation.
  • the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the quartz resonator.
  • the resonant frequency of the resonator As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 33.
  • Step 10 Bond the second package substrate.
  • the quartz wafer 10 after frequency measurement or frequency modulation is aligned with the quartz wafer or the second packaging substrate 60 .
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second packaging substrate 60 may also use other packaging materials.
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it may be a thick A quartz wafer with a thickness of 20-300 ⁇ m, which is exactly the same as the wafer size specification of the quartz wafer 10.
  • the second packaging substrate 60 is provided with a second packaging substrate conductive through hole 62 that is electrically connected to the electrode lead-out portion of the bottom electrode 40 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • a filling metal layer 74B is provided on the outside of the metal bonding layer 72B and is spaced apart from the metal bonding layer 72B.
  • the filling metal layer 74B only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • metal bonding layer 72B is spaced apart from fill metal layer 74B by a distance in the range of 2-200 microns.
  • the first packaging substrate 50 and the second packaging substrate 60 are respectively disposed on both sides of the quartz wafer to form a composite structure.
  • the composite structure is a sandwich structure including the first packaging substrate 50 , the piezoelectric layer, and the second packaging substrate 60 .
  • Step 11 Divide or slice the composite structure. Multiple structures in Figure 10 that are connected together are formed into individual structural particles, and the divided individual structural particles are as shown in Figure 10 .
  • Step 12 Provide external connection portion 34.
  • the electrode lead-out end of the top electrode 30 of each structural shot includes an external connection portion 34 that extends at least through the end surfaces of the first packaging substrate 50 and the second packaging substrate 60 to away from the second packaging substrate 60 one side of the bottom electrode.
  • the external connection portion 34 may be formed by metal sputtering or evaporation.
  • the electrode lead-out end of the bottom electrode may also include the external connection portion, so that it can extend at least through the end surfaces of the second packaging substrate 60 and the first packaging substrate 50 to an end of the first packaging substrate 50 away from the top electrode 30 side.
  • the external connection portion 34 extends through the end surfaces of the first packaging substrate 50 and the second packaging substrate 60 .
  • the electrode lead-out portion of the electrode is led out from between the packaging substrate and the quartz piezoelectric layer, there may be a situation where only the end surface of one of the two packaging substrates is covered. This is It is also within the protection scope of the present invention.
  • the external connection portion 34 is connected to the filling metal layer 74A and the filling metal layer 74B. Because of the presence of the filling metal layer, it is beneficial to keep the end surface of the composite structure where the external connection portion 34 needs to be placed flat after dicing or dividing, thereby facilitating the flattening or flattening of the external connection portion 34 and the electrical connection. connection stability.
  • the packaging substrate may be a quartz substrate or a substrate made of other materials, such as silicon, glass, sapphire, etc. No further details will be given in the following embodiments.
  • the packaging substrate is a transparent material. Therefore, frequency modulation can also occur after the packaging is completed, using laser to directly adjust the frequency through the transparent quartz packaging cover to adjust the frequency changes caused by packaging stress. No further details will be given in the following embodiments.
  • the ends of the electrode lead-out portions of the bottom electrode and the top electrode are simultaneously provided on the same side of one package substrate.
  • this has the following technical effect: reducing the packaging complexity; in addition, compared with the prior art in which the lead-out part of one electrode is arranged on both sides of the piezoelectric layer, The edge of the layer reaches the other side of the piezoelectric layer and is arranged in the same plane as the lead-out part of the other electrode, which has the following technical effect: reducing/avoiding the problem of unstable electrode resistance that may exist when the electrode crosses the piezoelectric layer.
  • the resonant structure of the quartz resonator adopts an inverted platform structure, which has better structural stability and improves the impact resistance of the chip compared to the embodiment in which the piezoelectric layer is a flat structure.
  • FIGS. 12 to 30 are schematic cross-sectional views of a manufacturing process of a quartz resonator according to another exemplary embodiment of the present invention. This embodiment can be adapted to wafer fabrication using quartz wafers of any size gauge.
  • Step 1 Make mask 20A.
  • a mask 20A is fabricated on one side (eg, front side) and the other side (eg, subside) of a quartz wafer (eg, 1-8 inches in diameter, 100 ⁇ m to 1 mm in thickness), using micro/nano
  • the electromechanical system photolithography method causes the mask 20A on one side to be patterned to expose the resonant area of the quartz wafer, while the first mask 20A on the other side is not patterned.
  • the patterned mask 20A is in the form of a frame mask.
  • the mask can be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or other Inert metal;
  • the mask can be SU-8 glue, or other photoresists suitable for dry etching.
  • the material of the mask 20A can also be applied to other embodiments, which will not be described again below.
  • Step 2 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • step 2 can also be replaced by dry etching, or wet etching can be combined with dry etching.
  • Step 3 Remove mask 20A. As shown in FIG. 14 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20A can be removed by wet etching.
  • Step 4 Make the top electrode.
  • metal sputtering or evaporation is used to fabricate the top electrode 30 of the resonator on one side of the quartz wafer 10 .
  • the top electrode 30 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 may be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Top electrode 30 covers resonant region 12 .
  • Step 5 Join the first package substrate.
  • the quartz wafer 10 on which the top electrode 30 is fabricated is aligned with the quartz wafer or the first packaging substrate 50 .
  • the first packaging substrate 50 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the first packaging substrate 50 may also use other packaging materials.
  • the first packaging substrate 50 when the first packaging substrate 50 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the first packaging substrate 50 is provided with a conductive blind hole 52′ for the first packaging substrate conductive through hole 52, which is electrically connected to the electrode lead-out portion of the top electrode 30.
  • a metal bonding layer is also provided at the joint between the first packaging substrate 50 and the quartz wafer 10 72A.
  • a filling metal layer 74A is provided on the outside of the metal bonding layer 72A and is spaced apart from the metal bonding layer 72A.
  • the filling metal layer 74A only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • Step 6 Perform double-sided thinning on the structure in Figure 16.
  • the first packaging substrate 50 and the quartz wafer 10 are thinned, for example, to less than 100 ⁇ m using a grinding and polishing process.
  • thinning may not be performed; if the thickness of the first packaging substrate 50 is also appropriate, thinning may not be performed.
  • Step 7 Make mask 20B.
  • a mask 20B is made on the other side of the quartz wafer and the lower side of the first packaging substrate 50, and micro/nano electromechanical system photolithography is used to make the mask on this side
  • the film 20B is patterned to expose the resonant region of the quartz wafer, while the mask 20B on the underside of the first package substrate 50 is not patterned.
  • the patterned mask 20B is in the form of a frame mask.
  • the mask 20B may be a metal mask, such as chromium gold (a layer of gold on the top and a layer of chromium on the bottom), or Other inert metals; for subsequent use of dry etching (for example, step 2 of the embodiment shown in Figures 12 to 30), the mask 20B can be SU-8 glue, or other photoresists.
  • Step 8 Wet etching.
  • an etching liquid such as an HF etching liquid with a temperature higher than 20°C and a concentration higher than 5%, or a HF/NH4F mixed etching liquid
  • the other side of 10 is etched.
  • step 8 may be replaced by dry etching, or wet etching may be combined with dry etching.
  • Step 9 Remove mask 20B. As shown in FIG. 20 , after the quartz wafer 10 is etched, it can be cleaned and dried, and then the mask 20B can be removed by wet etching.
  • Step 10 Wafer-level film thickness measurement.
  • the optical method was used to measure the thickness of quartz in the resonance area after grinding. The measurement point must be selected in the area with the top electrode on the other side of the quartz film.
  • the thickness of the quartz film in the resonance area of each wafer is measured using the method of optically measuring the thickness of the transparent film, and the difference from the design value d 0 is obtained to provide a basis for the next step of adjusting the film thickness of each wafer. .
  • Step 11 Adjust quartz film thickness. As shown in Figure 22, the quartz plate in the resonance area of the wafer is etched twice using ion beam etching or wet etching. Repeat the operations in Figure 21 and Figure 22 to adjust the thickness of the wafer multiple times to finally obtain a precise thickness. This process can be seen in Figure 32.
  • Step 12 Make the bottom electrode.
  • a resonator bottom electrode 40 is formed on the other side of the quartz wafer 10 by metal sputtering or evaporation.
  • the bottom electrode 40 is composed of at least one layer of metal, and the metal in direct contact with the surface of the quartz wafer 10 should be chromium, titanium tungsten, molybdenum, gold, silver, etc.
  • Step 13 Make mask 20C. As shown in FIG. 24 , a mask 20C is made on the first package substrate 50 in FIG. 24 , and the mask 20C on this side is patterned using micro/nano electromechanical system photolithography to expose the conductive blind holes 52 'Corresponding area.
  • the mask 20C can be SU-8 glue or other photoresist suitable for dry etching.
  • Step 14 Dry etching. As shown in Figure 25, the first packaging substrate 50 is etched using the mask 20C as a barrier layer to expose the conductive blind holes 52'.
  • Step 15 Remove mask 20C. As shown in FIG. 26 , after the above dry etching, the mask 20C can be removed by wet etching.
  • Step 16 Form conductive vias. As shown in Figure 27, a conductive material is provided on the first package substrate 50 side to electrically connect with the conductive blind hole 52' to form a conductive through hole 52.
  • the above steps 13 to 16 may not be required.
  • a thinning process such as grinding may be directly used to expose the conductive blind holes, and then step 16 is performed to form the conductive vias 52 .
  • Step 17 Frequency measurement and frequency modulation.
  • the quality of the top electrode 30 can be changed using, for example, a particle beam to improve the quality of the quartz resonator.
  • Resonant frequency As can be understood, when the measured resonant frequency meets the set frequency, the frequency modulation step does not need to be performed. This process can be seen in Figure 33.
  • Step 18 Bond the second package substrate.
  • the quartz wafer 10 after frequency measurement or frequency modulation is aligned with the quartz wafer or the second packaging substrate 60 .
  • the second packaging substrate 60 and the quartz wafer 10 can be bonded together using a metal diffusion bonding method, which can be gold-gold, gold-tin, copper-tin bonding, or other methods. They can also be joined together in other ways, which are not limited here.
  • the second packaging substrate 60 may also use other packaging materials.
  • the second packaging substrate 60 when the second packaging substrate 60 is a quartz substrate, it may be a quartz wafer with a thickness of 20-300 ⁇ m and completely consistent with the wafer size specifications of the quartz wafer 10 .
  • the second packaging substrate 60 is provided with a second packaging substrate conductive through hole 62 , which is electrically connected to the electrode lead-out portion of the bottom electrode 40 .
  • a metal bonding layer is also provided at the joint between the second packaging substrate 60 and the quartz wafer 10 72B.
  • a filling metal layer 74B is provided between the second packaging substrate 60 and the quartz wafer 10 and spaced apart from the outer side of the metal bonding layer 72B.
  • the filling metal layer 74B only needs to be provided on the side where the external connection is provided in the subsequent step 11.
  • the first packaging substrate 50 and the second packaging substrate 60 are respectively disposed on both sides of the quartz wafer to form a composite structure.
  • the composite structure is a sandwich structure including the first packaging substrate 50 , the piezoelectric layer, and the second packaging substrate 60 .
  • Step 19 Divide or slice the composite structure. Multiple structures in Figure 29 that are connected together are formed into individual structural particles, and the divided individual structural particles are as shown in Figure 29 .
  • Step 20 Provide external connection portion 34.
  • the electrode lead-out end of the top electrode 30 of each structural shot includes an external connection portion 34 that extends to at least the first packaging substrate 50 and the second packaging substrate 60 via the end surfaces of the packaging substrate 50 and the second packaging substrate 60 .
  • the external connection portion 34 may be formed by metal sputtering or evaporation.
  • the electrode lead-out end of the bottom electrode may also include the external connection portion, so that it can extend at least through the end surfaces of the second packaging substrate 60 and the first packaging substrate 50 to an end of the first packaging substrate 50 away from the top electrode 30 side.
  • the external connection portion 34 extends through the end surfaces of the first packaging substrate 50 and the second packaging substrate 60 .
  • the electrode lead-out portion of the electrode is led out from between the packaging substrate and the quartz piezoelectric layer, there may be a situation where only the end surface of one of the two packaging substrates is covered. This is It is also within the protection scope of the present invention.
  • the external connection portion 34 is connected to the filling metal layer 74A and the filling metal layer 74B. Because of the presence of the filling metal layer, it is helpful to keep the end surface of the composite structure where the external connection portion 34 needs to be placed flat after dicing or dividing, thereby being beneficial to the smoothness or planarization of the external connection portion 34 and the stability of the electrical connection.
  • micro/nano electromechanical systems (M/NEMS) photolithography technology is used in combination with wet etching/dry etching to: make the size of the particles less than 1 mm ⁇ 1 mm; and/or The thickness of the resonant region of the shot particles is less than 40 ⁇ m or the fundamental frequency of the resonator formed based on the shot particles is above 40 MHz.
  • M/NEMS micro/nano electromechanical systems
  • micro/nano electromechanical system photolithography technology it is possible to obtain fine patterns for subsequent etching that facilitate the formation of particle sizes less than 1 mm ⁇ 1 mm, while based on wet etching/dry etching, it is possible to Obtain particles with a size less than 1mm ⁇ 1mm; based on wet etching/dry etching, it can replace the mechanical mask to obtain a quartz piezoelectric layer thickness less than 40 ⁇ m.
  • the electrode lead-out portion of the top electrode and the electrode lead-out portion of the bottom electrode of the quartz resonator are on the same side of the packaging substrate, which is beneficial to: reducing/avoiding the possibility of electrodes crossing the piezoelectric layer. There is a technical problem of unstable electrode resistance.
  • the resonance structure of the quartz resonator adopts an anti-elevation structure.
  • This structure improves the impact resistance of the chip.
  • this structure can improve the boundary of the resonance area of the chip and reduce the lateral leakage of sound waves; and, the anti-elevation platform
  • the structure provides space for the vibration area, which avoids digging grooves in the package cover and helps to make the chip thinner.
  • the resonant region refers to the overlapping region of the top electrode, bottom electrode, piezoelectric layer, and cavity or gap in the thickness direction of the piezoelectric layer in the formed quartz resonator.
  • the resonance area of the wafer corresponds to the area in the wafer that needs to be formed as a resonance area of the resonator;
  • the resonance area of the piezoelectric layer corresponds to the area in the piezoelectric layer that needs to be formed as the resonance area of the resonator.
  • the non-resonant region is a portion outside the resonant region.
  • the non-resonant region of the piezoelectric layer refers to the region outside the resonant region of the piezoelectric layer in the horizontal or lateral direction.
  • each numerical range except that it is clearly stated that it does not include the endpoint value, can be the endpoint value or the median value of each numerical range, which are all within the protection scope of the present invention. .
  • the quartz resonator according to the present invention can be used to form a quartz crystal oscillator chip or an electronic device including a quartz resonator.
  • the electronic device here may be an electronic component such as an oscillator, a communication device such as a walkie-talkie or a mobile phone, or a large-scale product using a quartz resonator such as an automobile.
  • a quartz resonator including:
  • the bottom electrode and the top electrode, one of the top electrode and the bottom electrode is a first electrode, the other is a second electrode, the first electrode is on one side of the piezoelectric layer, and the second electrode is on one side of the piezoelectric layer.
  • the first packaging substrate and the second packaging substrate are respectively arranged on one side and the other side of the piezoelectric layer.
  • the first packaging substrate is opposite to the first electrode
  • the second packaging substrate is opposite to the second electrode.
  • the electrode lead-out end of the first electrode includes a first external connection portion extending at least through the end surface of the second packaging substrate to a side of the second package substrate away from the second electrode, or the electrode lead-out end of the second electrode includes at least one end through the first package substrate.
  • the end surface of the packaging substrate extends to the second external connection portion on a side of the first packaging substrate away from the first electrode.
  • the first external connection portion extends to a side of the second packaging substrate away from the second electrode via at least the end surfaces of the first packaging substrate and the second packaging substrate, or the second external connection portion extends at least via the second packaging substrate and the first packaging substrate.
  • the end surface extends to a side of the first packaging substrate away from the first electrode.
  • the first packaging substrate is provided with a first packaging substrate conductive through hole, the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode, the second packaging substrate is provided with a second packaging substrate conductive through hole, the The conductive via hole of the second packaging substrate is electrically connected to the electrode lead-out portion of the second electrode;
  • the first external connection portion is electrically connected to the conductive via hole of the first packaging substrate on a side of the first packaging substrate away from the first electrode and extends through the end surfaces of the first packaging substrate and the second packaging substrate to the second package.
  • the side of the substrate away from the second electrode, or the second external connection portion is electrically connected to the second packaging substrate conductive via hole on the side of the second packaging substrate away from the second electrode and extends through the second packaging substrate and the third An end surface of a packaging substrate extends to a side of the first packaging substrate away from the first electrode.
  • the first packaging substrate and the second packaging substrate are respectively bonded to the piezoelectric layer on both sides of the piezoelectric layer to form a sandwich structure.
  • the piezoelectric layer is an inverted platform structure including a boss, and the first packaging substrate and the second packaging substrate are respectively joined to the boss on both sides of the quartz piezoelectric layer to form the sandwich structure. .
  • the piezoelectric layer is a double-sided reverse platform structure
  • the piezoelectric layer is a single-sided reverse platform structure
  • the side of the first packaging substrate and the second packaging substrate facing the boss is a flat surface
  • a cavity is provided on a side of the first packaging substrate and/or the second packaging substrate facing the boss, and the projection of the resonance area of the resonator in the thickness direction falls into the cavity.
  • the first packaging substrate and the second packaging substrate are respectively bonded to the piezoelectric layer on both sides of the piezoelectric layer based on a metal bonding layer to form a sandwich structure;
  • the resonator further includes a filling metal layer outside the metal bonding layer and spaced apart from the metal bonding layer, and the filling metal layer is connected to the outer connection portion.
  • the metal bonding layer is spaced apart from the fill metal layer by a distance in the range of 2-200 microns.
  • the piezoelectric layer is a flat structure
  • a cavity is provided on the side of the first packaging substrate and the second packaging substrate facing the piezoelectric layer, and the projection of the resonance area of the resonator in the thickness direction falls into the cavity.
  • the resonator is a cantilever structure.
  • the first packaging substrate and the second packaging substrate are both quartz substrates.
  • the size of the piezoelectric layer is less than 1mm ⁇ 1mm; and/or
  • the thickness of the resonant region of the piezoelectric layer is less than 40 ⁇ m or the fundamental frequency of the resonator is above 40 MHz.
  • An electronic device including the quartz resonator according to any one of 1-12.
  • a method for manufacturing a quartz resonator including the steps:
  • Forming a resonant structure on a quartz wafer includes the steps of: using at least micro/nano electromechanical system photolithography technology to form a quartz piezoelectric layer corresponding to a plurality of quartz resonators on the quartz wafer, on one side of the quartz piezoelectric layer and on the other side of the quartz piezoelectric layer.
  • a first electrode layer including a first electrode and a second electrode layer including a second electrode are respectively provided on one side;
  • first packaging substrate and a second packaging substrate Provide a first packaging substrate and a second packaging substrate: the first packaging substrate and the second packaging substrate are respectively disposed on both sides of the quartz piezoelectric layer to form a composite structure, the first packaging substrate and the first electrode layer Oppositely, the second packaging substrate is opposite to the second electrode layer; and
  • Segmentation at least cutting or splitting the composite structure to form a plurality of mechanically separated structural particles
  • Providing an external connection part for the structural particles including the step of: making the electrode lead-out end of the first electrode of each structural particle include a first external connection part, the first external connection part extending to at least via the end surface of the second packaging substrate.
  • the side of the second packaging substrate away from the second electrode, or the electrode lead-out end of the second electrode of each structural particle includes a second external connection portion, which is at least via the end surface of the first packaging substrate Extending to a side of the first package substrate away from the first electrode.
  • the first external connection portion extends at least through the end surfaces of the first packaging substrate and the second packaging substrate to a side of the second packaging substrate away from the second electrode, or the second external connection portion The portion extends at least through the second packaging substrate and the end surface of the first packaging substrate to a side of the first packaging substrate away from the first electrode.
  • the first packaging substrate and the second packaging substrate are respectively bonded to the piezoelectric layer on both sides of the piezoelectric layer to form a composite structure. It is a sandwich structure.
  • the step of providing the external connection portion for the structural shot includes: forming the external connection portion by metal sputtering or evaporation.
  • the first packaging substrate and the second packaging substrate are respectively joined to the piezoelectric layer on both sides of the piezoelectric layer in a metal bonding manner to form a composite structure including the first packaging substrate, the piezoelectric layer The sandwich structure of the layer and the second packaging substrate;
  • the method further includes the steps of: arranging a filling metal layer spaced apart from the bonding layer outside the bonding layer formed by metal bonding; and
  • the external connection portion is in contact with the filling metal layer to facilitate planarization of the external connection portion at the end face of the sandwich structure.
  • step of forming the resonant structure with the quartz wafer includes:
  • Setting the first mask and patterning setting the first mask on both sides of the quartz wafer, and patterning the first mask on one or both sides using at least micro/nano electromechanical system lithography technology to expose a region corresponding to the resonant region of the resonator;
  • Primary thinning Use wet etching and/or dry etching to etch the exposed area of the quartz wafer to form an inverted mesa structure on the side where the exposed area of the quartz wafer is located;
  • Setting the first electrode layer setting the first electrode layer on one side of the quartz wafer forming the reverse platform structure
  • Measurement or secondary thinning Use optical methods to measure whether the thickness of the resonance area of the quartz wafer reaches the predetermined thickness on the other side of the quartz wafer, and if the thickness does not reach the predetermined thickness, measure whether the thickness of the resonance area of the quartz wafer reaches the predetermined thickness. On the other side of the circle, secondary thinning is performed on the quartz wafer so that the thickness of the quartz wafer in the resonance region reaches a predetermined thickness;
  • Set the second electrode layer Set the second electrode layer on the other side of the quartz wafer after performing the measurement or secondary thinning step.
  • Measurement or frequency modulation Measure the resonant frequency of the resonant area where the second electrode layer is set, and when the measured resonant frequency is less than the predetermined resonant frequency, increase the resonant frequency of the resonant area to the predetermined resonant frequency.
  • the first mask is set on both sides of the quartz wafer and the first mask is patterned on only one side of the quartz wafer using micro/nano electromechanical system photolithography technology. to expose a region corresponding to the resonant region of the resonator;
  • the quartz wafer provided with the first electrode layer is hermetically bonded to one side of the first packaging substrate;
  • the step further includes: setting a second mask on the other side of the quartz wafer and patterning it to expose the quartz crystal on the other side of the quartz wafer. Performing etching on the resonant region on the other side of the quartz wafer can form an inverse mesa structure on the other side of the quartz wafer, and remove the second mask.
  • the step further includes: performing a thinning process on the other side of the quartz wafer as a whole.
  • step of providing the first packaging substrate or the second packaging substrate includes:
  • a conductive blind hole is provided on one side of the substrate, and the conductive blind hole is suitable for electrical connection with the electrode lead-out portion of the corresponding electrode;
  • a third mask on the other side of the substrate, pattern the third mask to expose the position corresponding to the conductive blind hole, etch the first package substrate to expose the conductive blind hole, and remove the third mask , a conductive through hole is provided on the other side of the first packaging substrate, and the conductive through hole is electrically connected to the conductive blind hole;
  • a thinning process is performed on the other side of the substrate to expose the conductive blind hole, and a conductive through hole is provided on the other side of the substrate, and the conductive through hole is electrically connected to the conductive blind hole.
  • the first packaging substrate is provided with a first packaging substrate conductive through hole, the first packaging substrate conductive through hole is electrically connected to the electrode lead-out portion of the first electrode, the second packaging substrate is provided with a second packaging substrate conductive through hole, the The conductive via hole of the second packaging substrate is electrically connected to the electrode lead-out portion of the second electrode;
  • the first external connection portion is electrically connected to the first packaging substrate conductive via hole on a side of the first packaging substrate away from the first electrode and extends through the first packaging substrate and The end surface of the second packaging substrate extends to the side of the second packaging substrate away from the second electrode, or the second external connection portion is in electrical conduction with the second packaging substrate on the side of the second packaging substrate away from the second electrode.
  • the hole is electrically connected and extends through the end surfaces of the second packaging substrate and the first packaging substrate to a side of the first packaging substrate away from the first electrode.

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Abstract

本发明涉及一种石英谐振器及其制造方法，所述石英谐振器包括：石英压电层；底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，其中：第一电极的电极引出端包括至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧的第一外连接部，或者第二电极的电极引出端包括至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧的第二外连接部。本发明还涉及一种电子器件。

Description

封装基底的端面设置外连接部石英谐振器及其制造方法、电子器件 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种封装基底的端面设置外连接部石英谐振器及其制造方法，以及一种电子器件。
背景技术
高基频、小型化和低矮化是石英晶振片(下文中简称为晶片)发展的趋势。传统晶片制造方案多采用研磨切片的方式获得一定频率的散粒薄片，然后进行后续的镀电极与调频。然而，切片所采用的线切割技术对1mm×1mm及以下尺寸难以实现，基本无法覆盖1.2mm×1.0mm及以下尺寸的晶片制造，更无法满足1.0mm×0.8mm及以下尺寸规格晶片制造。晶片的基频主要受晶片谐振区域的厚度决定，晶片的基频由以下公式支配：
f0(MHz)＝1670(MHz·μm)/d(μm)     (1)
晶圆级制造可以实现单颗谐振器制造成本的大幅降低，以及谐振器之间的品控一致性；通常来说，晶圆尺寸越大，单颗谐振器的制造成本越低。然而，对于晶圆级制造方案，几百至数千颗晶片排列在单片晶圆上，对各个位置点石英厚度的精确控制挑战巨大，这也就直接导致了整片晶圆上晶片频率的准确性与一致性难以得到保证。因此，晶圆级晶片调频存在极大的挑战。目前已有技术采取的办法主要集中在采用具有超高精度膜厚监控系统的研磨技术，制备厚度均一度在几纳米之内的石英薄膜。这种频率控制与调节技术对材料和制造工 艺提出了极高的要求，而且晶圆面积越大，制造难度越高，阻碍了低成本、高效率的制造方案的产生。
现有的石英谐振器的顶电极的电极引出部和底电极的电极引出部中的一个经由压电层的边缘延伸到与另一个电极引出部同侧的位置，这种跨压电层布置电极引出部的方式，容易出现电极连接电阻不稳定(偏大甚至电连接断开)的问题。
此外，还希望在晶圆级制造单颗谐振器的基础上，优化谐振器的边界条件、减少声波横向泄漏，从而进一步提高谐振器的性能。但是，通过现有的机械研磨减薄方式难以优化谐振器的边界条件。
发明内容
为缓解或解决现有技术中的上述问题的至少一个方面，提出本发明。
根据本发明的实施例的一个方面，提出了一种石英谐振器，包括：
石英压电层；
底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
第一电极的电极引出端包括至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧的第一外连接部，或者第二电极的电极引出端包括至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧的第二外连接部。
根据本发明的实施例的另一方面，提出了一种石英谐振器的制造方法，包括步骤：
提供石英晶圆；
以石英晶圆形成谐振结构，包括步骤：至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层，在石英压电层的一侧和另一侧分别设置包括第一电极的第一电极层和包括第二电极的第二电极层；
提供第一封装基板和第二封装基板：所述第一封装基板和所述第二封装基 板分别设置在所述石英压电层的两侧以形成复合结构，第一封装基板与第一电极层相对，第二封装基板与第二电极层相对；和
分割：至少将所述复合结构切割或者裂片，以形成机械分离的多个结构散粒；
为结构散粒提供外连接部，包括步骤：使得每个结构散粒的第一电极的电极引出端包括第一外连接部，所述第一外连接部至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者使得每个结构散粒的第二电极的电极引出端包括第二外连接部，所述第二外连接部至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
本发明的实施例还涉及一种电子器件，包括上述的石英谐振器。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1-11为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图；
图12-30为根据本发明的另一个示例性实施例的石英谐振器的制作过程的截面示意图；
图31为根据本发明的一个示例性实施例的石英谐振器的截面示意图；
图32为石英晶圆的谐振区域的基频调节的流程示意图；
图33为石英谐振器的谐振频率调节的流程示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
本发明提出一种基于微/纳机电系统(M/NEMS)光刻技术的石英晶片制造工 艺，可以用于制作小尺寸、频率精准的石英谐振器。本发明中，采用了晶圆级频率/厚度监测与调控方法，降低了对石英晶圆片厚度加工均一度的要求，降低了加工难度。本方案对不同频段的石英晶片的制造普遍适用，并且不受石英晶圆面积的限制，具有明显的优势。
本发明基于微纳机电系统(M/NEMS)的晶片制造方案充分利用了MEMS光刻技术和晶圆级工艺制造方式的优势，利用湿法刻蚀晶片轮廓的方法，摆脱了切割技术对晶片尺寸的限制，可以实现1210、1008及以下更小尺寸晶片的加工。此外，晶圆制造的晶片加工方案能够提高尺寸加工精度，提高晶片加工效率。
本发明提出了一种晶圆级晶片制造与频率控制制程，摆脱了石英晶片对超高精度研磨技术的需求，同时大大降低了调频的难度，使得调频完全不受晶圆面积扩大的制约。同时，该方案满足了从低频到高频(30-300MHz)、超高频率(300MHz-3GHz)晶片的小型化制造，对推动石英晶片领域的发展具有重要意义。
下面参照图1-33示例性说明根据本发明的石英谐振器的制作过程。本发明中，附图标记示意性说明如下：
10：石英晶圆或晶圆或压电层。
12：谐振区域。
14：凸台。
20A：第一掩膜层或掩膜。
20B：第二掩膜层或掩膜。
20C：第三掩膜层或掩膜。
22：掩膜槽或掩膜开孔。
30：顶电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
32：顶电极的电连接部，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。在可选的实施例中，顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。
34：外连接部，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。在可选的实施例中，外连接部、顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。
40：底电极，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
50：第一封装石英晶圆或第一封装基板。
52：第一封装基板导电通孔。
52’：导电盲孔。
54：空腔
60：第二封装石英晶圆或第二封装基板。
62：第二封装基板导电通孔。
64：空腔。
72A、72B：金属键合层，可以是金金、金锡、铜锡键合等方式。
74A、74B：填充金属层，在可选的实施例中，填充金属层、外连接部、顶电极及其电连接部、底电极及其电连接部可以是相同的金属材料。
在本发明的具体实施例中，各部分以其中可行的一种材料为例进行说明，但不限于此。
图1-图11为根据本发明的一个示例性实施例的石英谐振器的制作过程的截面示意图。下面参照图1-图11示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图1所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)和另一侧(例如次面)制作掩膜20A，利用微/纳机电系统光刻的方式使得处于两面的掩膜20A被图案化，以露出石英晶圆的谐振区域。如图1所示的实施例中，图案化后的掩膜20A为边框掩膜的形式。
这里，对于后续使用湿法刻蚀(例如图1-图11所示实施例的步骤2)，掩膜可以是金属掩膜，例如铬金(上面一层金、下面一层铬)，或者其他惰性金属；对于后续使用干法刻蚀(例如图1-图11所示实施例的步骤2)，掩膜可以是SU-8胶，或者其他适合干法刻蚀的光刻胶。掩膜20A的材料也可以适用于其他实施例，后面不再赘述。
需要指出的是，在图1-图11中，仅仅示出了晶圆上的单个石英谐振器对应的区域，如能够理解的，在石英晶圆10上存在多个图1-图10所示的区域。在其他的实施例中，也应做相似的理解，后面不再赘述。
步骤2：湿法刻蚀。如图2所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10进行刻蚀，刻蚀深度为d1(d1等于石英谐振器设定频率对应的石英膜厚d0)。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。如图2所示，石英晶圆形成了双面反高台结构。
如能够理解的，也可以仅仅在一侧设置反高台结构，不过，此时，与石英晶圆接合的基底需要有空腔。
图31示出了本发明的一个示例性实施例的谐振器结构，其中：第一封装基板50和第二封装基板60面对压电层的一侧分别设置有空腔54和64，所述谐振器的谐振区域在厚度方向上的投影落入所述空腔内。在图31中，压电层的双侧为平坦面，但是，如能够理解的，在图31中，压电层的一侧或两侧也可以为反高台结构，或者，在图31中，在压电层的一侧为反高台结构的情况下，对应的基底与之面对的一侧也可以不设置有空腔，这些均在本发明的保护范围之内。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：去除掩膜20A。如图3所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤4：制作顶电极。如图4所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10的一侧制作谐振器的顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了谐振区域12。
步骤5：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图5所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依据。
步骤6：调节石英薄膜厚度。如图6所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图5和图6操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图32。
步骤7：制作底电极。如图7所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10的另一侧制作谐振器底电极40。底电极40至少由一层金属构成，其 中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。
步骤8：接合第一封装基板。如图8所示，将制作了底电极40的上述石英晶圆10与石英晶圆或第一封装基板50对准。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。第一封装基板50也可以采用其他的封装材料。
在本发明的实施例中，第一封装基板50是石英基底的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图8所示，第一封装基板50设置有第一封装基板导电通孔52，其与顶电极30的电极引出部电连接。
如图8所示的实施例中，在第一封装基板50与石英晶圆10之间以金属键合的情况下，第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。
进一步的实施例中，如图8所示，在第一封装基板50与石英晶圆10之间，在金属键合层72A的外侧与之间隔开的设置有填充金属层74A。如能够理解的，在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74A。
在本发明的一个实施例中，金属键合层72A与填充金属层74A间隔开的距离在2-100微米的范围内。
如能够理解的，石英晶圆10与第一封装基板50接合，也可以在上述的步骤6之后、步骤7之前。
步骤9：测频与调频。测量所得的石英谐振器的谐振频率f，在测得的谐振频率小于预定谐振频率f0的情况下，如图9所示，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图33。
步骤10：接合第二封装基板。如图10所示，将测频或调频后的上述石英晶圆10与石英晶圆或第二封装基板60对准。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。第二封装基板60也可以采用其他的封装材料。
在本发明的实施例中，第二封装基板60是石英基底的情况下，其可以是厚 度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图10所示，第二封装基板60设置有第二封装基板导电通孔62，其与底电极40的电极引出部电连接。
如图10所示的实施例中，在第二封装基板60与石英晶圆10之间以金属键合的情况下，第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。
进一步的实施例中，如图10所示，在第二封装基板60与石英晶圆10之间，在金属键合层72B的外侧与之间隔开的设置有填充金属层74B。如能够理解的，在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74B。
在本发明的一个实施例中，金属键合层72B与填充金属层74B间隔开的距离在2-200微米的范围内。
第一封装基板50和第二封装基板60分别设置在石英晶圆的两侧以形成复合结构，该复合结构为包括第一封装基板50、压电层、第二封装基板60的三明治结构。
步骤11：将复合结构分割或划片。以将连接在一起的多个图10中的结构形成为单独的结构散粒，分割后的单独的结构散粒如图10所示。
步骤12：提供外连接部34。使得每个结构散粒的顶电极30的电极引出端包括外连接部34，所述外连接部34至少经由第一封装基板50和第二封装基板60的端面延伸到第二封装基板60的远离底电极的一侧。
在本发明的实施例中，可以以金属溅射或者蒸镀的方式形成外连接部34。
如能够理解的，也可以底电极的电极引出端包括该外连接部，从而可以至少经由第二封装基板60和第一封装基板50的端面延伸到第一封装基板50的远离顶电极30的一侧。
在本发明的实施例中，因为封装基底设置有导电通孔，从而外连接部34延伸过第一封装基板50和第二封装基板60的端面。不过，在可选的实施例中，在电极的电极引出部从封装基底与石英压电层之间引出的情况下，则存在仅覆盖两个封装基底中的一个封装基底的端面的情况，这也在本发明的保护范围之内。
如图11所示，外连接部34与填充金属层74A以及填充金属层74B连接。因为填充金属层的存在，有利于保持复合结构在划片或者分割后的需要设置外连接部34的端面保持平整，从而有利于外连接部34的平整或平坦化以及电连 接的稳定性。
在本发明中，封装基底可以是石英基底，也可以其他材料的基底，如硅、玻璃、蓝宝石等。在后面的实施例中不再赘述。
在本发明中，在为全石英封装的情况下，封装基底为透明材料。因此，调频也可以发生在封装完成之后，利用激光透过透明的石英封装盖直接调节频率，用来调整因为封装应力带来的频率变动。在后面的实施例中不再赘述。
在本发明中，在一个封装基底的同一侧同时设置了底电极和顶电极的电极引出部的端部。这相对于现有技术中两个电极的引出部分别设置在压电层的两侧具有如下技术效果：减小封装复杂度；此外，这相对于现有技术中一个电极的引出部经由压电层的边缘而到达压电层的另一侧从而与另一电极的引出部同面设置具有如下技术效果：减小/避免了电极跨越压电层时可能存在的电极阻值不稳定的问题。
本发明中，石英谐振器的谐振结构利用采用反高台的结构，这相比于压电层为平坦结构的实施例具有更好结构稳定性，提高了晶片抗冲击能力。
图12-图30为根据本发明的另一个示例性实施例的石英谐振器的制作过程的截面示意图。在该实施例中，可以适用于利用任何尺寸规的石英晶圆进行晶片制造。
下面参照图12-图30示例性说明石英谐振器的制作过程，其包括步骤如下：
步骤1：制作掩膜20A。如图12所示，在石英晶圆(例如直径为1-8英寸，厚度为100μm至1mm)的一侧(例如正面)和另一侧(例如次面)制作掩膜20A，利用微/纳机电系统光刻的方式使得处于一侧的掩膜20A被图案化，以露出石英晶圆的谐振区域，而另一侧的第一掩膜20A没有被图案化。如图12所示的实施例中，图案化后的掩膜20A为边框掩膜的形式。
这里，对于后续使用湿法刻蚀(例如图12-图30所示实施例的步骤2)，掩膜可以是金属掩膜，例如铬金(上面一层金、下面一层铬)，或者其他惰性金属；对于后续使用干法刻蚀(例如图12-图30所示实施例的步骤2)，掩膜可以是SU-8胶，或者其他适合干法刻蚀的光刻胶。掩膜20A的材料也可以适用于其他实施例，后面不再赘述。
步骤2：湿法刻蚀。如图13所示，以掩膜20A作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英 晶圆10进行刻蚀。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。
虽然没有示出，步骤2也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤3：去除掩膜20A。如图14所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20A。
步骤4：制作顶电极。如图15所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10的一侧制作谐振器的顶电极30。顶电极30至少由一层金属构成，其中在石英晶圆10表面直接接触的金属可以为铬、钛钨、钼、金、银等。顶电极30覆盖了谐振区域12。
步骤5：接合第一封装基板。如图16所示，将制作了顶电极30的上述石英晶圆10与石英晶圆或第一封装基板50对准。第一封装基板50与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。第一封装基板50也可以采用其他的封装材料。
在本发明的实施例中，第一封装基板50是石英基底的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图16所示，第一封装基板50设置有用于第一封装基板导电通孔52的导电盲孔52’，其与顶电极30的电极引出部电连接。
如图16所示的实施例中，在第一封装基板50与石英晶圆10之间以金属键合的情况下，第一封装基板50与石英晶圆10接合处还设置有金属键合层72A。
进一步的实施例中，如图16所示，在第一封装基板50与石英晶圆10之间，在金属键合层72A的外侧与之间隔开的设置有填充金属层74A。如能够理解的，在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74A。
步骤6：对图16中的结构执行双面减薄。如图17所示，例如利用研磨和抛光工艺对第一封装基板50和石英晶圆10进行减薄，例如，至100μm以下。
如能够理解的，在石英晶圆10的厚度合适的情况下，也可以不执行减薄；在第一封装基板50的厚度也合适的情况下，也可以不执行减薄。
步骤7：制作掩膜20B。如图18所示，在石英晶圆的另一侧以及第一封装基板50的下侧制作掩膜20B，利用微/纳机电系统光刻的方式使得处于该侧的掩 膜20B被图案化，以露出石英晶圆的谐振区域，而处于第一封装基板50下侧的掩膜20B则没有被图案化。如图18所示的实施例中，图案化后的掩膜20B为边框掩膜的形式。
这里，对于后续使用湿法刻蚀(例如图12-图30所示实施例的步骤2)，掩膜20B可以是金属掩膜，例如铬金(上面一层金、下面一层铬)，或者其他惰性金属；对于后续使用干法刻蚀(例如图12-图30所示实施例的步骤2)，掩膜20B可以是SU-8胶，或者其他光刻胶。
步骤8：湿法刻蚀。如图19所示，以掩膜20B作为阻挡层，利用刻蚀液(例如温度高于20℃、浓度高于5％的HF刻蚀液、HF/NH4F混合刻蚀液)对上述石英晶圆10的另一侧进行刻蚀。例如，在高温高浓度刻蚀液作用下，可以获得较高的刻蚀速率和较为陡峭的晶面坡度。
虽然没有示出，步骤8也可以用干法刻蚀代替，或者将湿法刻蚀与干法刻蚀结合。
步骤9：去除掩膜20B。如图20所示，上述石英晶圆10刻蚀之后，可以进行清洗、烘干，然后湿法刻蚀的方式去除掩膜20B。
步骤10：晶圆级膜厚测量。利用光学方法对研磨后的谐振区域石英厚度进行厚度测量。测量点必须选在石英薄膜另一面有顶电极的区域。如图21所示，利用光学测量透明薄膜厚度的方法对各个晶片的谐振区域石英薄膜厚度进行测量，并得到与设计值d0之间的差值，以为下一步逐个晶片进行膜厚调节提供依据。
步骤11：调节石英薄膜厚度。如图22所示，利用离子束刻蚀或者湿法刻蚀的方式对晶片谐振区域石英片进行二次刻蚀。重复图21和图22操作，对晶片进行多次厚度调节，最终获得精准的厚度。该流程可以参见图32。
步骤12：制作底电极。如图23所示，利用金属溅射或者蒸镀的方式在上述石英晶圆10的另一侧制作谐振器底电极40。底电极40至少由一层金属构成，其中在石英晶圆10表面直接接触的金属应为铬、钛钨、钼、金、银等。
步骤13：制作掩膜20C。如图24所示，在图24中第一封装基板50上制作掩膜20C，利用微/纳机电系统光刻的方式使得处于该侧的掩膜20C被图案化，以露出与导电盲孔52’对应的区域。
这里，对于后续使用干法刻蚀(例如图12-图30所示实施例的步骤14)， 掩膜20C可以是SU-8胶，或者其他适合干法刻蚀的光刻胶。
步骤14：干法刻蚀。如图25所示，以掩膜20C作为阻挡层，对上述第一封装基板50进行刻蚀，以露出所述导电盲孔52’。
步骤15：去除掩膜20C。如图26所示，上述干法刻蚀之后，可以用湿法刻蚀的方式去除掩膜20C。
步骤16：形成导电通孔。如图27所示，在第一封装基板50侧设置导电材料以与导电盲孔52’电连接而形成导电通孔52。
如能够理解的，在第一封装基板50与石英晶圆10接合之前已经设置有导电通孔52的情况下可以不需要上述的步骤13-步骤16。
如能够理解的，可以直接用例如研磨的减薄工艺以露出导电盲孔，然后执行步骤16以形成导电通孔52。
步骤17：测频与调频。测量所得的石英谐振器的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，如图28所示，可以利用例如粒子束的方式改变顶电极30的质量，以提升石英谐振器的谐振频率。如能够理解的，在测得的谐振频率符合设定频率的情况下，可以不用执行调频步骤。该流程可以参见图33。
步骤18：接合第二封装基板。如图29所示，将测频或调频后的上述石英晶圆10与石英晶圆或第二封装基板60对准。第二封装基板60与石英晶圆10可以利用金属扩散键合方式键合在一起，可以是金金、金锡、铜锡键合等方式。也可以采用其他的方式接合在一起，这里不做限定。第二封装基板60也可以采用其他的封装材料。
在本发明的实施例中，第二封装基板60是石英基底的情况下，其可以是厚度为20-300μm、与石英晶圆10的晶圆尺寸规格完全一致的石英晶圆。
如图29所示，第二封装基板60设置有第二封装基板导电通孔62，其与底电极40的电极引出部电连接。
如图29所示的实施例中，在第二封装基板60与石英晶圆10之间以金属键合的情况下，第二封装基板60与石英晶圆10接合处还设置有金属键合层72B。
进一步的实施例中，如图29所示，在第二封装基板60与石英晶圆10之间，在金属键合层72B的外侧与之间隔开的设置有填充金属层74B。如能够理解的，在后续的步骤11中设置外连接部的一侧才需要设置填充金属层74B。
第一封装基板50和第二封装基板60分别设置在石英晶圆的两侧以形成复合结构，该复合结构为包括第一封装基板50、压电层、第二封装基板60的三明治结构。
步骤19：将复合结构分割或划片。以将连接在一起的多个图29中的结构形成为单独的结构散粒，分割后的单独的结构散粒如图29所示。
步骤20：提供外连接部34。如图30所示，使得每个结构散粒的顶电极30的电极引出端包括外连接部34，所述外连接部34至少经由第一封装基板50和第二封装基板60的端面延伸到第二封装基板60的远离底电极的一侧。
在本发明的实施例中，可以以金属溅射或者蒸镀的方式形成外连接部34。
如能够理解的，也可以底电极的电极引出端包括该外连接部，从而可以至少经由第二封装基板60和第一封装基板50的端面延伸到第一封装基板50的远离顶电极30的一侧。
在本发明的实施例中，因为封装基底设置有导电通孔，从而外连接部34延伸过第一封装基板50和第二封装基板60的端面。不过，在可选的实施例中，在电极的电极引出部从封装基底与石英压电层之间引出的情况下，则存在仅覆盖两个封装基底中的一个封装基底的端面的情况，这也在本发明的保护范围之内。
如图30所示，外连接部34与填充金属层74A以及填充金属层74B连接。因为填充金属层的存在，有利于保持复合结构在划片或者分割后的需要设置外连接部34的端面保持平整，从而有利于外连接部34的平整或平坦化以及电连接的稳定性。
在本发明的实施例中，采用微/纳机电系统(M/NEMS)光刻技术与湿法刻蚀/干法刻蚀相结合，可以：使得散粒的尺寸小于1mm×1mm；和/或使得散粒的谐振区域的厚度小于40μm或者基于该散粒形成的谐振器的基频在40MHz以上。具体的，基于微/纳机电系统光刻技术，可以获得用于后续刻蚀的、便于形成小于1mm×1mm的散粒尺寸的精细图案，而基于湿法刻蚀/干法刻蚀，则可以获得小于1mm×1mm尺寸的散粒；基于湿法刻蚀/干法刻蚀，可以替代机械掩膜获得小于40μm的石英压电层厚度。
在本发明的实施例中，石英谐振器的顶电极的电极引出部和底电极的电极引出部处于封装基底的同一侧，这有利于：减小/避免了电极跨越压电层时可能 存在的电极阻值不稳定的技术问题。
在本发明的实施例中，石英谐振器的谐振结构利用采用反高台的结构，该结构提高了晶片抗冲击能力，另外该结构可以改善晶片谐振区域的边界，减少声波横向泄露；并且，反高台结构为振动区域提供了空间，可以避免在封装盖上挖槽，有助于晶片的薄型化。
在本发明中，谐振区域是指在形成的石英谐振器中，顶电极、底电极、压电层以及空腔或空隙在压电层的厚度方向上的重合区域。在本发明中，晶圆的谐振区域对应于在晶圆中需要形成为谐振器的谐振区域的区域；压电层的谐振区域对应于在压电层中需要形成为谐振器的谐振区域的区域。在本发明中，非谐振区域是谐振区域之外的部分，对于压电层的非谐振区域，指的是在压电层的谐振区域在水平方向或横向方向外侧的区域。
需要指出的是，在本发明中，各个数值范围，除了明确指出不包含端点值之外，除了可以为端点值，还可以为各个数值范围的中值，这些均在本发明的保护范围之内。
如本领域技术人员能够理解的，根据本发明的石英谐振器可以用于形成石英晶振芯片或包括石英谐振器的电子器件。这里的电子器件，可以是例如振荡器等电子元件，也可以例如对讲机、手机等的通信设备，还可以是汽车等应用了石英谐振器的大型产品。
基于以上，本发明提出了如下技术方案：
1、一种石英谐振器，包括：
石英压电层；
底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
其中：
第一电极的电极引出端包括至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧的第一外连接部，或者第二电极的电极引出端包括至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧的第二外连接部。
2、根据1所述的谐振器，其中：
第一外连接部至少经由第一封装基板和第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者第二外连接部至少经由第二封装基板和第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
3、根据2所述的谐振器，其中：
第一封装基板设置有第一封装基板导电通孔，所述第一封装基板导电通孔与第一电极的电极引出部电连接，第二封装基板设置有第二封装基板导电通孔，所述第二封装基板导电通孔与第二电极的电极引出部电连接；
所述第一外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过第一封装基板和第二封装基板的端面而延伸到第二封装基板的远离第二电极的一侧，或者所述第二外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过第二封装基板与第一封装基板的端面而延伸到第一封装基板的远离第一电极的一侧。
4、根据3所述的谐振器，其中：
所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层接合以形成三明治结构。
5、根据4所述的谐振器，其中：
所述压电层为包括凸台的反高台结构，所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成所述三明治结构。
6、根据5所述的谐振器，其中：
所述压电层为双面反高台结构；或者
所述压电层为单面反高台结构；或者
所述第一封装基板和第二封装基板中面对所述凸台的一侧为平坦面；或者
第一封装基板和/或第二封装基板面对所述凸台的一侧设置有空腔，所述谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
7、根据4所述的谐振器，其中：
所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层基于金属键合层接合以形成三明治结构；
所述谐振器还包括在金属键合层的外侧而与金属键合层分隔开的填充金属层，所述填充金属层与所述外连接部相接。
8、根据7所述的谐振器，其中：
所述金属键合层与所述填充金属层间隔开的距离在2-200微米的范围内。
9、根据4所述的谐振器，其中：
所述压电层为平坦结构；且
第一封装基板和第二封装基板面对所述压电层的一侧均设置有空腔，所述谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
10、根据9所述的谐振器，其中：
所述谐振器为悬臂结构。
11、根据1-10中任一项所述的谐振器，其中：
第一封装基板和第二封装基板均为石英基底。
12、根据1-11中任一项所述的谐振器，其中：
所述压电层的尺寸小于1mm×1mm；和/或
所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
13、一种电子器件，包括根据1-12中任一项所述的石英谐振器。
14、一种石英谐振器的制造方法，包括步骤：
提供石英晶圆；
以石英晶圆形成谐振结构，包括步骤：至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层，在石英压电层的一侧和另一侧分别设置包括第一电极的第一电极层和包括第二电极的第二电极层；
提供第一封装基板和第二封装基板：所述第一封装基板和所述第二封装基板分别设置在所述石英压电层的两侧以形成复合结构，第一封装基板与第一电极层相对，第二封装基板与第二电极层相对；和
分割：至少将所述复合结构切割或者裂片，以形成机械分离的多个结构散粒；
为结构散粒提供外连接部，包括步骤：使得每个结构散粒的第一电极的电极引出端包括第一外连接部，所述第一外连接部至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者使得每个结构散粒的第二电极的电极引出端包括第二外连接部，所述第二外连接部至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
15、根据14所述的方法，其中：
为结构散粒提供外连接部的步骤中，第一外连接部至少经由第一封装基板和第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者第二外连接部至少经由第二封装基板和第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
16、根据14所述的方法，其中：
在提供第一封装基板和第二封装基板的步骤中，所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层接合以形成的复合结构为三明治结构。
17、根据14所述的方法，其中：
为结构散粒提供外连接部的步骤包括：以金属溅射或者蒸镀的方式形成外连接部。
18、根据17所述的方法，其中：
所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层以金属键合的方式接合以形成的复合结构为包括第一封装基板、压电层、第二封装基板的三明治结构；
在提供外连接部之前，所述方法还包括步骤：在以金属键合形成的键合层的外侧设置与键合层间隔开的填充金属层；且
在提供外连接部的步骤中，所述外连接部与所述填充金属层接触以便于在三明治结构的端面的外连接部平坦化。
19、根据14所述的方法，其中，以石英晶圆形成谐振结构的步骤包括：
设置第一掩膜及图案化：在石英晶圆的两侧设置第一掩膜，以及在两侧中的一侧或两侧至少利用微/纳机电系统光刻技术对第一掩膜图案化以露出对应于谐振器的谐振区域的区域；
一次减薄：利用湿法刻蚀和/或干法刻蚀对石英晶圆的露出的区域予以刻蚀以在石英晶圆的露出的区域所在的一侧形成反高台结构；
移除第一掩膜；
设置第一电极层：在形成反高台结构的石英晶圆的一侧设置第一电极层；
测量或者二次减薄：利用光学方法在石英晶圆的另一侧测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶 圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度；
设置第二电极层：在执行了测量或者二次减薄步骤后的石英晶圆的另一侧设置第二电极层。
20、根据19所述的方法，还包括步骤：
测量或者调频：测量设置了第二电极层的谐振区域的谐振频率，在测得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
21、根据19所述的方法，其中：
设置第一掩膜及图案化的步骤中，在石英晶圆的两侧设置第一掩膜以及仅在石英晶圆的一侧至少利用微/纳机电系统光刻技术对第一掩膜图案化以露出对应于谐振器的谐振区域的区域；
提供第一封装基板的步骤中，将设置了第一电极层的石英晶圆密封接合到第一封装基板的一侧；
在设置第一电极层之后以及测量或者二次减薄之前，还包括步骤：在石英晶圆的另一侧设置第二掩膜并对其图案化以在石英晶圆的另一侧露出石英晶圆的谐振区域，对石英晶圆的另一侧的谐振区域执行刻蚀可以在石英晶圆的另一侧形成反高台结构，以及移除第二掩膜。
22、根据21所述的方法，其中：
在石英晶圆的另一侧设置第二掩膜之前，还包括步骤：对石英晶圆的另一侧整体执行减薄工艺。
23、根据21所述的方法，其中，提供第一封装基板或第二封装基板的步骤包括：
在基底的一侧设置有导电盲孔，所述导电盲孔适于与对应电极的电极引出部电连接；以及
在基板的另一侧设置第三掩膜，对第三掩膜图案化以露出对应于所述导电盲孔的位置，对第一封装基板刻蚀以露出导电盲孔，移除第三掩膜，在第一封装基板的另一侧设置导电通孔，所述导电通孔与所述导电盲孔电连接；或者
在基底的另一侧执行减薄工艺以露出导电盲孔，在基底的另一侧设置导电通孔，所述导电通孔与所述导电盲孔电连接。
24、根据14-23中任一项所述的方法，其中，
第一封装基板设置有第一封装基板导电通孔，所述第一封装基板导电通孔与第一电极的电极引出部电连接，第二封装基板设置有第二封装基板导电通孔，所述第二封装基板导电通孔与第二电极的电极引出部电连接；
为结构散粒提供外连接部的步骤中，所述第一外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过第一封装基板和第二封装基板的端面而延伸到第二封装基板的远离第二电极的一侧，或者所述第二外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过第二封装基板与第一封装基板的端面而延伸到第一封装基板的远离第一电极的一侧。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (24)

  1. 一种石英谐振器，包括：
    石英压电层；
    底电极和顶电极，顶电极和底电极中的一个电极为第一电极、另一个为第二电极，所述第一电极处于压电层的一侧，所述第二电极处于压电层的另一侧；
    第一封装基板和第二封装基板，分别设置在压电层的一侧和另一侧，第一封装基板与第一电极相对，第二封装基板与第二电极相对，
    其中：
    第一电极的电极引出端包括至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧的第一外连接部，或者第二电极的电极引出端包括至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧的第二外连接部。
  2. 根据权利要求1所述的谐振器，其中：
    第一外连接部至少经由第一封装基板和第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者第二外连接部至少经由第二封装基板和第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
  3. 根据权利要求2所述的谐振器，其中：
    第一封装基板设置有第一封装基板导电通孔，所述第一封装基板导电通孔与第一电极的电极引出部电连接，第二封装基板设置有第二封装基板导电通孔，所述第二封装基板导电通孔与第二电极的电极引出部电连接；
    所述第一外连接部在第一封装基板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过第一封装基板和第二封装基板的端面而延伸到第二封装基板的远离第二电极的一侧，或者所述第二外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过第二封装基板与第一封装基板的端面而延伸到第一封装基板的远离第一电极的一侧。
  4. 根据权利要求3所述的谐振器，其中：
    所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层接合以形成三明治结构。
  5. 根据权利要求4所述的谐振器，其中：
    所述压电层为包括凸台的反高台结构，所述第一封装基板和所述第二封装基板分别在所述石英压电层的两侧与所述凸台接合以形成所述三明治结构。
  6. 根据权利要求5所述的谐振器，其中：
    所述压电层为双面反高台结构；或者
    所述压电层为单面反高台结构；或者
    所述第一封装基板和第二封装基板中面对所述凸台的一侧为平坦面；或者
    第一封装基板和/或第二封装基板面对所述凸台的一侧设置有空腔，所述谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
  7. 根据权利要求4所述的谐振器，其中：
    所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层基于金属键合层接合以形成三明治结构；
    所述谐振器还包括在金属键合层的外侧而与金属键合层分隔开的填充金属层，所述填充金属层与所述外连接部相接。
  8. 根据权利要求7所述的谐振器，其中：
    所述金属键合层与所述填充金属层间隔开的距离在2-200微米的范围内。
  9. 根据权利要求4所述的谐振器，其中：
    所述压电层为平坦结构；且
    第一封装基板和第二封装基板面对所述压电层的一侧均设置有空腔，所述谐振器的谐振区域在厚度方向上的投影落入所述空腔内。
  10. 根据权利要求9所述的谐振器，其中：
    所述谐振器为悬臂结构。
  11. 根据权利要求1-10中任一项所述的谐振器，其中：
    第一封装基板和第二封装基板均为石英基底。
  12. 根据权利要求1-11中任一项所述的谐振器，其中：
    所述压电层的尺寸小于1mm×1mm；和/或
    所述压电层的谐振区域的厚度小于40μm或者所述谐振器的基频在40MHz以上。
  13. 一种电子器件，包括根据权利要求1-12中任一项所述的石英谐振器。
  14. 一种石英谐振器的制造方法，包括步骤：
    提供石英晶圆；
    以石英晶圆形成谐振结构，包括步骤：至少利用微/纳机电系统光刻技术在石英晶圆上形成与多个石英谐振器对应的石英压电层，在石英压电层的一侧和另一侧分别设置包括第一电极的第一电极层和包括第二电极的第二电极层；
    提供第一封装基板和第二封装基板：所述第一封装基板和所述第二封装基板分别设置在所述石英压电层的两侧以形成复合结构，第一封装基板与第一电极层相对，第二封装基板与第二电极层相对；和
    分割：至少将所述复合结构切割或者裂片，以形成机械分离的多个结构散粒；
    为结构散粒提供外连接部，包括步骤：使得每个结构散粒的第一电极的电极引出端包括第一外连接部，所述第一外连接部至少经由第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者使得每个结构散粒的第二电极的电极引出端包括第二外连接部，所述第二外连接部至少经由第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
  15. 根据权利要求14所述的方法，其中：
    为结构散粒提供外连接部的步骤中，第一外连接部至少经由第一封装基板和第二封装基板的端面延伸到第二封装基板的远离第二电极的一侧，或者第二外连接部至少经由第二封装基板和第一封装基板的端面延伸到第一封装基板的远离第一电极的一侧。
  16. 根据权利要求14所述的方法，其中：
    在提供第一封装基板和第二封装基板的步骤中，所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层接合以形成的 复合结构为三明治结构。
  17. 根据权利要求14所述的方法，其中：
    为结构散粒提供外连接部的步骤包括：以金属溅射或者蒸镀的方式形成外连接部。
  18. 根据权利要求17所述的方法，其中：
    所述第一封装基板和所述第二封装基板分别在所述压电层的两侧与所述压电层以金属键合的方式接合以形成的复合结构为包括第一封装基板、压电层、第二封装基板的三明治结构；
    在提供外连接部之前，所述方法还包括步骤：在以金属键合形成的键合层的外侧设置与键合层间隔开的填充金属层；且
    在提供外连接部的步骤中，所述外连接部与所述填充金属层接触以便于在三明治结构的端面的外连接部平坦化。
  19. 根据权利要求14所述的方法，其中，以石英晶圆形成谐振结构的步骤包括：
    设置第一掩膜及图案化：在石英晶圆的两侧设置第一掩膜，以及在两侧中的一侧或两侧至少利用微/纳机电系统光刻技术对第一掩膜图案化以露出对应于谐振器的谐振区域的区域；
    一次减薄：利用湿法刻蚀和/或干法刻蚀对石英晶圆的露出的区域予以刻蚀以在石英晶圆的露出的区域所在的一侧形成反高台结构；
    移除第一掩膜；
    设置第一电极层：在形成反高台结构的石英晶圆的一侧设置第一电极层；
    测量或者二次减薄：利用光学方法在石英晶圆的另一侧测量石英晶圆的谐振区域的厚度是否达到预定厚度，以及在没有达到预定厚度的情况下在石英晶圆的另一侧对石英晶圆执行二次减薄以使得石英晶圆在谐振区域的厚度达到预定厚度；
    设置第二电极层：在执行了测量或者二次减薄步骤后的石英晶圆的另一侧设置第二电极层。
  20. 根据权利要求19所述的方法，还包括步骤：
    测量或者调频：测量设置了第二电极层的谐振区域的谐振频率，在测 得的谐振频率小于预定谐振频率的情况下，提升谐振区域的谐振频率到预定谐振频率。
  21. 根据权利要求19所述的方法，其中：
    设置第一掩膜及图案化的步骤中，在石英晶圆的两侧设置第一掩膜以及仅在石英晶圆的一侧至少利用微/纳机电系统光刻技术对第一掩膜图案化以露出对应于谐振器的谐振区域的区域；
    提供第一封装基板的步骤中，将设置了第一电极层的石英晶圆密封接合到第一封装基板的一侧；
    在设置第一电极层之后以及测量或者二次减薄之前，还包括步骤：在石英晶圆的另一侧设置第二掩膜并对其图案化以在石英晶圆的另一侧露出石英晶圆的谐振区域，对石英晶圆的另一侧的谐振区域执行刻蚀可以在石英晶圆的另一侧形成反高台结构，以及移除第二掩膜。
  22. 根据权利要求21所述的方法，其中：
    在石英晶圆的另一侧设置第二掩膜之前，还包括步骤：对石英晶圆的另一侧整体执行减薄工艺。
  23. 根据权利要求21所述的方法，其中，提供第一封装基板或第二封装基板的步骤包括：
    在基底的一侧设置有导电盲孔，所述导电盲孔适于与对应电极的电极引出部电连接；以及
    在基板的另一侧设置第三掩膜，对第三掩膜图案化以露出对应于所述导电盲孔的位置，对第一封装基板刻蚀以露出导电盲孔，移除第三掩膜，在第一封装基板的另一侧设置导电通孔，所述导电通孔与所述导电盲孔电连接；或者
    在基底的另一侧执行减薄工艺以露出导电盲孔，在基底的另一侧设置导电通孔，所述导电通孔与所述导电盲孔电连接。
  24. 根据权利要求14-23中任一项所述的方法，其中，
    第一封装基板设置有第一封装基板导电通孔，所述第一封装基板导电通孔与第一电极的电极引出部电连接，第二封装基板设置有第二封装基板导电通孔，所述第二封装基板导电通孔与第二电极的电极引出部电连接；
    为结构散粒提供外连接部的步骤中，所述第一外连接部在第一封装基 板的远离第一电极的一侧与第一封装基板导电通孔电连接且延伸过第一封装基板和第二封装基板的端面而延伸到第二封装基板的远离第二电极的一侧，或者所述第二外连接部在第二封装基板的远离第二电极的一侧与第二封装基板导电通孔电连接且延伸过第二封装基板与第一封装基板的端面而延伸到第一封装基板的远离第一电极的一侧。
PCT/CN2023/110649 2022-08-05 2023-08-02 封装基底的端面设置外连接部石英谐振器及其制造方法、电子器件 WO2024027735A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130265370A1 (en) * 2012-04-05 2013-10-10 Rohm Co., Ltd. Ink jet print head and fabrication method thereof
CN107800402A (zh) * 2016-09-01 2018-03-13 三星电机株式会社 体声波滤波器装置及制造体声波滤波器装置的方法
CN108429543A (zh) * 2017-02-14 2018-08-21 三星电机株式会社 体声波谐振器
CN209787129U (zh) * 2019-06-20 2019-12-13 杭州左蓝微电子技术有限公司 一种声波器件及一种声波器件温度控制装置
CN216531264U (zh) * 2021-12-10 2022-05-13 武汉敏声新技术有限公司 薄膜体声波谐振器及滤波器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130265370A1 (en) * 2012-04-05 2013-10-10 Rohm Co., Ltd. Ink jet print head and fabrication method thereof
CN107800402A (zh) * 2016-09-01 2018-03-13 三星电机株式会社 体声波滤波器装置及制造体声波滤波器装置的方法
CN108429543A (zh) * 2017-02-14 2018-08-21 三星电机株式会社 体声波谐振器
CN209787129U (zh) * 2019-06-20 2019-12-13 杭州左蓝微电子技术有限公司 一种声波器件及一种声波器件温度控制装置
CN216531264U (zh) * 2021-12-10 2022-05-13 武汉敏声新技术有限公司 薄膜体声波谐振器及滤波器

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