WO2024026928A1 - 半导体结构制备方法及半导体结构 - Google Patents

半导体结构制备方法及半导体结构 Download PDF

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WO2024026928A1
WO2024026928A1 PCT/CN2022/112651 CN2022112651W WO2024026928A1 WO 2024026928 A1 WO2024026928 A1 WO 2024026928A1 CN 2022112651 W CN2022112651 W CN 2022112651W WO 2024026928 A1 WO2024026928 A1 WO 2024026928A1
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gate
trench
word line
layer
along
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PCT/CN2022/112651
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English (en)
French (fr)
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王弘
李晓杰
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长鑫存储技术有限公司
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Priority to US18/152,779 priority Critical patent/US20240040766A1/en
Publication of WO2024026928A1 publication Critical patent/WO2024026928A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to semiconductor structure preparation methods and semiconductor structures.
  • the performance of the transistors connected by the word line structure in the three-dimensional stacked memory structure directly affects the overall performance of the three-dimensional stacked memory structure.
  • the number of memory cells per unit volume in the stacked memory structure continues to increase, resulting in the continuous reduction of the space occupied by the word line structure within the unit volume and the spacing between adjacent word line structures, increasing the complexity of the preparation process and reducing the performance of the prepared products. and reliability.
  • a semiconductor structure manufacturing method and a semiconductor structure are provided.
  • one aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, forming an initial stacked structure on the substrate, the initial stacked structure including a first layer stacked alternately along a first direction.
  • a dielectric layer and a target semiconductor layer, the first dielectric layer is adjacent to the substrate; forming first trench isolation structures and second trenches arranged at intervals along the second direction and extending along the third direction in the initial stacked structure
  • the isolation structure and the third trench isolation structure forming two spaced gate trenches with the bottom surface contacting the upper surface of the substrate, and the part of the target semiconductor layer located in the gate trench is exposed and suspended; forming a surrounding in the gate trench
  • adjacent gate structures along the first direction and the second direction are insulated from each other; the first direction, the second direction and the third direction are perpendicular to each other.
  • the upper surfaces of the first trench isolation structure, the second trench isolation structure and the third trench isolation structure are flush with the upper surface of the initial stacked structure; forming two intervals with the bottom surface contacting the upper surface of the substrate
  • the gate trench includes: forming a first mask layer covering the upper surface of the first trench isolation structure, the second trench isolation structure and the third trench isolation structure; patterning the first mask layer film layer, and based on the patterned first mask layer, the initial stacked structure is etched into a mask to obtain a gate trench, and the first trench isolation is located on opposite sides of the gate trench along the second direction.
  • the remainder of the structure, the remainder of the third trench isolation structure forms the first sidewall of the gate trench.
  • forming a gate structure surrounding the target semiconductor layer in the gate trench includes: trimming the portion of the target semiconductor layer located in the gate trench along the inner diameter direction of the target semiconductor layer to obtain a gate support pillar; A gate oxide layer is formed on the outer surface of the gate support pillar; a metal material layer is deposited, and the part of the metal material layer surrounding the gate oxide layer constitutes the gate metal layer; the gate oxide layer and the gate metal layer constitute the gate structure.
  • the portion of the metal material layer located on the first sidewall constitutes the second sidewall; after forming the gate structure surrounding the target semiconductor layer in the gate trench, the method includes: filling the first sidewall in the gate trench.
  • Low dielectric constant material layer, the upper surface of the first low dielectric constant material layer is flush with the upper surface of the initial stacked structure; remove the first sidewall, the second sidewall and part of the initial stacked structure, and obtain the third layer along the third side.
  • the word line auxiliary trench extends in the direction and the bottom surface contacts the upper surface of the substrate; a second low dielectric constant material layer is filled in the word line auxiliary trench, and the upper surface of the second low dielectric constant material layer is in contact with the initial stacked structure The upper surface is flush.
  • the method further includes: removing portions of the target semiconductor layer located on opposite sides of the gate trench along the second direction, and removing the second low dielectric
  • the electrical constant material layer is located between the adjacent first dielectric layers along the first direction to obtain the first word line trench; using the gate metal layer as an etching stop layer, the first low dielectric layer is etched along the second direction.
  • a constant material layer is used to obtain a second word line trench; a first word line portion is formed in the first word line trench, and a second word line portion is formed in the second word line trench.
  • the first word line part and the second word line part constitute a word line structure.
  • the method includes: removing the portion of the first dielectric layer located on opposite sides of the gate trench along the second direction to obtain a word line isolation trench; forming a third layer in the word line isolation trench. Layer of low dielectric constant material.
  • the two gate trenches are symmetrical to each other along the third direction; after forming the third low dielectric constant material layer in the word line isolation trench, the method includes: forming a bottom contact between the two gate trenches.
  • the method further includes: forming a body isolation structure between the two gate trenches with a bottom surface contacting the upper surface of the substrate; A source structure and a drain structure are formed on the target semiconductor layer located on opposite sides of the gate structure along the third direction, and the source structure is located between the gate structure and the body isolation structure.
  • the method further includes: forming a capacitor structure on the target semiconductor layer between the body isolation structure and the source structure, and forming a capacitor structure on the drain structure.
  • a bit line structure is formed on the target semiconductor layer on a side away from the capacitor structure along the third direction.
  • adjacent source structures along the third direction are symmetrical along the third direction; and/or adjacent drain structures along the third direction are symmetrical along the third direction.
  • the first word line part and the second word line part are prepared in the same process step.
  • the length of the second word line portion along the third direction is equal to the length of the gate structure along the third direction.
  • the initial stacked structure is symmetrical along the second direction with a symmetry axis of the second trench isolation structure extending along the third direction.
  • At least two of the first low-k material layer, the second low-k material layer, and the third low-k material layer are made of the same material.
  • another aspect of the present disclosure provides a semiconductor structure prepared by using the semiconductor structure preparation method in any embodiment of the present disclosure.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the subsequent formation of the gate can be controlled.
  • the horizontal word line part is such that the horizontal word line part is connected to the corresponding gate structure via the bridge word line part, as opposed to forming a multi-layered word line structure directly outside the gate structure and stacked in a direction perpendicular to the substrate surface. , at least it can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, reducing the complexity of the preparation process and increasing the performance and reliability of the prepared products. sex.
  • the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present disclosure can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. It can also control the size of the word line structure connected to the transistor gate structure, which reduces the complexity of the manufacturing process and increases the performance and reliability of the manufactured product.
  • Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 2- Figure 5a, Figure 6a, Figure 7a, Figure 8a, Figure 9a, Figure 10a, Figure 11a, Figure 12 and Figure 14 are schematic three-dimensional cross-sectional views corresponding to different steps in the semiconductor structure preparation method provided in some embodiments of the present disclosure. ;
  • Figure 5b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 5a along the direction AA';
  • Figure 5c is a schematic cross-sectional structural diagram along the AA' direction after forming the gate structure in the three-dimensional structure shown in Figure 5a in an embodiment of the present disclosure
  • Figure 6b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 6a along the direction AA';
  • Figure 7b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 7a along the direction AA';
  • Figure 8b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 8a along the direction AA';
  • Figure 9b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 9a along the direction AA';
  • Figure 10b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 10a along the direction AA';
  • Figure 11b is a schematic cross-sectional view of the three-dimensional structure shown in Figure 11a along the direction AA';
  • Figure 13 is a schematic top view of a memory cell structure provided in an embodiment of the present disclosure.
  • Figure 15 is a schematic top view of a memory cell structure provided in another embodiment of the present disclosure.
  • the oz direction can be the first direction
  • the oy direction can be the second direction
  • the ox direction can be the third direction
  • the oz direction can be the height/thickness direction.
  • first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the invention; for example, a first element, component, region, layer, doping type or section could be termed a second element, component, region, layer or section without departing from the teachings of the present invention;
  • the first doping type becomes the second doping type, and similarly, the second doping type can become the first doping type; the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “under”, “under”, “under”, “on”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “under” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the mutual insulation between the two described in the embodiment of the present disclosure includes but is not limited to the presence of one or more of insulating materials, insulating atmosphere or gaps between the two.
  • GAA Gate All Around
  • LGAA Lateral Gate All Around
  • VGAA Vertical Gate All Around
  • the channel and gate structure of LGAA are parallel to the substrate. Extending in the direction of the bottom surface makes it difficult to control the size of the gate structure and the word line structure connected to the gate structure.
  • the number of memory cells per unit volume is increased, it will be directly formed outside the gate structure parallel to the substrate.
  • the word line structure extending in the direction of the surface will inevitably reduce the volume of the word line structure and the spacing between adjacent word line structures, increase the complexity of the preparation process, and reduce the performance and reliability of the prepared product.
  • the present disclosure aims to provide a semiconductor structure preparation method and a semiconductor structure that can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, and can increase the space occupied by the word line structure and the spacing between adjacent word line structures. Controlling the size of the word line structure connected to the transistor gate structure reduces the complexity of the manufacturing process while increasing the performance and reliability of the manufactured product.
  • a semiconductor structure preparation method including the following steps:
  • Step S110 Provide a substrate, and form an initial stacked structure on the substrate.
  • the initial stacked structure includes a first dielectric layer and a target semiconductor layer stacked alternately along the first direction, and the first dielectric layer is adjacent to the substrate;
  • Step S120 Form first trench isolation structures, second trench isolation structures and third trench isolation structures that are spaced apart along the second direction and extend along the third direction in the initial stacked structure;
  • Step S130 Form two spaced gate trenches with the bottom surface contacting the upper surface of the substrate, and the part of the target semiconductor layer located in the gate trench is exposed and suspended;
  • Step S140 Form a gate structure surrounding the target semiconductor layer in the gate trench. Gate structures adjacent along the first direction and the second direction are insulated from each other; the first direction, the second direction and the third direction are mutually insulated. vertical.
  • the bottom surface contact liner is formed.
  • the two spaced gate trenches on the upper surface of the bottom expose and float the part of the target semiconductor layer located in the gate trench to form a gate structure surrounding the target semiconductor layer in the gate trench.
  • a bridge word line portion connected to the gate structure is formed, and then multiple layers of horizontal word line portions distributed at intervals are stacked in a direction perpendicular to the substrate surface, so that the horizontal word line portion is connected to the corresponding gate electrode through the bridge word line portion.
  • Structural connection compared to forming a multi-layer word line structure stacked in a direction perpendicular to the substrate surface directly outside the gate structure, this embodiment can at least reduce the number of memory cells per unit volume. Increasing the space volume occupied by the word line structure and the spacing between adjacent word line structures reduces the complexity of the preparation process and increases the performance and reliability of the prepared products.
  • Step S110 may include the following steps:
  • Step S111 Provide substrate 100;
  • Step S112 Form an initial stacked layer structure on the substrate 100.
  • the initial stacked layer structure includes the first dielectric layer 11 and the target semiconductor layer 12 alternately stacked in sequence along the first direction (such as the oz direction).
  • the first dielectric layer 11 and Substrates 100 are adjacent.
  • a first type doped well region (not shown) is formed in the substrate 100 , and the substrate can be made of semiconductor material, insulating material, conductor material or any combination thereof.
  • the substrate 100 may have a single-layer structure or a multi-layer structure.
  • the substrate 100 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an arsenic Indium oxide (InAs) substrate, indium phosphide (InP) substrate or other III/V semiconductor substrate or II/VI semiconductor substrate.
  • the substrate 100 may be a layered substrate including, for example, Si/SiGe, Si/SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore the type of substrate 100 should not limit the scope of the present disclosure.
  • An ion implantation process may be used to inject P-type ions into the substrate 100 to form a first-type doped well region (not shown).
  • the P-type ions may include but are not limited to boron (B) ions, gallium (Ga) ions, Any one or more of boron fluoride (BF2) ions and indium (In) ions.
  • the material of the first dielectric layer 11 may include but is not limited to silicon germanium (SiGe), and the material of the target semiconductor layer 12 may include but is not limited to silicon (Si); the first dielectric layer 11 made of silicon germanium can convert the silicon of the substrate 100 into The crystal lattice is completely transferred to the stacked silicon channel layer, ensuring that each silicon channel layer has the same silicon crystal lattice as the substrate 100 .
  • an etching process may be used to form in the initial stacked structure spaced apart along the second direction (for example, the oy direction) and extending along the third direction (for example, the ox direction).
  • the first trench 1311, the second trench 1321 and the third trench 1331 expose the upper surface of the substrate 100 in the first direction (eg oz direction), the second direction (for example, oy direction) and the third direction (for example, ox direction) are perpendicular to each other.
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), high concentration plasma etching (HDP), and the like.
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high concentration plasma etching
  • a deposition process is used to deposit isolation material in the first trench 1311, the second trench 1321, and the third trench 1331 to obtain the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133.
  • the bottom surface of the first trench isolation structure 131, the second trench isolation structure 132 and the third trench isolation structure 133 contacts the upper surface of the substrate 100; the first trench isolation structure 131, the second trench isolation structure 133 can be formed.
  • a chemical mechanical polishing (CMP) process is used to make the upper surface of the first trench isolation structure 131, the second trench isolation structure 132 and the third trench isolation structure 133
  • CMP chemical mechanical polishing
  • the surface is flush with the upper surface of the initial stacked structure to facilitate the subsequent formation of a flat first mask on the upper surfaces of the first trench isolation structure 131 , the second trench isolation structure 132 and the third trench isolation structure 133 layer, and etching the initial stacked structure based on the patterned first mask layer to obtain the gate trench, thereby improving the controllability of the morphology after etching the gate trench.
  • the isolation materials in the first trench isolation structure 131 , the second trench isolation structure 132 and the third trench isolation structure 133 may include one or more of polysilicon, silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • Deposition processes may include, but are not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition, and One or more processes such as Spin-on Dielectric (SOD).
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • HDP High Density Plasma
  • SOD Spin-on Dielectric
  • the initial stacked structure is symmetrical with the symmetry axis extending along the third direction (such as the ox direction) of the second trench isolation structure 132 to improve the symmetry of the semiconductor structure and reduce the process complexity. At the same time, it is convenient to monitor the structural parameters and electrical parameters of the prepared products.
  • the thickness of the target semiconductor layer 12 may be [60 nm, 100 nm], for example, the thickness of the target semiconductor layer 12 may be 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc.
  • the thickness of the first dielectric layer 11 may be [5nm, 20nm]. For example, the thickness of the first dielectric layer 11 may be 5nm, 10nm, 15nm or 20nm, etc.
  • the first dielectric layer 11 itself provides tensile stress, and each layer cannot be too thick, otherwise problems such as body tilt may easily occur; the target semiconductor layer 12 inevitably has defects during the preparation process, and increasing its thickness means increasing the probability of defect locations and / or quantity; if the thickness of the first dielectric layer 11 made of silicon germanium is too thick and has many defects, it will easily lead to a more serious grid mismatch in the top target semiconductor layer 12 .
  • step S130 the step of forming two spaced gate trenches 14 with bottom surfaces contacting the upper surface of the substrate may include the following steps:
  • Step S131 Form a first mask layer 134, which covers the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133;
  • Step S132 Pattern the first mask layer 134, and use the mask to etch the initial stacked structure based on the patterned first mask layer 134 to obtain the gate trench 14, which is located along the gate trench 14.
  • the remaining portions of the first trench isolation structure 131 and the remaining portion of the third trench isolation structure 133 on opposite sides in two directions (eg, oy direction) constitute the first sidewall 141 of the gate trench 14 .
  • a deposition process may be used to form a first mask layer covering the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133. 134;
  • the first mask layer 134 may include a single-layer structure or a multi-layer structure.
  • the first mask layer 134 includes, but is not limited to, a hard mask layer.
  • the hard mask layer is, for example, a spin-on hard mask layer (Spin-on Hardmasks, SOH for short).
  • the SOH layer may be an insulating layer of a hydrocarbon (C x H y ) system, which may include silicon hard mask materials, carbon hard mask materials, organic hard mask materials, etc.
  • SOH is an auxiliary material for forming semiconductor fine patterns. It has the characteristics of filling gaps, increasing flatness and enhancing corrosion resistance. Using this material to form a hard mask layer can make subsequent etching better.
  • the deposition process may include, but is not limited to, one or more of CVD, ALD, HDP, and SOD.
  • the initial stacked structure can be etched using a dry etching process and a wet etching process based on the patterned first mask layer 134 as a mask.
  • the gate trench 14 the part of the target semiconductor layer 12 located in the gate trench is exposed and suspended; the first trench isolation structure is located on opposite sides of the gate trench 14 along the second direction (for example, the oy direction).
  • the remaining portion of 131 and the remaining portion of the third trench isolation structure 133 form the first sidewall 141 of the gate trench 14 to protect the sidewall of the gate trench 14 .
  • the exposed and suspended portion of the target semiconductor layer 12 located in the gate trench 14 can be trimmed and changed, so that the size of the subsequently formed gate structure can be controlled.
  • step S140 forming the gate structure 20 surrounding the target semiconductor layer 12 in the gate trench 14 may include the following steps:
  • Step S141 Trim the portion of the target semiconductor layer 12 located inside the gate trench 14 along the inner diameter direction of the target semiconductor layer 12 to obtain the gate support pillar 143;
  • Step S142 Form the gate oxide layer 21 on the outer surface of the gate support pillar 143;
  • Step S143 Deposit a metal material layer.
  • the portion of the metal material layer surrounding the gate oxide layer 21 forms the gate metal layer 22.
  • the gate oxide layer 21 and the gate metal layer 22 form the gate structure 20.
  • an etching process can be used to trim the portion of the target semiconductor layer 12 located within the gate trench 14 along the inner diameter direction of the target semiconductor layer 12.
  • the etching time can control the thickness of the target semiconductor layer 12 to be removed, thereby controlling the thickness and length of the gate support pillar 143 along the oy direction to control the subsequent formation of the gate oxide layer 21 or gate metal on the outer surface of the gate support pillar 143
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • step S142 an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (Rapid Thermal Oxidation, RTO) can be used. ) and the like to form the gate oxide layer 21 on the outer surface of the gate support pillar 143 in the gate trench 14 .
  • the gate oxide layer 21 may be formed using a high-k dielectric constant material.
  • the material of the gate oxide layer 21 may include, but is not limited to, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), etc. any one or more.
  • a deposition process can be used to form a metal material layer.
  • the portion of the metal material layer located on the first sidewall 141 constitutes the second sidewall 142; the metal material layer surrounds the portion of the gate oxide layer 21.
  • the gate metal layer 22 is formed, and the gate oxide layer 21 and the gate metal layer 22 form the gate structure 20 .
  • the deposition process may include, but is not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition, and Any one or more of processes such as spin-on dielectric (SOD).
  • CVD Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • HDP High Density Plasma
  • SOD spin-on dielectric
  • the metal material layer may include, but is not limited to, any one or more of titanium nitride (TiN), titanium (Titanium, Ti), tungsten silicide (Tungsten silicide, Si 2 W), tungsten (Tungsten, W), etc. . Since the thickness of the target semiconductor layer 12 to be removed during trimming of the target semiconductor layer 12 can be controlled, the thickness and the length of the gate support pillar 143 along the oy direction can be controlled, so that the subsequent gate formation on the outer surface of the gate support pillar 143 can be controlled. The thickness of the oxide layer 21 or the gate metal layer 22 and the length along the oy direction control the size of the gate structure 20 being prepared.
  • step S140 after forming the gate structure 20 surrounding the target semiconductor layer 12 in the gate trench 14, the following steps may be included:
  • Step S151 Fill the first low dielectric constant material layer 144 in the gate trench 14, and the upper surface of the first low dielectric constant material layer 144 is flush with the upper surface of the initial stacked structure;
  • Step S152 Remove the first sidewall 141, the second sidewall 142 and part of the initial stacked structure to obtain the word line auxiliary trench 15 extending along the third direction and with the bottom surface contacting the upper surface of the substrate 100;
  • Step S153 Fill the word line auxiliary trench 15 with the second low dielectric constant material layer 16, and the upper surface of the second low dielectric constant material layer 16 is flush with the upper surface of the initial stacked structure.
  • step S151 an in-situ steam generation process (ISSG), an atomic layer deposition process, a plasma vapor deposition process, and a rapid thermal oxidation process (Rapid Thermal Oxidation Process) can be used.
  • Oxidation, RTO), etc. fill the first low dielectric constant material layer 144 in the gate trench 14.
  • a wet etching process, a dry etching process, or chemical mechanical polishing can be used.
  • the upper surface of the first low dielectric constant material layer 144 is planarized along the thickness direction (such as the oz direction) in any one or more of the process and the push etching process, so that the first low dielectric constant material layer 144 is planarized.
  • the upper surface of layer 144 is flush with the upper surface of the initial stacked structure to protect the gate structure 20 during subsequent etching and formation of word line trenches.
  • step S152 an etching process can be used to remove the first sidewall 141, the second sidewall 142 and part of the initial stacked structure to obtain an extension along the third direction (such as the ox direction). And the bottom surface contacts the word line auxiliary trench 15 on the upper surface of the substrate 100, so that the word line auxiliary trench 15 can subsequently form a bridge word line portion connected to the gate structure, and then a bridge word line portion perpendicular to the upper surface of the substrate 100 can be formed.
  • a plurality of horizontal word line portions are stacked at intervals in the direction, so that the horizontal word line portion is connected to the corresponding gate structure through the bridge word line portion.
  • the multi-layered word line structure is stacked in the direction.
  • This embodiment can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, and reduce the
  • the complexity of the preparation process also increases the performance and reliability of the prepared products.
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • a deposition process can be used to fill the second low dielectric constant material layer 16 in the word line auxiliary trench 15, and then a wet etching process or a dry etching process can be used.
  • the upper surface of the second low dielectric constant material layer 16 is planarized along the thickness direction (such as the oz direction) by any one or more of an etching process, a chemical mechanical polishing process, a push etching process, etc., so that the second low dielectric constant material layer 16 is planarized.
  • the upper surface of the two low dielectric constant material layers 16 is flush with the upper surface of the initial stacked structure, so as to protect the gate structure 20 during subsequent etching and formation of word line trenches.
  • the deposition process may include but is not limited to any one or more of CVD, ALD, HDP, SOD and other processes.
  • step S140 after forming the gate structure 20 surrounding the target semiconductor layer 12 in the gate trench 14, the following steps may be included:
  • Step S161 Remove the portion of the target semiconductor layer 12 located on opposite sides of the gate trench 14 along the second direction, and remove the portion of the second low dielectric constant material layer 16 located between the adjacent first dielectric layers 11 along the first direction. part to obtain the first word line trench 41;
  • Step S162 Using the gate metal layer 22 as an etching stop layer, etch the first low dielectric constant material layer 144 along the second direction to obtain a second word line trench (not shown);
  • Step S163 Form the first word line portion 31 in the first word line portion trench 41, and form the second word line portion 32 in the second word line portion trench (not shown).
  • the first word line portion 31 , the second word line portion 32 constitutes the word line structure 30 .
  • an etching process may be used to remove the portion of the target semiconductor layer 12 located on opposite sides of the gate trench 14 along the second direction (for example, the oy direction), and remove the second The low dielectric constant material layer 16 is located in a portion between adjacent first dielectric layers 11 along the first direction (eg, oz direction) to form the first word line trench 41 .
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • the length of the second word line portion 32 along the third direction is equal to the length of the gate structure 20 along the third direction (eg, ox direction), so as to reduce the length of the word line structure 30.
  • the connection impedance to the gate structure 20 is equal to the length of the gate structure 20 along the third direction (eg, ox direction), so as to reduce the length of the word line structure 30.
  • the gate metal layer 22 can be used as an etching stop layer, and an etching process can be used to etch the first low dielectric constant material layer 144 along the second direction to obtain the second Word line trench.
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • a deposition process may be used to form the first word line part 31 in the first word line part trench 41, and the second word line part 32 may be formed in the second word line part trench (not shown).
  • the word line part 31 and the second word line part 32 constitute the word line structure 30 .
  • the first word line part 31 and the second word line part 32 may be prepared and formed in the same process step, or may be prepared and formed in different process steps.
  • the deposition process may include but is not limited to any one or more of CVD, ALD, HDP, SOD and other processes.
  • the material of the word line structure 30 may include, but is not limited to, any one or more of rubidium, cobalt, nickel, titanium, tungsten, tantalum, tantalum titanium, tungsten nitride, copper, aluminum, and the like.
  • step S163 After forming the word line structure 30 in step S163, the following steps are also included:
  • Step S171 Remove the portion of the first dielectric layer 11 located on opposite sides of the gate trench 14 along the second direction (such as the oy direction) to obtain a word line isolation trench (not shown);
  • Step S172 Form a third low-k material layer 17 in the word line isolation trench.
  • an etching process may be used to remove the portion of the first dielectric layer 11 located on opposite sides of the gate trench 14 along the second direction to obtain a word line isolation trench (not yet shown). icon).
  • the etching process may include, but is not limited to, dry etching process and/or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • a deposition process may be used to form a third low-dielectric constant material layer 17 in the word line isolation trench, so that adjacent word line structures 30 in the oz direction are insulated from each other.
  • the deposition process may include but is not limited to any one or more of CVD, ALD, HDP, SOD and other processes. At least two of the first low dielectric constant material layer 144 , the second low dielectric constant material layer 16 and the third low dielectric constant material layer 17 are made of the same material.
  • the low dielectric constant material layer may include, but is not limited to, any one or more of silicon oxide, SiLK, MSQ, porous SiLK, porous MSQ, and the like.
  • this embodiment can at least increase the number of word lines without reducing the number of memory cells per unit volume.
  • the space volume occupied by the structure and the spacing between adjacent word line structures reduce the complexity of the preparation process and increase the performance and reliability of the prepared products.
  • Two gate trenches 14 can be set to be symmetrical with each other along a third direction (such as the ox direction); in step S172, a third low dielectric constant material is formed in the word line isolation trench.
  • a third direction such as the ox direction
  • Step S181 Form a body isolation structure 18 whose bottom surface contacts the upper surface of the substrate 100 between the two gate trenches 14;
  • Step S182 Form the source structure 191 between the body isolation structure 18 and the adjacent gate structure 20, and form a drain on the side of the gate structure 20 away from the body isolation structure 18 along the third direction (such as the ox direction). Structure192.
  • an etching process may be used to etch the initial stacked structure to obtain a body isolation trench (not shown).
  • the etching process may include but is not limited to a dry etching process and/or Or wet etching process.
  • the dry etching process may include but is not limited to any one or more of RIE, ICP, HDP, etc.
  • isolation material is deposited in the body isolation trench to obtain the body isolation structure 18 .
  • the deposition process may include but is not limited to any one or more of CVD, ALD, HDP, SOD and other processes.
  • the isolation material may include any one or more of silicon nitride, silicon oxide, silicon oxynitride, polysilicon, and the like.
  • the position of the body isolation structure 18 can be set so that the semiconductor structure is symmetrical with the symmetry axis m1 extending along the oy direction of the body isolation structure 18 , and adjacent gate structures along the oy direction can also be set. 20 is symmetrical about the axis of symmetry m2.
  • the source structure 191 may be formed on the target semiconductor layer between the body isolation structure 18 and the adjacent gate structure 20, and the source structure 191 may be formed on the gate structure 20 along the third direction ( For example, in the ox direction), a drain structure 192 is formed on the target semiconductor layer on a side away from the body isolation structure 18 to obtain the memory cell structure 200.
  • the adjacent source structures 191 along the ox direction are symmetrical about the symmetry axis m1
  • the adjacent drain structures 192 along the ox direction are symmetrical about the symmetry axis m1.
  • multiple body structures 300 are obtained that are spaced apart along the oz direction.
  • the body structure 300 includes four centrally symmetrical memory cell structures 200 . Since the exposed and suspended portion of the target semiconductor layer located in the gate trench can be trimmed and changed before forming the gate structure, the size of the subsequently formed gate structure can be controlled; since the first trench isolation structure and the third trench isolation structure can be utilized The trench isolation structure forms a bridge word line portion connected to the gate structure, and then multiple layers of horizontal word line portions distributed at intervals are stacked in a direction perpendicular to the substrate surface, so that the horizontal word line portion is connected to the bridge word line portion via the bridge word line portion. Corresponding gate structures are connected.
  • this embodiment can at least reduce the number of memory cells per unit volume without reducing the number of memory cells.
  • the spatial volume occupied by the word line structure and the spacing between adjacent word line structures are increased, which reduces the complexity of the preparation process and increases the performance and reliability of the prepared product.
  • the target semiconductor layer extends along the ox direction, and a first type of doping, such as P-type light doping, may be used.
  • the channel region conductive layer (not shown) is located between the source structure 191 and the drain structure 192.
  • the first type of doping such as P-type heavy doping
  • the drain structure 192 may use a second type of doping, such as N-type heavy doping, to form the drain region of the transistor.
  • the source structure 191 may be doped with a second type, such as N-type heavy doping, to form the source region of the transistor.
  • P-type impurity ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF 2 ) ions, and indium (In) ions;
  • N-type impurity ions may include But it is not limited to any one or more of phosphorus (P) ions, arsenic (As) ions, antimony (Sb) ions, etc.
  • step S172 after forming the third low-k material layer 17 in the word line isolation trench, the following steps may be included:
  • Step S181 Form a body isolation structure 18 whose bottom surface contacts the upper surface of the substrate 100 between the two gate trenches 14;
  • Step S183 Form the source structure 191 and the drain structure 192 on the target semiconductor layer located on opposite sides of the gate structure 20 along the third direction (such as the ox direction).
  • the source structure 191 is located between the gate structure 20 and the body isolation structure. Between 18.
  • the body structure 300 includes a memory cell structure 200 symmetrical about the symmetry axis m2.
  • the target semiconductor layer in the unit structure 200 extends along the ox direction, and may be doped with a first type, such as P-type light doping.
  • the channel region conductive layer (not shown) is located between the source structure 191 and the drain structure 192.
  • the first type of doping such as P-type heavy doping, can be used to form the channel region of the transistor; the drain structure 192 may use a second type of doping, such as N-type heavy doping, to form the drain region of the transistor.
  • the source structure 191 may be doped with a second type, such as N-type heavy doping, to form the source region of the transistor.
  • P-type impurity ions may include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF 2 ) ions, and indium (In) ions;
  • N-type impurity ions may include But it is not limited to any one or more of phosphorus (P) ions, arsenic (As) ions, antimony (Sb) ions, etc.
  • steps in the flowchart of FIG. 1 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 1 may include multiple steps or stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these steps or stages is also It does not necessarily need to be performed sequentially, but may be performed in turn or alternately with other steps or at least part of steps or stages in other steps.
  • the semiconductor structure includes a substrate 100 and an initial stacked structure located on the substrate 100.
  • the initial stacked structure includes sequentially along the first direction (such as the oz direction).
  • the first dielectric layer 11 and the target semiconductor layer 12 are alternately stacked, and the first dielectric layer 11 is adjacent to the substrate 100; the initial stacked structure is formed with spaced layers arranged along the second direction (such as the oy direction) and along the third direction.
  • the first trench isolation structure 131, the second trench isolation structure 132 and the third trench isolation structure 133 extending in the direction (such as the ox direction), the first trench isolation structure 131, the second trench isolation structure 132 and the third trench isolation structure 133 extend in the ox direction.
  • the bottom surface of the trench isolation structure 133 contacts the upper surface of the substrate 100; two spaced gate trenches 14 with the bottom surface contacting the upper surface of the substrate are formed in the initial stacked structure, and the target semiconductor layer 12 is located in the gate trenches 14 Part of it is exposed and suspended; a gate structure 20 is arranged around the outside of the target semiconductor layer 12 in the gate trench 14, between adjacent gate structures 20 along the first direction (such as the oz direction) and the second direction (such as the oy direction).
  • the trench isolation structure forms a bridge word line portion connected to the gate structure, and then multiple layers of horizontal word line portions distributed at intervals are stacked in a direction perpendicular to the substrate surface, so that the horizontal word line portion is connected to the bridge word line portion via the bridge word line portion. Corresponding gate structures are connected.
  • this embodiment can at least reduce the number of memory cells per unit volume without reducing the number of memory cells.
  • the spatial volume occupied by the word line structure and the spacing between adjacent word line structures are increased, which reduces the complexity of the preparation process and increases the performance and reliability of the prepared product.

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Abstract

本公开涉及一种半导体结构制备方法及半导体结构，包括：提供衬底，于衬底上形成初始叠层结构，初始叠层结构包括沿第一方向依次交替叠置的第一介质层、目标半导体层，第一介质层与衬底相邻；于初始叠层结构内形成沿第二方向间隔排布且沿第三方向延伸的第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构；形成底面接触衬底上表面的两个间隔的栅极沟槽，目标半导体层位于栅极沟槽内的部分裸露并悬空；于栅极沟槽内形成环绕目标半导体层的栅极结构。

Description

半导体结构制备方法及半导体结构
相关申请的交叉引用
本公开要求于2022年08月01日提交中国专利局、申请号为202210918006.1、申请名称为“半导体结构制备方法及半导体结构”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路设计及制造技术领域，特别是涉及半导体结构制备方法及半导体结构。
背景技术
随着集成电路制造工艺的不断发展，市场对半导体存储产品的存储能力及存储性能提出了更高的要求。如何在确保半导体存储产品的存储性能的前提下，提高半导体存储产品的存储能力成为研发者不断追求的目标，因此，立体堆叠型存储结构应运而生。
立体堆叠型存储结构中字线结构连接的晶体管的性能直接影响立体堆叠型存储结构的整体性能，传统的立体堆叠型存储结构的制备方法中，很难改变该晶体管的栅极尺寸，并且随着立体堆叠型存储结构中单位体积内存储单元数量不断增加，导致单位体积内字线结构所占空间体积及相邻字线结构的间距不断减少，增加了制备工艺复杂度的同时降低了制备产品的性能及可靠性。
发明内容
根据本公开的各种实施例，提供一种半导体结构制备方法及半导体结构。
根据一些实施例，本公开的一方面提供了一种半导体结构制备方法，包括：提供衬底，于衬底上形成初始叠层结构，初始叠层结构包括沿第一方向依次交替叠置的第一介质层、目标半导体层，第一介质层与衬底相邻；于初始叠层结构内形成沿第二方向间隔排布且沿第三方向延伸的第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构；形成底面接触衬底上表面的两个间隔的栅极沟槽，目标半导体层位于栅极沟槽内的部分裸露并悬空；于栅极沟槽内形成环绕目标半导体层的栅极结构，沿第一方向、第二方向相邻的栅极结构之间相互绝缘；第一方向、第二方向及第三方向相互垂直。
根据一些实施例，第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构的上表面与初始叠层结构的上表面齐平；形成底面接触衬底上表面的两个间隔的栅极沟槽，包括：形成第一掩膜层，第一掩膜层覆盖第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构的上表面；图形化第一掩膜层，并基于图形化后第一掩膜层为掩膜版刻蚀初始叠层结构，以得到栅极沟槽，位于栅极沟槽沿第二方向的相对两侧的第一沟槽隔离结构的剩余部分、第三沟槽隔离结构的剩余部分构成栅极沟槽的第一侧壁。
根据一些实施例，于栅极沟槽内形成环绕目标半导体层的栅极结构，包括：沿目标半导体层的内径方向修剪目标半导体层位于栅极沟槽内的部分，得到栅极支撑柱；于栅极支撑柱的外表面上形成栅氧化层；沉积金属材料层，金属材料层环绕栅氧化层的部分构成栅金属层，栅氧化层、栅金属层构成栅极结构。
根据一些实施例，金属材料层位于第一侧壁上的部分构成第二侧壁；于栅极沟槽内形成环绕目标半导体层的栅极结构之后，包括：于栅极沟槽内填充第一低介电常数材料层，第一低介电常数材料层的上表面与初始叠层结构的上表面齐平；去除第一侧壁、第二侧壁及部分初始叠层结构，得到沿第三方向延伸且底面接触衬底上表面的字线辅助沟槽；于字线辅助沟槽内填充第二低介电常数材料层，第二低介电常数材料层的上表面与初始叠层结构的上表面齐平。
根据一些实施例，于栅极沟槽内形成环绕目标半导体层的栅极结构之后，还包括：去除目标半导体层沿第二方向位于栅极沟槽相对两侧的部分，并去除第二低介电常数材料层位于沿第一方向相邻第一介质层之间的部分，得到第一字线部沟槽；以栅金属层为刻蚀停止层，沿第二方向刻蚀第一低介电常数材料层，得到第二字线部沟槽；于第一字线部沟槽内形成第一字线部，并于第二字线部沟槽内形成第二字线部，第一字线部、第二字线部构成字线结构。
根据一些实施例，形成字线结构之后，包括：去除第一介质层沿第二方向位于栅极沟槽相对两侧的部分，得到字线隔离沟槽；于字线隔离沟槽内形成第三低介电常数材料层。
根据一些实施例，两个栅极沟槽沿第三方向相互对称；于字线隔离沟槽内形成第三低介电常数材料层之后，包括：于两个栅极沟槽之间形成底面接触所述衬底的上表面的本体隔离结构；于本体隔离结构与相邻的栅极结构之间形成源极结构，及于栅极结构沿第三方向远离本体隔离结构的一侧形成漏极结构。
根据一些实施例，于字线隔离沟槽内形成第三低介电常数材料层之后，还包括：于两个栅极沟槽之间形成底面接触所述衬底的上表面的本体隔离结构；于位于栅极结构沿第三方向相对两侧的目标半导体层上形成源极结构、漏极结构，源极结构位于栅极结构与本体隔离结构之间。
根据一些实施例，于字线隔离沟槽内形成第三低介电常数材料层之后，还包括：于本体隔离结构与源极结构之间的目标半导体层上形成电容结构，及于漏极结构沿第三方向远离电容结构一侧的目标半导体层上形成位线结构。
根据一些实施例，沿第三方向相邻源极结构沿第三方向对称；及/或沿第三方向相邻漏极结构沿第三方向对称。
根据一些实施例，第一字线部、第二字线部在同一工艺步骤中制备而成。
根据一些实施例，第二字线部沿第三方向的长度与栅极结构沿第三方向的长度相等。
根据一些实施例，初始叠层结构以第二沟槽隔离结构的沿第三方向延伸的对称轴沿第二方向对称。
根据一些实施例，第一低介电常数材料层、第二低介电常数材料层及第三低介电常数材料层中至少两个的材料相同。
根据一些实施例，本公开的另一方面提供了一种半导体结构，采用本公开任一实施例中半导体结构制备方法制备而成。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的半导体结构制备方法及半导体结构中，由于可以在形成栅极结构之前，修剪并改变目标半导体层位于栅极沟槽内裸露并悬空的部分，从而可以控制后续形成栅极结构的尺寸；由于可以利用第一沟槽隔离结构、第三沟槽隔离结构形成与栅极结构连接的桥梁字线部，后续再在垂直于衬底表面的方向上叠置多层间隔分布的水平字线部，使得水平字线部经由桥梁字线部与对应的栅极结构连接，相对于直接在栅极结构的外侧形成在垂直于衬底表面的方向上叠置的多层字线结构，至少能够在不减小单位体积内存储单元数量的情况下，增加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
综上，本公开实施例提供的半导体结构制备方法及半导体结构，至少能够在确保单位体积内存储单元数量不减少的情况下，增加字线结构所占空间体积及相邻字线结构的间距，并能够控制字线结构连接晶体管栅极结构的尺寸，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例中提供的一种半导体结构制备方法的流程示意图；
图2-图5a、图6a、图7a、图8a、图9a、图10a、图11a、图12及图14为本公开一些实施例中提供的半导体结构制备方法中不同步骤对应的立体截面示意图；
图5b为图5a所示立体结构沿AA'方向所得截面结构示意图；
图5c为本公开一实施例中在图5a所示立体结构中形成栅极结构后沿AA'方向所得截面结构示意图；
图6b为图6a所示立体结构沿AA'方向所得截面结构示意图；
图7b为图7a所示立体结构沿AA'方向所得截面结构示意图；
图8b为图8a所示立体结构沿AA'方向所得截面结构示意图；
图9b为图9a所示立体结构沿AA'方向所得截面结构示意图；
图10b为图10a所示立体结构沿AA'方向所得截面结构示意图；
图11b为图11a所示立体结构沿AA'方向所得截面结构示意图；
图13为本公开一实施例中提供的一种存储单元结构的俯视图示意图；
图15为本公开另一实施例中提供的一种存储单元结构的俯视图示意图；
其中，oz方向可以为第一方向，oy方向可以为第二方向，ox方向可以为第三方向，oz方向可以为高度/厚度方向。
具体实施方式
为了便于理解本公开，下面将参阅相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它 取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本公开的基本构想，虽图示中仅显示与本公开中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
请注意，本公开实施例中所述的两者之间相互绝缘包括但不仅限于两者之间存在绝缘材料、绝缘气息或间隙等中一种或多种。
为了更好地适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面晶体管向具有更高功效的三维立体式的晶体管过渡，如全包围栅极(Gate All Around，GAA)晶体管。全包围栅极晶体管中，栅极从四周包围沟道所在的区域，与平面晶体管相比，全包围栅极晶体管的栅极对沟道的控制能力更强，能够更好的抑制短沟道效应。全包围栅极晶体管包括横向全包围栅极(Lateral Gate All Around，LGAA)晶体管和垂直全包围栅极(Vertical Gate All Around，VGAA)晶体管，其中，LGAA的沟道及栅极结构在平行于衬底表面的方向上延伸，导致栅极结构及与栅极结构连接的字线结构的尺寸很难控制，并且，若增加单位体积内存储单元数量，直接在栅极结构外侧形成在平行于衬底表面的方向上延伸的字线结构，不可避免地会减小字线结构的体积及相邻字线结构的间距，增加了制备工艺复杂度的同时降低了制备产品的性能及可靠性。
本公开旨在提供一种半导体结构制备方法及半导体结构，至少能够在确保单位体积内存储单元数量不减少的情况下，增加字线结构所占空间体积及相邻字线结构的间距，并能够控制字线结构连接晶体管栅极结构的尺寸，降低制备工艺复杂度的同时增加制备产品的性能及可靠性。
请参考图1，在本公开的一些实施例中，提供了一种半导体结构制备方法，包括如下步骤：
步骤S110：提供衬底，于衬底上形成初始叠层结构，初始叠层结构包括沿第一方向依次交替叠置的第一介质层、目标半导体层，第一介质层与衬底相邻；
步骤S120：于初始叠层结构内形成沿第二方向间隔排布且沿第三方向延伸的第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构；
步骤S130：形成底面接触衬底上表面的两个间隔的栅极沟槽，目标半导体层位于栅极沟槽内的部分裸露并悬空；
步骤S140：于栅极沟槽内形成环绕目标半导体层的栅极结构，沿第一方向、第二方向相邻的栅极结构之间相互绝缘；第一方向、第二方向及第三方向相互垂直。
具体地，在初始叠层结构内形成沿第二方向间隔排布且沿第三方向延伸的第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构之后，形成底面接触衬底上表面的两个间隔的栅极沟槽，使得目标半导体层位于栅极沟槽内的部分裸露并悬空，以在栅极沟槽内形成环绕目标半导体层的栅极结构，由于可以在形成栅极结构之前，修剪并改变目标半导体层位于栅极沟槽内裸露并悬空的部分，从而可以控制后续形成栅极结构的尺寸；由于可以利用第一沟槽隔离结构、第三沟槽隔离结构形成与栅极结构连接的桥梁字线部，后续再在垂直于衬底表面的方向上叠置多层间隔分布的水平字线部，使得水平字线部经由桥梁字线部与对应的栅极结构连接，相对于直接在栅极结构的外侧形成在垂直于衬底表面的方向上叠置的多层字线结构，本实施例至少能够在不减小单位体积内存储单元数量的情况下，增 加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
作为示例，请参考图1-图2，步骤S110中可以包括如下步骤：
步骤S111：提供衬底100；
步骤S112：于衬底100上形成初始叠层结构，初始叠层结构包括沿第一方向(例如oz方向)依次交替叠置的第一介质层11、目标半导体层12，第一介质层11与衬底100相邻。
示例地，衬底100内形成有第一类型掺杂阱区(未图示)，衬底可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底100可以为单层结构，也可以为多层结构。例如，衬底100可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底100可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。因此衬底100的类型不应限制本公开的保护范围。可以采用离子注入工艺向衬底100内注入P型离子，以形成第一类型掺杂阱区(未图示)，P型离子可以包括但不限于硼(B)离子、镓(Ga)离子、氟化硼(BF2)离子及铟(In)离子等中任一种或多种。第一介质层11的材料可以包括但不限于硅锗(SiGe)，目标半导体层12的材料可以包括但不限于硅(Si)；硅锗材质的第一介质层11能够将衬底100的硅晶格完整地传递到层叠的硅材质的沟道层中，保证每层硅材质的沟道层都能够与衬底100具有相同的硅晶格。
作为示例，请参考图1-图4，步骤S120中可以采用刻蚀工艺于初始叠层结构内形成沿第二方向(例如oy方向)间隔排布且沿第三方向(例如ox方向)延伸的第一沟槽1311、第二沟槽1321及第三沟槽1331，第一沟槽1311、第二沟槽1321及第三沟槽1331暴露出衬底100的上表面，第一方向(例如oz方向)、第二方向(例如oy方向)与第三方向(例如ox方向)相互垂直。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于反应离子刻蚀(RIE)、感应耦合等离子体刻蚀(ICP)及高浓度等离子体刻蚀(HDP)等中一种或多种。再采用沉积工艺于第一沟槽1311、第二沟槽1321及第三沟槽1331内沉积隔离材料得到第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133，第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的底面接触衬底100的上表面；可以在形成第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133之后，采用化学机械研磨工艺(Chemical Mechanical Polish，CMP)使得第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的上表面与初始叠层结构的上表面齐平，以便于后续在第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的上表面形成表面平整的第一掩膜层，并基于图形化后第一掩膜层刻蚀初始叠层结构得到栅极沟槽，提高栅极沟槽刻蚀后形貌的可控性。第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133内的隔离材料可以包括多晶硅、氮化硅、氧化硅及氮氧化硅等中一种或多种。沉积工艺可以包括但不限于化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强沉积工艺及旋涂介质层(Spin-on Dielectric，SOD)等工艺中的一种或多种。
作为示例，请继续参考图4，初始叠层结构以第二沟槽隔离结构132的沿第三方向(例如ox方向)延伸的对称轴对称，以提高制备半导体结构的对称性，降低工艺复杂度的同时，便于监控制备产品的结构参数与电性参数。
作为示例，请继续参考图4，目标半导体层12的厚度可以为[60nm，100nm]，例如目标半导体层12的厚度可以为60nm、70nm、80nm、90nm或100nm等等。第一介质层11的 厚度可以为[5nm，20nm]，例如第一介质层11的厚度可以为5nm、10nm、15nm或20nm等等。第一介质层11本身提供拉应力，每层不能太厚，否则容易产生本体倾斜等问题；目标半导体层12在制备的过程中不可避免存在缺陷，增加其厚度意味着增加缺陷位置出现的概率及/或数量；如果硅锗材质的第一介质层11厚度太厚且缺陷较多，容易导致顶部的目标半导体层12格失配越严重。
作为示例，请参考图1、图4-图5b，步骤S130中形成底面接触衬底上表面的两个间隔的栅极沟槽14的步骤可以包括如下步骤：
步骤S131：形成第一掩膜层134，第一掩膜层134覆盖第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的上表面；
步骤S132：图形化第一掩膜层134，并基于图形化后第一掩膜层134为掩膜版刻蚀初始叠层结构，以得到栅极沟槽14，位于栅极沟槽14沿第二方向(例如oy方向)的相对两侧的第一沟槽隔离结构131的剩余部分、第三沟槽隔离结构133的剩余部分构成栅极沟槽14的第一侧壁141。
作为示例，请继续参考图4，步骤S131中可以采用沉积工艺形成覆盖第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的上表面的第一掩膜层134；第一掩膜层134可以包括单层结构或多层结构。第一掩膜层134包括但不仅限于硬掩膜层。硬掩膜层例如为旋涂硬掩膜层(Spin-on Hardmasks，简称SOH)。SOH层可以是碳氢(C xH y)体系的绝缘层，其可包括硅硬掩膜材料、碳硬掩膜材料、以及有机硬掩膜材料等。SOH是形成半导体微细图形的辅助材料，其具有填补缺口、增加平坦度及增强耐腐蚀性等特性。采用这种材料形成硬掩膜层，可以使后续的刻蚀效果较好。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺中的一种或多种。
作为示例，请继续参考图5a-图5b，步骤S132中可以基于图形化后第一掩膜层134为掩膜版并采用干法刻蚀工艺及湿法刻蚀工艺刻蚀初始叠层结构，以得到栅极沟槽14，目标半导体层12位于栅极沟槽内的部分裸露并悬空；位于栅极沟槽14沿第二方向(例如oy方向)的相对两侧的第一沟槽隔离结构131的剩余部分、第三沟槽隔离结构133的剩余部分构成栅极沟槽14的第一侧壁141，以保护栅极沟槽14的侧壁。可以在形成栅极结构之前，修剪并改变目标半导体层12位于栅极沟槽14内裸露并悬空的部分，从而可以控制后续形成栅极结构的尺寸。
作为示例，请参考图1及图5c，步骤S140中于栅极沟槽14内形成环绕目标半导体层12的栅极结构20可以包括如下步骤：
步骤S141：沿目标半导体层12的内径方向修剪目标半导体层12位于栅极沟槽14内部分，得到栅极支撑柱143；
步骤S142：于栅极支撑柱143的外表面上形成栅氧化层21；
步骤S143：沉积金属材料层，金属材料层环绕栅氧化层21的部分构成栅金属层22，栅氧化层21、栅金属层22构成栅极结构20。
作为示例，请继续参考图5c，步骤S141中可以采用刻蚀工艺沿目标半导体层12的内径方向修剪目标半导体层12位于栅极沟槽14内部分，通过控制刻蚀工艺的刻蚀速率与刻蚀时间，可以控制去除目标半导体层12的厚度，从而控制栅极支撑柱143的厚度及沿oy方向的长度，以控制后续在栅极支撑柱143的外表面上形成栅氧化层21或栅金属层22的厚度及沿oy方向的长度。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。
作为示例，请继续参考图5c，步骤S142中可以采用原位水气生成工艺(In-Situ Steam Generation，ISSG)、原子层沉积工艺、等离子蒸汽沉积工艺及快速热氧化工艺(Rapid Thermal Oxidation，RTO)等中的任一种或几种于栅极沟槽14内栅极支撑柱143的外表面形成栅氧化层21。栅氧化层21可以采用高k介电常数材料形成。例如，栅氧化层21的 材料可以包括但不限于氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、氧化锆(ZrO 2)、氧化钽(Ta 2O 5)、氧化钛(TiO 2)及锶钛氧化物(SrTiO 3)等中任一种或几种。
作为示例，请继续参考图5c，步骤S143中可以采用沉积工艺形成金属材料层，金属材料层位于第一侧壁141上的部分构成第二侧壁142；金属材料层环绕栅氧化层21的部分构成栅金属层22，栅氧化层21、栅金属层22构成栅极结构20。沉积工艺可以包括但不限于化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)、高密度等离子沉积(High Density Plasma，HDP)工艺、等离子体增强沉积工艺及旋涂介质层(Spin-on Dielectric，SOD)等工艺等中的任一种或多种。金属材料层可以包括但不限于氮化钛(Titanium nitride，TiN)、钛(Titanium，Ti)、硅化钨(Tungsten silicide，Si 2W)及钨(Tungsten，W)等中任一种或几种。由于可以控制修剪目标半导体层12期间去除目标半导体层12的厚度，因而可以控制栅极支撑柱143的厚度及沿oy方向的长度，从而可以控制后续在栅极支撑柱143的外表面上形成栅氧化层21或栅金属层22的厚度及沿oy方向的长度，实现对制备栅极结构20尺寸的控制。
作为示例，请参考图1、图6a-图8b，步骤S140中于栅极沟槽14内形成环绕目标半导体层12的栅极结构20之后还可以包括如下步骤：
步骤S151：于栅极沟槽14内填充第一低介电常数材料层144，第一低介电常数材料层144的上表面与初始叠层结构的上表面齐平；
步骤S152：去除第一侧壁141、第二侧壁142及部分初始叠层结构，得到沿第三方向延伸且底面接触衬底100上表面的字线辅助沟槽15；
步骤S153：于字线辅助沟槽15内填充第二低介电常数材料层16，第二低介电常数材料层16的上表面与初始叠层结构的上表面齐平。
作为示例，请继续参考图6a-图6b，步骤S151中可以采用原位水气生成工艺(In-Situ Steam Generation，ISSG)、原子层沉积工艺、等离子蒸汽沉积工艺及快速热氧化工艺(Rapid Thermal Oxidation，RTO)等中的任一种或几种于栅极沟槽14内填充第一低介电常数材料层144，之后，可以采用湿法刻蚀工艺、干法刻蚀工艺、化学机械研磨工艺及平推刻蚀工艺等中任一种或多种，沿厚度方向(例如oz方向)对第一低介电常数材料层144的上表面进行平坦化处理，使得第一低介电常数材料层144的上表面与初始叠层结构的上表面齐平，以便于后续在刻蚀并形成字线沟槽的过程中保护栅极结构20。
作为示例，请继续参考图7a-图7b，步骤S152中可以采用刻蚀工艺去除第一侧壁141、第二侧壁142及部分初始叠层结构，得到沿第三方向(例如ox方向)延伸且底面接触衬底100上表面的字线辅助沟槽15，以便于后续藉由字线辅助沟槽15形成与栅极结构连接的桥梁字线部，后续再在垂直于衬底100上表面的方向上叠置多层间隔分布的水平字线部，使得水平字线部经由桥梁字线部与对应的栅极结构连接，相对于直接在栅极结构的外侧形成在垂直于衬底100上表面的方向上叠置的多层字线结构，本实施例至少能够在不减小单位体积内存储单元数量的情况下，增加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。
作为示例，请继续参考图8a-图8b，步骤S153中可以采用沉积工艺于字线辅助沟槽15内填充第二低介电常数材料层16，之后可以采用湿法刻蚀工艺、干法刻蚀工艺、化学机械研磨工艺及平推刻蚀工艺等中任一种或多种，沿厚度方向(例如oz方向)对第二低介电常数材料层16的上表面进行平坦化处理，使得第二低介电常数材料层16的上表面与初始叠层结构的上表面齐平，以便于后续在刻蚀并形成字线沟槽的过程中保护栅极结构20。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺等中的任一种或多种。
作为示例，请参考图1、图9a-图10b，步骤S140中于栅极沟槽14内形成环绕目标 半导体层12的栅极结构20之后还可以包括如下步骤：
步骤S161：去除目标半导体层12沿第二方向位于栅极沟槽14相对两侧的部分，并去除第二低介电常数材料层16位于沿第一方向相邻第一介质层11之间的部分，得到第一字线部沟槽41；
步骤S162：以栅金属层22为刻蚀停止层，沿第二方向刻蚀第一低介电常数材料层144，得到第二字线部沟槽(未图示)；
步骤S163：于第一字线部沟槽41内形成第一字线部31，并于第二字线部沟槽(未图示)内形成第二字线部32，第一字线部31、第二字线部32构成字线结构30。
作为示例，请继续参考图9a-图9b，步骤S161中可以采用刻蚀工艺去除目标半导体层12沿第二方向(例如oy方向)位于栅极沟槽14相对两侧的部分，并去除第二低介电常数材料层16位于沿第一方向(例如oz方向)相邻第一介质层11之间的部分，得到第一字线部沟槽41。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。
作为示例，请继续参考图9a，第二字线部32沿第三方向(例如ox方向)的长度与栅极结构20沿第三方向(例如ox方向)的长度相等，以降低字线结构30与栅极结构20之间的连接阻抗。
作为示例，请继续参考图9a-图10b，步骤S162中可以以栅金属层22为刻蚀停止层，采用刻蚀工艺沿第二方向刻蚀第一低介电常数材料层144，得到第二字线部沟槽。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。步骤S163中可以采用沉积工艺于第一字线部沟槽41内形成第一字线部31，并于第二字线部沟槽(未图示)内形成第二字线部32，第一字线部31、第二字线部32构成字线结构30。第一字线部31、第二字线部32可以在相同工艺步骤中制备形成，也可以在不同工艺步骤中制备形成。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺等中的任一种或多种。字线结构30的材料可以包括但不限于铷、钴、镍、钛、钨、钽、钛化钽、氮化钨、铜及铝等中任一种或多种。
作为示例，请参考图11a-图11b，步骤S163中形成字线结构30之后，还包括如下步骤：
步骤S171：去除第一介质层11沿第二方向(例如oy方向)位于栅极沟槽14相对两侧的部分，得到字线隔离沟槽(未图示)；
步骤S172：于字线隔离沟槽内形成第三低介电常数材料层17。
作为示例，请继续参考图11a-图11b，步骤S171中可以采用刻蚀工艺去除第一介质层11沿第二方向位于栅极沟槽14相对两侧的部分，得到字线隔离沟槽(未图示)。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。步骤S172中可以采用沉积工艺于字线隔离沟槽内形成第三低介电常数材料层17，使得沿oz方向相邻字线结构30之间相互绝缘。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺等中任一种或多种。第一低介电常数材料层144、第二低介电常数材料层16及第三低介电常数材料层17中至少两个的材料相同。低介电常数材料层可以包括但不限于氧化硅、SiLK、MSQ、多孔SiLK及多孔MSQ等中任一种或多种。相对于直接在栅极结构的外侧形成在垂直于衬底表面的方向上叠置的多层字线结构，本实施例至少能够在不减小单位体积内存储单元数量的情况下，增加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
作为示例，请参考图12-图13，可以设置两个栅极沟槽14沿第三方向(例如ox方向)相互对称；步骤S172中于字线隔离沟槽内形成第三低介电常数材料层17之后还可以包括如下步骤：
步骤S181：于两个栅极沟槽14之间形成底面接触衬底100上表面的本体隔离结构18；
步骤S182：于本体隔离结构18与相邻的栅极结构20之间形成源极结构191，及于栅极结构20沿第三方向(例如ox方向)远离本体隔离结构18的一侧形成漏极结构192。
作为示例，请继续参考图12，步骤S181中可以采用刻蚀工艺刻蚀初始叠层结构以得到本体隔离沟槽(未图示)，刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于RIE、ICP及HDP等中任一种或多种。然后于本体隔离沟槽内沉积隔离材料以得到本体隔离结构18。沉积工艺可以包括但不限于CVD、ALD、HDP及SOD等工艺等中任一种或多种。隔离材料可以包括氮化硅、氧化硅、氮氧化硅及多晶硅等中任一种或多种。
作为示例，请继续参考图13，可以设置本体隔离结构18的位置，使得制备半导体结构以本体隔离结构18的沿oy方向延伸的对称轴m1对称，也可以设置沿oy方向相邻的栅极结构20以对称轴m2对称。
作为示例，请继续参考图13，步骤S182中可以于本体隔离结构18与相邻的栅极结构20之间的目标半导体层上形成源极结构191，及于栅极结构20沿第三方向(例如ox方向)远离本体隔离结构18的一侧目标半导体层上形成漏极结构192，得到存储单元结构200。沿ox方向相邻源极结构191以对称轴m1对称，且沿ox方向相邻漏极结构192以对称轴m1对称。本实施例中得到沿oz方向间隔分布的多个本体结构300，本体结构300包括中心对称的4个存储单元结构200。由于可以在形成栅极结构之前，修剪并改变目标半导体层位于栅极沟槽内裸露并悬空的部分，从而可以控制后续形成栅极结构的尺寸；由于可以利用第一沟槽隔离结构、第三沟槽隔离结构形成与栅极结构连接的桥梁字线部，后续再在垂直于衬底表面的方向上叠置多层间隔分布的水平字线部，使得水平字线部经由桥梁字线部与对应的栅极结构连接，相对于直接在栅极结构的外侧形成在垂直于衬底表面的方向上叠置的多层字线结构，本实施例至少能够在不减小单位体积内存储单元数量的情况下，增加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
作为示例，请继续参考图13，存储单元结构200中目标半导体层沿ox方向延伸，可以采用第一类型掺杂，例如P型轻掺杂。沟道区导电层(未图示)位于源极结构191与漏极结构192之间，可以采用第一类型掺杂，例如P型重掺杂，用于形成晶体管的沟道区；漏极结构192可以采用第二类型掺杂，例如N型重掺杂，用于形成晶体管的漏区。源极结构191可以采用第二类型掺杂，例如N型重掺杂，用于形成晶体管的源区。P型杂质离子可以包括但不限于硼(B)离子、镓(Ga)离子、氟化硼(BF 2)离子及铟(In)离子等中任一种或多种；N型杂质离子可以包括但不限于磷(P)离子、砷(As)离子及锑(Sb)离子等中任一种或多种。
作为示例，请参考图14-图15，步骤S172中于字线隔离沟槽内形成第三低介电常数材料层17之后还可以包括如下步骤：
步骤S181：于两个栅极沟槽14之间形成底面接触衬底100上表面的本体隔离结构18；
步骤S183：于位于栅极结构20沿第三方向(例如ox方向)相对两侧的目标半导体层上形成源极结构191、漏极结构192，源极结构191位于栅极结构20与本体隔离结构18之间。
作为示例，请继续参考图15，通过本公开实施例中所述半导体结构制备方法得到沿oz方向间隔分布的多个本体结构300，本体结构300包括以对称轴m2对称的存储单元结构200，存储单元结构200中目标半导体层沿ox方向延伸，可以采用第一类型掺杂，例如P型轻掺杂。沟道区导电层(未图示)位于源极结构191与漏极结构192之间，可以采用第一类型掺杂，例如P型重掺杂，用于形成晶体管的沟道区；漏极结构192可以采用第二类型掺杂，例如N型重掺杂，用于形成晶体管的漏区。源极结构191可以采用第二类型 掺杂，例如N型重掺杂，用于形成晶体管的源区。P型杂质离子可以包括但不限于硼(B)离子、镓(Ga)离子、氟化硼(BF 2)离子及铟(In)离子等中任一种或多种；N型杂质离子可以包括但不限于磷(P)离子、砷(As)离子及锑(Sb)离子等中任一种或多种。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请参考图5a-图5c，在本公开实施例提供的半导体结构中，包括衬底100及位于衬底100上的初始叠层结构，初始叠层结构包括沿第一方向(例如oz方向)依次交替叠置的第一介质层11、目标半导体层12，第一介质层11与衬底100相邻；初始叠层结构内形成有沿第二方向(例如oy方向)间隔排布且沿第三方向(例如ox方向)延伸的第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133，第一沟槽隔离结构131、第二沟槽隔离结构132及第三沟槽隔离结构133的底面接触衬底100的上表面；初始叠层结构内形成有底面接触衬底上表面的两个间隔的栅极沟槽14，目标半导体层12位于栅极沟槽14内部分裸露并悬空；栅极沟槽14内目标半导体层12外侧环绕设置有栅极结构20，沿第一方向(例如oz方向)、第二方向(例如oy方向)相邻的栅极结构20之间相互绝缘；第一方向、第二方向及第三方向相互垂直。由于可以在形成栅极结构之前，修剪并改变目标半导体层位于栅极沟槽内裸露并悬空的部分，从而可以控制后续形成栅极结构的尺寸；由于可以利用第一沟槽隔离结构、第三沟槽隔离结构形成与栅极结构连接的桥梁字线部，后续再在垂直于衬底表面的方向上叠置多层间隔分布的水平字线部，使得水平字线部经由桥梁字线部与对应的栅极结构连接，相对于直接在栅极结构的外侧形成在垂直于衬底表面的方向上叠置的多层字线结构，本实施例至少能够在不减小单位体积内存储单元数量的情况下，增加字线结构所占空间体积及相邻字线结构的间距，降低了制备工艺复杂度的同时增加了制备产品的性能及可靠性。
请注意，上述实施例仅出于说明性目的而不意味对本公开的限制。本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构制备方法，包括：
    提供衬底，于所述衬底上形成初始叠层结构，所述初始叠层结构包括沿第一方向依次交替叠置的第一介质层、目标半导体层，所述第一介质层与所述衬底相邻；
    于所述初始叠层结构内形成沿第二方向间隔排布且沿第三方向延伸的第一沟槽隔离结构、第二沟槽隔离结构及第三沟槽隔离结构；
    形成底面接触所述衬底上表面的两个间隔的栅极沟槽，所述目标半导体层位于所述栅极沟槽内的部分裸露并悬空；
    于所述栅极沟槽内形成环绕所述目标半导体层的栅极结构，沿所述第一方向、所述第二方向相邻的所述栅极结构之间相互绝缘；所述第一方向、所述第二方向及所述第三方向相互垂直。
  2. 根据权利要求1所述的半导体结构制备方法，其中，所述第一沟槽隔离结构、所述第二沟槽隔离结构及所述第三沟槽隔离结构的上表面与所述初始叠层结构的上表面齐平；所述形成底面接触所述衬底上表面的两个间隔的栅极沟槽，包括：
    形成第一掩膜层，所述第一掩膜层覆盖所述第一沟槽隔离结构、所述第二沟槽隔离结构及所述第三沟槽隔离结构的上表面；
    图形化所述第一掩膜层，并基于图形化后第一掩膜层为掩膜版刻蚀所述初始叠层结构，以得到所述栅极沟槽，位于所述栅极沟槽沿所述第二方向的相对两侧的所述第一沟槽隔离结构的剩余部分、所述第三沟槽隔离结构的剩余部分构成所述栅极沟槽的第一侧壁。
  3. 根据权利要求2所述的半导体结构制备方法，其中，所述于所述栅极沟槽内形成环绕所述目标半导体层的栅极结构，包括：
    沿所述目标半导体层的内径方向修剪所述目标半导体层位于所述栅极沟槽内的部分，得到栅极支撑柱；
    于所述栅极支撑柱的外表面上形成栅氧化层；
    沉积金属材料层，所述金属材料层环绕所述栅氧化层的部分构成栅金属层，所述栅氧化层、所述栅金属层构成所述栅极结构。
  4. 根据权利要求3所述的半导体结构制备方法，其中，所述金属材料层位于所述第一侧壁上的部分构成第二侧壁；所述于所述栅极沟槽内形成环绕所述目标半导体层的栅极结构之后，包括：
    于所述栅极沟槽内填充第一低介电常数材料层，所述第一低介电常数材料层的上表面与所述初始叠层结构的上表面齐平；
    去除所述第一侧壁、所述第二侧壁及部分所述初始叠层结构，得到沿所述第三方向延伸且底面接触所述衬底上表面的字线辅助沟槽；
    于所述字线辅助沟槽内填充第二低介电常数材料层，所述第二低介电常数材料层的上表面与所述初始叠层结构的上表面齐平。
  5. 根据权利要求4所述的半导体结构制备方法，其中，所述于所述栅极沟槽内形成环绕所述目标半导体层的栅极结构之后，还包括：
    去除所述目标半导体层沿所述第二方向位于所述栅极沟槽相对两侧的部分，并去除所述第二低介电常数材料层位于沿所述第一方向相邻所述第一介质层之间的部分，得到第一字线部沟槽；
    以所述栅金属层为刻蚀停止层，沿所述第二方向刻蚀所述第一低介电常数材料层，得到第二字线部沟槽；
    于所述第一字线部沟槽内形成第一字线部，并于所述第二字线部沟槽内形成第二字线部，所述第一字线部、所述第二字线部构成字线结构。
  6. 根据权利要求5所述的半导体结构制备方法，其中，形成所述字线结构之后，包括：
    去除所述第一介质层沿所述第二方向位于所述栅极沟槽相对两侧的部分，得到字线隔离沟槽；
    于所述字线隔离沟槽内形成第三低介电常数材料层。
  7. 根据权利要求6所述的半导体结构制备方法，其中，两个所述栅极沟槽沿所述第三方向相互对称；于所述字线隔离沟槽内形成第三低介电常数材料层之后，包括：
    于两个所述栅极沟槽之间形成底面接触所述衬底的上表面的本体隔离结构；
    于所述本体隔离结构与相邻所述栅极结构之间形成源极结构，及于所述栅极结构沿所述第三方向远离所述本体隔离结构的一侧形成漏极结构。
  8. 根据权利要求6所述的半导体结构制备方法，其中，于所述字线隔离沟槽内形成第三低介电常数材料层之后，还包括：
    于两个所述栅极沟槽之间形成底面接触所述衬底的上表面的本体隔离结构；
    于位于所述栅极结构沿所述第三方向相对两侧的目标半导体层上形成源极结构、漏极结构，所述源极结构位于所述栅极结构与所述本体隔离结构之间。
  9. 根据权利要求7或8所述的半导体结构制备方法，其中，于所述字线隔离沟槽内形成第三低介电常数材料层之后，还包括：
    于所述本体隔离结构与所述源极结构之间的目标半导体层上形成电容结构，及于所述漏极结构沿所述第三方向远离所述电容结构一侧的目标半导体层上形成位线结构。
  10. 根据权利要求7所述的半导体结构制备方法，其中：
    沿所述第三方向相邻所述源极结构沿所述第三方向对称；及/或
    沿所述第三方向相邻所述漏极结构沿所述第三方向对称。
  11. 根据权利要求5-8任一项所述的半导体结构制备方法，其中，所述第一字线部、所述第二字线部在同一工艺步骤中制备而成。
  12. 根据权利要求5-8任一项所述的半导体结构制备方法，其中，所述第二字线部沿所述第三方向的长度与所述栅极结构沿所述第三方向的长度相等。
  13. 根据权利要求1-8任一项所述的半导体结构制备方法，其中，所述初始叠层结构以所述第二沟槽隔离结构的沿所述第三方向延伸的对称轴沿所述第二方向对称。
  14. 根据权利要求6-8任一项所述的半导体结构制备方法，其中，所述第一低介电常数材料层、所述第二低介电常数材料层及所述第三低介电常数材料层中至少两个的材料相同。
  15. 一种半导体结构，采用权利要求1-14任一项所述的半导体结构制备方法制备而成。
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