WO2024024386A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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WO2024024386A1
WO2024024386A1 PCT/JP2023/024274 JP2023024274W WO2024024386A1 WO 2024024386 A1 WO2024024386 A1 WO 2024024386A1 JP 2023024274 W JP2023024274 W JP 2023024274W WO 2024024386 A1 WO2024024386 A1 WO 2024024386A1
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hydrogen
region
semiconductor device
layer
conductivity type
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French (fr)
Japanese (ja)
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仁 坂根
正史 加藤
俊太 原田
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Shi Atex Co Ltd
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Shi Atex Co Ltd
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Priority to EP23846119.8A priority Critical patent/EP4564437A4/en
Priority to CN202380050841.0A priority patent/CN119487989A/zh
Publication of WO2024024386A1 publication Critical patent/WO2024024386A1/ja
Priority to US19/017,371 priority patent/US20250151352A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • SiC Silicon carbide
  • SiC semiconductor devices it is known that when a current is applied, injected carriers are trapped in stacking faults in an epitaxial layer, lowering the stacking fault energy and leading to expansion of the stacking faults. The expansion of stacking faults is viewed as an issue because it leads to an increase in forward voltage.
  • One exemplary object of an embodiment of the present invention is to provide a technique for suppressing the expansion of stacking faults during current application to a SiC semiconductor device.
  • a method for manufacturing a semiconductor device includes irradiating a semiconductor device including a substrate made of silicon carbide and a semiconductor layer of a first conductivity type on a first surface of the substrate with hydrogen ions to form a semiconductor device of 1 ⁇ m or more.
  • the method includes forming a high hydrogen concentration region having a hydrogen concentration exceeding 10 15 /cm 3 over the thickness. At least a portion of the high concentration hydrogen region is formed within the first conductivity type semiconductor layer.
  • This semiconductor device includes a substrate made of silicon carbide, a semiconductor layer of a first conductivity type provided on the substrate, and a high concentration hydrogen region having a hydrogen concentration exceeding 10 15 /cm 3 over a thickness of 1 ⁇ m or more. . At least a portion of the high concentration hydrogen region is formed within the first conductivity type semiconductor layer.
  • FIG. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device according to an embodiment.
  • 3 is a graph showing an example of the hydrogen concentration of a semiconductor device after hydrogen ion irradiation. It is a table showing the thickness of the high concentration hydrogen region and the presence or absence of expansion of stacking faults in comparative examples and examples.
  • FIG. 7 is a diagram schematically showing another example of the formation position of a high concentration hydrogen region.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 3 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor device.
  • 3 is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.
  • This embodiment relates to a SiC semiconductor device including a substrate made of silicon carbide (SiC) and a semiconductor layer of a first conductivity type provided on a first surface of the substrate.
  • SiC silicon carbide
  • a problem with such SiC semiconductor devices is that stacking faults existing near the interface between the substrate and the semiconductor layer expand when a current is applied, leading to an increase in forward voltage.
  • hydrogen ions are irradiated near the interface between the substrate and the semiconductor layer to fix hydrogen to partial dislocations surrounding stacking faults, thereby suppressing expansion of stacking faults when current is applied.
  • fixing hydrogen to partial dislocations it is possible to suppress a decrease in stacking fault energy due to trapping of injected carriers in stacking faults.
  • expansion of stacking faults can be suppressed by forming a high concentration hydrogen region having a hydrogen concentration of more than 10 15 /cm 3 over a thickness of 1 ⁇ m or more by irradiation with hydrogen ions.
  • a highly concentrated hydrogen region with a thickness of 1 ⁇ m or more, a sufficient amount of hydrogen can be fixed to the partial dislocations that border the stacking faults that exist near the interface between the substrate and the semiconductor layer, and the stacking faults can be expanded. can be suitably suppressed.
  • FIG. 1 is a cross-sectional view schematically showing a configuration example of a semiconductor device 10 according to an embodiment.
  • the semiconductor device 10 is a SiC semiconductor device, and is a metal oxide semiconductor field effect transistor (MOSFET).
  • the semiconductor device 10 includes a substrate 12, a buffer layer 14, a drift layer 16, a base region 18, a source region 20, a base contact region 22, a gate insulating film 24, a gate electrode 26, and an interlayer insulating film 28. , a source electrode 30 , and a drain electrode 32 .
  • MOSFET metal oxide semiconductor field effect transistor
  • the substrate 12 is a SiC substrate made of silicon carbide (SiC) of a first conductivity type (for example, n-type) or a second conductivity type (for example, p-type).
  • the substrate 12 is, for example, an n-type SiC substrate, and is doped with, for example, nitrogen (N) as an n-type impurity.
  • the impurity concentration of the first conductivity type or the second conductivity type of the substrate 12 is 1.0 ⁇ 10 18 /cm 3 or more, for example, 2.0 ⁇ 10 18 /cm 3 or more and 5.0 ⁇ 10 19 /cm 3 . It is as follows.
  • the substrate 12 includes a first surface 12a and a second surface 12b opposite to the first surface 12a.
  • the first surface 12a is, for example, a (0001) Si surface.
  • Buffer layer 14 is a first conductivity type SiC semiconductor layer epitaxially grown on first surface 12 a of substrate 12 .
  • the buffer layer 14 is, for example, an n-type SiC layer, and is doped with, for example, nitrogen (N) as an n-type impurity.
  • the first conductivity type impurity concentration of the buffer layer 14 is lower than the first conductivity type or second conductivity type impurity concentration of the substrate 12 and higher than the first conductivity type impurity concentration of the drift layer 16 .
  • the impurity concentration of the first conductivity type of the buffer layer 14 is, for example, 1.0 ⁇ 10 16 /cm 3 or more and 1.0 ⁇ 10 18 /cm 3 or less.
  • the thickness of the buffer layer 14 is 1.0 ⁇ m or more and 5.0 ⁇ m or less, for example, 1.5 ⁇ m or more and 3.0 ⁇ m or less, and for example, 2.0 ⁇ m.
  • Drift layer 16 is a first conductivity type SiC semiconductor layer epitaxially grown on buffer layer 14 .
  • the drift layer 16 is, for example, an n-type SiC layer, and is doped with, for example, nitrogen (N) as an n-type impurity.
  • the first conductivity type impurity concentration of the drift layer 16 is lower than the first conductivity type impurity concentration of the buffer layer 14 .
  • the first conductivity type impurity concentration of the drift layer 16 is, for example, 1.0 ⁇ 10 15 /cm 3 or more and 1.0 ⁇ 10 17 /cm 3 or less.
  • the thickness of the drift layer 16 is greater than the thickness of the buffer layer 14.
  • the thickness of the drift layer 16 is 5.0 ⁇ m or more and 50 ⁇ m or less, for example, 7.5 ⁇ m or more and 15 ⁇ m or less, and is, for example, 10 ⁇ m.
  • Base region 18 is a second conductivity type SiC semiconductor region provided on drift layer 16 .
  • the base region 18 is, for example, a p-type, and is doped with, for example, aluminum (Al) as a p-type impurity.
  • the base region 18 is formed, for example, by irradiating the drift layer 16 with impurity ions of the second conductivity type.
  • the impurity concentration of the second conductivity type in the base region 18 is higher than the impurity concentration of the first conductivity type in the drift layer 16 .
  • the second conductivity type impurity concentration of the base region 18 is, for example, 1.0 ⁇ 10 16 /cm 3 or more and 1.0 ⁇ 10 18 /cm 3 or less.
  • Source region 20 is a first conductivity type SiC semiconductor region provided on base region 18 .
  • Source region 20 is provided adjacent to gate insulating film 24 .
  • the source region 20 is, for example, an n-type, and is doped with, for example, nitrogen (N) as an n-type impurity.
  • the source region 20 is formed, for example, by irradiating the drift layer 16 with impurity ions of the first conductivity type.
  • the impurity concentration of the first conductivity type in the source region 20 is higher than that in the drift layer 16 .
  • the impurity concentration of the first conductivity type in the source region 20 is 1.0 ⁇ 10 18 /cm 3 or more, for example, 2.0 ⁇ 10 18 /cm 3 or more and 5.0 ⁇ 10 19 /cm 3 or less.
  • Base contact region 22 is a second conductivity type SiC semiconductor region provided on base region 18 .
  • Base contact region 22 is provided apart from gate insulating film 24 .
  • the base contact region 22 is, for example, a p-type, and is doped with, for example, aluminum (Al) as a p-type impurity.
  • the base contact region 22 is formed, for example, by irradiating the drift layer 16 with impurity ions of the second conductivity type.
  • the second conductivity type impurity concentration of base contact region 22 is higher than the second conductivity type impurity concentration of base region 18 .
  • the second conductivity type impurity concentration of the base contact region 22 is, for example, 1.0 ⁇ 10 17 /cm 3 or more and 1.0 ⁇ 10 19 /cm 3 or less.
  • the gate insulating film 24 is provided on the inner wall surface of the gate trench 34. Gate insulating film 24 is provided adjacent to drift layer 16, base region 18, and source region 20.
  • the gate trench 34 is formed so as to be dug from the upper surface 20a of the source region 20 toward the substrate 12. Gate trench 34 is formed to penetrate source region 20 and base region 18 and reach the top of drift layer 16 .
  • the gate insulating film 24 is formed of an oxide material, for example SiO 2 .
  • the gate electrode 26 is provided so as to fill the inside of the gate insulating film 24 (gate trench 34).
  • the gate electrode 26 is formed of, for example, polycrystalline silicon doped with n-type impurities such as phosphorus (P) and nitrogen (N).
  • the interlayer insulating film 28 is provided on the gate insulating film 24 and the gate electrode 26.
  • Interlayer insulating film 28 is formed of any insulating material.
  • the source electrode 30 is provided on the source region 20, base contact region 22, and interlayer insulating film 28. Source electrode 30 contacts upper surface 20a of source region 20 and upper surface 22a of base contact region 22.
  • the source electrode 30 is made of a metal material such as chromium (Cr) or nickel (Ni), for example.
  • the source electrode 30 may be formed of a metal multilayer film in which a plurality of metal layers made of different metal materials are laminated.
  • the source electrode 30 is a surface metal electrode layer formed on the surface of the semiconductor device 10.
  • the drain electrode 32 is provided on the second surface 12b of the substrate 12. Drain electrode 32 contacts second surface 12b of substrate 12.
  • the drain electrode 32 is made of a metal material such as chromium (Cr) or nickel (Ni), for example.
  • the drain electrode 32 may be formed of a metal multilayer film in which a plurality of metal layers made of different metal materials are laminated.
  • the drain electrode 32 is a back metal electrode layer formed on the back surface of the semiconductor device 10.
  • the semiconductor device 10 is irradiated with hydrogen ions, and a high concentration hydrogen region 40 having a hydrogen concentration exceeding 10 15 /cm 3 is formed over a thickness of 1 ⁇ m or more. At least a portion of the high concentration hydrogen region 40 is formed in the buffer layer 14 or the drift layer 16, which is a first conductivity type semiconductor layer. In the example of FIG. 1, the entire high concentration hydrogen region 40 is formed in the buffer layer 14, and the upper end 42 and lower end 44 of the high concentration hydrogen region 40 are located in the buffer layer 14.
  • FIG. 2 is a graph showing an example of the hydrogen concentration of the semiconductor device 10 after hydrogen ion irradiation.
  • FIG. 2 shows the case where the hydrogen ion irradiation energy was 960 keV and the dose was 1.0 ⁇ 10 13 /cm 2 .
  • the thickness range of the high hydrogen concentration region 40 where the hydrogen concentration exceeds 10 15 /cm 3 is approximately 1.9 ⁇ m.
  • the high hydrogen concentration region 40 has a hydrogen concentration greater than 10 16 /cm 3 in a thickness range 46 of approximately 1.1 ⁇ m.
  • the peak value of the hydrogen concentration in the high hydrogen concentration region 40 is about 1.1 ⁇ 10 17 /cm 3 .
  • the presence or absence of stacking fault expansion can be confirmed by an X-ray topography method or a photoluminescence method.
  • FIG. 3 is a table showing the thickness of the high concentration hydrogen region 40 and the presence or absence of stacking fault expansion in the comparative example and the example.
  • Figure 3 summarizes the presence or absence of stacking fault expansion when the hydrogen ion irradiation dose was varied in the range of 1.0 ⁇ 10 10 /cm 2 to 1.0 ⁇ 10 16 /cm 2 . .
  • Comparative Examples 1 and 2 in which the thickness of the high concentration hydrogen region 40 was less than 1 ⁇ m, expansion of stacking faults was confirmed.
  • Examples 1 to 5 in which the high concentration hydrogen region 40 had a thickness of 1 ⁇ m or more, no expansion of stacking faults was observed, indicating that expansion of stacking faults could be suppressed.
  • FIGS. 4(a) to 4(d) are diagrams schematically showing other examples of formation positions of the high concentration hydrogen regions 40a to 40d.
  • the high concentration hydrogen region 40a shown in FIG. 4(a) is formed across the substrate 12 and the buffer layer 14, and is formed across the first surface 12a, which is the interface between the substrate 12 and the buffer layer 14.
  • An upper end 42a of the high concentration hydrogen region 40a is located on the buffer layer 14, and a lower end 44a of the high concentration hydrogen region 40a is located on the substrate 12.
  • At least a portion of the high concentration hydrogen region 40a is formed in the substrate 12 and the buffer layer 14.
  • the high concentration hydrogen region 40b shown in FIG. 4(b) is formed across the substrate 12, buffer layer 14, and drift layer 16.
  • High concentration hydrogen region 40b is formed across first surface 12a, which is the interface between substrate 12 and buffer layer 14, and is also formed across interface 36 between buffer layer 14 and drift layer 16.
  • the upper end 42b of the high concentration hydrogen region 40b is located on the drift layer 16, and the lower end 44b of the high concentration hydrogen region 40b is located on the substrate 12.
  • At least a portion of high concentration hydrogen region 40b is formed in substrate 12, buffer layer 14, and drift layer 16.
  • a high concentration hydrogen region 40c shown in FIG. 4(c) is formed across the buffer layer 14 and the drift layer 16.
  • High concentration hydrogen region 40c is formed across interface 36 between buffer layer 14 and drift layer 16.
  • the upper end 42c of the high concentration hydrogen region 40c is located in the drift layer 16
  • the lower end 44c of the high concentration hydrogen region 40c is located in the buffer layer 14.
  • At least a portion of the high concentration hydrogen region 40b is formed in the buffer layer 14 and the drift layer 16.
  • the high concentration hydrogen region 40d shown in FIG. 4(d) is formed only in the drift layer 16.
  • An upper end 42d and a lower end 44d of the high concentration hydrogen region 40d are located in the drift layer 16.
  • the high concentration hydrogen regions 40, 40a to 40d are formed near the first surface 12a of the substrate 12. At least a portion of the high concentration hydrogen regions 40, 40a to 40d is preferably formed within 5 ⁇ m from the first surface 12a of the substrate 12.
  • the upper ends 42, 42a-42d or the lower ends 44, 44a-44d of the high concentration hydrogen regions 40, 40a-40d are preferably located within 5 ⁇ m from the first surface 12a of the substrate 12.
  • the upper ends 42, 42a-42d or the lower ends 44, 44a-44d of the high concentration hydrogen regions 40, 40a-40d may be formed within 4 ⁇ m, 3 ⁇ m, or 2 ⁇ m from the first surface 12a of the substrate 12.
  • the hydrogen concentration in the high-concentration hydrogen regions 40, 40a to 40d may be reduced after the fact due to annealing treatment included in the manufacturing process of the semiconductor device 10. For example, if an annealing process is performed after irradiation with hydrogen ions, the annealing process may cause hydrogen to diffuse and reduce the hydrogen concentration. At this time, the hydrogen fixed to the partial dislocations surrounding the stacking faults remains fixed even after the annealing process. In other words, hydrogen diffused by the annealing process is not fixed to the partial dislocations surrounding the stacking faults, and is considered not to contribute to suppressing the expansion of the stacking faults.
  • the buffer layer 14 or the drift layer 16 at the time of completion of the semiconductor device 10 is 1.0 ⁇ 10 15 /cm 2 or less, the buffer layer 14 or the drift layer 16 after hydrogen ion irradiation If the hydrogen concentration in the drift layer 16 exceeds 1.0 ⁇ 10 15 /cm 2 over a thickness of 1 ⁇ m or more, expansion of stacking faults can be suppressed.
  • the hydrogen concentration in the buffer layer 14 or drift layer 16 of the semiconductor device 10 may remain in a state exceeding 1.0 ⁇ 10 15 /cm 2 .
  • the high concentration hydrogen regions 40, 40a to 40d are formed by irradiation with hydrogen ions, expansion of stacking faults can be suppressed.
  • 5 to 11 are cross-sectional views schematically showing the manufacturing process of a semiconductor device.
  • the buffer layer 14 is formed on the first surface 12a of the substrate 12, and the drift layer 16 is formed on the buffer layer 14.
  • Buffer layer 14 and drift layer 16 can be formed using any epitaxial growth method such as chemical vapor deposition (CVD).
  • the growth temperature of the buffer layer 14 and the drift layer 16 is, for example, 1500° C. or more and 1700° C. or less.
  • hydrogen ions 50 are irradiated from above the drift layer 16 to form a high concentration hydrogen region 40 in the buffer layer 14.
  • Irradiation with hydrogen ions 50 can be performed using any ion irradiation device.
  • the hydrogen ions 50 can be irradiated using a cyclotron type or Van de Graff type ion irradiation device.
  • the hydrogen ions 50 may be irradiated from the second surface 12b (back surface) of the substrate 12.
  • second impurity ions 52 which are impurities of the second conductivity type, are irradiated onto the drift layer 16 to form the base region 18 and the base contact region 22.
  • the second impurity ions 52 are, for example, aluminum ions.
  • the base region 18 can be formed by irradiating the entire surface of the drift layer 16 with second impurity ions 52 .
  • the base contact region 22 can be formed by irradiating the second impurity ions 52 with the region other than the base contact region 22 being masked.
  • the drift layer 16 is irradiated with first impurity ions 54, which are impurities of the first conductivity type, to form the source region 20.
  • the first impurity ions 54 are, for example, nitrogen ions.
  • the source region 20 can be formed by irradiating the first impurity ions 54 with a region other than the source region 20 (for example, the base contact region 22) being masked.
  • an annealing process is performed at a first temperature to activate the first conductivity type or second conductivity type impurity implanted into the base region 18, source region 20, and base contact region 22.
  • the first temperature is 1500°C or higher, for example 1600°C or higher and 1800°C or lower.
  • a gate trench 34 is formed.
  • the gate trench 34 can be formed by forming a mask in a region other than the region where the gate trench 34 is to be formed and dry etching the source region 20, base region 18, and drift layer 16 in the opening region of the mask.
  • a gate insulating film 24 is formed on the inner wall surface of the gate trench 34.
  • the gate insulating film 24 can be formed, for example, by thermally oxidizing the inner wall surface of the gate trench 34 at a temperature of approximately 700° C. to 1000° C.
  • a gate electrode 26 is formed inside the gate insulating film 24. Gate electrode 26 can be formed using any technique such as CVD.
  • an interlayer insulating film 28 is formed on the source region 20, base contact region 22, gate insulating film 24, and gate electrode 26.
  • the interlayer insulating film 28 can be formed using any technique such as CVD.
  • a drain electrode 32 (back metal electrode layer) is formed on the second surface 12b of the substrate 12.
  • the drain electrode 32 can be formed using any film forming technique such as sputtering or vapor deposition.
  • the drain electrode 32 is annealed at a second temperature to bring the drain electrode 32 into ohmic contact with the second surface 12b of the substrate 12.
  • the second temperature is 450°C or higher, for example 600°C or higher and 800°C or lower.
  • the source electrode 30 (surface metal electrode layer) shown in FIG. 1 is formed.
  • the source electrode 30 can be formed using any film forming technique such as sputtering or vapor deposition.
  • the source electrode 30 is annealed at a third temperature to bring the source electrode 30 into ohmic contact with the source region 20 and the base contact region 22.
  • the third temperature is 300°C or higher, for example 350°C or higher and 500°C or lower.
  • FIG. 12 is a flowchart illustrating an example of a method for manufacturing the semiconductor device 10 according to the embodiment.
  • a first conductivity type semiconductor layer for example, the buffer layer 14 and the drift layer 16
  • hydrogen ions 50 are irradiated to form a high concentration hydrogen region 40 having a hydrogen concentration exceeding 10 15 /cm 3 over a thickness of 1 ⁇ m or more (S12).
  • a second conductivity type impurity ion 52 is irradiated to form the base region 18 and a base contact region 22 (S14), and a first conductivity type impurity ion 54 is irradiated to form the source region 20 (S16). .
  • the semiconductor device 10 is annealed at a first temperature of 1500° C. or higher (S18) to activate the impurities in the base region 18, source region 20, and base contact region 22.
  • a gate trench 34 is formed, and a gate insulating film 24 and a gate electrode 26 are formed in the gate trench 34 (S20).
  • an interlayer insulating film 28 is formed on the gate electrode 26 (S22).
  • a back metal electrode layer (drain electrode 32) is formed on the second surface 12b of the substrate 12, and annealed at a second temperature of 450° C. or higher (S24).
  • a part of the interlayer insulating film 28 is removed (S26), a surface metal electrode layer (source electrode 30) is formed on the interlayer insulating film 28, and annealed at a third temperature of 300° C. or higher (S28). .
  • the expansion of stacking faults is suppressed by irradiating hydrogen ions 50 so that a high concentration hydrogen region 40 with a hydrogen concentration exceeding 10 15 /cm 3 is formed over a thickness of 1 ⁇ m or more.
  • stacking faults present in buffer layer 14 and drift layer 16 can be prevented from expanding upward, and stacking faults can be prevented from reaching base region 18, source region 20, and base contact region 22. Thereby, it is possible to suppress performance deterioration due to use of the semiconductor device 10 while being energized.
  • the order of steps S12 to S16 may be changed.
  • the irradiation with the hydrogen ions 50 in S12 may be performed after the irradiation with the second impurity ions 52 in S14, or the irradiation with the hydrogen ions 50 in S12 may be performed after the irradiation with the first impurity ions 54 in S16. good.
  • the irradiation with the second impurity ions 52 in S14 may be performed after the irradiation with the first impurity ions 54 in S16.
  • irradiation with hydrogen ions 50 in S12 may be performed after the annealing process at the first temperature in S18.
  • the lattice defects caused by the irradiation with the hydrogen ions 50 can be recovered by the second temperature annealing process in S24.
  • the hydrogen ion 50 irradiation step in S12 may be performed between S18 and S20, between S20 and S22, or between S22 and S24.
  • the hydrogen ion 50 irradiation in S12 may be performed after the second temperature annealing process in S24.
  • the step of irradiating the hydrogen ions 50 in S12 may be performed between S24 and S26, or between S26 and S28.
  • the third temperature of the annealing process in S28 is low, diffusion of hydrogen injected into the high concentration hydrogen region 40 is suppressed.
  • the hydrogen concentration in the high hydrogen concentration region 40 may be maintained at more than 1.0 ⁇ 10 15 /cm 2 .
  • the order of steps S22 to S28 may be changed.
  • the formation of the interlayer insulating film 28 in S22 may be performed after the formation of the back metal electrode layer (drain electrode 32) in S24.
  • the step of forming the back metal electrode layer (drain electrode 32) in S24 may be performed after the step of S26 or after the step of S28.
  • the semiconductor device 10 is a MOSFET.
  • This embodiment is applicable to SiC semiconductor devices other than MOSFETs as long as they have a laminated structure of a substrate, a buffer layer, and a drift layer.
  • the semiconductor device 10 may be a transistor such as a junction field effect transistor (JFET), a bipolar transistor (BJT), or an insulated gate bipolar transistor (IGBT), or a diode such as a Schottky barrier diode or a PIN diode. It may be.
  • JFET junction field effect transistor
  • BJT bipolar transistor
  • IGBT insulated gate bipolar transistor

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  • Electrodes Of Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
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