WO2024021464A1 - 一种用于测序芯片表面化学处理及封装键合的方法 - Google Patents

一种用于测序芯片表面化学处理及封装键合的方法 Download PDF

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WO2024021464A1
WO2024021464A1 PCT/CN2022/141107 CN2022141107W WO2024021464A1 WO 2024021464 A1 WO2024021464 A1 WO 2024021464A1 CN 2022141107 W CN2022141107 W CN 2022141107W WO 2024021464 A1 WO2024021464 A1 WO 2024021464A1
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wafer
chip
sequencing
bonding
cover
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PCT/CN2022/141107
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English (en)
French (fr)
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周魏
宋扬
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深圳太古语科技有限公司
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    • C—CHEMISTRY; METALLURGY
    • C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
    • C12Q—MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS; COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES
    • C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
    • C12Q1/68—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids
    • C12Q1/6869—Methods for sequencing
    • C—CHEMISTRY; METALLURGY
    • C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
    • C12Q—MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS; COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES
    • C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
    • C12Q1/68—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids
    • C12Q1/6869—Methods for sequencing
    • C12Q1/6874—Methods for sequencing involving nucleic acid arrays, e.g. sequencing by hybridisation
    • C—CHEMISTRY; METALLURGY
    • C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
    • C12Q—MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS; COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES
    • C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
    • C12Q1/68—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids
    • C12Q1/6876—Nucleic acid products used in the analysis of nucleic acids, e.g. primers or probes
    • C12Q1/6883—Nucleic acid products used in the analysis of nucleic acids, e.g. primers or probes for diseases caused by alterations of genetic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container

Definitions

  • This application relates to the field of gene sequencing technology, such as a method for surface chemical treatment and packaging bonding of sequencing chips.
  • Gene sequencing is a new type of genetic testing technology.
  • the entire platform system includes sequencing instruments, biochemical reaction reagents, and gene sequencing chips.
  • the entire sequencing process is completed by cooperating with each other.
  • the sequencing chip is an important consumable and carrier for the gene sequencing system.
  • the surface of the sequencing chip It requires certain chemical modifications to form a specific group. This chemical group can capture the DNA fragment to be detected and stably fix the DNA fragment on its surface.
  • the sequencing chip can be internally packaged through a special encapsulation and bonding process. A specific cavity is formed.
  • biochemical reaction reagents will enter the chip flow channel sequentially according to the fluid sequence.
  • the reagents react with the DNA on the chip surface.
  • the sequencing instrument can detect the DNA carried on the NDA fragment.
  • the biological information of DNA fragments is obtained through optical and electrical signals to complete the entire sequencing process.
  • the processing technology of most sequencing chips is basically similar.
  • surface chemical treatment is performed on the chip substrate material.
  • Conventional treatment methods mainly include chemical vapor deposition and liquid immersion.
  • the surface uniformity and stability obtained by chemical vapor deposition are The stability is relatively good, but the cost of chemical vapor deposition is relatively high.
  • the liquid phase immersion method is low-cost, but its uniformity and stability are slightly worse.
  • All surface chemical treatment methods use chemical vapor deposition.
  • the processed substrate material and glass need to be packaged and bonded to form a sealed cavity.
  • the main packaging and bonding methods include double-sided adhesive PSA bonding, liquid
  • glue such as UV glue and thermosetting glue
  • the adhesive packaging bonding process are cumbersome and costly; and the surface chemical treatment that has been carried out on the surface of the chip substrate cannot withstand high temperatures, which means that chip packaging It is difficult to use high-temperature bonding processes such as anodic bonding. Therefore, most current mass-produced sequencing chips are mainly bonded by adhesive.
  • the embodiments of this application provide a method for surface chemical treatment and packaging bonding of sequencing chips.
  • This application redesigns the method of preparing sequencing chips, simplifies the operation process, reduces process costs, and realizes the standardization and batch production and processing of sequencing chips.
  • embodiments of the present application provide a method for surface chemical treatment and packaging bonding of sequencing chips, which method includes:
  • the process flow of preparing sequencing chips is redesigned, and the packaging and bonding is carried out from the wafer level, then chemical surface treatment is carried out from the wafer level, and finally the cutting and assembly of individual chips are carried out, which can significantly simplify the operation process and improve production efficiency. and reduce production costs.
  • the wafer substrate and the wafer cover are the core components of the entire chip.
  • One of the functions of the wafer cover is to form a specific flow channel by etching.
  • the main functions of the wafer substrate and the wafer cover are to pass specific.
  • the surface properties of the wafer capture the DNA, and then react the DNA with the reagents in the chip. Finally, the instrument carefully detects the signal on the substrate or cover.
  • the performance of the wafer substrate and wafer cover directly affects the biochemical reaction effect. and test results.
  • the materials of the wafer substrate and the wafer cover are each independently selected from any one or a combination of at least two of quartz glass, ordinary glass or silicon wafer.
  • the thickness of the wafer substrate is 0.5 mm to 1 mm, including but not limited to 0.6 mm, 0.7 mm, 0.8 mm or 0.9 mm.
  • the thickness of the wafer cover is 0.1 mm to 0.5 mm, including but not limited to 0.2 mm, 0.3 mm or 0.4 mm.
  • the method further includes the steps of cleaning the wafer substrate and the wafer cover plate respectively before drilling and etching.
  • the purpose of drilling is to connect the sequencing chip and the sequencing instrument to form the inlet and outlet holes of the chip.
  • the purpose of cleaning is to remove impurities on the substrate and provide a clean surface for subsequent surface treatment.
  • the cleaning method includes immersion cleaning, ultrasonic cleaning or plasma cleaning.
  • the cleaning liquid used in the cleaning includes ultrapure water.
  • the step of drying with inert gas is also included after the cleaning.
  • the inert gas includes nitrogen.
  • the drilling method includes laser drilling, mechanical drilling or sandblasting.
  • the drilling includes forming a liquid inlet hole and a liquid outlet hole.
  • the apertures of the liquid inlet hole and the liquid outlet hole are each independently 0.5mm to 2.0mm, including but not limited to 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.5mm , 1.6mm, 1.7mm, 1.8mm or 1.9mm.
  • the step of ultrasonic cleaning is further included after drilling.
  • the flow channel structure can be designed according to the requirements, and fluid simulation can be used for calculation analysis and optimization.
  • the fluid simulation can use software such as Comsol and Ansys.
  • the structural distribution of the chip on the wafer can be confirmed. According to the above Design the flow channel structure and the distribution of chips on the wafer, and design the corresponding optical mask.
  • the etching includes designing an optical mask according to the required flow channel structure, and using the optical mask to etch the wafer cover.
  • the etching method includes wet etching or dry etching.
  • the depth of the flow channel structure is 0.05 mm to 0.1 mm, including but not limited to 0.06 mm, 0.07 mm, 0.08 mm or 0.09 mm.
  • the depth tolerance control of etching the flow channel of the wafer cover using a mask can be +/-0.5 ⁇ m, +/-1 ⁇ m, or +/-2 ⁇ m, etc.
  • the etched wafer cover plate and the punched wafer substrate are bonded.
  • the entire bonding process requires aligning the wafer cover plate and the wafer substrate in sequence.
  • the wafer cover plate and the wafer substrate are The specific operation processes of laminating the circular substrate, bonding the wafer cover plate and the wafer substrate, and aligning and bonding the wafer cover plate and the wafer substrate can be performed on the wafer aligner. Bonding of the bottom and wafer cover can be performed on a bonding machine.
  • the bonding method includes anodic bonding, laser bonding or thermocompression bonding.
  • the anodic bonding temperature is 200°C to 400°C, including but not limited to 201°C, 202°C, 203°C, 205°C, 210°C, 250°C, 260°C, 280°C, 300°C, 350°C , 360°C, 370°C, 380°C or 390°C.
  • the surface treatment method includes chemical vapor deposition treatment or liquid phase immersion treatment.
  • the reagents in the chemical vapor deposition equipment can diffuse into the cavity inside the bonded wafer through the inlet and outlet holes on the wafer substrate, thereby generating a chemical reaction inside the cavity and depositing on the surface to achieve surface chemistry. Modification effect.
  • the effect of surface treatment forms a hydrophilic surface, a hydrophobic surface or a surface with specific functional groups according to specific needs.
  • the specific functional groups can be amino groups, hydroxyl groups, carboxyl groups, ether bonds, aldehyde groups, carbonyl groups or Other silane groups.
  • the temperature of the chemical vapor deposition process is 25°C to 50°C, including but not limited to 26°C, 27°C, 28°C, 29°C, 30°C, 31°C, 35°C, 36°C, 40°C, 42°C. °C, 44°C, 46°C, 48°C or 49°C
  • the time is 5min ⁇ 60min, including but not limited to 6min, 7min, 8min, 9min, 10min, 15min, 20min, 22min, 26min, 28min, 40min, 45min, 49min, 50min, 52min, 54min, 55min, 56min, 58min or 59min.
  • the method further includes the step of assembling a chip frame to the sequencing chip obtained after cutting.
  • the chip frame not only serves to connect the chip and the instrument platform, but also provides support and protection for the chip.
  • labels, marks or product information can be loaded on the chip frame structure according to actual needs.
  • the chip frame can Whether it is transparent or opaque, the processing method can be mechanical processing or mold injection molding.
  • the chip frame is also cleaned before use.
  • the material of the chip frame is selected from any one of plastic, ceramic or metal.
  • the cutting method may be laser cutting, knife cutting or other mechanical cutting methods.
  • This application also involves subsequent processes for a single sequencing chip formed after cutting, which may include assembling the chip shell, testing of the complete chip, vacuum packaging of the chip, etc.
  • the testing items may include appearance testing, size testing, and chip flow channel gap testing. wait.
  • the method includes the following steps;
  • step (6) Cut the bonded wafer processed in step (5) and assemble the chip frame to obtain a sequencing chip.
  • embodiments of the present application provide a sequencing chip prepared by the method described in the first aspect.
  • the sequencing chip has broad application prospects, such as gene sequencing, hybridization and disease diagnosis.
  • the sequencing chip preparation method provided by the embodiments of this application is based on a wafer-level process. Compared with the traditional single chip processing method, the overall efficiency is improved by nearly dozens of times, the operation is simple, the cost is low, and the use The preparation of sequencing chips is standardized, and the detection and quality control methods are more accurate;
  • the sequencing chip provided by the embodiments of the present application is packaged using a bonding method instead of the traditional gluing method, which significantly simplifies the process and reduces the cost. Moreover, the bonding step of the chip is performed before the surface chemical treatment, which can avoid the chemical reaction on the chip surface. Substances are destroyed during the bonding process;
  • the method provided by the embodiments of this application can further control the chip surface treatment method to chemical vapor deposition treatment, and chemical substances can diffuse into the chip cavity through the inlet and outlet, further improving uniformity and stability.
  • Figure 1 is a top view of an 8-inch wafer substrate according to an embodiment of the present application.
  • 1 in the figure is the wafer substrate, and 2 in the figure is the distribution of the substrate of a single sequencing chip on the 8-inch wafer substrate.
  • Figure 3 in the figure is the substrate for a single sequencing chip.
  • One wafer substrate can be cut out for 36 sequencing chips.
  • 4 in the figure is the liquid inlet or outlet on the substrate. The liquid inlet and outlet are at Distributed diagonally on the substrate of each sequencing chip;
  • Figure 2 is a side view of a single sequencing chip substrate in Figure 1, and 3 in the figure represents the substrate of a single sequencing chip;
  • Figure 3 is a top view of an 8-inch wafer cover according to an embodiment of the present application.
  • 5 in the figure is the wafer cover
  • 6 in the figure is the distribution of the cover of a single sequencing chip on the 8-inch wafer cover.
  • Figure Number 7 in the figure is the cover plate of a single sequencing chip. One wafer cover can be cut out to cover 36 sequencing chips.
  • Figure 8 in the figure is the shape of the flow channel cavity etched inside the cover plate of a single sequencing chip. Each sequencing chip cover plate There is a flow channel cavity on it;
  • Figure 4 is a side view of a single sequencing chip cover in Figure 3, 7 in the figure represents the cover of a single sequencing chip, and 8 in the figure represents the flow channel cavity of a single sequencing chip;
  • Figure 5 is a top view of the distribution of sequencing chips after anodic bonding of the wafer substrate and wafer cover according to an embodiment of the present application.
  • 9 in the figure is the wafer after anodic bonding
  • 10 in the figure is a single sequencing chip at 8 inches. Distribution on the wafer.
  • Figure 11 is a single sequencing chip. One wafer can be cut into 36 sequencing chips.
  • Figure 12 is the flow channel cavity inside a single sequencing chip.
  • Figure 13 is the liquid inlet of a single sequencing chip. hole or outlet;
  • Figure 6 is a diagram of a single sequencing chip in Figure 5.
  • 11 in the figure represents a single sequencing chip
  • 12 in the figure is the flow channel cavity inside a single sequencing chip
  • 13 in the figure is the liquid inlet or outlet hole of a single sequencing chip
  • Figure 7 is a top view of a single sequencing chip according to an embodiment of the present application after being assembled with a chip frame. 14 in the figure represents the complete chip assembled with the chip frame, and 15 in the figure is the chip frame;
  • Figure 8 is a pressure distribution diagram inside the flow channel of the sequencing chip according to an embodiment of the present application.
  • Figure 9 is a stress distribution diagram on the surface of a sequencing chip according to an embodiment of the present application.
  • Figure 10 is a physical diagram of a sequencing chip product according to an embodiment of the present application.
  • connection In this application, unless otherwise clearly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two elements or an interactive relationship between two elements.
  • connection In this application, unless otherwise clearly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two elements or an interactive relationship between two elements.
  • the processing and preparation method of the sequencing chip mainly includes the structural design of the internal flow channel of the chip, drilling of the wafer substrate, etching of the flow channel of the wafer cover, wafer substrate and wafer cover Anodic bonding of plates, surface chemical treatment of wafers after bonding and wafer cutting, etc.
  • the function of the chip frame is first to provide support and protection for the main part of the sequencing chip, and secondly to serve as a connecting part for the contact between the sequencing chip and the sequencing instrument.
  • the material of the chip frame can be engineering plastics, and its types can be polyetheretherketone (PEEK), polyetherimide (PEI), polycarbonate (PC), polyphenylene sulfide ( PPS), polyoxymethylene (POM), polyphenylene ether (PPO), etc.
  • PEEK polyetheretherketone
  • PEI polyetherimide
  • PC polycarbonate
  • PPS polyphenylene sulfide
  • POM polyoxymethylene
  • PPO polyphenylene ether
  • the sequencing chip substrate has a liquid inlet and a liquid outlet.
  • the number of the liquid inlet and liquid outlet is not limited to 1, but can also be 2, 3, or more. to 3.
  • the shapes of the liquid inlet and the liquid outlet on the sequencing chip substrate may be circular, elliptical, square, rectangular, triangular, or polygonal.
  • liquid inlet and liquid outlet on the sequencing chip substrate can be located on the bottom surface.
  • the substrate of the sequencing chip may be made of quartz glass, silicon wafer or ordinary glass.
  • the internal flow channel cavity of the sequencing chip can have a certain flow channel design structure.
  • the shape of this structure has been verified through theoretical calculation simulation and specific experiments, which can effectively solve and improve fluid flow and Distribution uniformity, thereby improving reagent replacement ratio and reaction efficiency.
  • the shape of the flow channel of the sequencing chip can have a streamlined structure.
  • the streamlined structure is not limited to having arc-shaped surfaces on both sides or both ends of the flow channel.
  • the shape can also be circular or elliptical. , parabolic, smooth curve and other structures.
  • the number of flow channels of the sequencing chip is not limited to 1, but can also be 2, 3, or more than 3.
  • the cleaning method of the wafer substrate and the wafer cover may be ultrasonic cleaning, centrifugal oscillation, plasma cleaning, buffer immersion cleaning, etc.
  • the wafer substrate needs further drilling processing after cleaning.
  • the drilling processing methods include laser drilling, sandblasting drilling, mechanical drilling, etc.
  • the purpose of drilling holes on the wafer substrate is to serve as the liquid inlet hole and the liquid outlet hole of the sequencing chip, and the size of the hole diameter is 0.5 mm to 2 mm.
  • the above-mentioned wafer cover plate needs further etching processing after cleaning.
  • the flow channel shape of the wafer cover plate is designed through a mask to form a specific flow channel structure, and the depth of the flow channel is formed into a specific flow channel structure through etching.
  • the etching method of the wafer cover can include wet etching, dry etching, etc.
  • the etching process of the wafer cover is to form the flow channel cavity of the sequencing chip, and the etched flow channel depth can range from 50 ⁇ m to 100 ⁇ m.
  • the etched wafer cover plate and the punched wafer substrate are bonded.
  • the main steps include wafer alignment, wafer bonding, and wafer bonding.
  • the specific bonding method may be anodic bonding, thermocompression bonding, laser bonding, etc.
  • the height of the sealed flow channel cavity ranges from 50 ⁇ m to 100 ⁇ m.
  • the bonded wafer requires further surface treatment to form a surface structure of amino groups.
  • the surface treatment of the wafer substrate and the wafer cover will form specific functionalities. Groups, including hydroxyl group, carboxyl group, ether bond, aldehyde group, carbonyl group, etc.
  • the surface treatment method of the above-mentioned wafer substrate and wafer cover can be chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD).
  • CVD Chemical Vapor Deposition
  • This treatment method can ensure that the wafer substrate and wafer cover are The required functional groups are evenly distributed on the surface, and the stability is relatively good.
  • the surface treatment method of the bonded wafer substrate and wafer cover can also be a liquid phase immersion method. Therefore, the wafer substrate Surface treatment methods for wafer covers mainly include chemical vapor deposition, liquid immersion and other methods.
  • the bonded wafer can be further detected after surface treatment.
  • the detection method can be to test the contact angle of the surface. This method requires destroying some sequencing chips through random inspection.
  • the wafer lining The contact angle between the bottom and the surface of the wafer cover represents the surface tension and surface energy of water.
  • the contact angle can indirectly reflect the degree and quality of the surface treatment effect.
  • it can also The method of directly loading nucleic acid is used to test, and the nucleic acid captured on the chip surface is used to determine whether it has the required functional groups and the density of the surface functional groups.
  • the bonded wafer is cut to form a single sequencing chip, and the cutting method can be laser cutting, knife cutting, mechanical cutting and other methods.
  • the above-mentioned theoretical simulation calculation method of the fluid inside the chip in which the flow of the fluid includes laminar flow, turbulent flow, turbulent flow, etc., as well as the uniformity of the fluid flow and distribution, the method mainly calculates It is not limited to the distribution of flow velocity and streamlines inside the flow channel, the distribution of pressure inside the flow channel, and the stress distribution inside the flow channel and the chip cover.
  • the flow channel design of the sequencing chip will affect the flow and distribution of reagents.
  • the structural design of the flow channel is unreasonable or the surface treatment is uneven, , during the fluid flow process, sometimes the fluid will flow along the local area to form dead volumes and bubbles.
  • the existence of dead volumes will lead to the residue and contamination of reagents.
  • the formation of bubbles will affect biochemical reactions. Both dead volumes and bubbles will seriously affect the overall Therefore, dead volume and bubbles are key considerations in the flow channel design process.
  • This application provides a method for surface chemical treatment and packaging bonding of sequencing chips.
  • the method steps are:
  • the depth of the flow channel structure is 0.05mm, and use fluid simulation to perform calculation analysis and optimization. At the same time, confirm the structural distribution of the chip on the wafer;
  • the etching method uses wet etching.
  • the etching depth is about 50 ⁇ m.
  • the etching precision tolerance can be controlled at +/-2 ⁇ m;
  • Anodicly bond the etched wafer cover and the punched wafer substrate The entire bonding process requires aligning the wafer cover and the wafer substrate in sequence.
  • the wafer cover The specific operations of bonding to the wafer substrate, bonding of the wafer cover and the wafer substrate, and the alignment and bonding of the wafer cover and the wafer substrate are performed on the wafer alignment machine.
  • the method mainly uses markings on the wafer cover and wafer substrate.
  • the bonding of the wafer substrate and the wafer cover is performed on a bonding machine, and the anodic bonding temperature is 200°C;
  • the specific method is to place the bonded wafers in the card slot, and put the card slot containing the wafers into the surface treatment equipment.
  • the treatment method is to use chemical vapor deposition to form the surface structure of the amination group.
  • the temperature of the chemical vapor deposition treatment is 25°C and the time is 60 minutes;
  • This application provides a method for surface chemical treatment and packaging bonding of sequencing chips.
  • the method steps are:
  • the depth of the flow channel structure is 0.07mm, and use fluid simulation to perform calculation analysis and optimization. At the same time, confirm the structural distribution of the chip on the wafer;
  • the etching method uses wet etching.
  • the etching depth is about 50 ⁇ m.
  • the etching precision tolerance can be controlled at +/-2 ⁇ m;
  • Anodicly bond the etched wafer cover and the punched wafer substrate The entire bonding process requires aligning the wafer cover and the wafer substrate in sequence.
  • the wafer cover The specific operations of bonding to the wafer substrate, bonding of the wafer cover and the wafer substrate, and the alignment and bonding of the wafer cover and the wafer substrate are performed on the wafer alignment machine.
  • the main method is to use markings on the wafer cover and wafer substrate.
  • the bonding of the wafer substrate and the wafer cover is performed on a bonding machine, and the anodic bonding temperature is 300°C;
  • the specific method is to place the bonded wafers in the card slot, and put the card slot containing the wafers into the surface treatment equipment.
  • the treatment method is to use chemical vapor deposition to form the surface structure of the amino group.
  • the temperature of the chemical vapor deposition treatment is 45°C and the time is 20 minutes;
  • the single sequencing chip formed after the above cutting is subjected to subsequent processes, including assembling the chip frame, inspection of the complete chip (testing the contact angle of the surface, the surface contact angle is 120°) and vacuum packaging of the chip.
  • This application provides a method for surface chemical treatment and packaging bonding of sequencing chips.
  • the method steps are:
  • Drill the wafer substrate The specific method is to use laser drilling. Drill two holes with a diameter of 2 mm. They can be used as liquid inlets or liquid outlets respectively. On the substrate of each sequencing chip It is distributed diagonally on the surface. After drilling, it is ultrasonically cleaned and dried with high nitrogen gas;
  • the depth of the flow channel structure is 0.1mm, and use fluid simulation to perform calculation analysis and optimization. At the same time, confirm the structural distribution of the chip on the wafer;
  • the etching method uses wet etching.
  • the etching depth is about 50 ⁇ m.
  • the etching precision tolerance can be controlled at +/-2 ⁇ m;
  • Anodicly bond the etched wafer cover and the punched wafer substrate The entire bonding process requires aligning the wafer cover and the wafer substrate in sequence.
  • the wafer cover The specific operations of bonding to the wafer substrate, bonding of the wafer cover and the wafer substrate, and the alignment and bonding of the wafer cover and the wafer substrate are performed on the wafer alignment machine.
  • the main method is to use markings on the wafer cover and wafer substrate.
  • the bonding of the wafer substrate and the wafer cover is performed on a bonding machine, and the anodic bonding temperature is 400°C;
  • the specific method is to place the bonded wafers in the card slot, and put the card slot containing the wafers into the surface treatment equipment.
  • the treatment method is to use chemical vapor deposition to form the surface structure of the amino group.
  • the temperature of the chemical vapor deposition treatment is 50°C and the time is 5 minutes;
  • the single sequencing chip formed after the above cutting is subjected to subsequent processes, including assembling the chip frame, inspection of the complete chip (testing the contact angle of the surface, the surface contact angle is 60°) and vacuum packaging of the chip.
  • Figure 1 is a top view of an 8-inch wafer substrate.
  • Figure 1 is the wafer substrate.
  • Figure 2 is the substrate of a single sequencing chip on an 8-inch wafer. The distribution on the substrate.
  • 3 in the picture is the substrate of a single sequencing chip. One wafer substrate can be cut out for 36 sequencing chips.
  • 4 in the picture is the liquid inlet or outlet on the substrate. The liquid inlet and outlet are diagonally distributed on the substrate of each sequencing chip;
  • 2 in the figure is a side view of a single sequencing chip substrate in Figure 1, and 3 in the figure represents the substrate of a single sequencing chip;
  • Figure 3 This is a top view of the 8-inch wafer cover of this application.
  • Figure 6 is the distribution of the cover plate of a single sequencing chip on the 8-inch wafer cover.
  • Figure 7 is the cover plate of a single sequencing chip.
  • Figure 8 shows the shape of the flow channel cavity etched inside a single sequencing chip cover. There is a flow channel cavity on each sequencing chip cover;
  • Figure 4 shows the single flow channel cavity in Figure 3.
  • Side view of the sequencing chip cover. 7 in the figure represents the cover of a single sequencing chip, and 8 in the figure represents the flow channel cavity of a single sequencing chip.
  • Figure 5 shows the sequencing after anodic bonding of the wafer substrate and the wafer cover.
  • Top view of chip distribution Figure 10 shows the distribution of a single sequencing chip on an 8-inch wafer.
  • Figure 11 shows a single sequencing chip.
  • Figure 12 shows the flow inside a single sequencing chip.
  • Channel cavity, 13 in the figure is the inlet or outlet hole of a single sequencing chip
  • Figure 6 is a diagram of a single sequencing chip in Figure 5, 11 in the figure represents a single sequencing chip, and 12 in the figure is the flow inside a single sequencing chip Channel cavity, 13 in the figure is the inlet or outlet hole of a single sequencing chip
  • Figure 7 is a top view of a single sequencing chip after being assembled with the chip frame, 14 in the figure represents the complete chip assembled with the chip frame, 15 in the figure is chip frame.
  • the pressure distribution inside the prepared sequencing chip flow channel and the stress distribution on the chip surface were analyzed. The results are shown in Figures 8 and 9.
  • the pressure distribution inside the chip flow channel uses different color depths to represent the pressure. From As can be seen in Figure 8, the pressure distribution is mainly from the liquid inlet to the liquid outlet, and the pressure gradually increases. This is due to the negative pressure pumping mode of the sequencing instrument itself. However, the maximum pressure in the chip flow channel The difference between the pressure and the minimum pressure is very small. A small pressure difference can reduce the load on the flow path of the sequencing instrument. At the same time, the uniform pressure inside the chip can reduce the variability of biochemical reagent reactions in different areas of the chip surface.
  • the stress distribution on the chip surface uses different color depths to represent the magnitude of the stress.
  • the stress distribution at other positions is very uniform, and the stress at the edge position is larger.
  • the multi-phase interface formed by the chip substrate, chip cover, pressure-sensitive adhesive, and liquid reagent is formed under the action of external forces.
  • the area at the edge where the stress is relatively large is smaller, which also means that the affected area is smaller.
  • the method for preparing sequencing chips of this application has a simple process, can perform batch surface treatment and packaging, significantly improves production efficiency and capacity, and reduces costs.
  • the flow channel design of this application is relatively reasonable and can effectively weaken the edge effect of the chip flow channel. Reduce the deformation of the chip cover and flow channel, reduce the difference in biochemical reactions at the chip inlet, outlet and different areas, thereby improving the overall performance of the sequencing chip.
  • this application carries out packaging bonding and surface treatment from the wafer level, and finally cuts and assembles a single chip, which can solve the relevant technical problems existing in the current sequencing chip preparation and simplify the operation process on this basis. Reduce process costs and significantly improve production efficiency and capacity.

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Abstract

用于测序芯片表面化学处理及封装键合的方法。所述方法包括:对晶圆基底进行打孔，在晶圆盖板蚀刻流道结构，将打孔后的晶圆基底和蚀刻后晶圆盖板进行键合，得到键合晶圆，对键合晶圆进行表面处理，进行切割，得到所述测序芯片。从晶圆级别进行封装键合以及表面处理，最后进行单个芯片的切割和组装，能够解决目前测序芯片制备中存在的相关技术问题，并且在此基础上简化操作流程，降低工艺成本，显著提高生产效率和产能。

Description

一种用于测序芯片表面化学处理及封装键合的方法 技术领域
本申请涉及基因测序技术领域，例如一种用于测序芯片表面化学处理及封装键合的方法。
背景技术
基因测序是一种新型基因检测技术，整个平台系统包括测序仪器，生化反应试剂和基因测序芯片等，通过相互配合来完成测序全流程，测序芯片是基因测序系统的重要耗材和载体，测序芯片表面需要经过一定化学修饰而形成特定的基团，此化学基团能够捕捉所要检测的DNA片段，并且可以将DNA片段稳定的固定在其表面，同时，测序芯片经过特殊的封装键合工艺可以在内部形成特定的腔体，在测序仪器液路系统的驱动下下，生化反应试剂会根据流体时序依次进入芯片流道中，试剂和芯片表面的DNA进行反应，测序仪器可以通过检测NDA片段上所携带的光学以及电学信号而获取DNA片段的生物信息，从而完成整个测序流程。
目前，大部分测序芯片的加工处理工艺基本类似，首先在芯片衬底材料上面进行表面化学处理，常规的处理方法主要包括化学气相沉积和液相浸泡法，化学气相沉积获得的表面均匀性和稳定性比较好，不过化学气相沉积的成本相对比较高，液相浸泡的方法成本低廉，不过其均匀性和稳定性略差一些，相比于液相浸泡的方法，目前大部分的量产测序芯片的表面化学处理方法均采用化学气相沉积的方式。
芯片的衬底材料在进行表面化学处理后，需要将处理后的衬底材料和玻璃进行封装键合而形成密封的腔体，目前主要的封装键合方法包括双面胶PSA的粘结，液体胶水(例如UV胶和热固胶)的粘结，胶粘的封装键合工艺比较繁琐，且成本比较高；且芯片衬底表面已经进行的表面化学处理无法承受高温，这就意味着芯片封装难以采用阳极键合等高温键合工艺，因此，目前大部分的量产测序芯片的键合方式主要是胶粘的方式。经过上述的芯片衬底材料的表面化学处理，胶粘的封装键合，然后再对单个的芯片进行后续的组装，整个流程的工序比较多，导致操作比较繁琐和良率下降，并且芯片的封装键合是基于单 个芯片，整体产能也比较受限。
综上所述，基于基因测序芯片开发和生产中存在的技术问题，亟需开新的测序芯片的制备方法，以提高基因测序芯片的产能和降低基因测序芯片的成本。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供一种用于测序芯片表面化学处理及封装键合的方法，本申请重新设计制备测序芯片的方法，简化操作流程，降低工艺成本，实现测序芯片的标准化和批量化生产加工。
第一方面，本申请实施例提供一种用于测序芯片表面化学处理及封装键合的方法，所述方法包括：
对晶圆衬底进行打孔，在晶圆盖板蚀刻流道结构，将打孔后的晶圆衬底和蚀刻后晶圆盖板进行键合，得到键合晶圆，对键合晶圆进行表面处理，进行切割，得到所述测序芯片。
本申请中，重新设计制备测序芯片工艺流程，从晶圆级别进行封装键合，然后从晶圆级别进行化学的表面处理，最后进行单个芯片的切割和组装，能够显著简化操作流程、提高生产效率并降低生产成本。
本申请中，晶圆衬底和晶圆盖板是整个芯片的核心部件，晶圆盖板其中一个作用是蚀刻形成特定的流道，晶圆衬底和晶圆盖板的主要功能是通过特定的表面属性将DNA进行捕获，然后使DNA和芯片中的试剂进行反应，最后仪器对基板或者盖板上的信号尽心检测，晶圆衬底和晶圆盖板的性能好坏直接影响生化反应效果和测试结果。
优选地，所述晶圆衬底和晶圆盖板的材质各自独立地选自石英玻璃、普通玻璃或硅片中任意一种或至少两种的组合。
优选地，所述晶圆衬底的厚度为0.5mm～1mm，包括但不限于0.6mm、0.7mm、0.8mm或0.9mm。
优选地，所述晶圆盖板的厚度为0.1mm～0.5mm，包括但不限于0.2mm、0.3mm或0.4mm。
优选地，所述方法还包括在打孔和蚀刻前分别对晶圆衬底和晶圆盖板进行 清洗的步骤。
本申请中，打孔的目的是为了使测序芯片和测序仪器相连通，形成芯片的进液孔和出液孔，清洗的作用是去除基板上面的杂质，为后续的表面处理提供洁净的表面。
优选地，所述清洗的方式包括浸泡清洗、超声清洗或等离子清洗。
优选地，所述清洗使用的清洗液包括超纯水。
优选地，所述清洗后还包括使用惰性气体吹干的步骤。
优选地，所述惰性气体包括氮气。
优选地，所述打孔的方法包括激光打孔、机械打孔或喷砂打孔。
优选地，所述打孔包括形成进液孔和出液孔。
优选地，所述进液孔和出液孔的孔径各自独立地为0.5mm～2.0mm，包括但不限于0.6mm、0.7mm、0.8mm、0.9mm、1mm、1.2mm、1.4mm、1.5mm、1.6mm、1.7mm、1.8mm或1.9mm。
优选地，所述打孔后还包括进行超声清洗的步骤。
本申请中，可根据需求设计流道结构，并利用流体的模拟仿真进行计算分析和优化，流体的模拟仿真可以采用Comsol和Ansys等软件，同时，确认芯片在晶圆上的结构分布，根据上述的流道结构设计和芯片在晶圆上的分布，设计对应的光学掩膜版。
优选地，所述蚀刻包括根据所需流道结构设计光学掩膜版，利用所述光学掩膜版对晶圆盖板进行蚀刻。
优选地，所述蚀刻的方法包括湿法刻蚀或干法刻蚀。
优选地，所述流道结构的深度为0.05mm～0.1mm，包括但不限于0.06mm、0.07mm、0.08mm或0.09mm。
本申请中，利用掩膜版对晶圆盖板进行流道的蚀刻加工的深度公差控制可以是+/-0.5μm、+/-1μm或+/-2μm等。
本申请中，蚀刻好的晶圆盖板和打孔好的晶圆衬底进行键合，整个键合过程需要依次进行晶圆盖板和晶圆衬底进行对准，晶圆盖板和晶圆衬底的贴合，晶圆盖板和晶圆衬底的键合，晶圆盖板和晶圆衬底对准和贴合的具体操作过程可以在晶圆对准机上进行，晶圆衬底和晶圆盖板的键合可以在键合机上进行。
优选地，所述键合的方法包括阳极键合、激光键合或热压键合。
优选地，所述阳极键合的温度为200℃～400℃，包括但不限于201℃、202℃、203℃、205℃、210℃、250℃、260℃、280℃、300℃、350℃、360℃、370℃、380℃或390℃。
优选地，所述表面处理的方法包括化学气相沉积处理或液相浸泡处理。
本申请中，化学气相沉积设备中的试剂可以通过晶圆衬底上面的进出液孔扩散到键合后晶圆内部的腔体，从而在腔体内部产生化学反应而沉积到表面，达到表面化学修饰的效果。
本申请中，表面处理的效果根据具体需求形成亲水性表面、疏水性表面或具有特定官能基团的表面，具体的官能基团可以是氨基、羟基、羧基、醚键、醛基、羰基或其他硅烷基团。
优选地，所述化学气相沉积处理的温度为25℃～50℃，包括但不限于26℃、27℃、28℃、29℃、30℃、31℃、35℃、36℃、40℃、42℃、44℃、46℃、48℃或49℃，时间为5min～60min，包括但不限于6min、7min、8min、9min、10min、15min、20min、22min、26min、28min、40min、45min、49min、50min、52min、54min、55min、56min、58min或59min。
优选地，所述方法还包括向切割后得到的测序芯片组装芯片框架的步骤。
本申请中，芯片框架不仅起到芯片和仪器平台的连接作用，同时还为芯片提供支撑和保护作用，另外，芯片框架结构件上可以根据实际需求加载标签，标记或者产品信息等，芯片框架可以是透明或者不透明，加工方式可以是机械加工或开模注塑等。
本申请中，所述芯片框架使用前同样进行清洗。
所述芯片框架的材质选自塑料、陶瓷或金属中任意一种。
本申请中，切割方法可以是激光切割、刀切割或者其他机械切割方法。
本申请中，还涉及切割后形成的单个测序芯片进行后续的工艺，可包括装配芯片外壳、完整芯片的检测、芯片的真空包装等，检测项目可包括外观检测、尺寸检测、芯片流道间隙检测等。
作为优选的技术方案，所述方法包括以下步骤；
(1)对晶圆衬底和晶圆盖板进行超声清洗；
(2)对晶圆衬底进行打孔并进行超声清洗；
(3)根据所需流道结构设计光学掩膜版，利用所述光学掩膜版对晶圆盖板 进行蚀刻；
(4)将打孔后的晶圆衬底和蚀刻后的晶圆盖板进行键合，得到键合晶圆；
(5)对所述键合晶圆进行化学气相沉积处理或液相浸泡处理；
(6)将步骤(5)处理后的键合晶圆进行切割，并组装芯片框架，得到测序芯片。
第二方面，本申请实施例提供一种测序芯片，所述测序芯片由第一方面所述的方法制备得到。
本发中，所述测序芯片具有广泛应用前景，例如基因测序、杂交及疾病诊断等。
与相关技术相比，本申请实施例具有以下有益效果：
(1)本申请实施例提供的测序芯片制备方法，整体基于晶圆级别的工艺流程，相比于传统单个芯片的加工方式，整体的效率提高近几十倍，操作简便、成本低，且使测序芯片的制备标准化，检测和质控方式更加准确；
(2)本申请实施例提供的测序芯片的封装采用键合方法取代传统胶粘的方式，显著简化工艺、降低成本，并且芯片的键合步骤在表面化学处理之前进行，可以避免芯片表面的化学物质在键合过程中受到破坏；
(3)本申请实施例提供的方法可进一步控制芯片表面处理方式为化学气相沉积处理，化学物质可以通过进出液口扩散到芯片腔体，进一步提高均匀性和稳定性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本文技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本文的技术方案，并不构成对本文技术方案的限制。
图1为本申请一实施例的8英寸晶圆衬底的俯视图，图中1为晶圆衬底，图中2为单个测序芯片的衬底在8英寸晶圆衬底上面的分布情况，图中3为单个测序芯片的衬底，一个晶圆衬底可以切割出来36个测序芯片的衬底，图中4为衬底上的进液口或出液口，进液口和出液口在每个测序芯片的衬底上呈对角分布；
图2为图1中单个测序芯片衬底的侧视图，图中3代表单个测序芯片的衬底；
图3为本申请一实施例的8英寸晶圆盖板的俯视图，图中5为晶圆盖板，图中6为单个测序芯片的盖板在8英寸晶圆盖板上面的分布情况，图中7为单个测序芯片的盖板，一个晶圆盖板可以切割出来36个测序芯片的盖板，图中8为单个测序芯片盖板内部蚀刻的流道腔体形状，每个测序芯片盖板上面有一个流道腔体；
图4为图3中单个测序芯片盖板的侧视图，图中7代表单个测序芯片的盖板，图中8代表单个测序芯片的流道腔体；
图5为本申请一实施例的晶圆衬底和晶圆盖板阳极键合后的测序芯片分布俯视图，图中9为阳极键合后的晶圆，图中10为单个测序芯片在8英寸晶圆上面的分布情况，图中11为单个测序芯片，一个晶圆可以切割出来36个测序芯片，图中12为单个测序芯片内部的流道腔体，图中13为单个测序芯片的进液孔或出液孔；
图6为图5中的单个测序芯片图，图中11代表单个测序芯片，图中12为单个测序芯片内部的流道腔体，图中13为单个测序芯片的进液孔或出液孔；
图7为本申请一实施例的单个测序芯片组装上芯片框架之后的俯视图，图中14代表组装有芯片框架的完整芯片，图中15为芯片框架；
图8为本申请一实施例的测序芯片流道内部的压力分布图；
图9为本申请一实施例的测序芯片表面的应力分布图；
图10为本申请一实施例的测序芯片产品实物图。
具体实施方式
为进一步阐述本申请所采取的技术手段及其效果，以下结合实施例和附图对本申请作进一步地说明。可以理解的是，此处所描述的具体实施方式仅仅用于解释本申请，而非对本申请的限定。
实施例中未注明具体技术或条件者，按照本领域内的文献所描述的技术或条件，或者按照产品说明书进行。所用试剂或仪器未注明生产厂商者，均为可通过正规渠道商购获得的常规产品。
在本申请中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、 “固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
本申请的具体实施方式中，测序芯片的加工制备方法，主要包括芯片内部流道的结构设计，晶圆衬底的打孔，晶圆盖板的流道蚀刻，晶圆衬底和晶圆盖板的阳极键合，键合后晶圆的表面化学处理和晶圆的切割等。
本申请的具体实施方式中，芯片框架的功能首先为测序芯片的主体部分提供支撑和保护，其次作为测序芯片和测序仪器接触的连接部分。
本申请的具体实施方式中，芯片框架的材质可以是工程塑料，其种类可以是聚醚醚酮(PEEK)、聚醚酰亚胺(PEI)、聚碳酸酯(PC)、聚苯硫醚(PPS)、聚甲醛(POM)、聚苯醚(PPO)等。
本申请的具体实施方式中，测序芯片衬底具有进液口和出液口，所述的进液口和出液口的数量不局限于1个，还可以是2个，3个，或者多于3个。
本申请的具体实施方式中，测序芯片衬底上的进液口和出液口的形状可以是圆形、椭圆形、正方形、长方形、三角形以及多边形。
本申请的具体实施方式中，测序芯片衬底上的进液口和出液口，其所在位置可以在底面。
本申请的具体实施方式中，测序芯片的衬底，其材质可以是石英玻璃、硅片或普通玻璃。
本申请的具体实施方式中，测序芯片的内部的流道腔体可以具有一定的流道设计结构，此结构的形状经过理论的计算模拟和具体的实验验证，可以有效的解决和改善流体流动和分布的均匀性，从而提高试剂的替换比和反应效率。
本申请的具体实施方式中，测序芯片流道的形状可以具有流线型结构，其中，此流线型结构不局限于流道两侧或者两端具有圆弧形曲面的其形状还可以是圆形，椭圆形，抛物线形，圆滑的曲线等结构。
本申请的具体实施方式中，测序芯片的流道数量不局限于1个，还可以是2个，3个，或者多于3个。
本申请的具体实施方式中，晶圆衬底和晶圆盖板的清洗，清洗方式可以为超声清洗、离心震荡的方法、等离子清洗的方法、缓冲液浸泡清洗的方法等。
本申请的具体实施方式中，晶圆衬底在清洗之后需要进一步打孔加工，打孔加工的方法包括激光打孔、喷砂打孔、机械钻孔等。
本申请的具体实施方式中，晶圆衬底上打孔的目的是作为测序芯片的进液孔和出液孔，孔径的尺寸为0.5mm～2mm。
本申请的具体实施方式中，上述晶圆盖板在清洗之后需要进一步蚀刻加工，晶圆盖板的流道形状通过掩膜版设计形成特定的流道结构，而流道的深度通过蚀刻形成特定深度的流道，晶圆盖板的蚀刻方式可以包括湿法刻蚀，干法刻蚀等。
本申请的具体实施方式中，晶圆盖板蚀刻加工是形成测序芯片的流道腔体，蚀刻的流道深度范围可以为50μm～100μm。
本申请的具体实施方式中，蚀刻后的晶圆盖板和打孔的晶圆衬底进行键合，主要步骤包括晶圆的对准，晶圆的贴合和晶圆的键合等步骤。
本申请的具体实施方式中，具体键合方式可以是阳极键合，热压键合和激光键合等。
本申请的具体实施方式中，晶圆衬底和晶圆盖板键合后形成的流道腔体，密封的流道腔体高度范围为50μm-100μm。
本申请的具体实施方式中，键合后的晶圆需要进一步表面处理形成氨基化基团的表面结构，在其他实施例中，晶圆衬底和晶圆盖板的表面处理会形成特定的官能基团，包括羟基、羧基、醚键、醛基、羰基等。
本申请的具体实施方式中，上述晶圆衬底和晶圆盖板的表面处理的方法可以为化学气相沉积(Chemical Vapor Deposition简称CVD)，此处理方法可以保证晶圆衬底和晶圆盖板的表面形成均匀分布的所需的官能团，并且稳定性比较好，此外，键合后的晶圆衬底和晶圆盖板表面处理方法还可以是液相浸泡的方法，因此，晶圆衬底和晶圆盖板的表面处理方法主要包括化学气相沉积，液相浸泡等方法。
本申请的具体实施方式中，键合后的晶圆在表面处理之后，可进一步的检测，检测方法可以是测试表面的接触角，此方法需要通过抽检的方式破坏掉部分测序芯片，晶圆衬底和晶圆盖板表面的接触角代表对水的表面张力和表面能，接触角可以间接的反映表面处理效果的程度和好坏，除了采用接触角的方法间接测量表面处理的效果，还可以采用直接加载核酸的方法测试，根据芯片表面 捕获核酸的情况判断是否具有所要的官能团，以及表面官能团的密度。
本申请的具体实施方式中，键合后的晶圆切割形成单个的测序芯片，切割方式可以是激光切割、刀切割和机械切割等方法。
本申请的具体实施方式中，上述的芯片内部流体的理论模拟计算方法，其中流体的流动包括层流，湍流，紊流等情况，以及所述的流体流动和分布的均匀性，其方法主要计算不局限于流道内部流速以及流线的分布情况，流道内部压力的分布情况，流道内部以及芯片盖板的应力分布情况。
本申请的具体实施方式中，测序芯片的流道设计会影响试剂的流动和分布，目前很多类似的微流控的芯片和流道中，如果流道的结构设计不合理，或者表面处理的不均匀，在流体流动过程中，有时候流体会沿着局部流动而形成死体积和气泡，死体积的存在会导致试剂的残留和污染，气泡的形成会影响生化反应，死体积和气泡都会严重影响整体的测试效果，因此，死体积和气泡是流道设计过程中重点考虑的因素。
另外，流道设计的不合理会影响测序试剂在测序芯片中的替换比，从而间接的导致试剂用量的增多，测序仪器抽液时间的延长，测序效率的下降，因此，测序芯片内部的流道结构设计对测序芯片和系统的整体性能至关重要。
实施例1
本申请提供一种用于测序芯片表面化学处理及封装键合的方法，所述方法步骤为：
(1)对芯片框架进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面；
(2)对晶圆衬底(石英玻璃材质，厚度0.5mm)和晶圆盖板(普通玻璃材质，厚度0.1mm)进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面，晶圆的保存在氮气柜里面；
(3)对晶圆衬底进行打孔加工处理，具体方式采用激光打孔，打2个孔，孔径均为0.5mm，可分别作为进液口或出液口，在每个测序芯片的衬底上呈对角分布，打孔完之后再对其进行超声清洗和高出氮气吹干处理；
(4)设计测序芯片的的流道结构，流道结构的深度为0.05mm，并利用流体的模拟仿真进行计算分析和优化，同时，确认芯片在晶圆上的结构分布；
(5)根据上述的芯片流道结构设计和芯片在晶圆上的分布，设计对应的光 学掩膜版，并进行掩膜版的加工制备；
(6)利用上述的掩膜版对晶圆盖板进行蚀刻加工，蚀刻的方法采用湿法刻蚀，蚀刻深度大约50μm，蚀刻的精度公差可以控制在+/-2μm；
(7)将上述蚀刻好的晶圆盖板和打孔好的晶圆衬底进行阳极键合，整个键合过程需要依次进行晶圆盖板和晶圆衬底进行对准，晶圆盖板和晶圆衬底的贴合，晶圆盖板和晶圆衬底的键合，晶圆盖板和晶圆衬底对准和贴合的具体操作过程在晶圆对准机上进行，对准方式主要是采用晶圆盖板和晶圆衬底上的标识，晶圆衬底和晶圆盖板的键合是在键合机上进行，阳极键合的温度为200℃；
(8)对上述键合好的晶圆进行表面化学处理，具体方式是将键合后的晶圆放在卡槽里，将装有晶圆的卡槽放入到表面处理的设备中，表面处理方法为采用化学气相沉积的方法形成氨基化基团的表面结构，化学气相沉积处理的温度为25℃，时间为60min；
(9)将上述键合与化学气相沉积表面处理后的晶圆进行激光切割，从而形成单个的测序芯片；
(10)将上述切割后形成的单个测序芯片进行后续的工艺，包括装配芯片框架，完整芯片的检测(测试表面的接触角，表面接触角为80°)和芯片的真空包装，最终得到成品芯片如图10所示。
实施例2
本申请提供一种用于测序芯片表面化学处理及封装键合的方法，所述方法步骤为：
(1)对芯片框架进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面；
(2)对晶圆衬底(硅片材质，厚度0.8mm)和晶圆盖板(普通玻璃材质，厚度0.4mm)进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面，晶圆的保存在氮气柜里面；
(3)对晶圆衬底进行打孔加工处理，具体方式采用激光打孔，打2个孔，孔径均为0.9mm，可分别作为进液口或出液口，在每个测序芯片的衬底上呈对角分布，打孔完之后再对其进行超声清洗和高出氮气吹干处理；
(4)设计测序芯片的的流道结构，流道结构的深度为0.07mm，并利用流体的模拟仿真进行计算分析和优化，同时，确认芯片在晶圆上的结构分布；
(5)根据上述的芯片流道结构设计和芯片在晶圆上的分布，设计对应的光学掩膜版，并进行掩膜版的加工制备；
(6)利用上述的掩膜版对晶圆盖板进行蚀刻加工，蚀刻的方法采用湿法刻蚀，蚀刻深度大约50μm，蚀刻的精度公差可以控制在+/-2μm；
(7)将上述蚀刻好的晶圆盖板和打孔好的晶圆衬底进行阳极键合，整个键合过程需要依次进行晶圆盖板和晶圆衬底进行对准，晶圆盖板和晶圆衬底的贴合，晶圆盖板和晶圆衬底的键合，晶圆盖板和晶圆衬底对准和贴合的具体操作过程在晶圆对准机上进行，对准方式主要是采用晶圆盖板和晶圆衬底上的标识，晶圆衬底和晶圆盖板的键合是在键合机上进行，阳极键合的温度为300℃；
(8)对上述键合好的晶圆进行表面化学处理，具体方式是将键合后的晶圆放在卡槽里，将装有晶圆的卡槽放入到表面处理的设备中，表面处理方法为采用化学气相沉积的方法形成氨基化基团的表面结构，化学气相沉积处理的温度为45℃，时间为20min；
(9)将上述键合与化学气相沉积表面处理后的晶圆进行激光切割，从而形成单个的测序芯片；
(10)将上述切割后形成的单个测序芯片进行后续的工艺，包括装配芯片框架，完整芯片的检测(测试表面的接触角，表面接触角为120°)和芯片的真空包装。
实施例3
本申请提供一种用于测序芯片表面化学处理及封装键合的方法，所述方法步骤为：
(1)对芯片框架进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面；
(2)对晶圆衬底(普通玻璃材质，厚度1mm)和晶圆盖板(石英玻璃材质，厚度0.5mm)进行超声清洗，清洗过程中采用超纯水，清洗之后，采用高纯氮气吹干晶圆的表面，晶圆的保存在氮气柜里面；
(3)对晶圆衬底进行打孔加工处理，具体方式采用激光打孔，打2个孔，孔径均为2mm，可分别作为进液口或出液口，在每个测序芯片的衬底上呈对角分布，打孔完之后再对其进行超声清洗和高出氮气吹干处理；
(4)设计测序芯片的的流道结构，流道结构的深度为0.1mm，并利用流体 的模拟仿真进行计算分析和优化，同时，确认芯片在晶圆上的结构分布；
(5)根据上述的芯片流道结构设计和芯片在晶圆上的分布，设计对应的光学掩膜版，并进行掩膜版的加工制备；
(6)利用上述的掩膜版对晶圆盖板进行蚀刻加工，蚀刻的方法采用湿法刻蚀，蚀刻深度大约50μm，蚀刻的精度公差可以控制在+/-2μm；
(7)将上述蚀刻好的晶圆盖板和打孔好的晶圆衬底进行阳极键合，整个键合过程需要依次进行晶圆盖板和晶圆衬底进行对准，晶圆盖板和晶圆衬底的贴合，晶圆盖板和晶圆衬底的键合，晶圆盖板和晶圆衬底对准和贴合的具体操作过程在晶圆对准机上进行，对准方式主要是采用晶圆盖板和晶圆衬底上的标识，晶圆衬底和晶圆盖板的键合是在键合机上进行，阳极键合的温度为400℃；
(8)对上述键合好的晶圆进行表面化学处理，具体方式是将键合后的晶圆放在卡槽里，将装有晶圆的卡槽放入到表面处理的设备中，表面处理方法为采用化学气相沉积的方法形成氨基化基团的表面结构，化学气相沉积处理的温度为50℃，时间为5min；
(9)将上述键合与化学气相沉积表面处理后的晶圆进行激光切割，从而形成单个的测序芯片；
(10)将上述切割后形成的单个测序芯片进行后续的工艺，包括装配芯片框架，完整芯片的检测(测试表面的接触角，表面接触角为60°)和芯片的真空包装。
结合图1～图7对测序芯片制备进行进一步说明，图1为8英寸晶圆衬底的俯视图，图中1为晶圆衬底，图中2为单个测序芯片的衬底在8英寸晶圆衬底上面的分布情况，图中3为单个测序芯片的衬底，一个晶圆衬底可以切割出来36个测序芯片的衬底，图中4为衬底上的进液口或出液口，进液口和出液口在每个测序芯片的衬底上呈对角分布；图中2为图1中单个测序芯片衬底的侧视图，图中3代表单个测序芯片的衬底；图3为本申请8英寸晶圆盖板的俯视图，图中6为单个测序芯片的盖板在8英寸晶圆盖板上面的分布情况，图中7为单个测序芯片的盖板，一个晶圆盖板可以切割出来36个测序芯片的盖板，图中8为单个测序芯片盖板内部蚀刻的流道腔体形状，每个测序芯片盖板上面有一个流道腔体；图4为图3中单个测序芯片盖板的侧视图，图中7代表单个测序芯片的盖板，图中8代表单个测序芯片的流道腔体；图5为晶圆衬底和晶圆盖板 阳极键合后的测序芯片分布俯视图，图中10为单个测序芯片在8英寸晶圆上面的分布情况，图中11为单个测序芯片，一个晶圆可以切割出来36个测序芯片，图中12为单个测序芯片内部的流道腔体，图中13为单个测序芯片的进液孔或出液孔；图6为图5中的单个测序芯片图，图中11代表单个测序芯片，图中12为单个测序芯片内部的流道腔体，图中13为单个测序芯片的进液孔或出液孔；图7为单个测序芯片组装上芯片框架之后的俯视图，图中14代表组装有芯片框架的完整芯片，图中15为芯片框架。
此外，对制备的测序芯片流道内部的压力分布和芯片表面的应力分布进行分析，结果如图8和图9所示，芯片流道内部的压力分布，采用不同颜色深度表示压力的大小，从图8中可以看出，压力分布主要是从进液口到出液口方向，压力逐渐增大的趋势，这是由于本身测序仪器的负压抽液模式导致，不过，芯片流道中的最大压力和最小压力之间的差值非常小，压力差值较小可以降低测序仪器流路的负载，同时芯片内部压力的均匀可以降低芯片表面不同区域生化试剂反应的差异性。芯片表面的应力分布，采用不同颜色深度表示应力的大小，从图9中可以看出，芯片流道内部，除了边缘位置之外，其他位置的应力分布非常均匀，而边缘位置的应力较大，主要是因为芯片基板，芯片盖板，压敏胶，液体试剂形成的多相界面处在外力作用下形成的，不过应力比较大的边缘位置的区域较小，也意味着受影响区域较小。
本申请的制备测序芯片的方法，工艺简单，能够进行批量化表面处理和封装，显著提高生产效率和产能，降低成本，本申请流道设计比较合理，可以有效的减弱芯片流道的边缘效应，减小芯片盖板和流道的形变，减小芯片进液口，出液口以及不同区域的生化反应差异性，从而可以整体提高测序芯片的性能。
综上所述，本申请从晶圆级别进行封装键合以及表面处理，最后进行单个芯片的切割和组装，能够解决目前测序芯片制备中存在的相关技术问题，并且在此基础上简化操作流程，降低工艺成本，显著提高生产效率和产能。
申请人声明，本申请通过上述实施例来说明本申请的详细方法，但本申请并不局限于上述详细方法，即不意味着本申请必须依赖上述详细方法才能实施。所属技术领域的技术人员应该明了，对本申请的任何改进，对本申请产品各原料的等效替换及辅助成分的添加、具体方式的选择等，均落在本申请的保护范围和公开范围之内。

Claims (12)

  1. 一种用于测序芯片表面化学处理及封装键合的方法，其包括：
    对晶圆衬底进行打孔，在晶圆盖板蚀刻流道结构，将打孔后的晶圆衬底和蚀刻后晶圆盖板进行键合，得到键合晶圆，对键合晶圆进行表面处理，进行切割，得到所述测序芯片。
  2. 根据权利要求1所述的方法，其中，所述晶圆衬底和晶圆盖板的材质各自独立地选自石英玻璃、普通玻璃或硅片中任意一种或至少两种的组合。
  3. 根据权利要求1或2所述的方法，其中，所述晶圆衬底的厚度为0.5mm～1mm。
  4. 根据权利要求1-3任一项所述的方法，其中，所述晶圆盖板的厚度为0.1mm～0.5mm。
  5. 根据权利要求1-4任一项所述的方法，其中，所述方法还包括在打孔和蚀刻前分别对晶圆衬底和晶圆盖板进行清洗的步骤；
    优选地，所述清洗的方式包括浸泡清洗、超声清洗或等离子清洗；
    优选地，所述清洗使用的清洗液包括超纯水；
    优选地，所述清洗后还包括使用惰性气体吹干的步骤；
    优选地，所述惰性气体包括氮气。
  6. 根据权利要求1-5任一项所述的方法，其中，所述打孔的方法包括激光打孔、机械打孔或喷砂打孔；
    优选地，所述打孔包括形成进液孔和出液孔；
    优选地，所述进液孔和出液孔的孔径各自独立地为0.5mm～2.0mm；
    优选地，所述打孔后还包括进行超声清洗的步骤。
  7. 根据权利要求1-6任一项所述的方法，其中，所述蚀刻包括根据所需流道结构设计光学掩膜版，利用所述光学掩膜版对晶圆盖板进行蚀刻；
    优选地，所述蚀刻的方法包括湿法刻蚀或干法刻蚀；
    优选地，所述流道结构的深度为0.05mm～0.1mm。
  8. 根据权利要求1-7任一项所述的方法，其中，所述键合的方法包括阳极键合、激光键合或热压键合；
    优选地，所述阳极键合的温度为200℃～400℃。
  9. 根据权利要求1-8任一项所述的方法，其中，所述表面处理的方法包括化学气相沉积处理或液相浸泡处理；
    优选地，所述化学气相沉积处理的温度为25℃～50℃，时间为5 min～60 min。
  10. 根据权利要求1-9任一项所述的方法，其中，所述方法还包括向切割后得到的测序芯片组装芯片框架的步骤；
    所述芯片框架的材质选自塑料、陶瓷或金属中任意一种。
  11. 根据权利要求1-10任一项所述的方法，其中，所述方法包括以下步骤；
    (1)对晶圆衬底和晶圆盖板进行超声清洗；
    (2)对晶圆衬底进行打孔并进行超声清洗；
    (3)根据所需流道结构设计光学掩膜版，利用所述光学掩膜版对晶圆盖板进行蚀刻；
    (4)将打孔后的晶圆衬底和蚀刻后的晶圆盖板进行键合，得到键合晶圆；
    (5)对所述键合晶圆进行化学气相沉积处理或液相浸泡处理；
    (6)将步骤(5)处理后的键合晶圆进行切割，并组装芯片框架，得到测序芯片。
  12. 一种测序芯片，其中，所述测序芯片由权利要求1-10任一项所述的方法制备得到。
PCT/CN2022/141107 2022-07-26 2022-12-22 一种用于测序芯片表面化学处理及封装键合的方法 WO2024021464A1 (zh)

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