WO2021170145A1 - 芯片的分离方法以及晶圆 - Google Patents

芯片的分离方法以及晶圆 Download PDF

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WO2021170145A1
WO2021170145A1 PCT/CN2021/078527 CN2021078527W WO2021170145A1 WO 2021170145 A1 WO2021170145 A1 WO 2021170145A1 CN 2021078527 W CN2021078527 W CN 2021078527W WO 2021170145 A1 WO2021170145 A1 WO 2021170145A1
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phase medium
chip
solid
array substrate
cover plate
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PCT/CN2021/078527
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English (en)
French (fr)
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聂泳忠
刘晓敏
林祖鉴
叶新文
许财源
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西人马联合测控（泉州）科技有限公司
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Publication of WO2021170145A1 publication Critical patent/WO2021170145A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00865—Multistep processes for the separation of wafers into individual elements
    • B81C1/00904—Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
    • B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
    • B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip

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  • This application relates to the field of chip technology, and in particular to a method for separating chips and wafers.
  • Chips such as microfluidic chips have been widely used in life sciences, medicine, food and environmental sanitation inspections due to their small size, low cost, portability, fast analysis speed, and few samples required for analysis.
  • silicon-based microfluidic chips are similar in production process to integrated circuits, and it is easy to achieve large-scale mass production of microfluidic chips by using mature integrated circuit production processes.
  • the production efficiency is high, but there are also corresponding drawbacks.
  • the performance is that when the mass-produced chips are dicing, the cutting blade will easily generate debris on the wafer at high speed.
  • the coolant is driven by the cutting blade into the cutting part to cool and remove the debris generated during cutting. Because the pores of the chip are in an open state, it is inevitable that the coolant will carry the debris into the pores of the microfluidic chip and affect the performance of the chip.
  • the embodiments of the present application provide a chip separation method and a wafer.
  • the chip separation method can meet the separation and molding requirements of the chip, and at the same time can prevent debris from entering the channel of the chip, and ensure the performance of the chip.
  • a method for separating a chip including:
  • the array substrate includes a bottom plate and a plurality of chip units with holes, and the plurality of chip units are distributed on the bottom plate at intervals; a solid phase medium of a predetermined thickness is deposited on the array substrate, and the solid phase medium is filled in the holes; on the array substrate
  • the upper bonding cover plate covers the chip unit to form a wafer; the wafer is cut to form a plurality of dicing bodies, each dicing body includes a chip unit; the upper solid-phase medium of the dicing body is removed to form a chip with holes .
  • the step of removing the solid-phase medium on the cutting body to form a chip with pores specifically includes: providing an etching solution for the solid-phase medium; placing the cutting body in the etching solution for a predetermined period of time.
  • the liquid acts on the solid-phase medium and separates the solid-phase medium from the pores to form a chip with pores.
  • the step of removing the solid-phase medium on the cutting body to form a chip with pores further includes heating the etching solution, and/or making the cutting body vibrate relative to the etching solution.
  • the bottom plate is made of silicon wafers
  • the cover plate is made of silicon wafers
  • the solid phase medium is gold
  • the etching solution includes iodine and potassium iodide
  • the solid phase medium is aluminum
  • the etching solution includes phosphoric acid, A mixed solution of nitric acid and acetic acid.
  • the bottom plate is made of silicon wafers
  • the cover plate is made of glass sheets
  • the solid phase medium is silicon nitride
  • the etching solution includes phosphoric acid
  • the solid phase medium is silicon oxide
  • the etching solution includes hydrogen. Mixture of fluoric acid and ammonium fluoride.
  • the chip separation method before the step of bonding a cover plate on the array substrate to cover the chip unit to form a wafer, the chip separation method further includes: removing at least part of the solid phase medium by chemical mechanical polishing, So that the surface of the bottom plate provided with the chip unit is at least partially exposed to the outside of the solid phase medium and forms a bonding area.
  • the chip separation method before the step of bonding a cover plate on the array substrate to cover the chip unit to form a wafer, the chip separation method further includes: removing at least part of the solid phase medium by chemical mechanical polishing, The thickness of the solid-phase medium corresponding to the outer edge of the surface where the chip unit is set on the bottom plate is
  • the melting point of the solid phase medium is greater than 400°C.
  • a wafer which includes: an array substrate, including a bottom plate and a plurality of chip units with holes, the plurality of chip units are distributed on the bottom plate at intervals; a solid medium is deposited on the array substrate and Fill the hole; the cover plate is bonded with the array substrate and covers the chip unit.
  • the solid phase medium is gold, aluminum, silicon oxide, or silicon nitride.
  • the chip separation method is to directly deposit a solid phase medium of a predetermined thickness on the array substrate, and make the solid phase medium fill the holes of the chip unit, so that the array substrate and the cover
  • the solid-phase medium can prevent the debris generated during the dicing of the wafer from entering the channel of the chip unit. After the dicing is completed, remove the dicing
  • the solid-phase medium deposited in the body can not only meet the molding requirements of the chip with pores, but also enable the molded chip to have better performance.
  • FIG. 1 is a schematic flowchart of a chip separation method according to an embodiment of the present application
  • FIG. 2 is an exploded view of the wafer according to the embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for separating a chip according to another embodiment of the present application.
  • FIG. 4 is a schematic diagram of the array substrate and the solid phase medium after the solid phase medium is removed in the chip separation method of the embodiment of the present application;
  • FIG. 5 is a schematic flowchart of a method for separating a chip according to another embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for separating a chip according to another embodiment of the present application.
  • 11-bottom plate 111-carrying surface; 112-outer peripheral surface; 113-bottom surface; 12-chip unit;
  • orientation words appearing in the following description are all directions shown in the figure, and do not limit the chip separation method and the specific structure of the wafer in this application.
  • the terms “installation” and “connection” should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection, or Integrally connected; it can be directly connected or indirectly connected.
  • the specific meanings of the above-mentioned terms in this application can be understood according to specific circumstances.
  • FIG. 1 shows a schematic flowchart of a chip separation method according to an embodiment of the present application
  • FIG. 2 shows an exploded view of a wafer according to an embodiment of the present application.
  • An embodiment of the present application provides a method for separating a chip, including:
  • the array substrate 10 includes a bottom plate 11 and a plurality of chip units 12 with holes, and the plurality of chip units 12 are distributed on the bottom plate 11 at intervals.
  • each dicing body includes a chip unit 12;
  • the chip separation method provided by the embodiment of the present application can meet the cutting and molding requirements of the chip, and at the same time can prevent debris from entering the hole of the chip, and ensure the performance of the chip.
  • the provided array substrate 10 may be prefabricated in advance, of course, it may also be prefabricated on site.
  • the bottom plate 11 may be a circular plate, and the bottom plate 11 has a bottom surface 113, a bearing surface 111, and an outer peripheral surface 112 arranged to surround the bottom surface 113 in the thickness direction X of itself, and a plurality of chip units 12 are located on the bearing surface 111. side.
  • a plurality of chip units 12 may be distributed in rows and columns on the bottom plate 11, and two adjacent chip units 12 are spaced apart from each other and form a cutting area.
  • depositing a solid-phase medium 20 of a predetermined thickness on the array substrate 10 may specifically deposit the solid-phase medium 20 on the side of the carrying surface 111 where the plurality of chip units 12 are located, and the thickness of the deposition may be based on the solid-phase medium.
  • the form of 20 and the size of the array substrate 10 are required to be set, as long as the solid-phase medium 20 can be filled in the holes of each chip unit 12.
  • the solid-phase medium 20 can cover the bearing surface 111 of the array substrate 10 away from the bottom surface 113 thereof, which facilitates the deposition of the solid-phase medium 20, thereby better ensuring the filling requirements of the pores.
  • the structural shape of the provided cover plate 30 can match the structural shape of the bottom plate 11.
  • it can also be a circular plate, and the cover plate 30 is in the thickness direction X of the bottom plate 11.
  • the upper and bottom plate 11 are stacked on each other and connected to each other by bonding to cover each chip unit 12.
  • the chip units 12 may be separated from each other by cutting the space area (ie, the cutting area) between two adjacent chip units 12 to form a plurality of cutting bodies. Since the holes of each chip unit 12 are filled with the solid-phase medium 20, when the wafer is diced, the solid-phase medium 20 can prevent debris generated during the dicing of the wafer from entering the hole of the chip unit 12 Inside the road.
  • step S500 after the cutting is completed, the deposited solid-phase medium 20 in each cutting body is removed, which can not only meet the molding requirements of chips with holes, but also enable the molded chips to have better performance. And it only needs to form the solid phase medium 20 by deposition, the operation process is simple, and man-hours are saved.
  • the melting point of the solid phase medium 20 is greater than or equal to 400°C.
  • FIG. 3 shows a schematic flowchart of a chip separation method according to another embodiment of the present application.
  • step S500 specifically includes:
  • the cutting body is placed in an etching solution for a predetermined time, and the etching solution acts on the solid-phase medium 20 to separate the solid-phase medium 20 from the pores, so as to form a chip with pores.
  • the operation is simple, and the reliability of the separation effect of the solid-phase medium 20 and the pores can be ensured.
  • the composition of the etching solution can be specifically set according to the material of the solid phase medium 20, as long as it can ensure the reaction with the solid phase medium 20 and separate the solid phase medium 20 from the channel.
  • the bottom plate 11 may be made of silicon wafers, and the cover plate 30 may also be made of silicon wafers.
  • the solid-phase medium 20 may be a metal medium.
  • the solid-phase medium 20 may be a metal medium.
  • the phase medium 20 may be gold.
  • the etching solution corresponding to gold can be a mixed solution of iodine and potassium iodide, as long as it can react with the solid phase medium 20 on the cutting body and separate it from the pores.
  • the solid phase medium 20 is not limited to gold. In some other examples, the solid phase medium 20 may also be aluminum.
  • the etching solution may include a mixed solution of phosphoric acid, nitric acid, and acetic acid, with phosphoric acid as the main component. .
  • the ratio of the etching solution containing phosphoric acid, nitric acid, and acetic acid may be 16:1:3. The use of this component ratio in the etching solution can further optimize the separation effect of aluminum and ensure the performance of the formed chip.
  • the metal medium is not limited to gold and aluminum, but can also be other metal mediums, as long as it can meet the filling requirements of the pores, and the melting point of the solid-phase medium 20 itself is greater than that of the cover plate.
  • the bonding temperature between 30 and the array substrate 10 can be any, and it will not be listed here.
  • the solid-phase medium 20 is not limited to being a metallic medium. In some other examples, the solid-phase medium 20 may also be a non-metallic medium. In some optional examples, the solid-phase medium 20 may be silicon oxide. At this time, the corresponding etching solution may be a mixed solution of hydrofluoric acid and ammonium fluoride.
  • the solid-phase medium 20 when the solid-phase medium 20 is a non-metallic medium, the solid-phase medium 20 can also be silicon nitride.
  • the etching solution can be a phosphoric acid solution, or an 85% phosphoric acid solution.
  • step S500 may further include a step of heating the etching solution to increase the temperature of the etching solution, thereby increasing the etching solution and the solid phase medium. The reaction rate.
  • the required temperature of the etching solution can be defined according to the material of the solid phase medium 20 and the composition of the etching solution.
  • the solid phase medium 20 is silicon nitride and the etching solution is phosphoric acid solution.
  • the temperature of the liquid is raised to any value between 130°C and 150°C, including the two end values of 130°C and 150°C. By raising the temperature of the corrosive liquid, the separation rate of the solid-phase medium 20 from the channel is increased by 1.5 times or more.
  • step S500 further includes the step of making the cutting body vibrate in the corrosive liquid.
  • the cutting body By making the cutting body vibrate in the corrosive liquid, the solid phase can be further accelerated.
  • the cutting body may be vibrated by means such as ultrasonic waves, so as to meet the requirement of increasing the separation rate of the solid-phase medium 20 and the pores.
  • FIG. 4 shows a schematic diagram of the array substrate 10 and the solid phase medium 20 after the solid phase medium 20 is removed in the chip separation method of the embodiment of the present application
  • FIG. 5 shows the present application A schematic flow chart of a method for separating a chip according to another embodiment.
  • the chip separation method before step S300, the chip separation method further includes step S600:
  • At least part of the solid phase medium 20 is removed, so that the surface of the bottom plate 11 where the chip unit 12 is at least partially exposed to the outside of the solid phase medium 20 and forms a bonding area.
  • the solid phase medium 20 can effectively prevent the solid phase medium 20 from affecting the bonding and ensure the cover The stability of the bonding connection between 30 and the array substrate 10.
  • the solid-phase medium 20 is aluminum, silicon oxide or silicon nitride
  • at least part of the solid-phase medium 20 can be removed so that the surface of the bottom plate 11 where the chip unit 12 is at least partially exposed to the outside of the solid-phase medium 20 and The formation of the bonding area ensures the bonding requirements between the cover plate 30 and the array substrate 10.
  • chemical mechanical polishing may be used to remove at least part of the solid phase medium 20, so that the surface of the bottom plate 11 where the chip unit 12 is at least partially exposed to the outside of the solid phase medium 20 and forms a bonding area.
  • FIG. 6 shows a schematic flow chart of a chip separation method according to another embodiment of the present application.
  • the chip separation method provided in the above embodiment is performed before step S300 ,
  • the chip separation method may further include step S700:
  • the thickness of the solid-phase medium 20 at the outer edge of the surface where the base plate 11 is provided with the chip unit 12 corresponds to Any value between, including Two end values, optional Any value in between. Since part of the solid-phase medium 20 can be bonded to the cover plate 30, such as gold, it is not necessary to expose the surface of the bottom plate 11 where the chip unit 12 is at least partially exposed to the outside of the solid-phase medium 20 before step S300.
  • the grinding debris and changing its thickness can change the flatness of the solid-phase medium 20 formed after deposition, which is more conducive to the implementation of step S300, and ensures the bonding requirements between the cover plate 30 and the array substrate 10, and at the same time, it can effectively Reduce the difficulty of bonding.
  • chemical mechanical polishing may be used to remove at least part of the solid-phase medium 20, so that the thickness of the solid-phase medium 20 at the outer edge of the surface where the base plate 11 is provided with the chip unit 12 corresponds to Any value in between.
  • the chip separation method provided by the embodiment of the present application directly deposits a solid-phase medium 20 of a predetermined thickness on the array substrate 10, and makes the solid-phase medium 20 fill the holes, so that the array substrate 10 and the cover plate 30 are formed after bonding
  • the solid-phase medium 20 can prevent the debris generated during the dicing of the wafer from entering the holes of the chip unit 12, and remove the deposited solids in each dicing body after the cutting is completed.
  • the phase medium 20 can not only meet the molding requirements of chips with holes, but also enable the molded chips to have better performance.
  • the embodiment of the present application also provides a new wafer, including an array base 10, a solid-phase medium 20, and a cover plate 30.
  • the array base 10 includes a bottom plate 11 and a plurality of chip units with holes. 12. A plurality of chip units 12 are distributed on the bottom plate 11 at intervals.
  • the solid phase medium 20 is deposited on the array base 10 and fills the holes, and the cover plate 30 is bonded to the array base 10 and covers the chip unit 12.
  • the structure of the array substrate 10 and the cover plate 30 are the same as those introduced in the chip separation method described above, and will not be repeated here.
  • the solid-phase medium 20 may cover the bearing surface 111 on the side of the array substrate 10 away from the bottom surface 113 of the bottom plate 11, which is more conducive to the deposition of the solid-phase medium 20 and can ensure the passage of each chip unit 12 Fill demand.
  • the solid-phase medium 20 may be a metal medium, such as gold or aluminum. Of course, in some other examples, it may also be a non-metallic medium, such as silicon oxide or silicon nitride.
  • the components of the above four solid-phase media 20 are just examples of several alternative embodiments, but not limited to this, as long as they can meet the filling requirements of the channels and can avoid the bonding between the array substrate 10 and the cover plate 30 The connection has an impact, and at the same time it can be ensured that it can be removed by the corresponding etching solution after being diced.
  • the solid-phase medium 20 can effectively block the dicing process when the wafer is diced and separated to form the chip.
  • the debris enters the channel to ensure the function of the separated and molded chips.

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Abstract

一种芯片的分离方法，包括：提供阵列基体（10），阵列基体（10）包括底板（11）以及多个具有孔道的芯片单元（12），多个芯片单元（12）间隔分布于底板（11）；在阵列基体（10）上沉积预定厚度的固相介质（20），并使得固相介质（20）填充于孔道；在阵列基体（10）上键合盖板（30），盖板（30）覆盖芯片单元（12），以形成晶圆；切割晶圆并形成多个切割体，每个切割体包括芯片单元（12）；去除切割体上的固相介质（20），以成型具有孔道的芯片。芯片的分离方法能够满足芯片的切割成型要求，同时能够避免碎屑进入芯片的孔道内，保证芯片的性能。还提供了一种晶圆。

Description

芯片的分离方法以及晶圆
相关申请的交叉引用
本申请要求享有于2020年02月27日提交的、名称为“芯片的分离方法以及晶圆”的中国专利申请第202010122897.0号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及芯片技术领域，特别是涉及一种芯片的分离方法以及晶圆。
背景技术
芯片如微流控芯片由于体积小、成本低、便于携带、分析速度快、分析所需样品少等特点在生命科学、医学、食品和环境卫生检查等领域得到了广泛应用。
其中，硅基的微流控芯片由于生产工艺与集成电路相似，利用成熟的集成电路生产工艺很容易实现微流控芯片的大规模批量化生产，生产效率高，但也存在相应的弊端，主要表现为批量化生产的芯片在划片时，切割刀片在高转速下容易使得晶圆产生碎屑，在切割过程中，冷却液通过切割刀片带动进入切割部位进行冷却并移除切割时产生的碎屑，而由于芯片的孔道处于开放状态，不可避免的冷却液会带着碎屑进入到微流控芯片的孔道内，影响芯片的性能。
因此，亟需一种新的芯片的分离方法以及晶圆。
发明内容
本申请实施例提供一种芯片的分离方法以及晶圆，芯片的分离方法能够满足芯片的分离成型要求，同时能够避免碎屑进入芯片的孔道内，保证芯片的性能。
一方面，根据本申请实施例提出了一种芯片的分离方法，包括：
提供阵列基体，阵列基体包括底板以及多个具有孔道的芯片单元，多个芯片单元间隔分布于底板；在阵列基板上沉积预定厚度的固相介质，并使得固相介质填充于孔道；在阵列基板上键合盖板，盖板覆盖芯片单元，以形成晶圆；切割晶圆并形成多个切割体，每个切割体包括芯片单元；去除切割体的上固相介质，以成型具有孔道的芯片。
根据本申请实施例的一个方面，去除切割体上的固相介质，以成型具有孔道的芯片的步骤具体包括：提供固相介质用腐蚀液；将切割体置于腐蚀液中预定时间，通过腐蚀液作用于固相介质并使得固相介质与孔道分离，以成型具有孔道的芯片。
根据本申请实施例的一个方面，去除切割体上的固相介质，以成型具有孔道的芯片的步骤还包括：加热所述腐蚀液，和/或，使切割体相对腐蚀液振动。
根据本申请实施例的一个方面，底板由硅片制成，盖板由硅片制成，固相介质为金，腐蚀液包括碘和碘化钾；或者，固相介质为铝，腐蚀液包括磷酸、硝酸以及醋酸的混合溶液。
根据本申请实施例的一个方面，底板由硅片制成，盖板由玻璃片制成，固相介质为氮化硅，腐蚀液包括磷酸；或者，固相介质为氧化硅，腐蚀液包括氢氟酸与氟化铵混合液。
根据本申请实施例的一个方面，在阵列基板上键合盖板，盖板覆盖芯片单元，以形成晶圆的步骤之前，芯片的分离方法还包括：采用化学机械抛光去除至少部分固相介质，以使底板设置芯片单元的表面至少部分暴露于固相介质的外侧并形成键合区域。
根据本申请实施例的一个方面，在阵列基板上键合盖板，盖板覆盖芯片单元，以形成晶圆的步骤之前，芯片的分离方法还包括：采用化学机械抛光去除至少部分固相介质，以使底板设置芯片单元的表面的外缘处对应固相介质的厚度为
Figure PCTCN2021078527-appb-000001
根据本申请实施例的一个方面，固相介质的熔点大于400℃。
另一方面，根据本申请实施例提出了一种晶圆，包括：阵列基体，包 括底板以及多个具有孔道的芯片单元，多个芯片单元间隔分布于底板；固相介质，沉积于阵列基体并填充孔道；盖板，与阵列基板键合并覆盖芯片单元。
根据本申请实施例的另一个方面，固相介质为金、铝、氧化硅或者氮化硅。
根据本申请实施例提供的芯片的分离方法以及晶圆，芯片的分离方法通过在阵列基体上直接沉积预定厚度的固相介质，并使得固相介质填充于芯片单元的孔道，使得阵列基板与盖板在键合后形成的晶圆被切割成多个切割体时，固相介质能够阻止晶圆在被切割的过程中产生的碎屑进入芯片单元的孔道内，当切割完成后通过去除各切割体内沉积的固相介质即可，不仅能够满足具有孔道的芯片的成型要求，同时还能够使得成型的芯片具有更好的性能。
附图说明
下面将参考附图来描述本申请示例性实施例的特征、优点和技术效果。
图1是本申请一个实施例的芯片的分离方法的流程示意图；
图2是本申请实施例晶圆的分解图；
图3是本申请另一个实施例的芯片的分离方法的流程示意图；
图4是本申请实施例的芯片的分离方法中固相介质被去除后阵列基板与固相介质的示意图；
图5是本申请又一个实施例的芯片的分离方法的流程示意图；
图6是本申请再一个实施例的芯片的分离方法的流程示意图。
其中：
10-阵列基体；
11-底板；111-承载面；112-外周面；113-底面；12-芯片单元；
20-固相介质；
30-盖板；
X-厚度方向。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例绘制。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例。在下面的详细描述中，提出了许多具体细节，以便提供对本申请的全面理解。但是，对于本领域技术人员来说很明显的是，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请的更好的理解。在附图和下面的描述中，至少部分的公知结构和技术没有被示出，以便避免对本申请造成不必要的模糊；并且，为了清晰，可能夸大了部分结构的尺寸。此外，下文中所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。
下述描述中出现的方位词均为图中示出的方向，并不是对本申请的芯片的分离方法以及晶圆的具体结构进行限定。在本申请的描述中，还需要说明的是，除非另有明确的规定和限定，术语“安装”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以间接相连。对于本领域的普通技术人员而言，可视具体情况理解上述术语在本申请中的具体含义。
为了更好地理解本申请，下面结合图1至图6根据本申请实施例的用于芯片的分离方法以及晶圆进行详细描述。
请一并参阅图1以及图2，图1示出了本申请一个实施例的芯片的分离方法的流程示意图，图2示出了本申请实施例晶圆的分解图。
本申请实施例提供一种芯片的分离方法，包括：
S100、提供阵列基体10，阵列基体10包括底板11以及多个具有孔道的芯片单元12，多个芯片单元12间隔分布于底板11。
S200、在阵列基体10上沉积预定厚度的固相介质20，并使得固相介质20填充于孔道。
S300、在阵列基体10上键合盖板30，盖板30覆盖芯片单元12，以 形成晶圆。
S400、切割晶圆并形成多个切割体，每个切割体包括芯片单元12；
S500、去除切割体上的固相介质20，以成型具有孔道的芯片。
本申请实施例提供的芯片的分离方法，能够满足芯片的切割成型要求，同时能够避免碎屑进入芯片的孔道内，保证芯片的性能。
可选的，在步骤S100中，提供的阵列基体10可以是提前预制好的，当然也可以是现场预制的。可选的，底板11可以为圆形板，底板11在自身厚度方向X具有相对设置的底面113、承载面111以及围合底面113设置的外周面112，多个芯片单元12位于承载面111所在侧。可选的，多个芯片单元12在底板11上可以行列分布，相邻两个芯片单元12彼此之间相互间隔并形成切割区域。
可选的，在步骤S200中，在阵列基体10上沉积预定厚度的固相介质20具体可以在多个芯片单元12所在的承载面111侧沉积固相介质20，沉积的厚度可以根据固相介质20的形式以及阵列基体10的尺寸要求设置，只要使得固相介质20能够填充于各芯片单元12的孔道即可。
在一些可选的实施例中，固相介质20可以覆盖阵列基体10远离其底面113的承载面111，易于固相介质20的沉积，进而能够更好的保证孔道的填充要求。
可选的，在步骤S300中，所提供的盖板30的结构形状可以与底板11的结构形状相匹配，可选的，其同样可以为圆形板，盖板30在底板11的厚度方向X上与底板11相互层叠并通过键合的方式相互连接，以覆盖各芯片单元12。
在一些可选的示例中，在步骤S400中，可以通过切割相邻两个芯片单元12之间的间隔区域(即切割区域)使得芯片单元12彼此分离，形成多个切割体。由于每个芯片单元12的孔道内均被固相介质20填充，因此在对晶圆进行切割时，固相介质20能够阻止晶圆在被切割的过程中产生的碎屑进入芯片单元12的孔道内。
在步骤S500中，当切割完成后去除各切割体内的沉积的固相介质20，既能够满足具有孔道的芯片的成型要求，同时还能够使得成型的芯片 具有更好的性能。且只需要通过沉积的方式形成固相介质20即可，操作流程简单，并节约工时。
在一些可选的实施例中，上述各实施例提供的芯片的分离方法，其固相介质20的熔点大于等于400℃。通过限定固相介质20的熔点采用上述数值范围，即能够满足对孔道的填充效果，避免碎屑进入孔道内，同时，还能够避免盖板30与阵列基体10在键合时因升温导致固相介质20相变问题的发生，进而避免因相变导致孔道内出现孔隙的问题发生。
请一并参阅图3，图3示出了本申请另一个实施例的芯片的分离方法的流程示意图。
在一些可选的实施例中，上述各实施例提供的芯片的分离方法，其步骤S500具体包括：
S510、提供固相介质20用腐蚀液；
S520、将切割体置于腐蚀液中预定时间，通过腐蚀液作用于固相介质20并使得固相介质20与孔道分离，以成型具有孔道的芯片。
通过利用腐蚀液与固相介质20作用使其与孔道分离的方式，操作简单，能够保证固相介质20与孔道的分离效果的可靠性。
可选的，腐蚀液的成分具体可以根据固相介质20的材质进行设定，只要能够保证与固相介质20反应，使固相介质20与孔道分离均可。
在一些可选的实施例中，底板11可以由硅片制成，盖板30也可以由硅片制成，此时，固相介质20可以为金属介质，在一些可选的示例中，固相介质20可以为金，在步骤S300中，阵列基体10在与盖板30键合时，金可以与硅通过形成金硅共熔物而达到键合。在步骤S500时，金对应的腐蚀液可以为碘与碘化钾的混合溶液，只要满足与切割体上的固相介质20反应并使其与孔道分离即可。
可以理解的是，固相介质20不限于为金，在一些其他的示例中，固相介质20也可以为铝，此时，腐蚀液可以包括磷酸、硝酸以及醋酸的混合溶液，磷酸为主要成分。可选的，腐蚀液包含磷酸、硝酸以及醋酸的比例可以为16：1：3，腐蚀液采用该种成分比例能够进一步优化铝的分离效果，保证成型的芯片的性能。
可以理解的是，当固相介质20采用金属介质时，金属介质不限于为金以及铝，也可以为其他金属介质，只要能够满足孔道的填充要求，同时固相介质20本身的熔点大于盖板30与阵列基体10之间的键合温度均可，在此就不一一列举。
可以理解的是，固相介质20并不限于为金属介质，在一些其他的示例中，固相介质20也可以为非金属介质，一些可选的示例中，固相介质20可以为氧化硅，此时，对应的腐蚀液可以为氢氟酸与氟化铵混合液。
当然，在有些示例中，固相介质20当采用非金属介质时，固相介质20还可以为氮化硅，此时腐蚀液可以采用磷酸溶液，可选为85％的磷酸溶液，同样可以满足固相介质20对孔道的填充要求以及晶圆切割后固相介质20与孔道的分离要求。
在一些可选的实施例中，上述各实施例提供的芯片的分离方法，其步骤S500还可以进一步包括对加热腐蚀液的步骤，以提高腐蚀液的温度，进而提高腐蚀液与固相介质20的反应速率。
腐蚀液所需温度可以根据固相介质20的材质以及腐蚀液的成分进行限定，在一些可选的示例中，以固相介质20为氮化硅，腐蚀液采用磷酸溶液为例，可以将腐蚀液升温至130℃～150℃之间的任意数值，包括130℃、150℃两个端值，通过对腐蚀液进行升温，使得固相介质20与孔道的分离速率提高1.5倍及以上。
作为一种可选的实施方式，上述各实施例提供的芯片的分离方法，其步骤S500进一步包括使得切割体在腐蚀液中振动步骤，通过使得切割体在腐蚀液中振动，能够进一步加快固相介质20与孔道的分离速率。在一些可选的实施例中，可以通过超声波等方式使得切割体振动，进而满足提高固相介质20与孔道的分离速率的要求。
请一并参阅图4以及图5，图4示出了本申请实施例的芯片的分离方法中固相介质20被去除后阵列基体10与固相介质20的示意图，图5示出了本申请又一个实施例的芯片的分离方法的流程示意图。
作为一种可选的实施方式，上述各实施例提供的芯片的分离方法，在步骤S300之前，芯片的分离方法还包括步骤S600：
去除至少部分固相介质20，以使底板11设置芯片单元12的表面至少部分暴露于固相介质20的外侧并形成键合区域。通过将底板11设置芯片单元12的表面至少部分暴露于固相介质20的外侧并形成键合区域，使得在执行步骤S300时，能够有效的避免固相介质20对键合产生影响，保证盖板30与阵列基体10之间键合连接的稳定性。
例如，在固相介质20为铝、氧化硅或者氮化硅时，均可通过去除至少部分固相介质20，以使底板11设置芯片单元12的表面至少部分暴露于固相介质20的外侧并形成键合区域保证盖板30与阵列基体10之间的键合要求。
在一些可选的实施例中，可以采用化学机械抛光去除至少部分固相介质20，以使底板11设置芯片单元12的表面至少部分暴露于固相介质20的外侧并形成键合区域。采用化学机械抛光方式，可以精准的控制固相介质20被去除的厚度以及去除的位置。
请一并参阅图6，图6示出了本申请再一个实施例的芯片的分离方法的流程示意图，当然，在一些其他的示例中，上述实施例提供的芯片的分离方法，在步骤S300之前，芯片的分离方法还可以包括步骤S700：
去除至少部分固相介质20，使得底板11设置芯片单元12的表面的外缘处对应固相介质20的厚度为
Figure PCTCN2021078527-appb-000002
之间的任意数值，包括
Figure PCTCN2021078527-appb-000003
两个端值，可选为
Figure PCTCN2021078527-appb-000004
之间的任意数值。由于部分材质的固相介质20能够与盖板30键合，例如金，因此在步骤S300之前，可以不必使得底板11设置芯片单元12的表面至少部分暴露于固相介质20的外侧，只需要将其进行磨屑，改变其厚度，可以改变沉积后形成的固相介质20的平整性，更利于步骤S300的实施，保证盖板30与阵列基体10之间的键合要求，同时，能够有效的降低键合难度。同时，限制固相介质20的厚度为
Figure PCTCN2021078527-appb-000005
之间的任意数值，能够保证与盖板键合时所需厚度，进而保证与盖板的键合要求，同时，能够使得固相介质的厚度适中，避免材料浪费。
同样的，在一些可选的实施例中，可以采用化学机械抛光去除至少部分固相介质20，以使底板11设置芯片单元12的表面的外缘处对应固相介 质20的厚度为
Figure PCTCN2021078527-appb-000006
之间的任意数值。采用化学机械抛光方式，可以精准的控制固相介质20被去除的厚度以及去除的位置。
本申请实施例提供的芯片的分离方法，通过在阵列基体10上直接沉积预定厚度的固相介质20，并使得固相介质20填充于孔道，使得阵列基体10与盖板30在键合后形成的晶圆别切割成多个切割体时，固相介质20能够阻止晶圆在被切割的过程中产生的碎屑进入芯片单元12的孔道内，当切割完成后去除各切割体内的沉积的固相介质20，既能够满足具有孔道的芯片的成型要求，同时还能够使得成型的芯片具有更好的性能。
作为一种可选的实施方式，本申请实施例还提供一种新的晶圆，包括阵列基体10、固相介质20以及盖板30，阵列基体10包括底板11以及多个具有孔道的芯片单元12，多个芯片单元12间隔分布于底板11。固相介质20沉积于阵列基体10并填充孔道，盖板30与阵列基体10键合并覆盖芯片单元12。
可选的，阵列基体10以及盖板30的结构形式同上述在芯片的分离方法中的介绍，在此就不重复赘述。
在一些可选的实施例中，固相介质20可以覆盖阵列基体10远离底板11的底面113一侧的承载面111，更利于固相介质20的沉积，且能够保证各芯片单元12的孔道的填充需求。
在一些可选的示例中，固相介质20可以为金属介质，例如可以为金、铝，当然，在一些其他的示例中，也可以为非金属介质，例如可以为氧化硅或者氮化硅等，上述四种固相介质20的成分只是举例说明几种可选的实施方案，但不限于此，只要能够满足孔道的填充需求，且能够避免对阵列基体10与盖板30之间的键合连接产生影响，同时能够保证被划片切割后可以通过相应的腐蚀液去除均可。
本申请实施例提供的晶圆，由于在芯片单元12的孔道内沉积有固相介质20，使得晶圆在被划片分离，以成型芯片的过程中，固相介质20能够有效的阻击切割产生的碎屑进入孔道内，进而保证分离成型的芯片的功能。
虽然已经参考优选实施例对本申请进行了描述，但在不脱离本申请的 范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本申请并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (13)

  1. 一种芯片的分离方法，其中，包括：
    提供阵列基体，所述阵列基体包括底板以及多个具有孔道的芯片单元，多个所述芯片单元间隔分布于所述底板；
    在所述阵列基体上沉积预定厚度的固相介质，并使得所述固相介质填充于所述孔道；
    在所述阵列基体上键合盖板，所述盖板覆盖所述芯片单元，以形成晶圆；
    切割所述晶圆并形成多个切割体，每个所述切割体包括所述芯片单元；
    去除所述切割体上的所述固相介质，以成型具有所述孔道的芯片。
  2. 根据权利要求1所述的芯片的分离方法，其中，所述去除所述切割体上的所述固相介质，以成型具有所述孔道的芯片的步骤具体包括：
    提供所述固相介质用腐蚀液；
    将所述切割体置于所述腐蚀液中预定时间，通过所述腐蚀液作用于所述固相介质并使得所述固相介质与所述孔道分离，以成型具有所述孔道的所述芯片。
  3. 根据权利要求2所述的芯片的分离方法，其中，所述去除所述切割体上的所述固相介质，以成型具有所述孔道的芯片的步骤还包括：
    加热所述腐蚀液。
  4. 根据权利要求2所述的芯片的分离方法，其中，所述去除所述切割体上的所述固相介质，以成型具有所述孔道的芯片的步骤还包括：
    使所述切割体相对所述腐蚀液振动。
  5. 根据权利要求2所述的芯片的分离方法，其中，所述底板由硅片制成；
    所述盖板由硅片制成，所述固相介质为金，所述腐蚀液包括碘和碘化钾。
  6. 根据权利要求2所述的芯片的分离方法，其中，所述盖板由硅片制成，所述固相介质为铝，所述腐蚀液包括磷酸、硝酸以及醋酸的混合溶液。
  7. 根据权利要求2所述的芯片的分离方法，其中，所述底板由硅片制成，所述盖板由玻璃片制成；
    所述固相介质为氮化硅，所述腐蚀液包括磷酸。
  8. 根据权利要求2所述的芯片的分离方法，其中，所述底板由硅片制成，所述盖板由玻璃片制成；所述固相介质为氧化硅，所述腐蚀液包括氢氟酸与氟化铵混合液。
  9. 根据权利要求1至7任意一项所述的芯片的分离方法，其中，在所述阵列基体上键合盖板，所述盖板覆盖所述芯片单元，以形成晶圆的步骤之前，所述芯片的分离方法还包括：
    采用化学机械抛光去除至少部分所述固相介质，以使所述底板设置所述芯片单元的表面至少部分暴露于所述固相介质的外侧并形成键合区域。
  10. 根据权利要求1至7任意一项所述的芯片的分离方法，其中，在所述阵列基体上键合盖板，所述盖板覆盖所述芯片单元，以形成晶圆的步骤之前，所述芯片的分离方法还包括：
    采用化学机械抛光去除至少部分所述固相介质，以使所述底板设置所述芯片单元的表面的外缘处对应所述固相介质的厚度为
    Figure PCTCN2021078527-appb-100001
  11. 根据权利要求1至7任意一项所述的芯片的分离方法，其中，所述固相介质的熔点大于400℃。
  12. 一种晶圆，其中，包括：
    阵列基体，包括底板以及多个具有孔道的芯片单元，多个所述芯片单元间隔分布于所述底板；
    固相介质，沉积于所述阵列基体并填充所述孔道；
    盖板，与所述阵列基体键合并覆盖所述芯片单元。
  13. 根据权利要求11所述的晶圆，其中，所述固相介质为金、铝、 氧化硅或者氮化硅。
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