WO2024016384A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024016384A1
WO2024016384A1 PCT/CN2022/109872 CN2022109872W WO2024016384A1 WO 2024016384 A1 WO2024016384 A1 WO 2024016384A1 CN 2022109872 W CN2022109872 W CN 2022109872W WO 2024016384 A1 WO2024016384 A1 WO 2024016384A1
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Prior art keywords
areas
unit
forming
substrate
exposure
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PCT/CN2022/109872
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English (en)
French (fr)
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薛东
刘志拯
李宗翰
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长鑫存储技术有限公司
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Publication of WO2024016384A1 publication Critical patent/WO2024016384A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • the semiconductor structure and its forming method provided by some embodiments of the present disclosure are used to improve the manufacturing efficiency of packaged integrated circuits, thereby improving the manufacturing efficiency of semiconductor structures.
  • the present disclosure provides a method for forming a semiconductor structure, including the following steps:
  • the substrate including a plurality of unit areas
  • a switching circuit structure is respectively formed in a plurality of exposure areas in a plurality of the unit areas.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas of the substrate include:
  • the photomask pattern is used to simultaneously expose multiple unit areas in the substrate, and the exposure areas are formed in multiple unit areas simultaneously.
  • the number of the mask patterns is multiple; the specific steps of sequentially forming multiple exposure areas in multiple unit areas of the substrate include:
  • the first loop steps include:
  • a mask pattern is used as the current mask pattern in the first cycle step next time.
  • the specific steps of using the current mask pattern to expose multiple unit areas in the substrate include:
  • the current mask pattern is used to sequentially expose a plurality of unit areas in the substrate.
  • the specific steps of sequentially exposing multiple unit areas in the substrate using the current mask pattern include:
  • the second loop step includes:
  • the current unit area is exposed at least once using the current mask pattern, at least one exposure area is formed in the current unit area, and the next unit area adjacent to the current unit area is used as the next unit area. Once the current unit area in the second loop step.
  • the number of the mask patterns is more than four, and each of the mask patterns performs the cycle step at least once.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas of the substrate include:
  • the unit area is exposed multiple times using the mask pattern, and a plurality of the exposure areas are sequentially formed in the unit area.
  • the marks are respectively formed at edges of a plurality of unit areas of the substrate.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas of the substrate include:
  • Marks are respectively formed at the edges of the plurality of pre-exposure areas in each of the unit areas;
  • the exposure areas are respectively formed in the middle of the plurality of pre-exposure areas in each of the unit areas.
  • the pre-exposure area includes a device area and a scribe line area distributed around the periphery of the device area;
  • the mark is formed in the scribe line area, and the exposure area is formed in the device area.
  • the cutting lane area includes a first cutting lane extending along a first direction, and a second cutting lane intersecting the first cutting lane and extending along a second direction, the first direction and The second directions are all directions parallel to the top surface of the substrate, and the first direction intersects the second direction; at the edges of the plurality of pre-exposure areas in each of the unit areas
  • the specific steps to form marks include:
  • a second mark is formed in the second cutting lane of the unit area, and the first mark and the second mark together constitute the mark.
  • the marks at the edges of multiple pre-exposure areas within the unit area are all the same; or,
  • the marks at the edges of at least two pre-exposure areas in the unit area are different.
  • the following steps are further included:
  • a dielectric layer covering the mark is formed in a plurality of the unit areas.
  • the specific steps of forming switching circuit structures in multiple exposure areas in multiple unit areas include:
  • a plurality of the exposure areas in a plurality of the unit areas are developed simultaneously, and the switching circuit structure is respectively formed in the multiple exposure areas of each unit area.
  • the following steps are also included:
  • At least one first semiconductor device and at least one second semiconductor device are packaged above the adapter board, and the adapter circuit structure is electrically connected to the first semiconductor device and the second semiconductor device.
  • the substrate is a bare wafer, and the marks are formed on the bare wafer.
  • the present disclosure also provides a semiconductor structure formed using the above-mentioned method for forming a semiconductor structure, including:
  • the substrate including a plurality of unit areas
  • each of the unit areas includes a plurality of the switching circuit structures, and the same switching circuit structure exists in at least two of the unit areas.
  • multiple switching circuit structures in the unit area are all the same; or,
  • it also includes:
  • a mark is located at the edge of the unit area, and the unit area includes a plurality of marks corresponding to a plurality of switching circuit structures in a one-to-one manner.
  • it also includes:
  • a dielectric layer covers the mark, and the switching circuit structure is located above the dielectric layer.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. After sequentially forming multiple exposure areas in multiple unit areas on a substrate, the transformation is then formed in multiple exposure areas in the multiple unit areas.
  • the transfer circuit pattern formed by all the exposure areas in each unit area together constitutes a packaged integrated circuit. That is, some embodiments of the present disclosure form multiple exposures in the entire unit area. After one of the exposed areas, a switching circuit structure is simultaneously formed in multiple of the exposed areas through one development, thereby simplifying the formation process of the packaged integrated circuit and improving the manufacturing efficiency of the packaged integrated circuit.
  • some embodiments of the present disclosure provide an alignment basis for the subsequent formation of a switching circuit structure in the unit area by separately forming marks in each unit area of the substrate, thereby improving the efficiency of forming a switching circuit structure in the unit area.
  • the accuracy of the circuit structure improves the manufacturing yield of packaged integrated circuits.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • FIGS. 2 to 8 are schematic diagrams of the main process structures in the process of forming semiconductor structures according to specific embodiments of the present disclosure.
  • FIG. 1 is a flow chart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure.
  • Figures 2 to 8 illustrate the steps of forming the semiconductor structure in the specific embodiment of the present disclosure. Schematic diagram of the main process structure in the process. As shown in Figures 1-8, the method for forming the semiconductor structure includes the following steps:
  • a substrate 20 is provided.
  • the substrate 20 includes a plurality of unit regions 21, as shown in FIG. 2 .
  • the material of the substrate 20 may be, but is not limited to, silicon. This specific embodiment will be described by taking the substrate 20 as a silicon substrate as an example.
  • a photolithography process may be used to define multiple unit regions 21 in the substrate 20 .
  • a plurality of the unit regions 21 may be arranged in a two-dimensional array along the first direction D1 and the second direction D2 in the substrate 20 , wherein, The first direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate 20 , and the first direction D1 and the second direction D2 intersect.
  • FIGS. 2 to 8 in this specific implementation manner illustrate using the substrate 20 including four unit regions 21 as an example.
  • the unit area 21 is subsequently used as a transfer structure (such as a transfer board) for packaging and integrating the first semiconductor device and the second semiconductor device. Therefore, the structure and quantity of the first semiconductor device can be packaged and integrated according to the requirements. As well as the structure and quantity of the second semiconductor devices, the size of the unit region 21 is adjusted. In this specific embodiment, the plurality of unit areas 21 have the same size and shape. A plurality in this specific embodiment means two or more. Wherein, the first semiconductor device and the second semiconductor device are any one or a combination of two or more of a memory chip, a logic chip, an image sensor, a processor, and a power supply chip.
  • any two adjacent unit areas 21 there is a gap between any two adjacent unit areas 21 to facilitate subsequent division of the adjacent unit areas 21 through a cutting process and reduce the risk of damage to the interior of the unit area 21 .
  • the edges of any two adjacent unit areas 21 are in contact and any two adjacent unit areas 21 do not overlap, so as to further improve the space on the substrate 20 Utilization.
  • step S12 multiple exposure areas are sequentially formed in the plurality of unit areas 21 of the substrate 20, as shown in FIG. 2.
  • step S13 a switching circuit structure is formed in a plurality of exposed areas in the plurality of unit areas 21 respectively.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas 21 of the substrate 20 include:
  • the mask pattern is used to simultaneously expose multiple unit areas 21 in the substrate, and the exposed areas are formed in multiple unit areas 21 at the same time.
  • the exposure area described in this specific embodiment refers to an area that has been exposed using a mask pattern and has not been developed. Specifically, according to the specific structure of the switching circuit structure that needs to be formed in the unit area 21, the corresponding photomask pattern is selected, and the photomask pattern is used to perform exposure in the unit area 21. . Since multiple unit areas 21 are provided on the substrate 20 in this specific embodiment, the mask pattern is used to pair the multiple unit areas that need to form switching circuit structures corresponding to the mask pattern. 21 are exposed at the same time, and the same exposure area is formed in multiple unit areas 21 at the same time, thereby further reducing the frequent replacement of photomasks, simplifying the manufacturing process of the semiconductor structure, and improving the manufacturing process of the semiconductor structure. efficiency.
  • the number of the mask patterns is multiple; the specific steps of sequentially forming multiple exposure areas in the multiple unit areas 21 of the substrate 20 include:
  • the first loop steps include :
  • the current mask pattern is used to expose a plurality of the unit areas 21 in the substrate 20, and the exposure areas are formed in the plurality of unit areas 21 in a manner consistent with the current mask pattern.
  • the next adjacent mask pattern is used as the current mask pattern in the next first cycle step.
  • the number of the mask patterns is more than four, and each of the mask patterns performs the first cycle step at least once.
  • the number of the mask patterns is four, five, six or seven.
  • the number of the photomask patterns is four to ensure the complete formation of the packaged integrated circuit while saving process flow.
  • the specific steps of forming switching circuit structures in multiple exposure areas in multiple unit areas 21 include:
  • the plurality of exposure areas in the plurality of unit areas 21 are developed simultaneously, and the switching circuit structure is formed in the multiple exposure areas of each unit area 21 respectively.
  • the normal exposure range of a mask or photomask is 26 ⁇ 33mm2.
  • the transfer circuit structure formed in one unit area 21 needs to be able to package and integrate multiple first semiconductor devices and multiple second semiconductor devices, which results in the need to form one unit area 21
  • the size of the switching circuit structure is larger than the normal exposure range of a mask or photomask.
  • this specific embodiment provides a plurality of said photomask patterns, and transfers a plurality of said photomask patterns to one of said unit areas 21 respectively, so as to form a plurality of said photomask patterns in said unit area 21.
  • a plurality of the exposure areas corresponding to the mask patterns are spliced and combined to form a package integrated circuit exposure area by splicing and combining the multiple exposure areas in one unit area 21 .
  • the pattern structures of the plurality of photomask patterns are different from each other.
  • multiple photomask patterns When multiple photomask patterns are used to form multiple switching circuit structures in one unit area 21, multiple photomask patterns may be used to sequentially expose one unit area 21, and then The entire unit area 21 is developed, so that only one development is required in the process of forming multiple switching circuit structures in the unit area 21, saving the need to form a complete package in the unit area 21. Integrating the entire process of the circuit improves the process efficiency of the semiconductor structure and reduces the manufacturing cost of the semiconductor structure. Wherein, the packaged integrated circuit is formed by a combination of all the switching circuit structures in one of the unit areas 21.
  • the specific steps of using the current mask pattern to expose the plurality of unit areas 21 in the substrate 20 include:
  • the current mask pattern is used to sequentially expose multiple unit areas in the substrate 20 .
  • the number of the mask patterns is four, and the current mask pattern is used to simultaneously expose multiple unit areas in the substrate 20 in each first cycle step.
  • the four photomask patterns are arranged in sequence and are respectively the first photomask pattern, the second photomask pattern, the third photomask pattern and the fourth photomask pattern.
  • the first mask pattern, the second mask pattern, the third mask pattern and the fourth mask pattern are different from each other.
  • the first exposure area 30 is shown in Figure 3 .
  • the first cycle step is performed for a second time: first, a second mask is formed, the second mask includes a one-to-one correspondence with the plurality of unit areas 21 in the substrate 20 A plurality of the second mask patterns; then, a plurality of the second mask patterns are used to expose the plurality of unit areas 21 one by one to form a second mask pattern in each of the unit areas 21. Exposure area 40, as shown in Figure 4.
  • the first cycle step is performed for a third time: first, a third mask is formed, the third mask includes a one-to-one correspondence with the plurality of unit areas 21 in the substrate 20 A plurality of the third mask patterns; then, a plurality of the third mask patterns are used to expose the plurality of unit areas 21 one by one at the same time, forming a third unit area 21 in each unit area 21. Exposure area 50, as shown in Figure 5.
  • the first cycle step is performed for the fourth time: first, a fourth mask is formed, the fourth mask includes a one-to-one correspondence with the plurality of unit areas 21 in the substrate 20 A plurality of the fourth mask patterns; then, a plurality of the fourth mask patterns are used to expose a plurality of the unit areas 21 one by one to form a fourth mask pattern in each of the unit areas 21. Exposure area 60, as shown in Figure 6.
  • the switching circuit structure includes a first switching circuit structure 31 formed by developing the first exposure area 30, a second switching circuit structure 41 formed by developing the second exposure area 40, and a second switching circuit structure 41 formed by developing the second exposure area 40.
  • the first switching circuit structure 31 , the second switching circuit structure 41 , the third switching circuit structure 51 and the fourth switching circuit structure 61 are independent of each other. connect.
  • there are at least two of the first switching circuit structure 31 , the second switching circuit structure 41 , the third switching circuit structure 51 and the fourth switching circuit structure 61 . are electrically connected to each other.
  • the current mask pattern can also be used to sequentially modify the substrates.
  • the plurality of unit areas 21 in the bottom 20 are exposed to form different packaged integrated circuits in the plurality of unit areas 21 to improve the manufacturing flexibility of the semiconductor structure.
  • the specific steps of using the current mask pattern to sequentially expose multiple unit areas 21 in the substrate 20 include:
  • the second cycle step Steps include:
  • the current unit area is exposed at least once using the current mask pattern, at least one exposure area is formed in the current unit area, and the next unit area adjacent to the current unit area is used as the next unit area. Once the current unit area in the second loop step.
  • the current photomask pattern is used in a plurality of the When performing exposure in the unit area 21, first perform the second cycle step for the first time: use the current mask pattern to perform at least one exposure in the first unit area, and form at least one in the first unit area.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas 21 of the substrate 20 include:
  • the unit area 21 is exposed multiple times using the mask pattern, and a plurality of the exposure areas are sequentially formed in the unit area 21 .
  • the mask pattern can be used to expose multiple positions in the unit area 21 sequentially, so as to A plurality of the exposure areas with the same structure are formed in the unit area 21 so that a plurality of the same first semiconductor devices or a plurality of the same second semiconductor devices can be subsequently integrated or packaged.
  • the marks 22 are respectively formed at the edges of the plurality of unit areas 21 of the substrate 20 .
  • the mask pattern and the unit area can be aligned first through the formed mark 22, and then the alignment is performed. Exposure is performed to ensure the accuracy of the position of the formed exposure area on the substrate 20, thereby ensuring the accuracy of the position of the transfer circuit structure subsequently formed in the unit area 21, to avoid This solves the problem of subsequent inability to accurately package the first semiconductor device and the second semiconductor device due to the deviation of the transfer circuit structure.
  • the specific steps of sequentially forming multiple exposure areas in multiple unit areas 21 of the substrate 20 include:
  • a plurality of pre-exposure areas are respectively predefined in the plurality of unit areas 21;
  • Marks 22 are respectively formed at the edges of the plurality of pre-exposure areas in each unit area 21;
  • the exposure areas are respectively formed in the middle of the plurality of pre-exposure areas in each unit area 21 .
  • the pre-exposure area includes a device area 211 and a scribe line area 212 distributed around the periphery of the device area 211;
  • the mark 22 is formed in the scribe area 212 , and the exposure area is formed in the device area 211 .
  • each of the pre-exposure areas includes the device area 211 and the scribe area 212 distributed around the periphery of the device area 211.
  • the device area 211 is subsequently used to form the exposure area; the dicing track area 212 is subsequently used for cutting to separate the adjacent unit areas 21 .
  • the mark 22 is prevented from occupying the device area 211, which helps to improve the area utilization of the device area 211.
  • a marking mask can be formed, and multiple marking patterns corresponding to a plurality of the pre-exposure areas can be formed in the marking mask, and then, using the marking mask Expose and develop multiple kerf areas 212 in multiple pre-exposure areas at the same time, thereby forming the marks 22 in the kerf areas 212 of multiple pre-exposure areas at the same time to save money.
  • the entire process flow of forming the marks 22 in the plurality of pre-exposed areas in the unit area 21 simplifies the manufacturing process of the semiconductor structure.
  • the mark 22 described in this specific embodiment may be an alignment mark (Alignment Mark) or an overlay mark (Overlay Mark).
  • the cutting lane area 212 includes a first cutting lane extending along the first direction D1 and a second cutting lane intersecting the first cutting lane and extending along the second direction D2.
  • One direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate 20 , and the first direction D1 intersects the second direction D2; in each of the unit areas 21
  • the specific steps of forming marks 22 at the edges of multiple pre-exposure areas include:
  • a second mark is formed in the second cutting lane of the unit area 21 , and the first mark and the second mark together constitute the mark 22 .
  • the plurality of pre-exposure areas in each unit area 21 are rectangular, and the cutting track area 212 in each of the pre-exposure areas includes two edges.
  • the first cutting lane and the two second cutting lanes together form a frame-shaped cutting lane area 212 .
  • Each of the marks 22 includes the first mark located in the first cutting track and the second mark located in the second cutting track.
  • the first mark can ensure that the mask pattern and the device area 211 are aligned in the first direction D1
  • the second mark can ensure that the mask pattern and the device area 211 are aligned in the first direction D1.
  • Alignment in the second direction D2, that is, through the first mark and the second mark further ensures the accuracy of the position of the transfer circuit structure inside the device area 211, thereby further improving the subsequent integrated packaging. The accuracy of the first semiconductor device and the second semiconductor device.
  • the marks 22 at the edges of multiple pre-exposed areas in the unit area 21 are all the same; or,
  • the difference in the mark 22 means that one or both of the size and structure of the mark 22 are different.
  • the following steps are further included:
  • a dielectric layer covering the marks 22 is formed in a plurality of the unit areas 21 .
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit an oxide material (
  • An insulating dielectric material such as silicon dioxide is applied to the surface of the mark 22 and the surface of the substrate 20 and is processed through a planarization process such as chemical mechanical polishing (CMP) to form a layer covering the mark 22 and the substrate.
  • CMP chemical mechanical polishing
  • the dielectric layer of bottom 20 is formed before forming the transfer circuit structure, so as to reduce the influence of the mark 22 on the subsequent formation of the transfer circuit structure.
  • the following steps are also included:
  • the transfer board includes a plurality of the transfer circuit structures located in the unit areas 21;
  • At least one first semiconductor device 90 and at least one second semiconductor device 91 are packaged above the transfer board, and the transfer circuit structure is electrically connected to the first semiconductor device 90 and the second semiconductor device 91 .
  • the substrate 20 includes a plurality of unit regions 21 arranged in an array along the first direction D1 and the second direction D2, and any pair of two adjacent units 21 Quasi-arrangement means that the scribe line areas 212 in any two adjacent unit areas 21 are aligned, and the device areas 211 in any two adjacent unit areas 21 are also aligned.
  • the substrate 20 is cut along the scribe area 212 to divide the substrate 20 into a plurality of mutually independent unit areas 21 , and each unit area 21 serves as one of the adapter boards.
  • the substrate 20 in each transfer board serves as the transfer substrate.
  • Figure 7 is a schematic top view of the adapter plate in this embodiment. As shown in FIG. 7 , each of the transfer boards includes the transfer substrate and a packaged integrated circuit located above the transfer substrate.
  • Each of the packaged integrated circuits is composed of one of the unit areas 21 . All the switching circuit structures are spliced and combined.
  • FIG. 7 takes the packaged integrated circuit including the first switching circuit structure 31 , the second switching circuit structure 41 , the third switching circuit structure 51 and the fourth switching circuit structure 61 as an example. Be explained.
  • the transfer circuit structure is formed of conductive material and is used to integrate and package the first semiconductor device 90 and the second semiconductor device 91 to realize the connection between the first semiconductor device 90 and the second semiconductor device 91 . electrical connection between.
  • a plurality of first semiconductor devices 90 and a plurality of second semiconductor devices 91 are fixed on the adapter board, and the first semiconductor devices 91 are electrically connected.
  • the semiconductor device 90 is connected to the switching circuit structure, and is electrically connected to the second semiconductor device 91 and the switching circuit structure.
  • the first semiconductor device 90 may be, but is not limited to, HBM (High Bandwidth Memory).
  • the second semiconductor device 91 may be, but is not limited to, an ASIC (Application Specific Integrated Circuit).
  • the substrate 20 is a bare wafer, and the mark 22 is formed on the bare wafer.
  • This specific embodiment also provides a semiconductor structure, which is formed using the method for forming the semiconductor structure as described above.
  • the method for forming the semiconductor structure can be seen in Figures 1-8, and the schematic diagram of the semiconductor structure can be seen in Figures 2- Figure 8.
  • the semiconductor structure includes: including:
  • Substrate 20 said substrate including a plurality of unit areas 21;
  • each of the unit areas 21 includes a plurality of the switching circuit structures, and the same switching circuit structure exists in at least two of the unit areas 21 .
  • the material of the substrate 20 may be but is not limited to silicon. This specific embodiment will be described by taking the substrate 20 as a silicon substrate as an example.
  • the substrate 20 is a bare wafer.
  • a plurality of the unit regions 21 may be arranged in a two-dimensional array along the first direction D1 and the second direction D2 in the substrate 20 , wherein, The first direction D1 and the second direction D2 are both directions parallel to the top surface of the substrate 20 , and the first direction D1 and the second direction D2 intersect.
  • multiple switching circuit structures in the unit area 21 are all the same; or,
  • the normal exposure range of a mask is 26 ⁇ 33mm 2 .
  • multiple first semiconductor devices and multiple second semiconductor devices need to be packaged and integrated together, that is, one
  • the multiple transfer circuit structures formed in the unit area 21 need to be able to package and integrate multiple first semiconductor devices and multiple second semiconductor devices, which results in the need to form one in the unit area 21.
  • the size of the switching circuit structure is larger than the normal exposure range of a mask.
  • this specific embodiment provides multiple photomask patterns, and performs multiple exposures in the unit area 21 sequentially. After forming multiple exposure areas, the entire unit area 21 is developed. A packaged integrated circuit composed of a plurality of switching circuit structures is formed in the unit area 21 .
  • the semiconductor structure further includes:
  • the mark 22 is located at the edge of the unit area 21, and the unit area 21 includes a plurality of the marks 22 corresponding to a plurality of the switching circuit structures.
  • the mark 22 may be an alignment mark or an overlay mark.
  • the mark 22 is used to align the mask pattern with the unit area 21 during the process of forming the transfer circuit structure, so as to improve the position accuracy of the transfer circuit structure in the unit area 21, thereby The accuracy of integrated packaging of the first semiconductor device and the second semiconductor device through the transfer circuit structure is improved.
  • the semiconductor structure further includes:
  • a dielectric layer covers the mark 22, and the switching circuit structure is located above the dielectric layer.
  • the dielectric layer covering the mark 22 is formed before forming the transfer circuit structure, that is, the dielectric layer is formed between the mark 22 and the transfer circuit structure to reduce the number of The influence of the mark 22 on the subsequent formation of the switching circuit structure.
  • the material of the dielectric layer may be, but is not limited to, an insulating dielectric material such as an oxide material (such as silicon dioxide).
  • Some embodiments of this specific embodiment provide a semiconductor structure and a method for forming the same. After sequentially forming multiple exposure areas in multiple unit areas on the substrate, the multiple exposure areas in the multiple unit areas are then separately formed. A transfer circuit pattern is formed, and the transfer circuit patterns formed by all the exposure areas in each of the unit areas together constitute a packaged integrated circuit. That is, some embodiments of this specific implementation mode use multiple circuits in the entire unit area. After multiple exposure areas are formed by one exposure, a transfer circuit structure is simultaneously formed in multiple exposure areas through one development, thereby simplifying the formation process of the packaged integrated circuit and improving the manufacturing efficiency of the packaged integrated circuit.
  • some embodiments of this specific embodiment provide an alignment basis for the subsequent formation of switching circuit structures in the unit area by forming marks in each unit area of the substrate, thereby improving the efficiency of forming the switching circuit structure in the unit area.
  • the accuracy of the switching circuit structure improves the manufacturing yield of packaged integrated circuits.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构的形成方法包括如下步骤：提供衬底，所述衬底包括多个单元区域；于所述衬底的多个所述单元区域中依次形成多个曝光区域；于多个所述单元区域中多个曝光区域分别形成转接电路结构。本公开提高了半导体结构的制造效率。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年07月21日递交的中国专利申请号202210859317.5、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
目前，半导体集成电路(IC)产业已经经历了指数式增长。IC材料和设计中的技术进步已经产生了数代IC，其中，每代IC都比前一代IC具有更小和更复杂的电路。在IC发展的过程中，功能密度(即每一芯片面积上互连器件的数量)普遍增加，几何尺寸(即使用制造工艺可以产生的最小部件)不断减小。除了IC部件变得更小和更复杂之外，在其上制造IC的晶圆变得越来越大，提高半导体器件的集成度已成为当前发展的重要方向。
为了提高半导体器件的集成度，通常需要将多个存储芯片与逻辑芯片整合在一起，形成半导体器件。通过所述逻辑芯片向所述存储芯片发送控制信号，以实现存储芯片的写入、读取和擦除等操作。当前在整合多颗存储芯片与逻辑芯片的过程中，由于用于整合多颗存储芯片和逻辑芯片的封装整合电路需要频繁更换掩膜版，并分别进行多次曝光、显影工艺，因而，存在整合效率低等问题，从而降低了半导体制造效率。
因此，如何提高封装整合电路的制造效率，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于提高封装整合电路的制造效率，从而提高半导体结构的制造效率。
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：
提供衬底，所述衬底包括多个单元区域；
于所述衬底的多个所述单元区域中依次形成多个曝光区域；
于多个所述单元区域中多个曝光区域分别形成转接电路结构。
在一些实施例中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
提供光罩图案；
采用所述光罩图案同时对所述衬底中的多个所述单元区域进行曝光，同时于多个所述单元区域中形成所述曝光区域。
在一些实施例中，所述光罩图案的数量为多个；于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
对多个所述光罩图案依次排序；
选择一个光罩图案作为当前光罩图案，并执行多次第一循环步骤，直至于所述衬底的多个所述单元区域中依次形成多个曝光区域，所述第一循环步骤包括：
采用所述当前光罩图案对所述衬底中的多个所述单元区域进行曝光，于多个所述单元区域中形成所述曝光区域，且以与所述当前光罩图案相邻的下一光罩图案作为下一次所述第一循环步骤中的当前光罩图案。
在一些实施例中，采用所述当前光罩图案对所述衬底中的多个所述单元区域进行曝光的具体步骤包括：
采用所述当前光罩图案同时对所述衬底中的多个所述单元区域进行曝光；或者，
采用所述当前光罩图案依次对所述衬底中的多个所述单元区域进行曝光。
在一些实施例中，采用所述当前光罩图案依次对所述衬底中的多个所述单元区域进行曝光的具体步骤包括：
选择一个单元区域作为当前单元区域，并执行多次第二循环步骤，直至所述当前光罩图案完成对所述衬底中的多个所述单元区域的曝光，所述第二循环步骤包括：
采用所述当前光罩图案对所述当前单元区域进行至少一次曝光，于所述当前单元区域中形成至少一个所述曝光区域，并以与所述当前单元区域相邻的下一单元区域作为下一次所述第二循环步骤中的当前单元区域。
在一些实施例中，所述光罩图案的数量为四个以上，且每个所述光罩图案执行至少一次所述循环步骤。
在一些实施例中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
提供光罩图案；
采用所述光罩图案对所述单元区域进行多次曝光，于所述单元区域中依次形成多个所述曝光区域。
在一些实施例中，于所述衬底的多个所述单元区域中依次形成多个曝光区域之前，还包括如下步骤：
于所述衬底的多个所述单元区域的边缘处分别形成所述标记。
在一些实施例中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
于多个所述单元区域中分别预先定义多个预曝光区域；
于每个所述单元区域的多个所述预曝光区域的边缘处分别形成标记；
于每个所述单元区域的多个所述预曝光区域的中部分别形成所述曝光区域。
在一些实施例中，所述预曝光区域包括器件区域、以及围绕所述器件区域的外周分布的切割道区域；
所述标记形成于所述切割道区域，所述曝光区域形成于所述器件区域。
在一些实施例中，所述切割道区域包括沿第一方向延伸的第一切割道、以及与所述第一切割道相交且沿第二方向延伸的第二切割道，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；于每个所述单元区域的多个所述预曝光区域的边缘处分别形成标记的具体步骤包括：
于所述单元区域的所述第一切割道中形成第一标记；
于所述单元区域的所述第二切割道中形成第二标记，所述第一标记和所述第二标记共同构成所述标记。
在一些实施例中，所述单元区域内的多个所述预曝光区域的边缘处的所述标记均相同；或者，
所述单元区域内至少存在两个所述预曝光区域的边缘处的所述标记不同。
在一些实施例中，于每个所述单元区域的多个所述预曝光区域的中部分别形成所述曝光区域之前，还包括如下步骤：
于多个所述单元区域中形成覆盖所述标记的介质层。
在一些实施例中，于多个所述单元区域中多个曝光区域分别形成转接电路结构的具体步骤包括：
对多个所述单元区域中的多个所述曝光区域同时进行显影，于每个所述单元区域的多个所述曝光区域分别形成所述转接电路结构。
在一些实施例中，于多个所述单元区域中多个曝光区域分别形成转接电路结构之后，还包括如下步骤：
切割所述衬底，形成与多个所述单元区域一一对应的多个转接板，所述转接板包括位于所述单元区域内的多个所述转接电路结构；
于所述转接板上方封装至少一个第一半导体器件和至少一个第二半导体器件，所述转接电路结构电连接所述第一半导体器件和所述第二半导体器件。
在一些实施例中，所述衬底为裸晶圆，所述标记形成于所述裸晶圆上。
根据另一些实施例，本公开还提供了一种半导体结构，采用如上所述的半导体结构的 形成方法形成，包括：
衬底，所述衬底包括多个单元区域；
转接电路结构，每个所述单元区域包括多个所述转接电路结构，至少两个所述单元区域中存在相同的所述转接电路结构。
在一些实施例中，所述单元区域中的多个所述转接电路结构均相同；或者，
所述单元区域中至少存在两个不同的所述转接电路结构。
在一些实施例中，还包括：
标记，位于所述单元区域的边缘处，且所述单元区域中包括与多个所述转接电路结构一一对应的多个所述标记。
在一些实施例中，还包括：
介质层，覆盖所述标记，所述转接电路结构位于所述介质层上方。
本公开一些实施例提供的半导体结构及其形成方法，通过在衬底上的多个单元区域中依次形成多个曝光区域之后，再于多个所述单元区域中的多个曝光区域分别形成转接电路图案，每个所述单元区域中的所有所述曝光区域形成的所述转接电路图案共同构成封装整合电路，即本公开一些实施例是在整个所述单元区域通过多次曝光形成多个所述曝光区域之后，再通过一次显影于多个所述曝光区域同时形成转接电路结构，从而简化了封装整合电路的形成工艺，提高了封装整合电路的制造效率。另外，本公开一些实施例通过在衬底的每个单元区域中分别形成标记，为后续在所述单元区域中形成转接电路结构提供了对准依据，从而提高了在单元区域中形成转接电路结构的精度，改善了封装整合电路的制造良率。
附图说明
附图1是本公开具体实施方式中半导体结构的形成方法流程图；
附图2-附图8是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2-附图8是本公开具体实施方式在形成半导体结构的过程中主要的工艺结构示意图。如图1-图8所示，所述半导体结构的形成方法，包括如下步骤：
步骤S11，提供衬底20，所述衬底20包括多个单元区域21，如图2所示。
所述衬底20的材料可以是但不限于硅，本具体实施方式以所述衬底20为硅衬底为例进行说明。在一实施例中，可以采用光刻工艺在所述衬底20中定义多个所述单元区域21。为了提高对所述衬底20上空间的利用率，多个所述单元区域21可以在所述衬底20中沿第一方向D1和第二方向D2呈二维阵列排布，其中，所述第一方向D1和所述第二方向D2均为平行于所述衬底20的顶面的方向，且所述第一方向D1和所述第二方向D2相交。本具体实施方式中的图2-图8是以所述衬底20上包括四个单元区域21为例进行说明。所述单元区域21后续用作封装整合第一半导体器件和第二半导体器件的转接结构(例如转接板)，因此，可以根据所需封装整合的所述第一半导体器件的结构和数量、以及所述第二半导体器件的结构和数量，调整所述单元区域21的尺寸大小。在本具体实施方式中，多个所述单元区域21的尺寸和形状均相同。本具体实施方式中的多个是指两个以上。其中，所述第一半导体器件和所述第二半导体器件为存储芯片、逻辑芯片、图像传感器、处理器、电源芯片中的人任一种或者两种以上的组合。
在一实施例中，任意相邻的两个所述单元区域21之间具有空隙，以便于后续通过切割工艺分割相邻的所述单元区域21，降低对所述单元区域21内部造成损伤的风险。在另一实施例中，任意相邻的两个所述单元区域21的边缘相接触且任意相邻的两个所述单元区域21 不交叠，以进一步提高对所述衬底20上空间的利用率。
步骤S12，于所述衬底20的多个所述单元区域21中依次形成多个曝光区域，如图2所示。
步骤S13，于多个所述单元区域21中多个曝光区域分别形成转接电路结构。
在一些实施例中，于所述衬底20的多个所述单元区域21中依次形成多个曝光区域的具体步骤包括：
提供光罩图案；
采用所述光罩图案同时对所述衬底中的多个所述单元区域21进行曝光，同时于多个所述单元区域21中形成所述曝光区域。
本具体实施方式中所述的曝光区域是指采用光罩图案进行曝光后、且未进行显影的区域。具体来说，根据需要在所述单元区域21中形成的所述转接电路结构的具体结构，选择相应的所述光罩图案，并采用所述光罩图案在所述单元区域21中进行曝光。由于本具体实施方式在所述衬底20上设置了多个所述单元区域21，采用所述光罩图案对需要形成与所述光罩图案对应的转接电路结构的多个所述单元区域21同时进行曝光，同时在多个所述单元区域21中形成相同的所述曝光区域，从而可以进一步减少频繁更换光罩的操作，简化所述半导体结构的制造流程，提高所述半导体结构的制造效率。
在一些实施例中，所述光罩图案的数量为多个；于所述衬底20的多个所述单元区域21中依次形成多个曝光区域的具体步骤包括：
对多个所述光罩图案依次排序；
选择一个光罩图案作为当前光罩图案，并执行多次第一循环步骤，直至于所述衬底20的多个所述单元区域21中依次形成多个曝光区域，所述第一循环步骤包括：
采用所述当前光罩图案对所述衬底20中的多个所述单元区域21进行曝光，于多个所述单元区域21中形成所述曝光区域，且以与所述当前光罩图案相邻的下一光罩图案作为下一次所述第一循环步骤中的当前光罩图案。
在一些实施例中，所述光罩图案的数量为四个以上，且每个所述光罩图案执行至少一次所述第一循环步骤。举例来说，所述光罩图案的数量为四个、五个、六个或者七个。优选的，所述光罩图案的数量为四个，以在节省工艺流程的同时，确保完整的所述封装整合电路的形成。
在一些实施例中，于多个所述单元区域21中多个曝光区域分别形成转接电路结构的具体步骤包括：
对多个所述单元区域21中的多个所述曝光区域同时进行显影，于每个所述单元区域21的多个所述曝光区域分别形成所述转接电路结构。
具体来说，一块掩膜版或者光罩的正常曝光范围为26×33mm2，为了提高集成度，需要将多个所述第一半导体器件与多个所述第二半导体器件一起进行封装整合，即一个所述单元区域21中形成的所述转接电路结构需要能够封装整合多个所述第一半导体器件和多个所述第二半导体器件，这就导致一个所述单元区域21中所需形成的所述转接电路结构的尺寸大于一块掩膜版或者光罩的正常曝光范围。为此，本具体实施方式提供多个所述光罩图案，并将多个所述光罩图案分别转移至一个所述单元区域21中，以于所述单元区域21中形成与多个所述光罩图案分别对应的多个所述曝光区域，由一个所述单元区域21中的多个所述曝光区域拼接、组合形成一个所述封装整合电路曝光区域。在一实施例中，多个所述光罩图案的图案结构互不相同。
当采用多个所述光罩图案在一个所述单元区域21中形成多个所述转接电路结构时，可以采用多个所述光罩图案依次对一个所述单元区域21进行曝光之后，再对整个所述单元区域21进行显影，从而可以在所述单元区域21内形成多个所述转接电路结构的工艺中仅需进行一次显影，节省了在所述单元区域21中形成完整的封装整合电路的整个流程，提高了所述半导体结构的制程效率，并降低了所述半导体结构的制造成本。其中，所述封装整合 电路由一个所述单元区域21内所有的所述转接电路结构组合形成。
在一些实施例中，采用所述当前光罩图案对所述衬底20中的多个所述单元区域21进行曝光的具体步骤包括：
采用所述当前光罩图案同时对所述衬底20中的多个所述单元区域进行曝光；或者，
采用所述当前光罩图案依次对所述衬底20中的多个所述单元区域进行曝光。
以下以所述光罩图案的数量为四个、且在每一次所述第一循环步骤中采用所述当前光罩图案同时对所述衬底20中的多个所述单元区域进行曝光为例进行说明。举例来说，对四个所述光罩图案依次排序，分别为第一个光罩图案、第二个光罩图案、第三个光罩图案和第四个光罩图案。所述第一光罩图案、所述第二光罩图案、所述第三光罩图案和所述第四光罩图案互不相同。先执行第一次所述第一循环步骤的过程：首先，形成第一掩膜版，所述第一掩膜版中包括与所述衬底20中的多个所述单元区域21一一对应的多个所述第一个光罩图案；接着，同时采用多个所述第一个光罩图案一一对多个所述单元区域21进行曝光，于每个是所述单元区域21中形成第一曝光区域30，如图3所示。接着，执行第二次所述第一循环步骤：首先，形成第二掩膜版，所述第二掩膜版中包括与所述衬底20中的多个所述单元区域21一一对应的多个所述第二个光罩图案；接着，同时采用多个所述第二个光罩图案一一对多个所述单元区域21进行曝光，于每个所述单元区域21中形成第二曝光区域40，如图4所示。接着，执行第三次所述第一循环步骤：首先，形成第三掩膜版，所述第三掩膜版中包括与所述衬底20中的多个所述单元区域21一一对应的多个所述第三个光罩图案；接着，同时采用多个所述第三个光罩图案一一对多个所述单元区域21进行曝光，于每个所述单元区域21中形成第三曝光区域50，如图5所示。之后，执行第四次所述第一循环步骤：首先，形成第四掩膜版，所述第四掩膜版中包括与所述衬底20中的多个所述单元区域21一一对应的多个所述第四个光罩图案；接着，同时采用多个所述第四个光罩图案一一对多个所述单元区域21进行曝光，于每个所述单元区域21中形成第四曝光区域60，如图6所示。
在执行完上述的四次所述循环步骤之后，同时对所述衬底20上的所有所述单元区域21进行显影，从而同时在所述衬底20上的所有所述单元区域21中分别形成多个所述转接电路结构。其中，所述转接电路结构包括由所述第一曝光区域30显影形成的第一转接电路结构31、由所述第二曝光区域40显影形成的第二转接电路结构41、由所述第三曝光区域50显影形成的第三转接电路结构51、以及由所述第四曝光区域50显影形成的第四转接电路结构51，参见图7。在一实施例中，所述第一转接电路结构31、所述第二转接电路结构41、所述第三转接电路结构51和所述第四转接电路结构61相互独立、互不连接。在另一实施例中，所述第一转接电路结构31、所述第二转接电路结构41、所述第三转接电路结构51和所述第四转接电路结构61中至少存在两者相互电连接。
以上是以采用所述当前光罩图案同时对多个所述单元区域21进行曝光为例进行说明，以进一步简化所述半导体结构的光刻步骤。在另一些实施例中，当多个所述单元区域21中需要形成与所述当前光罩图案对应的转接电路结构的位置不同时，也可以采用所述当前光罩图案依次对所述衬底20中的多个所述单元区域21进行曝光，以在多个所述单元区域21中形成不同的封装整合电路，以提高所述半导体结构的制造灵活性。
在一些实施例中，采用所述当前光罩图案依次对所述衬底20中的多个所述单元区域21进行曝光的具体步骤包括：
选择一个单元区域21作为当前单元区域，并执行多次第二循环步骤，直至所述当前光罩图案完成对所述衬底20中的多个所述单元区域21的曝光，所述第二循环步骤包括：
采用所述当前光罩图案对所述当前单元区域进行至少一次曝光，于所述当前单元区域中形成至少一个所述曝光区域，并以与所述当前单元区域相邻的下一单元区域作为下一次所述第二循环步骤中的当前单元区域。
以所述衬底20上包括四个单元区域，即第一单元区域、第二单元区域、第三单元区域 和第四单元区域为例，在采用所述当前光罩图案依次在多个所述单元区域21中进行曝光时，先执行第一次所述第二循环步骤：采用所述当前光罩图案在所述第一单元区域进行至少一次曝光，于所述第一单元区域中形成至少一个所述曝光区域；再执行第二次所述第二循环步骤：采用所述当前光罩图案在所述第二单元区域进行至少一次曝光，于所述第二单元区域中形成至少一个所述曝光区域；再执行第三次所述第二循环步骤：采用所述当前光罩图案在所述第三单元区域进行至少一次曝光，于所述第三单元区域中形成至少一个所述曝光区域；最后执行第四次所述第二循环步骤：采用所述当前光罩图案在所述第四单元区域进行至少一次曝光，于所述第四单元区域中形成至少一个所述曝光区域。
在一些实施例中，于所述衬底20的多个所述单元区域21中依次形成多个曝光区域的具体步骤包括：
提供光罩图案；
采用所述光罩图案对所述单元区域21进行多次曝光，于所述单元区域21中依次形成多个所述曝光区域。
具体来说，当需要在所述单元区域21中形成多个相同的所述转接电路图案时，可以采用所述光罩图案对所述单元区域21中的多个位置分别依次进行曝光，以于所述单元区域21中形成多个结构相同的所述曝光区域，使得后续能够整合或者封装多个相同的所述第一半导体器件或者多个相同的所述第二半导体器件。
在一些实施例中，于所述衬底20的多个所述单元区域21中依次形成多个曝光区域之前，还包括如下步骤：
于所述衬底20的多个所述单元区域21的边缘处分别形成所述标记22。
具体来说，在采用光刻工艺于所述单元区域21中形成所述曝光区域时，可以先通过已形成的所述标记22对准所述光罩图案和所述单元区域，对准之后再进行曝光，以确保形成的所述曝光区域在所述衬底20上的位置的准确性，进而确保了后续在所述单元区域21中形成的所述转接电路结构的位置的准确性，避免了因所述转接电路结构偏移导致后续无法准确封装所述第一半导体器件和所述第二半导体器件的问题。
在一些实施例中，于所述衬底20的多个所述单元区域21中依次形成多个曝光区域的具体步骤包括：
于多个所述单元区域21中分别预先定义多个预曝光区域；
于每个所述单元区域21的多个所述预曝光区域的边缘处分别形成标记22；
于每个所述单元区域21的多个所述预曝光区域的中部分别形成所述曝光区域。
在一些实施例中，所述预曝光区域包括器件区域211、以及围绕所述器件区域211的外周分布的切割道区域212；
所述标记22形成于所述切割道区域212，所述曝光区域形成于所述器件区域211。
具体来说，所述单元区域21中多个所述预曝光区域，每个所述预曝光区域均包括所述器件区域211、以及环绕所述器件区域211的外周分布的所述切割道区域212。其中，所述器件区域211后续用于形成所述曝光区域；所述切割道区域212后续用于切割，以分离相邻的所述单元区域21。本具体实施方式通过将所述标记22仅形成在所述切割道区域212中，避免所述标记22占用所述器件区域211，有助于提高所述器件区域211的面积利用率。而且，本具体实施方式可以形成一个标记掩膜版，且在所述标记掩膜版中形成与多个所述预曝光区域一一对应的多个标记图案，然后，采用所述标记掩膜版同时对多个所述预曝光区域中的多个所述切割道区域212进行曝光、显影，从而同时于多个所述预曝光区域的所述切割道区域212中形成所述标记22，以节省在所述单元区域21中的多个所述预曝光区域内形成所述标记22的整个工艺流程，简化了所述半导体结构的制程工艺。本具体实施方式中所述的标记22可以是对准标记(Alignment Mark)，也可以是套刻标记(Overlay Mark)。
在一些实施例中，所述切割道区域212包括沿第一方向D1延伸的第一切割道、以及与所述第一切割道相交且沿第二方向D2延伸的第二切割道，所述第一方向D1和所述第二方 向D2均为平行于所述衬底20的顶面的方向，且所述第一方向D1与所述第二方向D2相交；于每个所述单元区域21的多个所述预曝光区域的边缘处分别形成标记22的具体步骤包括：
于所述单元区域21的所述第一切割道中形成第一标记；
于所述单元区域21的所述第二切割道中形成第二标记，所述第一标记和所述第二标记共同构成所述标记22。
举例来说，如图2所示，每个所述单元区域21内的多个所述预曝光区域均呈矩形，每个所述预曝光区域中的所述切割道区域212包括两条沿所述第一方向D1延伸的所述第一切割道、以及两条沿所述第二方向D2延伸的所述第二切割道，每条所述第一切割道沿所述第一方向D1相对的两端部分别与两条所述第二切割道连接，每条所述第二切割道沿所述第二方向D2相对的两端部分别与两条所述第一切割道连接，两条所述第一切割道和两条所述第二切割道共同形成围框状的所述切割道区域212。每个所述标记22均包括位于所述第一切割道中的所述第一标记和位于所述第二切割道中的所述第二标记，在后续形成所述转接电路结构的过程中，通过所述第一标记可以确保光罩图案与所述器件区域211在所述第一方向D1上对准，并同时通过所述第二标记确保所述光罩图案与所述器件区域211在所述第二方向D2上对准，即通过所述第一标记和所述第二标记进一步确保了所述转接电路结构在所述器件区域211内部位置的精确度，从而进一步提高了后续整合封装所述第一半导体器件和所述第二半导体器件的精准度。
为了简化所述标记22的形成工艺，在一些实施例中，所述单元区域21内的多个所述预曝光区域的边缘处的所述标记22均相同；或者，
为了满足采用不同的光罩图案在所述单元区域21内形成不同的曝光区域的需求，所述单元区域21内至少存在两个所述预曝光区域的边缘处的所述标记22不同。在一示例中，所述标记22不同是指所述标记22的尺寸、结构中的一者或者两者不同。
在一些实施例中，于每个所述单元区域21的多个所述预曝光区域的中部分别形成所述曝光区域之前，还包括如下步骤：
于多个所述单元区域21中形成覆盖所述标记22的介质层。
举例来说，在采用光刻工艺于所述衬底20的所述单元区域21中形成所述标记22之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氧化物材料(例如二氧化硅)等绝缘介质材料于所述标记22的表面和所述衬底20的表面，并通过化学机械研磨(CMP)等平坦化工艺处理之后，形成覆盖所述标记22和所述衬底20的所述介质层。本具体实施方式通过在形成所述转接电路结构之前，形成覆盖所述标记22的所述介质层，以减少所述标记22对后续形成所述转接电路结构的影响。
在一些实施例中，于多个所述单元区域21中多个曝光区域分别形成转接电路结构之后，还包括如下步骤：
切割所述衬底20，形成与多个所述单元区域21一一对应的多个转接板，所述转接板包括位于所述单元区域21内的多个所述转接电路结构；
于所述转接板上方封装至少一个第一半导体器件90和至少一个第二半导体器件91，所述转接电路结构电连接所述第一半导体器件90和所述第二半导体器件91。
举例来说，所述衬底20上包括沿所述第一方向D1和所述第二方向D2呈阵列排布的多个所述单元区域21，且任意相邻的两个所述单元21对准排布，即任意相邻的两个所述单元区域21中的所述切割道区域212对准、且任意相邻的两个所述单元区域21中的所述器件区域211也对准。沿所述切割道区域212切割所述衬底20，以将所述衬底20分割为多个相互独立的所述单元区域21，每个所述单元区域21作为一个所述转接板。每个所述转接板中的所述衬底20作为所述转接衬底。附图7是本具体实施方式中转接板的俯视结构示意图。如图7所示，每个所述转接板包括所述转接衬底、以及位于所述转接衬底上方的封装整合电路，每个所述封装整合电路由一个所述单元区域21中所有的所述转接电路结构拼接、组合构成。图7以所述封装整合电路包括所述第一转接电路结构31、所述第二转接电路结构 41、所述第三转接电路结构51和所述第四转接电路结构61为例进行说明。
所述转接电路结构采用导电材料形成，用于在整合封装所述第一半导体器件90和所述第二半导体器件91，以实现所述第一半导体器件90与所述第二半导体器件91之间的电连接。举例来说，在形成所述转接板之后，将多个所述第一半导体器件90和多个所述第二半导体器件91均固定于所述转接板上，且电连接所述第一半导体器件90与所述转接电路结构、并电连接所述第二半导体器件91与所述转接电路结构。在一示例中，所述存第一半导体器件90可以是但不限于HBM(High Bandwidth Memory，高带宽存储器)。所述第二半导体器件91可以是但不限于ASIC(Application Specific Integrated Circuit，专用集成电路)。
为了简化工艺制程、节约制造成本，在一些实施例中，所述衬底20为裸晶圆，所述标记22形成于所述裸晶圆上。
本具体实施方式还提供了一种半导体结构，采用如上所述的半导体结构的形成方法形成，所述半导体结构的形成方法可以参见图1-图8，所述半导体结构的示意图可以参见图2-图8。如图2-图8所示，所述半导体结构，包括：包括：
衬底20，所述衬底包括多个单元区域21；
转接电路结构，每个所述单元区域21包括多个所述转接电路结构，至少两个所述单元区域21中存在相同的所述转接电路结构。
具体来说，所述衬底20的材料可以是但不限于硅，本具体实施方式以所述衬底20为硅衬底为例进行说明。在一实施例中，所述衬底20为裸晶圆。为了提高对所述衬底20上空间的利用率，多个所述单元区域21可以在所述衬底20中沿第一方向D1和第二方向D2呈二维阵列排布，其中，所述第一方向D1和所述第二方向D2均为平行于所述衬底20的顶面的方向，且所述第一方向D1和所述第二方向D2相交。
为了简化所述半导体结构的制造工艺，在一些实施例中，所述单元区域21中的多个所述转接电路结构均相同；或者，
所述单元区域21中至少存在两个不同的所述转接电路结构，以满足不同半导体器件封装整合的需求。
具体来说，一块掩膜版的正常曝光范围为26×33mm 2，为了提高集成度，需要将多个所述第一半导体器件与多个所述第二半导体器件一起进行封装整合，即一个所述单元区域21中形成的多个所述转接电路结构需要能够封装整合多个所述第一半导体器件与多个所述第二半导体器件，这就导致一个所述单元区域21中所需形成的所述转接电路结构的尺寸大于一块掩膜版的正常曝光范围。为此，本具体实施方式提供多个所述光罩图案，并在所述单元区域21中依次进行多次曝光，形成多个所述曝光区域之后，再对整个所述单元区域21进行显影，以于所述单元区域21中形成由多个所述转接电路结构构成的封装整合电路。
在一些实施例中，所述半导体结构还包括：
标记22，位于所述单元区域21的边缘处，且所述单元区域21中包括与多个所述转接电路结构一一对应的多个所述标记22。其中，所述标记22可以为对准标记，也可以为套刻标记。所述标记22用于在形成转接电路结构的过程中进行光罩图案与所述单元区域21的对准，以提高所述转接电路结构在所述单元区域21内的位置精确度，从而提高通过所述转接电路结构整合封装第一半导体器件和第二半导体器件的精度。
在一些实施例中，所述半导体结构还包括：
介质层，覆盖所述标记22，所述转接电路结构位于所述介质层上方。
本具体实施方式通过在形成所述转接电路结构之前，形成覆盖所述标记22的所述介质层，即在所述标记22与所述转接电路结构之间形成所述介质层，以减少所述标记22对后续形成所述转接电路结构的影响。其中，所述介质层的材料可以是但不限于氧化物材料(例如二氧化硅)等绝缘介质材料。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过在衬底上的多个单元区域中依次形成多个曝光区域之后，再于多个所述单元区域中的多个曝光区域分别形成 转接电路图案，每个所述单元区域中的所有所述曝光区域形成的所述转接电路图案共同构成封装整合电路，即本具体实施方式一些实施例是在整个所述单元区域通过多次曝光形成多个所述曝光区域之后，再通过一次显影于多个所述曝光区域同时形成转接电路结构，从而简化了封装整合电路的形成工艺，提高了封装整合电路的制造效率。另外，本具体实施方式一些实施例通过在衬底的每个单元区域中分别形成标记，为后续在所述单元区域中形成转接电路结构提供了对准依据，从而提高了在单元区域中形成转接电路结构的精度，改善了封装整合电路的制造良率。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种半导体结构的形成方法，包括如下步骤：
    提供衬底，所述衬底包括多个单元区域；
    于所述衬底的多个所述单元区域中依次形成多个曝光区域；
    于多个所述单元区域中多个曝光区域分别形成转接电路结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
    提供光罩图案；
    采用所述光罩图案同时对所述衬底中的多个所述单元区域进行曝光，同时于多个所述单元区域中形成所述曝光区域。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述光罩图案的数量为多个；于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
    对多个所述光罩图案依次排序；
    选择一个光罩图案作为当前光罩图案，并执行多次第一循环步骤，直至于所述衬底的多个所述单元区域中依次形成多个曝光区域，所述第一循环步骤包括：
    采用所述当前光罩图案对所述衬底中的多个所述单元区域进行曝光，于多个所述单元区域中形成所述曝光区域，且以与所述当前光罩图案相邻的下一光罩图案作为下一次所述第一循环步骤中的当前光罩图案。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，采用所述当前光罩图案对所述衬底中的多个所述单元区域进行曝光的具体步骤包括：
    采用所述当前光罩图案同时对所述衬底中的多个所述单元区域进行曝光；或者，
    采用所述当前光罩图案依次对所述衬底中的多个所述单元区域进行曝光。
  5. 根据权利要求3所述的半导体结构的形成方法，其中，采用所述当前光罩图案依次对所述衬底中的多个所述单元区域进行曝光的具体步骤包括：
    选择一个单元区域作为当前单元区域，并执行多次第二循环步骤，直至所述当前光罩图案完成对所述衬底中的多个所述单元区域的曝光，所述第二循环步骤包括：
    采用所述当前光罩图案对所述当前单元区域进行至少一次曝光，于所述当前单元区域中形成至少一个所述曝光区域，并以与所述当前单元区域相邻的下一单元区域作为下一次所述第二循环步骤中的当前单元区域。
  6. 根据权利要求3所述的半导体结构的形成方法，其中，所述光罩图案的数量为四个以上，且每个所述光罩图案执行至少一次所述循环步骤。
  7. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
    提供光罩图案；
    采用所述光罩图案对所述单元区域进行多次曝光，于所述单元区域中依次形成多个所述曝光区域。
  8. 根据权利要求1所述的半导体结构的形成方法，其中，于所述衬底的多个所述单元区域中依次形成多个曝光区域之前，还包括如下步骤：
    于所述衬底的多个所述单元区域的边缘处分别形成标记。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，于所述衬底的多个所述单元区域中依次形成多个曝光区域的具体步骤包括：
    于多个所述单元区域中分别预先定义多个预曝光区域；
    于每个所述单元区域的多个所述预曝光区域的边缘处分别形成标记；
    于每个所述单元区域的多个所述预曝光区域的中部分别形成所述曝光区域。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，所述预曝光区域包括器件区域、以及围绕所述器件区域的外周分布的切割道区域；
    所述标记形成于所述切割道区域，所述曝光区域形成于所述器件区域。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，所述切割道区域包括沿第一方向延伸的第一切割道、以及与所述第一切割道相交且沿第二方向延伸的第二切割道，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；于每个所述单元区域的多个所述预曝光区域的边缘处分别形成标记的具体步骤包括：
    于所述单元区域的所述第一切割道中形成第一标记；
    于所述单元区域的所述第二切割道中形成第二标记，所述第一标记和所述第二标记共同构成所述标记。
  12. 根据权利要求9所述的半导体结构的形成方法，其中，所述单元区域内的多个所述预曝光区域的边缘处的所述标记均相同；或者，
    所述单元区域内至少存在两个所述预曝光区域的边缘处的所述标记不同。
  13. 根据权利要求9所述的半导体结构的形成方法，其中，于每个所述单元区域的多个所述预曝光区域的中部分别形成所述曝光区域之前，还包括如下步骤：
    于多个所述单元区域中形成覆盖所述标记的介质层。
  14. 根据权利要求1所述的半导体结构的形成方法，其中，于多个所述单元区域中多个曝光区域分别形成转接电路结构的具体步骤包括：
    对多个所述单元区域中的多个所述曝光区域同时进行显影，于每个所述单元区域的多个所述曝光区域分别形成所述转接电路结构。
  15. 根据权利要求1所述的半导体结构的形成方法，其中，于多个所述单元区域中多个曝光区域分别形成转接电路结构之后，还包括如下步骤：
    切割所述衬底，形成与多个所述单元区域一一对应的多个转接板，所述转接板包括位于所述单元区域内的多个所述转接电路结构；
    于所述转接板上方封装至少一个第一半导体器件和至少一个第二半导体器件，所述转接电路结构电连接所述第一半导体器件和所述第二半导体器件。
  16. 根据权利要求8所述的半导体结构的形成方法，其中，所述衬底为裸晶圆，所述标记形成于所述裸晶圆上。
  17. 一种半导体结构，采用如权利要求1所述的半导体结构的形成方法形成，包括：
    衬底，所述衬底包括多个单元区域；
    转接电路结构，每个所述单元区域包括多个所述转接电路结构，至少两个所述单元区域中存在相同的所述转接电路结构。
  18. 根据权利要求17所述半导体结构，其中，所述单元区域中的多个所述转接电路结构均相同；或者，
    所述单元区域中至少存在两个不同的所述转接电路结构。
  19. 根据权利要求17所述的半导体结构，还包括：
    标记，位于所述单元区域的边缘处，且所述单元区域中包括与多个所述转接电路结构一一对应的多个所述标记。
  20. 根据权利要求19所述的半导体结构，还包括：
    介质层，覆盖所述标记，所述转接电路结构位于所述介质层上方。
PCT/CN2022/109872 2022-07-21 2022-08-03 半导体结构及其形成方法 WO2024016384A1 (zh)

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