WO2024014209A1 - 撮像装置 - Google Patents

撮像装置 Download PDF

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Publication number
WO2024014209A1
WO2024014209A1 PCT/JP2023/021813 JP2023021813W WO2024014209A1 WO 2024014209 A1 WO2024014209 A1 WO 2024014209A1 JP 2023021813 W JP2023021813 W JP 2023021813W WO 2024014209 A1 WO2024014209 A1 WO 2024014209A1
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WIPO (PCT)
Prior art keywords
electrode
semiconductor layer
section
electrode part
imaging device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/021813
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English (en)
French (fr)
Japanese (ja)
Inventor
善明 菊池
秀益 大内
学 冨田
利起 林
永 千葉
秀臣 熊野
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Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to EP23839384.7A priority Critical patent/EP4557371A4/en
Priority to CN202380044786.4A priority patent/CN119318225A/zh
Priority to KR1020257002526A priority patent/KR20250034961A/ko
Priority to JP2024533588A priority patent/JPWO2024014209A1/ja
Priority to US18/880,720 priority patent/US20260006922A1/en
Publication of WO2024014209A1 publication Critical patent/WO2024014209A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H10F39/182—Colour image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H10F39/80373—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor characterised by the gate of the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present disclosure relates to, for example, an imaging device.
  • Patent Document 1 an amplification transistor having a gate electrode including a vertical gate electrode portion buried in a depth direction from one surface of a semiconductor substrate made of a p-type layer, which is a well layer, is disclosed.
  • a formed solid-state imaging device is disclosed.
  • An imaging device includes a photoelectric conversion section that generates charges according to the amount of received light, and a photoelectric conversion section that performs a predetermined operation on the charges generated in the photoelectric conversion section, and that are arranged in parallel in a first direction.
  • a first active element having a gate electrode including a first electrode part, a second electrode part, and a third electrode part connecting the first electrode part and the second electrode part;
  • the first electrode part and the second electrode part of the gate electrode are embedded in the first surface side, and the first electrode part and the second electrode part are connected to each other.
  • a first semiconductor layer having a non-doped first semiconductor region therebetween.
  • the first electrode part and the second electrode part are embedded in the first semiconductor layer in which the first electrode part and the second electrode part constituting the gate electrode of the first active element are embedded.
  • a non-doped first semiconductor region is formed between the second electrode portion and the second electrode portion. Thereby, the entire first semiconductor layer between the first electrode part and the second electrode part is used as a channel region.
  • FIG. 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure.
  • 2 is a schematic plan view showing a schematic configuration of the imaging device shown in FIG. 1.
  • FIG. 3 is a schematic diagram showing a cross-sectional configuration taken along the line A-A' shown in FIG. 2.
  • FIG. 2 is an equivalent circuit diagram of the unit cell shown in FIG. 1.
  • FIG. FIG. 2 is a schematic diagram showing an example of a cross-sectional configuration of the imaging device shown in FIG. 1.
  • FIG. 6 is a schematic diagram showing an example of a planar layout of the first substrate shown in FIG. 5.
  • FIG. 6 is a schematic diagram showing an example of a planar layout of the second substrate shown in FIG. 5.
  • FIG. 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure.
  • 2 is a schematic plan view showing a schematic configuration of the imaging device shown in FIG. 1.
  • FIG. FIG. 3 is
  • FIG. 6B is a schematic cross-sectional view taken along line I-I' shown in FIG. 6B.
  • FIG. 6B is a schematic cross-sectional view taken along the line II-II' shown in FIG. 6B.
  • FIG. 6B is a schematic cross-sectional view taken along the line III-III' shown in FIG. 6B.
  • FIG. 6B is a schematic cross-sectional view taken along the line IV-IV' shown in FIG. 6B.
  • FIG. It is a schematic diagram explaining the channel formed in a notch part.
  • FIG. 3 is a developed view of a channel formed in a cutout.
  • FIG. 7A is a schematic cross-sectional view illustrating an example of the manufacturing process of the pixel transistor shown in FIG. 7A and the like.
  • FIG. 7A is a schematic cross-sectional view illustrating an example of the manufacturing process of the pixel transistor shown in FIG. 7A and the like.
  • FIG. 10A is a schematic cross-sectional view showing a step subsequent to FIG. 10A.
  • FIG. 10B is a schematic cross-sectional view showing a step following FIG. 10B.
  • FIG. 10C is a schematic cross-sectional view showing a step following FIG. 10C.
  • FIG. 10D is a schematic cross-sectional view showing a step following FIG. 10D.
  • FIG. 10 is a schematic cross-sectional view showing a step following FIG. 10E.
  • FIG. 10 is a schematic cross-sectional view showing a step following FIG. 10F.
  • FIG. 10 is a schematic cross-sectional view showing a step following FIG. 10G.
  • 10H is a schematic cross-sectional view showing a step following FIG. 10H.
  • FIG. FIG. 10A is a schematic cross-sectional view showing a step subsequent to FIG. 10A.
  • FIG. 10B is a schematic cross-sectional view showing a step following FIG. 10B.
  • FIG. 10C is
  • FIG. 10 is a schematic cross-sectional view showing a step subsequent to FIG. 10I.
  • FIG. 3 is a schematic cross-sectional diagram illustrating another configuration of a pixel transistor according to the present disclosure.
  • 12 is a schematic cross-sectional view illustrating a manufacturing process of the pixel transistor shown in FIG. 11.
  • FIG. 7A is a schematic cross-sectional view illustrating another example of the manufacturing process of the pixel transistor shown in FIG. 7A and the like.
  • FIG. 4 is a schematic diagram for explaining a path of an input signal to the imaging device shown in FIG. 3.
  • FIG. 4 is a schematic diagram for explaining a signal path of a pixel signal of the imaging device shown in FIG. 3.
  • FIG. 2 is a schematic plan view showing the configuration of a pixel transistor as Comparative Example 1.
  • FIG. 17 is a schematic cross-sectional view taken along the line V-V′ shown in FIG. 16.
  • FIG. 17 is a schematic cross-sectional view taken along line VI-VI' shown in FIG. 16.
  • FIG. 3 is a schematic diagram showing an example of a planar layout of fins.
  • FIG. 3 is a schematic cross-sectional view showing an example of the shape of a fin formed by etching.
  • FIG. 7 is a schematic cross-sectional view showing another example of the shape of a fin formed by etching.
  • 3 is a schematic plan view showing the configuration of a pixel transistor as Comparative Example 2.
  • FIG. 23 is a schematic cross-sectional view taken along line VIII-VIII' shown in FIG. 22.
  • FIG. 23 is a schematic cross-sectional view taken along line IX-IX' shown in FIG. 22.
  • FIG. FIG. 3 is a characteristic diagram showing mutual conductance (gm) of Comparative Example 2 and Example.
  • FIG. 3 is a characteristic diagram showing current-voltage characteristics of Comparative Example 2 and Example.
  • FIG. 3 is a schematic cross-sectional view of a pixel transistor according to Modification Example 1 of the present disclosure.
  • FIG. 3 is a characteristic diagram showing the relationship between noise current (Isub) and life depending on sidewall width.
  • FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process of a pixel transistor according to Modification Example 2 of the present disclosure.
  • FIG. 29A is a schematic cross-sectional view showing a step subsequent to FIG. 29A.
  • FIG. 29B is a schematic cross-sectional view showing a step subsequent to FIG. 29B.
  • FIG. 29C is a schematic cross-sectional view showing a step following FIG. 29C.
  • FIG. 29D is a schematic cross-sectional view showing a step subsequent to FIG. 29D.
  • FIG. 29E is a schematic cross-sectional view showing a step subsequent to FIG. 29E.
  • FIG. 29F is a schematic cross-sectional view showing a step following FIG. 29F.
  • FIG. 29 is a schematic cross-sectional view showing a step following FIG. 29G.
  • FIG. 29H is a schematic cross-sectional view showing a step following FIG. 29H.
  • FIG. 29I is a schematic cross-sectional view showing a step subsequent to FIG. 29I.
  • FIG. 29 is a schematic cross-sectional view showing a step following FIG. 29J.
  • FIG. 7 is a schematic plan view showing the configuration of a pixel transistor according to Modification Example 2 of the present disclosure.
  • FIG. 2 is a block diagram showing a configuration example of an electronic device including the imaging device shown in FIG. 1.
  • FIG. FIG. 2 is a schematic diagram showing an example of the overall configuration of a photodetection system using the imaging device shown in FIG. 1 and the like.
  • 32A is a diagram showing an example of a circuit configuration of the photodetection system shown in FIG. 32A.
  • FIG. FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.
  • FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU.
  • FIG. 1 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.
  • the imaging device 1 in FIG. 1 includes, for example, an input section 510A, a row drive section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.
  • pixels 541 are repeatedly arranged in an array. More specifically, a unit cell 539 including a plurality of pixels serves as a repeating unit, and is repeatedly arranged in an array in a row direction and a column direction. Note that in this specification, for convenience, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction may be referred to as the V direction. In the example of FIG. 1, one unit cell 539 includes, for example, four pixels (pixels 541A, 541B, 541C, and 541D).
  • the pixel array section 540 is provided with pixels 541A, 541B, 541C, and 541D, as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543.
  • the row drive signal line 542 drives the pixels 541 included in each of the plurality of unit cells 539 arranged in the row direction in the pixel array section 540.
  • each pixel arranged in the row direction is driven.
  • the unit cell 539 is provided with a plurality of transistors.
  • a plurality of row drive signal lines 542 are connected to one unit cell 539 in order to drive these plurality of transistors, respectively.
  • a unit cell 539 is connected to the vertical signal line (column readout line) 543 . Pixel signals are read out from each of pixels 541A, 541B, 541C, and 541D included in unit cell 539 via vertical signal line (column readout line) 543.
  • the row driving section 520 is, for example, a row address control section that determines the position of a row for pixel driving, in other words, a row decoder section and a row driving section that generates signals for driving the pixels 541A, 541B, 541C, and 541D. It includes a circuit section.
  • the column signal processing section 550 includes, for example, a load circuit section that is connected to the vertical signal line 543 and forms a source follower circuit with the pixels 541A, 541B, 541C, and 541D (unit cells 539).
  • the column signal processing section 550 may include an amplifier circuit section that amplifies the signal read out from the unit cell 539 via the vertical signal line 543.
  • the column signal processing section 550 may include a noise processing section. In the noise processing section, for example, the system noise level is removed from the signal read out from the unit cell 539 as a result of photoelectric conversion.
  • the column signal processing section 550 includes, for example, an analog-to-digital converter (ADC).
  • ADC analog-to-digital converter
  • the analog-to-digital converter converts the signal read from the unit cell 539 or the noise-processed analog signal into a digital signal.
  • the ADC includes, for example, a comparator section and a counter section. In the comparator section, the analog signal to be converted and the reference signal to be compared are compared. The counter section measures the time until the comparison result at the comparator section is reversed.
  • the column signal processing section 550 may include a horizontal scanning circuit section that controls scanning of readout columns.
  • the timing control unit 530 supplies timing control signals to the row driving unit 520 and column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.
  • the image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of an imaging operation in the imaging device 1.
  • the image signal processing section 560 includes, for example, an image signal processing circuit section and a data holding section.
  • Image signal processing section 560 may include a processor section.
  • An example of the signal processing executed in the image signal processing unit 560 is to add many gradations when the AD-converted imaging data is data of a dark subject, and to add many gradations when the AD-converted imaging data is data of a bright subject.
  • This is a tone curve correction process that reduces the gradation.
  • it is preferable to store characteristic data of the tone curve in advance in the data holding unit of the image signal processing unit 560 to determine which tone curve is used to correct the gradation of the image data.
  • the input unit 510A is for inputting, for example, the reference clock signal, timing control signal, characteristic data, etc. to the imaging device 1 from outside the device.
  • the timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal.
  • the characteristic data is, for example, to be stored in the data holding section of the image signal processing section 560.
  • the input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).
  • the input terminal 511 is an external terminal for inputting data.
  • the input circuit section 512 is for taking in the signal input to the input terminal 511 into the imaging device 1 .
  • the input amplitude changing unit 513 changes the amplitude of the signal taken in by the input circuit unit 512 to an amplitude that can be easily used inside the imaging device 1.
  • the input data conversion circuit section 514 is configured by, for example, a serial-parallel conversion circuit. This serial-to-parallel conversion circuit converts a serial signal received as input data into a parallel signal. Note that the input amplitude changing section 513 and the input data converting circuit section 514 may be omitted in the input section 510A.
  • the power supply unit supplies power set to various voltages required inside the imaging device 1 based on the power supplied to the imaging device 1 from the outside.
  • the input section 510A may be provided with a memory interface circuit that receives data from the external memory device.
  • External memory devices include, for example, flash memory, SRAM, and DRAM.
  • the output unit 510B outputs the image data to the outside of the device.
  • This image data is, for example, image data photographed by the imaging device 1, image data subjected to signal processing by the image signal processing section 560, and the like.
  • the output section 510B includes, for example, an output data conversion circuit section 515, an output amplitude changing section 516, an output circuit section 517, and an output terminal 518.
  • the output data conversion circuit section 515 is composed of, for example, a parallel-to-serial conversion circuit, and in the output data conversion circuit section 515, a parallel signal used inside the imaging device 1 is converted into a serial signal.
  • the output amplitude changing unit 516 changes the amplitude of the signal used inside the imaging device 1.
  • the signal with the changed amplitude can be easily used by an external device connected to the outside of the imaging device 1.
  • the output circuit section 517 is a circuit that outputs data from the inside of the imaging device 1 to the outside of the device, and the output circuit section 517 drives wiring outside the imaging device 1 connected to the output terminal 518. At the output terminal 518, data is output from the imaging device 1 to the outside of the device.
  • the output data conversion circuit section 515 and the output amplitude changing section 516 may be omitted.
  • the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device.
  • External memory devices include, for example, flash memory, SRAM, and DRAM.
  • FIG. 2 and 3 show an example of a schematic configuration of the imaging device 1.
  • the imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300).
  • FIG. 2 schematically shows the planar configuration of the first substrate 100, second substrate 200, and third substrate 300
  • FIG. 3 shows the first substrate 100, second substrate 200, and third substrate stacked on each other.
  • the cross-sectional configuration of the third substrate 300 is schematically represented.
  • FIG. 3 corresponds to a cross-sectional configuration taken along line AA' shown in FIG.
  • the imaging device 1 is a three-dimensional imaging device configured by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300).
  • the first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T.
  • the second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T.
  • the third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T.
  • the sum of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around the wiring is These are called wiring layers (100T, 200T, 300T) provided on the substrate 200 and the third substrate 300).
  • the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and along the stacking direction, the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor
  • the layers 300S are arranged in this order. Specific configurations of the first substrate 100, second substrate 200, and third substrate 300 will be described later.
  • the arrow shown in FIG. 3 represents the direction of incidence of the light L into the imaging device 1.
  • the light incidence side of the imaging device 1 is referred to as "lower”, “lower side”, and “lower”, and the side opposite to the light incidence side is referred to as "upper”, “upper side”, and "upper”. There are cases.
  • the wiring layer side may be referred to as the front surface
  • the semiconductor layer side may be referred to as the back surface. Note that the description in the specification is not limited to the above-mentioned names.
  • the imaging device 1 is, for example, a back-illuminated imaging device in which light enters from the back side of a first substrate 100 having a photodiode.
  • Both the pixel array section 540 and the unit cell 539 included in the pixel array section 540 are constructed using both the first substrate 100 and the second substrate 200.
  • the first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the unit cell 539. Each of these pixels 541 has a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later).
  • the second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) included in the unit cell 539.
  • the pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via transfer transistors, or resets the photodiodes.
  • the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction.
  • the second substrate 200 further includes a power line 544 extending in the row direction.
  • the third substrate 300 includes, for example, an input section 510A, a row drive section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B.
  • the row driving section 520 is provided, for example, in a region that partially overlaps the pixel array section 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). .
  • the row driving section 520 is provided in a region that overlaps near the end of the pixel array section 540 in the H direction in the stacking direction.
  • the column signal processing section 550 is provided, for example, in a region that partially overlaps the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region that overlaps near the end of the pixel array section 540 in the V direction in the stacking direction.
  • the input section 510A and the output section 510B may be arranged in a portion other than the third substrate 300, for example, they may be arranged in the second substrate 200.
  • the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.
  • the pixel circuit provided on the second substrate 200 is also sometimes called a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this specification, the term pixel circuit is used.
  • the first substrate 100 and the second substrate 200 are electrically connected, for example, by a through electrode (for example, through electrodes 120E and 121E in FIG. 5, which will be described later).
  • the second substrate 200 and the third substrate 300 are electrically connected via contact portions 201, 202, 301, and 302, for example.
  • Contact portions 201 and 202 are provided on the second substrate 200, and contact portions 301 and 302 are provided on the third substrate 300.
  • the contact portion 201 of the second substrate 200 is in contact with the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 is in contact with the contact portion 302 of the third substrate 300.
  • the second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided and a contact region 202R in which a plurality of contact portions 202 are provided.
  • the third substrate 300 has a contact region 301R in which a plurality of contact parts 301 are provided and a contact region 302R in which a plurality of contact parts 302 are provided.
  • the contact regions 201R and 301R are provided between the pixel array section 540 and the row drive section 520 in the stacking direction. In other words, the contact regions 201R and 301R are provided, for example, in a region where the row driving section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region near this region.
  • the contact regions 201R and 301R are arranged, for example, at the ends of these regions in the H direction.
  • a contact region 301R is provided at a position overlapping a part of the row driving section 520, specifically, an end of the row driving section 520 in the H direction.
  • the contact sections 201 and 301 connect, for example, the row drive section 520 provided on the third substrate 300 and the row drive signal line 542 provided on the second substrate 200.
  • the contact portions 201 and 301 may connect, for example, the input portion 510A provided on the third substrate 300, the power supply line 544, and a reference potential line (reference potential line VSS to be described later).
  • the contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction.
  • the contact regions 202R and 302R are provided, for example, in a region where the column signal processing section 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region near this region. ing.
  • the contact regions 202R and 302R are arranged, for example, at the ends of these regions in the V direction.
  • a contact region 301R is provided at a position overlapping a part of the column signal processing section 550, specifically, an end of the column signal processing section 550 in the V direction.
  • the contact portions 202 and 302 transmit a pixel signal (a signal corresponding to the amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of unit cells 539 included in the pixel array portion 540 to a third This is for connecting to the column signal processing section 550 provided on the substrate 300. Pixel signals are sent from the second substrate 200 to the third substrate 300.
  • FIG. 3 is an example of a cross-sectional view of the imaging device 1.
  • the first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T.
  • the imaging device 1 includes an electrical connection section that electrically connects the second substrate 200 and the third substrate 300.
  • the contact portions 201, 202, 301, and 302 are formed with electrodes made of a conductive material.
  • the conductive material is made of, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au).
  • the contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by, for example, directly bonding wirings formed as electrodes, and connect the second substrate 200 and the third substrate 300. Enables input and/or output of signals to and from.
  • the electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location.
  • the electrical connection portion may be provided in a region that does not overlap with the pixel array portion 540 in the stacking direction. Specifically, it may be provided in a region that overlaps in the stacking direction with a peripheral portion located outside the pixel array section 540.
  • connection holes H1 and H2 are provided with connection holes H1 and H2, for example.
  • the connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200.
  • the connection hole portions H1 and H2 are provided outside the pixel array portion 540 (or the portion overlapping the pixel array portion 540).
  • the connection hole portion H1 is placed outside the pixel array portion 540 in the H direction
  • the connection hole portion H2 is placed outside the pixel array portion 540 in the V direction.
  • the connection hole portion H1 reaches an input portion 510A provided on the third substrate 300
  • the connection hole portion H2 reaches an output portion 510B provided on the third substrate 300.
  • connection holes H1 and H2 may be hollow, or may contain a conductive material at least in part.
  • connection holes H1 and H2 may be hollow, or may contain a conductive material at least in part.
  • bonding wires are connected to electrodes formed as the input section 510A and/or the output section 510B.
  • electrodes formed as the input section 510A and/or the output section 510B are connected to conductive materials provided in the connection holes H1 and H2.
  • the conductive material provided in the connection holes H1, H2 may be embedded in part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2. good.
  • the third substrate 300 has a structure in which the input section 510A and the output section 510B are provided, but the present invention is not limited to this.
  • the input section 510A and/or the output section 510B can be provided on the second substrate 200 by sending signals from the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T.
  • the input section 510A and/or the output section 510B can be provided on the first substrate 100 by sending signals from the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.
  • the pixels 541A, 541B, 541C, and 541D have common components.
  • identification number 1 is added to the end of the code of the component of pixel 541A
  • identification number 2 is added to the end of the code of the component of pixel 541B
  • An identification number 3 is given to the end of the code of the component of the pixel 541C
  • an identification number 4 is given to the end of the code of the component of the pixel 541D.
  • the identification numbers at the end of the symbols of the constituent elements of the pixels 541A, 541B, 541C, and 541D are omitted.
  • FIG. 4 is an equivalent circuit diagram showing an example of the configuration of the unit cell 539.
  • the unit cell 539 includes a plurality of pixels 541 (four pixels 541A, 541B, 541C, and 541D in FIG. 4), one pixel circuit 210 connected to the plurality of pixels 541, and a pixel circuit 210 connected to the pixel circuit 210. and a vertical signal line 543.
  • the pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.
  • the unit cell 539 operates one pixel circuit 210 in a time-division manner to control each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) provided in two adjacent pixels.
  • the signals are sequentially output to the vertical signal line 543.
  • One pixel circuit 210 is connected to a plurality of pixels 541, and the pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time-sharing manner. "The circuit 210 will be shared.”
  • the pixels 541A, 541B, 541C, and 541D have common components.
  • the pixels 541A, 541B, 541C, and 541D each include, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR.
  • a photodiode PD a cathode is electrically connected to the source of the transfer transistor TR, and an anode is electrically connected to a reference potential line (eg, ground).
  • the photodiode PD photoelectrically converts incident light and generates a charge depending on the amount of received light.
  • the transfer transistor TR is, for example, an n-type CMOS (Complementary Metal Oxide Semiconductor) transistor.
  • Transfer transistor TR In the transfer transistor TR, a drain is electrically connected to the floating diffusion FD, and a gate is electrically connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one unit cell 539.
  • Transfer transistor TR transfers the charge generated by photodiode PD to floating diffusion FD.
  • the floating diffusion FD is an n-type diffusion layer region formed in a p-type semiconductor layer.
  • the floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is a charge-voltage conversion means that generates a voltage according to the amount of charge.
  • the four floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) included in the unit cell 539 of 1 are electrically connected to each other and connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. electrically connected.
  • the drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line.
  • This drive signal line is part of a plurality of row drive signal lines 542 connected to one unit cell 539.
  • the drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line.
  • This drive signal line is part of a plurality of row drive signal lines 542 connected to one unit cell 539.
  • the gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.
  • the source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line.
  • This drive signal line is part of a plurality of row drive signal lines 542 connected to one unit cell 539.
  • the transfer transistor TR When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD.
  • the gate of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 5 described later) to a depth reaching the PD. There is.
  • the reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST turns on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD.
  • the selection transistor SEL controls the output timing of pixel signals from the pixel circuit 210.
  • the amplification transistor AMP generates, as a pixel signal, a voltage signal corresponding to the level of charge held in the floating diffusion FD.
  • Amplification transistor AMP is connected to vertical signal line 543 via selection transistor SEL.
  • This amplification transistor AMP constitutes a source follower in the column signal processing section 550 together with a load circuit section connected to the vertical signal line 543.
  • the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing section 550 via the vertical signal line 543 when the selection transistor SEL is turned on.
  • the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.
  • the FD conversion gain switching transistor FDG is used to change the charge-voltage conversion gain in the floating diffusion FD.
  • the pixel signal is small.
  • the capacitance of the floating diffusion FD (FD capacitance C)
  • V when converted into voltage by the amplification transistor AMP becomes small.
  • the pixel signal becomes large, so unless the FD capacitance C is large, the floating diffusion FD cannot receive the charge of the photodiode PD.
  • the FD capacitance C needs to be large so that V when converted into voltage by the amplification transistor AMP does not become too large (in other words, becomes small).
  • the FD conversion gain switching transistor FDG when the FD conversion gain switching transistor FDG is turned on, the gate capacitance corresponding to the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes smaller. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched.
  • the FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.
  • the pixel circuit 210 is configured with three transistors: an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.
  • the pixel circuit 210 includes, for example, at least one pixel transistor such as an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.
  • the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP.
  • the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL.
  • the source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542.
  • the source of the amplification transistor AMP (output end of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.
  • the number of pixels 541 that share one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.
  • FIG. 5 shows an example of a cross-sectional configuration of the first substrate 100, second substrate 200, and third substrate 300 of the imaging device 1 in a direction perpendicular to the main surface.
  • FIG. 5 is a schematic representation to make it easier to understand the positional relationship of the components, and may differ from the actual cross section.
  • FIG. 6A schematically represents an example of a planar layout of the first substrate 100.
  • FIG. 6B schematically represents an example of the planar layout of the second substrate 200.
  • a first substrate 100, a second substrate 200, and a third substrate 300 are stacked in this order.
  • the imaging device 1 further includes a light receiving lens 401 on the back surface side (light incident surface side) of the first substrate 100.
  • a color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100.
  • the light receiving lens 401 is provided, for example, in each of the pixels 541A, 541B, 541C, and 541D.
  • the imaging device 1 is, for example, a back-illuminated imaging device.
  • the imaging device 1 includes a pixel array section 540 arranged at the center and a peripheral section (not shown) arranged outside the pixel array section 540.
  • the first substrate 100 has a semiconductor layer 100S and a wiring layer 100T in order from the light receiving lens 401 side.
  • the semiconductor layer 100S is made of, for example, a silicon substrate.
  • a photodiode PD is embedded in the semiconductor layer 100S.
  • the semiconductor layer 100S has, for example, a p-well layer 112 in a part of the surface (the surface on the wiring layer 100T side) and in the vicinity thereof, and the other region (more than the p-well layer 112) It has an n-type semiconductor region 111 in a deep region).
  • the n-type semiconductor region 111 and the p-well layer 112 constitute a pn junction type photodiode PD.
  • P-well layer 112 is a p-type semiconductor region.
  • the semiconductor layer 100S corresponds to a specific example of the "second semiconductor layer" in the embodiment of the present disclosure.
  • a floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S.
  • Floating diffusion FD is constituted by an n-type semiconductor region provided within p-well layer 112.
  • the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the unit cell 539, for example, as shown in FIG. 6A. There is.
  • the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this unit cell 539 are connected to electrical connection means (described later) within the first substrate 100 (more specifically, within the wiring layer 100T).
  • the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrodes 120E, which will be described later). There is.
  • the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means. There is.
  • the VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD.
  • the floating diffusion FD is arranged at one corner, and the VSS contact region 118 is arranged at a diagonal corner of the floating diffusion FD.
  • the VSS contact region 118 is composed of, for example, a p-type semiconductor region.
  • the VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Thereby, the reference potential is supplied to the semiconductor layer 100S.
  • the first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR.
  • the photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D.
  • the transfer transistor TR is provided on the surface side of the semiconductor layer 100S (the side opposite to the light incident surface side, the second substrate 200 side).
  • Transfer transistor TR has a transfer gate TG.
  • the transfer gate TG includes, for example, a horizontal portion TGb facing the surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S.
  • the vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 111.
  • the transfer transistor TR may be configured by a planar transistor.
  • a transfer gate TG is provided on the surface of the semiconductor layer 100S.
  • a gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG.
  • the semiconductor layer 100S is provided with a pixel separation section 117 that separates the pixels 541A, 541B, 541C, and 541D from each other.
  • the pixel separation section 117 is formed to extend in the normal direction of the semiconductor layer 100S (direction perpendicular to the surface of the semiconductor layer 100S (Z-axis direction in FIG. 5)).
  • the pixel separation section 117 is provided so as to partition the pixels 541A, 541B, 541C, and 541D from each other, and has, for example, a grid-like planar shape.
  • the pixel separation unit 117 electrically and optically isolates the pixels 541A, 541B, 541C, and 541D from each other, for example.
  • the pixel separation section 117 includes, for example, a light shielding film 117A and an insulating film 117B.
  • tungsten (W) or the like is used for the light shielding film 117A.
  • the insulating film 117B is provided between the light shielding film 117A and the p-well layer 112 or the n-type semiconductor region 111.
  • the insulating film 117B is made of silicon oxide (SiO), for example.
  • the pixel isolation section 117 has, for example, an FTI (Full Trench Isolation) structure, and penetrates through the semiconductor layer 100S. Although not shown, the pixel isolation section 117 is not limited to an FTI structure penetrating the semiconductor layer 100S.
  • a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S may be used.
  • the pixel separation section 117 extends in the normal direction of the semiconductor layer 100S and is formed in a part of the semiconductor layer 100S.
  • a first pinning region 113 and a second pinning region 116 are provided in the semiconductor layer 100S.
  • the first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is arranged between the n-type semiconductor region 111 and the fixed charge film 114.
  • the second pinning region 116 is provided on a side surface of the pixel isolation section 117, specifically, between the pixel isolation section 117 and the p-well layer 112 or the n-type semiconductor region 111.
  • the first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.
  • a fixed charge film 114 having negative fixed charges is provided between the semiconductor layer 100S and the insulating film 115.
  • the electric field induced by the fixed charge film 114 forms the first pinning region 113 of the hole accumulation layer at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S. This suppresses the generation of dark current caused by the interface level on the light-receiving surface side of the semiconductor layer 100S.
  • the fixed charge film 114 is formed of, for example, an insulating film having negative fixed charges. Examples of the material of the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.
  • a light shielding film 117A is provided between the fixed charge film 114 and the insulating film 115.
  • This light shielding film 117A may be provided continuously with the light shielding film 117A that constitutes the pixel separation section 117.
  • the light shielding film 117A between the fixed charge film 114 and the insulating film 115 is selectively provided, for example, at a position facing the pixel separation section 117 in the semiconductor layer 100S.
  • An insulating film 115 is provided to cover this light shielding film 117A.
  • the insulating film 115 is made of silicon oxide, for example.
  • the wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes pad portions 120, 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in this order from the semiconductor layer 100S side. There is.
  • the horizontal portion TGb of the transfer gate TG is provided, for example, in this wiring layer 100T. Note that the configuration of the wiring layer 100T is not limited to the above-described configuration, and may be any configuration as long as it includes wiring and an insulating film.
  • the pad portions 120 and 121 are provided in selective regions on the surface of the semiconductor layer 100S, for example, via an insulating film (not shown).
  • the pad section 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D to each other.
  • the pad portion 120 is arranged, for example, at the center of the unit cell 539 in a plan view for each unit cell 539.
  • This pad section 120 is provided so as to straddle the pixel separation section 117, and is arranged to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4. Specifically, as shown in FIG.
  • the pad section 120 connects at least a portion of each of a plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210, and Perpendicular to the surface of the semiconductor layer 100S with respect to at least a part of the pixel separation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210. are formed in areas that overlap in the same direction.
  • the pad portion 121 is for connecting the plurality of VSS contact regions 118 to each other.
  • the VSS contact regions 118 provided in the pixels 541C and 541D of one unit cell 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other unit cell 539 are connected to the pad portion 121. electrically connected.
  • the pad section 121 is provided, for example, so as to straddle the pixel separation section 117, and is arranged to overlap at least a portion of each of these four VSS contact regions 118.
  • the pad section 121 connects at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation section 117 formed between the plurality of VSS contact regions 118 with a semiconductor layer. It is formed in a region that overlaps the surface of the layer 100S in a direction perpendicular to it.
  • the pad section 120 By providing the pad section 120, it is possible to reduce the number of wiring lines for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) in the entire chip. Similarly, by providing the pad portion 121, the number of wirings for supplying potential to each VSS contact region 118 can be reduced in the entire chip. This makes it possible to reduce the area of the entire chip, suppress electrical interference between wiring lines in miniaturized pixels, and/or reduce costs by reducing the number of parts.
  • the pad portions 120 and 121 are made of, for example, polysilicon (PolySi), more specifically, doped polysilicon to which impurities are added.
  • the pad portions 120 and 121 are preferably made of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100.
  • the pad portions 120 and 121 may be made of metal materials such as tantalum nitride (TaN), aluminum (Al), and copper (Cu).
  • the passivation film 122 is provided over the entire surface of the semiconductor layer 100S, for example, so as to cover the pad portions 120 and 121.
  • the passivation film 122 is made of, for example, a silicon nitride (SiN) film.
  • Interlayer insulating film 123 covers pad parts 120 and 121 with passivation film 122 in between.
  • This interlayer insulating film 123 is provided, for example, over the entire surface of the semiconductor layer 100S.
  • the interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film.
  • the bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200.
  • This bonding film 124 is provided over the entire main surface of the first substrate 100.
  • the bonding film 124 is made of, for example, a silicon nitride film.
  • the light receiving lens 401 faces the semiconductor layer 100S with the fixed charge film 114 and the insulating film 115 in between.
  • the light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.
  • the second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side.
  • the semiconductor layer 200S is made of a silicon substrate.
  • a well region 211 is provided in a selective region, although the details will be described later.
  • the second substrate 200 is provided with pixel circuits 210 arranged for each unit cell 539, for example, as shown in FIG. 6B.
  • the well region 211 is provided, for example, around the active regions 200X of the four transistors that constitute the pixel circuit 210.
  • the well region 211 corresponds to a specific example of the "second semiconductor region" in the embodiment of the present disclosure, and is, for example, a p-type semiconductor region.
  • the pixel circuit 210 is provided, for example, on the front surface side (wiring layer 200T side) of the semiconductor layer 200S.
  • the second substrate 200 is bonded to the first substrate 100 such that the back surface side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. ing. That is, the second substrate 200 is bonded face-to-back to the first substrate 100.
  • the semiconductor layer 200S corresponds to a specific example of the "first semiconductor layer" in the embodiment of the present disclosure.
  • the second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S, and an element isolation region 213 provided in a part of the semiconductor layer 200S in the thickness direction.
  • the insulating region 212 is a region where the through electrodes 120E, 121E and the through electrode TGV for electrically connecting the first substrate 100 and the second substrate 200 are provided insulated from the semiconductor layer 200S.
  • the semiconductor layer 200S is divided by this insulating region 212, and the through electrodes 120E, 121E and the through electrode TGV are arranged in this insulating region 212.
  • the insulating region 212 has approximately the same thickness as the semiconductor layer 200S. Insulating region 212 is made of silicon oxide, for example.
  • the through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction.
  • the upper ends of the through electrodes 120E and 121E are connected to the wiring (first wiring layer W1, second wiring layer W2, and third wiring layer W3) of the wiring layer 200T.
  • the through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and have their lower ends connected to the pad portions 120 and 121.
  • the through electrode 120E is for electrically connecting the pad portion 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrode 120E.
  • the through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the VSS contact region 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 by the through electrode 121E.
  • the through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction.
  • the upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T.
  • This through electrode TGV is provided to penetrate through the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and its lower end is connected to the transfer gate TG.
  • Such a through electrode TGV connects the transfer gates TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, and 541D and the wiring of the wiring layer 200T (a part of the row drive signal line 542).
  • the through electrode TGV electrically connects the transfer gate TG of the first substrate 100 to the wiring TRG of the second substrate 200, and connects the transfer transistor TR (transfer transistors TR1, TR2 , TR3, TR4), and drive signals are sent to each of them.
  • the element isolation region 213 is provided on the surface side of the semiconductor layer 200S.
  • the element isolation region 213 has an STI (Shallow Trench Isolation) structure.
  • the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in this trench.
  • This insulating film is made of silicon oxide, for example.
  • the element isolation region 213 is for element isolation between a plurality of transistors forming the pixel circuit 210 according to the layout of the pixel circuit 210.
  • the semiconductor layer 200S extends below the element isolation region 213 (deep in the semiconductor layer 200S). In this embodiment, a well region 211 is selectively formed below this element isolation region 213.
  • the pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.
  • the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG are arranged in parallel in the X-axis direction.
  • the amplification transistor AMP and the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG, which are arranged in parallel in the X-axis direction, are respectively provided in the continuous semiconductor layer 200S, and the amplification transistor AMP and the selection transistor SEL are provided in the continuous semiconductor layer 200S.
  • the reset transistor RST and the FD conversion gain switching transistor FDG are isolated by an element isolation region 213, respectively.
  • the semiconductor layer 200S provided with the amplification transistor AMP and the selection transistor SEL and the semiconductor layer 200S provided with the reset transistor RST and the FD conversion gain switching transistor FDG are separated by an insulating region 212.
  • the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG correspond to a specific example of the "first active element" in the embodiment of the present disclosure.
  • a transistor arranged in parallel with that transistor and formed in the same semiconductor layer 200S is a “second active element” in the embodiment of the present disclosure. This corresponds to "an active element”.
  • the selection transistors SEL formed in the same semiconductor layer 200S and arranged in parallel in the X-axis direction are set as "second active elements”. Equivalent to.
  • amplification transistor AMP the configurations of the amplification transistor AMP, selection transistor SEL, reset transistor RST, FD transfer transistor FDG, and the semiconductor layer 200S provided with these will be described in detail. Note that when there is no need to distinguish the components of the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD transfer transistor FDG from each other, they are referred to as pixel transistors.
  • the amplification transistor AMP, selection transistor SEL, reset transistor RST, and FD transfer transistor FDG have a three-dimensional structure, such as a fin type, for example.
  • a transistor with a three-dimensional structure is one in which a plurality of flat gate electrodes are provided facing the channel, or one in which a curved surface of the gate electrode is provided around the channel.
  • the effective gate width can be made larger than that of the planar transistor. Therefore, a large amount of current flows through the three-dimensionally structured transistor, resulting in a high mutual conductance (gm). This makes it possible to improve the operating speed of a three-dimensional transistor compared to a planar transistor.
  • RN Random Noise
  • RTS Random Telegraph Signal
  • FIG. 7A schematically shows a cross-sectional configuration corresponding to the line II' shown in FIG. 6B.
  • FIG. 7B schematically shows a cross-sectional configuration corresponding to the line II-II' shown in FIG. 6B.
  • FIG. 7C schematically shows a cross-sectional configuration corresponding to the line III-III' shown in FIG. 6B.
  • FIG. 7D schematically shows a cross-sectional configuration corresponding to the line IV-IV' shown in FIG. 6B.
  • the pixel transistors including the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD transfer transistor FDG have a fin 200A extending in one direction, and a gate electrode 214G surrounding the top surface and two side walls of the fin 200A. and a source region 214S and a drain region 214D formed at both ends of the fin 200A in the extending direction, and an LDD (Light Detailed Drive) provided between the gate electrode 214G and the source region 214S and between the gate electrode 214G and the drain region 214D, respectively.
  • Doped Drain region 214L the pixel transistor includes a side wall 215 surrounding a gate electrode 214G formed on the semiconductor layer 200S, and a gate insulating film 216 provided between the gate electrode 214G and the semiconductor layer 200S.
  • the fin 200A is formed by processing the semiconductor layer 200S from the surface 200S1 side.
  • the fin 200A extends, for example, in the Y-axis direction and has a side wall substantially perpendicular to the surface 200S1 of the semiconductor layer 200S.
  • the fin 200A stands upright on the surface 200S1 of the semiconductor layer 200S with a substantially constant width in a substantially perpendicular direction.
  • the fin 200A is formed of a non-doped semiconductor layer 200S.
  • non-doped refers to a state in which ions for element isolation are not passed through. This non-doped region corresponds to a specific example of the "first semiconductor region" in the embodiment of the present disclosure.
  • FIGS. 7A and 7B show an example in which the sidewalls of the fins 200A are formed perpendicularly to the surface 200S1 of the semiconductor layer 200S, the sidewalls of the base portions are formed so that the base portions of the fins 200A are widened. It may form a curved surface. This alleviates stress concentration on the base portion of the fin 200A, prevents it from breaking during the manufacturing process, and improves yield.
  • the pixel transistor has one or more fins 200A.
  • the amplification transistor AMP has two fins 200A arranged in parallel in the X-axis direction.
  • the selection transistor SEL, the reset transistor RST, and the FD transfer transistor FDG each have one fin 200A.
  • the gate electrode 214G includes vertical portions 214Ga and 214Gb provided in the semiconductor layer 200S, and a horizontal portion 214Gc facing the surface 200S1 of the semiconductor layer 200S.
  • the vertical portions 214Ga and 214Gb extend in the thickness direction of the semiconductor layer 200S.
  • One end of the vertical portions 214Ga, 214Gb is in contact with the horizontal portion 214Gc, and the other end is provided within the semiconductor layer 200S.
  • the gate electrode 214G includes vertical portions 214Ga and 214Gb embedded in the semiconductor layer 200S along the sidewall of the fin 200A, and a vertical portion 214Ga and a vertical portion arranged in parallel in the X-axis direction between the fins 200A.
  • the vertical portions 214Ga and 214Gb correspond to a specific example of a “first electrode portion” and a “second electrode portion” in the embodiment of the present disclosure
  • the horizontal portion 214Gc corresponds to a specific example of the “first electrode portion” and the “second electrode portion” in the embodiment of the present disclosure. This corresponds to a specific example of a "third electrode section.”
  • a transistor having two fins 200A such as the amplification transistor AMP, further includes a vertical portion 214Gd between the vertical portion 214Ga and the vertical portion 214Gb.
  • the vertical portion 214Gd like the vertical portions 214Ga and 214Gb, has one end in contact with the horizontal portion 214Gc and the other end provided within the semiconductor layer 200S.
  • This vertical portion 214Gd corresponds to a specific example of the "fourth electrode section" in the embodiment of the present disclosure.
  • a cutout portion X is formed in the active region 200X of the semiconductor layer 200S that constitutes each pixel transistor.
  • the notch X is formed in the fin 200A portion of the outer edge of the active region 200X having a substantially rectangular shape, in which the vertical portions 214Ga and 214Gb of the gate 214 are embedded.
  • FIG. 8 schematically shows a channel formed in the cutout X of the semiconductor layer 200S.
  • FIG. 9 is a developed view of a channel formed in the cutout X of the semiconductor layer 200S in a pixel transistor (eg, selection transistor SEL) having one fin 200A.
  • a pixel transistor eg, selection transistor SEL
  • the horizontal portion 214Gc of the gate electrode 214G covers the entire fin 200A extending in the Y-axis direction, and the source region 214S formed at both ends of the fin 200A, for example, as shown in FIG. 6B. and protrudes so as to cover part of the drain region 214D.
  • a channel is formed in the cutout X.
  • a surface channel 214Ca is formed near the surface 200S1 of the semiconductor layer 200S facing the horizontal portion 214Gc of the gate electrode 214G, and a surface channel 214Ca is formed near the surface 200S1 of the gate electrode 214G opposite to the horizontal portion 214Gc.
  • a side wall channel 214Cb is formed on the side wall of the fin 200A facing each other, a bottom channel 214Cc is formed on the semiconductor layer 200S facing the bottom surface of each of the vertical portions 214Ga and 214Gb, and a pair of side surfaces facing each other in the Y-axis direction are formed on each of the vertical portions 214Ga and 214Gb.
  • Transport channels 214Cd are formed in the semiconductor layer 200S facing the semiconductor layer 200S (eg, the semiconductor layer 200S facing the shaded area in FIG. 7B), respectively. Note that the width of the sidewall channel 214Cb in the Y-axis direction becomes narrower from the front surface 200S1 to the back surface 200S2 of the semiconductor layer 200S, as shown in FIG. This allows current to flow through the bottom channel 214Cc and transport channel 214Cd, along with the surface channel 214Ca and sidewall channel 214Cb.
  • the wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (first wiring layer W1, second wiring layer W2, and third wiring layer W3).
  • the passivation film 221 is in contact with the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S.
  • This passivation film 221 covers the gate electrodes of each of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG.
  • Interlayer insulating film 222 is provided between passivation film 221 and third substrate 300.
  • a plurality of wirings (first wiring layer W1, second wiring layer W2, and third wiring layer W3) are separated by this interlayer insulating film 222.
  • the interlayer insulating film 222 is made of silicon oxide, for example.
  • a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and contact parts 201 and 202 are provided in this order from the semiconductor layer 200S side, and these are connected to each other by an interlayer insulating film 222.
  • the interlayer insulating film 222 is provided with a plurality of connection parts that connect the first wiring layer W1, the second wiring layer W2, or the third wiring layer W3 and the layers below these layers.
  • the connection portion is a portion in which a conductive material is buried in a connection hole provided in the interlayer insulating film 222.
  • the through electrode 120E is connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG through the first wiring layer W1.
  • the first wiring layer W1 connects, for example, the through electrode 121E and a connection portion connected to, for example, a VSS contact region provided in the semiconductor layer 200S. Thereby, the VSS contact region of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S are electrically connected.
  • the contact portions 201 and 202 may be provided at a position overlapping the pixel array portion 540 in a plan view, or may be provided at a peripheral portion outside the pixel array portion 540.
  • the contact parts 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side).
  • the contact parts 201 and 202 are made of metal such as Cu (copper) and Al (aluminum), for example.
  • the contact parts 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side).
  • the contact parts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.
  • the third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side.
  • the surface of the semiconductor layer 300S is provided on the second substrate 200 side.
  • the semiconductor layer 300S is made of a silicon substrate.
  • a circuit is provided on the surface side of this semiconductor layer 300S.
  • the surface side portion of the semiconductor layer 300S includes, for example, an input section 510A, a row drive section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. At least some of them are provided.
  • the wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact parts 301 and 302. There is.
  • the contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the second substrate 200 side). Each contact portion 202 is in contact with the contact portion 202 .
  • the contact sections 301 and 302 are connected to at least any of the circuits formed in the semiconductor layer 300S (for example, the input section 510A, the row drive section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560, and the output section 510B).
  • the contact parts 301 and 302 are made of metal such as Cu (copper) and aluminum (Al), for example.
  • metal such as Cu (copper) and aluminum (Al), for example.
  • an external terminal is connected to the input section 510A through the connection hole H1, and an external terminal is connected to the output section 510B through the connection hole H2.
  • Method for manufacturing pixel transistor 10A to 10J illustrate an example of a method for manufacturing the pixel transistor shown in FIG. 6B and the like.
  • a hard mask is formed on the surface 200S1 of the semiconductor layer 200S, and photolithography and etching are performed. For example, as shown in FIG. 10A, a plurality of grooves H3 are formed on the surface 200S1 of the semiconductor layer 200S. A plurality of fins 200A are formed at regular intervals on the entire surface 200S1. As a result, fins 200A are formed on the surface 200S1 of the semiconductor layer 200S with a substantially constant width and standing in a substantially vertical direction.
  • a silicon nitride film is formed as a hard mask 231 so as to fill the groove H3 between the plurality of fins 200A, and then the hard mask 231 is formed by CMP (Chemical Mechanical Polishing). Grind and flatten the surface.
  • the hard mask 231 is patterned by photolithography and etching so as to protect the active region 200X of the pixel transistor.
  • the fin 200A exposed from the hard mask 231 is etched. At this time, a portion of the fin 200A remains to form a convex portion 200B.
  • a p-type impurity for example, boron (B)
  • B boron
  • FIG. 10F an oxide film 232 is formed on the semiconductor layer 200S by, for example, thermal oxidation.
  • the oxide film 232 and hard mask 231 are ground by CMP to planarize the surface. This forms an element isolation region 213 that isolates adjacent pixel transistors.
  • the convex portion 200B formed in the semiconductor layer 200S can improve the adhesion strength between the semiconductor layer 200S and the element isolation region 213 by fitting into the element isolation region 213.
  • a continuous gate insulating film 216 is formed.
  • a polysilicon film 233 is formed so as to fill in between adjacent fins 200A and between fins 200A and element isolation region 213.
  • the polysilicon film 233 is processed.
  • the gate electrode 214G of the pixel transistor for example, the amplification transistor AMP and the selection transistor SEL
  • an n-type impurity for example, phosphorus (P)
  • an n-type impurity for example, arsenic (As)
  • As arsenic
  • FIG. 7A and the like show an example in which the well region 211 is selectively formed only below the element isolation region 213, the present invention is not limited to this.
  • the well region 211 may extend over the entire back surface 200S2 of the semiconductor layer 200S without reaching the base portion of the fin 200A. This enables more stable element isolation.
  • the well region 211 extending over the entire back surface 200S2 of the semiconductor layer 200S is formed by processing the front surface 200S1 of the semiconductor layer 200S by photolithography and etching to form a plurality of fins 200A. It can be formed by first implanting a p-type impurity (for example, boron (B)) by ion implantation or the like from the surface 200S1 side of the semiconductor layer 200S.
  • a p-type impurity for example, boron (B)
  • FIG. 10A shows an example in which a plurality of fins 200A are formed upright at equal intervals over the entire surface 200S1 of the semiconductor layer 200S
  • the present invention is not limited to this.
  • a layout in which a plurality of pixel transistors constituting the pixel circuit 210 are densely arranged may be used.
  • the groove H3 may be provided only in a predetermined region, and a plurality of fins 200A may be formed. In other words, it is not necessary to form the dummy fins 200A.
  • By arranging a layout in which a plurality of pixel transistors are densely arranged it is possible to form the fins 200A that stand up in a substantially vertical direction and have a substantially constant width without forming the dummy fins 200A.
  • FIGS. 14 and 15. 14 and 15 are the same as in FIG. 3 with arrows representing the paths of each signal added.
  • FIG. 14 shows the paths of input signals inputted to the imaging device 1 from the outside, the power supply potential, and the reference potential by arrows.
  • signal paths of pixel signals output from the imaging device 1 to the outside are represented by arrows.
  • an input signal for example, a pixel clock and a synchronization signal
  • the row drive unit 520 generates a row drive signal. produced.
  • This row drive signal is sent to the second substrate 200 via the contact parts 301 and 201. Furthermore, this row drive signal reaches each unit cell 539 of the pixel array section 540 via the row drive signal line 542 in the wiring layer 200T.
  • drive signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven.
  • the drive signal of the transfer gate TG is input to the transfer gate TG of the first substrate 100, and the pixel 541 is driven.
  • the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and the wiring The pixel circuit 210 of each unit cell 539 is supplied via wiring in the layer 200T.
  • the reference potential is also supplied to the pixels 541 of the first substrate 100.
  • pixel signals photoelectrically converted by the pixels 541 of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each unit cell 539.
  • a pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact sections 202 and 302. This pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300, and then outputted to the outside via the output section 510B.
  • FIG. 16 schematically shows a planar configuration of a pixel transistor as Comparative Example 1.
  • FIG. 17 schematically shows a cross-sectional configuration corresponding to the line VV' shown in FIG. 16.
  • FIG. 18 schematically shows a cross-sectional configuration corresponding to the line VI-VI' shown in FIG. 16.
  • the drain region 1214D having the highest voltage is transferred to the source region 1214S of the adjacent transistor. Can prevent current from flowing.
  • a p-type impurity eg, boron (B)
  • B boron
  • steps such as gate processing, LDD implantation, sidewall processing, and implantation of n-type impurities (for example, arsenic (As)) to form source and drain regions are performed.
  • a transistor having a cross-sectional configuration as shown in FIG. 18 is formed. As shown in FIGS.
  • the transistor formed in this manner has a P-type well 1211 formed at the base of the fin 1200A, which is a region where current does not easily flow even if the channel is reversed. is created.
  • a P-type well 1211 formed at the base of the fin 1200A, which is a region where current does not easily flow even if the channel is reversed. is created.
  • L channel length
  • W channel width
  • the gm of the fin type transistor manufactured using the above method is 1.4.
  • RTS Random Telegraph Signal
  • the entire fin 200A formed between the vertical portions 214Ga and 214Gb constituting the gate electrode 214G is made of non-doped semiconductor.
  • the layer 200S is formed. This allows the entire fin 200A to be used as a channel region. Therefore, gm can be improved compared to a general fin type transistor. Furthermore, RTS noise can be improved.
  • the imaging device 1 of this embodiment it is possible to improve device characteristics compared to an imaging device equipped with a general fin-type pixel transistor.
  • FIG. 19 schematically shows an example of a planar layout of the plurality of fins 1200A.
  • FIG. 20 schematically shows an example of the cross-sectional shape of each fin 1200A when the fin 1200A is formed by etching in the planar layout shown in FIG.
  • FIG. 20 schematically shows another example of the cross-sectional shape of each fin 1200A when the fin 1200A is formed by etching in the planar layout shown in FIG.
  • a taper is formed on the side surface of the fins 1200A.
  • Anisotropic dry etching can be performed vertically by balancing the re-deposition of reaction products between the etching gas and the etched material and etching. However, when the peripheral etching areas are different, the balance between attachment of reaction products and etching changes due to the difference in the etching areas.
  • the flow rate of etching gas is adjusted so that the side walls of adjacent fins 1200A are vertical at interval W2.
  • the pressure, electrode voltage, etc. as shown in FIG. 20, although the side walls of the fins 1200A adjacent to each other at the interval W2 can be machined vertically, the side walls are tapered depending on the intervals of other parts. Ru.
  • the flow rate and pressure of the etching gas, the electrode voltage, etc. are adjusted so that the side wall of the fin 1200A between the interval W3 and the interval W4 is vertical, as shown in FIG.
  • the side walls of the fins 1200A arranged at narrow intervals are excessively etched, resulting in a curved cross-sectional shape.
  • the gate insulating film formed on the constricted part becomes extremely thin, which may cause a decrease in durability or breakdown. becomes.
  • the plurality of fins 120A and the active region 120X are processed separately. Specifically, as shown in FIG. 10A, grooves H3 are formed so that a plurality of fins 200A including the dummy fins 200A are equally spaced, and then the dummy fins 200A are selectively removed to form the element. A separation region 213 is formed. As a result, the side walls of all the fins 200A are processed substantially vertically. Therefore, the size of the transistor in the width direction (X-axis direction) of the fin 200A can be reduced, and area efficiency can be improved. Further, since the width of the groove H3 for forming the fin 200A is substantially constant, the time required to consider etching conditions can be reduced. Furthermore, since the side walls of the fins 200A are substantially vertical, short channel characteristics (SCE) can be improved.
  • SCE short channel characteristics
  • FIG. 22 schematically shows a planar configuration of a pixel transistor as Comparative Example 2.
  • FIG. 23 schematically shows a cross-sectional configuration corresponding to the line VIII-VIII' shown in FIG. 22.
  • FIG. 24 schematically shows a cross-sectional configuration corresponding to the line IX-IX' shown in FIG. 22.
  • FIG. 25 shows mutual conductance (gm) of Comparative Example 2 and Example.
  • FIG. 26 shows the current-voltage characteristics of Comparative Example 2 and Example. As shown in FIG. 23, if there is no taper in the buried portion of the gate electrode 1214G, a channel is formed on the bottom surface of the buried gate electrode 1214G.
  • the depth of the fin 1200A is made deep (for example, 200 nm) and the source region 1214S and drain region 1214D are formed to a depth corresponding to the base portion of the fin 1200A, impurities will diffuse into the vertical channel portion. It becomes a transistor that cannot be turned off.
  • the maximum depth of the source region 1214S and drain region 1214D is about 100 nm to 150 nm, and the impurity concentration becomes lower in deeper portions. Therefore, in the vertical channel portion of the fin 1200A having a depth exceeding 100 nm to 150 nm, the resistance of the source region 1214S and the drain region 1214D becomes high, so that not much current flows.
  • a notch X is formed at the outer edge of the active region 200X having a substantially rectangular shape, vertical portions 214Ga and 214Gb of the gate 214 are formed in this notch X, and the source
  • the horizontal portion 214Gc so as to cover part of the region 214S and the drain region 214D, in addition to the surface channel 214Ca, a side wall channel 214Cb, a bottom channel 214Cc, and a transport channel 214Cd are formed in the cutout X. Therefore, as shown in FIGS. 25 and 26, it is desirable to provide a transistor that has a higher gm and excellent current-voltage characteristics compared to the above-described transistor (Comparative Example 2) even though the transistor has the same area. becomes possible.
  • FIG. 27 schematically illustrates a cross-sectional configuration of a pixel transistor according to Modification 1 of the present disclosure.
  • the width of the horizontal portion 214Gc constituting the gate electrode 214G extending to the source region 214S side and the drain region 214D side is the same, but the width is not limited to this.
  • the width (W5) of the horizontal portion 214Gc constituting the gate electrode 214G extending toward the drain region 214D is made larger than the width (W6) of extending toward the source region 214S ( W5>W6).
  • NMOS transistors have a problem in that the current value decreases due to an increase in threshold voltage and a decrease in mobility due to the occurrence of hot carrier injection (HCI) phenomenon.
  • HCI hot carrier injection
  • FIG. 28 shows the relationship between noise current (Isub) and life depending on sidewall width. It can be seen that when trying to reduce the footprint by reducing the sidewall width, the lifespan is shortened.
  • the horizontal portion 214Gc forming the gate electrode 214G is made to extend more toward the drain region 214D side where a high voltage is applied.
  • the extension of the horizontal portion 214Gc toward the drain region 214D can provide the same effect as the formation of the sidewall 215. Specifically, by extending the horizontal portion 214Gc to the side of the drain region 214D, a distance between the drain region 214D and the channel end can be ensured, so that the electric field at the end of the gate electrode 142G can be relaxed. Further, a sufficient area can be secured between the drain region 214D and the channel region in which the LDD region 214L for relaxing the electric field is formed.
  • (2-2. Modification 2) 29A to 29K illustrate an example of a method for manufacturing a pixel transistor according to Modification 2 of the present disclosure.
  • FIG. 29A photolithography and etching are performed on the semiconductor layer 200S in which the well region 211 has been formed in advance, and the semiconductor layer 200S other than the active region is processed.
  • a silicon nitride film (SiN film) 235 is formed and the surface is planarized by CMP, and then a hard mask 234 is patterned by lithography.
  • a p-type impurity for example, boron (B)
  • B boron
  • an oxide film that will become the element isolation region 213 is formed on the semiconductor layer 200S by, for example, thermal oxidation.
  • the oxide film and SiN film 235 that will become the element isolation region 213 are ground by CMP to planarize the surface, and then a hard mask 236 is formed.
  • This hard mask 236 may be an oxide film or a multilayer film such as a silicon nitride film stacked on an oxide film.
  • the hard mask 236 is patterned using a lithography technique.
  • the semiconductor layer 200S exposed from the hard mask 236 is etched to form a groove H3 having the same width. Thereby, a plurality of fins 200A are formed.
  • hard mask 236 is removed using a hot phosphoric acid solution.
  • FIG. 29I after forming a continuous gate insulating film 216 on the side surfaces and top surfaces of the plurality of fins 200A and the surface of the semiconductor layer 200S exposed between the adjacent fins 200A, the adjacent fins 200A A polysilicon film 233 is formed so as to fill in the space between the fin 200A and the element isolation region 213.
  • the polysilicon film 233 is processed.
  • the gate electrode 214G of the pixel transistor for example, the amplification transistor AMP and the selection transistor SEL
  • an n-type impurity for example, phosphorus (P)
  • P phosphorus
  • an n-type impurity for example, arsenic (As) is implanted at a higher concentration than the LDD region 214L to form a source region 214S and a drain region 214D, thereby completing the pixel transistor shown in FIG. 29K. do.
  • n-type impurity for example, arsenic (As)
  • FIG. 30 schematically represents the planar configuration of the amplification transistor AMP and selection transistor SEL shown in FIG. 29K.
  • the pixel transistor manufactured using the manufacturing process of this modification since the element isolation region 213 is first formed, the groove H3 formed at the outer edge of the active region, which forms the notch portion X, remains as it is. Therefore, the width is wider than the vertical portions 214Ga and 214Gb of the gate electrode 214G formed in the cutout portion X of the pixel transistor manufactured using the manufacturing process described in the above embodiment.
  • the width of the vertical portions 214Ga, 214Gb of the gate electrode 214G is smaller than, for example, the vertical portion 214Gd embedded in the active region of the amplification transistor AMP, whereas in the present modification example
  • the width of the vertical portions 214Ga, 214Gb of the gate electrode 214G formed using the manufacturing process is, for example, approximately the same width as the vertical portion 214Gd embedded in the active region of the amplification transistor AMP.
  • the area of the gate electrode 214G increases accordingly.
  • the area efficiency is lower than that of the pixel transistor of the above embodiment, even if the plurality of fins 200A are formed after forming the element isolation region 213, the same effect as that of the above embodiment can be obtained. It is possible to form a pixel transistor that provides the following.
  • the imaging device 1 and the like can be applied to any type of electronic device having an imaging function, such as a camera system such as a digital still camera or a video camera, or a mobile phone having an imaging function.
  • FIG. 31 shows a schematic configuration of electronic device 1000.
  • the electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display section 1004, a recording section 1005, an operation section 1006, and a power supply section 1007. and are interconnected via a bus line 1008.
  • a lens group 1001 an imaging device 1
  • a DSP (Digital Signal Processor) circuit 1002 a frame memory 1003, a display section 1004, a recording section 1005, an operation section 1006, and a power supply section 1007. and are interconnected via a bus line 1008.
  • DSP Digital Signal Processor
  • the lens group 1001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1.
  • the imaging device 1 converts the amount of incident light focused on the imaging surface by the lens group 1001 into an electrical signal for each pixel, and supplies the electrical signal to the DSP circuit 1002 as a pixel signal.
  • the DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1.
  • the DSP circuit 1002 processes signals from the imaging device 1 and outputs image data obtained.
  • the frame memory 1003 temporarily stores image data processed by the DSP circuit 1002 in units of frames.
  • the display unit 1004 is composed of a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays image data of moving images or still images captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk. to be recorded.
  • a panel type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel
  • a recording medium such as a semiconductor memory or a hard disk. to be recorded.
  • the operation unit 1006 outputs operation signals regarding various functions owned by the electronic device 1000 in accordance with user operations.
  • the power supply unit 1007 appropriately supplies various kinds of power to serve as operating power for the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006 to these supply targets.
  • FIG. 32A schematically represents an example of the overall configuration of a photodetection system 2000 including the imaging device 1.
  • FIG. 32B shows an example of the circuit configuration of the photodetection system 2000.
  • the photodetection system 2000 includes a light emitting device 2001 as a light source section that emits infrared light L2, and a photodetection device 2002 as a light receiving section having a photoelectric conversion element.
  • the photodetection device 2002 the above-described imaging device 1 can be used.
  • the light detection system 2000 may further include a system control section 2003, a light source drive section 2004, a sensor control section 2005, a light source side optical system 2006, and a camera side optical system 2007.
  • the light detection device 2002 can detect light L1 and light L2.
  • the light L1 is the light that is the ambient light from the outside reflected on the subject (measurement object) 2100 (FIG. 32A).
  • Light L2 is light that is emitted by the light emitting device 2001 and then reflected by the subject 2100.
  • the light L1 is, for example, visible light
  • the light L2 is, for example, infrared light.
  • Light L1 can be detected in a photoelectric conversion section in photodetection device 2002, and light L2 can be detected in a photoelectric conversion region in photodetection device 2002.
  • Image information of the subject 2100 can be obtained from the light L1, and distance information between the subject 2100 and the light detection system 2000 can be obtained from the light L2.
  • the photodetection system 2000 can be installed in, for example, an electronic device such as a smartphone or a mobile object such as a car.
  • the light emitting device 2001 can be configured with, for example, a semiconductor laser, a surface emitting semiconductor laser, or a vertical cavity surface emitting laser (VCSEL).
  • VCSEL vertical cavity surface emitting laser
  • an iTOF method can be adopted, but the method is not limited thereto.
  • the photoelectric conversion unit can measure the distance to the subject 2100 using, for example, time-of-flight (TOF).
  • a structured light method or a stereo vision method can be adopted as a method for detecting the light L2 emitted from the light emitting device 2001 by the photodetecting device 2002.
  • the distance between the light detection system 2000 and the subject 2100 can be measured by projecting a predetermined pattern of light onto the subject 2100 and analyzing the degree of distortion of the pattern.
  • the stereo vision method the distance between the light detection system 2000 and the subject can be measured by, for example, using two or more cameras and acquiring two or more images of the subject 2100 viewed from two or more different viewpoints. can.
  • the light emitting device 2001 and the photodetecting device 2002 can be synchronously controlled by the system control unit 2003.
  • FIG. 33 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (present technology) can be applied.
  • FIG. 33 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using the endoscopic surgery system 11000.
  • the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 that supports the endoscope 11100. , and a cart 11200 loaded with various devices for endoscopic surgery.
  • the endoscope 11100 is composed of a lens barrel 11101 whose distal end is inserted into a body cavity of a patient 11132 over a predetermined length, and a camera head 11102 connected to the proximal end of the lens barrel 11101.
  • an endoscope 11100 configured as a so-called rigid scope having a rigid tube 11101 is shown, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible tube. good.
  • An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101.
  • a light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and the light is guided to the tip of the lens barrel. Irradiation is directed toward an observation target within the body cavity of the patient 11132 through the lens.
  • the endoscope 11100 may be a direct-viewing mirror, a diagonal-viewing mirror, or a side-viewing mirror.
  • An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from an observation target is focused on the image sensor by the optical system.
  • the observation light is photoelectrically converted by the image sensor, and an electric signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated.
  • the image signal is transmitted as RAW data to a camera control unit (CCU) 11201.
  • CCU camera control unit
  • the CCU 11201 includes a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and the like, and centrally controls the operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under control from the CCU 11201.
  • the light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site or the like.
  • a light source such as an LED (light emitting diode)
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • the user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100.
  • a treatment tool control device 11205 controls driving of an energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, or the like.
  • the pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 in order to inflate the body cavity of the patient 11132 for the purpose of ensuring a field of view with the endoscope 11100 and a working space for the operator. send in.
  • the recorder 11207 is a device that can record various information regarding surgery.
  • the printer 11208 is a device that can print various types of information regarding surgery in various formats such as text, images, or graphs.
  • the light source device 11203 that supplies irradiation light to the endoscope 11100 when photographing the surgical site can be configured, for example, from a white light source configured by an LED, a laser light source, or a combination thereof.
  • a white light source configured by a combination of RGB laser light sources
  • the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image is adjusted in the light source device 11203. It can be carried out.
  • the laser light from each RGB laser light source is irradiated onto the observation target in a time-sharing manner, and the drive of the image sensor of the camera head 11102 is controlled in synchronization with the irradiation timing, thereby supporting each of RGB. It is also possible to capture images in a time-division manner. According to this method, a color image can be obtained without providing a color filter in the image sensor.
  • the driving of the light source device 11203 may be controlled so that the intensity of the light it outputs is changed at predetermined time intervals.
  • the drive of the image sensor of the camera head 11102 in synchronization with the timing of changes in the light intensity to acquire images in a time-division manner and compositing the images, a high dynamic It is possible to generate an image of a range.
  • the light source device 11203 may be configured to be able to supply light in a predetermined wavelength range compatible with special light observation.
  • Special light observation uses, for example, the wavelength dependence of light absorption in body tissues to illuminate the mucosal surface layer by irradiating a narrower band of light than the light used for normal observation (i.e., white light).
  • Narrow Band Imaging is performed to photograph specific tissues such as blood vessels with high contrast.
  • fluorescence observation may be performed in which an image is obtained using fluorescence generated by irradiating excitation light.
  • Fluorescence observation involves irradiating body tissues with excitation light and observing the fluorescence from the body tissues (autofluorescence observation), or locally injecting reagents such as indocyanine green (ICG) into the body tissues and It is possible to obtain a fluorescence image by irradiating excitation light corresponding to the fluorescence wavelength of the reagent.
  • the light source device 11203 may be configured to be able to supply narrowband light and/or excitation light compatible with such special light observation.
  • FIG. 34 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 33.
  • the camera head 11102 includes a lens unit 11401, an imaging section 11402, a driving section 11403, a communication section 11404, and a camera head control section 11405.
  • the CCU 11201 includes a communication section 11411, an image processing section 11412, and a control section 11413. Camera head 11102 and CCU 11201 are communicably connected to each other by transmission cable 11400.
  • the lens unit 11401 is an optical system provided at the connection part with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401.
  • the lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.
  • the imaging element configuring the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type).
  • image signals corresponding to RGB are generated by each imaging element, and a color image may be obtained by combining them.
  • the imaging unit 11402 may be configured to include a pair of imaging elements for respectively acquiring right-eye and left-eye image signals corresponding to 3D (dimensional) display. By performing 3D display, the operator 11131 can more accurately grasp the depth of the living tissue at the surgical site.
  • a plurality of lens units 11401 may be provided corresponding to each imaging element.
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.
  • the drive unit 11403 is constituted by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under control from the camera head control unit 11405. Thereby, the magnification and focus of the image captured by the imaging unit 11402 can be adjusted as appropriate.
  • the communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.
  • the communication unit 11404 receives a control signal for controlling the drive of the camera head 11102 from the CCU 11201 and supplies it to the camera head control unit 11405.
  • the control signal may include, for example, information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing, and/or information specifying the magnification and focus of the captured image. Contains information about conditions.
  • the above imaging conditions such as the frame rate, exposure value, magnification, focus, etc. may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. good.
  • the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
  • the camera head control unit 11405 controls the drive of the camera head 11102 based on the control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102.
  • the communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
  • the communication unit 11411 transmits a control signal for controlling the drive of the camera head 11102 to the camera head 11102.
  • the image signal and control signal can be transmitted by electrical communication, optical communication, or the like.
  • the image processing unit 11412 performs various image processing on the image signal, which is RAW data, transmitted from the camera head 11102.
  • the control unit 11413 performs various controls related to the imaging of the surgical site etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site etc. For example, the control unit 11413 generates a control signal for controlling the drive of the camera head 11102.
  • control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal subjected to image processing by the image processing unit 11412.
  • the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 detects the shape and color of the edge of an object included in the captured image to detect surgical tools such as forceps, specific body parts, bleeding, mist when using the energy treatment tool 11112, etc. can be recognized.
  • the control unit 11413 may use the recognition result to superimpose and display various types of surgical support information on the image of the surgical site. By displaying the surgical support information in a superimposed manner and presenting it to the surgeon 11131, it becomes possible to reduce the burden on the surgeon 11131 and allow the surgeon 11131 to proceed with the surgery reliably.
  • the transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.
  • communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.
  • the technology according to the present disclosure can be applied to the imaging unit 11402 among the configurations described above. By applying the technology according to the present disclosure to the imaging unit 11402, detection accuracy is improved.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be applied to any type of transportation such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), etc. It may also be realized as a device mounted on the body.
  • FIG. 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output section 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a drive force generation device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits the drive force to wheels, and a drive force transmission mechanism that controls the steering angle of the vehicle. It functions as a control device for a steering mechanism to adjust and a braking device to generate braking force for the vehicle.
  • the body system control unit 12020 controls the operations of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a turn signal, or a fog lamp.
  • radio waves transmitted from a portable device that replaces a key or signals from various switches may be input to the body control unit 12020.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, power window device, lamp, etc. of the vehicle.
  • the external information detection unit 12030 detects information external to the vehicle in which the vehicle control system 12000 is mounted.
  • an imaging section 12031 is connected to the outside-vehicle information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the external information detection unit 12030 may perform object detection processing such as a person, car, obstacle, sign, or text on the road surface or distance detection processing based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electrical signal as an image or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • a driver condition detection section 12041 that detects the condition of the driver is connected to the in-vehicle information detection unit 12040.
  • the driver condition detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver condition detection unit 12041. It may be calculated, or it may be determined whether the driver is falling asleep.
  • the microcomputer 12051 calculates control target values for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, Control commands can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following distance based on vehicle distance, vehicle speed maintenance, vehicle collision warning, vehicle lane departure warning, etc. It is possible to perform cooperative control for the purpose of
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of autonomous driving, etc., which does not rely on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of preventing glare, such as switching from high beam to low beam. It can be carried out.
  • the audio and image output unit 12052 transmits an output signal of at least one of audio and images to an output device that can visually or audibly notify information to the occupants of the vehicle or to the outside of the vehicle.
  • an audio speaker 12061, a display section 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 36 is a diagram showing an example of the installation position of the imaging section 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle 12100.
  • An imaging unit 12101 provided in the front nose and an imaging unit 12105 provided above the windshield inside the vehicle mainly acquire images in front of the vehicle 12100.
  • Imaging units 12102 and 12103 provided in the side mirrors mainly capture images of the sides of the vehicle 12100.
  • An imaging unit 12104 provided in the rear bumper or back door mainly captures images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided above the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 36 shows an example of the imaging range of the imaging units 12101 to 12104.
  • An imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • an imaging range 12114 shows the imaging range of the imaging unit 12101 provided on the front nose.
  • the imaging range of the imaging unit 12104 provided in the rear bumper or back door is shown. For example, by overlapping the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an image sensor having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In particular, by determining the three-dimensional object that is closest to the vehicle 12100 on its path and that is traveling at a predetermined speed (for example, 0 km/h or more) in approximately the same direction as the vehicle 12100, it is possible to extract the three-dimensional object as the preceding vehicle. can.
  • a predetermined speed for example, 0 km/h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, etc., in which the vehicle travels autonomously without depending on the driver's operation.
  • the microcomputer 12051 transfers three-dimensional object data to other three-dimensional objects such as two-wheeled vehicles, regular vehicles, large vehicles, pedestrians, and utility poles based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceeds a set value and there is a possibility of a collision, the microcomputer 12051 transmits information via the audio speaker 12061 and the display unit 12062. By outputting a warning to the driver via the vehicle control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
  • the microcomputer 12051 determines a collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk exceed
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101 to 12104.
  • pedestrian recognition involves, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and a pattern matching process is performed on a series of feature points indicating the outline of an object to determine whether it is a pedestrian or not.
  • the audio image output unit 12052 creates a rectangular outline for emphasis on the recognized pedestrian.
  • the display unit 12062 is controlled to display the .
  • the audio image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the photoelectric conversion unit (photodiode PD) and the pixel circuit (pixel circuit 210) are provided on different substrates (the first substrate 100 and the second substrate 200). , but is not limited to this.
  • the pixel circuit 210 may be formed together with the transfer transistor TR on the surface of the semiconductor layer 100S constituting the first substrate 100, on which the photodiode PD is formed. In that case as well, similar effects can be obtained by applying the present technology.
  • the present technology can be applied to various semiconductor devices and electronic devices other than imaging devices.
  • the present invention can be applied to electronic devices including semiconductor elements such as photodetecting elements, light receiving elements, photoelectric conversion elements, ionizing radiation energy conversion elements, semiconductor detectors, integrated circuits, and memories.
  • semiconductor elements such as photodetecting elements, light receiving elements, photoelectric conversion elements, ionizing radiation energy conversion elements, semiconductor detectors, integrated circuits, and memories.
  • the photodiode PD and the pixel circuit 210 are installed on different substrates (first substrate 100 and second substrate 200).
  • the configuration provided in the photodiode PD can provide a greater effect because it is not affected by the p-well layer 112 that constitutes the photodiode PD.
  • the present disclosure can also have the following configuration.
  • the first electrode part and the second electrode part constituting the gate electrode of the first active element are embedded.
  • a non-doped first semiconductor region is formed between the two. This makes it possible to use the entire first semiconductor layer between the first electrode part and the second electrode part as a channel region, thereby making it possible to improve device characteristics.
  • a photoelectric conversion unit that generates a charge according to the amount of received light; A predetermined operation is performed on the charges generated in the photoelectric conversion section, and a first electrode section and a second electrode section are arranged in parallel in a first direction, and the first electrode section and the second electrode section are arranged in parallel in a first direction.
  • a first active element having a gate electrode including a third electrode portion connected to the electrode portion has a first surface and a second surface facing each other, the first electrode part and the second electrode part of the gate electrode are embedded in the first surface side, and the first electrode part and a first semiconductor layer having a non-doped first semiconductor region between the second electrode section.
  • the imaging device includes a first standing portion formed of the first semiconductor region provided between the first electrode portion and the second electrode portion of the first active element. , a convex portion is provided between the first electrode portion of the second active element and a second standing portion formed of the first semiconductor region provided between the second electrode portion.
  • the convex portion is covered by a separation portion that electrically separates the first active element and the second active element,
  • the first active element is a surface channel formed near the first surface of the first semiconductor layer between the first electrode part and the second electrode part; a sidewall channel extending from the surface channel along each of opposing first side surfaces of the first electrode portion and the second electrode portion; A bottom channel is formed on the bottom surface of the first electrode section and the second electrode section and is continuous with the side wall channel;
  • the imaging device according to any one of (1) to (7), wherein the imaging device has a transport channel that extends along a second side surface adjacent to the first side surface and is continuous with the bottom channel. . (9) The imaging device according to (8), wherein the width of the side wall channel becomes narrower from the first surface side to the second surface side.
  • the imaging device according to any one of (10).
  • the first active element has a fourth electrode part provided between the first electrode part and the second electrode part and connected to the third electrode part,
  • the imaging device according to any one of (1) to (11), wherein the fourth electrode portion is embedded in the first semiconductor region.
  • the imaging device according to (12), wherein the first electrode part, the second electrode part, and the fourth electrode part have the same width in the first direction.
  • the width of the first electrode part and the second electrode part in the first direction is smaller than the width of the fourth electrode part in the first direction.
  • the first electrode part and the second electrode part each extend in a second direction substantially perpendicular to the first direction in plan view
  • the third electrode portion is formed on the first surface of the first semiconductor layer, and is formed on the outside of both ends of the first electrode portion and the second electrode portion in the extending direction. It has an overhanging part, The width of the first protruding part protruding from the one end of the first protruding part protruding toward one end of both ends of each of the first electrode part and the second electrode part;
  • the imaging device according to any one of (1) to (14), wherein the width of the second projecting portion projecting toward the end portion from the other end portion is different from each other.
  • the first semiconductor region extends in the second direction between the first electrode part and the second electrode part in a plan view, The method according to (15), wherein the first semiconductor layer has third semiconductor regions doped with impurities of a second conductivity type at both ends of the first semiconductor region in the extending direction. Imaging device.
  • the third semiconductor region on one end side is a source region of the first active element
  • the third semiconductor region on the other end side is a drain region of the first active element
  • the first overhang extends toward the source region
  • the second projecting portion projects toward the drain region
  • the imaging device according to (16) wherein a projecting width of the second projecting portion is larger than a projecting width of the first projecting portion.
  • the first active element is one or more transistors that constitute a pixel circuit that generates a pixel signal based on the charge generated in the photoelectric conversion section.
  • a photoelectric conversion unit that generates a charge according to the amount of received light; a first semiconductor layer having a first surface and a second surface facing each other; A predetermined operation is performed on the charges generated in the photoelectric conversion section, and a first electrode section and a second electrode section are arranged in parallel in a first direction, and the first electrode section and the second electrode section are arranged in parallel in a first direction.
  • a first active element having a gate electrode including a third electrode part connected to the electrode part; The first electrode portion and the second electrode portion are each embedded in the first surface side of the first semiconductor layer, and each is approximately located in the first direction in plan view.
  • the third electrode portion is formed on the first surface of the first semiconductor layer, and is formed on the outside of both ends of the first electrode portion and the second electrode portion in the extending direction. It has an overhanging part, The width of the first protruding part protruding from the one end of the first protruding part protruding toward one end of both ends of each of the first electrode part and the second electrode part; The width of the second overhang extending toward the end of the second overhang from the other end is different from each other.

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  • Solid State Image Pick-Up Elements (AREA)
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KR1020257002526A KR20250034961A (ko) 2022-07-12 2023-06-12 촬상 장치
JP2024533588A JPWO2024014209A1 (https=) 2022-07-12 2023-06-12
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JP2021034435A (ja) 2019-08-20 2021-03-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置およびその製造方法、並びに電子機器
WO2021171798A1 (ja) * 2020-02-28 2021-09-02 ソニーセミコンダクタソリューションズ株式会社 撮像装置及び光検出装置
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TW202416517A (zh) 2024-04-16
EP4557371A1 (en) 2025-05-21
CN119318225A (zh) 2025-01-14

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