WO2024012032A1 - 动态d触发器、数据运算单元、芯片、算力板及计算设备 - Google Patents

动态d触发器、数据运算单元、芯片、算力板及计算设备 Download PDF

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Publication number
WO2024012032A1
WO2024012032A1 PCT/CN2023/093277 CN2023093277W WO2024012032A1 WO 2024012032 A1 WO2024012032 A1 WO 2024012032A1 CN 2023093277 W CN2023093277 W CN 2023093277W WO 2024012032 A1 WO2024012032 A1 WO 2024012032A1
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Prior art keywords
terminal
node
electrically connected
flip
dynamic
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PCT/CN2023/093277
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English (en)
French (fr)
Inventor
陈双文
李智
张楠赓
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上海嘉楠捷思信息技术有限公司
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Publication of WO2024012032A1 publication Critical patent/WO2024012032A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a clock-controlled memory device, and in particular to a register, arithmetic unit, a chip and a computing device used in large-scale data computing equipment.
  • Dynamic triggers are widely used and can be used to register digital signals.
  • the transmitted data is usually temporarily stored in the parasitic capacitance generated by the transistors that constitute the latch unit.
  • the temporarily stored data is prone to dynamic leakage, resulting in insufficient data retention time, which in turn leads to data loss and reduced operation accuracy.
  • the present invention provides a dynamic D flip-flop, which can effectively increase the retention time of data and improve the security and accuracy of data.
  • the present invention provides a dynamic D flip-flop, which includes an input terminal for inputting a first data; an output terminal for outputting a second data; and a clock signal terminal for providing a clock signal. ;
  • a first latch unit used to transmit the data at the input end and latch the first data under the control of a clock signal; a second latch unit, used to latch the data transmitted by the first latch unit data; an output drive unit for outputting the data received from the second latch unit;
  • the first latch unit, the second latch unit and the output drive unit are connected in series in sequence between the input terminal and the output terminal; there is a first node between the first latch unit and the second latch unit, and there is a first node between the second latch unit and the output driving unit.
  • a second node wherein, it also includes a data holding unit, the data holding unit is electrically connected to the first node and/or the second node, and the data holding unit is used to assist in storing the data latched there. data at the first node and/or the second node.
  • the above dynamic D flip-flop wherein the data holding unit has a first end and a second end, the first end of the data holding unit is electrically connected to the first node, and the data holding unit has The second terminal is electrically connected to the second node.
  • the data holding unit includes a PMOS transistor and/or an NMOS transistor.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, and the source terminal of the PMOS transistor is electrically connected to the first node or the second node, so The drain terminal of the PMOS transistor is electrically connected to the second node or the first node, and the gate terminal of the PMOS transistor is electrically connected to a power supply.
  • the above dynamic D flip-flop wherein the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the source terminal of the NMOS transistor is electrically connected to the first node or the second node, so The drain terminal of the NMOS transistor is electrically connected to the second node or the first node, and the gate terminal of the NMOS transistor is electrically connected to a ground.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, and the source terminal and drain terminal of the PMOS transistor are electrically connected to the first node or the second node. node, the gate terminal of the PMOS transistor is electrically connected to the second node or the first node.
  • the above dynamic D flip-flop wherein the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the source terminal and drain terminal of the NMOS transistor are electrically connected to the first node or the second node. node, the gate terminal of the NMOS transistor is electrically connected to the second node or the first node.
  • the data holding unit is electrically connected to the first node or the second node, and the data holding unit includes a PMOS transistor and/or an NMOS transistor.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to the first node, the PMOS transistor The gate terminal is electrically connected to a power source.
  • the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to the first node, the NMOS transistor The gate terminal is electrically connected to ground.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to a power supply, and the gate terminal of the PMOS transistor electrically connected to the first node.
  • the NMOS transistor has a source terminal and a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to a ground, and the gate terminal of the NMOS transistor is electrically connected to the first node.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the PMOS transistor are electrically connected to a power supply, and the drain terminal of the PMOS transistor electrically connected to the first node.
  • the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the NMOS transistor are electrically connected to a ground, and the drain terminal of the NMOS transistor electrically connected to the first node.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to the second node, the PMOS transistor The gate terminal is electrically connected to a power source.
  • the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to the second node, the NMOS transistor The gate terminal is electrically connected to ground.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the PMOS transistor are electrically connected to a power supply, and the gate terminal of the PMOS transistor electrically connected to the second node.
  • the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the drain terminal of the NMOS transistor are electrically connected to a ground, and the gate terminal of the NMOS transistor electrically connected to the second node.
  • the above dynamic D flip-flop wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the PMOS transistor are electrically connected to a power supply, and the drain terminal of the PMOS transistor electrically connected to the second node.
  • the NMOS transistor has a source terminal, a drain terminal and a gate terminal, the source terminal and the gate terminal of the NMOS transistor are electrically connected to a ground, and the drain terminal of the NMOS transistor electrically connected to the second node.
  • the clock signal includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are inverted.
  • the first latch unit is a transmission gate.
  • the transmission gate includes a PMOS transistor connected in parallel and an NMOS transistor, the gate terminal of the PMOS transistor is electrically connected to the first clock signal, and the gate terminal of the NMOS transistor is electrically connected to the second clock signal.
  • the second latch unit is a three-state inverter.
  • the three-state inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor connected in series, wherein the first PMOS transistor
  • the gate terminal of the transistor and the second NMOS transistor are electrically connected as the input terminal of the three-state inverter
  • the gate terminal of the second PMOS transistor is electrically connected to the second clock signal
  • the first The gate terminal of the NMOS transistor is electrically connected to the first clock signal.
  • the output driving unit is an inverter.
  • the inverter includes a PMOS transistor and an NMOS transistor connected in series.
  • Using the dynamic D flip-flop of the present invention can effectively increase the retention time of data and improve the security and accuracy of data.
  • the present invention also provides a data operation unit, including an interconnected control circuit, an operation circuit, and a plurality of dynamic D flip-flops.
  • the plurality of dynamic D flip-flops are connected in series and/or in parallel. Connection; wherein, the plurality of dynamic D flip-flops are any of the above dynamic D flip-flops.
  • the present invention also provides a chip, which includes at least one data operation unit as described above.
  • the present invention also provides a computing board for a computing device, which includes at least one chip as described above.
  • the present invention also provides a computing device, including a power board, a control board, a connection board, a radiator and a plurality of computing power boards.
  • the control board communicates with the computing power board through the connection board.
  • the force board is connected, the heat sink is arranged around the hash board, and the power board is used to provide power to the connection board, the control board, the heat sink and the hash board, and its characteristics
  • the computing power board is the computing power board as mentioned above.
  • Figure 1 is a schematic circuit structure diagram of a dynamic D flip-flop according to an embodiment of the present invention
  • Figure 2 is a schematic circuit structure diagram of a dynamic D flip-flop according to another embodiment of the present invention.
  • Figure 3 is a schematic circuit structure diagram of a dynamic D flip-flop according to another embodiment of the present invention.
  • Figure 4 is a schematic circuit structure diagram of a dynamic D flip-flop according to yet another embodiment of the present invention.
  • Figure 5 is a schematic circuit structure diagram of a dynamic D flip-flop according to an expanded embodiment of the present invention.
  • Figure 6 is a schematic structural diagram of the data operation unit of the present invention.
  • Figure 7 is a schematic structural diagram of the chip of the present invention.
  • Figure 8 is a schematic structural diagram of the computing board of the present invention.
  • Figure 9 is a schematic structural diagram of the computing device of the present invention.
  • connection here includes any direct and indirect means of electrical connection. Indirect electrical connection means include connection through other devices.
  • FIG. 1 is a schematic circuit structure diagram of a dynamic D flip-flop according to an embodiment of the present invention.
  • the dynamic D flip-flop 100 includes an input terminal D, an output terminal Q, a first clock signal terminal CLK1, a second clock signal terminal CLK2, a first latch unit 101, a second latch unit 102, and an output driver. unit 103 and data holding unit 104.
  • the first latch unit 101, the second latch unit 102 and the output driving unit 103 are connected in series between the input terminal D and the output terminal Q.
  • the first latch unit 101 and the second latch unit 102 form a first A second node S1 is formed between node S0, the second latch unit 102 and the output driving unit 103.
  • the data holding unit 104 is electrically connected between the first node S0 and the second node S1.
  • the input terminal D of the dynamic D flip-flop 100 is used to input the required transmission data from the outside to the dynamic D flip-flop 100
  • the output terminal Q is used to output the required transmission data from the dynamic D flip-flop 100 to the outside.
  • a clock signal terminal CLK1 and a second clock signal terminal CLK2 are used to trigger the dynamic D
  • the device 100 provides a clock control signal, which includes a clock signal CKP and a clock signal CKN, to control the on and off of the first latch unit 101 and the second latch unit 102.
  • the clock signal CKN and the clock signal CKP are inverted clock signals, and the first latch unit 101 and the second latch unit 102 are not turned on or off at the same time.
  • the first latch unit 101 of the dynamic D flip-flop 100 has a transmission gate structure, and the first latch unit 101 includes PMOS transistors and NMOS transistors connected in parallel. One end of the first latch unit 101 is electrically connected to the input terminal D, and the other end of the first latch unit 101 is electrically connected to the first node S0.
  • the gate terminal of the NMOS transistor of the first latch unit 101 is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor is electrically connected to the clock signal CKP.
  • the first latch unit 101 When CKP is low level and CKN is high level, both the PMOS transistor and the NMOS transistor of the first latch unit 101 are in a conductive state, and the input terminal D transmits the data to be transmitted to the first latch unit 101 through the first latch unit 101 . Node S0.
  • CKP When CKP is high level and CKN is low level, both the PMOS transistor and the NMOS transistor of the first latch unit 101 are in a non-conducting state, and the data at the input terminal D cannot pass through the first latch unit 101 to the first node S0 To transmit, the first latch unit 101 latches the data transmitted to the first node S0 in the previous time period.
  • the first latch unit 101 uses a transmission gate structure as an example. Of course, it can also be other forms of analog switching units such as three-state inverters, as long as the switching function can be realized under the control of a clock signal. , the present invention is not limited to this.
  • the second latch unit 102 of the dynamic D flip-flop 100 is a three-state inverter structure.
  • the second latch unit 102 includes a first PMOS transistor 102P1 connected in series between the power supply VDD and the ground VSS. , the second PMOS transistor 102P2, the first NMOS transistor 102N1 and the second NMOS transistor 102N2.
  • the gate terminals of the first PMOS transistor 102P1 and the second NMOS transistor 102N2 are connected together, serving as the input terminal of the second latch unit 102, and are electrically connected to the first node S0.
  • the drain terminals of the second PMOS transistor 102P2 and the first NMOS transistor 102N1 are connected together to form the output terminal of the second latch unit 102 and are electrically connected to the second node S1.
  • the source terminal of the first PMOS transistor 102P1 is connected to the power supply VDD, and the source terminal of the second NMOS transistor 102N2 is connected to the ground VSS.
  • the gate terminal of the second PMOS transistor 102P2 is controlled by the clock signal CKN
  • the gate terminal of the first NMOS transistor 102N1 is controlled by the clock signal CKP, serving as the clock control terminal of the second latch unit 102
  • the gate terminal of the first PMOS transistor 102P1 can also be controlled by the clock signal CKN
  • the gate terminal of the second NMOS transistor 102N2 can be controlled by the clock signal CKP.
  • the gate terminals of the second PMOS transistor 102P2 and the first NMOS transistor 102N1 are connected together as the input terminal of the second latch unit 102 .
  • the present invention is not limited thereto.
  • CKP When CKP is high level, CKN is low level, the second PMOS transistor 102P2 and the first NMOS transistor 102N1 are both in the conductive state, and the second latch unit 102 inverts the data at the first node S0 and then forwards the data to the first node S0.
  • the two nodes S1 transmit and output the data to the output driving unit 103.
  • the output driving unit 103 then transmits the data to the output terminal Q to rewrite the data at the output terminal Q.
  • the output driving unit 103 of the dynamic D flip-flop 100 has an inverter structure, and the data received from the second latch unit 102 is inverted again to form data with the same phase as the data at the input terminal D, And output the data through the output terminal Q.
  • the output driving unit can also improve data driving capabilities.
  • Dynamic D flip-flop 100 also includes a data holding unit 104.
  • the data holding unit 104 includes a PMOS transistor 104P and an NMOS transistor 104N.
  • the PMOS transistor 104P and the NMOS transistor 104N are connected in parallel between the first node S0 and the second node S1.
  • the source terminal of the PMOS transistor 104P and the drain terminal of the NMOS transistor 104N are electrically connected in parallel to the second node S1
  • the drain terminal of the PMOS transistor 104P and the source terminal of the NMOS transistor 104N are electrically connected in parallel to the first node S0.
  • the gate terminal of the transistor 104P is electrically connected to the power supply VDD
  • the gate terminal of the NMOS transistor 104N is electrically connected to the ground VSS.
  • the data holding unit 104 Since the gate terminal of the PMOS transistor 104P in the data holding unit 104 is electrically connected to the power supply VDD, and the gate terminal of the NMOS transistor 104N is electrically connected to the ground VSS, driven by the high-level signal of the power supply VDD, the PMOS transistor 104P is in an off state. Driven by the low level signal of ground VSS, the NMOS transistor 104N is also in the off state.
  • the data holding unit 104 is equivalent to a capacitor, which is used to assist in storing the data latched at the first node S0, prolong the data holding time, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 can be used together as the data holding unit 104, or can be used as the data holding unit 104 respectively. That is to say, the data holding unit PMOS crystals can be included in 104
  • the transistor 104P and the NMOS transistor 104N may also include only the PMOS transistor 104P or the NMOS transistor 104N, and the present invention is not limited thereto.
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal of the PMOS transistor 104P is electrically connected to the first node or the second node.
  • the drain terminal of the PMOS transistor 104P is electrically connected to the second node or the first node. node, the gate terminal of the PMOS transistor 104P is electrically connected to a power supply.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal of the NMOS transistor 104N is electrically connected to the first node or the second node.
  • the drain terminal of the NMOS transistor 104N is electrically connected to the second node or the first node. node, the gate terminal of the NMOS transistor 104N is electrically connected to a ground.
  • FIG. 2 is a schematic circuit structure diagram of a dynamic D flip-flop according to another embodiment of the present invention.
  • the difference between the dynamic D flip-flop 100 shown in FIG. 2 and the embodiment shown in FIG. 1 lies in the structure of the data holding unit 104.
  • the data holding unit 104 includes a PMOS transistor 104P and an NMOS transistor 104N.
  • the PMOS transistor 104P and the NMOS transistor 104N are connected together in parallel.
  • the source terminal of the PMOS transistor 104P is electrically connected to the NMOS transistor 104N.
  • the source terminal of the PMOS transistor 104P is electrically connected to the first node S0, and the drain terminal of the PMOS transistor 104P is electrically connected to the drain terminal of the NMOS transistor 104N, and is electrically connected to the first node S0, the gate terminal of the PMOS transistor 104P and the NMOS transistor The gate terminals of 104N are connected together and electrically connected to the second node S1.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 are used as capacitors to assist in storing the data latched at the first node S0 and transmitted to the second node S1, extending the data retention time and improving the data retention time. Storage stability, thereby enhancing data security and accuracy.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 can be used together as the data holding unit 104, or can be used as the data holding unit 104 respectively. That is to say, the data holding unit 104 may include a PMOS transistor 104P and an NMOS transistor 104N, or may only include a PMOS transistor 104P or an NMOS transistor 104N. The invention is not limited thereto.
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the PMOS transistor 104P are electrically connected to the first node or the second node.
  • the gate of the PMOS transistor 104P The terminal is electrically connected to the second node or the first node.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the NMOS transistor 104N are electrically connected to the first node or the second node.
  • the gate terminal of the NMOS transistor 104N is electrically connected to the second node. or the first node.
  • FIG. 3 is a schematic circuit structure diagram of a dynamic D flip-flop according to another embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is that in this embodiment, the data holding unit 104 is only electrically connected to the first node S0.
  • the source terminal and the drain terminal of the PMOS transistor 104P are connected in parallel and electrically connected to the first node S0 , and the gate terminal of the PMOS transistor 104P is electrically connected to the power supply VDD.
  • the source terminal and the drain terminal of the NMOS transistor 104N are connected in parallel and electrically connected to the first node S0, and the gate terminal of the NMOS transistor 104N is electrically connected to the ground VSS.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 are respectively used as capacitors to assist in storing the data latched at the first node S0, extend the data holding time, improve the stability of data storage, and thereby enhance the Data security and accuracy.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 can be used together as the data holding unit 104, or can be used as the data holding unit 104 respectively. That is to say, the data holding unit 104 may include a PMOS transistor 104P and an NMOS transistor 104N, or may only include a PMOS transistor 104P or an NMOS transistor 104N. The invention is not limited thereto.
  • the data holding unit 104 may be provided at the first node S0 or the second node S1, or the data holding unit 104 may be provided at both the first node S0 and the second node S1.
  • the invention is not limited thereto. .
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the PMOS transistor 104P are electrically connected to the first node.
  • the gate terminal of the PMOS transistor 104P is electrically connected to a power supply.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the NMOS transistor 104N are electrically connected to the first node, and the gate terminal of the NMOS transistor 104N is electrically connected to a ground.
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the PMOS transistor 104P are electrically connected to the second node.
  • the gate terminal of the PMOS transistor 104P is electrically connected to a power supply.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the NMOS transistor 104N are electrically connected to the second node.
  • the gate terminal of the NMOS transistor 104N is electrically connected to a ground.
  • FIG. 4 is a schematic circuit structure diagram of a dynamic D flip-flop according to yet another embodiment of the present invention. The difference from the embodiment shown in FIG. 3 lies in the connection method of the data holding unit 104.
  • the source terminal and the drain terminal of the PMOS transistor 104P are connected in parallel and electrically connected to the power supply VDD, and the gate terminal of the PMOS transistor 104P is electrically connected to the first node S0 .
  • the source terminal and the drain terminal of the NMOS transistor 104N are connected in parallel and electrically connected to the ground VSS, and the gate terminal of the NMOS transistor 104N is electrically connected to the first node S0.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 are used as capacitors to assist in storing the data latched at the first node S0, extend the data holding time, improve the stability of data storage, and thereby enhance the data safety and accuracy.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 can be used together as the data holding unit 104, or can be used as the data holding unit 104 respectively. That is to say, the data holding unit 104 may include a PMOS transistor 104P and an NMOS transistor 104N, or may only include a PMOS transistor 104P or an NMOS transistor 104N. The invention is not limited thereto.
  • the data holding unit 104 may be provided at the first node S0 or the second node S1, or the data holding unit 104 may be provided at both the first node S0 and the second node S1.
  • the invention is not limited thereto. .
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the PMOS transistor 104P are electrically connected to a power supply.
  • the gate terminal of the PMOS transistor 104P is electrically connected to the first node.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the NMOS transistor 104N are electrically connected to a ground, and the gate terminal of the NMOS transistor 104N is electrically connected to the first node.
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the PMOS transistor 104P are electrically connected to a power supply.
  • the gate terminal of the PMOS transistor 104P is electrically connected to the second node.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal and the drain terminal of the NMOS transistor 104N are electrically connected to a ground, and the gate terminal of the NMOS transistor 104N is electrically connected to the second node.
  • FIG. 5 is a schematic circuit structure diagram of a dynamic D flip-flop according to an extended embodiment of the present invention. The difference from the embodiment shown in Figures 3 and 4 lies in the connection method of the data holding unit 104.
  • the source terminal and the gate terminal of the PMOS transistor 104P are connected in parallel and electrically connected to the power supply VDD, and the drain terminal of the PMOS transistor 104P is electrically connected to the first node S0 .
  • the source terminal and the gate terminal of the NMOS transistor 104N are connected in parallel and electrically connected to the ground VSS, and the drain terminal of the NMOS transistor 104N is electrically connected to the first node S0.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 are used as capacitors to assist in storing the data latched at the first node S0, extending the data holding time, improving the stability of data storage, and thereby enhancing the data safety and accuracy.
  • the PMOS transistor 104P and the NMOS transistor 104N in the data holding unit 104 can be used together as the data holding unit 104, or can be used as the data holding unit 104 respectively. That is to say, the data holding unit 104 may include a PMOS transistor 104P and an NMOS transistor 104N, or may only include a PMOS transistor 104P or an NMOS transistor 104N. The invention is not limited thereto.
  • the data holding unit 104 may be provided at the first node S0 or the second node S1, or the data holding unit 104 may be provided at both the first node S0 and the second node S1.
  • the invention is not limited thereto. .
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal (or drain terminal) and gate terminal of the PMOS transistor 104P are electrically connected to a power supply.
  • the drain terminal (or source terminal) of the PMOS transistor 104P is electrically connected to a power supply. Connect to the first node.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal (or drain terminal) and gate terminal of the NMOS transistor 104N are electrically connected to a ground.
  • the drain terminal (or source terminal) of the NMOS transistor 104N is electrically connected to a ground. Connect to the first node.
  • the PMOS transistor 104P has a source terminal, a drain terminal and a gate terminal.
  • the source terminal (or drain terminal) and gate terminal of the PMOS transistor 104P are electrically connected to a power supply.
  • the drain terminal (or source terminal) of the PMOS transistor 104P is electrically connected to a power supply. Connect to the second node.
  • the NMOS transistor 104N has a source terminal, a drain terminal and a gate terminal.
  • the source terminal (or drain terminal) and gate terminal of the NMOS transistor 104N are electrically connected to a ground.
  • the drain terminal (or source terminal) of the NMOS transistor 104N is electrically connected to a ground. Connect to the second node.
  • connection method of a PMOS transistor and an NMOS transistor is used as an explanation.
  • the source and drain electrodes of the PMOS transistor and the NMOS transistor can be interchanged.
  • the present invention is not limited to this.
  • the present invention also provides a data operation unit.
  • Figure 6 is a schematic structural diagram of the data operation unit of the present invention.
  • the data operation unit 800 includes a control circuit 801 , an operation circuit 802 and a plurality of dynamic D flip-flops 100 , and the plurality of dynamic D flip-flops 100 are connected in series or in parallel.
  • the control circuit 801 refreshes the data in the dynamic D flip-flop 100 and reads the data from the dynamic D flip-flop 100.
  • the operation circuit 802 performs operation on the read data, and then the control circuit 801 outputs the operation result.
  • FIG. 7 is a schematic structural diagram of the chip of the present invention.
  • the chip 900 includes a control unit 901 and one or more data operation units 800 .
  • the control unit 901 inputs data to the data operation unit 800 and processes the data output by the data operation unit 800.
  • the present invention also provides a hashrate board.
  • Figure 8 is a schematic structural diagram of the hashrate board of the present invention. As shown in Figure 8, each computing board 1000 includes one or more chips 900, which perform large-scale operations on work data delivered by the computing device.
  • each computing device 1100 includes a connection board 1101 , a control board 1102 , a heat sink 1103 , a power board 1104 , and one or more computing boards 1000 .
  • the control board 1102 is connected to the hash board 1000 through the connection board 1101, and the heat sink 1103 is arranged around the hash board 1000.
  • the power board 1104 is used to provide power to the connection board 1101, the control board 1102, the heat sink 1103 and the computing board 1000.
  • orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operations and therefore should not be construed as limitations of the invention.
  • the present invention can also have various other embodiments.
  • those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and deformations should fall within the protection scope of the appended claims of the present invention.
  • the dynamic D trigger provided by the present invention can assist in storing data locked at the node, extend the data retention time, improve the stability of data storage, and thereby enhance the security and accuracy of the data.

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Abstract

本发明提供一种动态D触发器（100），包括一输入端（D），一输出端（Q），一时钟信号端（CLK1、CLK2），一第一锁存单元（101），一第二锁存单元（102），一输出驱动单元（103）；所述第一锁存单元（101）、所述第二锁存单元（102）以及所述输出驱动单元（103）依次串接在所述输入端（D）和所述输出端（Q）之间；所述第一锁存单元（101）与所述第二锁存单元（102）之间具有一第一节点（S0），所述第二锁存单元（102）与所述输出驱动单元（103）之间具有一第二节点（S1）；其中，还包括一数据保持单元（104），所述数据保持单元（104）电性连接至所述第一节点（S0）和/或所述第二节点（S1）。可以有效增加数据的保持时间，提高数据的安全性和正确率。

Description

动态D触发器、数据运算单元、芯片、算力板及计算设备 技术领域
本发明涉及一种受时钟控制的存储器件，尤其涉及一种在大规模数据运算设备中应用的寄存器、运算单元、芯片及计算设备。
背景技术
动态触发器应用非常广泛，可用做数字信号的寄存。现有动态触发器中，所传输的数据通常暂存在构成锁存单元的晶体管所产生的寄生电容中。但是，由于运算频率逐渐提高，暂存的数据容易产生动态漏电，导致数据维持时间不够，进而导致数据丢失并降低运算正确率。
因此，如何有效提高动态触发器中数据的维持时间实为需要解决的问题。
发明公开
为了解决上述问题，本发明提供一种动态D触发器，可以有效增加数据的保持时间，提高数据的安全性和正确率。
为了实现上述目的，本发明提供一种动态D触发器，包括一输入端，用于输入一第一数据；一输出端，用于输出一第二数据；一时钟信号端，用于提供时钟信号；一第一锁存单元，用于传输所述输入端的数据并在时钟信号控制下锁存所述第一数据；一第二锁存单元，用于锁存所述第一锁存单元所传输的数据；一输出驱动单元，用于输出从所述第二锁存单元接收到的数据；所述第一锁存单元、所述第二锁存单元以及所述输出驱动单元依次串接在所述输入端和所述输出端之间；所述第一锁存单元与所述第二锁存单元之间具有一第一节点，所述第二锁存单元与所述输出驱动单元之间具有一第二节点；其中，还包括一数据保持单元，所述数据保持单元电性连接至所述第一节点和/或所述第二节点，所述数据保持单元用于辅助存储被锁存在所述第一节点和/或所述第二节点处的数据。
上述的动态D触发器，其中，所述数据保持单元具有一第一端以及一第二端，所述数据保持单元的第一端电性连接至所述第一节点，所述数据保持单元的第二端电性连接至所述第二节点。
上述的动态D触发器，其中，所述数据保持单元包括一PMOS晶体管和/或一NMOS晶体管。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端电性连接至所述第一节点或所述第二节点，所述PMOS晶体管的漏极端电性连接至所述第二节点或所述第一节点，所述PMOS晶体管的栅极端电性连接至一电源。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端电性连接至所述第一节点或所述第二节点，所述NMOS晶体管的漏极端电性连接至所述第二节点或所述第一节点，所述NMOS晶体管的栅极端电性连接至一地。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第一节点或所述第二节点，所述PMOS晶体管的栅极端电性连接至所述第二节点或所述第一节点。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第一节点或所述第二节点，所述NMOS晶体管的栅极端电性连接至所述第二节点或所述第一节点。
上述的动态D触发器，其中，所述数据保持单元电性连接至所述第一节点或所述第二节点，所述数据保持单元包括一PMOS晶体管和/或一NMOS晶体管。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第一节点，所述PMOS晶体管的栅极端电性连接至一电源。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第一节点，所述NMOS晶体管的栅极端电性连接至一地。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至一电源，所述PMOS晶体管的栅极端电性连接至所述第一节点。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端 及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至一地，所述NMOS晶体管的栅极端电性连接至所述第一节点。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及栅极端电性连接至一电源，所述PMOS晶体管的漏极端电性连接至所述第一节点。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及栅极端电性连接至一地，所述NMOS晶体管的漏极端电性连接至所述第一节点。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第二节点，所述PMOS晶体管的栅极端电性连接至一电源。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第二节点，所述NMOS晶体管的栅极端电性连接至一地。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至一电源，所述PMOS晶体管的栅极端电性连接至所述第二节点。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至一地，所述NMOS晶体管的栅极端电性连接至所述第二节点。
上述的动态D触发器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及栅极端电性连接至一电源，所述PMOS晶体管的漏极端电性连接至所述第二节点。
上述的动态D触发器，其中，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及栅极端电性连接至一地，所述NMOS晶体管的漏极端电性连接至所述第二节点。
上述的动态D触发器，其中，所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。
上述的动态D触发器，其中，所述第一锁存单元为传输门。
上述的动态D触发器，其中，所述传输门包括并联连接的一PMOS晶体管 以及一NMOS晶体管，PMOS晶体管的栅极端电性连接至所述第一时钟信号，所述NMOS晶体管的栅极端电性连接至所述第二时钟信号。
上述的动态D触发器，其中，所述第二锁存单元为三态反相器。
上述的动态D触发器，其中，所述三态反相器包括串联连接的一第一PMOS晶体管、一第二PMOS晶体管、一第一NMOS晶体管以及一第二NMOS晶体管，其中所述第一PMOS晶体管和所述第二NMOS晶体管的栅极端电性连接作为所述三态反相器的输入端，所述第二PMOS晶体管的栅极端电性连接至所述第二时钟信号，所述第一NMOS晶体管的栅极端电性连接至所述第一时钟信号。
上述的动态D触发器，其中，所述输出驱动单元为反相器。
上述的动态D触发器，其中，所述反相器包括串联连接的一PMOS晶体管以及一NMOS晶体管。
使用本发明的动态D触发器，可以有效增加数据的保持时间，提高数据的安全性和正确率。
为了更好地实现上述目的，本发明还提供了一种数据运算单元，包括互联连接的控制电路、运算电路、多个动态D触发器，所述多个动态D触发器为串联和/或并联连接；其中，所述多个动态D触发器为任意一种上述的动态D触发器。
为了更好地实现上述目的，本发明还提供了一种芯片，其中，包括至少一个如上所述的数据运算单元。
为了更好地实现上述目的，本发明还提供了一种用于计算设备的算力板，其中，包括至少一个如上所述的芯片。
为了更好地实现上述目的，本发明还提供了一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其特征在于：所述算力板为如上所述的算力板。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1为本发明一实施例动态D触发器的电路结构示意图；
图2为本发明又一实施例动态D触发器的电路结构示意图；
图3为本发明另一实施例动态D触发器的电路结构示意图；
图4为本发明再一实施例动态D触发器的电路结构示意图；
图5为本发明一拓展实施例动态D触发器的电路结构示意图；
图6为本发明数据运算单元的结构示意图；
图7为本发明芯片的结构示意图；
图8为本发明算力板的结构示意图；
图9为本发明计算设备的结构示意图。
其中，附图标记：
100：动态D触发器
101：第一锁存单元
102：第二锁存单元
102P1：第一PMOS晶体管
102P2：第二PMOS晶体管
102N1：第一NMOS晶体管
102N2：第二NMOS晶体管
103：输出驱动单元
104：数据保持单元
104P：PMOS晶体管
104N：NMOS晶体管
800：数据运算单元
801：控制电路
802：运算电路
900：芯片
901：控制单元
1000：算力板
1100：计算设备
1101：连接板
1102：控制板
1103：散热器
1104：电源板
D：输入端
Q：输出端
CLK1：第一时钟信号端
CLK2：第二时钟信号端
CKP、CKN：时钟信号
S0：第一节点
S1：第二节点
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。
在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此为包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
实施例一：
图1为本发明一实施例动态D触发器的电路结构示意图。如图1所示，动态D触发器100包括输入端D、输出端Q、第一时钟信号端CLK1、第二时钟信号端CLK2、第一锁存单元101、第二锁存单元102、输出驱动单元103以及数据保持单元104。第一锁存单元101、第二锁存单元102以及输出驱动单元103依次串联连接在输入端D和输出端Q之间，第一锁存单元101和第二锁存单元102之间形成第一节点S0，第二锁存单元102和输出驱动单元103之间形成第二节点S1。数据保持单元104电性连接在第一节点S0以及第二节点S1之间。其中，动态D触发器100的输入端D用于从外部向动态D触发器100输入所需要的传输的数据，输出端Q用于从动态D触发器100向外部输出所需要传输的数据，第一时钟信号端CLK1以及第二时钟信号端CLK2用于向动态D触发 器100提供时钟控制信号，时钟控制信号包括时钟信号CKP以及时钟信号CKN，以控制第一锁存单元101及第二锁存单元102的导通与关闭。其中，时钟信号CKN与时钟信号CKP为反相时钟信号，且第一锁存单元101及第二锁存单元102不会同时导通或关闭。
具体的，如图1所示，动态D触发器100的第一锁存单元101为传输门结构，第一锁存单元101包括并联连接的PMOS晶体管以及NMOS晶体管。其中，第一锁存单元101的一端电性连接至输入端D，第一锁存单元101的另一端电性连接至第一节点S0。第一锁存单元101的NMOS晶体管的栅极端电性连接至时钟信号CKN，PMOS晶体管的栅极端电性连接至时钟信号CKP。当CKP为低电平时，CKN为高电平，第一锁存单元101的PMOS晶体管与NMOS晶体管均为导通状态，输入端D将所要传输的数据通过第一锁存单元101传送至第一节点S0。当CKP为高电平时，CKN为低电平，第一锁存单元101的PMOS晶体管与NMOS晶体管均为不导通状态，输入端D的数据不能通过第一锁存单元101向第一节点S0进行传送，第一锁存单元101将上一时间周期所传送至第一节点S0的数据进行锁存。在本实施例中，第一锁存单元101以传输门结构进行举例，当然，也可以是其他形式的模拟开关单元如三态反相器，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。
继续参照图1所示，动态D触发器100的第二锁存单元102为三态反相器结构，第二锁存单元102包括串联连接在电源VDD以及地VSS之间的第一PMOS晶体管102P1、第二PMOS晶体管102P2、第一NMOS晶体管102N1以及第二NMOS晶体管102N2。其中第一PMOS晶体管102P1和第二NMOS晶体管102N2的栅极端连接在一起，作为第二锁存单元102的输入端，并电性连接至第一节点S0。第二PMOS晶体管102P2和第一NMOS晶体管102N1的漏极端连接在一起，形成第二锁存单元102的输出端，并电性连接至第二节点S1。第一PMOS晶体管102P1的源极端连接到电源VDD，第二NMOS晶体管102N2的源极端连接到地VSS。
在本实施例中，第二PMOS晶体管102P2的栅极端受时钟信号CKN的控制，第一NMOS晶体管102N1的栅极端受时钟信号CKP的控制，作为第二锁存单元102的时钟控制端。当然，也可以是第一PMOS晶体管102P1的栅极端受时钟信号CKN的控制，第二NMOS晶体管102N2的栅极端受时钟信号CKP的控制， 第二PMOS晶体管102P2与第一NMOS晶体管102N1的栅极端连接在一起作为第二锁存单元102的输入端。本发明并不以此为限。
具体的，如图1所示，当CKP为低电平时，CKN为高电平，第二PMOS晶体管102P2与第一NMOS晶体管102N1均为不导通状态，第二锁存单元102呈高阻状态，第一节点S0处的数据不能通过第二锁存单元102向第二节点S1处传输，第一节点S0处的数据被锁存，保持原来的状态，起到数据寄存的作用。
当CKP为高电平时，CKN为低电平，第二PMOS晶体管102P2与第一NMOS晶体管102N1均为导通状态，第二锁存单元102将第一节点S0处所数据的数据反相后向第二节点S1传输，并将数据输出到输出驱动单元103，输出驱动单元103再将数据传输至输出端Q，以改写输出端Q的数据。
如图1所示，动态D触发器100的输出驱动单元103为反相器结构，将从第二锁存单元102接收的数据再次反相，以形成与输入端D的数据相同相位的数据，并将数据通过输出端Q将数据输出。同时，输出驱动单元还能够提高数据的驱动能力。
动态D触发器100还包括数据保持单元104。在本实施例中，数据保持单元104包括PMOS晶体管104P以及NMOS晶体管104N，PMOS晶体管104P以及NMOS晶体管104N并联连接在第一节点S0与第二节点S1之间。具体的，PMOS晶体管104P的源极端与NMOS晶体管104N的漏极端并联电性连接至第二节点S1，PMOS晶体管104P的漏极端与NMOS晶体管104N的源极端并联电性连接至第一节点S0，PMOS晶体管104P的栅极端电性连接至电源VDD，NMOS晶体管104N的栅极端电性连接至地VSS。
由于数据保持单元104中PMOS晶体管104P的栅极端电性连接至电源VDD，NMOS晶体管104N的栅极端电性连接至地VSS，在电源VDD的高电平信号驱动下，PMOS晶体管104P处于截止状态，在地VSS的低电平信号驱动下，NMOS晶体管104N同样处于截止状态。此时，数据保持单元104相当于一电容，用于辅助存储被锁存在第一节点S0处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。
需要说明的是，于本发明中，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N既可以共同作为数据保持单元104使用，也可以分别作为数据保持单元104使用，也就是说，数据保持单元104中可以包括PMOS晶体 管104P以及NMOS晶体管104N，也可以只包括PMOS晶体管104P或者NMOS晶体管104N，本发明并不以此为限。
作为示例：
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端电性连接至第一节点或第二节点，PMOS晶体管104P的漏极端电性连接至第二节点或第一节点，PMOS晶体管104P的栅极端电性连接至一电源。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端电性连接至第一节点或第二节点，NMOS晶体管104N的漏极端电性连接至第二节点或第一节点，NMOS晶体管104N的栅极端电性连接至一地。
实施例二：
图2为本发明又一实施例动态D触发器的电路结构示意图。图2所示动态D触发器100与图1所示实施例不同之处在于数据保持单元104的结构。如图2所示，在本实施例中，数据保持单元104包括PMOS晶体管104P以及NMOS晶体管104N，PMOS晶体管104P以及NMOS晶体管104N并联连接在一起，PMOS晶体管104P的源极端电性连接至NMOS晶体管104N的源极端，并电性连接至第一节点S0，PMOS晶体管104P的漏极端电性连接至NMOS晶体管104N的漏极端，并电性连接至第一节点S0，PMOS晶体管104P的栅极端以及NMOS晶体管104N的栅极端连接在一起，并电性连接至第二节点S1。
同样的，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N作为电容使用，用于辅助存储被锁存在第一节点S0处以及传输至第二节点S1处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。
需要说明的是，于本发明中，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N既可以共同作为数据保持单元104使用，也可以分别作为数据保持单元104使用，也就是说，数据保持单元104中可以包括PMOS晶体管104P以及NMOS晶体管104N，也可以只包括PMOS晶体管104P或者NMOS晶体管104N，本发明并不以此为限。
作为示例：
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端及漏极端电性连接至第一节点或第二节点，PMOS晶体管104P的栅极 端电性连接至第二节点或第一节点。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端及漏极端电性连接至第一节点或第二节点，NMOS晶体管104N的栅极端电性连接至第二节点或第一节点。
变形例：
图3为本发明另一实施例动态D触发器的电路结构示意图。与图1所示实施例不同之处在于，在本实施例中，数据保持单元104仅仅电性连接至第一节点S0。
如图3所示，在本实施例中，PMOS晶体管104P的源极端和漏极端并联连接并电性连接至第一节点S0，PMOS晶体管104P的栅极端电性连接至电源VDD。NMOS晶体管104N的源极端和漏极端并联连接并电性连接至第一节点S0，NMOS晶体管104N的栅极端电性连接至地VSS。
同样的，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N分别作为电容使用，用于辅助存储被锁存在第一节点S0处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。
需要说明的是，于本发明中，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N既可以共同作为数据保持单元104使用，也可以分别作为数据保持单元104使用，也就是说，数据保持单元104中可以包括PMOS晶体管104P以及NMOS晶体管104N，也可以只包括PMOS晶体管104P或者NMOS晶体管104N，本发明并不以此为限。
当然，数据保持单元104可以设置于第一节点S0，也可以设置于第二节点S1，或者，在第一节点S0以及第二节点S1均设置数据保持单元104，本发明并不以此为限。
作为示例：
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端及漏极端电性连接至第一节点，PMOS晶体管104P的栅极端电性连接至一电源。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端及漏极端电性连接至第一节点，NMOS晶体管104N的栅极端电性连接至一地。
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端及漏极端电性连接至第二节点，PMOS晶体管104P的栅极端电性连接至一电源。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端及漏极端电性连接至第二节点，NMOS晶体管104N的栅极端电性连接至一地。
图4为本发明再一实施例动态D触发器的电路结构示意图。与图3所示实施例不同之处在于数据保持单元104的连接方式不同。如图4所示，在本实施例中，PMOS晶体管104P的源极端和漏极端并联连接并电性连接至电源VDD，PMOS晶体管104P的栅极端电性连接至第一节点S0。NMOS晶体管104N的源极端和漏极端并联连接并电性连接至地VSS，NMOS晶体管104N的栅极端电性连接至第一节点S0。
同样的，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N作为电容使用，用于辅助存储被锁存在第一节点S0处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。
需要说明的是，于本发明中，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N既可以共同作为数据保持单元104使用，也可以分别作为数据保持单元104使用，也就是说，数据保持单元104中可以包括PMOS晶体管104P以及NMOS晶体管104N，也可以只包括PMOS晶体管104P或者NMOS晶体管104N，本发明并不以此为限。
当然，数据保持单元104可以设置于第一节点S0，也可以设置于第二节点S1，或者，在第一节点S0以及第二节点S1均设置数据保持单元104，本发明并不以此为限。
作为示例：
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端及漏极端电性连接至一电源，PMOS晶体管104P的栅极端电性连接至第一节点。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端及漏极端电性连接至一地，NMOS晶体管104N的栅极端电性连接至第一节点。
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端及漏极端电性连接至一电源，PMOS晶体管104P的栅极端电性连接至第二节点。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端及漏极端电性连接至一地，NMOS晶体管104N的栅极端电性连接至第二节点。
图5为本发明一拓展实施例动态D触发器的电路结构示意图。与图3、图4所示实施例不同之处在于数据保持单元104的连接方式不同。如图5所示，在本实施例中，PMOS晶体管104P的源极端和栅极端并联连接并电性连接至电源VDD，PMOS晶体管104P的漏极端电性连接至第一节点S0。NMOS晶体管104N的源极端和栅极端并联连接并电性连接至地VSS，NMOS晶体管104N的漏极端电性连接至第一节点S0。
同样的，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N作为电容使用，用于辅助存储被锁存在第一节点S0处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。
需要说明的是，于本发明中，数据保持单元104中的PMOS晶体管104P以及NMOS晶体管104N既可以共同作为数据保持单元104使用，也可以分别作为数据保持单元104使用，也就是说，数据保持单元104中可以包括PMOS晶体管104P以及NMOS晶体管104N，也可以只包括PMOS晶体管104P或者NMOS晶体管104N，本发明并不以此为限。
当然，数据保持单元104可以设置于第一节点S0，也可以设置于第二节点S1，或者，在第一节点S0以及第二节点S1均设置数据保持单元104，本发明并不以此为限。
作为示例：
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端(或漏极端)及栅极端电性连接至一电源，PMOS晶体管104P的漏极端(或源极端)电性连接至第一节点。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端(或漏极端)及栅极端电性连接至一地，NMOS晶体管104N的漏极端(或源极端)电性连接至第一节点。
PMOS晶体管104P具有一源极端、一漏极端及一栅极端，PMOS晶体管104P的源极端(或漏极端)及栅极端电性连接至一电源，PMOS晶体管104P的漏极端(或源极端)电性连接至第二节点。
NMOS晶体管104N具有一源极端、一漏极端及一栅极端，NMOS晶体管104N的源极端(或漏极端)及栅极端电性连接至一地，NMOS晶体管104N的漏极端(或源极端)电性连接至第二节点。
以上实施例中，均以PMOS晶体管、NMOS晶体管的一种连接方式作为说明，其中，PMOS晶体管、NMOS晶体管中的源极和漏极可以互换，本发明并不以此为限。
本发明还提供一种数据运算单元，图6为本发明数据运算单元的结构示意图。如图6所示，数据运算单元800包括控制电路801、运算电路802以及多个动态D触发器100，多个动态D触发器100之间串联或并联连接。控制电路801对动态D触发器100中的数据进行刷新并从动态D触发器100中读取数据，运算电路802对读取的数据进行运算，再由控制电路801将运算结果输出。
本发明还提供一种芯片，图7为本发明芯片的结构示意图。如图7所示，芯片900包括控制单元901，以及一个或多个数据运算单元800。控制单元901向数据运算单元800输入数据并将数据运算单元800输出的数据进行处理。
本发明还提供一种算力板，图8为本发明算力板的结构示意图。如图8所示，每一个算力板1000上包括一个或多个芯片900，对计算设备下发的工作数据进行大规模运算。
本发明还提供一种计算设备，所述计算设备优选用于挖掘虚拟数字货币的运算，当然所述计算设备也可以用于其他任何海量运算。图9为本发明计算设备的结构示意图。如图9所示，每一个计算设备1100包括连接板1101、控制板1102、散热器1103、电源板1104，以及一个或多个算力板1000。控制板1102通过连接板1101与算力板1000连接，散热器1103设置在算力板1000的周围。电源板1104用于向连接板1101、控制板1102、散热器1103以及算力板1000提供电源。
需要说明的是，在本发明的描述中，术语“横向”、“纵向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的 方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，并不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
换言之，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的动态D触发器，具有以下有益效果：
本发明提供的动态D触发器，能够辅助存储被锁存在节点处的数据，延长数据保持时间，提高数据存储的稳定性，进而增强数据的安全性和正确率。

Claims (31)

  1. 一种动态D触发器，其特征在于，包括：
    一输入端，用于输入一第一数据；
    一输出端，用于输出一第二数据；
    一时钟信号端，用于提供时钟信号；
    一第一锁存单元，用于传输所述输入端的数据并在时钟信号控制下锁存所述第一数据；
    一第二锁存单元，用于锁存所述第一锁存单元所传输的数据；
    一输出驱动单元，用于输出从所述第二锁存单元接收到的数据；
    所述第一锁存单元、所述第二锁存单元以及所述输出驱动单元依次串接在所述输入端和所述输出端之间；
    所述第一锁存单元与所述第二锁存单元之间具有一第一节点，所述第二锁存单元与所述输出驱动单元之间具有一第二节点；
    其中，还包括一数据保持单元，所述数据保持单元电性连接至所述第一节点和/或所述第二节点，所述数据保持单元用于辅助存储被锁存在所述第一节点和/或所述第二节点处的数据。
  2. 如权利要求1所述的动态D触发器，其特征在于：所述数据保持单元具有一第一端以及一第二端，所述数据保持单元的第一端电性连接至所述第一节点，所述数据保持单元的第二端电性连接至所述第二节点。
  3. 如权利要求2所述的动态D触发器，其特征在于：所述数据保持单元包括一PMOS晶体管和/或一NMOS晶体管。
  4. 如权利要求3所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端电性连接至所述第一节点或所述第二节点，所述PMOS晶体管的漏极端电性连接至所述第二节点或所述第一节点，所述PMOS晶体管的栅极端电性连接至一电源。
  5. 如权利要求3所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端电性连接至所述第一节点或所述第二节点，所述NMOS晶体管的漏极端电性连接至所述第二节点或所述第一节点，所述NMOS晶体管的栅极端电性连接至一地。
  6. 如权利要求3所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第一节点或所述第二节点，所述PMOS晶体管的栅极端电性连接至所述第二节点或所述第一节点。
  7. 如权利要求3所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第一节点或所述第二节点，所述NMOS晶体管的栅极端电性连接至所述第二节点或所述第一节点。
  8. 如权利要求1所述的动态D触发器，其特征在于：所述数据保持单元电性连接至所述第一节点或所述第二节点，所述数据保持单元包括一PMOS晶体管和/或一NMOS晶体管。
  9. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第一节点，所述PMOS晶体管的栅极端电性连接至一电源。
  10. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第一节点，所述NMOS晶体管的栅极端电性连接至一地。
  11. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至一电源，所述PMOS晶体管的栅极端电性连接至所述第一节点。
  12. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至一地，所述NMOS晶体管的栅极端电性连接至所述第一节点。
  13. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及栅极端电性连接至一电源，所述PMOS晶体管的漏极端电性连接至所述第一节点。
  14. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及栅极端电性连接至一地，所述NMOS晶体管的漏极端电性连接至所述第一节点。
  15. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管 具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至所述第二节点，所述PMOS晶体管的栅极端电性连接至一电源。
  16. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至所述第二节点，所述NMOS晶体管的栅极端电性连接至一地。
  17. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及漏极端电性连接至一电源，所述PMOS晶体管的栅极端电性连接至所述第二节点。
  18. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及漏极端电性连接至一地，所述NMOS晶体管的栅极端电性连接至所述第二节点。
  19. 如权利要求8所述的动态D触发器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的源极端及栅极端电性连接至一电源，所述PMOS晶体管的漏极端电性连接至所述第二节点。
  20. 如权利要求8所述的动态D触发器，其特征在于：所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的源极端及栅极端电性连接至一地，所述NMOS晶体管的漏极端电性连接至所述第二节点。
  21. 如权利要求1所述的动态D触发器，其特征在于：所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。
  22. 如权利要求21所述的动态D触发器，其特征在于：所述第一锁存单元为传输门。
  23. 如权利要求22所述的动态D触发器，其特征在于：所述传输门包括并联连接的一PMOS晶体管以及一NMOS晶体管，PMOS晶体管的栅极端电性连接至所述第一时钟信号，所述NMOS晶体管的栅极端电性连接至所述第二时钟信号。
  24. 如权利要求21所述的动态D触发器，其特征在于：所述第二锁存单元为三态反相器。
  25. 如权利要求24所述的动态D触发器，其特征在于：所述三态反相器包括串联连接的一第一PMOS晶体管、一第二PMOS晶体管、一第一NMOS晶体 管以及一第二NMOS晶体管，其中所述第一PMOS晶体管和所述第二NMOS晶体管的栅极端电性连接作为所述三态反相器的输入端，所述第二PMOS晶体管的栅极端电性连接至所述第二时钟信号，所述第一NMOS晶体管的栅极端电性连接至所述第一时钟信号。
  26. 如权利要求1所述的动态D触发器，其特征在于：所述输出驱动单元为反相器。
  27. 如权利要求26所述的动态D触发器，其特征在于：所述反相器包括串联连接的一PMOS晶体管以及一NMOS晶体管。
  28. 一种数据运算单元，包括互联连接的控制电路、运算电路、多个动态D触发器，所述多个动态D触发器为串联和/或并联连接；其特征在于：所述多个动态D触发器为权利要求1-27中任意一种所述的动态D触发器。
  29. 一种芯片，其特征在于，包括至少一个如权利要求28所述的数据运算单元。
  30. 一种用于计算设备的算力板，其特征在于，包括至少一个如权利要求29所述的芯片。
  31. 一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其特征在于：所述算力板为如权利要求30所述的算力板。
PCT/CN2023/093277 2022-07-14 2023-05-10 动态d触发器、数据运算单元、芯片、算力板及计算设备 WO2024012032A1 (zh)

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