WO2024008186A1 - 高速链路最坏电源噪声求解方法、系统及存储介质 - Google Patents

高速链路最坏电源噪声求解方法、系统及存储介质 Download PDF

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WO2024008186A1
WO2024008186A1 PCT/CN2023/106368 CN2023106368W WO2024008186A1 WO 2024008186 A1 WO2024008186 A1 WO 2024008186A1 CN 2023106368 W CN2023106368 W CN 2023106368W WO 2024008186 A1 WO2024008186 A1 WO 2024008186A1
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power supply
supply noise
data template
period
switching current
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PCT/CN2023/106368
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English (en)
French (fr)
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蒲菠
何秋森
范峻
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宁波德图科技有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation

Definitions

  • the present invention relates to the field of integrated circuits and systems, and in particular to a method for solving the worst-case power supply noise of a high-speed link, a computer-readable storage medium for executing steps in the method for solving the worst-case power supply noise of a high-speed link, and A system for solving the worst-case power supply noise of high-speed links.
  • SSN Simultaneous Switch Noise
  • N refers to the number of simultaneous switches, that is, when N buffer drivers in the chip switch states at the same time, the current flowing through the loop parasitic inductance L loop (the current loop inductance on the power supply ground plane) will expand N times.
  • i refers to the current drawn when a single transistor switches state; the current generated when multiple transistors switch simultaneously is called simultaneous switching current.
  • noise will be generated on the power ground plane or power rail, so it is also called power supply noise.
  • Power supply noise will be coupled into the signal line and manifested at the output end of the driver, causing noise and jitter in the output waveform.
  • This invention is aimed at the power supply noise on the chip packaging level PDN, that is, the power supply ground in the package Noise on the plane.
  • the traditional approach is to obtain the target impedance of the PDN through frequency domain simulation, and use the impedance curve Z PDN (f) to find the worst-case data template, that is, to find the resonant frequency of the PDN. If the PDN has A resonance point requires multiple simulations of the entire link, and then a data template with a strong PDN resonance frequency is used as an excitation input to the driver to obtain the worst power supply noise.
  • this mechanism of finding the worst data template is only applicable to the PDN structure where the current changes linearly with the impedance, and cannot be applied to the nonlinear Z PDN (f) curve and I PDN (f) spectral component PDN structure.
  • V(j ⁇ ) I(j ⁇ )Z(j ⁇ ) (2)
  • Formula (2) explains this phenomenon from the frequency domain perspective.
  • Z(j ⁇ ) is the impedance frequency function of PDN
  • I(j ⁇ ) is the frequency function of PDN current.
  • V(j ⁇ ) frequency domain power supply noise
  • Z(j ⁇ ) changes over time
  • I(j ⁇ ) depends on the state activity in the system and can be time-varying and non-periodic stationary, that is, when the state activity changes over time, (such as the data template before the driver) changes, the spectrum of I(j ⁇ ) will change as the data template changes, as shown in Figure 1.
  • the impedance curve Z PDN (f) can only reflect the characteristics of the PDN impedance at different frequencies, and cannot reflect the characteristics of the current in the frequency domain. Only when the spectral component of the PDN output current I(j ⁇ ) in the impedance frequency band is large, will it The largest amplitude of power supply noise occurs. Therefore, it is not accurate enough to obtain the worst data template based only on the impedance information and resonance frequency in the frequency domain.
  • Figure 2a is the model structure of PDN, and the model is given in the form of S parameters.
  • 1, 2, 3, 4, and 5 are chip ports, connected to the chip's decoupling capacitor.
  • the on-chip decoupling capacitor is 20.8nf, and its parasitic resistance is 0.0015 ohms. Adding a constant sine wave current source with an amplitude of 1A at port 1 can obtain the PDN impedance curve as shown in Figure 2b.
  • the PDN impedance is different at different frequencies. Due to the interaction between the package inductance in the PDN and the on-chip decoupling capacitor, the PDN resonates at 233MHz.
  • Figure 3 describes the simulated full-link model, including PDN, PCB, packaging, driver and receiver models. Input data templates of different frequencies to the driver, and obtain the time domain power supply noise simulation results as shown in Table 1.
  • the data template of the worst power supply noise is not necessarily at the resonant frequency of the PDN, but depends on the joint action of the current spectrum and the impedance spectrum.
  • the technical problem to be solved by the present invention is to provide a method for solving the worst power supply noise of a high-speed link that can quickly obtain the worst power supply noise based on the modeling frequency sweep method, and a method for executing the worst power supply noise of the high-speed link.
  • the present invention provides a method for solving the worst power supply noise of high-speed links, which includes the following steps:
  • S3, omit the channel link structure, directly use the simultaneous switching current as the input of the PDN, scan the simultaneous switching current at the frequency of the data template, and obtain multiple sets of power supply noise with different amplitudes;
  • the frequency of the simultaneous switching current is the frequency of the worst case data template of the power supply noise.
  • the method for solving the worst power supply noise of a high-speed link is further improved, and the data template is a square wave signal type data template with a duty cycle of 50%.
  • I pt is a forward period triangular pulse, the period is the same as the period of the added data template, the rise time of the triangular pulse is equal to T pr , and the fall time is equal to T pf ;
  • I nt is a negative periodic triangular pulse.
  • the period is the same as the period of the added data template.
  • the delay time is half a period.
  • the rise time of the triangular pulse is equal to T nr and the fall time is equal to T nf ;
  • I dc is the direct current
  • the present invention provides a computer-readable storage medium for executing the steps in any one of the above high-speed link worst power supply noise solving methods.
  • the present invention provides a high-speed link worst-case power supply noise solution system, which includes:
  • the driver module inputs the data template at the specified frequency before the driver
  • the calculation module obtains all relevant data templates based on the clock frequency
  • the modeling module obtains the simultaneous switching current waveform profile based on a full-link simulation and approximates the simultaneous switching current
  • the noise acquisition module omits the channel link structure, directly uses the simultaneous switching current as the input of the PDN, scans the simultaneous switching current at the frequency of the data template, and obtains multiple sets of power supply noise with different amplitudes;
  • Frequency acquisition module which is used to acquire the worst-case power supply noise and its corresponding simultaneous switching current.
  • the high-speed link worst power supply noise solution system is further improved, and the data template is a square wave signal type data template with a duty cycle of 50%.
  • the modeling module's approximate modeling of simultaneous switching currents includes:
  • I pt is a forward period triangular pulse, the period is the same as the period of the added data template, the rise time of the triangular pulse is equal to T pr , and the fall time is equal to T pf ;
  • I nt is a negative periodic triangular pulse.
  • the period is the same as the period of the added data template.
  • the delay time is half a period.
  • the rise time of the triangular pulse is equal to T nr and the fall time is equal to T nf ;
  • I dc is the direct current
  • the noise acquisition module scans at the frequency of the data template while the switching current period changes from 9.38ns to 0.938ns, with a change step of 0.1ns, corresponding to the scan.
  • the obtained data template frequencies range from 100.6MHz to 1.066GHz.
  • the worst power supply noise does not necessarily appear at the PDN resonant frequency.
  • the impedance curve only describes the characteristics of the PDN impedance. Power supply noise is generated by the interaction between impedance and current. It is not enough to only determine the resonant frequency as the worst data template based on the impedance curve of the PDN. It is also necessary to analyze the simultaneous switching output current of the PDN. The output current of the PDN is the source of power supply noise.
  • the present invention provides a frequency sweep method to find the worst data template. It only needs one full-link simulation to obtain the simultaneous switching current. The equivalent modeling of the simultaneous switching current is used as an incentive, and the channel model is omitted. Finally, the period of simultaneous switching current is changed to obtain the worst power supply noise. Compared with the traditional multi-resonance point multiple full-link simulation, the present invention is more time-saving and accurate in finding the worst power supply noise.
  • Figure 1 is a schematic diagram of the Z PDN (f) curve and I PDN (f) spectral component PDN structure
  • Figure 2a is a schematic diagram of the topology of PDN
  • Figure 2b is a schematic diagram of the impedance curve of Z PDN (f);
  • Figure 3 is a schematic diagram of the full-link model including the PDN network
  • Figure 4a is a schematic diagram of the power supply voltage and PDN output current spectrum of different frequency data templates
  • Figure 4b is a schematic diagram of the power supply noise waveform corresponding to the power supply voltage of different frequency data templates and the PDN output current spectrum;
  • Figure 5 is a schematic diagram of the equivalent waveform of PDN simultaneous switching current at 178MHz;
  • Figure 6 is a schematic diagram of power supply noise excited by switching currents of different frequencies.
  • the present invention provides a method for solving the worst power supply noise of high-speed links, which includes the following steps:
  • S3 omit the channel link structure, directly use the simultaneous switching current as the input of the PDN, scan the simultaneous switching current at the frequency of the data template, and obtain multiple sets of power supply noise with different amplitudes.
  • the frequency of the simultaneous switching current is the frequency of the worst case data template of the power supply noise.
  • the second embodiment of the present invention is further described as follows based on the steps of the above-mentioned first embodiment
  • T is the period and f is the frequency.
  • f is the frequency.
  • the clock period is the length of the 01 sequence with a duty cycle of 50%. By expanding the period by 2, 3, 4... times, the relevant frequency division of the clock frequency can be obtained as The frequency of the data pattern at which the worst-case data pattern occurs at some frequency among these relevant divisions.
  • the Fourier series expansion of the square wave signal is:
  • the amplitude of the fundamental wave (sine wave) of the square wave is the largest when the duty cycle is 50%.
  • a DC component will be introduced. Regardless of the duty cycle of the signal, its effective value remains unchanged. The greater the DC component, the smaller the AC component, and the fundamental wave belongs to the AC component. , so only a square wave signal type data template with a duty cycle of 50% can excite the worst power supply noise.
  • Extract all relevant data templates Taking the above-mentioned DDR4 packaged PDN system as an example, first determine the clock frequency of the PDN operation.
  • the clock frequency of DDR4 is 1066MHz and the data sampling rate is 2133MHz.
  • the selected data template is shown in Table 3.
  • the switching current profile is roughly composed of three parts, namely steady-state current, rising side current and falling side current.
  • the rise time T pr , fall time T pf , and amplitude M p of the forward pulse of the simultaneous switching current and the rise time T nr , fall time T nf , and amplitude of the negative pulse are obtained.
  • M n is almost unchanged.
  • I pt is a positive periodic triangular pulse
  • the period is the same as the period of the added data template
  • the rising time of the triangular pulse is equal to T pr
  • the falling time is equal to T pf
  • the amplitude is equal to M p
  • nt is a negative periodic triangular pulse.
  • the period is the same as the period of the added data template
  • the delay time is half a period
  • the rise time of the triangular pulse is equal to T nr and the fall time is equal to T nf
  • the amplitude is equal to M p
  • I dc is the direct current flow.
  • a comparison of the equivalent model and the simultaneous switching current at 178MHz is shown in Figure 5. The portion of the current marked by 2 in the diagram is compensated with 1.
  • Frequency sweep processing by scanning the period of the switching current, the period transformation range is 9.38ns to 0.938ns, the change step is 0.1ns, and the corresponding scanned data template frequency is from 100.6MHz to 1.066GHz.
  • the simulation results show the trend diagram of the power supply noise on the PDN changing with the switching current frequency (that is, the data template frequency) as shown in Figure 6. From Figure 6, the data template with a frequency of 178MHz excites the worst power supply noise, with a peak-to-peak value of 18.1mv. It is consistent with the power supply noise excited by the 178MHz data template in Table 2. The power supply noise at other frequencies is also the same as the power supply noise excited at the same frequency in Table 2.
  • the present invention provides a computer-readable storage medium used in the steps of the method for solving the worst power supply noise of a high-speed link described in any one of the first embodiment or the second embodiment.
  • the present invention provides a high-speed link worst-case power supply noise solution system, which includes:
  • the driver module inputs a data template at a specified frequency in front of the driver, that is, a square wave signal type data template with a duty cycle of 50%;
  • the calculation module obtains all relevant data templates based on the clock frequency
  • the modeling module obtains the simultaneous switching current waveform profile based on a full-link simulation and approximates the simultaneous switching current
  • the noise acquisition module omits the channel link structure, directly uses the simultaneous switching current as the input of the PDN, scans the simultaneous switching current at the frequency of the data template, and obtains multiple sets of power supply noise with different amplitudes;
  • Frequency acquisition module which is used to acquire the worst power supply noise and its corresponding simultaneous switching power flow.
  • the present invention provides a high-speed link worst-case power supply noise solution system, which includes:
  • the driver module inputs the data template at the specified frequency before the driver
  • the calculation module obtains all relevant data templates based on the clock frequency
  • the modeling module obtains the simultaneous switching current waveform profile based on a full-link simulation and approximates the simultaneous switching current, including:
  • I pt is a forward period triangular pulse, the period is the same as the period of the added data template, the rise time of the triangular pulse is equal to T pr , and the fall time is equal to T pf .
  • I nt is a negative periodic triangular pulse
  • the period is the same as the period of the added data template
  • the delay time is half a period
  • the rise time of the triangular pulse is equal to T nr
  • the fall time is equal to T nf .
  • I dc is the direct current
  • the noise acquisition module omits the channel link structure, directly uses the simultaneous switching current as the input of the PDN, and scans the simultaneous switching current period at the frequency of the data template from 9.38ns to 0.938ns, with a change step of 0.1ns, corresponding to the scan to
  • the data template frequency ranges from 100.6MHz to 1.066GHz to obtain multiple sets of power supply noise with different amplitudes.
  • Frequency acquisition module which is used to acquire the worst-case power supply noise and its corresponding simultaneous switching current.

Abstract

本发明公开了一种高速链路最坏电源噪声求解方法、系统及存储介质，包括：在驱动器前输入指定频率下的数据模板，得到周期性的同时开关电流，根据时钟频率得到所有相关的数据模板；进行一次全链路仿真得到同时开关电流波形轮廓，并对同时开关电流近似建模；省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；找出最坏的电源噪声及其对应的同时开关电流，则该同时开关电流的频率就是电源噪声最坏情况的数据模板的频率。本发明基于建模扫频法能快速得到最坏电源噪声。

Description

高速链路最坏电源噪声求解方法、系统及存储介质
本申请要求于2022年07月08日提交中国专利局、申请号为202210806096.5、发明名称为“高速链路最坏电源噪声求解方法、系统及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及集成电路及系统领域，特别是涉及一种高速链路最坏电源噪声求解方法，一种用于执行所述高速链路最坏电源噪声求解方法中步骤的计算机可读存储介质，以及一种高速链路最坏电源噪声求解系统。
背景技术
随着集成电路的设计水平和工艺水平的不断发展，电路的集成度越来越高，时钟频率也随之越来越高，形成了Ghz以上的高速电路。以前忽略不计的电源噪声现在可以影响整个系统的工作状态，因此对电源噪声的研究越来越受到重视。电源噪声会耦合到信号线中，引起逻辑门电路的误触发，使得器件正常工作电压偏置，严重时会导致器件失效。电源噪声的大小与驱动器输入的数据有着十分密切的关系，因此找到能够激励出最大幅度电源噪声的数据模板对于电源分配网络的研究有着重要意义。
同时开关噪声(Simultaneous SwitchNoise，SSN)是指当数字电路驱动器中大量晶体管同时迅速动作、电平状态改变时，产生一个很大的瞬间变化电流，该电流流经回路寄生电感时，形成交流压降，从而引起电源电压的波动ΔV。同时开关噪声的定义如下：
ΔV＝N*Lloop(di/dt)     (1)
其中，N指的是同时开关的数量，即当芯片中N个缓冲驱动同时切换状态时，流经回路寄生电感Lloop(电源地平面上的电流回路电感)的电流将会扩大N倍。i指的是单个晶体管状态切换时所汲取的电流；当多个晶体管同时切换时产生的电流称为同时开关电流。经过感性封装后，会在电源地平面上或电源轨道处产生噪声，因此也称为电源噪声。电源噪声又会耦合到信号线中，在驱动器的输出端表现出来，造成输出波形的噪声和抖动。本发明针对的是芯片封装级PDN上的电源噪声，即封装中电源地 平面上的噪声。
对于寻找最坏情况的电源噪声，传统的做法是频域仿真得到PDN的目标阻抗，利用阻抗曲线ZPDN(f)来找出最坏情况数据模板，即找到PDN的谐振频率，如果PDN有多个谐振点，需要全链路多次仿真，然后用具有很强成分的PDN谐振频率的数据模板来作为激励输入到驱动器中，得到最坏电源噪声。然而这种寻找最坏数据模板的机制只适用于电流随阻抗线性变化的PDN结构，并不能适用于非线性ZPDN(f)曲线以及IPDN(f)谱分量PDN结构。
V(jω)＝I(jω)Z(jω)      (2)
公式(2)从频域角度解释了这一现象。在公式(2)中Z(jω)为PDN的阻抗频率函数，I(jω)为PDN电流的频率函数，两者相互作用下产生频域电源噪声V(jω)。在一般情况下，Z(jω)是随时间推移而改变的，然而I(jω)则取决于系统中的状态活动情况，可以是时变的和非周期平稳的，即随时间推移当状态活动(例如驱动器前的数据模板)改变时，I(jω)的频谱会随着数据模板的改变而改变，如图1所示。
阻抗曲线ZPDN(f)只能反映不同频率下PDN阻抗的特性，并不能体现频域中电流的特性，只有当PDN输出电流I(jω)在阻抗频带内的频谱分量较大时，才会出现最大幅度的电源噪声。因而若只根据频域的阻抗信息和谐振频率得到最坏数据模板是不够准确的。
以DDR4的封装中电源分配网络系统来说明。图2a是PDN的模型结构，模型是以S参数形式给出。1、2、3、4、5为芯片端口，连接芯片的去耦电容，PDN中有4个低电感电容器，连接在11、12、13、14端口。图中有5个通路，且通路之间相互独立，互不影响。以第一通路来分析，片上去耦电容为20.8nf，其寄生电阻为0.0015欧姆，在端口1处加幅度为1A的恒定正弦波电流源可得PDN阻抗曲线如图2b所示。从图中可以看出不同频率下PDN阻抗不同，由于PDN中的封装电感与片上去耦电容的相互作用，使得PDN在233MHz下发生了谐振。图3描述了仿真的全链路模型，包括PDN、PCB、封装、驱动器和接收器等模型。对驱动器输入不同频率的数据模板，得到时域电源噪声仿真结果如表1所示。
表1不同频率下的电源噪声
从表1中可以看出虽然PDN在233MHz频率处发生谐振，但在178MHz处激励出了最坏电源噪声，此处电源噪声的峰峰值为18mv，这是因为在所有频率的数据模板中178MHz频率处的PDN输出电流频谱分量最大，这主要是由于片上去耦电容的充放电周期和晶体管开关时间等工艺参数共同决定的。对不同频率的PDN输出电流做傅里叶变换可以得到不同频率的电流谱，如图4a所示，其对应的电源噪声波形如图4b所示。将频域阻抗与电流频谱相乘得到频域电源噪声，将频域电源噪声进行傅立叶反变换，得到时域的电源噪声，其峰峰值如表2所示。178MHz的电流谱与PDN阻抗的相互作用激励出最坏的电源噪声。因而最坏电源噪声的数据模板不一定在PDN的谐振频率处，而取决于电流频谱和阻抗频谱的共同作用。
表2不同频率下的Ipdn

发明内容
在发明内容部分中引入了一系列简化形式的概念，该简化形式的概念均为本领域现有技术简化，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
本发明要解决的技术问题是提供一种基于建模扫频法能快速得到最坏电源噪声的高速链路最坏电源噪声求解方法，以及一种用于执行所述高速链路最坏电源噪声求解方法中步骤的计算机可读存储介质和一种高速链路最坏电源噪声求解系统。
为解决上述技术问题，本发明提供一种高速链路最坏电源噪声求解方法，包括以下步骤：
S1，在驱动器前输入指定频率下的数据模板，得到周期性的同时开关电流，根据时钟频率得到所有相关的数据模板；
S2，进行一次全链路仿真得到同时开关电流波形轮廓，并对同时开关电流近似建模；
S3，省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；
S4，找出最坏的电源噪声及其对应的同时开关电流，则该同时开关电流的频率就是电源噪声最坏情况的数据模板的频率。
可选择的，进一步改进所述的高速链路最坏电源噪声求解方法，所述数据模板是占空比为50％的方波信号类的数据模板。
可选择的，进一步改进所述的高速链路最坏电源噪声求解方法，同时开关电流近似建模包括：
数据模板周期T满足T＞2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
数据模板周期T满足T＜2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
其中Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf；
Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr，下降时间等于Tnf；
Idc是直流电流。
可选择的，进一步改进所述的高速链路最坏电源噪声求解方法，以数据模板的频率扫描同时开关电流周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz。
为解决上述技术问题，本发明提供一种用于执行上述任意一项所述高速链路最坏电源噪声求解方法中步骤的计算机可读存储介质。
为解决上述技术问题，本发明提供一种高速链路最坏电源噪声求解系统，包括：
驱动模块，其在驱动器前输入指定频率下的数据模板；
计算模块，其根据时钟频率得到所有相关的数据模板；
建模模块，其基于一次全链路仿真得到同时开关电流波形轮廓，对同时开关电流近似建模；
噪声采集模块，其省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；
频率获取模块，其用于获取最坏的电源噪声及其对应的同时开关电流。
可选择的，进一步改进所述的高速链路最坏电源噪声求解系统，所述数据模板是占空比为50％的方波信号类的数据模板。
可选择的，进一步改进所述的高速链路最坏电源噪声求解系统，建模模块对同时开关电流近似建模包括：
数据模板周期T满足T＞2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
数据模板周期T满足T＜2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
其中Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf；
Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr，下降时间等于Tnf；
Idc是直流电流。
可选择的，进一步改进所述的高速链路最坏电源噪声求解系统，噪声采集模块以数据模板的频率扫描同时开关电流周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz。
最坏电源噪声不一定出现在PDN谐振频率处，阻抗曲线只描述了PDN阻抗的特性，电源噪声是阻抗与电流相互作用产生的。只根据PDN的阻抗曲线确定谐振频率作为最坏数据模板，这样的分析是不够的，还要分析PDN的同时开关输出电流，PDN的输出电流是产生电源噪声的根源。本发明为寻找最坏数据模板给出了扫频法，只需一次全链路仿真得到同时开关电流，通过同时开关电流的等效建模作为激励，省略了通道模型，然 后改变同时开关电流的周期，得到最坏电源噪声。相比于传统的多谐振点多次全链路仿真本发明找寻最坏电源噪声更加省时，且准确。
说明书附图
本发明附图旨在示出根据本发明的特定示例性实施例中所使用的方法、结构和/或材料的一般特性，对说明书中的描述进行补充。然而，本发明附图是未按比例绘制的示意图，因而可能未能够准确反映任何所给出的实施例的精确结构或性能特点，本发明附图不应当被解释为限定或限制由根据本发明的示例性实施例所涵盖的数值或属性的范围。下面结合附图与具体实施方式对本发明作进一步详细的说明：
图1是ZPDN(f)曲线以及IPDN(f)谱分量PDN结构示意图；
图2a是PDN的拓扑结构示意图；
图2b是ZPDN(f)的阻抗曲线示意图；
图3是包含PDN网络的全链路模型示意图；
图4a是不同频率数据模板的电源电压与PDN输出电流频谱示意图；
图4b是不同频率数据模板的电源电压与PDN输出电流频谱对应的电源噪声波形示意图；
图5是178MHz下的PDN同时开关电流等效波形示意图；
图6是不同频率的开关电流激励出的电源噪声示意图。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容充分地了解本发明的其他优点与技术效果。本发明还可以通过不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点加以应用，在没有背离发明总的设计思路下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。本发明下述示例性实施例可以多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的具体实施例。应当理解的是，提供这些实施例是为了使得本发明的公开彻底且完整，并且将这些示例性具体实施例的技术方案充分传达给本领域技术人员。
第一实施例
本发明提供一种高速链路最坏电源噪声求解方法，包括以下步骤：
S1，在驱动器前输入指定频率下的数据模板，得到周期性的同时开关电流，根据时钟频率得到所有相关的数据模板。
S2，进行一次全链路仿真得到同时开关电流波形轮廓，并对同时开关电流近似建模。
S3，省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声。
S4，找出最坏的电源噪声及其对应的同时开关电流，则该同时开关电流的频率就是电源噪声最坏情况的数据模板的频率。
第二实施例
本发明第二实施例针基于上述第一实施例各步骤进一步说明如下；
在驱动器前输入特定频率下的数据模板，会得到周期性的同时开关电流，改变数据模板的频率，同时开关电流会随着数据模板的变化而有规律地变化，图5中的虚线为178MHz的同时开关电流波形。
确定PDN的工作时钟频率，公式如下：
T＝1/f          (3)
其中，T为周期，f为频率，求出时钟周期，时钟周期为占空比为50％的01序列的时长，将周期扩大2，3，4…倍，可得到时钟频率的相关分频作为数据模板的频率，最坏数据模板会出现在这些相关分频的某个频率处。方波信号傅里叶级数展开式为：
方波在占空比为50％时的基波(正弦波)幅值最大。当信号的占空比不等于50％时，就会引入直流分量，而信号不论占空比为多少，其有效值不变，直流分量越大，交流分量就越小，而基波属于交流分量，因此只有占空比为50％的方波信号类的数据模板才能激励出最坏的电源噪声。
提取所有相关数据模板，以上述DDR4封装PDN系统为例，首先确定PDN工作的时钟频率，DDR4的时钟频率为1066MHz，数据采样速率为2133MHz。UI＝0.469ns，T＝0.938ns，UI代表一个位时长，选择为占空比为50％的数据模板作为驱动器的输入，所选择的数据模板如表3所示。
表3不同频率的数据模板
其中，···代表重复数据模板。
同时开关电流的建模，以DDR4封装PDN中的同时开关电流为例，具体建模过程如下：
同时开关电流轮廓大致由三部分构成，分别是稳态电流，上升边电流和下降边电流。通过观察不同频率下的同时开关电流波形，得出同时开关电流的正向脉冲的上升时间Tpr、下降时间Tpf、幅度Mp和负向脉冲的上升时间Tnr、下降时间Tnf、幅度Mn几乎不变的结论。当所加数据模板的周期T满足如下条件时：
T＞2(Tpr+Tpf+Tnr+Tnf)      (5)
开关电流Issi可用如下公式建模：
Issi＝Ipt+Int+Idc     (6)
式(6)中，Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf，幅度等于Mp；Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr、下降时间等于Tnf；幅度等于Mp；Idc是直流电 流。等效模型与178MHz下的同时开关电流的对比图如图5所示。图中由2标示的电流部分用1进行补偿。
当所加数据模板的周期T满足如下条件时：
T＜2(Tpr+Tpf+Tnr+Tnf)      (7)
同时开关电流仍用公式(6)建模。其中三角脉冲下降时间变为：
式(6)中的其余变量保持不变。将上述等效电流模型作为激励，仿真PDN上的电源噪声。
扫频处理，通过扫描开关电流的周期，周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz。仿真得到PDN上电源噪声随同时开关电流频率(即数据模板频率)变化的趋势图如图6所示。从图6中得到178MHz频率的数据模板激励出了最坏电源噪声，其峰峰值即为18.1mv。它与表2中178MHz数据模板激励出的电源噪声相一致，其余频率处的电源噪声也与表2中的相同频率下激励出的电源噪声大小相同。
第三实施例
本发明提供一种用于第一实施例或第二实施例任意一项所述高速链路最坏电源噪声求解方法中步骤的计算机可读存储介质。
第四实施例
本发明提供一种高速链路最坏电源噪声求解系统，包括：
驱动模块，其在驱动器前输入指定频率下的数据模板，即占空比为50％的方波信号类的数据模板；
计算模块，其根据时钟频率得到所有相关的数据模板；
建模模块，其基于一次全链路仿真得到同时开关电流波形轮廓，对同时开关电流近似建模；
噪声采集模块，其省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；
频率获取模块，其用于获取最坏的电源噪声及其对应的同时开关电 流。
第五实施例；
本发明提供一种高速链路最坏电源噪声求解系统，包括：
驱动模块，其在驱动器前输入指定频率下的数据模板；
计算模块，其根据时钟频率得到所有相关的数据模板；
建模模块，其基于一次全链路仿真得到同时开关电流波形轮廓，对同时开关电流近似建模，包括：
数据模板周期T满足T＞2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc。
数据模板周期T满足T＜2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模，Issi＝Ipt+Int+Idc。
其中Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf。
Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr，下降时间等于Tnf。
Idc是直流电流。
噪声采集模块，其省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz得到多组不同幅度大小的电源噪声。
频率获取模块，其用于获取最坏的电源噪声及其对应的同时开关电流。
除非另有定义，否则这里所使用的全部术语(包括技术术语和科学术语)都具有与本发明所属领域的普通技术人员通常理解的意思相同的意思。还将理解的是，除非这里明确定义，否则诸如在通用字典中定义的术语这类术语应当被解释为具有与它们在相关领域语境中的意思相一致的意思，而不以理想的或过于正式的含义加以解释。
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些 并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (9)

  1. 一种高速链路最坏电源噪声求解方法，其特征在于，包括以下步骤：
    S1，在驱动器前输入指定频率下的数据模板，得到周期性的同时开关电流，根据时钟频率得到所有相关的数据模板；
    S2，进行一次全链路仿真得到同时开关电流波形轮廓，并对同时开关电流近似建模；
    S3，省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；
    S4，找出最坏的电源噪声及其对应的同时开关电流，则该同时开关电流的频率就是电源噪声最坏情况的数据模板的频率。
  2. 如权利要求1所述的高速链路最坏电源噪声求解方法，其特征在于，所述数据模板是占空比为50％的方波信号类的数据模板。
  3. 如权利要求1所述的高速链路最坏电源噪声求解方法，其特征在于，同时开关电流近似建模包括：
    数据模板周期T满足T＞2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
    数据模板周期T满足T＜2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
    其中Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf；
    Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr，下降时间等于Tnf；
    Idc是直流电流。
  4. 如权利要求1所述的高速链路最坏电源噪声求解方法，其特征在于，以数据模板的频率扫描同时开关电流周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz。
  5. 一种用于执行权利要求1-4任意一项所述高速链路最坏电源噪声求解方法中步骤的计算机可读存储介质。
  6. 一种高速链路最坏电源噪声求解系统，其特征在于，包括：
    驱动模块，其在驱动器前输入指定频率下的数据模板；
    计算模块，其根据时钟频率得到所有相关的数据模板；
    建模模块，其基于一次全链路仿真得到同时开关电流波形轮廓，对同时开关电流近似建模；
    噪声采集模块，其省略通道链路结构，直接将同时开关电流作为PDN的输入，以数据模板的频率扫描同时开关电流，得到多组不同幅度大小的电源噪声；
    频率获取模块，其用于获取最坏的电源噪声及其对应的同时开关电流。
  7. 如权利要求6所述的高速链路最坏电源噪声求解系统，其特征在于，所述数据模板是占空比为50％的方波信号类的数据模板。
  8. 如权利要求6所述的高速链路最坏电源噪声求解系统，其特征在于，建模模块对同时开关电流近似建模包括：
    数据模板周期T满足T＞2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流Issi用如下公式建模：Issi＝Ipt+Int+Idc；
    数据模板周期T满足T＜2(Tpr+Tpf+Tnr+Tnf)时，同时开关电流用如下公式建模：Issi＝Ipt+Int+Idc；
    其中Ipt是正向周期三角脉冲，周期与所加数据模板周期相同，三角脉冲上升时间等于Tpr，下降时间等于Tpf；
    Int是负向周期三角脉冲，周期与所加数据模板周期相同，延迟时间为半个周期，三角脉冲上升时间等于Tnr，下降时间等于Tnf；
    Idc是直流电流。
  9. 如权利要求6所述的高速链路最坏电源噪声求解系统，其特征在于，噪声采集模块以数据模板的频率扫描同时开关电流周期变换范围为9.38ns到0.938ns，变化步长为0.1ns，对应扫描到的数据模板频率从100.6MHz到1.066GHz。
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CN115166572A (zh) * 2022-07-08 2022-10-11 宁波德图科技有限公司 高速链路最坏电源噪声求解方法、系统及存储介质

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