WO2024007443A1 - 具有多阈值电压的GaN基HEMT结构、其制备方法及应用 - Google Patents

具有多阈值电压的GaN基HEMT结构、其制备方法及应用 Download PDF

Info

Publication number
WO2024007443A1
WO2024007443A1 PCT/CN2022/117566 CN2022117566W WO2024007443A1 WO 2024007443 A1 WO2024007443 A1 WO 2024007443A1 CN 2022117566 W CN2022117566 W CN 2022117566W WO 2024007443 A1 WO2024007443 A1 WO 2024007443A1
Authority
WO
WIPO (PCT)
Prior art keywords
barrier layer
layer
gan
region
gate
Prior art date
Application number
PCT/CN2022/117566
Other languages
English (en)
French (fr)
Inventor
钟耀宗
孙钱
高宏伟
郭小路
陈昕
杨勇
杨辉
Original Assignee
广东中科半导体微纳制造技术研究院
中国科学院苏州纳米技术与纳米仿生研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广东中科半导体微纳制造技术研究院, 中国科学院苏州纳米技术与纳米仿生研究所 filed Critical 广东中科半导体微纳制造技术研究院
Priority to EP22944072.2A priority Critical patent/EP4336563A1/en
Priority to CA3209196A priority patent/CA3209196A1/en
Priority to JP2023548706A priority patent/JP2024528764A/ja
Publication of WO2024007443A1 publication Critical patent/WO2024007443A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present application relates to a high electron mobility transistor (HEMT) device structure, specifically to a GaN-based HEMT structure with multiple threshold voltages, its preparation method and application, and belongs to the field of semiconductor technology.
  • HEMT high electron mobility transistor
  • Group III nitride semiconductors represented by GaN are called third-generation semiconductors and have the advantages of large bandgap, good chemical stability, and high breakdown voltage.
  • GaN-based HEMTs composed of heterostructures such as AlGaN/GaN have the advantages of high electron concentration and mobility, and have excellent performance in high frequency, high withstand voltage, low on-resistance, etc., and can be used in various power conversion systems,
  • the core device of the radio frequency power amplifier system has broad prospects in application fields such as consumer electronics, industrial electronics, and automotive electronics.
  • N-MOSFET N-channel metal-oxide-semiconductor field-effect transistor
  • P-MOSFET P-channel metal-oxide-semiconductor field effect transistor
  • Semiconductor field effect transistor is composed of two devices, namely C-MOS circuit (complementary logic circuit), which has the advantages of low power consumption and high integration.
  • N-MOSFET is a field effect transistor prepared by inverting electrons on a p-type silicon material as a conductive channel
  • P-MOSFET is a field effect transistor prepared by inverting holes on an n-type silicon material as a conductive channel.
  • GaN-based materials due to the presence of many defect states, undoped GaN often exhibits a weak n-type; and due to the incomplete ionization characteristics of the acceptor Mg impurity, p-type materials need to be doped with a higher concentration of Mg; In addition, the bulk mobility of holes in GaN is very low, usually 1 to 10 cm 2 /(V ⁇ s).
  • the main solution to realize N-MOSFET in GaN system is to use two-dimensional electron gas (2DEG) induced by AlGaN/GaN heterojunction polarization effect as the conductive channel, and adopt technologies such as groove gate and p-type gate.
  • 2DEG two-dimensional electron gas
  • the solution is to realize the enhancement mode n-FET with positive threshold voltage to realize the N-MOSFET characteristics of high-level turn-on and low-level turn-off;
  • the solution to realize P-MOSFET is mainly: using p-GaN/AlGaN heterogeneous
  • the two-dimensional hole gas induced by the mass junction polarization effect serves as the conductive channel, and gate technologies such as groove gate and ion implantation gate are used to realize enhancement-mode p-FET with negative threshold voltage to achieve low-level turn-on, High-level turn-off P-MOS transistor characteristics.
  • n-FET and p-FET are connected in series to build a complementary logic circuit unit, and finally realize the relevant functional circuit design and manufacturing.
  • complementary logic circuits (0/1 logic) based on GaN n-FETs and p-FETs.
  • the GaN-based p-FET in the above-mentioned complementary logic circuit technology usually utilizes body holes in p-type GaN, or two-dimensional hole gas at the p-GaN/AlGaN interface, and its mobility is very low. , around 10cm 2 /(V ⁇ s) at room temperature, with a maximum of no more than 50cm 2 /(V ⁇ s), which is different from the mobility of AlGaN/GaN-induced two-dimensional electron gas which is usually 1500cm 2 /(V ⁇ s) huge.
  • the ultimate calculation speed of a logic operation circuit is strongly related to the mobility of carriers in semiconductor materials. The higher the carrier mobility, the faster the ultimate calculation speed of the circuit. Therefore, for logic circuits composed of GaN-based p-FETs and n-FETs, the ultimate calculation speed will be limited by the mobility of two-dimensional hole gas, making it difficult to take advantage of the GaN material system.
  • the GaN-based p-FET in the above-mentioned complementary logic circuit technology requires high-quality p-GaN ohmic contacts.
  • the current preparation of p-GaN ohmic contacts requires the p-GaN surface layer to be heavily doped with Mg to more than 10 20 cm -3 , and high work function metals such as Ni and Pd are required.
  • the contact resistivity is usually above 10 -4 ⁇ cm 2 , and higher contact resistivity will lead to greater power loss.
  • the thermal stability of p-GaN ohmic contacts is also poor and is not suitable for harsh working environments.
  • the p-FET gates in the above-mentioned complementary logic circuit technology are mostly prepared through etching, ion implantation and other processes, which have problems with uniformity and reliability.
  • etching ion implantation
  • other processes which have problems with uniformity and reliability.
  • GaN dry etching to thin the p-FET gate region, or using ion implantation to perform acceptor compensation on p-GaN, it is difficult to avoid causing lattice damage and surface contamination to the GaN layer, introducing gate
  • the extreme interface state causes problems such as threshold voltage drift, large leakage and other device performance deterioration.
  • the performance of the prepared p-FET cannot meet the requirements of logic operations.
  • the above-mentioned high and low threshold logic circuit technology requires the realization of high and low threshold voltage enhancement devices (such as devices with threshold voltages >1V and >2V) on the same wafer, and requires extremely high uniformity and reliability.
  • high and low threshold voltage enhancement devices such as devices with threshold voltages >1V and >2V
  • GaN-based devices there is currently no perfect solution.
  • the main purpose of this application is to provide a GaN-based HEMT structure with multiple threshold voltages and a preparation method thereof to overcome the shortcomings of the existing technology.
  • One aspect of the present application provides a GaN-based HEMT structure with multiple threshold voltages, including a channel layer and a barrier layer, with a two-dimensional electron gas formed between the channel layer and the barrier layer; the barrier The layer at least has a first source region and a second source region, a first gate region and a second gate region, a first drain region and a second drain region; the first source region, the first gate region The electrode region and the first drain region cooperate with each other to form a first HEMT unit, the first HEMT unit has a first threshold voltage; the second source region, the second gate region and the second drain region cooperate with each other to form a second HEMT unit, the second HEMT unit having a second threshold voltage; wherein the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, so that the The first threshold voltage is higher than the second threshold voltage.
  • Another aspect of the present application provides a method for preparing a GaN-based HEMT structure with multiple threshold voltages, which includes:
  • At least a first source region and a second source region, a first gate region and a second gate region, a first drain region and a second drain region are defined on the barrier layer, wherein the third A source region, a first gate region and a first drain region cooperate with each other to form a first HEMT unit, and the second source region, a second gate region and a second drain region cooperate with each other to form a first HEMT unit.
  • the first HEMT unit has a first threshold voltage
  • the second HEMT unit has a second threshold voltage
  • the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, or after the growth of the barrier layer is completed, the thickness of the barrier layer is A local area of the barrier layer is removed, so that the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, so that the first threshold voltage is higher than the second threshold voltage.
  • GaN-based HEMT device which includes the GaN-based HEMT structure with multiple threshold voltages and multiple gates, multiple sources and multiple drains that cooperate with the HEMT structure. pole.
  • Another aspect of the present application provides the use of the GaN-based HEMT structure with multiple threshold voltages in preparing high and low threshold logic circuits.
  • this application can realize an enhanced GaN-based HEMT structure with more than two threshold voltages on the same wafer.
  • the manufacturing process is compatible with the conventional III-V semiconductor device manufacturing process and is suitable for industrial production.
  • the barrier layer of the GaN-based HEMT can be an AlGaN/GaN/AlGaN composite structure, and the introduction of the GaN insertion layer can be used as a sacrificial layer for etching and thermal decomposition of the first gate region, ensuring that the gate
  • the thickness of the regional AlGaN barrier layer and the effective removal of etching damage provide a good guarantee for the uniformity of the threshold voltage and the reliability of the device; furthermore, the two threshold voltage enhancement GaN HEMTs implemented in this application form a coordinated circuit.
  • the two enhancement mode GaN HEMT implemented in this application both use high mobility two-dimensional electrons.
  • gas has the ability to switch quickly, and the logic circuit made with it has faster calculation speed and stronger anti-interference ability; therefore, this application can well meet the application of high and low threshold logic circuits need.
  • Figure 1 is a schematic diagram of a logic unit composed of a multi-threshold voltage HEMT in the prior art
  • Figure 2 is a schematic diagram of the epitaxial structure of a GaN-based HEMT device in Embodiment 1;
  • Figure 3 is a schematic diagram of making a groove structure in the first gate region of the epitaxial structure shown in Figure 2;
  • Figure 4 is a schematic diagram of a secondary epitaxial P-type layer on the epitaxial structure shown in Figure 3;
  • Figure 5 is a schematic diagram of fabricating a P-type gate on the device structure shown in Figure 4;
  • Figure 6 is a schematic structural diagram of a GaN-based HEMT device in Embodiment 1;
  • Figure 7 is a schematic structural diagram of a GaN-based HEMT device in Embodiment 2.
  • Figure 8 is a schematic structural diagram of a GaN-based HEMT device in Embodiment 3.
  • Figure 9 is a schematic structural diagram of a GaN-based HEMT device in Embodiment 4.
  • Figure 10 is a schematic structural diagram of a GaN-based HEMT device in Embodiment 5.
  • Some embodiments of the present application provide a GaN-based HEMT structure with multiple threshold voltages including a channel layer and a barrier layer, with a two-dimensional electron gas formed between the channel layer and the barrier layer; the barrier The layer at least has a first source region and a second source region, a first gate region and a second gate region, a first drain region and a second drain region; the first source region, the first gate region The electrode region and the first drain region cooperate with each other to form a first HEMT unit, the first HEMT unit has a first threshold voltage; the second source region, the second gate region and the second drain region cooperate with each other to form a second HEMT unit, the second HEMT unit having a second threshold voltage; wherein the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, so that the The first threshold voltage is higher than the second threshold voltage.
  • the barrier layer further has a third source region, a third gate region and a third drain region; the third source region, the third gate region and the third drain region Cooperate with each other to form a third HEMT unit, the third HEMT unit has a third threshold voltage; the thickness of the barrier layer in the second gate region is smaller than the thickness in the third gate region, so that the third gate region A threshold voltage>the second threshold voltage>the third threshold voltage.
  • HEMT units other than the third HEMT unit.
  • the threshold voltage of each HEMT unit can be adjusted, and a GaN-based HEMT structure with multiple threshold voltages can be obtained based on the same wafer, with good uniformity and High reliability.
  • the HEMT structure further includes a P-type layer disposed on multiple gate regions of the barrier layer for reducing or depleting multiple gate regions of the barrier layer. Two-dimensional electron gas below the gate region.
  • a groove structure is formed in at least one gate region of the barrier layer, and the P-type layer distributed on the gate region is at least partially filled into the groove structure.
  • the HEMT structures of this application are all n-FETs. They only use epitaxial growth of p-type cap layers on the grooves with different thickness barrier layers to achieve different threshold voltages. ; Therefore, there is no need to face the difficulties in preparing the p-GaN ohmic contact of p-FET, namely: heavy doping of the p-GaN surface layer, the use of metals with high work functions, and harsh process conditions; there is also no need to face the difficulties in p-GaN material Problems such as high defect state concentration and low hole mobility.
  • the barrier layer includes a plurality of barrier layer sub-layers sequentially disposed on the channel layer.
  • a groove structure is formed in at least one gate region of the barrier layer, the groove openings of the groove structure are distributed on the surface of the barrier layer, and the groove bottoms are distributed inside and adjacent to one sub-layer of the barrier layer. The interface between two barrier layer sublayers or the surface of the channel layer.
  • a groove structure is formed in at least one gate region of the barrier layer, and the barrier layer includes a first barrier layer sub-layer and a second barrier layer disposed on the first barrier layer sub-layer. sub-layer, the groove structure includes a first groove structure and a second groove structure, the first groove structure is formed in the first barrier layer sub-layer, and a part of the second barrier layer sub-layer Regions are recessed into the first groove structure to form said second groove structure.
  • the HEMT structure further includes at least one insertion layer distributed between two barrier layer sub-layers.
  • a groove structure is formed in at least one gate region of the barrier layer, the groove openings of the groove structure are distributed on the surface of the barrier layer, and the groove bottoms are distributed inside an insertion layer or an insertion layer. at the interface between the layer and the adjacent barrier layer sublayer.
  • the GaN insertion layer when etching the barrier layer to form a gate groove, can be used as a sacrificial layer for etching and thermal decomposition, effectively removing lattice damage and surface contamination, and causing thermal decomposition to automatically terminate at
  • the AlGaN barrier layer below can avoid the problems of device performance deterioration such as threshold voltage drift and large leakage caused by the gate interface state introduced by etching, and ensure that the first gate region or the first gate region and the second gate
  • the consistency of the barrier thickness in the polar region improves the uniformity of the device threshold voltage.
  • a groove structure is formed in at least one gate region of the barrier layer, the groove openings of the groove structure are distributed on the surface of the barrier layer, and the groove bottoms are distributed on the surface of the channel layer, and at least A continuous gate dielectric layer is covered on the inner wall of the groove structure, and the gate dielectric layer is used to separate the gate electrode from the inner wall of the groove structure.
  • the HEMT structure specifically includes a transition layer, a voltage-resistant layer, a channel layer and a barrier layer grown sequentially on a substrate.
  • Some embodiments of the present application also provide a GaN-based HEMT device, which includes the GaN-based HEMT structure with multiple threshold voltages and a gate, source, drain, etc. that cooperate therewith.
  • a gate, a source and a drain can be respectively provided.
  • the materials and arrangements of the gate, source, and drain are all known to those skilled in the art, and will not be explained in detail here.
  • the GaN-based HEMT structure or the GaN-based HEMT device may also include other structural layers, such as a passivation layer, a structure for electrically isolating multiple HEMT units, etc., which are also known in this field. Known to the skilled person.
  • Some embodiments of the present application provide a method for preparing a GaN-based HEMT structure with multiple threshold voltages, including:
  • At least a first source region and a second source region, a first gate region and a second gate region, a first drain region and a second drain region are defined on the barrier layer, wherein the third A source region, a first gate region and a first drain region cooperate with each other to form a first HEMT unit, and the second source region, a second gate region and a second drain region cooperate with each other to form a first HEMT unit.
  • the first HEMT unit has a first threshold voltage
  • the second HEMT unit has a second threshold voltage
  • the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, or after the growth of the barrier layer is completed, the thickness of the barrier layer is A local area of the barrier layer is removed, so that the thickness of the barrier layer in the first gate region is smaller than the thickness in the second gate region, so that the first threshold voltage is higher than the second threshold voltage.
  • the preparation method specifically includes: after the barrier layer is grown, etching at least the first gate region to form a groove in at least the first gate region. structure.
  • the preparation method specifically includes: first growing a first barrier layer sub-layer, and etching a first groove structure in a selected area of the first barrier layer sub-layer, the selected The area corresponds to the first gate area, and then a second barrier layer sub-layer is grown on the first barrier layer sub-layer, so that a local area of the second barrier layer sub-layer is recessed into the first groove structure, and forming a second groove structure to form the barrier layer.
  • the preparation method specifically includes: sequentially growing a plurality of barrier layer sub-layers on the channel layer, and growing an insertion layer between at least two barrier layer sub-layers, thereby forming the barrier. layer.
  • the preparation method specifically includes: growing a P-type layer on the barrier layer, filling a local area of the P-type layer into the groove structure, and then growing the P-type layer The remaining regions except the gate regions are etched away to reduce or deplete the two-dimensional electron gas under the plurality of gate regions of the barrier layer.
  • the preparation method specifically includes: growing a gate dielectric layer on the barrier layer, and making the gate dielectric layer continuously cover at least the inner wall of the groove structure.
  • dry etching or wet etching processes commonly used in this field can be used to etch the barrier layer to form the groove structure.
  • the channel layer, barrier layer, P-type layer, insertion layer, etc. may be mainly formed of III-V semiconductor compounds, that is, GaN-based materials, especially formed of III-nitrides.
  • the material of the channel layer may be GaN, etc.
  • the material of the barrier layer may be AlGaN, AlInGaN, etc.
  • the material of the P-type layer may be GaN, AlGaN, etc.
  • the material of the insertion layer may be GaN, etc., and is not limited to this.
  • the material of the gate dielectric layer may include silicon nitride or silicon oxide, but is not limited thereto.
  • the transition layer, voltage-resistant layer, channel layer, barrier layer, etc. can use HVPE (Hydride Vapor Phase Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), PECVD (Plasma Enhanced) commonly used in this field.
  • HVPE Hydride Vapor Phase Epitaxy
  • MOCVD Metal Organic Chemical Vapor Deposition
  • PECVD Pullasma Enhanced
  • Chemical vapor deposition and other methods are grown and formed, and are not limited thereto.
  • the preparation method may also include other device processing steps known in the art, such as forming a surface passivation layer on the device structure, and further forming a gate, source, and drain after depositing a dielectric layer, and forming a gate electrode on each electrode. Deposit metal to prepare field plate structures, etc. to form the final GaN-based HEMT device.
  • the GaN-based HEMT structure includes an AlGaN/GaN heterojunction, and is adopted on an AlGaN barrier layer or a GaN channel layer with or without grooves.
  • the thickness of the barrier layer in this area is small, so the concentration of two-dimensional electron gas (2DEG) induced by the AlGaN/GaN heterojunction is low, and the secondary After epitaxy of p-GaN or AlGaN/p-GaN, the 2DEG under the gate is easily depleted and the energy band is raised higher, which will form a HEMT unit with a high threshold voltage; while for the AlGaN barrier layer without grooves
  • the gate region has a thicker barrier layer.
  • the p-GaN gate prepared by secondary epitaxy will form a HEMT unit with a low threshold voltage due to the thick barrier layer.
  • the thickness of the AlGaN barrier layer of the two HEMT units is controlled by high-precision MOCVD and other processing equipment, and the uniformity of the threshold voltage is guaranteed.
  • the process of this application can realize enhanced GaN-based HEMT structures with more than two threshold voltages on the same wafer, is compatible with conventional III-V semiconductor device preparation processes, is suitable for industrial production, and can effectively guarantee the GaN The uniformity of the threshold voltage of the HEMT-based structure and the reliability of the device, etc.
  • the introduced GaN insertion layer can be used as a sacrificial layer for etching and thermal decomposition of the first gate region to ensure that the gate region AlGaN
  • the thickness of the barrier layer can effectively remove etching damage, thereby more effectively ensuring the uniformity of the device threshold voltage and the reliability of the device.
  • Some embodiments of the present application also provide a high and low threshold logic circuit, which includes the GaN-based HEMT structure with multiple threshold voltages.
  • the enhancement-mode GaN HEMTs with multiple threshold voltages form a coordinated circuit, which has lower power consumption and higher safety than a coordinated circuit formed by depletion-mode/enhancement-mode GaN HEMTs.
  • many of the enhanced GaNHEMTs use high-mobility two-dimensional electron gas as the conductive channel, which has the ability to switch quickly.
  • the logic circuit made with it has faster calculation speed and stronger anti-interference. ability.
  • this application can simultaneously realize high uniformity high and low threshold voltage enhancement mode HEMTs on GaN-based wafers, and meet the basic device requirements of 1/2 logic circuits.
  • the GaN-based HEMT structure of the present application has higher reliability.
  • the logic circuit implemented using the GaN-based HEMT structure of the present application uses two-dimensional electron gas with high mobility as the conductive channel, and has the characteristics of fast switching speed and high integration.
  • this embodiment provides a method for preparing a GaN-based HEMT device with multiple threshold voltages, including:
  • MOCVD metal organic vapor deposition
  • Layer 103 unintentionally doped GaN layer 104 having a thickness of about 150 nm, a first AlGaN barrier sub-layer 105A having a thickness of about 12 nm, a GaN insertion layer 106A having a thickness of about 4 nm, a second AlGaN barrier sub-layer having a thickness of about 4 nm 105B, as shown in Figure 2.
  • the first AlGaN barrier layer sub-layer 105A and the second AlGaN barrier layer sub-layer 105B constitute a barrier layer.
  • a first p-GaN layer 107A (also named a first P-type gate) is prepared in the first gate region, and a second p-GaN layer is prepared in the second gate region of the second AlGaN barrier layer sub-layer 105B.
  • 107B (can also be named the second P-type gate), as shown in Figure 5.
  • Ti/Al/Ti/Au are respectively deposited in the area to form the first source contact metal 109A, the second source contact metal 109B, the first drain contact metal 110A, and the second drain contact metal 110B. After annealing, they are prepared into ohmic touch. Furthermore, the first Schottky gate contact metal 108A, the first source contact metal 109A and the first drain contact metal 110A cooperate to form a transistor unit A with a high threshold voltage, and the second Schottky gate contact metal 108B, The second source contact metal 109B and the second drain contact metal 110B constitute the transistor cell B having a low threshold voltage.
  • the gate transfer characteristics of the GaN-based HEMT device were tested using I-V and other methods, and the average threshold voltage of transistor unit A was approximately 2.1V, and the average threshold voltage of transistor unit B was approximately 1.3V.
  • the test results confirm that the solution of this embodiment can prepare p-type gate enhancement-mode HEMTs with high and low threshold voltages on the same wafer.
  • the MOCVD method is used to sequentially grow the AlN/AlGaN transition layer 202, the C-doped Al 0.07 Ga 0.93 N high-resistance layer 203, the unintentionally doped GaN layer 204, and the thickness on the substrate 201.
  • AlGaN barrier layer 205A of approximately 18 to 25 nm.
  • step S2 of Embodiment 1 use photoresist as a mask, and after photolithography patterning, use the ICP etching method to etch and remove a portion of the first gate region of the AlGaN barrier layer 205A along the thickness direction (for example, approximately 6nm), forming a groove structure.
  • the groove structure is terminated at a certain depth within the AlGaN barrier layer 205A (the distance between the bottom of the groove and the channel layer is 8 to 20 nm), and then the p-type GaN is epitaxially epitaxially performed for a second time.
  • layer or p-type AlGaN layer referred to as p-type cap layer).
  • step S3 of Embodiment 1 use photoresist as a mask, and use dry etching to remove the p-type cap layer in the non-gate region after photolithography patterning, so that the etching stops at the AlGaN barrier layer 205A. surface, thereby preparing a first p-type cap layer 207A (also named the first P-type gate) in the first gate region, and preparing a second p-type cap layer in the second gate region of the AlGaN barrier layer 205A.
  • 207B can also be named the second P-type gate).
  • step S4 of Embodiment 1 use an organic cleaning method such as acetone to remove the photoresist, and then use hydrofluoric acid (HF) or the like to remove the oxide layer on the surface of the barrier layer, followed by rapid annealing to restore the AlGaN/GaN heterogeneity. Two-dimensional electron gas at the junction.
  • organic cleaning method such as acetone to remove the photoresist
  • hydrofluoric acid (HF) or the like to remove the oxide layer on the surface of the barrier layer
  • Ti/Au is deposited on the two P-type gates, and after annealing, the first Schottky gate contact metal 208A and the second Schottky gate contact metal 208B are prepared, and in each source region and drain of the barrier layer Ti/Al/Ti/Au are respectively deposited in the area to form the first source contact metal 209A, the second source contact metal 209B, the first drain contact metal 210A, and the second drain contact metal 210B. After annealing, they are prepared into ohmic touch.
  • first Schottky gate contact metal 208A, the first source contact metal 209A and the first drain contact metal 210A cooperate to form a transistor unit A with a high threshold voltage
  • second Schottky gate contact metal 208B, The second source contact metal 209B and the second drain contact metal 210B constitute the transistor cell B having a low threshold voltage.
  • the gate transfer characteristics of the GaN-based HEMT device in this embodiment were tested, and the average threshold voltage of transistor unit A was approximately 2.3V, and the average threshold voltage of transistor unit B was approximately 1.1V.
  • the MOCVD method is used to sequentially grow the AlN/AlGaN transition layer 302, the C-doped Al 0.07 Ga 0.93 N high-resistance layer 303, the unintentionally doped GaN layer 304 and the thickness on the substrate 301.
  • the first AlGaN barrier layer sub-layer 305A is about 2 to 10 nm, and then all the left gate region of the first AlGaN barrier layer sub-layer 305A is removed through patterned etching, and then the second epitaxy thickness is about 0 to 10 nm.
  • a 10 nm GaN layer, an AlGaN layer with a thickness of about 5 to 15 nm, and a p-(Al)GaN layer with a thickness of about 70 nm form a stacked structure 305B (preferably, the GaN layer has a thickness of about 5 nm, and the AlGaN thickness is about 10 nm).
  • a first p-type layer 307B (also named a first P-type gate) is prepared in the first gate region of the stacked structure 305B.
  • a second p-type layer 307B (also named a second P-type gate) is prepared in the second gate region.
  • step S4 of Embodiment 1 respectively manufacture the first Schottky gate contact metal 308A, the second Schottky gate contact metal 308B, the first source contact metal 309A, the second source contact metal 309B, and the first Schottky gate contact metal 308B. Drain contact metal 310A, second drain contact metal 310B, etc. Furthermore, the first Schottky gate contact metal 308A, the first source contact metal 309A and the first drain contact metal 310A cooperate to form a transistor unit A with a high threshold voltage, and the second Schottky gate contact metal 308B, The second source contact metal 309B and the second drain contact metal 310B constitute the transistor cell B having a low threshold voltage.
  • the gate transfer characteristics of the GaN-based HEMT device in this embodiment were tested, and the average threshold voltage of transistor unit A was approximately 2.3V, and the average threshold voltage of transistor unit B was approximately 1.3V.
  • the MOCVD method is used to sequentially grow an AlN/AlGaN transition layer 402, a C-doped Al 0.07 Ga 0.93 N high-resistance layer 403, an unintentionally doped GaN layer 404, and a third layer on the substrate 401.
  • step S2 of Embodiment 1 use photoresist as a mask, and after photolithography patterning, use the ICP etching method to etch the first gate region and the second gate region of the AlGaN barrier layer along the thickness direction. A portion is removed to form a first groove structure and a second groove structure respectively.
  • the groove bottom surface of the first groove structure is located on the surface of the first AlGaN barrier layer sub-layer 405A, and the groove bottom surface of the second groove structure is located on the surface of the first AlGaN barrier layer sub-layer 405A.
  • the third gate region of the AlGaN barrier layer is not etched.
  • a GaN layer with a thickness of about 0 ⁇ 10nm, an AlGaN layer with a thickness of about 0 ⁇ 10nm and a p-(Al)GaN layer with a thickness of about 70nm are epitaxially grown twice to form a stacked structure (which can also be considered is a P-type layer).
  • the thickness of the GaN layer in the stacked structure is about 5 nm, and the thickness of the AlGaN layer is about 5 nm.
  • step S4 of Embodiment 1 prepare a first p-type layer 407A, a second p-type layer 407B, and a third p-type layer in the first gate region, the second gate region, and the third gate region respectively. 407C.
  • step S4 of Embodiment 1 respectively manufacture the first Schottky gate contact metal 408A, the second Schottky gate contact metal 408B, the third Schottky gate contact metal 408C, the first source contact metal 409A, The second source contact metal 409B, the third source contact metal 409C, the first drain contact metal 310A, the second drain contact metal 310B, the third drain contact metal 310C, and so on.
  • the first Schottky gate contact metal 308A, the first source contact metal 309A and the first drain contact metal 310A cooperate to form the transistor unit A
  • the second Schottky gate contact metal 308B and the second source contact metal 308B are used to form the transistor unit A.
  • the metal 309B and the second drain contact metal 310B constitute the transistor unit B
  • the third Schottky gate contact metal 308C, the third source contact metal 309C and the third drain contact metal 310C constitute the transistor unit C.
  • the gate transfer characteristics of the GaN-based HEMT device in this embodiment were tested, and the average threshold voltage of transistor unit A was about 2.4V, the average threshold voltage of transistor unit B was about 1.3V, and the average threshold voltage of transistor unit C was about - 2.0V.
  • the MOCVD method is used to sequentially grow the AlN/AlGaN transition layer 502, the high-resistance (Al)GaN withstand voltage layer 503, the (Al)GaN conductive channel layer 504, and the AlGaN potential on the substrate 501.
  • step S2 of Embodiment 1 use photoresist as a mask, and after photolithography patterning, use ICP etching to remove the first gate region of the AlGaN barrier layer 505 along the thickness direction to form a groove. structure, and the groove structure is terminated on the surface of the (Al)GaN conductive channel layer 504, and the second gate region of the AlGaN barrier layer 505 is not etched.
  • insulating gate dielectric layer 506 such as aluminum nitride (with a thickness of about 1 to 20 nm) on the surface of the AlGaN barrier layer 505, and then refer to step S4 of Embodiment 1 to fabricate the first Schottky gate contact metal 508A and the second Schottky gate contact metal 508A, respectively.
  • the first and second Schottky gate contact metals are preferably metals with higher work functions such as Ni and Pd.
  • first Schottky gate contact metal 508A, the first source contact metal 509A, and the first drain contact metal 510A cooperate to form a transistor unit A with a high threshold voltage
  • second Schottky gate contact metal 508B, The second source contact metal 509B and the second drain contact metal 510B constitute the transistor cell B having a low threshold voltage.
  • the above embodiments of the present application achieve wafer-level preparation of high and low threshold voltage devices by accurately controlling the thickness of the barrier layer or dielectric layer in the gate region of the device.
  • the prepared multi-threshold voltage HEMT is highly integrated and has high carrier mobility.
  • the threshold voltage has good uniformity and can be used to implement functional circuits based on 1/2 logic.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本申请公开了一种具有多阈值电压的GaN基HEMT、其制备方法及应用。所述HEMT结构包括沟道层和势垒层，沟道层与势垒层之间形成有二维电子气；势垒层至少具有第一、第二源极区，第一、第二栅极区，以及第一、第二漏极区；第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元；第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元；势垒层在第一栅极区的厚度小于在第二栅极区的厚度，使第一HEMT单元的阈值电压高于第二HEMT单元的阈值电压。本申请可以实现高、低阈值电压HEMT器件的晶圆级制备，制得的多阈值电压HEMT高度集成，且载流子迁移率高、阈值电压均匀性好，可以很好地满足高低阈值型逻辑电路的应用需求。

Description

具有多阈值电压的GaN基HEMT结构、其制备方法及应用
本申请基于并要求于2022年7月7日递交的申请号为202210808044.1、发明名称为“具有多阈值电压的GaN基HEMT结构、其制备方法及应用”的中国专利申请的优先权。
技术领域
本申请涉及一种高电子迁移率晶体管(HEMT)器件结构，具体涉及一种具有多阈值电压的GaN基HEMT结构、其制备方法及应用，属于半导体技术领域。
背景技术
以GaN为代表的III族氮化物半导体被称为第三代半导体，具有禁带宽度大、化学稳定性好、击穿电压高等优势。而且由AlGaN/GaN等异质结构成的GaN基HEMT具有高电子浓度和迁移率的优势，在高频、高耐压、低导通电阻等方面表现优异，可用作各类电力转化系统、射频功放系统的核心器件，在消费电子、工业电子，以及汽车电子等应用领域具有广阔的前景。
在电力电子、射频电子等领域，为了实现某些特定功能，如信号降噪、运算放大等，通常需要在芯片内部集成逻辑性功能电路。在以硅为材料基础的现代大规模集成电路中，逻辑电路的基本单元由N-MOSFET(N沟道金属-氧化物-半导体场效应晶体管)和P-MOSFET(P沟道金属-氧化物-半导体场效应晶体管)两种器件构成，即C-MOS电路(互补型逻辑电路)，其具有低功耗、高集成度等优势。N-MOSFET是在p型硅材料上反型出电子作为导电沟道制备的场效应晶体管，而P-MOSFET则是在n型硅材料上反型出空穴作为导电沟道制备的场效应晶体管。然而在GaN基材料中，由于存在较多的缺陷态，非掺GaN常呈现出弱n型；而由于受主Mg杂质的不完全电离特性，p型材料则需要掺入较高浓度的Mg；此外，GaN中空穴的体迁移率非常低，通常在1～10cm 2/(V·s)。因此，由于GaN材料禁带宽度大，且缺乏可靠的栅极介质材料，利用半导体反型或强反型产生电子或空穴的方案很难实现，特别是产生具有高迁移率的空穴几乎不可能。
目前，在GaN体系中实现类N-MOSFET的方案主要是：利用AlGaN/GaN异质结极化效应诱导的二维电子气(2DEG)作为导电沟道，采用凹槽栅、p型栅等技术方案来实现阈值电压为正的增强型n-FET，以实现高电平开启、低电平关断的N-MOSFET特性；实现类 P-MOSFET的方案则主要是：利用p-GaN/AlGaN异质结极化效应诱导的二维空穴气作为导电沟道，采用凹槽栅、离子注入型栅等栅极技术来实现阈值电压为负的增强型p-FET，以实现低电平开启、高电平关断的P-MOS晶体管特性。然后将n-FET和p-FET串联构建互补型逻辑电路单元，最终实现相关的功能性电路设计和制造。然而，基于GaN的n-FET和p-FET的互补型逻辑电路(0/1逻辑)的制备仍存在很多技术难点。
目前在硅半导体技术中，有一种逻辑电路则是基于低、高阈值电压器件(1/2逻辑)的方案，请参阅图1。其利用具有不同阈值电压的增强型晶体管(n-FET 1和n-FET 2)制作逻辑电路功能单元，利用不同栅极电压下晶体管的开关态差异实现信号的运算处理。这种电路设计无需GaN基p-FET，可使逻辑电路具备快速运算能力。但是，高低阈值型逻辑电路需要在同一晶圆、甚至极小的区域内稳定、均匀地实现至少两种不同阈值电压的器件。
综上，现有GaN基互补型逻辑电路技术对于GaN基p-FET的性能要求和现有高低阈值型逻辑电路的技术要求，对当前GaN基HEMT器件制造来说，形成了很大的挑战。具体阐述如下：
其一，上述互补型逻辑电路技术中的GaN基p-FET通常利用的是p型GaN中的体空穴，或者是p-GaN/AlGaN界面处的二维空穴气，其迁移率非常低，常温下在10cm 2/(V·s)左右，最高不超过50cm 2/(V·s)，与AlGaN/GaN诱导的二维电子气通常在1500cm 2/(V·s)的迁移率相差巨大。然而，逻辑运算电路的极限计算速度与半导体材料中载流子的迁移率有着很强的关联，载流子迁移率越高，电路的极限计算速度越快。因此，以GaN基p-FET和n-FET构成的逻辑电路，极限计算速度会受限于二维空穴气的迁移率，很难发挥出GaN材料体系的优势。
其二，上述互补型逻辑电路技术中的GaN基p-FET需要高质量的p-GaN欧姆接触。然而，目前p-GaN欧姆接触的制备需要p-GaN表层重掺杂Mg至10 20cm -3以上，同时需要采用高功函数的金属，如Ni、Pd等。较为苛刻的制备条件下，接触电阻率也通常在10 -4Ω·cm 2以上，较高的接触电阻率会导致较大的功率损耗。此外，由于制备工艺的问题，p-GaN欧姆接触的热稳定性也较差，不适合严苛的工作环境。
其三，上述互补型逻辑电路技术中的p-FET栅极多通过刻蚀、离子注入等工艺制备，存在均匀性与可靠性的问题。采用GaN干法刻蚀的方法对p-FET栅极区进行减薄处理、或者采用离子注入对p-GaN进行受主补偿时，难以避免对GaN层造成晶格损伤和表面沾污，引入栅极界面态，造成阈值电压漂移、漏电大等器件性能恶化的问题，制备的p-FET性能难以满足逻辑运算的要求。
其四，上述高低阈值型逻辑电路技术要求在同一晶圆上实现高、低阈值电压的增强型器 件(如阈值电压＞1V和＞2V的器件)，并且要求极高的均匀性和可靠性，对于GaN基器件而言，目前并未有完善的解决方案。
发明内容
本申请的主要目的在于提供一种具有多阈值电压的GaN基HEMT结构及其制备方法，以克服现有技术中的不足。
为实现前述发明目的，本申请采用的技术方案包括：
本申请的一个方面提供了一种具有多阈值电压的GaN基HEMT结构，包括沟道层和势垒层，所述沟道层与势垒层之间形成有二维电子气；所述势垒层至少具有第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区；所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第一HEMT单元具有第一阈值电压；所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所述第二HEMT单元具有第二阈值电压；其中，所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，使所述第一阈值电压高于第二阈值电压。
本申请的另一个方面提供了一种具有多阈值电压的GaN基HEMT结构的制备方法，其包括：
在衬底上依次生长沟道层、势垒层；
至少在所述势垒层上定义出第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区，其中所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所述第一HEMT单元具有第一阈值电压，所述第二HEMT单元具有第二阈值电压；
并且，在生长所述势垒层时，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，或者，在所述势垒层生长完毕后，将所述势垒层的局部区域去除，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，从而使所述第一阈值电压高于第二阈值电压。
本申请的又一个方面提供了一种GaN基HEMT器件，其包含所述的具有多阈值电压的GaN基HEMT结构以及与所述HEMT结构配合的多个栅极、多个源极和多个漏极。
本申请的又一个方面提供了所述的具有多阈值电压的GaN基HEMT结构在制备高低阈值型逻辑电路中的用途。
相较于现有技术，首先，本申请能够在同一晶圆上实现具有两种以上阈值电压的增强型GaN基HEMT结构，制作工艺与常规III-V族半导体器件制备工艺兼容，适于工业化生产； 其次，所述GaN基HEMT的势垒层可为AlGaN/GaN/AlGaN复合结构，引入所述GaN插入层可作为所述第一栅极区刻蚀和热分解的牺牲层，能保证栅极区域AlGaN势垒层的厚度且有效去除刻蚀损伤，为阈值电压的均匀性及器件的可靠性形成良好保障；再者，本申请实现的两种阈值电压的增强型GaN HEMT形成配合的电路，相较于耗尽型/增强型GaN HEMT形成配合的电路，具有更低的功耗和更高的安全性；最后，本申请实现的两种增强型GaN HEMT均采用高迁移率的二维电子气作为导电沟道，具有快速开关的能力，以其配合制成的逻辑电路具有更快的计算速度和更强的抗干扰能力；因此，本申请能够很好地满足高低阈值型逻辑电路的应用需求。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中一种利用多阈值电压HEMT组成的逻辑单元的示意图；
图2是实施例1中一种GaN基HEMT器件的外延结构示意图；
图3是在图2所示外延结构的第一栅极区制作凹槽结构的示意图；
图4是在图3所示外延结构上二次外延P型层的示意图；
图5是在图4所示器件结构上制作P型栅的示意图；
图6是实施例1中一种GaN基HEMT器件的结构示意图；
图7是实施例2中一种GaN基HEMT器件的结构示意图；
图8是实施例3中一种GaN基HEMT器件的结构示意图；
图9是实施例4中一种GaN基HEMT器件的结构示意图；
图10是实施例5中一种GaN基HEMT器件的结构示意图。
具体实施方式
本申请的一些实施例提供的一种具有多阈值电压的GaN基HEMT结构包括沟道层和势垒层，所述沟道层与势垒层之间形成有二维电子气；所述势垒层至少具有第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区；所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第一HEMT单元具有第一阈值电压；所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所 述第二HEMT单元具有第二阈值电压；其中，所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，使所述第一阈值电压高于第二阈值电压。
在一个实施例中，所述势垒层还具有第三源极区、第三栅极区及第三漏极区；所述第三源极区、第三栅极区及第三漏极区相互配合，用于形成第三HEMT单元，所述第三HEMT单元具有第三阈值电压；所述势垒层在第二栅极区的厚度小于在第三栅极区的厚度，使所述第一阈值电压＞第二阈值电压＞第三阈值电压。
在本申请中，依据类似方式，还可以在所述势垒层上定义出除第一、第二、第三栅极区之外的其它栅极区，用于形成除第一、第二、第三HEMT单元之外的其它HEMT单元。其中通过使势垒层在不同栅极区有不同的厚度，从而对各个HEMT单元的阈值电压的高低进行调控，进而可以基于同一晶圆获得具有多阈值电压的GaN基HEMT结构，均匀性好、可靠性高。
在一个实施例中，所述HEMT结构还包括P型层，所述P型层设置在所述势垒层的多个栅极区上，用于降低或耗尽所述势垒层的多个栅极区下方的二维电子气。
进一步的，至少在所述势垒层的一个栅极区形成有凹槽结构，分布在该栅极区上的P型层至少部分填充入所述凹槽结构。
相较于现有GaN基p-FET，本申请的HEMT结构均为n-FET，仅利用在具有不同厚度势垒层的所述凹槽上外延生长p型帽层，以实现不同的阈值电压；因此，无需面临p-FET的p-GaN欧姆接触制备的难点，即：对p-GaN表层进行重掺杂、采用高功函数的金属、严苛工艺条件；也无需面临p-GaN材料中缺陷态浓度高，空穴迁移率低等问题。
在一个实施例中，所述势垒层包括依次设置在沟道层上的多个势垒层子层。
进一步的，至少在所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽口分布在势垒层表面，槽底分布在一个势垒层子层内部、相邻两个势垒层子层的界面处或者沟道层表面。
或者，至少在所述势垒层的一个栅极区形成有凹槽结构，所述势垒层包括第一势垒层子层和设置在第一势垒层子层上的第二势垒层子层，所述凹槽结构包括第一凹槽结构和第二凹槽结构，所述第一凹槽结构形成在第一势垒层子层内，所述第二势垒层子层的局部区域下凹进入第一凹槽结构，从而形成所述第二凹槽结构。
在一个实施例中，所述HEMT结构还包括至少一个插入层，所述插入层分布在两个势垒层子层之间。
在一个实施例中，至少在所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽 口分布在势垒层表面，槽底分布在一个插入层内部或者一个插入层与相邻势垒层子层的界面处。
示例性的，对势垒层进行刻蚀形成栅极凹槽时，可利用GaN插入层作为刻蚀和热分解的牺牲层，有效去除晶格损伤和表面沾污，且使热分解自动终止于下方AlGaN势垒层，从而可以避免因刻蚀引入栅极界面态而造成的阈值电压漂移、漏电大等器件性能恶化的问题，并保证第一栅极区或者第一栅极区和第二栅极区势垒厚度的一致性，进而提升器件阈值电压的均匀性。
在一个实施例中，至少在所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽口分布在势垒层表面，槽底分布在沟道层表面，并且至少在所述凹槽结构的内壁上覆设有连续的栅介质层，所述栅介质层用于将栅极与凹槽结构内壁分隔。
在一个实施例中，所述HEMT结构具体包括依次生长在衬底上的过渡层、耐压层、沟道层和势垒层。
本申请的一些实施例还提供了一种GaN基HEMT器件，其包括所述具有多阈值电压的GaN基HEMT结构以及与之配合的栅极、源极、漏极等。在其中的每一HEMT单元内，可以分别设置一栅极、一源极和一漏极。所述栅极、源极、漏极的材质、设置方式均是本领域技术人员已知的，此处不再予以详解说明。
另外，所述GaN基HEMT结构或所述GaN基HEMT器件中，还可包括其它结构层，例如钝化层、用于将多个HEMT单元电性隔离的结构等，同样的，其也是本领域技术人员已知的。
本申请的一些实施例提供的一种具有多阈值电压的GaN基HEMT结构的制备方法包括：
在衬底上依次生长沟道层、势垒层；
至少在所述势垒层上定义出第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区，其中所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所述第一HEMT单元具有第一阈值电压，所述第二HEMT单元具有第二阈值电压；
并且，在生长所述势垒层时，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，或者，在所述势垒层生长完毕后，将所述势垒层的局部区域去除，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，从而使所述第一阈值电压高于第二阈值电压。
在一个实施例中，所述的制备方法具体包括：在所述势垒层生长完毕后，至少对所述第一栅极区进行刻蚀，从而至少在所述第一栅极区形成凹槽结构。
在一个实施例中，所述的制备方法具体包括：先生长第一势垒层子层，并在第一势垒层子层的选定区域刻蚀出第一凹槽结构，所述选定区域对应于所述第一栅极区，再在第一势垒层子层上生长第二势垒层子层，使第二势垒层子层的局部区域下凹进入第一凹槽结构，并形成第二凹槽结构，从而形成所述势垒层。
在一个实施例中，所述的制备方法具体包括：在沟道层依次生长多个势垒层子层，并在至少两个势垒层子层之间生长插入层，从而形成所述势垒层。
在一个实施例中，所述的制备方法具体包括：在所述势垒层上生长P型层，使所述P型层的局部区域填充入所述凹槽结构，之后将所述P型层除栅极区之外的其余区域刻蚀去除，以将所述势垒层的多个栅极区下方的二维电子气降低或耗尽。
在一个实施例中，所述的制备方法具体包括：在所述势垒层上生长栅介质层，并使所述栅介质层至少连续覆盖所述凹槽结构的内壁。
在本申请中，可以利用本领域常用的干法刻蚀或湿法腐蚀工艺对势垒层进行刻蚀以形成所述的凹槽结构。
在本申请中，所述沟道层、势垒层、P型层、插入层等可以主要由III-V族半导体化合物，即GaN基材料形成，特别是由III族氮化物形成。例如，所述沟道层的材质可以是GaN等，势垒层的材质可以是AlGaN、AlInGaN等，P型层的材质可以是GaN、AlGaN等，插入层的材质可以是GaN等，且不限于此。所述栅介质层的材质可以包括氮化硅或氧化硅等，且不限于此。
在本申请中，所述过渡层、耐压层、沟道层和势垒层等可以利用本领域常用的HVPE(氢化物气相外延)、MOCVD(金属有机化学气相沉积)、PECVD(等离子体增强化学的气相沉积)等方式生长形成，且不限于此。
此外，所述制备方法还可以包括其它本领域已知的器件加工工序，比如在器件结构上制作表面钝化层，以及沉积介质层后进一步制作栅极、源极、漏极，以及在各个电极上沉积金属制备场板结构等，以形成最终的GaN基HEMT器件。
示例性的，在本申请的一个典型实施方式中，所述GaN基HEMT结构包含AlGaN/GaN异质结，并且是采用在有凹槽和无凹槽的AlGaN势垒层或GaN沟道层上二次外延p-GaN或AlGaN/p-GaN层的方法，然后图形化制备出两种以上p-GaN栅极，以此在同一晶圆上实现高、低阈值电压的增强型器件。
具体的，对于AlGaN势垒层的栅极凹槽区域来说，该区域的势垒层厚度较小，因此其AlGaN/GaN异质结诱导的二维电子气(2DEG)浓度较低，二次外延p-GaN或AlGaN/p-GaN 后，栅极下方的2DEG容易被耗尽，能带被抬得较高，将形成具有高阈值电压的HEMT单元；而对于AlGaN势垒层的无凹槽的栅极区，该区域的势垒层厚度较大，二次外延制备的p-GaN栅极由于势垒层厚，将形成具有低阈值电压的HEMT单元。两种HEMT单元的AlGaN势垒层厚度由高精度的MOCVD等加工设备等控制，阈值电压的均匀性具有保障。
本申请的工艺能够在同一晶圆上实现具有两种以上阈值电压的增强型GaN基HEMT结构，且与常规III-V族半导体器件制备工艺兼容，适于工业化生产，并能有效保障所述GaN基HEMT结构的阈值电压的均匀性及器件的可靠性等。
尤其是，当采用AlGaN/GaN/AlGaN复合结构作为所述GaN基HEMT的势垒层时，引入的GaN插入层可作为第一栅极区刻蚀和热分解的牺牲层，保证栅极区域AlGaN势垒层的厚度且有效去除刻蚀损伤，从而更为有效的保障器件阈值电压的均匀性及器件的可靠性。
本申请的一些实施例还提供了一种高低阈值型逻辑电路，其包含所述的具有多阈值电压的GaN基HEMT结构。该多种阈值电压的增强型GaN HEMT形成配合的电路，相较于耗尽型/增强型GaN HEMT形成配合的电路，具有更低的功耗和更高的安全性。同时，其中的多种增强型GaNHEMT均采用高迁移率的二维电子气作为导电沟道，具有快速开关的能力，以其配合制成的逻辑电路具有更快的计算速度和更强的抗干扰能力。
总之，本申请可以在GaN基晶圆上同时实现高均匀性的高低阈值电压增强型HEMT，并满足1/2逻辑电路的基础器件需求。同时，与现有p-FET相比，本申请的GaN基HEMT结构具有更高的可靠性。且相比于现有的互补型逻辑电路，利用本申请GaN基HEMT结构实现的逻辑电路利用具有高迁移率的二维电子气作为导电沟道，具有开关速度快，集成度高的特点。
以下将结合附图及若干实施例对本申请的技术方案进行更详细的描述，但应当理解，如下实施例仅仅是为了解释和说明该技术方案，但不限制本申请的范围。又及，若非特别说明，如下实施例中所采用的各种原料、反应设备、检测设备及方法等均是本领域已知的。
实施例1
请参阅图2-图6，本实施例提供的一种具有多阈值电压的GaN基HEMT器件的制备方法包括：
S1、采用金属有机气相沉积(MOCVD)的方法，在Si<111>衬底101上依次生长厚度约300nm的AlN/AlGaN过渡层102、厚度约4μm的C掺杂的Al 0.07Ga 0.93N高阻层103、厚度约150nm的非故意掺杂GaN层104、厚度约12nm的第一AlGaN势垒层子层105A、厚度约4nm的GaN插入层106A、厚度约4nm的第二AlGaN势垒层子层105B，如图2所示。第一AlGaN 势垒层子层105A和第二AlGaN势垒层子层105B组成势垒层。
S2、采用光刻胶作掩膜，光刻图形化后利用ICP刻蚀法将第二AlGaN势垒层子层105B的第一栅极区沿厚度方向刻蚀去除约6nm，形成凹槽结构，如图3所示。经过湿法表面处理和MOCVD高温热分解处理后，使凹槽结构终止于第一AlGaN势垒层子层105A表面，然后二次外延厚度约80nm的Mg掺杂浓度为2～5×10 19/cm 3的p型GaN层，如图4所示。
S3、采用光刻胶作为掩膜，光刻图形化后利用干法刻蚀法去除非栅极区的p-GaN层，使刻蚀停止在第一AlGaN势垒层子层105A表面，从而在第一栅极区制备出第一p-GaN层107A(亦可命名为第一P型栅)，在第二AlGaN势垒层子层105B的第二栅极区制备出第二p-GaN层107B(亦可命名为第二P型栅)，如图5所示。
S4、采用丙酮等有机清洗的方法去除光刻胶，测试得到两个P型栅的高度约为80nm。然后利用氢氟酸(HF)等去除势垒层表面的氧化层，在500℃、N 2气氛下快速退火以恢复AlGaN/GaN异质结处的二维电子气。然后在两个P型栅上沉积Ti/Au，退火后制备成第一肖特基栅接触金属108A、第二肖特基栅接触金属108B，并在势垒层的各个源极区、漏极区分别沉积Ti/Al/Ti/Au，分别形成第一源极接触金属109A、第二源极接触金属109B、第一漏极接触金属110A、第二漏极接触金属110B，退火后制备成欧姆接触。进而，由第一肖特基栅接触金属108A、第一源极接触金属109A和第一漏极接触金属110A配合形成具有高阈值电压的晶体管单元A，由第二肖特基栅接触金属108B、第二源极接触金属109B和第二漏极接触金属110B构成具有低阈值电压的晶体管单元B。
本实施例最终制得的GaN基HEMT器件的结构如图6所示。
采用I-V等方法对所述GaN基HEMT器件进行栅极转移特性测试，得到晶体管单元A的阈值电压均值约为2.1V，晶体管单元B的阈值电压均值约为1.3V。该测试结果证实，本实施例的方案可以同一晶圆上制备出具有高低阈值电压的p型栅增强型HEMT。
实施例2
本实施例提供的一种具有多阈值电压的GaN基HEMT器件的制备方法包括如下步骤：
S1、参考实施例1的步骤S1，采用MOCVD法在衬底201上依次生长AlN/AlGaN过渡层202、C掺杂的Al 0.07Ga 0.93N高阻层203、非故意掺杂GaN层204、厚度约18～25nm的AlGaN势垒层205A。
S2、参考实施例1的步骤S2，采用光刻胶作掩膜，光刻图形化后利用ICP刻蚀法将AlGaN势垒层205A的第一栅极区沿厚度方向刻蚀去除一部分(例如约6nm)，形成凹槽结构。经过湿法表面处理和MOCVD高温热分解处理后，使凹槽结构终止于AlGaN势垒层205A内的 一定深度处(槽槽槽底面距离沟道层8～20nm)，然后二次外延p型GaN层或p型AlGaN层(简称p型帽层)。
S3、参考实施例1的步骤S3，采用光刻胶作为掩膜，光刻图形化后利用干法刻蚀法去除非栅极区的p型帽层，使刻蚀停止在AlGaN势垒层205A表面，从而在第一栅极区制备出第一p型帽层207A(亦可命名为第一P型栅)，在AlGaN势垒层205A的第二栅极区制备出第二p型帽层207B(亦可命名为第二P型栅)。
S4、参考实施例1的步骤S4，采用丙酮等有机清洗的方法去除光刻胶，然后利用氢氟酸(HF)等去除势垒层表面的氧化层，之后快速退火以恢复AlGaN/GaN异质结处的二维电子气。然后在两个P型栅上沉积Ti/Au，退火后制备成第一肖特基栅接触金属208A、第二肖特基栅接触金属208B，并在势垒层的各个源极区、漏极区分别沉积Ti/Al/Ti/Au，分别形成第一源极接触金属209A、第二源极接触金属209B、第一漏极接触金属210A、第二漏极接触金属210B，退火后制备成欧姆接触。进而，由第一肖特基栅接触金属208A、第一源极接触金属209A和第一漏极接触金属210A配合形成具有高阈值电压的晶体管单元A，由第二肖特基栅接触金属208B、第二源极接触金属209B和第二漏极接触金属210B构成具有低阈值电压的晶体管单元B。
本实施例最终制得的GaN基HEMT器件的结构如图7所示。
对本实施例的GaN基HEMT器件进行栅极转移特性测试，得到晶体管单元A的阈值电压均值约为2.3V，晶体管单元B的阈值电压均值约为1.1V。
实施例3
本实施例提供的一种具有多阈值电压的GaN基HEMT器件的制备方法包括如下步骤：
S1、参考实施例1的步骤S1，采用MOCVD法在衬底301上依次生长AlN/AlGaN过渡层302、C掺杂的Al 0.07Ga 0.93N高阻层303、非故意掺杂GaN层304和厚度约2～10nm的第一AlGaN势垒层子层305A，再通过图形化刻蚀方式将该第一AlGaN势垒层子层305A的左侧栅极区全部去除，然后二次外延厚度约0～10nm的GaN层、厚度约5～15nm的AlGaN层和厚度约70nm的p-(Al)GaN层，形成一叠层结构305B(优选的，GaN层厚度约5nm，AlGaN厚度约10nm)。
S2、参考实施例1的步骤S2～S3，在叠层结构305B的第一栅极区制备出第一p型层307B(亦可命名为第一P型栅)，在叠层结构305B的第二栅极区制备出第二p型层307B(亦可命名为第二P型栅)。
S3、参考实施例1的步骤S4，分别制作第一肖特基栅接触金属308A、第二肖特基栅接 触金属308B、第一源极接触金属309A、第二源极接触金属309B、第一漏极接触金属310A、第二漏极接触金属310B等。进而，由第一肖特基栅接触金属308A、第一源极接触金属309A和第一漏极接触金属310A配合形成具有高阈值电压的晶体管单元A，由第二肖特基栅接触金属308B、第二源极接触金属309B和第二漏极接触金属310B构成具有低阈值电压的晶体管单元B。
本实施例最终制得的GaN基HEMT器件的结构如图8所示。
对本实施例的GaN基HEMT器件进行栅极转移特性测试，得到晶体管单元A的阈值电压均值约为2.3V，晶体管单元B的阈值电压均值约为1.3V。
实施例4
本实施例提供的一种具有多阈值电压的GaN基HEMT器件的制备方法包括如下步骤：
S1、参考实施例1的步骤S1，采用MOCVD法在衬底401上依次生长AlN/AlGaN过渡层402、C掺杂的Al 0.07Ga 0.93N高阻层403、非故意掺杂GaN层404、第一AlGaN势垒层子层405A、第一GaN插入层406A、第二AlGaN势垒层子层405B、第二GaN插入层406B、第三AlGaN势垒层子层405C；
S2、参考实施例1的步骤S2，采用光刻胶作掩膜，光刻图形化后利用ICP刻蚀法将AlGaN势垒层的第一栅极区、第二栅极区沿厚度方向刻蚀去除一部分，以分别形成第一凹槽结构、第二凹槽结构，第一凹槽结构的槽槽底面位于第一AlGaN势垒层子层405A表面，第二凹槽结槽槽槽底面位于第二AlGaN势垒层子层405B表面，对AlGaN势垒层的第三栅极区不进行刻蚀。
S3、在AlGaN势垒层上二次外延厚度约0～10nm的GaN层、厚度约0～10nm的AlGaN层和厚度约70nm的p-(Al)GaN层，形成一叠层结构(亦可认为是P型层)。优选的，该叠层结构中GaN层厚度约5nm，AlGaN厚度约5nm。
S4、参考实施例1的步骤S3，在第一栅极区、第二栅极区、第三栅极区分别制备出第一p型层407A、第二p型层407B、第三p型层407C。
S3、参考实施例1的步骤S4，分别制作第一肖特基栅接触金属408A、第二肖特基栅接触金属408B、第三肖特基栅接触金属408C、第一源极接触金属409A、第二源极接触金属409B、第三源极接触金属409C、第一漏极接触金属310A、第二漏极接触金属310B、第三漏极接触金属310C等。进而，由第一肖特基栅接触金属308A、第一源极接触金属309A和第一漏极接触金属310A配合形成晶体管单元A，由第二肖特基栅接触金属308B、第二源极接触金属309B和第二漏极接触金属310B构成晶体管单元B，由第三肖特基栅接触金属308C、 第三源极接触金属309C和第三漏极接触金属310C构成晶体管单元C。
本实施例最终制得的GaN基HEMT器件的结构如图9所示。
对本实施例的GaN基HEMT器件进行栅极转移特性测试，得到晶体管单元A的阈值电压均值约为2.4V，晶体管单元B的阈值电压均值约为1.3V，晶体管单元C的阈值电压均值约为-2.0V。
实施例5
本实施例提供的一种具有多阈值电压的GaN基HEMT器件的制备方法包括如下步骤：
S1、参考实施例1的步骤S1，采用MOCVD法在衬底501上依次生长AlN/AlGaN过渡层502、高阻(Al)GaN耐压层503、(Al)GaN导电沟道层504、AlGaN势垒层505。
S2、参考实施例1的步骤S2，采用光刻胶作掩膜，光刻图形化后利用ICP刻蚀法将AlGaN势垒层505的第一栅极区沿厚度方向刻蚀去除并形成凹槽结构，且使凹槽结构终止于(Al)GaN导电沟道层504表面，对于AlGaN势垒层505的第二栅极区则不进行刻蚀。
S3、在AlGaN势垒层505表面沉积氮化铝等绝缘栅介质层506(厚度约1～20nm)，之后参考实施例1的步骤S4，分别制作第一肖特基栅接触金属508A、第二肖特基栅接触金属508B、第一源极接触金属509A、第二源极接触金属509B、第一漏极接触金属510A、第二漏极接触金属510B等。其中第一、第二肖特基栅接触金属优选采用Ni、Pd等功函数较高的金属。进而，由第一肖特基栅接触金属508A、第一源极接触金属509A和第一漏极接触金属510A配合形成具有高阈值电压的晶体管单元A，由第二肖特基栅接触金属508B、第二源极接触金属509B和第二漏极接触金属510B构成具有低阈值电压的晶体管单元B。
本实施例最终制得的GaN基HEMT器件的结构如图10所示。
本申请以上实施例通过精确控制器件栅区势垒层或介质层的厚度，实现了高、低阈值电压器件的晶圆级制备，制备的多阈值电压HEMT高度集成，且载流子迁移率高、阈值电压均匀性好，可以用于实现基于1/2逻辑的功能电路。
应说明的是，以上所述仅为本申请的优选实施例而已，并不用于限制本申请，尽管参照前述实施例对本申请进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种具有多阈值电压的GaN基HEMT结构，包括沟道层和势垒层，所述沟道层与势垒层之间形成有二维电子气；其特征在于：所述势垒层至少具有第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区；所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第一HEMT单元具有第一阈值电压；所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所述第二HEMT单元具有第二阈值电压；其中，所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，使所述第一阈值电压高于第二阈值电压。
  2. 根据权利要求1所述的具有多阈值电压的GaN基HEMT结构，其特征在于：所述势垒层还具有第三源极区、第三栅极区及第三漏极区；所述第三源极区、第三栅极区及第三漏极区相互配合，用于形成第三HEMT单元，所述第三HEMT单元具有第三阈值电压；所述势垒层在第二栅极区的厚度小于在第三栅极区的厚度，使所述第一阈值电压＞第二阈值电压＞第三阈值电压。
  3. 根据权利要求1所述的具有多阈值电压的GaN基HEMT结构，其特征在于还包括P型层，所述P型层设置在所述势垒层的多个栅极区上，用于降低或耗尽所述势垒层的多个栅极区下方的二维电子气。
  4. 根据权利要求3所述的具有多阈值电压的GaN基HEMT结构，其特征在于：至少在所述势垒层的一个栅极区形成有凹槽结构，分布在该栅极区上的P型层至少部分填充入所述凹槽结构。
  5. 根据权利要求1所述的具有多阈值电压的GaN基HEMT结构，其特征在于：所述势垒层包括依次设置在沟道层上的多个势垒层子层。
  6. 根据权利要求5所述的具有多阈值电压的GaN基HEMT结构，其特征在于：至少在所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽口分布在势垒层表面，槽底分布在一个势垒层子层内部、相邻两个势垒层子层的界面处或者沟道层表面，
    或者，至少在所述势垒层的一个栅极区形成有凹槽结构，所述势垒层包括第一势垒层子层和设置在第一势垒层子层上的第二势垒层子层，所述凹槽结构包括第一凹槽结构和第二凹槽结构，所述第一凹槽结构形成在第一势垒层子层内，所述第二势垒层子层的局部区域下凹进入第一凹槽结构，从而形成所述第二凹槽结构；
    和/或，所述HEMT结构还包括至少一个插入层，所述插入层分布在两个势垒层子层之间。
  7. 根据权利要求6所述的具有多阈值电压的GaN基HEMT结构，其特征在于：至少在 所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽口分布在势垒层表面，槽底分布在一个插入层内部或者一个插入层与相邻势垒层子层的界面处。
  8. 根据权利要求1所述的具有多阈值电压的GaN基HEMT结构，其特征在于：至少在所述势垒层的一个栅极区形成有凹槽结构，所述凹槽结构的槽口分布在势垒层表面，槽底分布在沟道层表面，并且至少在所述凹槽结构的内壁上覆设有连续的栅介质层，所述栅介质层用于将栅极与凹槽结构内壁分隔。
  9. 根据权利要求1所述的具有多阈值电压的GaN基HEMT结构，其特征在于具体包括依次生长在衬底上的过渡层、耐压层、沟道层和势垒层。
  10. 一种具有多阈值电压的GaN基HEMT结构的制备方法，其特征在于包括：
    在衬底上依次生长沟道层、势垒层；
    至少在所述势垒层上定义出第一源极区及第二源极区、第一栅极区及第二栅极区、第一漏极区及第二漏极区，其中所述第一源极区、第一栅极区及第一漏极区相互配合，用于形成第一HEMT单元，所述第二源极区、第二栅极区及第二漏极区相互配合，用于形成第二HEMT单元，所述第一HEMT单元具有第一阈值电压，所述第二HEMT单元具有第二阈值电压；
    并且，在生长所述势垒层时，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，或者，在所述势垒层生长完毕后，将所述势垒层的局部区域去除，使所述势垒层在第一栅极区的厚度小于在第二栅极区的厚度，从而使所述第一阈值电压高于第二阈值电压。
  11. 根据权利要求10所述的具有多阈值电压的GaN基HEMT结构的制备方法，其特征在于具体包括：
    在所述势垒层生长完毕后，至少对所述第一栅极区进行刻蚀，从而至少在所述第一栅极区形成凹槽结构；
    或者，先生长第一势垒层子层，并在第一势垒层子层的选定区域刻蚀出第一凹槽结构，所述选定区域对应于所述第一栅极区，再在第一势垒层子层上生长第二势垒层子层，使第二势垒层子层的局部区域下凹进入第一凹槽结构，并形成第二凹槽结构，从而形成所述势垒层。
  12. 根据权利要求10或11所述的具有多阈值电压的GaN基HEMT结构的制备方法，其特征在于具体包括：在沟道层依次生长多个势垒层子层，并在至少两个势垒层子层之间生长插入层，从而形成所述势垒层。
  13. 根据权利要求11所述的具有多阈值电压的GaN基HEMT结构的制备方法，其特征在于具体包括：在所述势垒层上生长P型层，使所述P型层的局部区域填充入所述凹槽结构，之后将所述P型层除栅极区之外的其余区域刻蚀去除，以将所述势垒层的多个栅极区下方的 二维电子气降低或耗尽。
  14. 根据权利要求11所述的具有多阈值电压的GaN基HEMT结构的制备方法，其特征在于具体包括：在所述势垒层上生长栅介质层，并使所述栅介质层至少连续覆盖所述凹槽结构的内壁。
  15. 权利要求1-9中任一项所述具有多阈值电压的GaN基HEMT结构在制作高低阈值型逻辑电路中的用途。
PCT/CN2022/117566 2022-07-07 2022-09-07 具有多阈值电压的GaN基HEMT结构、其制备方法及应用 WO2024007443A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP22944072.2A EP4336563A1 (en) 2022-07-07 2022-09-07 Gan-based hemt structure having multiple threshold voltages, and preparation method therefor and application thereof
CA3209196A CA3209196A1 (en) 2022-07-07 2022-09-07 Gan-based hemt structure having multithreshold voltage, and preparation method and application therefor
JP2023548706A JP2024528764A (ja) 2022-07-07 2022-09-07 複数の閾値電圧を有するＧａＮ系ＨＥＭＴ構造、その製造方法および用途

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210808044.1 2022-07-07
CN202210808044.1A CN115172367A (zh) 2022-07-07 2022-07-07 具有多阈值电压的GaN基HEMT结构、其制备方法及应用

Publications (1)

Publication Number Publication Date
WO2024007443A1 true WO2024007443A1 (zh) 2024-01-11

Family

ID=83492769

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/117566 WO2024007443A1 (zh) 2022-07-07 2022-09-07 具有多阈值电压的GaN基HEMT结构、其制备方法及应用

Country Status (2)

Country Link
CN (1) CN115172367A (zh)
WO (1) WO2024007443A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117690925A (zh) * 2024-02-01 2024-03-12 浙江大学 GaN基器件的单片集成结构及其制备方法
CN118398494A (zh) * 2024-06-28 2024-07-26 合肥欧益睿芯科技有限公司 E/D集成的GaAs HEMT器件及其制造方法、电路和电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118299412A (zh) * 2023-01-04 2024-07-05 中兴通讯股份有限公司 一种氮化镓器件及氮化镓器件的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150162424A1 (en) * 2013-12-06 2015-06-11 International Re'ctifier Corporation Dual-Gated Group III-V Merged Transistor
CN107210323A (zh) * 2015-03-30 2017-09-26 德州仪器公司 常关型iii族氮化物晶体管
CN112185959A (zh) * 2020-08-28 2021-01-05 西安电子科技大学 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法
CN112599523A (zh) * 2019-10-01 2021-04-02 台湾积体电路制造股份有限公司 集成晶体管器件及形成其的方法
CN114038909A (zh) * 2021-10-22 2022-02-11 北京大学深圳研究生院 增强型氮化镓功率器件及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150162424A1 (en) * 2013-12-06 2015-06-11 International Re'ctifier Corporation Dual-Gated Group III-V Merged Transistor
CN107210323A (zh) * 2015-03-30 2017-09-26 德州仪器公司 常关型iii族氮化物晶体管
CN112599523A (zh) * 2019-10-01 2021-04-02 台湾积体电路制造股份有限公司 集成晶体管器件及形成其的方法
CN112185959A (zh) * 2020-08-28 2021-01-05 西安电子科技大学 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法
CN114038909A (zh) * 2021-10-22 2022-02-11 北京大学深圳研究生院 增强型氮化镓功率器件及其制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117690925A (zh) * 2024-02-01 2024-03-12 浙江大学 GaN基器件的单片集成结构及其制备方法
CN117690925B (zh) * 2024-02-01 2024-05-14 浙江大学 GaN基器件的单片集成结构及其制备方法
CN118398494A (zh) * 2024-06-28 2024-07-26 合肥欧益睿芯科技有限公司 E/D集成的GaAs HEMT器件及其制造方法、电路和电子设备

Also Published As

Publication number Publication date
CN115172367A (zh) 2022-10-11

Similar Documents

Publication Publication Date Title
US9252258B2 (en) CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof
US11362205B2 (en) Group III nitride enhancement-mode HEMT based on composite barrier layer structure and manufacturing method thereof
EP3520144B1 (en) Doped gate dielectric materials
CN108305834B (zh) 一种增强型氮化镓场效应器件的制备方法
WO2024007443A1 (zh) 具有多阈值电压的GaN基HEMT结构、其制备方法及应用
JP5678485B2 (ja) 半導体装置
US20160218204A1 (en) Enhancement Mode High Electron Mobility Transistor and Manufacturing Method Thereof
CN110112215B (zh) 兼具栅介质与刻蚀阻挡功能结构的功率器件及制备方法
JP5599089B2 (ja) 半導体装置、半導体装置の製造方法、半導体基板、および半導体基板の製造方法
JP2017157589A (ja) 半導体装置および半導体装置の製造方法
CN113394096B (zh) Hemt器件及其自隔离方法、制作方法
US20230290834A1 (en) ENHANCEMENT-MODE GaN HFET
CN113410297B (zh) MIS分裂栅GaN基高电子迁移率晶体管及其制备方法
US8350293B2 (en) Field effect transistor and method of manufacturing the same
CN111739800B (zh) 一种SOI基凹栅增强型GaN功率开关器件的制备方法
CN114843337A (zh) 双栅结构氮化镓高电子迁移率晶体管及其制作方法
US20230352599A1 (en) Semiconductor device
EP4336563A1 (en) Gan-based hemt structure having multiple threshold voltages, and preparation method therefor and application thereof
TW202121543A (zh) 二極體、二極體的製造方法及電氣機器
US20100127307A1 (en) Field effect transistor and method of manufacturing the same
CN116613065B (zh) 一种增强型氮化镓hemt器件及制造方法
CN116314320A (zh) 一种p型氮化镓晶体管及其制备方法
CN118263309A (zh) 具有p型半导体场板的增强型场效应晶体管及其制备方法
CN114864505A (zh) 一种GaN HEMT和GaOx MOSFET异构反相器的制备方法
CN117790563A (zh) 一种增强型GaN高电子迁移率晶体管及其制备方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2023548706

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2022944072

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022944072

Country of ref document: EP

Effective date: 20231208

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22944072

Country of ref document: EP

Kind code of ref document: A1