WO2024000644A1 - 测试电路、测试系统、测试方法和半导体器件 - Google Patents

测试电路、测试系统、测试方法和半导体器件 Download PDF

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Publication number
WO2024000644A1
WO2024000644A1 PCT/CN2022/105109 CN2022105109W WO2024000644A1 WO 2024000644 A1 WO2024000644 A1 WO 2024000644A1 CN 2022105109 W CN2022105109 W CN 2022105109W WO 2024000644 A1 WO2024000644 A1 WO 2024000644A1
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Prior art keywords
circuit
mirror
input terminal
signal
transistor
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PCT/CN2022/105109
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English (en)
French (fr)
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侯闯明
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长鑫存储技术有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a test circuit, a test system, a test method and a semiconductor device.
  • MOS metal-oxide-semiconductor field-effect transistor, metal-oxide-semiconductor field-effect transistor
  • PMOS and NMOS can be connected in series to form an inverter.
  • the inverter is a CMOS with an inverting effect.
  • the effective driving current of PMOS and NMOS in CMOS can assist in the analysis of CMOS.
  • the parasitic capacitance of CMOS can be analyzed based on the effective driving current to determine the impact of ion doping on the parasitic capacitance and resistance of CMOS, thereby obtaining a higher-speed circuit. .
  • the device width of PMOS and NMOS is usually adjusted so that the switching voltage of the logic gate composed of transistors is at half the operating voltage.
  • the gate, source and drain of the PMOS are drawn out separately to apply half the operating voltage to the source and gate.
  • the channel current measured at the drain can be as the effective drive current of PMOS.
  • the effective driving current of NMOS can be measured. It can be seen that the effective driving current can also be understood as the flip current.
  • Embodiments of the present disclosure provide a test circuit, a test system, a test method and a semiconductor device, which can improve the test accuracy of flip current.
  • an embodiment of the present disclosure provides a test circuit, including a ring oscillation circuit and a mirror circuit;
  • the ring oscillation circuit includes a plurality of first reverse units connected in sequence, each of the first reverse units includes a first input terminal and a first output terminal, and at least one of the first reverse units has A first input terminal and a first output terminal are connected to the mirror circuit;
  • the mirror circuit is used to receive a first voltage signal corresponding to the first input terminal of the first reverse unit and a second voltage signal corresponding to the first output terminal, and to When a level flip occurs at the first input terminal of the unit, the flip current of the transistor in the first reverse unit is mirrored according to the first voltage signal and the second voltage signal.
  • the mirror circuit includes a mirror control circuit and at least one mirror test circuit
  • the mirror control circuit includes at least one control signal output terminal.
  • the control signal output terminal is connected to the mirror test circuit in a one-to-one correspondence.
  • the mirror control circuit is used to transmit the signal to the mirror through the control signal output terminal.
  • the test circuit sends a mirror control signal, the mirror control signal is used to indicate the flip state of the first reverse unit;
  • Each of the mirror test circuits is also connected to a first input terminal and a first output terminal of one of the first reverse units, and the mirror test circuit is used to determine the first reverse unit according to the mirror control signal. Whether a level flip occurs at the first input terminal, and when a level flip occurs, the flip current of the transistor in the first reverse unit is mirrored according to the first voltage signal and the second voltage signal.
  • the mirror control circuit includes a plurality of second reverse units cascaded in sequence, and the number of the second reverse units is the same as the number of the first reverse units.
  • the mirror control circuit Work at the same power supply voltage as the ring oscillation circuit;
  • Each of the second inversion units includes a second input terminal, and at least one of the second input terminals serves as the control signal output terminal and is connected to the mirror test circuit for connecting all of the second inversion units.
  • the voltage signal of the second input terminal is sent to the mirror test circuit as the mirror control signal.
  • the mirror test circuit includes a mirror transistor and a test control circuit, and the test control circuit is respectively connected to the control signal output end, the first input end, the first output end and the mirror image transistor.
  • the transistor is connected, and the test control circuit is used to determine whether a level flip occurs at the first input terminal according to the mirror control signal sent by the mirror control circuit, and when a level flip occurs, according to all received
  • the first voltage signal and the second voltage signal control the operating voltage of the mirror transistor, so that the current of the mirror transistor is the same as the current of the transistor in the first reverse unit.
  • the test control circuit includes a selection signal generation circuit and a voltage control circuit
  • the selection signal generation circuit is connected to the mirror control circuit and the voltage control circuit.
  • the selection signal generation circuit is used to output a selection signal according to the mirror control signal sent by the mirror control circuit.
  • the selection signal is used to indicate Whether the level of the first input terminal is about to flip;
  • the voltage control circuit is connected to the selection signal generating circuit, the first input terminal, the first output terminal and the mirror transistor respectively, and the voltage control circuit is used when the selection signal indicates the first When a level flip occurs at an input terminal, the gate voltage signal of the mirror transistor is controlled to be consistent with the first voltage signal, and the drain voltage signal of the mirror transistor is controlled to be consistent with the second voltage signal.
  • the voltage control circuit includes a first selection circuit, a second selection circuit, and a first delay circuit
  • the control input terminal of the first selection circuit is connected to the selection signal generating circuit for receiving the selection signal;
  • the control input terminal of the second selection circuit is connected to the output terminal of the first delay circuit, and
  • the input end of the first delay circuit is connected to the output end of the selection signal generation circuit, and the control input end of the second selection circuit is used to receive the delayed selection signal;
  • One of the data input terminals of the first selection circuit is connected to the first input terminal, and the output terminal of the first selection circuit is connected to the gate of the mirror transistor for when the selection signal indicates that the When a level flip occurs at the first input terminal, the first voltage signal is used as the gate voltage signal of the mirror transistor;
  • One of the data input terminals of the second selection circuit is connected to the first output terminal, and the output terminal of the second selection circuit is connected to the drain of the mirror transistor for when the selection signal indicates that the When a level flip occurs at the first input terminal, the second voltage signal is used as the drain voltage signal of the mirror transistor.
  • the other data input end of the first selection circuit is connected to a power supply voltage signal, and the first selection circuit is also used to indicate that the selection signal indicates When the level of the first input terminal does not flip, the power supply voltage signal is used as the gate voltage signal of the mirror transistor;
  • the other data input terminal of the second selection circuit is grounded, and the second selection circuit is configured to switch the drain of the mirror transistor when the selection signal indicates that the level of the first input terminal does not flip. pole grounded.
  • the other data input terminal of the first selection circuit is connected to ground, and the first selection circuit is also used to indicate the first input when the selection signal indicates When the level of the terminal does not flip, the gate of the mirror transistor is controlled to be grounded;
  • the other data input terminal of the second selection circuit is connected to the power supply voltage signal.
  • the second selection circuit is also used to switch the level of the first input terminal when the selection signal indicates that the level of the first input terminal has not flipped.
  • the power supply voltage signal serves as the drain voltage signal of the mirror transistor.
  • the test circuit further includes: a second delay circuit, the input terminal of the second delay circuit and the enable input terminal of the mirror control circuit are connected to the same enable signal, and the second delay circuit The circuit is used to delay the received enable signal for a preset time and then output it to the enable input end of the ring oscillation circuit through the output end of the second delay circuit.
  • the second delay circuit is The oscillation signal generated by controlling the ring oscillation circuit lags behind the mirror control signal generated by the mirror control circuit.
  • the second delay circuit includes an even number of cascaded inverters.
  • the selection signal generation circuit includes a NOR gate and an inverter circuit, and the two input terminals of the NOR gate are respectively connected to the second input terminal of the second inverter unit and the inverter circuit.
  • the output end of the circuit is connected, and the input end of the inverter circuit is connected to the second input end of the second inversion unit.
  • the selection signal is a high level signal, it indicates the level of the first input end. Toggle from high level to low level.
  • the selection signal generation circuit includes a NAND gate and an inverter circuit, and the two input terminals of the NAND gate are respectively connected to the second input terminal of the second inverter unit and the inverter circuit.
  • the output end of the circuit is connected, and the input end of the inverter circuit is connected to the second input end of the second inversion unit.
  • the selection signal is a low level signal, it indicates the level of the first input end. Toggle from low level to high level.
  • the inverter circuit includes an odd number of cascaded inverters.
  • the first inversion unit at the first stage includes a first NAND gate, and the remaining first inversion units include a first NOT gate.
  • the two input terminals of the first NAND gate are respectively As the enable input end of the ring oscillation circuit and the first input end of the first inversion unit, the output end of the first NAND gate serves as the first output end of the first inversion unit.
  • the input terminal and the output terminal of the first NOT gate serve as the corresponding first input terminal and the first output terminal of the first inversion unit respectively.
  • the second inversion unit in the first stage includes a second NAND gate, and the remaining second inversion units include a second NOT gate.
  • the two input terminals of the second NAND gate are respectively As the enable input end of the mirror control circuit and the second input end of the second inversion unit, the output end of the second NAND gate serves as the second output end of the second inversion unit.
  • the input terminal and the output terminal of the second NOT gate serve as the second input terminal and the second output terminal of the corresponding second inversion unit respectively.
  • the first NOT gate and the second NOT gate each include a first transistor and a second transistor of different types, and the power input terminal of the first NAND gate and the power input terminal of the first transistor The sources are all connected to the same power supply voltage signal;
  • the gate of the first transistor is connected to the gate of the second transistor and serves as the input of the corresponding NOT gate. terminal; the drain of the first transistor is connected to the drain of the second transistor and serves as the output terminal of the corresponding NOT gate, and the source of the second transistor is grounded.
  • the source of the mirror transistor and the first reverse unit are connected to the same power supply voltage signal; when the mirror transistor is an NMOS tube, The source of the mirror transistor is connected to ground.
  • the first delay circuit includes an odd number of cascaded inverters.
  • an embodiment of the present disclosure provides a test system, including an enable signal generating circuit and the test circuit of the first aspect, the output end of the enable signal generating circuit is connected to the test circuit, and the enable signal generating circuit is connected to the test circuit.
  • the enable signal generated by the signal generating circuit is used to drive the test circuit to operate.
  • a frequency dividing element and an output buffer element are further included.
  • the input end of the frequency dividing element is connected to one of the first output ends of the ring oscillation circuit of the test circuit.
  • the output buffer element is connected to the The output terminal connection of the frequency dividing component.
  • embodiments of the present disclosure provide a testing method for the testing system of the second aspect, where the testing method includes:
  • equivalent parameters of the transistors in the first reverse unit of the ring oscillation circuit are determined, and the equivalent parameters include at least one of the following: equivalent capacitance and equivalent resistance.
  • embodiments of the present disclosure provide a semiconductor device, including the testing system of the second aspect.
  • the test circuit, test system, test method and semiconductor device provided by the embodiments of the present disclosure can mirror the current of the transistor in the first reverse unit through the mirror circuit. In this way, the current between different transistors in a first reverse unit can be removed, which helps to improve the accuracy of testing the flip current.
  • Figure 1 is a schematic structural diagram of a ring oscillation circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic current diagram between adjacent inverters in the ring oscillation circuit shown in Figure 1 provided by an embodiment of the present disclosure
  • Figure 3 is another current schematic diagram between adjacent inverters in the ring oscillation circuit shown in Figure 1 provided by an embodiment of the present disclosure
  • Figure 4 is a schematic structural diagram of a test circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a ring oscillation circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of another test circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of the mirror test circuit in Figure 6 provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of the mirror test circuit when the mirror transistor provided by the embodiment of the present disclosure is a PMOS transistor;
  • Figure 9 is a schematic structural diagram of the mirror test circuit when the mirror transistor provided by the embodiment of the present disclosure is an NMOS transistor;
  • Figure 10 is a signal timing diagram of the mirror test circuit shown in Figure 8 provided by an embodiment of the present disclosure.
  • Figure 11 is a signal timing diagram of the mirror test circuit shown in Figure 9 provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of a test system provided by an embodiment of the present disclosure.
  • Figure 13 is a step flow chart of a testing method provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a ring oscillation circuit provided by an embodiment of the present disclosure.
  • a ring oscillation circuit can be obtained by connecting multiple cascaded inverters.
  • the example in Figure 1 shows a ring oscillation circuit composed of five inverters cascaded.
  • the ring oscillation circuit The number of inverters included in the oscillation circuit is not limited.
  • the specific structure of one of the inverters is marked in detail in Figure 1.
  • the structures of the other inverters are the same and are not marked in Figure 1.
  • each stage of inverter is connected to the input end of the next stage inverter, thus forming a ring oscillation circuit.
  • Each inverter in Figure 1 is obtained by connecting PMOS and NMOS.
  • the gate G of PMOS is connected to the gate G of NMOS, and the two connected gates G serve as the input terminals of the inverter.
  • the drain D of the PMOS is connected to the drain D of the NMOS, and the two connected drains D serve as the output terminals of the inverter.
  • the source S of the PMOS is connected to the power supply voltage signal VDD, and the source S of the NMOS is connected to the ground GND.
  • the output terminal of some inverters has a level flip from high level to low level, and the output terminal of another part of the inverter has a level flip from low level to high level.
  • Flat flip In this way, the moment of level flipping can be accurately captured, so that the current at that moment can be used as the flipping current.
  • FIG. 2 is a schematic current diagram between adjacent inverters in the ring oscillation circuit shown in FIG. 1 provided by an embodiment of the present disclosure.
  • the PMOS in the previous stage inverter gradually conducts and generates current I1.
  • the current I1 flows through the common gate of the NMOS and PMOS of the subsequent inverter. Under the action of current I1, the gate voltage of the NMOS of the subsequent inverter increases.
  • FIG. 3 is another current schematic diagram between adjacent inverters in the ring oscillation circuit shown in FIG. 1 provided by an embodiment of the present disclosure.
  • the NMOS in the previous stage inverter when the level V of the input terminal of the previous stage inverter flips from low level to high level, the NMOS in the previous stage inverter gradually conducts and generates current I3.
  • the current I3 reduces the level of the common gate of the subsequent stage inverter to 0.
  • the PMOS in the previous stage inverter is not completely cut off, and there will still be a part of the current I4 flowing from the PMOS of the previous stage inverter through the NMOS of the previous stage inverter to the ground terminal GND.
  • Current I3 and current I4 flow into GND together, so the flip current of NMOS measured at the GND port is larger.
  • embodiments of the present disclosure consider mirroring the flip current in the transistor through a mirror circuit.
  • the current measured in this way only includes the current flowing through the transistor, and does not include the current flowing through the two transistors in the same inverter when they are in the on state at the same time.
  • the measured flip current is more accurate.
  • FIG. 4 is a schematic structural diagram of a test circuit provided by an embodiment of the present disclosure.
  • the test circuit 100 includes a ring oscillation circuit 101 and a mirror circuit 102 .
  • the ring oscillation circuit 101 includes a plurality of first reverse units 1011 connected in sequence.
  • Each first reverse unit 1011 includes a first input terminal and a first output terminal.
  • At least one first reverse unit The first input terminal and the first output terminal of 1011 are both connected to the mirror circuit 102 .
  • the mirror circuit 102 is configured to receive a first voltage signal corresponding to the first input terminal of the first inversion unit 1011 and a second voltage signal corresponding to the first output terminal, and generate a voltage signal at the first input terminal of the first inversion unit 1011.
  • the flipping current of the transistor in the first reverse unit 1011 is mirrored according to the first voltage signal and the second voltage signal.
  • the above-mentioned first reverse unit may be any unit with a reverse function, including but not limited to: NOT gate, NAND gate, NOR gate, XOR gate, XOR gate, controllable NOT gate, etc.
  • the NOT gate can be one of PMOS tube, NMOS tube and CMOS tube.
  • the ring oscillation circuit 101 in Figure 4 exemplifies five first reverse units 1011. However, in actual applications, the number of first reverse units only needs to be an odd number. The number of first reverse units does not matter here. be restricted.
  • Figure 4 illustrates a first reverse unit 1011 connected to the mirror circuit 102, but in actual applications there may be multiple first reverse units 1011 connected to the mirror circuit 102 to test the first reverse connection.
  • the first reverse unit 1011 is used to reverse process the first voltage signal at the first input terminal and then output it through the first output terminal.
  • the output voltage signal is called a second voltage signal.
  • each first inversion unit 1011 can be a NOT gate, which can be called a first NOT gate, so that each first inversion unit 1011 The first input terminal of is the input terminal of the first NOT gate, and the first output terminal of each first inversion unit 1011 is the output terminal of the first NOT gate. In this way, the output terminal of each first NOT gate of the ring oscillation circuit is connected to the input terminal of the first NOT gate of the next stage.
  • the structure of the first-stage reverse unit may be different from the structures of the remaining first reverse units 1011 .
  • Figure 5 is a schematic structural diagram of a ring oscillation circuit provided by an embodiment of the present disclosure.
  • the first-stage first inversion unit 1011 may be the first NAND gate 10112 in FIG. 5
  • the remaining first inversion units 1011 may be composed of the first NAND gate 10111 in FIG. 5 .
  • An input terminal of the first NAND gate 10112 serves as an enable input terminal of the ring oscillation circuit 101 .
  • the other input terminal of the first NAND gate 10112 serves as the first input terminal corresponding to the first inversion unit 1011
  • the output terminal of the first NAND gate 10112 serves as the first output terminal of the first inversion unit 1011
  • the input terminal and the output terminal of the first NOT gate 10111 serve as the first input terminal and the first output terminal of the corresponding first inversion unit 1011 respectively.
  • the connection between the first reverse units 1011 is the connection between the above-mentioned first NAND gate 10112 and the first NOT gate 10111 .
  • the output terminal of the first NAND gate 10112 is connected to the input terminal of the first NAND gate 10111 in the first inversion unit 1011 of the second stage.
  • the other input terminal of the first NAND gate 10112 is connected to the output terminal of the first NOT gate 10111 in the first inversion unit 1011 of the last stage, and the output terminals of the remaining first NOT gates 10111 are connected to the first NOT gate of the next stage. 10111 input connection.
  • the enable input terminal in Figure 5 is used to control the oscillation of the ring oscillation circuit 101.
  • the enable signal is a low-level signal.
  • the ring oscillation circuit 101 shown in FIG. 5 does not oscillate.
  • the enable signal is a high-level signal
  • the ring oscillation circuit 101 shown in FIG. 5 starts to oscillate, that is to say, the first NOT gate 10111 starts to work, and the level of the first input terminal undergoes a level flip.
  • the flip current can be tested.
  • the embodiment of the present disclosure can combine the enable signal and the first NAND gate 10112 to flexibly control the oscillation of the ring oscillation circuit 101.
  • the enable signal can be used to control the ring oscillation circuit 101 to stop. Oscillation helps save electricity.
  • the above-mentioned first NOT gate 10111 may be an inverter including first transistors and/or second transistors of different types.
  • the first transistor may be a PMOS transistor
  • the second transistor may be an NMOS transistor, or It can be a TTL (Transistor-Transistor Logic, transistor-transistor logic) inverter.
  • the power input terminal of the first NAND gate 10112 in the ring oscillation circuit 101 and the source of the first transistor of each first NOT gate 10111 are connected to the same power supply voltage signal VDD to supply the ring oscillation circuit 101 Provide power.
  • VDD voltage signal
  • the gate G of the first transistor PMOS is connected to the gate G of the second transistor NMOS, and serves as the input terminal of the corresponding first NOT gate 10111, that is, the corresponding The first input terminal of the first inversion unit 1011.
  • the drain D of the first transistor PMOS is connected to the drain D of the second transistor NMOS, and serves as the output terminal of the corresponding first NOT gate 10111, that is, the first output terminal of the corresponding first reverse unit 1011, and the second The source S of the transistor is connected to ground.
  • first NOT gate 10111 in the second-level first inversion unit 1011 is marked in Figure 5 .
  • the structures of the other first NOT gates 10111 are the same and are not marked in Figure 5 .
  • FIG. 6 is a schematic structural diagram of another test circuit provided by an embodiment of the present disclosure.
  • the mirror circuit 102 may include: a mirror control circuit 1021 and at least one mirror test circuit 1022 .
  • the mirror control circuit 1021 is used to control the mirror test circuit 1022 to mirror flip current. In this way, the independent operation of the mirror control and the mirror test can be realized, which improves the modularity of the mirror circuit 102 and facilitates the management and maintenance of the mirror circuit 102 .
  • Figure 6 illustrates one mirror test circuit 1022, but in actual applications, there can be multiple mirror test circuits, and the number of mirror test circuits is at most the same as the number of first NOT gates 10111 to perform The transistor in gate 10111 is mirrored and its flip current is tested.
  • the above-mentioned mirror control circuit 1021 may include at least one control signal output terminal.
  • the control signal output terminal is connected to the mirror test circuit 1022 in a one-to-one correspondence.
  • the mirror control circuit 1021 is used to send a mirror control signal to the mirror test circuit 1022 through the control signal output terminal.
  • the mirror control signal is used to indicate the flip state of the first reverse unit 1011.
  • Each mirror test circuit 1022 is also connected to a first input terminal and a first output terminal of a first inversion unit 1011, that is, the input terminal and output terminal of at least one first NOT gate 10111 in FIG. 6 .
  • the mirror test circuit 1022 is used to determine whether a level flip occurs at the first input terminal of the first reverse unit 1011 according to the mirror control signal, and when a level flip occurs, mirror the first reverse image according to the first voltage signal and the second voltage signal. Flip current to the transistor in cell 1011. When level flipping does not occur, the mirror test circuit 1022 may not mirror the flipping current, thereby saving power.
  • the transistor that the mirror test circuit 1022 wants to mirror the flip current is the transistor in the first NOT gate 10111.
  • the embodiment of the present disclosure can set a corresponding mirror test circuit 1022 for each first reverse unit 1011, so that different mirror test circuits 1022 can perform independent tests, avoid coupling between different mirror test circuits 1022, and help Improve test accuracy.
  • the mirror control circuit 1021 is used to generate the mirror control signal
  • the mirror test circuit 1022 is used to perform mirroring according to the mirror control signal. This helps to improve the integration level of the circuit and facilitate circuit management and maintenance.
  • the above-mentioned mirror control circuit 1021 may be a mirror circuit of the ring oscillation circuit 101, with the same structure as the ring oscillation circuit 101.
  • the reverse unit in the mirror control circuit 1021 may be called a second reverse unit.
  • the second input terminal of the inverting unit is called a second input terminal
  • the second output terminal of the second inverting unit is called a second output terminal.
  • the mirror control circuit 1021 may include a plurality of second reverse units cascaded in sequence.
  • Each second inversion unit includes a second input terminal.
  • the second input terminal serves as a control signal output terminal and is connected to the mirror test circuit 1022 for sending the voltage signal of the second input terminal of the second inversion unit as a mirror control signal.
  • Mirror test circuit 1022 is
  • the working state of the mirror control circuit 1021 needs to be the same as the working state of the ring oscillation circuit 101 .
  • the number of second reverse units may be the same as the number of first reverse units 1011.
  • the mirror control circuit 1021 and the ring oscillation circuit 101 work at the same power supply voltage, so that the ring oscillation circuit 101 and the mirror control The operating voltage of the circuit 1021 is consistent, thus ensuring that the mirror control circuit 1021 and the oscillation frequency are consistent with the oscillation frequency of the ring oscillation circuit 101.
  • the mirror control circuit 1021 may not include the second NAND gate 10212.
  • Each second reverse unit in the mirror control circuit 1021 Both are composed of the second NOT gate 10211.
  • the mirror control circuit 1021 may also include a second NAND gate 10212.
  • the first-stage second inversion unit includes a second NAND gate 10212, and the remaining second inversion units include a second NOT gate 10211.
  • the two input terminals of the second NAND gate 10212 serve as the enable input terminal of the mirror control circuit 1021 and the second input terminal of the second inversion unit, and the output terminal of the second NAND gate 10212 serves as the third input terminal of the second inversion unit.
  • the input terminal and the output terminal of the second NOT gate 10211 are respectively used as the second input terminal and the second output terminal of the corresponding second inversion unit, and the second input terminal can be used as the control signal output terminal.
  • the above-mentioned second NAND gates 10211 each include a first transistor PMOS and a second transistor NMOS of different types.
  • the power input terminal of the second NAND gate 10212 and the source S of the second transistor NMOS are both connected to the same power supply voltage signal. VDD.
  • the gate G of the first transistor PMOS is connected to the gate G of the second transistor NMOS, and serves as the input terminal of the corresponding second NOT gate 10211, that is, the third inverting unit of the second inversion unit. Two input terminals.
  • the drain D of the first transistor PMOS is connected to the drain D of the second transistor NMOS, and serves as the output end of the corresponding second NOT gate 10211, that is, the second output end of the corresponding second reverse unit.
  • the second transistor The source S of NMOS is connected to ground.
  • the mirror control circuit 1021 and the ring oscillation circuit 101 in the embodiment of the present disclosure have the same structure and have the same working status. In this way, the mirror control signal output by the mirror control circuit 1021 can accurately indicate the level flip state of the first reverse unit 1011 in the ring oscillation circuit 101, which helps to improve the test accuracy of the flip current.
  • the above-mentioned mirror control circuit 1021 needs to generate a control signal to enable the mirror test circuit 1022 to perform mirroring, and this process requires a certain amount of time.
  • the oscillation of the mirror control circuit 1021 can be lagged behind the oscillation of the ring oscillation circuit 101.
  • the above-mentioned test circuit 100 may further include: a second delay circuit 103 .
  • the input terminal of the second delay circuit 103 and the enable input terminal of the mirror control circuit 1021 are connected to the same enable signal. That is to say, the enable input terminal of the mirror control circuit 1021 is the second NAND gate 10212 of the mirror control circuit 1021 an input terminal.
  • the other input terminal of the second NAND gate 10212 is connected to the output of the second NAND gate 10211 of the second inversion unit of the last stage.
  • the second delay circuit 103 is used to delay the received enable signal for a preset time, and then output it to the enable input end of the ring oscillation circuit 101 through the output end of the second delay circuit 103.
  • the second delay circuit 103 is used to control the ring oscillation circuit.
  • the oscillation signal generated by the oscillation circuit 101 lags behind the mirror control signal generated by the mirror control circuit 1021 .
  • the preset time can be set according to actual circuit design needs, so as to make the mirror control signal arrive at the mirror test circuit 1022 earlier than the first voltage signal as much as possible, so that the mirror control signal can predict or indicate the corresponding first reverse unit.
  • the changing trend of the first voltage signal controls the gate and drain of the mirror transistor to connect to the voltage signal corresponding to the transistor in the first reverse unit before the first voltage signal flips, which can ensure the accuracy of the mirror test circuit 1022 of mirror flip current.
  • the above-mentioned second delay circuit 103 can be composed of any logic circuit, so that the processing process of the logic circuit can consume a long time to achieve the purpose of delay.
  • the input and output signals of the second delay circuit 103 must be the same, so that the working state of the ring oscillation circuit 101 at time t can be consistent with the working state of the mirror control circuit 1021 at time t+T.
  • T is the preset time for the second delay circuit 103 to delay the enable signal. In this way, not only can the mirror control signal arrive at the mirror test circuit 1022 earlier than the first voltage signal as much as possible, but the level flip state of the corresponding first voltage signal can also be accurately indicated through the mirror control signal, which helps to further improve the mirror image. Test circuit 1022 for mirroring accuracy of flip current.
  • the above-mentioned second delay circuit 103 may include an even number of cascaded inverters, the input of the first-stage inverter is used as the input of the second delay circuit 103, and the output of the first-stage inverter is connected with the next The input of the first-stage inverter is connected, and the output of the last-stage inverter is used as the output of the second delay circuit 103 .
  • the signal input to the second delay circuit 103 undergoes an even number of inversions to obtain the same signal as the input signal.
  • each inverter requires a certain amount of time to process the signal, so delays can be achieved.
  • the number of inverters in the second delay circuit 103 may be positively correlated according to the aforementioned preset time to be delayed.
  • the preset time is larger, the number of inverters is larger.
  • the number of inverters in the second delay circuit 103 is smaller.
  • the second delay circuit 103 can be formed by inverters, and the preset time of the delay can be adjusted according to the number of inverters, which helps to improve the adjustment flexibility of the preset time.
  • FIG. 7 is a schematic structural diagram of the mirror test circuit in FIG. 6 provided by an embodiment of the present disclosure.
  • the mirror test circuit 1022 may include a mirror transistor and a test control circuit.
  • the test control circuit is connected to the control signal output terminal of the mirror control circuit 1021, the input terminal of the first NOT gate 10111 (that is, the first input terminal), the output terminal of the first NOT gate 10111 (that is, the first output terminal) and the mirror image respectively. Transistor connection.
  • the control signal output terminal of the mirror control circuit 1021 is also the second input terminal in FIG. 7 . Based on these connections, the test control circuit can receive the mirror control signal from the mirror control circuit 1021 to determine whether a level flip occurs at the first input terminal.
  • the test control circuit may also receive a first voltage signal from a first input terminal and a second voltage signal from a second input terminal.
  • the test control circuit determines that a level flip occurs in the level of the first input terminal according to the mirror control circuit 1021, the test control circuit can control the working voltage of the mirror transistor according to the first voltage signal and the second voltage signal, so that the current of the mirror transistor is consistent with the third voltage signal.
  • the currents of the transistors in a reverse unit 1011 are the same.
  • the mirror transistor is the same transistor as one of the transistors in the first NOT gate 10111.
  • the mirror transistor may be a PMOS transistor to mirror the current of the PMOS transistor in the first NOT gate 10111 .
  • the mirror transistor in the second inverter 10211 includes an NMOS transistor, the mirror transistor may be an NMOS transistor to mirror the current of the first invertor NMOS transistor.
  • test control circuit can control the mirror transistor to turn off to save power.
  • the embodiment of the present disclosure can control the mirror transistor to have the same working state as the transistor in the first NOT gate 10111 through the test control circuit. In this way, the mirroring of the current can be realized, so that the mirror transistor can accurately mirror the current in the first NOT gate 10111. transistor current.
  • the above test control circuit may further include a selection signal generation circuit and a voltage control circuit.
  • the selection signal generation circuit is connected to the second input end of the mirror control circuit 1021 and the voltage control circuit.
  • the selection signal generation circuit is used to receive the mirror control signal sent by the mirror control circuit 1021 and output the selection signal according to the mirror control signal.
  • the selection signal is used to indicate whether the level of the first input terminal is about to undergo a level flip, including but not limited to: indicating that a level transition occurs when the selection signal is high level, and indicating that a level transition occurs when the selection signal is low level.
  • the embodiments of the present disclosure do not limit it.
  • the voltage control circuit is respectively connected to the selection signal generating circuit, the first input terminal, the first output terminal and the mirror transistor. In this way, the voltage control circuit can receive the selection signal generating circuit, the first voltage signal at the first input terminal, and the second voltage signal at the first output terminal.
  • the voltage control circuit is used to control the gate voltage signal of the mirror transistor to be consistent with the first voltage signal, and the drain voltage signal of the mirror transistor to be consistent with the second voltage signal when the selection signal indicates that a level flip occurs at the first input terminal.
  • the selection signal indicates that the flip current of the transistor in the first reverse unit needs to be mirrored.
  • the voltage control circuit controls the gate and drain voltages of the mirror transistor according to the selection signal to be the same as the gate and drain voltages of the transistor in the first reverse unit to be mirrored, thereby realizing mirroring of the transistor current.
  • the oscillation frequency of the mirror control circuit is the same as that of the ring oscillation circuit, and due to the enable signal control of the second delay circuit 103, the oscillation signal of the mirror control circuit is earlier than the oscillation signal of the ring oscillation circuit by a preset time, That is, the signal change at the second input terminal of the second reverse unit in the mirror control circuit is earlier than the signal change at the first input terminal of the corresponding first reverse unit in the ring oscillation circuit. Therefore, the second input terminal of the second reverse unit
  • the corresponding mirror control signal can indicate the changing trend of the first voltage signal, and control the first selection circuit and the second selection circuit to change the gate of the first reverse unit when a flip occurs earlier than the first reverse unit.
  • the first voltage signal and the second voltage signal at the drain are given to the mirror transistor.
  • the first voltage signal is the gate voltage signal of the PMOS and NMOS in the first NOT gate 10111
  • the second voltage signal is the drain voltage signal of the PMOS and NMOS in the first NOT gate 10111.
  • the mirror transistor is a PMOS transistor
  • the source of the mirror transistor and the first reverse unit 1011 are connected to the same power supply voltage signal.
  • the working voltage of each pole of the mirror transistor is the same as the working voltage of each pole of the PMOS in the first NOT gate 10111, thereby making the mirror transistor and the PMOS in the first NOT gate 10111 be in the same working state, thus ensuring that the mirror transistor
  • the accuracy of mirroring the flip current of the PMOS in the first NOT gate 10111 helps to improve the accuracy of the flip current of the PMOS transistor.
  • the mirror transistor is an NMOS transistor
  • the source of the mirror transistor is grounded.
  • the working voltage of each pole of the mirror transistor is the same as the working voltage of each pole of the NMOS in the first NOT gate 10111, thereby making the mirror transistor and the NMOS in the first NOT gate 10111 be in the same working state, thereby ensuring that the mirror transistor
  • the accuracy of mirroring the flip current of the NMOS in the first NOT gate 10111 helps to improve the accuracy of the flip current of the NMOS transistor.
  • the above voltage control circuit may further include a first selection circuit, a second selection circuit and a first delay circuit.
  • the first selection circuit is used to control the gate voltage signal of the mirror transistor
  • the second selection circuit is used to control the drain voltage signal of the mirror transistor.
  • control input end of the first selection circuit is directly connected to the selection signal generating circuit for receiving the selection signal.
  • the control input terminal of the second selection circuit is connected to the output terminal of the first delay circuit, and the input terminal of the first delay circuit is connected to the output terminal of the selection signal generating circuit.
  • the control input terminal of the second selection circuit is used to receive the delayed signal. Select signal.
  • the first delay circuit is used to delay the selection signal and then send it to the second selection circuit, so that the control of the drain voltage signal by the second selection circuit lags behind the control of the gate voltage signal by the first selection circuit.
  • the second voltage signal of the first NOT gate 10111 lags behind the first voltage signal of the first NOT gate 10111 .
  • the time when the second selection circuit receives the selection signal lags behind the time when the first selection circuit receives the selection signal, so that the control of the drain voltage signal by the second selection circuit lags behind the control of the gate voltage by the first selection circuit. Signal control.
  • the above-mentioned first delay circuit can be any logic circuit, so as to achieve the purpose of delay through the processing of the logic circuit.
  • FIG. 8 is a schematic structural diagram of the mirror test circuit when the mirror transistor is a PMOS transistor provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of the mirror test circuit when the mirror transistor is an NMOS transistor provided by an embodiment of the present disclosure. Referring to FIGS. 8 and 9 , both the first selection circuit and the second selection circuit may be multiplexers.
  • one of the data input terminals 1 of the first selection circuit is connected to the first input terminal of the first inversion unit 1011 (that is, the input terminal of the first NOT gate 10111 in the first inversion unit 1011 ).
  • the other data input terminal 0 of the first selection circuit can be connected to the power supply voltage signal VDD.
  • the selection signal is high level, it indicates that the level of the first input terminal undergoes a level flip.
  • the first selection circuit selects the first voltage signal of the input terminal of the first NOT gate 10111 connected to its data input terminal 1 as its output signal, and the output terminal of the first selection circuit is connected to the gate G of the mirror transistor PMOS, that is, The first selection circuit is used to use the first voltage signal as a gate voltage signal of the mirror transistor PMOS.
  • the signal received by the second selection circuit from the control input terminal is an inverted signal of the selection signal. Therefore, as shown in FIG. 8 , one of the data input terminals 0 of the second selection circuit is connected to the first output terminal, and the output terminal of the second selection circuit is connected to the drain D of the mirror transistor PMOS. Therefore, when the selection signal is high level to indicate a level flip of the level of the first input terminal, the second voltage signal received by the data input terminal 0 is used as the drain voltage signal of the mirror transistor PMOS.
  • one of the data input terminals 0 of the first selection circuit is connected to the first input terminal of the first inversion unit 1011 , and the other data input terminal 1 of the first selection circuit can be connected to the ground GND.
  • the selection signal is low level, it indicates that the level of the first input terminal undergoes a level flip.
  • the first selection circuit selects the first voltage signal of the input terminal of the first inversion unit 10111 connected to its data input terminal 0 as its output signal, and the output terminal of the first selection circuit is connected to the gate G of the mirror transistor NMOS, That is, the first selection circuit is used to use the first voltage signal as the gate voltage signal of the mirror transistor NMOS when the selection signal is low level to indicate a level flip.
  • the signal received by the second selection circuit from the control input terminal is an inverted signal of the selection signal. Therefore, as shown in Figure 9, one of the data input terminals 1 of the second selection circuit is connected to the output terminal of the first NOT gate 10111, and the output terminal of the second selection circuit is connected to the drain D of the mirror transistor NMOS for use in When the selection signal is low level to indicate that the level of the first input terminal is level flipped, the second voltage signal received by the data input terminal 1 is used as the drain voltage signal of the mirror transistor NMOS.
  • the above-mentioned first selection circuit and the second selection circuit can control the operating voltage of the gate G and drain D of the mirror transistor, so that They are respectively consistent with the voltages of the gate G and the drain D of the transistor in the first NOT gate 10111.
  • the above-mentioned first selection circuit and the second selection circuit can operate in any state. Therefore, the other data input terminal of the first selection circuit and the other data input terminal of the second selection circuit The input terminal can be connected to any voltage signal.
  • the mirror transistor can be controlled to turn off through the first selection circuit and the second selection circuit.
  • the other data input terminal 0 of the first selection circuit can be connected to the power supply voltage signal VDD. Therefore, the first selection circuit is also used to use the power supply voltage signal VDD as the gate voltage signal of the mirror transistor PMOS when the selection signal is low level to indicate that the level of the first input terminal does not flip.
  • the other data input terminal 1 of the second selection circuit is connected to the ground GND, and the second selection circuit is used to connect the drain of the mirror transistor to the ground when the selection signal is low level to indicate that the level of the first input terminal does not flip. In this way, the mirror transistor PMOS tube is turned off.
  • the mirror test circuit 1022 shown in Figure 8 is a structure when the selection signal is high level to indicate level flipping. In practical applications, it can also be used to indicate that the level of the first input terminal is level flipped when the selection signal is low level. At this time, the circuit connecting the data input terminals 1 and 0 of the first selection circuit in Figure 8 needs to be exchanged, and the circuit connecting the data input terminals 1 and 0 of the second selection circuit also needs to be exchanged, which will not be described again.
  • the other data input terminal 1 of the first selection circuit is connected to ground. Therefore, the first selection circuit is also used to control the gate G of the mirror transistor NMOS to be grounded when the selection signal is high level to indicate that the level of the first input terminal does not flip.
  • the other data input terminal 0 of the second selection circuit is connected to the power supply voltage signal VDD.
  • the second selection circuit is also used to change the level of the first input terminal when the selection signal is high level to indicate that the level of the first input terminal has not flipped.
  • the power supply voltage signal VDD serves as the drain voltage signal of the mirror transistor NMOS. In this way, the mirror transistor NMOS is turned off.
  • the above-mentioned selection signal generation circuit is used to identify the level flip of the mirror control signal based on the delay effect of the inverter circuit, that is, to realize whether the level flip occurs at the first input terminal.
  • the mirror test circuit 1022 shown in Figure 9 is a structure when the selection signal is low level to indicate level flipping. In practical applications, it can also be used to indicate that the level of the first input terminal occurs a level flip when the selection signal is at a high level. At this time, the circuit connecting the data input terminals 1 and 0 of the first selection circuit in Figure 9 needs to be exchanged, and the circuit connecting the data input terminals 1 and 0 of the second selection circuit also needs to be exchanged, which will not be described again here.
  • the first delay circuit is an inverter with an inverting function.
  • the first delay circuit may not have an inverting function. In this case, it is necessary to switch the circuits connecting the data input terminals 1 and 0 of the second selection circuit in Figures 8 and 9.
  • the first selection circuit and the second selection circuit in the mirror test circuit 1022 have been described above, and the selection signal generation circuit will be described in detail below.
  • the mirror transistor is a PMOS transistor.
  • the selection signal generated by the selection signal generation circuit instructs the level of the first input terminal to flip from high level to low level
  • the first voltage signal and the second voltage signal are sequentially Connect to the gate and drain of the mirror transistor PMOS so that the mirror transistor PMOS starts to conduct.
  • the current in the mirror transistor PMOS can mirror the flip current of the PMOS transistor in the first NOT gate 10111, and since the mirror transistor PMOS is not connected to the NMOS transistor, the current of the mirror transistor PMOS only includes the flip current, excluding the CMOS flipping process.
  • the effective driving current of the PMOS tube in the first NOT gate 10111 can be obtained by the leakage current generated when the NMOS tube and the PMOS tube are turned on at the same time.
  • the selection signal generation circuit may include a NOR gate and an inverter circuit.
  • the two input terminals of the NOR gate are respectively connected to the second input terminal of the second inverting unit and the output terminal of the inverting circuit, and the input terminal of the inverting circuit is connected to the second input terminal of the second inverting unit.
  • FIG. 10 is a signal timing diagram of the mirror test circuit shown in FIG. 8 provided by an embodiment of the present disclosure.
  • Figure 10 shows the timing sequence of the selection signal, the output signal of the first delay circuit, the gate voltage signal of the PMOS tube, and the drain voltage signal of the PMOS tube when the mirror control signal flips from high level to low level.
  • the mirror control signal input to the NOR gate in Figure 8 is high level, so the selection signal output by the NOR gate is always low level.
  • the output signal of the first delay circuit is inverted with the selection signal and is always at a high level. Therefore, the first selection circuit in Figure 8 controls the gate voltage signal of the PMOS tube to be the power supply voltage signal VDD received by the data input terminal 0, which is a high level, and the second selection circuit controls the drain voltage signal of the PMOS tube to be the data
  • the ground signal GND received by input terminal 1 is a low-level signal.
  • the mirror control signal begins to flip from high level to low level, and ends at time t2.
  • the mirror control signal input to the NOR gate flips to low level, but due to the inversion and delay of the inverting circuit in Figure 8, the other input end of the NOR gate is still low level, so , the selection signal output by the NOR gate flips to high level.
  • the high level of the above selection signal lasts for a period of time until the end of time t4, and the duration of the high level is the time delay between the input and output of the inverter circuit.
  • the selection signal is the input of the first delay circuit, so as shown in FIG. 10 , the output signal of the first delay circuit is an inverse delayed signal of the selection signal.
  • the first selection circuit controls the gate voltage signal of the PMOS tube according to the selection signal to be the first voltage signal received by the data input terminal 1 from the first input terminal.
  • the first voltage signal at the first input end of the first reverse unit also flips from high level to low level, which is consistent with the first voltage.
  • the voltage of the PMOS gate connected to the signal gradually becomes low level.
  • the second selection circuit controls the drain voltage signal of the PMOS tube according to the inverted delay signal of the selection signal, which is the output signal of the first delay circuit in Figure 10, to be the data input terminal 0 received from the first output terminal. In the same way as the second voltage signal, the voltage of the PMOS drain connected to the second voltage signal gradually changes to a high level signal.
  • the first selection circuit controls the gate voltage signal of the PMOS tube according to the selection signal to be the power supply voltage signal VDD received by the data input terminal 0, that is, high level signal.
  • the control input terminal of the second selection circuit receives the inverse delayed signal of the selection signal.
  • the control input terminal of the second selection circuit still receives is a low-level signal, and the second selection circuit continues to control the drain of the PMOS tube to receive the second voltage signal from the data input terminal 0 according to the inverted delay signal.
  • the first selection circuit controls the drain voltage signal of the PMOS tube according to the selection signal to be the ground signal received by the data input terminal 1, that is, low level signal.
  • the selection signal is a high-level signal, it indicates that the level of the first input terminal flips from high level to low level.
  • the generated signal of the above-mentioned selection signal generating circuit can also be inverted and then input into the first selection circuit and the first delay circuit as a selection signal, so as to indicate the first selection signal when the selection signal is a low-level signal.
  • the level of the input terminal flips from high level to low level, so that the flipping current of the PMOS tube can be tested.
  • the circuits connected to the data input terminals 1 and 0 of the first selection circuit in Figure 8 need to be exchanged.
  • the circuits connected to the data input terminals 1 and 0 of the circuit also need to be exchanged, so I won’t go into details here.
  • the mirror transistor is an NMOS transistor.
  • the selection signal generated by the selection signal generation circuit indicates that the level of the first input terminal is flipped from low level to high level, the first voltage signal and the second voltage signal are sequentially Connect to the gate and drain of the mirror transistor NMOS so that the mirror transistor NMOS begins to conduct.
  • the current in the mirror transistor NMOS can mirror the flip current of the NMOS transistor in the first NOT gate 10111, and since the mirror transistor NMOS is not connected to the PMOS transistor, the current of the mirror transistor NMOS only includes the flip current, excluding the CMOS flipping process.
  • the effective driving current of the NMOS tube in the first NOT gate 10111 can be obtained by the leakage current generated when the NMOS tube and the PMOS tube are turned on at the same time.
  • the selection signal generation circuit includes a NAND gate and an inverter circuit.
  • the two input terminals of the NAND gate are respectively connected to the second input terminal of the second inverter unit and the output terminal of the inverter circuit.
  • the input terminal of the circuit is connected to the second input terminal of the second inversion unit.
  • a capacitor C is also connected between VDD and the control input terminal of the second selection circuit, and the capacitor C can delay the signal input to the control input terminal.
  • FIG. 11 is a signal timing diagram of the mirror test circuit shown in FIG. 9 provided by an embodiment of the present disclosure.
  • Figure 11 shows the timing sequence of the selection signal, the output signal of the first delay circuit, the gate voltage signal of the NMOS transistor, and the drain voltage signal of the NMOS transistor when the mirror control signal flips from low level to high level.
  • the mirror control signal input to the NAND gate in Figure 9 is low level, so the selection signal output by the NAND gate is always high level.
  • the output signal of the first delay circuit is inverted with the selection signal and is always low level. Therefore, the first selection circuit in Figure 9 controls the gate voltage signal of the NMOS tube to be the ground signal GND received by the data input terminal 1, which is a low level, and the second selection circuit controls the drain voltage signal of the NMOS tube to be the data input
  • the power supply voltage signal VDD received by terminal 0 is a high level signal.
  • the mirror control signal begins to flip from low level to high level, and ends at time t2.
  • the mirror control signal input to the NAND gate flips to high level, but due to the inversion and delay of the inverting circuit in Figure 9, the other input end of the NAND gate is still high level, so , the selection signal output by the NAND gate flips to low level.
  • the low level of the above-mentioned selection signal lasts for a period of time until the end of time t4, and the duration of the low level is the time delay between the input and output of the inverter circuit.
  • the selection signal is the input of the first delay circuit, and the output signal of the first delay circuit is the inverse delayed signal of the selection signal.
  • the first selection circuit controls the gate voltage signal of the NMOS transistor according to the selection signal to be the first voltage signal received by the data input terminal 0 from the first input terminal.
  • the first voltage signal at the first input terminal of the first reverse unit also flips from low level to high level, and the The voltage of the NMOS gate connected to a voltage signal also gradually changes to a high level.
  • the second selection circuit controls the drain voltage signal of the NMOS transistor to pass through the data input terminal 1 of the second selection circuit based on the inverted delay signal of the selection signal, that is, the output signal of the first delay circuit in Figure 11. Similarly, for the second voltage signal received by the first output terminal, the voltage of the NMOS drain connected to the second voltage signal gradually changes to a low level signal.
  • the first selection circuit controls the gate voltage signal of the NMOS tube according to the selection signal to be the ground signal GND received by the data input terminal 1, that is, low level signal.
  • the control input terminal of the second selection circuit receives the inversion delayed signal of the selection signal.
  • the control input terminal of the second selection circuit still receives is a high-level signal, and the second selection circuit continues to control the drain of the NMOS transistor to receive the second voltage signal from the data input terminal 1 according to the inverted delay signal.
  • the second selection circuit controls the drain voltage signal of the NMOS transistor according to the selection signal to be the power supply voltage signal VDD received from the data input terminal 0. That is, a high-level signal.
  • the selection signal is a low-level signal, it indicates that the level of the first input terminal flips from low level to high level.
  • the signal generated by the above-mentioned selection signal generating circuit can also be inverted and then input into the first selection circuit and the first delay circuit as a selection signal, so that when the selection signal is a high-level signal, the first The level of the input terminal flips from low level to high level, so that the flip current of the NMOS tube can be tested.
  • the above-mentioned inverter circuit includes an odd number of cascaded inverters.
  • Figures 8 and 9 illustrate an inverter circuit composed of three inverters.
  • An odd number of cascaded inverters can not only achieve inversion of the mirror control signal, but also achieve delay, that is, multiple functions can be realized simultaneously through one circuit, which helps to reduce circuit costs.
  • Figure 12 is a schematic structural diagram of a test system provided by an embodiment of the present disclosure.
  • the test system 20 includes an enable signal generation circuit 21 and a test circuit 100 .
  • the output end of the enable signal generating circuit 21 is connected to the test circuit 100 , and the enable signal generated by the enable signal generating circuit 21 is used to drive the test circuit 100 to run.
  • the output terminal of the enable signal generating circuit 21 is connected to the enable input terminal in FIG. 5 .
  • the above-mentioned test system 20 may also include a frequency dividing component 22 and an output buffer component 23.
  • the input end of the frequency dividing element 22 is connected to one of the first output ends of the ring oscillation circuit 101 of the test circuit 100
  • the output buffer element 23 is connected to the output end of the frequency dividing element 22 .
  • the frequency dividing component 22 is used to perform frequency dividing processing on the oscillation signal generated by the test circuit 100, and may be a 1/2 frequency divider, for example.
  • the output buffer element 23 is used to buffer the frequency-divided signal to output to an external device.
  • FIG 13 is a step flow chart of a testing method provided by an embodiment of the present disclosure, which is used in the aforementioned testing system.
  • the testing method may include S301 to S303.
  • the equivalent parameters include at least one of the following: equivalent capacitance and equivalent resistance.
  • the embodiment of the present disclosure can accurately test the flip current in the first NOT gate through the current of the mirror transistor, thereby improving the accuracy of the equivalent capacitance and equivalent resistance.
  • An embodiment of the present disclosure also provides a semiconductor device, including the test system described in the claims.

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Abstract

本公开实施例提供一种测试电路、测试系统、测试方法和半导体器件，测试电路包括环形振荡电路和镜像电路；环形振荡电路包括依次级联的多个第一反向单元，每个第一反向单元包括第一输入端和第一输出端，至少一个第一反向单元的第一输入端和第一输出端与镜像电路连接；镜像电路，用于接收第一反向单元的第一输入端对应的第一电压信号和第一输出端对应的第二电压信号，并在第一反向单元的第一输入端发生电平翻转时，根据第一电压信号和第二电压信号镜像第一反向单元中晶体管的翻转电流。本公开实施例可以通过镜像电路镜像第一反向单元中晶体管的电流。这样，可以去除一个第一反向单元中不同晶体管之间的电流，有助于提高测试翻转电流的准确度。

Description

测试电路、测试系统、测试方法和半导体器件
本申请要求于2022年06月30日提交中国专利局、申请号为202210760104.7、申请名称为“测试电路、测试系统、测试方法和半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种测试电路、测试系统、测试方法和半导体器件。
背景技术
MOS(metal-oxide-semiconductor field-effect transistor，金氧半场效晶体管)在半导体技术领域中广泛应用，例如，PMOS和NMOS串联可以构成反相器，反相器是具有反相作用的CMOS。CMOS中的PMOS和NMOS的有效驱动电流可以辅助对CMOS进行分析，例如，可以根据有效驱动电流分析CMOS的寄生电容，以确定离子掺杂对CMOS寄生电容和电阻的影响，进而获得更加高速的电路。
现有的CMOS技术中，为了获得最佳的噪声容限，通常会调节PMOS和NMOS的器件宽度，以使晶体管构成的逻辑门的转换电压处于一半的工作电压下。在测量PMOS的有效驱动电流时，将PMOS的栅极、源极和漏极都单独引出，以在源极和栅极施加一半的工作电压，此时，在漏极测量得到的沟道电流可以作为PMOS的有效驱动电流。同理，可以测量得到NMOS的有效驱动电流。可以看出，有效驱动电流也可以理解为翻转电流。
然而，不同晶体管的跨导不同，从而逻辑门的转移曲线的中点并不是在一半的工作电压处。并且在逻辑电平翻转的时间内，晶体管会依次经历过饱和区和线性区，因此某一固定偏压下的单一直流测试并不能反映其等效的翻转电流。而且电平翻转的时间很短，沟道内反型层载流子具有一定的产生时间和湮灭时间。这些原因均会导致无法准确的在出现电平翻转时通过简单的直流测试得到真正的翻转电流，使测试的翻转电流的准确度较低。
发明内容
本公开实施例提供一种测试电路、测试系统、测试方法和半导体器件，可以提高翻转电流的测试准确度。
第一方面，本公开实施例提供一种测试电路，包括环形振荡电路和镜像电路；
其中，所述环形振荡电路包括依次级联的多个第一反向单元，每个所述第一反向单元包括第一输入端和第一输出端，至少一个所述第一反向单元的第一输入端和第一输出端与所述镜像电路连接；
所述镜像电路，用于接收所述第一反向单元的所述第一输入端对应的第一电压信号和 所述第一输出端对应的第二电压信号，并在所述第一反向单元的所述第一输入端发生电平翻转时，根据所述第一电压信号和所述第二电压信号镜像所述第一反向单元中晶体管的翻转电流。
在一些实施方式中，所述镜像电路包括镜像控制电路和至少一个镜像测试电路；
所述镜像控制电路，包括有至少一个控制信号输出端，所述控制信号输出端与所述镜像测试电路一一对应连接，所述镜像控制电路用于通过所述控制信号输出端向所述镜像测试电路发送镜像控制信号，所述镜像控制信号用于指示所述第一反向单元的翻转状态；
每个所述镜像测试电路还与一个所述第一反向单元的第一输入端和第一输出端连接，所述镜像测试电路用于根据所述镜像控制信号确定所述第一反向单元的所述第一输入端是否发生电平翻转，并在发生电平翻转时，根据所述第一电压信号和所述第二电压信号镜像所述第一反向单元中晶体管的翻转电流。
在一些实施方式中，所述镜像控制电路包括依次级联的多个第二反向单元，所述第二反向单元的数量与所述第一反向单元的数量相同，所述镜像控制电路与所述环形振荡电路工作在同一电源电压下；
每个所述第二反向单元包括第二输入端，至少一个所述第二输入端作为所述控制信号输出端与所述镜像测试电路连接，用于将所述第二反向单元的所述第二输入端的电压信号作为所述镜像控制信号发送给所述镜像测试电路。
在一些实施方式中，所述镜像测试电路包括镜像晶体管和测试控制电路，所述测试控制电路分别与所述控制信号输出端、所述第一输入端、所述第一输出端和所述镜像晶体管连接，所述测试控制电路用于根据所述镜像控制电路发送的所述镜像控制信号，确定所述第一输入端是否发生电平翻转，并在发生电平翻转时，根据接收到的所述第一电压信号和所述第二电压信号控制所述镜像晶体管的工作电压，使所述镜像晶体管的电流与所述第一反向单元中晶体管的电流相同。
在一些实施方式中，所述测试控制电路包括选择信号生成电路和电压控制电路；
所述选择信号生成电路与所述镜像控制电路、所述电压控制电路连接，所述选择信号生成电路用于根据所述镜像控制电路发送的镜像控制信号输出选择信号，所述选择信号用于指示所述第一输入端的电平是否将要发生电平翻转；
所述电压控制电路分别与所述选择信号生成电路、所述第一输入端、所述第一输出端和所述镜像晶体管连接，所述电压控制电路用于在所述选择信号表示所述第一输入端发生电平翻转时，控制所述镜像晶体管的栅极电压信号与所述第一电压信号一致，以及所述镜像晶体管的漏极电压信号与所述第二电压信号一致。
在一些实施方式中，所述电压控制电路包括第一选择电路、第二选择电路和第一延迟电路；
所述第一选择电路的控制输入端与所述选择信号生成电路连接，用于接收所述选择信号；所述第二选择电路的控制输入端与所述第一延迟电路的输出端连接，且所述第一延迟电路的输入端与所述选择信号生成电路的输出端连接，所述第二选择电路的控制输入端用于接收延迟的所述选择信号；
所述第一选择电路的其中一个数据输入端与所述第一输入端连接，所述第一选择电路的输出端与所述镜像晶体管的栅极连接，用于在所述选择信号指示所述第一输入端的电平 发生电平翻转时，将所述第一电压信号作为所述镜像晶体管的栅极电压信号；
所述第二选择电路的其中一个数据输入端与所述第一输出端连接，所述第二选择电路的输出端与所述镜像晶体管的漏极连接，用于在所述选择信号指示所述第一输入端的电平发生电平翻转时，将所述第二电压信号作为所述镜像晶体管的漏极电压信号。
在一些实施方式中，当所述镜像晶体管为PMOS管时，所述第一选择电路的另一个数据输入端接入电源电压信号，所述第一选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述电源电压信号作为所述镜像晶体管的栅极电压信号；
所述第二选择电路的另一个数据输入端接地，所述第二选择电路用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述镜像晶体管的漏极接地。
在一些实施方式中，当所述镜像晶体管为NMOS管时，所述第一选择电路的另一个数据输入端接地，所述第一选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，控制所述镜像晶体管的栅极接地；
所述第二选择电路的另一个数据输入端接入电源电压信号，所述第二选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述电源电压信号作为所述镜像晶体管的漏极电压信号。
在一些实施方式中，所述测试电路还包括：第二延迟电路，所述第二延迟电路的输入端和所述镜像控制电路的使能输入端接入同一使能信号，所述第二延迟电路用于将接收到的所述使能信号延迟预设时间后，通过所述第二延迟电路的输出端输出至所述环形振荡电路的所述使能输入端，所述第二延迟电路用于控制所述环形振荡电路产生的振荡信号滞后于所述镜像控制电路产生的镜像控制信号。
在一些实施方式中，所述第二延迟电路包括偶数个级联的反相器。
在一些实施方式中，所述选择信号生成电路包括或非门和反相电路，所述或非门的两个输入端分别与所述第二反向单元的第二输入端、所述反相电路的输出端连接，所述反相电路的输入端与所述第二反向单元的第二输入端连接，当所述选择信号为高电平信号时，指示所述第一输入端的电平由高电平到低电平翻转。
在一些实施方式中，所述选择信号生成电路包括与非门和反相电路，所述与非门的两个输入端分别与所述第二反向单元的第二输入端、所述反相电路的输出端连接，所述反相电路的输入端与所述第二反向单元的第二输入端连接，当所述选择信号为低电平信号时，指示所述第一输入端的电平由低电平到高电平翻转。
在一些实施方式中，所述反相电路包括奇数个级联的反相器。
在一些实施方式中，第一级所述第一反向单元包括第一与非门，其余所述第一反向单元包括第一非门，所述第一与非门的两个输入端分别作为所述环形振荡电路的所述使能输入端和所述第一反向单元的第一输入端，所述第一与非门的输出端作为所述第一反向单元的第一输出端，所述第一非门的输入端和输出端分别作为对应的所述第一反向单元的第一输入端和第一输出端。
在一些实施方式中，第一级所述第二反向单元包括第二与非门，其余所述第二反向单元包括第二非门，所述第二与非门的两个输入端分别作为所述镜像控制电路的所述使能输入端和所述第二反向单元的第二输入端，所述第二与非门的输出端作为所述第二反向单元的第二输出端，所述第二非门的输入端和输出端分别作为对应的所述第二反向单元的第二 输入端和第二输出端。
在一些实施方式中，所述第一非门和所述第二非门均包括不同类型的第一晶体管和第二晶体管，所述第一与非门的电源输入端和所述第一晶体管的源极均接入同一电源电压信号；
在所述第一非门和所述第二非门的任意一个非门中，所述第一晶体管的栅极与所述第二晶体管的栅极连接，并作为对应的所述非门的输入端；所述第一晶体管的漏极与所述第二晶体管的漏极连接，并作为对应的所述非门的输出端，所述第二晶体管的源极接地。
在一些实施方式中，当所述镜像晶体管为PMOS管时，所述镜像晶体管的源极与所述第一反向单元接入大小相同的电源电压信号；当所述镜像晶体管为NMOS管时，所述镜像晶体管的源极接地。
在一些实施方式中，所述第一延迟电路包括奇数个级联的反相器。
第二方面，本公开实施例提供一种测试系统，包括使能信号产生电路和前述第一方面的测试电路，所述使能信号产生电路的输出端与所述测试电路连接，所述使能信号产生电路生成的使能信号用于驱动所述测试电路运行。
在一些实施方式中，还包括分频元件和输出缓冲元件，所述分频元件的输入端与所述测试电路的环形振荡电路的其中一个第一输出端连接，所述输出缓冲元件与所述分频元件的输出端连接。
第三方面，本公开实施例提供一种测试方法，用于前述第二方面的测试系统，所述测试方法包括：
通过使能信号驱动所述测试电路运行；
在所述测试电路的运行过程中，获取所述测试电路中的镜像晶体管的电流和所述环形振荡电路的振荡频率；
根据所述镜像晶体管的电流和所述振荡频率，确定所述环形振荡电路的第一反向单元中的晶体管的等效参数，所述等效参数包括以下至少一种：等效电容和等效电阻。
第四方面，本公开实施例提供一种半导体器件，包括前述第二方面的测试系统。
本公开实施例提供的测试电路、测试系统、测试方法和半导体器件，可以通过镜像电路镜像第一反向单元中晶体管的电流。这样，可以去除一个第一反向单元中不同晶体管之间的电流，有助于提高测试翻转电流的准确度。
附图说明
图1是本公开实施例提供的一种环形振荡电路的结构示意图；
图2是本公开实施例提供的图1所示的环形振荡电路中相邻反相器之间的一种电流示意图；
图3是本公开实施例提供的图1所示的环形振荡电路中相邻反相器之间的另一种电流示意图；
图4是本公开实施例提供的一种测试电路的结构示意图；
图5是本公开实施例提供的一种环形振荡电路的结构示意图；
图6是本公开实施例提供的另一种测试电路的结构示意图；
图7是本公开实施例提供的图6中镜像测试电路的结构示意图；
图8是本公开实施例提供的镜像晶体管为PMOS管时镜像测试电路的结构示意图；
图9是本公开实施例提供的镜像晶体管为NMOS管时镜像测试电路的结构示意图；
图10是本公开实施例提供的图8所示的镜像测试电路的信号时序图；
图11是本公开实施例提供的图9所示的镜像测试电路的信号时序图；
图12是本公开实施例提供的一种测试系统的结构示意图；
图13是本公开实施例提供的一种测试方法的步骤流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
为了在电平翻转时刻测试翻转电流，可以通过一个环形振荡电路实现翻转电流的测试。图1是本公开实施例提供的一种环形振荡电路的结构示意图。参照图1所示，环形振荡电路可以由多个依次级联的反相器连接得到，图1中示例给出了五个反相器级联构成的环形振荡电路，但在实际应用中，环形振荡电路包括的反相器数量并不限制。图1中详细标注了其中一个反相器的具体结构，其余反相器的结构与其相同，从而并未在图1中标注。
从图1中可以看出，每级反相器的输出端与下一级反相器的输入端连接，这样就构成一个环形振荡电路。
图1中的每个反相器由PMOS和NMOS连接得到，PMOS的栅极G与NMOS的栅极G连接，并且两个连接的栅极G作为反相器的输入端。PMOS的漏极D与NMOS的漏极D连接，并且两个连接的漏极D作为反相器的输出端。PMOS的源极S接入电源电压信号VDD，NMOS的源极S接地GND。
图1所示的环形振荡电路中，部分反相器的输出端出现从高电平至低电平的电平翻转，另一部分反相器的输出端出现从低电平到高电平的电平翻转。这样，就可以准确的捕捉到电平翻转的时刻，从而可以将该时刻的电流作为翻转电流。
图2是本公开实施例提供的图1所示的环形振荡电路中相邻反相器之间的一种电流示意图。参照图2所示，在前一级反相器的输入端的电平V从高电平翻转为低电平的过程中，前一级反相器中的PMOS逐渐导通并产生电流I1，该电流I1流向后一级反相器的NMOS和PMOS的共栅极。在电流I1的作用下，后一级反相器的NMOS的栅 极电压升高。然而，在这个过程中，前一级反相器中的NMOS并未完全截止，仍然会有部分电流I2从前一级反相器的PMOS流经前一级反相器的NMOS到达接地端GND。电流I1和电流I2一起均从VDD端流出，从而在VDD端口测量的PMOS的翻转电流偏大，准确度较低。
图3是本公开实施例提供的图1所示的环形振荡电路中相邻反相器之间的另一种电流示意图。参照图3所示，在前一级反相器的输入端的电平V从低电平翻转为高电平的过程中，前一级反相器中的NMOS逐渐导通并产生电流I3，该电流I3使后一级反相器的共栅极的电平降低为0。然而，在这个过程中，前一级反相器中的PMOS并未完全截止，仍然会有部分电流I4从前一级反相器的PMOS流经前一级反相器的NMOS到达接地端GND。电流I3和电流I4一起流入GND，从而在GND端口测量的NMOS的翻转电流较大。
为了解决上述问题，本公开实施例考虑通过一个镜像电路来镜像晶体管中的翻转电流。这样测量的电流仅包括流经该晶体管的电流，并不包括同一反相器中两个晶体管同时处于导通状态时流经这两个晶体管的电流。从而，测量的翻转电流更加准确。
图4是本公开实施例提供的一种测试电路的结构示意图。参照图4所示，测试电路100包括环形振荡电路101和镜像电路102。
参照图4所示，环形振荡电路101包括依次级联的多个第一反向单元1011，每个第一反向单元1011包括第一输入端和第一输出端，至少一个第一反向单元1011的第一输入端和第一输出端均与镜像电路102连接。镜像电路102用于接收第一反向单元1011的第一输入端对应的第一电压信号和第一输出端对应的第二电压信号，并在第一反向单元1011的第一输入端发生电平翻转时，根据第一电压信号和第二电压信号镜像第一反向单元1011中晶体管的翻转电流。
其中，上述第一反向单元可以为具有反向功能的任意单元，包括但不限于：非门、与非门、或非门、异或门、同或门以及可控非门等。非门可以为PMOS管、NMOS管和CMOS管中的一种。
图4的环形振荡电路101中示例性给出了5个第一反向单元1011，但实际应用中第一反向单元的数量只要为奇数即可，在此对第一反向单元的数量不加以限制。图4中示例性给出了一个第一反向单元1011与镜像电路102连接，但在实际应用中可以有多个第一反向单元1011与镜像电路102连接，以测试连接的第一反向单元1011中的晶体管的翻转电流。在环形振荡电路101中的晶体管相同时，测试的翻转电流可以代表了这一类型晶体管的翻转电流。
其中，第一反向单元1011用于将第一输入端的第一电压信号进行反向处理之后通过第一输出端输出，输出的电压信号称为第二电压信号。上述环形振荡电路可以有两种。
在环形振荡电路的一种实施方式中，如图4所示，每一级第一反向单元1011均可以为一个非门，可以称为第一非门，从而每个第一反向单元1011的第一输入端为第一非门的输入端，每个第一反向单元1011的第一输出端为其中的第一非门的输出端。这样，环形振荡电路的每个第一非门的输出端均与下一级第一非门的输入端连接。
在环形振荡电路的另一种实施方式中，如图5所示，第一级反向单元的结构可以与其余第一反向单元1011的结构不同。图5是本公开实施例提供的一种环形振荡电路的结构 示意图。第一级第一反向单元1011可以为图5中的第一与非门10112，而其余第一反向单元1011可以由图5中的第一非门10111构成。第一与非门10112的一个输入端作为环形振荡电路101的使能输入端。第一与非门10112的另一个输入端作为对应第一反向单元1011的第一输入端，第一与非门10112的输出端作为第一反向单元1011的第一输出端。第一非门10111的输入端和输出端分别作为对应的第一反向单元1011的第一输入端和第一输出端。
参照图5所示，第一反向单元1011之间的连接也就是上述第一与非门10112和第一非门10111之间的连接。其中，第一与非门10112的输出端与第二级第一反向单元1011中的第一非门10111的输入端连接。第一与非门10112的另一输入端与最后一级第一反向单元1011中的第一非门10111的输出端连接，其余第一非门10111的输出端与下一级第一非门10111的输入端连接。
图5中的使能输入端用于控制环形振荡电路101的振荡。在初始状态下，使能信号为低电平信号，此时，图5所示的环形振荡电路101并不振荡。当使能信号为高电平信号时，图5所示的环形振荡电路101开始振荡，也就是说，第一非门10111开始工作，第一输入端的电平出现电平翻转。在环形振荡电路101开始振荡时，可以测试翻转电流。
可以看出，本公开实施例可以结合使能信号和第一与非门10112，灵活的控制环形振荡电路101的振荡，在不需要测试翻转电流时，可以通过使能信号控制环形振荡电路101停止振荡，助于节约电能。
在一些实施方式中，上述第一非门10111可以是包括不同类型的第一晶体管和/或第二晶体管的反相器，例如，第一晶体管为PMOS管，第二晶体管可以为NMOS管，还可以是TTL(Transistor-Transistor Logic，晶体管-晶体管逻辑)反相器。
参照图5所示，环形振荡电路101中第一与非门10112的电源输入端和各第一非门10111的第一晶体管的源极均接入同一电源电压信号VDD，以向环形振荡电路101提供电源。当然，由于环形振荡电路101可以在没有第一与非门10112的情况下振荡，从而在环形振荡电路101中不存在第一与非门10112时，各第一晶体管的源极均接入同一电源电压信号VDD。
在图5所示的任一第一非门10111中，第一晶体管PMOS的栅极G与第二晶体管NMOS的栅极G连接，并作为对应的第一非门10111的输入端，也就是对应的第一反向单元1011的第一输入端。第一晶体管PMOS的漏极D与第二晶体管NMOS的漏极D连接，并作为对应的第一非门10111的输出端，也就是对应的第一反向单元1011的第一输出端，第二晶体管的源极S接地。
需要说明的是，图5中标注了第二级第一反向单元1011中第一非门10111的内部详细结构，其余第一非门10111的结构相同，再图5中并未标注。
上述环形振荡电路101在振荡过程中，可以通过镜像电路102镜像其中的晶体管的翻转电流。图6是本公开实施例提供的另一种测试电路的结构示意图。参照图6所示，镜像电路102可以包括：镜像控制电路1021和至少一个镜像测试电路1022，镜像控制电路1021用于控制镜像测试电路1022镜像翻转电流。如此，可以实现镜像控制和镜像测试的独立运行，提高了镜像电路102的模块化，有助于对镜像电路102的管理和维护。
图6中示例性给出了一个镜像测试电路1022，但在实际应用中，镜像测试电路可以为 多个，并且镜像测试电路的数量最多与第一非门10111的数量相同，以对第一非门10111中的晶体管进行镜像，进而测试其翻转电流。
上述镜像控制电路1021可以包括有至少一个控制信号输出端，控制信号输出端与镜像测试电路1022一一对应连接，镜像控制电路1021用于通过控制信号输出端向镜像测试电路1022发送镜像控制信号，镜像控制信号用于指示第一反向单元1011的翻转状态。
每个镜像测试电路1022还与一个第一反向单元1011的第一输入端和第一输出端连接，也就是图6中的至少一个第一非门10111的输入端和输出端。镜像测试电路1022用于根据镜像控制信号确定第一反向单元1011的第一输入端是否发生电平翻转，并在发生电平翻转时，根据第一电压信号和第二电压信号镜像第一反向单元1011中晶体管的翻转电流。在未发生电平翻转时，镜像测试电路1022可以不镜像翻转电流，从而可以节约电能。
其中，镜像测试电路1022要镜像翻转电流的晶体管是第一非门10111中的晶体管。
本公开实施例可以针对每个第一反向单元1011设置对应的镜像测试电路1022，从而使不同镜像测试电路1022之间进行独立的测试，避免不同镜像测试电路1022之间的耦合，有助于提高测试的准确度。此外，镜像控制电路1021用于生成镜像控制信号，镜像测试电路1022用于根据镜像控制信号进行镜像，这样，有助于提高电路的集成度，方便电路管理和维护。
在一些实施方式中，上述镜像控制电路1021可以是环形振荡电路101的镜像电路，结构与环形振荡电路101相同，可以将镜像控制电路1021中的反向单元称为第二反向单元，第二反向单元的第二输入端称为第二输入端，第二反向单元的第二输出端称为第二输出端。这样，镜像控制电路1021可以包括依次级联的多个第二反向单元。每个第二反向单元包括第二输入端，第二输入端作为控制信号输出端与镜像测试电路1022连接，用于将第二反向单元的第二输入端的电压信号作为镜像控制信号发送给镜像测试电路1022。
为了使镜像控制信号可以准确的指示第一输入端的电平翻转状态，需要使镜像控制电路1021的工作状态与环形振荡电路101的工作状态相同。基于该考虑，第二反向单元的数量可以与第一反向单元1011的数量相同，此外，镜像控制电路1021与环形振荡电路101工作在同一电源电压下，以使环形振荡电路101和镜像控制电路1021的工作电压一致，这样，可以保证镜像控制电路1021和振荡频率与环形振荡电路101的振荡频率一致。
与前述环形振荡电路101相同，当环形振荡电路101不包括第一与非门10112时，镜像控制电路1021也可以不包括第二与非门10212，镜像控制电路1021中每个第二反向单元均由第二非门10211构成。当环形振荡电路101中的第一级第一反向单元1011包括第一与非门10112时，镜像控制电路1021也可以包括第二与非门10212。第一级第二反向单元包括第二与非门10212，其余第二反向单元包括第二非门10211。第二与非门10212的两个输入端作为镜像控制电路1021的使能输入端和第二反向单元的第二输入端，第二与非门10212的输出端作为第二反向单元的第二输出端。第二非门10211的输入端和输出端分别作为对应的第二反向单元的第二输入端和第二输出端，第二输入端即可作为控制信号输出端。
相应的，上述第二非门10211均包括不同类型的第一晶体管PMOS和第二晶体管NMOS，第二与非门10212的电源输入端和第二晶体管NMOS的源极S均接入同一电源电压信号VDD。在任一第二非门10211中，第一晶体管PMOS的栅极G与第二晶体管NMOS 的栅极G连接，并作为对应的第二非门10211的输入端，也就是第二反向单元的第二输入端。第一晶体管PMOS的漏极D与第二晶体管NMOS的漏极D连接，并作为对应的第二非门10211的输出端，也就是对应的第二反向单元的第二输出端，第二晶体管NMOS的源极S接地。
综上所述，本公开实施例的镜像控制电路1021与环形振荡电路101具有相同的结构，并且工作状态一致。如此，可以使镜像控制电路1021输出的镜像控制信号准确的指示环形振荡电路101中第一反向单元1011的电平翻转状态，有助于提高翻转电流的测试准确度。
可以看出，上述镜像控制电路1021需要生成控制信号，以使镜像测试电路1022进行镜像，这个过程需要消耗一定时长。为了使环形振荡电路101的第一电压信号和镜像控制电路1021生成的镜像控制信号尽可能的同时到达镜像测试电路1022，可以将镜像控制电路1021的振荡滞后于环形振荡电路101的振荡。
在一些实施方式中，参照图6所示，上述测试电路100还可以包括：第二延迟电路103。第二延迟电路103的输入端和镜像控制电路1021的使能输入端接入同一使能信号，也就是说，镜像控制电路1021的使能输入端为镜像控制电路1021的第二与非门10212的一个输入端。第二与非门10212的另一个输入端与最后一级第二反向单元的第二非门10211的输出连接。第二延迟电路103用于将接收到的使能信号延迟预设时间后，通过第二延迟电路103的输出端输出至环形振荡电路101的使能输入端，第二延迟电路103用于控制环形振荡电路101产生的振荡信号滞后于镜像控制电路1021产生的镜像控制信号。
其中，预设时间可以根据实际电路设计需要进行设置，以尽可能的使镜像控制信号早于第一电压信号到达镜像测试电路1022，使镜像控制信号起到预测或指示对应的第一反向单元中第一电压信号的变化趋势的作用，以在第一电压信号翻转之前，控制镜像晶体管的栅极和漏极接入第一反向单元中晶体管对应的电压信号，可以保证镜像测试电路1022准确的镜像翻转电流。
上述第二延迟电路103可以是任意逻辑电路构成的，从而可以使该逻辑电路的处理过程消耗时长以达到延迟的目的。但是，第二延迟电路103的输入和输出信号必须相同，从而可以使环形振荡电路101在t时刻的工作状态与镜像控制电路1021在t+T时刻的工作状态一致。其中，T是前述第二延迟电路103对使能信号进行延迟的预设时间。这样，不仅可以尽可能的使镜像控制信号早于第一电压信号到达镜像测试电路1022，还可以通过镜像控制信号准确的指示对应的第一电压信号的电平翻转状态，有助于进一步提高镜像测试电路1022对翻转电流的镜像准确度。
在一些实施方式中，上述第二延迟电路103可以包括偶数个级联的反相器，第一级反相器的输入作为第二延迟电路103的输入，第一级反相器的输出与下一级反相器的输入连接，最后一级反相器的输出作为第二延迟电路103的输出。这样，输入到第二延迟电路103的信号经过偶数次反相得到的信号与输入的信号相同。但每一个反相器对信号的处理均需要一定的时长，从而可以实现延迟。
需要说明的是，第二延迟电路103中反相器的数量可以根据前述要延迟的预设时间正相关。当预设时间越大时，反相器的数量越多。反之，第二延迟电路103中反相器的数量越少。
本公开实施例可以通过反相器构成第二延迟电路103，并且可以根据反相器的数量调整延迟的预设时间，有助于提高预设时间的调整灵活性。
图7是本公开实施例提供的图6中镜像测试电路的结构示意图。参照图7所示，镜像测试电路1022可以包括镜像晶体管和测试控制电路。测试控制电路分别与镜像控制电路1021的控制信号输出端、第一非门10111的输入端(也就是第一输入端)、第一非门10111的输出端(也就是第一输出端)和镜像晶体管连接。根据前述说明，镜像控制电路1021的控制信号输出端也就是图7中的第二输入端。基于这些连接，测试控制电路可以从镜像控制电路1021接收镜像控制信号，以确定第一输入端是否发生电平翻转。此外，测试控制电路还可以从第一输入端接收第一电压信号，以及从第二输入端接收第二电压信号。
测试控制电路在根据镜像控制电路1021确定第一输入端的电平发生电平翻转时，测试控制电路可以根据第一电压信号和第二电压信号控制镜像晶体管的工作电压，使镜像晶体管的电流与第一反向单元1011中晶体管的电流相同。
其中，镜像晶体管是与第一非门10111中的其中一个晶体管相同的晶体管。当第一非门10111中的晶体管包括PMOS管时，镜像晶体管可以为PMOS管，以镜像第一非门10111中PMOS管的电流。当第二非门10211中的晶体管包括NMOS管时，镜像晶体管可以为NMOS管，以镜像第一非门NMOS管的电流。
当然，在未发生电平翻转时，测试控制电路可以控制镜像晶体管截止，以节约电能。
本公开实施例可以通过测试控制电路控制镜像晶体管与第一非门10111中的晶体管相同的工作状态，这样，即可实现电流的镜像，这样可以通过镜像晶体管准确的镜像第一非门10111中的晶体管的电流。
参照图7所示，上述测试控制电路可以进一步包括选择信号生成电路和电压控制电路，选择信号生成电路与镜像控制电路1021的第二输入端、电压控制电路连接。
其中，选择信号生成电路用于接收镜像控制电路1021发送的镜像控制信号，并根据镜像控制信号输出选择信号。选择信号用于指示第一输入端的电平是否将要发生电平翻转，包括但不限于：选择信号为高电平时指示发生电平转换、选择信号为低电平时指示发生电平转换。本公开实施例对其不加以限制。
电压控制电路分别与选择信号生成电路、第一输入端、第一输出端和镜像晶体管连接。如此，电压控制电路可以接收到选择信号生成电路、第一输入端的第一电压信号，以及第一输出端的第二电压信号。电压控制电路用于在选择信号表示第一输入端发生电平翻转时，控制镜像晶体管的栅极电压信号与第一电压信号一致，以及镜像晶体管的漏极电压信号与第二电压信号一致。
具体地，在镜像控制信号指示第一反向单元的第一输入端为电平翻转状态时，选择信号指示需要镜像第一反向单元中晶体管的翻转电流。此时，电压控制电路根据选择信号控制镜像晶体管的栅极和漏极电压与待镜像的第一反向单元中的晶体管的栅极和漏极电压分别相同，从而实现晶体管电流的镜像。
此外，由于镜像控制电路的振荡频率与环形振荡电路的振荡频率相同，并且因第二延迟电路103的使能信号控制，使镜像控制电路的振荡信号比环形振荡电路的振荡信号早预设时间，即镜像控制电路中第二反向单元的第二输入端的信号变化要早于环形振荡电路中对应的第一反向单元的第一输入端的信号变化，因此，第二反向单元第二输入端对应的镜 像控制信号，可以指示第一电压信号的变化趋势，并在早于第一反向单元发生翻转时，控制第一选择电路和第二选择电路将第一反向单元中的栅极的第一电压信号和漏极的第二电压信号给到镜像晶体管。
可以理解的是，第一电压信号是第一非门10111中的PMOS和NMOS的栅极电压信号，第二电压信号是第一非门10111中PMOS和NMOS的漏极电压信号。
此外，当镜像晶体管为PMOS管时，镜像晶体管的源极与第一反向单元1011接入大小相同的电源电压信号。如此，可以保证镜像晶体管的各个极的工作电压和第一非门10111中PMOS的各个极的工作电压相同，进而使镜像晶体管和第一非门10111中PMOS处于相同的工作状态，进而保证镜像晶体管对第一非门10111中PMOS的翻转电流的镜像准确度，有助于提高PMOS管的翻转电流的准确度。
当镜像晶体管为NMOS管时，镜像晶体管的源极接地。如此，可以保证镜像晶体管的各个极的工作电压和第一非门10111中NMOS的各个极的工作电压相同，进而使镜像晶体管和第一非门10111中NMOS处于相同的工作状态，进而保证镜像晶体管对第一非门10111中NMOS的翻转电流的镜像准确度，有助于提高NMOS管的翻转电流的准确度。
在本公开实施例的一种示例中，参照图7所示，上述电压控制电路可以进一步包括第一选择电路、第二选择电路和第一延迟电路。其中，第一选择电路用于控制镜像晶体管的栅极电压信号，第二选择电路用于控制镜像晶体管的漏极电压信号。
从图7中可以看出，第一选择电路的控制输入端直接与选择信号生成电路连接，用于接收选择信号。而第二选择电路的控制输入端与第一延迟电路的输出端连接，且第一延迟电路的输入端与选择信号生成电路的输出端连接，第二选择电路的控制输入端用于接收延迟的选择信号。
可以理解的是，第一延迟电路用于对选择信号进行延迟后发送给第二选择电路，以使第二选择电路对漏极电压信号的控制滞后于第一选择电路对栅极电压信号的控制，这与第一非门10111的第二电压信号滞后于该第一非门10111的第一电压信号一致。如此，第二选择电路接收到选择信号的时间滞后于第一选择电路接收到选择信号的时间，也就可以使第二选择电路对漏极电压信号的控制滞后于第一选择电路对栅极电压信号的控制。
需要说明的是，上述第一延迟电路可以是任意逻辑电路，以通过逻辑电路的处理过程来达到延迟的目的。例如，第一延迟电路包括奇数个级联的反相器。考虑到同一第一反向单元10111的第二电压信号滞后于该第一反向单元的第一电压信号的时长，是一个反相器的处理时长。从而这里可以选取一个反相器实现延迟，可以准确的将选择信号延迟一个反相器的处理时长。参照图10或11所示，若将该反相器的处理时长记为t，第一选择电路对栅极电压信号的控制在t1时刻进行，从而，第二选择电路对漏极电压信号的控制在t3＝t1+t时刻进行。这样，可以使镜像晶体管的漏极和第一非门10111中晶体管的漏极在同一时刻相同，有助于提高镜像翻转电流的准确度。
图8是本公开实施例提供的镜像晶体管为PMOS管时镜像测试电路的结构示意图，图9是本公开实施例提供的镜像晶体管为NMOS管时镜像测试电路的结构示意图。参照图8和图9所示，上述第一选择电路和第二选择电路均可以为多路选择器。
参照图8所示，第一选择电路的其中一个数据输入端1与第一反向单元1011的第一输入端(也就是第一反向单元1011中的第一非门10111的输入端)连接，第一选择电路 的另一个数据输入端0可以接入电源电压信号VDD。当选择信号为高电平时，指示第一输入端的电平发生电平翻转。此时，第一选择电路选择与其数据输入端1连接的第一非门10111的输入端的第一电压信号作为其输出信号，第一选择电路的输出端与镜像晶体管PMOS的栅极G连接，即第一选择电路用于将第一电压信号作为镜像晶体管PMOS的栅极电压信号。
相应的，当第一延迟电路为CMOS反相器等具有反相功能的器件时，第二选择电路从控制输入端接收的信号是选择信号的反相信号。从而，参照图8所示，第二选择电路的其中一个数据输入端0与第一输出端连接，第二选择电路的输出端与镜像晶体管PMOS的漏极D连接。从而，在选择信号为高电平以指示第一输入端的电平发生电平翻转时，将数据输入端0接收的第二电压信号作为镜像晶体管PMOS的漏极电压信号。
参照图9所示，第一选择电路的其中一个数据输入端0与第一反向单元1011的第一输入端连接，第一选择电路的另一个数据输入端1可以接地GND。当选择信号为低电平时，指示第一输入端的电平发生电平翻转。此时，第一选择电路选择与其数据输入端0连接的第一反向单元10111的输入端的第一电压信号作为其输出信号，第一选择电路的输出端与镜像晶体管NMOS的栅极G连接，即第一选择电路用于在选择信号为低电平以指示出现电平翻转时，将第一电压信号作为镜像晶体管NMOS的栅极电压信号。
相应的，当第一延迟电路为CMOS反相器等具有反相功能的器件时，第二选择电路从控制输入端接收的信号是选择信号的反相信号。从而，参照图9所示，第二选择电路的其中一个数据输入端1与第一非门10111的输出端连接，第二选择电路的输出端与镜像晶体管NMOS的漏极D连接，用于在选择信号为低电平以指示第一输入端的电平发生电平翻转时，将数据输入端1接收的第二电压信号作为镜像晶体管NMOS的漏极电压信号。
从图8和图9中可以看出，在第一输入端产生电平翻转时，上述第一选择电路和第二选择电路可以控制镜像晶体管的栅极G和漏极D的工作电压，以使其分别与第一非门10111中的晶体管的栅极G的漏极D的电压一致。在第一输入端未产生电平翻转时，上述第一选择电路和第二选择电路可以工作在任意状态下，从而，第一选择电路的另一个数据输入端和第二选择电路的另一个数据输入端可以接入任意电压信号。
但是，为了更好的节约电能，在第一输入端未产生电平翻转时，可以通过第一选择电路和第二选择电路控制镜像晶体管截止。参照图8所示，当镜像晶体管为PMOS管时，第一选择电路的另一个数据输入端0可以接入电源电压信号VDD。从而，第一选择电路还用于在选择信号为低电平以指示第一输入端的电平未发生电平翻转时，将电源电压信号VDD作为镜像晶体管PMOS的栅极电压信号。第二选择电路的另一个数据输入端1接地GND，第二选择电路用于在选择信号为低电平以指示第一输入端的电平未发生电平翻转时，将镜像晶体管的漏极接地。这样，镜像晶体管PMOS管截止。
可以看出，图8所示的镜像测试电路1022是在选择信号为高电平以指示电平翻转时的结构。在实际应用中，还可以在选择信号为低电平时，指示第一输入端的电平发生电平翻转。此时，图8中的第一选择电路的数据输入端1和0连接的电路需要交换，第二选择电路的数据输入端1和0连接的电路也需要交换，在此再赘述。
参照图9所示，当镜像晶体管为NMOS管时，第一选择电路的另一个数据输入端1接地。从而第一选择电路还用于在选择信号为高电平以指示第一输入端的电平未发生电平 翻转时，控制镜像晶体管NMOS的栅极G接地。此外，第二选择电路的另一个数据输入端0接入电源电压信号VDD，第二选择电路还用于在选择信号为高电平以指示第一输入端的电平未发生电平翻转时，将电源电压信号VDD作为镜像晶体管NMOS的漏极电压信号。这样，镜像晶体管NMOS截止。
上述选择信号生成电路用于根据其中的反相电路的延迟作用，识别镜像控制信号的电平翻转，也就是实现了识别第一输入端是否出现电平翻转。
可以看出，图9所示的镜像测试电路1022是在选择信号为低电平以指示电平翻转时的结构。在实际应用中，还可以在选择信号为高电平时，指示第一输入端的电平发生电平翻转。此时，图9中的第一选择电路的数据输入端1和0连接的电路需要交换，第二选择电路的数据输入端1和0连接的电路也需要交换，在此再赘述。
此外，从图8和图9中可以看出，第一延迟电路为具有反相功能的反相器。在实际应用中，第一延迟电路还可以不具有反相功能，此时，需要对图8和图9中的第二选择电路的数据输入端1和0连接的电路交换。
上面说明了镜像测试电路1022中的第一选择电路和第二选择电路，下面详细说明选择信号生成电路。
如图8所示，镜像晶体管为PMOS管，选择信号生成电路生成的选择信号在指示第一输入端的电平由高电平到低电平翻转时，将第一电压信号和第二电压信号依次连接至镜像晶体管PMOS的栅极和漏极，以使镜像晶体管PMOS开始导通。这样，镜像晶体管PMOS中的电流就可以镜像第一非门10111中的PMOS管的翻转电流，而且由于镜像晶体管PMOS没有连接NMOS管，镜像晶体管PMOS的电流只包括翻转电流，排除了CMOS翻转过程中NMOS管和PMOS管同时导通产生的漏电流，即可得到了第一非门10111中PMOS管的有效驱动电流。
参照图8所示，选择信号生成电路可以包括或非门和反相电路。或非门的两个输入端分别与第二反向单元的第二输入端、反相电路的输出端连接，反相电路的输入端与第二反向单元的第二输入端连接。
图10是本公开实施例提供的图8所示的镜像测试电路的信号时序图。图10中示出了在镜像控制信号从高电平向低电平翻转时，选择信号、第一延迟电路的输出信号、PMOS管的栅极电压信号和PMOS管的漏极电压信号的时序。
参照图10所示，在t1时刻之前，输入到图8中或非门的镜像控制信号为高电平，从而或非门输出的选择信号始终为低电平。第一延迟电路的输出信号与选择信号反相，从而始终为高电平。因此，图8中的第一选择电路控制PMOS管的栅极电压信号为数据输入端0接收的电源电压信号VDD，也就是高电平，第二选择电路控制PMOS管的漏极电压信号为数据输入端1接收的接地信号GND，也就是低电平信号。
在t1时刻时，镜像控制信号开始从高电平翻转为低电平，并在t2时刻结束翻转。
在t2时刻时，输入到或非门的镜像控制信号翻转为低电平，但由于图8中反相电路的反相以及延迟作用，或非门的另一个输入端仍然为低电平，从而，或非门输出的选择信号翻转为高电平。
上述选择信号的高电平持续一段时长直至t4时刻结束，该高电平的持续时长为反相电路的输入和输出之间的时间延迟。
从图8中可以看出，选择信号是第一延迟电路的输入，从而参照图10所示，第一延迟电路的输出信号是选择信号的反相延迟信号。
在上述图10中高电平的选择信号的作用下，第一选择电路根据该选择信号控制PMOS管的栅极电压信号为数据输入端1从第一输入端接收的第一电压信号，此时，在滞后于镜像控制电路中第二反向单元产生的镜像控制信号预设时间之后，第一反向单元第一输入端的第一电压信号也由高电平翻转为低电平，与第一电压信号连接的PMOS栅极的电压也逐渐变为低电平。同时，第二选择电路根据该选择信号的反相延迟信号，也就是图10中的第一延迟电路的输出信号，控制PMOS管的漏极电压信号为数据输入端0从第一输出端接收的第二电压信号，同理，与第二电压信号连接的PMOS漏极的电压逐渐变为高电平信号。
在t4时刻时，由于选择信号开始从高电平翻转为低电平，从而第一选择电路根据该选择信号控制PMOS管的栅极电压信号为数据输入端0接收的电源电压信号VDD，也就是高电平信号。
由于图8中第一延迟电路的反相延迟作用，第二选择电路的控制输入端接收到的是选择信号的反相延迟信号，在t4时刻，第二选择电路的控制输入端接收到的仍然是低电平信号，第二选择电路根据该反相延迟信号继续控制PMOS管的漏极从数据输入端0接收第二电压信号。
在t5时刻时，由于第一延迟电路的输出信号开始翻转为高电平，从而第一选择电路根据该选择信号控制PMOS管的漏极电压信号为数据输入端1接收的接地信号，也就是低电平信号。
可以看出，当选择信号为高电平信号时，指示第一输入端的电平由高电平到低电平翻转。
在实际应用中，还可以将上述选择信号生成电路的生成信号进行反相之后作为选择信号输入到第一选择电路和第一延迟电路中，以在选择信号为低电平信号时，指示第一输入端的电平从高电平到低电平翻转，从而可以测试PMOS管的翻转电流，此时，图8中的第一选择电路的数据输入端1和0连接的电路需要交换，第二选择电路的数据输入端1和0连接的电路也需要交换，在此不再赘述。
如图9所示，镜像晶体管为NMOS管，选择信号生成电路生成的选择信号在指示第一输入端的电平由低电平到高电平翻转时，将第一电压信号和第二电压信号依次连接至镜像晶体管NMOS的栅极和漏极，以使镜像晶体管NMOS开始导通。这样，镜像晶体管NMOS中的电流就可以镜像第一非门10111中的NMOS管的翻转电流，而且由于镜像晶体管NMOS没有连接PMOS管，镜像晶体管NMOS的电流只包括翻转电流，排除了CMOS翻转过程中NMOS管和PMOS管同时导通产生的漏电流，即可得到了第一非门10111中NMOS管的有效驱动电流。
参照图9所示，选择信号生成电路包括与非门和反相电路，与非门的两个输入端分别与第二反向单元的第二输入端、反相电路的输出端连接，反相电路的输入端与第二反向单元的第二输入端连接。
从图8和图9中还可以看出，VDD和第二选择电路的控制输入端之间还连接有一电容C，该电容C可以延迟输入到控制输入端的信号。
图11是本公开实施例提供的图9所示的镜像测试电路的信号时序图。图11中示出了 在镜像控制信号从低电平向高电平翻转时，选择信号、第一延迟电路的输出信号、NMOS管的栅极电压信号和NMOS管的漏极电压信号的时序。
参照图11所示，在t1时刻之前，输入到图9中与非门的镜像控制信号为低电平，从而与非门输出的选择信号始终为高电平。第一延迟电路的输出信号与选择信号反相，从而始终为低电平。因此，图9中的第一选择电路控制NMOS管的栅极电压信号为数据输入端1接收的接地信号GND，也就是低电平，第二选择电路控制NMOS管的漏极电压信号为数据输入端0接收的电源电压信号VDD，也就是高电平信号。
在t1时刻时，镜像控制信号开始从低电平翻转为高电平，并在t2时刻结束翻转。
在t2时刻时，输入到与非门的镜像控制信号翻转为高电平，但由于图9中反相电路的反相以及延迟作用，与非门的另一个输入端仍然为高电平，从而，与非门输出的选择信号翻转为低电平。
上述选择信号的低电平持续一段时长直至t4时刻结束，该低电平的持续时长为反相电路的输入和输出之间的时间延迟。
从图9中可以看出，选择信号是第一延迟电路的输入，第一延迟电路的输出信号是选择信号的反相延迟信号。
在上述图11中低电平的选择信号的作用下，第一选择电路根据该选择信号控制NMOS管的栅极电压信号为数据输入端0从第一输入端接收的第一电压信号，此时，在滞后于镜像控制电路中第二反向单元产生的镜像控制信号预设时间之后，第一反向单元的第一输入端的第一电压信号也由低电平翻转为高电平，与第一电压信号连接的NMOS栅极的电压也逐渐变为高电平。同时，第二选择电路根据该选择信号的反相延迟信号，也就是图11中的第一延迟电路的输出信号，控制NMOS管的漏极电压信号为通过第二选择电路的数据输入端1从第一输出端接收的第二电压信号，同理，与第二电压信号连接的NMOS漏极的电压逐渐变为低电平信号。
在t4时刻时，由于选择信号开始从低电平翻转为高电平，从而第一选择电路根据该选择信号控制NMOS管的栅极电压信号为数据输入端1接收的接地信号GND，也就是低电平信号。
由于图9中第一延迟电路的反相延迟作用，第二选择电路的控制输入端接收到的是选择信号的反相延迟信号，在t4时刻，第二选择电路的控制输入端接收到的仍然是高电平信号，第二选择电路根据该反相延迟信号继续控制NMOS管的漏极从数据输入端1接收第二电压信号。
在t5时刻时，由于第一延迟电路的输出信号开始翻转为低电平，从而第二选择电路根据该选择信号控制NMOS管的漏极电压信号为从数据输入端0接收的电源电压信号VDD，也就是高电平信号。
可以看出，当选择信号为低电平信号时，指示第一输入端的电平由低电平到高电平翻转。
在实际应用中，还可以将上述选择信号生成电路生成的信号进行反相之后作为选择信号输入到第一选择电路和第一延迟电路中，以在选择信号为高电平信号时，指示第一输入端的电平从低电平到高电平翻转，从而可以测试NMOS管的翻转电流。
在一些实施方式中，上述反相电路包括奇数个级联的反相器，图8和图9中示例性给 出了三个反相器构成的反相电路。奇数个级联的反相器不仅可以实现镜像控制信号的反相，还可以实现延迟，也就是通过一种电路同时实现多种功能，有助于降低电路成本。
图12是本公开实施例提供的一种测试系统的结构示意图。参照图12所示，该测试系统20包括：使能信号产生电路21和测试电路100。其中，使能信号产生电路21的输出端与测试电路100连接，使能信号产生电路21生成的使能信号用于驱动测试电路100运行。
当测试电路100包括图5所示的环形振荡电路101时，使能信号产生电路21的输出端与图5中的使能输入端连接。
在一些实施方式中，上述测试系统20还可以包括分频元件22和输出缓冲元件23。其中，分频元件22的输入端与测试电路100的环形振荡电路101的其中一个第一输出端连接，输出缓冲元件23与分频元件22的输出端连接。
其中，分频元件22用于对测试电路100生成的振荡信号进行分频处理，例如，可以为1/2分频器等。
输出缓冲元件23用于对分频之后的信号进行缓冲，以输出给外部设备。
图13是本公开实施例提供的一种测试方法的步骤流程图，用于前述测试系统。参照图13所示，该测试方法可以包括S301至S303。
S301：通过使能信号驱动测试电路运行。
S302：在测试电路的运行过程中，获取测试电路中的镜像晶体管的电流和环形振荡电路的振荡频率。
S303：根据镜像晶体管的电流和振荡频率，确定环形振荡电路的第一反向单元中的晶体管的等效参数，等效参数包括以下至少一种：等效电容和等效电阻。
本公开实施例可以通过镜像晶体管的电流准确的测试第一非门中的翻转电流，从而可以提高等效电容和等效电阻的准确度。
本公开实施例还提供一种半导体器件，包括权利要求前述测试系统。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
为了方便解释，已经结合具体的实施方式进行了上述说明。但是，上述示例性的讨论不是意图穷尽或者将实施方式限定到上述公开的具体形式。根据上述的教导，可以得到多种修改和变形。上述实施方式的选择和描述是为了更好的解释原理以及实际的应用，从而使得本领域技术人员更好的使用所述实施方式以及适于具体使用考虑的各种不同的变形的实施方式。

Claims (22)

  1. 一种测试电路，包括环形振荡电路和镜像电路；
    其中，所述环形振荡电路包括依次级联的多个第一反向单元，每个所述第一反向单元包括第一输入端和第一输出端，至少一个所述第一反向单元的第一输入端和第一输出端与所述镜像电路连接；
    所述镜像电路，用于接收所述第一反向单元的所述第一输入端对应的第一电压信号和所述第一输出端对应的第二电压信号，并在所述第一反向单元的所述第一输入端发生电平翻转时，根据所述第一电压信号和所述第二电压信号镜像所述第一反向单元中晶体管的翻转电流。
  2. 根据权利要求1所述的测试电路，其中，所述镜像电路包括镜像控制电路和至少一个镜像测试电路；
    所述镜像控制电路，包括有至少一个控制信号输出端，所述控制信号输出端与所述镜像测试电路一一对应连接，所述镜像控制电路用于通过所述控制信号输出端向所述镜像测试电路发送镜像控制信号，所述镜像控制信号用于指示所述第一反向单元的翻转状态；
    每个所述镜像测试电路还与一个所述第一反向单元的第一输入端和第一输出端连接，所述镜像测试电路用于根据所述镜像控制信号确定所述第一反向单元的所述第一输入端是否发生电平翻转，并在发生电平翻转时，根据所述第一电压信号和所述第二电压信号镜像所述第一反向单元中晶体管的翻转电流。
  3. 根据权利要求2所述的测试电路，其中，
    所述镜像控制电路包括依次级联的多个第二反向单元，所述第二反向单元的数量与所述第一反向单元的数量相同，所述镜像控制电路与所述环形振荡电路工作在同一电源电压下；
    每个所述第二反向单元包括第二输入端，至少一个所述第二输入端作为所述控制信号输出端与所述镜像测试电路连接，用于将所述第二反向单元的所述第二输入端的电压信号作为所述镜像控制信号发送给所述镜像测试电路。
  4. 根据权利要求3所述的测试电路，其中，
    所述镜像测试电路包括镜像晶体管和测试控制电路，所述测试控制电路分别与所述控制信号输出端、所述第一输入端、所述第一输出端和所述镜像晶体管连接，所述测试控制电路用于根据所述镜像控制电路发送的所述镜像控制信号，确定所述第一输入端是否发生电平翻转，并在发生电平翻转时，根据接收到的所述第一电压信号和所述第二电压信号控制所述镜像晶体管的工作电压，使所述镜像晶体管的电流与所述第一反向单元中晶体管的电流相同。
  5. 根据权利要求4所述的测试电路，其中，所述测试控制电路包括选择信号生成电路和电压控制电路；
    所述选择信号生成电路与所述镜像控制电路、所述电压控制电路连接，所述选择信号生成电路用于根据所述镜像控制电路发送的镜像控制信号输出选择信号，所述选择信号用于指示所述第一输入端的电平是否将要发生电平翻转；
    所述电压控制电路分别与所述选择信号生成电路、所述第一输入端、所述第一输出端和所述镜像晶体管连接，所述电压控制电路用于在所述选择信号表示所述第一输入端发生 电平翻转时，控制所述镜像晶体管的栅极电压信号与所述第一电压信号一致，以及所述镜像晶体管的漏极电压信号与所述第二电压信号一致。
  6. 根据权利要求5所述的测试电路，其中，所述电压控制电路包括第一选择电路、第二选择电路和第一延迟电路；
    所述第一选择电路的控制输入端与所述选择信号生成电路连接，用于接收所述选择信号；所述第二选择电路的控制输入端与所述第一延迟电路的输出端连接，且所述第一延迟电路的输入端与所述选择信号生成电路的输出端连接，所述第二选择电路的控制输入端用于接收延迟的所述选择信号；
    所述第一选择电路的其中一个数据输入端与所述第一输入端连接，所述第一选择电路的输出端与所述镜像晶体管的栅极连接，用于在所述选择信号指示所述第一输入端的电平发生电平翻转时，将所述第一电压信号作为所述镜像晶体管的栅极电压信号；
    所述第二选择电路的其中一个数据输入端与所述第一输出端连接，所述第二选择电路的输出端与所述镜像晶体管的漏极连接，用于在所述选择信号指示所述第一输入端的电平发生电平翻转时，将所述第二电压信号作为所述镜像晶体管的漏极电压信号。
  7. 根据权利要求6所述的测试电路，其中，当所述镜像晶体管为PMOS管时，所述第一选择电路的另一个数据输入端接入电源电压信号，所述第一选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述电源电压信号作为所述镜像晶体管的栅极电压信号；
    所述第二选择电路的另一个数据输入端接地，所述第二选择电路用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述镜像晶体管的漏极接地。
  8. 根据权利要求6所述的测试电路，其中，当所述镜像晶体管为NMOS管时，所述第一选择电路的另一个数据输入端接地，所述第一选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，控制所述镜像晶体管的栅极接地；
    所述第二选择电路的另一个数据输入端接入电源电压信号，所述第二选择电路还用于在所述选择信号指示所述第一输入端的电平未发生电平翻转时，将所述电源电压信号作为所述镜像晶体管的漏极电压信号。
  9. 根据权利要求4所述的测试电路，所述测试电路还包括：第二延迟电路，所述第二延迟电路的输入端和所述镜像控制电路的使能输入端接入同一使能信号，所述第二延迟电路用于将接收到的所述使能信号延迟预设时间后，通过所述第二延迟电路的输出端输出至所述环形振荡电路的使能输入端，所述第二延迟电路用于控制所述环形振荡电路产生的振荡信号滞后于所述镜像控制电路产生的镜像控制信号。
  10. 根据权利要求9所述的测试电路，其中，所述第二延迟电路包括偶数个级联的反相器。
  11. 根据权利要求7所述的测试电路，其中，所述选择信号生成电路包括或非门和反相电路，所述或非门的两个输入端分别与所述第二反向单元的第二输入端、所述反相电路的输出端连接，所述反相电路的输入端与所述第二反向单元的第二输入端连接，当所述选择信号为高电平信号时，指示所述第一输入端的电平由高电平到低电平翻转。
  12. 根据权利要求8所述的测试电路，其中，所述选择信号生成电路包括与非门和反相电路，所述与非门的两个输入端分别与所述第二反向单元的第二输入端、所述反相电路的 输出端连接，所述反相电路的输入端与所述第二反向单元的第二输入端连接，当所述选择信号为低电平信号时，指示所述第一输入端的电平由低电平到高电平翻转。
  13. 根据权利要求11或12所述的测试电路，其中，所述反相电路包括奇数个级联的反相器。
  14. 根据权利要求9所述的测试电路，其中，第一级所述第一反向单元包括第一与非门，其余所述第一反向单元包括第一非门，所述第一与非门的两个输入端分别作为所述环形振荡电路的所述使能输入端和所述第一反向单元的第一输入端，所述第一与非门的输出端作为所述第一反向单元的第一输出端，所述第一非门的输入端和输出端分别作为对应的所述第一反向单元的第一输入端和第一输出端。
  15. 根据权利要求14所述的测试电路，其中，第一级所述第二反向单元包括第二与非门，其余所述第二反向单元包括第二非门，所述第二与非门的两个输入端分别作为所述镜像控制电路的所述使能输入端和所述第二反向单元的第二输入端，所述第二与非门的输出端作为所述第二反向单元的第二输出端，所述第二非门的输入端和输出端分别作为对应的所述第二反向单元的第二输入端和第二输出端。
  16. 根据权利要求15所述的测试电路，其中，所述第一非门和所述第二非门均包括不同类型的第一晶体管和第二晶体管，所述第一与非门的电源输入端和所述第一晶体管的源极均接入同一电源电压信号；
    在所述第一非门和所述第二非门的任意一个非门中，所述第一晶体管的栅极与所述第二晶体管的栅极连接，并作为对应的所述非门的输入端；所述第一晶体管的漏极与所述第二晶体管的漏极连接，并作为对应的所述非门的输出端，所述第二晶体管的源极接地。
  17. 根据权利要求4至12任一项所述的测试电路，其中，当所述镜像晶体管为PMOS管时，所述镜像晶体管的源极与所述第一反向单元接入大小相同的电源电压信号；当所述镜像晶体管为NMOS管时，所述镜像晶体管的源极接地。
  18. 根据权利要求6所述的测试电路，其中，所述第一延迟电路包括奇数个级联的反相器。
  19. 一种测试系统，包括使能信号产生电路和权利要求1至18任一项所述的测试电路，所述使能信号产生电路的输出端与所述测试电路连接，所述使能信号产生电路生成的使能信号用于驱动所述测试电路运行。
  20. 根据权利要求19所述的测试系统，还包括分频元件和输出缓冲元件，所述分频元件的输入端与所述测试电路的环形振荡电路的其中一个第一输出端连接，所述输出缓冲元件与所述分频元件的输出端连接。
  21. 一种测试方法，用于权利要求19或20所述的测试系统，所述测试方法包括：
    通过使能信号驱动所述测试电路运行；
    在所述测试电路的运行过程中，获取所述测试电路中的镜像晶体管的电流和所述环形振荡电路的振荡频率；
    根据所述镜像晶体管的电流和所述振荡频率，确定所述环形振荡电路的第一反向单元中的晶体管的等效参数，所述等效参数包括以下至少一种：等效电容和等效电阻。
  22. 一种半导体器件，包括权利要求19或20所述的测试系统。
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