WO2021134651A1 - 时钟占空比的校准装置 - Google Patents

时钟占空比的校准装置 Download PDF

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Publication number
WO2021134651A1
WO2021134651A1 PCT/CN2019/130872 CN2019130872W WO2021134651A1 WO 2021134651 A1 WO2021134651 A1 WO 2021134651A1 CN 2019130872 W CN2019130872 W CN 2019130872W WO 2021134651 A1 WO2021134651 A1 WO 2021134651A1
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Prior art keywords
clock
electrically connected
module
buffer circuit
type
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PCT/CN2019/130872
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English (en)
French (fr)
Inventor
王宇涛
闵卿
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/130872 priority Critical patent/WO2021134651A1/zh
Priority to CN201980103324.9A priority patent/CN114868336A/zh
Publication of WO2021134651A1 publication Critical patent/WO2021134651A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Definitions

  • the embodiment of the present application relates to a communication system, and in particular, to a clock duty ratio calibration device.
  • the crystal oscillator is used as a reference clock source, and the requirements for its noise and oscillation frequency also increase.
  • the crystal oscillator module is a clock generating device including a crystal oscillator.
  • the reference clock obtained by multiplying the frequency of the clock output by the crystal oscillator circuit will have spurs, which will affect the normal operation of the business using the reference clock. It is of great significance to calibrate the duty cycle of the clock output by the oscillation circuit block.
  • the embodiment of the present application provides a clock duty cycle calibration device, which can accurately calibrate the duty cycle of the clock to a preset duty cycle.
  • an embodiment of the present application provides a clock duty cycle calibration device, including: a crystal oscillator, a buffer module, and a calibration module electrically connected in sequence; wherein the buffer module includes an adjustable buffer circuit; the adjustable The first input terminal of the buffer circuit is electrically connected to the calibration module, the second input terminal of the adjustable buffer circuit is electrically connected to the crystal oscillator, and the output terminal of the adjustable buffer circuit is electrically connected to the calibration module.
  • the number of switches of the first type and the number of switches of the second type in the open state of the buffer module are related to the duty cycle of the clock;
  • the calibration module is used to feed the first input terminal of the adjustable buffer circuit A buffer circuit control signal is sent, and the buffer circuit control signal is used to control the number of switches of the first type and the number of switches of the second type that are in an open state in the buffer module.
  • the first type of switch is a P-type MOS transistor
  • the second type of switch is an N-type MOS transistor.
  • the buffer module of the clock duty ratio calibration device in this solution includes an adjustable buffer circuit.
  • the number of the first type of switch and the number of the second type of switch in the adjustable buffer circuit that are in the open state can affect the clock's duty ratio, and
  • the calibration module can send a buffer circuit control signal to adjust the number of the first type of switch and the second type of switch in the open state of the buffer module. Therefore, the device of this embodiment can adjust the number of the first type of switch and the second type of switch in the open state in the buffer module.
  • the number of switches of the second type realizes the calibration of the duty cycle of the clock, and the calibration result is accurate.
  • the buffer module further includes a fixed buffer circuit, and the number of switches of the first type in the open state in the fixed buffer circuit is the first fixed number and the number of switches of the second type in the open state.
  • the number is a second fixed number; the first input terminal of the fixed buffer circuit is electrically connected with the crystal oscillator, and the output terminal of the fixed buffer circuit is electrically connected with the calibration module.
  • the setting of the fixed buffer circuit in this solution can make the first type of switch and the second type of switch in the open state exist in the buffer module at the same time, so as to ensure the normal operation of the buffer module.
  • the accuracy of the clock duty cycle calibration can be adjusted by adjusting the number of the first type of switches and the number of the second type of switches included in the fixed buffer circuit.
  • the adjustable buffer circuit includes N switch groups of the first type connected in series and M switch groups of the second type connected in series.
  • the drain of a switch group is electrically connected to the drain of the second switch group in the M second type switch groups and then is electrically connected to the calibration module; the gate of the first switch group and the gate of the second switch group are electrically connected After being connected, it is electrically connected to the crystal oscillator; the N and M are both integers greater than or equal to 2; the gates of the other switch groups in the N first type switch groups are connected to the M second type switches
  • the grids of other switch groups in the group are all electrically connected to the calibration module.
  • the adjustable buffer circuit in this scheme is simple and easy to implement. In addition, it is possible to realize that only one switch of the same adjustable buffer circuit is in the on state, so that the number of the first type of switches and the number of the second type of switches in the entire buffer module are easier to control, so that the duty cycle of the clock is more efficient.
  • the calibration module includes a phase detection submodule, and the phase detection submodule is configured to output the difference between the delayed rising edge of the clock and the rising edge of the clock reversed.
  • the alignment result which is used for the generation of the buffer circuit control signal.
  • the phase detection sub-module when the clock is the first clock, the phase detection sub-module is configured to output the first rising edge of the delayed rising edge of the first clock and the rising edge of the second clock after the clock is reversed. Alignment result; when the clock is the second clock, the phase detection sub-module is used to output the delayed rising edge of the second clock and the rising edge of the third clock after the second clock is reversed The second alignment result. The first alignment result and the second alignment result are used together to generate the buffer circuit control signal.
  • the phase detection sub-module of the calibration module provided by this solution can output the alignment result between the delayed rising edge of the clock and the rising edge after the clock is reversed.
  • the process of obtaining the alignment result involves the low time or high level of the clock Time, so that the calibration module can realize the purpose of judging whether the current duty cycle of the clock is the preset duty cycle.
  • the phase detection sub-module includes a first multiplexer, a second multiplexer, a delayer, and a phase detector; the output terminal of the first multiplexer is connected to The input terminal of the delay device is electrically connected, the output terminal of the delay device is also electrically connected to the input terminal of the phase detector, and the output terminal of the second multiplexer is electrically connected to the input terminal of the phase detector. Terminals are electrically connected.
  • the first channel of the first multiplexer is used to input a first clock
  • the first channel of the second multiplexer is used to input a second clock after the first clock is reversed
  • the second channel of the first multiplexer is used to input the second clock
  • the second channel of the second multiplexer is used to input the third inverted second clock. clock.
  • the phase detection sub-module of this solution can reduce the number of delayers and phase detectors, and reduce the complexity of the phase detection sub-module.
  • the phase detection sub-module includes: a first delayer, a second delayer, a first phase detector, and a second phase detector; the output of the first delayer The terminal is electrically connected with the input terminal of the first phase detector, and the output terminal of the second delayer is electrically connected with the input terminal of the second phase detector.
  • the input end of the first delayer is used for inputting a first clock
  • the input end of the first phase detector is used for inputting the clock delayed by the first delayer and the clock The second clock after being reversed
  • the input end of the second delayer is used to input the second clock
  • the input end of the second phase detector is used to input the second clock by the first The clock delayed by the second delayer and the third clock after the second reverse clock is reversed.
  • the phase detection sub-module of this solution can improve the efficiency of the calibration clock duty cycle.
  • the calibration module further includes a reverse sub-module, which is electrically connected to the phase detection sub-module; the reverse sub-module is used to reverse the clock. To enable the phase detection sub-module to output the alignment result.
  • the reverse sub-module provided by this solution can output the reverse clock, so as to realize the purpose of judging whether the current duty cycle of the clock is the preset duty cycle together with the phase detection sub-module and the processor.
  • the reversing sub-module includes a first inverter and a second inverter, and the output terminal of the first inverter is electrically connected to the input terminal of the second inverter. Connection; the first inverter and the second inverter are connected with the phase detection sub-module.
  • the calibration module includes a processor, which is electrically connected to the first input terminal of the adjustable buffer circuit; The alignment result of the rising edge and the rising edge after the clock is reversed outputs the buffer circuit control signal.
  • This solution realizes the output of the buffer circuit control signal, that is, realizes the purpose of calibrating the duty cycle of the clock.
  • a frequency multiplication circuit is further included; the frequency multiplication circuit is electrically connected to the calibration module.
  • the setting of the frequency multiplier circuit in this solution can achieve different duty cycles and/or clocks of different frequencies.
  • an embodiment of the present application provides a method for calibrating a clock duty ratio.
  • the method is based on the above-mentioned clock duty ratio calibration device.
  • the method includes: acquiring a first delay corresponding to a first clock;
  • the rising edge of the clock is delayed by the first delayer of the calibration module, and the first time delay can be aligned with the rising edge of the second clock;
  • the second clock is the odd-numbered reverse of the first clock Obtain the second time delay corresponding to the second clock, and the rising edge of the second clock is delayed by the second delayer of the calibration module.
  • the second time delay can be compared with the third The rising edge of the clock is aligned, and the third clock is obtained after the second clock is reversed an odd number of times; according to the first time delay and the second time delay, the duty of the first clock is calibrated ratio.
  • the first delayer and the second delayer may be the same delayer or different delayers.
  • the first delay corresponding to the first clock may be referred to as the first delay of the first delayer, and the second delay corresponding to the second clock may be referred to as the second delay of the second delayer.
  • the first clock is obtained by at least the original clock generated by the crystal oscillator after passing through a buffer module, and the buffer module includes an adjustable buffer circuit; and the calibration is performed according to the first time delay and the second time delay.
  • the duty cycle of the first clock includes: if the first time delay and the second time delay are not the same, sending a buffer circuit control signal to the adjustable buffer circuit to adjust the adjustable buffer circuit The number of switches of the first type and the number of switches of the second type that are in the open state in the switch to obtain the updated first clock, the second clock, and the third clock; return to get the corresponding to the first clock Operation of the first delay corresponding to the second clock and the second delay corresponding to the second clock until the first delay corresponding to the first clock is the same as the second delay corresponding to the second clock, it is determined
  • the duty cycle of the first clock is calibrated to a preset duty cycle.
  • the acquiring the first time delay corresponding to the first clock includes: receiving a first alignment result from a first phase detector, where the first alignment result indicates the first clock The rising edge of is delayed by the first delayer and aligned with the rising edge of the second clock; the output terminal of the first delayer is connected to the first phase detector; it is determined to be aligned with the first As a result, the corresponding delay of the first delayer is the first delay corresponding to the first clock.
  • the receiving the first alignment result from the first phase detector includes: receiving the first alignment result from the first phase detector, if the first alignment result is The result indicates that the rising edge of the first clock is not aligned with the rising edge of the second clock after being delayed by the first delayer, and then the first type of delay control signal is sent to all according to the alignment result of the first path.
  • the delayer to update the delay of the first delayer; and return to the step of receiving the first alignment result from the first phase detector until the first alignment result is received.
  • a second alignment result from a second phase detector is received, where the second alignment result indicates that the rising edge of the second clock is delayed by the second delayer and is delayed by the second The rising edges of the three clocks are aligned; the output terminal of the second delayer is connected to the second phase detector; it is determined that the delay of the second delayer corresponding to the second alignment result is the The second time delay corresponding to the second clock.
  • the receiving the second alignment result from the second phase detector includes: receiving the second alignment result from the second phase detector, and if the second alignment result is Indicate that the rising edge of the second clock is delayed by the second delayer and is not aligned with the rising edge of the third clock, then the second type of delay control signal is sent to the The second delayer to update the time delay of the second delayer; returning to the step of receiving the second alignment result from the second phase detector until the second alignment result is received.
  • first phase detector and the second phase detector may be the same phase detector, or may be different phase detectors.
  • calibrating the duty cycle of the first clock according to the first time delay and the second time delay includes: if the first time delay and the second time delay If the delay is the same, it is determined that the duty cycle of the first clock is calibrated to the preset duty cycle.
  • the method further includes: sending a first time delay control signal and a second time delay control signal to the delayer of the frequency multiplier circuit, so that the output of the frequency multiplier circuit accounts for A target clock with an empty ratio of 1/N; the first delay control signal is used to indicate a second fixed delay, the second fixed delay is 1/N times the first fixed delay, and the second The delay second control signal is used to indicate a second adjustment delay, the second adjustment delay is 1/N times the first adjustment delay, and the first fixed delay is the same as the first adjustment delay.
  • the sum of delays is the delay of the first delayer or the second delayer when the duty cycle of the first clock is calibrated to the preset duty cycle; the delay of the delayer of the frequency multiplication circuit is The sum of the second fixed time delay and the second adjusted time delay; the frequency of the target clock is twice the input clock of the frequency multiplication circuit.
  • the method further includes: sending a first time delay control signal and a second time delay control signal to the delayer of the frequency multiplier circuit, so that the output of the frequency multiplier circuit accounts for A target clock with an empty ratio of 1/N; the first delay control signal is used to indicate a first fixed delay, the second delay control signal is used to indicate a first adjustment delay, and the first fixed time The sum of the delay and the first adjusted delay is the delay of the first delayer or the second delayer when the duty cycle of the first clock is calibrated to the preset duty cycle; the frequency multiplier circuit The fixed delay of the delayer of is 1/N times the first fixed delay, and the adjustment delay of the delayer of the frequency multiplier circuit is 1/N times the first adjustment delay; The frequency of the target clock is twice the input clock of the frequency multiplication circuit.
  • the method further includes: sending the first time delay control signal and the second time delay control signal to the delayer of each of the P frequency multipliers connected in series in sequence,
  • the first delay control signal is used to indicate a first fixed delay
  • the second The time delay control signal is used to indicate a first adjustment time delay
  • the sum of the first fixed time delay and the first adjustment time delay is the first time when the duty cycle of the first clock is calibrated to a preset duty cycle
  • the time delay of a delayer or a second delayer; the frequency of the target clock is 2 p times the input clock of the first multiplier circuit in the P multiplier circuits, and the p multiplier fixed frequency delay circuit delay is 1/2 p times said first fixed delay, adjusting the delay of the first adjustable delay times 1/2 p.
  • the buffer module of the clock duty cycle calibration device in this solution includes an adjustable buffer circuit.
  • the number of the first type of switch and the second type of switch in the adjustable buffer circuit in the open state can affect the clock duty cycle, and the calibration module
  • the buffer circuit control signal can be sent to adjust the number of the first type of switch and the second type of switch in the open state in the adjustable buffer circuit. Therefore, the device of this embodiment can adjust the number of the first type of switch and the second type of switch in the open state in the buffer module.
  • the number of switches of the second type accurately calibrates the duty cycle of the clock to the preset duty cycle.
  • FIG. 1 is a schematic diagram of a structure of a clock duty ratio calibration device provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a group of switches of the first type provided by an embodiment of the application;
  • FIG. 3 is a schematic diagram of a structure of an adjustable buffer circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of another structure of an adjustable buffer circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a buffer module provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a structure of a fixed buffer circuit provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of another structure of a buffer module provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of a calibration module provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of another calibration module provided by an embodiment of the application.
  • FIG. 10 is a schematic diagram of another structure of a clock duty ratio calibration device provided by an embodiment of the application.
  • FIG. 11 is a schematic diagram of another structure of a clock duty ratio calibration device provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a frequency multiplication circuit provided by an embodiment of this application.
  • FIG. 13 is a schematic diagram of another structure of a clock duty ratio calibration device provided by an embodiment of the application.
  • FIG. 14 is a schematic diagram of another structure of a clock duty ratio calibration device provided by an embodiment of the application.
  • 15 is a schematic diagram of a clock waveform provided by an embodiment of the application.
  • 16 is a schematic diagram 1 of clock rising edge alignment provided by an embodiment of this application.
  • FIG. 17 is a second schematic diagram of clock rising edge alignment provided by an embodiment of this application.
  • Duty cycle refers to the time ratio of the effective level in a cycle.
  • the standard duty cycle of a square wave is 50% or 0.5, which means that the positive level takes 0.5 cycles and the negative level takes 0.5 cycles.
  • the duty cycle of the clock may not be 0.5.
  • the reference clock obtained by multiplying the clock will have spurs, which will affect the business of using the reference clock. Normally, therefore, it is of great significance to calibrate the duty cycle of the clock whose waveform is a square wave output by the crystal oscillator circuit block to 0.5.
  • the embodiment of the present application provides a clock duty ratio calibration device for calibrating the duty cycle of a clock whose waveform is a square wave output from a crystal oscillator circuit block to 0.5 and a clock duty ratio calibration method based on the device.
  • FIG. 1 is a schematic structural diagram of a clock duty ratio calibration device provided by an embodiment of the application.
  • the clock duty ratio calibration device of this embodiment includes: a crystal oscillator 101, a buffer module 102, and a calibration module 103.
  • the buffer module 102 includes an adjustable buffer circuit, and the adjustable buffer circuit includes a first type of switch and a second type of switch.
  • the number of switches of the first type and the number of switches of the second type in the on-state of the buffer module 102 are related to the duty cycle of the clock.
  • the first input terminal of the adjustable buffer circuit is electrically connected with the calibration module 103
  • the second input terminal of the adjustable buffer circuit is electrically connected with the crystal oscillator 101
  • the output terminal of the adjustable buffer circuit is electrically connected with the calibration module 103.
  • the calibration module 103 is used to send a buffer circuit control signal to the first input terminal of the adjustable buffer circuit, and the buffer circuit control signal is used to control the number of the first type of switches and the number of the second type of switches in the buffer module 102 that are in an open state.
  • the buffer module 102 and the calibration module 103 are respectively described in detail below.
  • the buffer module 102 will be described in detail.
  • the number of adjustable buffer circuits is one or more, and the buffer circuit control signals received by the same buffer circuit are the same. If there are multiple adjustable buffer circuits, the buffer circuit control signals received in the multiple adjustable buffer circuits can be the same or at least two of the adjustable buffer circuits receive different buffer circuit control signals. .
  • the number of switches of the first type can be multiple, and the number of switches of the second type can be multiple.
  • the number of switches of the first type included in different bar buffer circuits may be the same or different, and the number of switches of the second type included in different bar buffer circuits may be the same or different.
  • the first type of switch is a P-type MOS tube (for the convenience of subsequent descriptions, the P-type MOS tube is referred to as a pmos tube); the second type of switch is an N-type MOS tube (for the convenience of subsequent descriptions, it is referred to as N Type MOS tube is nmos tube).
  • the following describes a specific structure of the adjustable buffer circuit.
  • the adjustable buffer circuit includes N switch groups of the first type connected in series and M switch groups of the second type connected in series, the drain of the first switch group of the N first type switch groups and M second type switches
  • the drain of the second switch group in the group is electrically connected to the calibration module 103; the gate of the first switch group and the gate of the second switch group are electrically connected to the crystal oscillator 101.
  • the gates of the other switch groups in the N first-type switch groups and the gates of the other switch groups in the M second-type switch groups are electrically connected to the calibration module 103. That is to say, the gates of the other switch groups in the N first-type switch groups are the first input terminals of the adjustable buffer circuit, and the gates of the other switch groups in the M second-type switch groups are the other switch groups of the adjustable buffer circuit. A first input terminal.
  • the source of the third switch group in the N first-type switch groups may also be connected to the mains power supply, and the source of the fourth switch group in the M second-type switch groups may be grounded.
  • N-2 switch groups of the first type between the third switch group and the first switch group and there are M-2 switch groups of the second type between the fourth switch group and the second switch group.
  • each first type switch group includes at least one first type switch connected in parallel, that is, the source connection of each first type switch and the drain connection of each first type switch in each first type switch group , Deletion connection of each first type switch.
  • FIG. 2 is a schematic diagram of a first type switch group.
  • a first type switch group in FIG. 2 includes two pmos tubes 201 and 202, and the source of the pmos tube 201 is connected to the source of the pmos tube 202, The drain of the pmos tube 201 is connected to the drain of the pmos tube 202, and the drain of the pmos tube 201 is connected to the gate of the pmos tube 202.
  • each switch group of the second type includes at least one switch of the second type connected in parallel.
  • the source of each second-type switch in each second-type switch group is connected, the drain of each second-type switch is connected, and the gate of each second-type switch is connected.
  • the number of the first type switches included in the first type switch group included in each adjustable buffer circuit may be different, and each adjustable buffer circuit may be different.
  • the number of second-type switches included in the second-type switch group included in the snubber circuit may be different.
  • the same adjustable buffer circuit the number of switches of the first type included in each switch group of the first type may be the same, and the number of switches of the second type included in each switch group of the second type may be the same.
  • the number of switches of the first type included may be the same as the number of switches of the second type included in the switch group of the second type.
  • FIG. 3 is a schematic diagram of a structure of an adjustable buffer circuit provided by an embodiment of the application.
  • the adjustable buffer circuit includes two pmos tubes 301 and 302 connected in series, and two nmos tubes 303 and 304 connected in series; among them, the pmos tube 301 is a first type switch group, and the pmos tube 302 is a first switch group.
  • the nmos tube 303 is a second type of switch group, and the nmos tube 304 is a second type of switch group.
  • the gate of the pmos tube 301 and the gate of the nmos tube 304 are both the first input of the adjustable buffer circuit, and the calibration module 103 sends the same buffer circuit control signal xo_dac ⁇ 0> to the gate of the pmos tube 301 and the nmos tube 304
  • the gate of the pmos tube 301 is connected to the mains power supply, and the source of the nmos tube 304 is grounded.
  • the pmos tube 301 is the third switch group of the two switch groups of the first type
  • the nmos tube 304 is the fourth switch group of the two switch groups of the second type.
  • the drain of the pmos tube 302 is connected to the drain of the nmos tube 303, and the output terminal of the adjustable buffer circuit is electrically connected to the calibration module 103, and the output signal is buf_out; the gate of the pmos tube 302 and the gate of the nmos tube 303 are both connected to The crystal oscillator 101 is electrically connected.
  • the gate of the pmos tube 302 and the gate of the nmos tube 303 are the second input terminal of the adjustable buffer circuit.
  • the clock xo_out generated by the crystal oscillator 101 can be input through the second input terminal of the adjustable buffer circuit. Adjust the buffer circuit.
  • the pmos tube 302 is the first switch group of the two switch groups of the first type
  • the nmos tube 303 is the second switch group of the two switch groups of the second type.
  • FIG. 4 is a schematic diagram of another structure of an adjustable buffer circuit provided by an embodiment of the application.
  • the adjustable buffer circuit includes 2 pmos tube groups 401 and 402 connected in series, and 2 nmos tube groups 403 and 404 connected in series.
  • the pmos tube group 401 includes 2 pmos tubes
  • the pmos tube group 402 includes There are 2 pmos tubes
  • the nmos tube group 403 includes 2 nmos tubes
  • the nmos tube group 404 includes 2 nmos tubes.
  • the gate of the pmos tube group 401 and the gate of the nmos tube group 404 are both the first input of the adjustable buffer circuit, and the calibration module 103 sends the same buffer circuit control signal xo_dac ⁇ 1> to the gate of the pmos tube group 401, Grid of nmos tube group 404.
  • the pmos tube group 401 is the third switch group of the two first type switch groups
  • the nmos tube group 404 is the fourth switch group of the two second type switch groups.
  • the drain of the pmos tube group 402 is connected to the drain of the nmos tube group 403 as the output terminal of the adjustable buffer circuit and electrically connected to the calibration module 103, and the output signal is buf_out.
  • the gate of the pmos tube group 402 and the gate of the nmos tube group 403 are electrically connected to the crystal oscillator 101.
  • the gate of the pmos tube group 402 and the gate of the nmos tube group 403 are the second input terminals of the adjustable buffer circuit.
  • the clock xo_out generated by the oscillator 101 is input to the adjustable buffer circuit through the second input terminal of the adjustable buffer circuit.
  • the pmos tube group 402 is the first switch group of the two first type switch groups
  • the nmos tube group 403 is the second switch group of the two second type switch groups.
  • FIG. 5 is a schematic diagram of a buffer module provided by an embodiment of the application.
  • the buffer module 102 includes L adjustable buffer circuits, and the first input end of each adjustable buffer circuit is used to receive the buffer circuit control signal xo_dac ⁇ l> sent by the calibration module 103, that is, it is electrically connected to the calibration module 103. Connection; the second input terminal of each adjustable buffer circuit is used to receive the output signal xo_out of the crystal oscillator 101, that is, the second input terminal is electrically connected to the crystal oscillator 101; the output terminal of each adjustable buffer circuit is It is electrically connected to the calibration module 103.
  • One end of each adjustable buffer circuit is connected to the mains power supply, and the other end is grounded.
  • the adjustable buffer circuit 1 may be as shown in FIG. 3
  • the adjustable buffer circuit 2 may be as shown in FIG.
  • each of the L adjustable buffer circuits includes N switch groups of the first type and M switch groups of the second type.
  • the number of switches of the first type included in each switch group of the first type in the same adjustable buffer circuit is the same, and the number of switches of the second type included in each switch group of the second type in the same adjustable snubber circuit is the same;
  • the ratio of the number of switches of the first type included in each first type switch group in the buffer circuit to the L-th adjustment buffer circuit may be 1: Jerusalem:2 l and/or the first buffer circuit to the L-th adjustment
  • the ratio of the number of switches of the second type included in each switch group of the second type in the snubber circuit may be 1:...:2 l .
  • the buffer module 102 In order to make the first type of switch and the second type of switch in the open state exist in the buffer module 102 at the same time, so as to ensure the normal operation of the buffer module 102, the buffer module 102 also includes a fixed buffer circuit, and the second type of switch in the fixed buffer circuit is in the open state.
  • the number of switches of the first type is a first fixed number and the number of switches of the second type in an on state is a second fixed number.
  • the fixed buffer circuit includes a first input terminal, a second input terminal, and a third input terminal.
  • the first input terminal of the fixed buffer circuit is connected to the output terminal of the crystal oscillator 101, and the second input terminal is used to input the first preset control signal.
  • the third input terminal is used to input the second preset control signal
  • the first preset control signal is a signal that can make the first type of switches in the fixed buffer circuit are all on
  • the second preset control signal is capable of making the fixed
  • the second type of switches in the buffer circuit are all signals in the on state.
  • the fixed buffer circuit further includes an output terminal, and the output terminal of the fixed buffer circuit is electrically connected to the calibration module 103.
  • the number of fixed buffer circuits can be one or more.
  • the fixed buffer circuit includes P switch groups of the first type connected in series and Q switch groups of the second type connected in series, the drain of the first switch group of the P first type switch groups and Q switch groups of the second type
  • the drain electrode of the second switch group in the second switch group is electrically connected to the calibration module 103; the gate of the first switch group and the gate of the second switch group are both electrically connected and then electrically connected to the crystal oscillator 101.
  • the gates of the other switch groups in the P first type switch groups are the second input terminals of the fixed buffer circuit for inputting the first preset control signal, and the first preset control signal makes the P first type switch groups The first type of switches are in the on state.
  • the gates of the other switch groups in the Q second type switch groups are the third input terminals of the fixed buffer circuit for inputting the second preset control signal.
  • the second preset control signal makes the Q second type switch groups Each second type switch is in an on state.
  • the source of the third switch group in the P first type switch groups can also be connected to the mains power supply, and the source of the fourth switch group in the Q second type switch groups can be grounded.
  • each of the P first type switch groups connected in series includes at least one first type switch connected in parallel.
  • each of the Q second type switch groups connected in series includes at least one second type switch connected in parallel.
  • the number of switches of the first type and the number of switches of the second type included in the fixed buffer circuit may affect the accuracy and range of the clock duty cycle calibration.
  • FIG. 6 is a schematic structural diagram of a fixed buffer circuit provided by an embodiment of the application.
  • the fixed buffer circuit includes two pmos tubes 601 and 602 connected in series, and two nmos tubes 603 and 604 connected in series; among them, the pmos tube 601 is a first type switch group, and the pmos tube 602 is a first
  • the nmos tube 603 is a second-type switch group
  • the nmos tube 604 is a second-type switch group.
  • the gate of the pmos tube 601 is the second input terminal of the fixed buffer circuit for inputting the first preset control signal
  • the gate of the nmos tube 604 is the third input terminal of the fixed buffer circuit for inputting the second preset control signal.
  • the source of the pmos tube 601 is connected to the mains power supply, and the source of the nmos tube 604 is grounded.
  • the pmos tube 601 is the third switch group of the two switch groups of the first type
  • the nmos tube 604 is the fourth switch group of the two switch groups of the second type.
  • the output terminal of the fixed buffer circuit is electrically connected to the calibration module 103, and the output signal is buf_out; the gate of the pmos tube 602 and the gate of the nmos tube 603 are both connected to the crystal
  • the oscillator 101 is electrically connected.
  • the gate of the pmos tube 602 and the gate of the nmos tube 603 are the first input terminal of the fixed buffer circuit, and the original clock xo_out generated by the crystal oscillator 101 is input adjustable through the second input terminal of the adjustable buffer circuit Buffer circuit.
  • the pmos tube 602 is the first switch group in the two sets of first-type switches
  • the nmos tube 603 is the second switch group in the two sets of second-type switches.
  • FIG. 7 is a schematic diagram of another structure of a buffer module provided by an embodiment of the application.
  • the buffer module 102 includes L adjustable buffer circuits and a fixed buffer circuit.
  • the first input of each adjustable buffer circuit is used to receive the buffer circuit control signal xo_dac ⁇ l> sent by the calibration module 103, namely Electrically connected to the calibration module 103;
  • the second input end of each adjustable buffer circuit is used to receive the output signal xo_out of the crystal oscillator 101, that is, the second input end of the adjustable buffer circuit is electrically connected to the crystal oscillator 101;
  • the output terminal of each adjustable buffer circuit is electrically connected to the calibration module 103.
  • One end of each adjustable buffer circuit is connected to the mains power supply, and the other end is grounded.
  • the first input terminal of the fixed buffer circuit is used to receive the output signal xo_out of the crystal oscillator 101, that is, the first input terminal of the fixed buffer circuit is electrically connected to the crystal oscillator 101; the output terminal of the buffer circuit of the fixed buffer circuit is connected to the calibration module 103 is electrically connected; one end of the fixed buffer circuit is connected to the mains power supply, and the other end is grounded.
  • the adjustable buffer circuit 1 may be as shown in FIG. 3
  • the adjustable buffer circuit 2 may be as shown in FIG. 4
  • a fixed buffer circuit may be as shown in FIG. 6.
  • the calibration module 103 includes a phase detection sub-module.
  • the phase detection sub-module is used to output the first alignment result of the delayed rising edge of the first clock and the rising edge of the first clock reversed; and also used to output the second clock The second alignment result of the delayed rising edge and the rising edge of the second clock being reversed.
  • the first alignment result and the second alignment result are used for the generation of the buffer circuit control signal.
  • the first clock is obtained after the clock generated by the crystal oscillator 101 passes through the buffer module 102 at least, and the second clock is obtained after the first clock is reversed.
  • the phase detection sub-module includes but is not limited to the following two forms:
  • the phase detection sub-module includes a first multiplexer, a second multiplexer, a delayer and a phase detector; the output of the first multiplexer and the input of the delayer Electrically connected, the output end of the delayer is also electrically connected to the input end of the phase detector, and the output end of the second multiplexer is electrically connected to the input end of the phase detector.
  • the first channel of the first multiplexer is used to input the first clock, and the first channel of the second multiplexer is used to input the second clock after the first clock is reversed;
  • the second channel of the first multiplexer is used to input the second clock, and the second channel of the second multiplexer is used to input the third clock after the second clock is inverted.
  • the phase detection sub-module includes: a first delayer, a second delayer, a first phase detector and a second phase detector; the output terminal of the first delayer and the first phase detector The input end of the second delayer is electrically connected, and the output end of the second delayer is electrically connected to the input end of the second phase detector.
  • the input end of the first delayer is used to input the first clock
  • the input end of the first phase detector is used to input the first clock delayed by the first delayer and the first clock The second clock after being reversed.
  • the input end of the second delayer is used to input the second clock
  • the input end of the second phase detector is used to input the second clock delayed by the second delayer and the second clock after the second clock is reversed.
  • the calibration module 103 may also include a reverse sub-module which is electrically connected to the phase detection sub-module; the reverse sub-module is used to reverse the first clock so that the phase detection sub-module outputs the first alignment result and is used for Reverse the second clock so that the phase detection sub-module outputs the second alignment result.
  • the inverting sub-module includes a first inverter and a second inverter, and the output terminal of the first inverter is electrically connected to the input terminal of the second inverter; the first inverter and the second inverter are electrically connected.
  • the inverters are all connected with the phase detection sub-module.
  • the input of the first inverter is the first clock mentioned above
  • the output of the first inverter or the input of the second inverter is called the second clock mentioned above
  • the output of the second inverter For the third clock.
  • the calibration module 103 may further include a processor, and the processor is electrically connected to the first input terminal of the adjustable buffer circuit.
  • the processor is configured to output a buffer circuit control signal according to the first alignment result and the second alignment result.
  • the calibration module 103 may include a reverse sub-module, a phase detection sub-module, and a processor that are electrically connected in sequence.
  • the input terminal of the reverse sub-module is electrically connected with the output terminal of the buffer module 102, and the output terminal of the processor is electrically connected with the first input terminal of the adjustable buffer circuit.
  • a specific structure of the calibration module 103 may be as follows: the input end of the first inverter is electrically connected to the input end of the first channel of the first multiplexer, and the first The output terminal of the inverter is also electrically connected to the input terminal of the first channel of the second multiplexer and the input terminal of the second channel of the first multiplexer. The output terminal of the second inverter is electrically connected to the input terminal of the second channel of the second multiplexer. The input terminal of the second channel of the channel selector is electrically connected.
  • the output end of the first multiplexer is electrically connected with the delayer, the delayer is also electrically connected with the input end of the phase detector, and the output end of the second multiplexer is electrically connected with the phase detector.
  • the output end of the phase detector is electrically connected with the processor, and the processor is also electrically connected with the first multiplexer, the second multiplexer and the delayer.
  • FIG. 8 is a schematic structural diagram of a calibration module provided by an embodiment of the application.
  • the calibration module 103 shown in FIG. 8 corresponds to the first form of the phase detection sub-module.
  • the input terminal of the first inverter 801 and the input terminal of the first channel 0 of the first multiplexer 802 and The output end of the buffer module 102 is electrically connected, the output end of the first inverter 801 is electrically connected to the input end of the second inverter 803, and the output end of the first inverter 801 is also connected to the second multiplexer 804
  • the input terminal of the first channel 0 and the input terminal of the second channel 1 of the first multiplexer 802 are electrically connected, and the output terminal of the second inverter 803 is connected to the input of the second channel 1 of the second multiplexer 804 Terminals are electrically connected.
  • the output end of the first multiplexer 802 is electrically connected to the delay 805, the delay 805 is also electrically connected to the input end of the phase detector 806, and the output end of the second multiplexer 804 is electrically connected to the phase detector 806. connection.
  • the output end of the phase detector 806 is electrically connected to the processor 807, and the processor 807 is also connected to the first multiplexer 802, the second multiplexer 804, and the delay 805.
  • another specific structure of the calibration module 103 may be as follows: the input end of the first inverter is electrically connected to one end of the first delayer, and the other end of the first delayer is electrically connected. One end is electrically connected with the input end of the first phase detector.
  • the output terminal of the first inverter is electrically connected to the input terminal of the first phase detector and one end of the second delayer respectively; the output terminal of the second inverter is electrically connected to the input terminal of the second phase detector, and
  • the other end of the second delayer is electrically connected to the second phase detector.
  • the output ends of the first phase detector and the second phase detector are electrically connected with the processor; the processor is also electrically connected with the first delayer and the second delayer.
  • FIG. 9 is a schematic structural diagram of another calibration module provided by an embodiment of the application.
  • the calibration module 103 shown in FIG. 9 corresponds to the second form of the phase detection sub-module.
  • the input end of the first inverter 901 is electrically connected to one end of the first delayer 902, and the first delayer The other end of the 902 is electrically connected to the input end of the first phase detector 903.
  • the output terminal of the first inverter 901 is electrically connected to the input terminal of the second inverter 904, the input terminal of the first phase detector 903, and one end of the second delayer 905; the output of the second inverter 904 The terminal is electrically connected to the input terminal of the second phase detector 906, and the other end of the second delayer 905 is electrically connected to the second phase detector 906.
  • the output ends of the first phase detector 903 and the second phase detector 906 are both electrically connected to the processor 907; the processor 907 is also electrically connected to the first delayer 902 and the second delayer 905.
  • each adjustable buffer circuit and fixed buffer circuit in the buffer module 102 can be directly electrically connected to the calibration module 103, and can also be electrically connected to the calibration module 103 indirectly.
  • the processor in the calibration module 103 is connected to the first input terminal of each adjustable buffer circuit in the buffer module 102.
  • each adjustable buffer circuit and fixed buffer circuit in the buffer module 102 When the output ends of each adjustable buffer circuit and fixed buffer circuit in the buffer module 102 are indirectly electrically connected to the first inverter of the calibration module 103, the output ends of each adjustable buffer circuit and the fixed buffer circuit in the buffer module 102 are indirectly electrically connected to the first inverter of the calibration module 103.
  • the output terminal of the circuit can be electrically connected to the first inverter of the calibration module 103 through the first circuit.
  • the first circuit includes but is not limited to the following forms:
  • the first circuit includes a first buffer, one end of the first buffer is electrically connected to the output end of each adjustable buffer circuit and the fixed buffer circuit in the buffer module 102, and the other end of the first buffer is connected to the calibration
  • the module 103 is electrically connected, for example, to the input terminal of the first inverter of the calibration module 103.
  • the clock duty ratio calibration device can be as shown in FIG. 10.
  • the clock duty ratio calibration device includes a crystal oscillator 101, a buffer module 102, a first buffer 1003 and a calibration module 103.
  • the first circuit includes a capacitor, an inductor, a third inverter, a fourth inverter, and a first buffer.
  • One end of the capacitor is electrically connected to the output end of each adjustable buffer circuit and the output end of the fixed buffer circuit in the buffer module 102, and the other end of the capacitor is electrically connected to one end of the inductor and the input end of the third inverter.
  • the other end and the output end of the third inverter are respectively electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to one end of the first buffer, and the other end of the first buffer is electrically connected to
  • the calibration module 103 is electrically connected, for example, the other end of the first buffer is electrically connected to the input end of the first inverter of the calibration module 103.
  • the clock duty ratio calibration device can be as shown in FIG. 11.
  • the clock duty ratio calibration device includes a crystal oscillator 101, a buffer module 102, a capacitor 1101, an inductor 1103, a third inverter 1102, a fourth inverter 1104, a first buffer 1003 and a calibration module 103.
  • the clock duty ratio calibration device of this embodiment may further include one or more frequency multiplication circuits.
  • the frequency multiplier circuit is electrically connected to the calibration module 103.
  • the frequency multiplication circuit includes: a third delayer and an exclusive OR device XOR that are electrically connected, as shown in FIG. 12 in detail.
  • the input terminal of the frequency multiplier circuit is electrically connected to the output terminal of the second inverter of the calibration module 103, that is, the output terminal of the second inverter and the third delayer and XOR electrical connection.
  • the third delayer is also electrically connected to the processor of the calibration module 103.
  • the frequency multiplier circuit can be directly electrically connected to the calibration module 103 or indirectly electrically connected to the calibration module 103.
  • the calibration module 103 can be electrically connected to the input terminal of the second buffer (for example, the output terminal of the second inverter of the calibration module 103 and the input terminal of the second buffer Electrically connected), the second buffer is electrically connected to the frequency multiplier circuit (the output end of the second buffer is electrically connected to the third delayer and the XOR).
  • the corresponding clock duty ratio calibration device may be as shown in FIG. 13.
  • the clock duty cycle calibration device includes a crystal oscillator 101, a buffer module 102, a capacitor 1101, an inductor 1103, a third inverter 1102, a fourth inverter 1104, a first buffer 1003, a calibration module 103,
  • the frequency multiplication circuit 1302 may include one or more, and the case of multiple frequency multiplication circuits 1302 is not shown in the figure.
  • the clock duty ratio calibration device of this embodiment may further include a third multiplexer.
  • the first channel of the third multiplexer is electrically connected to the output end of the frequency multiplier circuit, and the second channel of the third multiplexer is electrically connected to the calibration module 103.
  • the second channel of the third multiplexer is directly or indirectly electrically connected to the calibration module 103.
  • the calibration module 103 can be electrically connected to the second buffer, the second buffer is electrically connected to the frequency multiplier circuit, and the second buffer is also electrically connected to the first The second channel connection of the three multiplexers.
  • the corresponding clock duty ratio calibration device when the second channel of the third multiplexer is indirectly electrically connected to the calibration module 103 may be as shown in FIG. 14.
  • the clock duty cycle calibration device includes a crystal oscillator 101, a buffer module 102, a capacitor 1101, an inductor 1103, a third inverter 1102, a fourth inverter 1104, a first buffer 1003, a calibration module 103,
  • the frequency multiplication circuit 1302 may include one or more, and the case of multiple frequency multiplication circuits 1302 is not shown in the figure.
  • the clock duty ratio calibration device has been described above, and the method for calibrating the clock duty ratio based on the above clock duty ratio calibration device will be described below.
  • the first inverter of the calibration module 103 inputs the first clock, and the first clock is obtained after the clock generated by the crystal oscillator 101 passes through the buffer module 102 at least.
  • the first clock is obtained by sequentially passing the clock generated by the crystal oscillator 101 through the buffer module 102 and the first buffer.
  • the clock duty cycle calibration device is shown in Figure 11, the first clock is the clock generated by the crystal oscillator 101 after passing through the buffer module 102, the capacitor, the third inverter, the fourth inverter, and the first buffer in sequence. owned. It is understandable that the duty ratio of the clock generated by the crystal oscillator 101 may change after passing through the buffer module 102, and the duty ratio will not change after passing through electrical components such as capacitors, inverters, and buffers.
  • the second clock is obtained.
  • the second clock is the output of the first inverter and the input of the second inverter; the second clock passes through the second inverter to obtain the third clock.
  • the third clock is the output of the second inverter and the output of the second inverter. It can be understood that the duty ratios of the first clock, the second clock, and the third clock are the same. Since the third clock is the final output clock, or the third clock is the final output through the frequency multiplier circuit, therefore, when the duty cycle of the first clock, the second clock, or the third clock is the preset duty cycle , It can be considered that a clock with a preset duty cycle is obtained.
  • Figure a in Figure 15 is the waveform of the first clock P1
  • Figure b is the waveform of the second clock P2 after the first clock is reversed
  • Figure c is the third clock P3 after the second clock is reversed. ⁇ waveform.
  • the delayer that appears later is the delayer in the calibration module.
  • MUX1 0 + Delay1 INV1 + MUX2 0 + T1(1), where MUX1 0 is The first clock is the delay generated by the first channel of the first multiplexer, Delay1 is the delay 1 of the delayer, and INV1 is the delay generated by the first clock to obtain the second clock through the first inverter, MUX2 0 is the time delay generated by the second clock through the first channel of the second multiplexer, and T1 is the high level time of the first clock or the second clock.
  • MUX1 1 + Delay2 INV2 + MUX2 1 + T2(2), where MUX1 1 is The second clock is the delay generated by the second channel of the first multiplexer, Delay2 is the delay 2 of the delayer, and INV2 is the delay generated by the third clock from the second clock through the second inverter, MUX2 1 is the time delay generated by the second clock through the second channel of the second multiplexer, and T2 is the low level time of the second clock or the third clock.
  • the performance of the first inverter and the second inverter are roughly the same.
  • the duty cycle of the calibration time of 0.5 is converted into obtaining the first delay of the delay.
  • the rising edge of the first clock is delayed by the first delay and can be aligned with the rising edge of the second clock to obtain the delay
  • the second delay, the rising edge of the second clock is delayed and the second delay can be aligned with the rising edge of the third clock. If the first delay and the second delay are equal, the first clock and the second clock ,
  • the duty cycle of the third clock is the preset duty cycle 0.5.
  • the first multiplexer is electrically connected to the delayer
  • the second multiplexer and the delayer are electrically connected to the phase detector
  • the input terminal of the first inverter is electrically connected to the first multiplexer.
  • the first channel is connected, and the input terminal of the first inverter is the first clock, that is, the first clock is sequentially input to the phase detector after passing through the first channel of the first multiplexer and the delayer;
  • the second inverter The input end of the divider is connected to the first channel of the second multiplexer, and the input end of the second inverter is the second clock, that is, the second clock is input to the first channel of the second multiplexer Phase detector.
  • the processor controls the first channel of the first multiplexer and the first channel of the second multiplexer to be turned on, so that the first clock passes through the first multiplexer in turn.
  • the first channel of the selector and the delayer are delayed and input to the phase detector, and the second clock is input to the phase detector after passing through the first channel of the second multiplexer.
  • the phase detector detects the rising edge of the first clock after passing through the first channel of the first multiplexer, the rising edge of the delayer delaying the current delay, and the rising edge of the second clock after passing through the first channel of the second multiplexer.
  • the alignment state of the edge can also be said to be judging the alignment state of the rising edge of the first clock with the rising edge of the second clock after the current delay is delayed by the delayer, so as to output the alignment result of the first route to the processor.
  • the first alignment result indicates the alignment status
  • the alignment status includes but is not limited to any of the following: the rising edge of the two clocks is aligned, and the rising edge of the A clock of the two clocks is ahead of the B clock.
  • the lag time when the rising edge of the A clock of the two clocks lags behind the rising edge of the B clock both indicate that the rising edge of the first clock is not aligned with the rising edge of the second clock after being delayed by the delayer for the current time delay.
  • the processor determines that the rising edge of the first clock is not aligned with the rising edge of the second clock after being delayed by the delayer according to the alignment result of the first route, it sends the first type of delay control according to the alignment result of the first route Signal to the delayer to update the delay of the delayer. That is, the processor determines whether the delay of the delayer should be increased or decreased and the adjustment amount according to the alignment result of the first path, and sends the first type of delay control signal to the delayer to update the delay of the delayer.
  • the first type of delay control signal indicates the adjustment delay of the delayer, and the delay of the delayer includes a fixed delay and an adjusted delay.
  • the processor determines that the rising edge of the first clock is delayed by the delayer and is aligned with the rising edge of the second clock according to the alignment result of the first path, the processor determines that the current delay of the delayer is the first of the delayer. Time delay.
  • the delayer After the delayer receives the first-type delay control signal, it updates the delay according to the first-type delay control signal. At this time, the first clock passes through the first channel of the first multiplexer and the delayer delays the new delay. After the delay is input to the phase detector, the phase detector detects that the first clock passes through the first channel of the first multiplexer in turn, the delayer delays the rising edge of the new time delay and the second clock passes through the first channel.
  • the alignment state of the rising edge after the first channel of the second multiplexer can also be said to be judging the alignment state of the rising edge of the first clock with the rising edge of the second clock after a new delay by the delayer. To output the new first alignment result to the processor.
  • the processor determines that the rising edge of the first clock is delayed by the delayer and is not aligned with the rising edge of the second clock according to the new alignment result of the first route, and then sends a new one according to the new alignment result of the first route.
  • the first type of delay control signal is sent to the delayer to update the delay of the delayer again. If the processor determines that the rising edge of the first clock is delayed by the delayer and is aligned with the rising edge of the second clock according to the new alignment result of the first route, the processor determines that the new delay of the delayer is a delayer The first time delay.
  • the processor determines that the rising edge of the first clock is delayed by the delayer and then aligns with the rising edge of the second clock according to the received alignment result of the first route.
  • the delay of the delayer is the delay. The first delay of the timer.
  • the first multiplexer is electrically connected to the delayer
  • the second multiplexer and the delayer are electrically connected to the phase detector
  • the input end of the second inverter is electrically connected to the first multiplexer.
  • the second channel is connected, and the input of the second inverter is the second clock, that is, the second clock is input to the phase detector after passing through the second channel of the second multiplexer and the delayer in turn; the second inverter
  • the output of the divider is connected to the second channel of the second multiplexer, and the output of the second inverter is the third clock, that is, the third clock is input to the second channel of the second multiplexer Phase detector.
  • the processor controls the second channel of the first multiplexer and the second channel of the second multiplexer to be turned on, so that the second clock sequentially passes through the first multiplexer.
  • the second channel of the selector and the delayer are delayed and input to the phase detector, and the second clock is input to the phase detector after passing through the second channel of the second multiplexer.
  • the phase detector detects the rise of the second clock after passing through the second channel of the first multiplexer, the rising edge of the delayer delaying the current delay, and the rising edge of the third clock after passing through the second channel of the second multiplexer
  • the alignment state of the edge can also be said to be judging the alignment state of the rising edge of the second clock with the rising edge of the third clock after the current delay is delayed by the delayer, so as to output the second alignment result to the processor.
  • the second alignment result indicates the alignment state, and the meaning of the alignment state is the same as that described above, and will not be repeated here.
  • the second type of delay control is sent according to the alignment result of the second Signal to the delayer to update the delay of the delayer. That is, the processor determines whether the delay of the delayer should be increased or decreased and the amount of adjustment according to the second alignment result, and sends the second type of delay control signal to the delayer to update the delay of the delayer.
  • the second type of delay control signal indicates the adjustment delay of the delayer, and the delay of the delayer includes a fixed delay and an adjusted delay. If the processor determines according to the second alignment result that the rising edge of the second clock is delayed by the delayer and is aligned with the rising edge of the third clock, the processor determines that the current delay of the delayer is the delayer The second delay.
  • the delayer After the delayer receives the second-type delay control signal, it updates the delay according to the second-type delay control signal. At this time, the second clock passes through the second channel of the first multiplexer and the delayer delays the new delay. After the delay is input to the phase detector, the phase detector detects that the second clock passes through the second channel of the first multiplexer in turn, the delayer delays the rising edge of the new time delay and the third clock passes through the first The alignment state of the rising edge after the second channel of the second multiplexer can also be said to be judging the alignment state of the rising edge of the second clock with the rising edge of the third clock after a new delay by the delayer. To output the new second alignment result to the processor.
  • the processor determines that the rising edge of the second clock is not aligned with the rising edge of the third clock after being delayed by the delayer according to the new second alignment result, it will send a new one according to the new second alignment result.
  • the second type of delay control signal is sent to the delayer to update the delay of the delayer again. If the processor determines that the rising edge of the second clock is delayed by the delayer and is aligned with the rising edge of the third clock according to the second alignment result, the processor determines that the new delay of the delayer is the first delay of the delayer. Two time delay.
  • the processor determines according to the received second alignment result that the rising edge of the second clock is delayed by the delayer and then aligned with the rising edge of the third clock.
  • the delay of the delayer is the delay.
  • the second delay of the timer is the delay.
  • the first clock, the second clock, and the third The duty cycle of the clock is the preset duty cycle 0.5, that is, the clock calibration is completed.
  • the processing method in the case where the first time delay and the second time delay of the delayer are not equal will be described below.
  • the processor determines that the first delay of the delayer and the second delay of the delayer are not the same, it means that the duty cycle of the clock generated by the crystal oscillator 101 after passing through the buffer module 102 is not the preset duty cycle 0.5, that is, the low-level time and the high-level time are not the same. Therefore, the processor sends a buffer circuit control signal to the adjustable buffer circuit of the buffer module 102 to adjust the number of the first type of switch and the second type of switch that are in the on state in the adjustable buffer circuit to obtain the updated first clock, The second clock and the third clock. The duty ratios of the updated first clock, second clock, and third clock are also updated.
  • the number of the first type of switches and the number of the second type of switches in the buffer module 102 that are in the on state affect the duty cycle of the clock generated by the crystal oscillator 101 after passing through the buffer module 102.
  • the first type of switches is When the pmos tube and the second type of switch are nmos tubes, the larger the number of nmos tubes, the smaller the duty cycle of the clock generated by the crystal oscillator 101 after passing through the buffer module 102.
  • the size of the first delay of the delayer and the second delay of the delayer can reflect the length of the low-level time and the high-level time, that is, it can reflect the deviation of the duty cycle relative to the preset duty cycle. High or low.
  • the processor determines the clock generated by the crystal oscillator 101 after the current buffer module 102 (such as the first clock, the second clock, and the third clock) according to the first delay and the second delay of the delayer. If the duty cycle of) is too small, the generated buffer circuit control signal should be a buffer control signal that can increase the number of pmos tubes in the on state. Therefore, when the processor determines, according to the first delay of the delayer and the second delay of the delayer, that the duty cycle of the clock generated by the crystal oscillator 101 after passing through the current buffer module 102 is too large, then The generated buffer circuit control signal should be a buffer control signal that can increase the number of nmos tubes in the on state.
  • the processor can control the number of switches of the first type and the number of switches of the second type in the open state in the buffer module 102 by inputting the first buffer circuit control signal or the second buffer circuit control signal to each adjustable buffer circuit.
  • the current first adjustable buffer circuit inputs the first buffer circuit control signal
  • the current second adjustable buffer circuit inputs the first buffer circuit control signal
  • the current third adjustable buffer circuit inputs the second buffer circuit control signal
  • the current fourth adjustable buffer circuit inputs the second buffer circuit control signal
  • the pmos tubes of the first and second adjustable buffer circuits are all turned on Status
  • the nmos tubes of the third and fourth adjustable buffer circuits are all in the on state.
  • the adjustable buffer circuit sends the first buffer circuit control signal, the second buffer circuit control signal to the second adjustable buffer circuit, the second buffer circuit control signal to the third adjustable buffer circuit, and the fourth adjustable buffer circuit
  • the circuit sends a second buffer circuit control signal to increase the number of nmos tubes in the on state.
  • the processor determines that the duty cycle of the clock generated by the crystal oscillator 101 after passing the current buffer module 102 is too small, then it can be adjusted to the first one.
  • the buffer circuit sends the first buffer circuit control signal, sends the first buffer circuit control signal to the second adjustable buffer circuit, sends the first buffer circuit control signal to the third adjustable buffer circuit, and sends the fourth adjustable buffer circuit Send the second buffer circuit control signal to increase the number of pmos tubes in the open state; or, the number of pmos tubes in the third adjustable buffer circuit is greater than the number of pmos tubes in the second adjustable buffer circuit, and the processor According to the first time delay of the delayer and the second time delay of the delayer, if it is determined that the duty cycle of the clock generated by the crystal oscillator 101 after passing through the current buffer module 102 is too small, you can go to item 1
  • the adjustable buffer circuit sends the first buffer circuit control signal, the second buffer circuit control signal to the second adjustable buffer circuit, the first buffer circuit control signal to the third adjustable buffer circuit, and the fourth adjustable buffer The circuit sends a second buffer circuit control signal to increase the number of pmos tubes in the open state.
  • the buffer module 102 is updated, and the clock generated by the crystal oscillator 101 is occupied by the clock after the new buffer module 102
  • the empty ratio is also updated, that is, the updated first clock, the updated second clock, and the updated third clock are obtained.
  • the method of obtaining the first delay and the second delay of the delayer according to the first clock, the second clock, and the third clock is adopted, and the updated first clock, the updated second clock, and the updated third clock are used according to the method of obtaining the first delay and the second delay of the delayer.
  • the clock acquires the new first delay and the new second delay of the delayer, until the first delay and the second delay of the obtained delayer are the same, that is, the clock generated by the crystal oscillator 101 is passed through the buffer module 102
  • the duty cycle of the subsequent clock (that is, the output clock) is adjusted to a preset duty cycle of 0.5.
  • the duty cycle of the calibration time can be converted to 0.5 to obtain the third delay of the delayer, and the falling edge of the first clock is delayed.
  • the third time delay can be aligned with the rising edge of the second clock
  • the fourth time delay of the delayer is obtained, and the falling edge of the second clock is delayed by the second time delay and can be aligned with the falling edge of the third clock. If the third time delay and the fourth time delay are equal, the duty ratios of the first clock, the second clock, and the third clock are the preset duty ratios of 0.5.
  • the method of acquiring the third delay of the delayer and the method of acquiring the fourth delay of the delayer is similar to the method of acquiring the first delay of the delayer and the method of acquiring the second delay of the delayer, and will not be repeated here. .
  • the output clock can be directly output to generate a reference clock for the service.
  • the output clock can also change the frequency and/or duty cycle through the frequency multiplier circuit to obtain a new clock.
  • the processor sends the first delay control signal and the second delay control signal to the delayer of the frequency multiplication circuit, the first delay control signal is used to indicate the second fixed delay, and the first delay control signal is used to indicate the second fixed delay.
  • the second fixed delay is 1/N times the first fixed delay
  • the second delay second control signal is used to instruct the second adjustment delay
  • the second adjustment delay is 1/N times the first adjustment delay
  • the sum of the first fixed delay and the first adjusted delay is the delay of the calibration module 103 when the duty cycle of the clock generated by the crystal oscillator 101 is adjusted to the preset duty cycle of 0.5 after the buffer module 102 is adjusted.
  • the delay of the timer is the delay of the timer.
  • the delay of the delayer of the frequency multiplier circuit is the sum of the second fixed delay and the second adjusted delay
  • the clock output by the frequency multiplier circuit is the target clock with a duty ratio of 1/N
  • the frequency of the target clock It is twice the input clock of the frequency multiplier circuit.
  • the input clock of the frequency multiplier circuit is the third clock or the clock after the third clock passes through the second buffer.
  • the processor sends the first delay control signal and the second delay control signal to the delayer of the frequency multiplication circuit, and the first delay control signal is used to indicate the first fixed delay, The second delay control signal is used to indicate the first adjustment delay.
  • the sum of the first fixed delay and the first adjustment delay is the duty cycle of the clock generated by the crystal oscillator 101 after the buffer module 102 is adjusted to The time delay of the delayer of the calibration module 103 corresponding to the preset duty ratio of 0.5.
  • the delayer of the frequency multiplier circuit obtains 1/N times the first adjustment delay and 1/N times the first fixed delay, 1/N times the first adjustment delay and 1/N times the first fixed time
  • the sum of the delays is the delay of the delayer of the frequency multiplier circuit.
  • the clock output by the frequency multiplier circuit is a target clock with a duty ratio of 1/N, and the frequency of the target clock is twice the input clock of the frequency multiplier circuit.
  • the input clock of the frequency multiplier circuit is the third clock or the clock after the third clock passes through the second buffer.
  • the processor sends the first time delay control signal and the second time delay control signal to the delayer of each frequency multiplier circuit in the P frequency multiplier circuits connected in series, and the first time delay
  • the delay control signal is used to indicate the first fixed delay
  • the second delay control signal is used to indicate the first adjusted delay.
  • the sum of the first fixed delay and the first adjusted delay is the buffered clock generated by the crystal oscillator 101 When the duty cycle of the clock after the module 102 is adjusted to a preset duty cycle of 0.5, the delay of the delayer of the calibration module 103 corresponding to the time delay.
  • P octave circuits the p-th p 1/2 times frequency multiplier circuit acquiring a first fixed delay, 1/2 p times the first delay adjustment, so that the p-th octave circuits P frequency multiplier circuit delay times of 1/2 p 1/2 p with a first fixed delay times of the delay and the first adjustment.
  • the p-th multiplier circuit in the P multiplying circuits outputs a target clock with a duty ratio of 0.5, and the frequency of the target clock is 2 p of the input clock of the first multiplying circuit of the P multiplying circuits.
  • the input clock of the first frequency multiplier circuit in the P multiplier circuits is the third clock or the clock after the third clock passes through the second buffer.
  • the buffer module of the clock duty cycle calibration device in this solution includes an adjustable buffer circuit.
  • the number of the first type of switch and the second type of switch in the adjustable buffer circuit in the open state can affect the clock duty cycle, and the calibration module
  • the buffer circuit control signal can be sent to adjust the number of the first type of switch and the second type of switch in the open state in the adjustable buffer circuit. Therefore, the device of this embodiment can adjust the number of the first type of switch and the second type of switch in the open state in the buffer module.
  • the number of switches of the second type accurately calibrates the duty cycle of the clock to a preset duty cycle of 0.5. It is simple and easy to implement, and the calibration efficiency is high.

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Abstract

本申请实施例提供一种时钟占空比校准装置，该装置包括：依次电连接的晶体振荡器、缓冲模块、校准模块；其中，该缓冲模块包括可调缓冲电路；该可调缓冲电路的第一输入端与该校准模块电连接，该可调缓冲电路的第二输入端与该晶体振荡器电连接，该可调缓冲电路的输出端与该校准模块电连接；该缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量与时钟的占空比相关；该校准模块用于向该可调缓冲电路的第一输入端发送缓冲电路控制信号，该缓冲电路控制信号用于控制该缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量。本申请实施例可以准确的将时钟的占空比校准至预设占空比。

Description

时钟占空比的校准装置 技术领域
本申请实施例涉及通信系统，尤其涉及一种时钟占空比校准装置。
背景技术
随着通信系统对信号噪声的要求越来越高，晶体振荡器作为参考时钟来源，对其噪声、振荡频率的要求也随之提高。晶体振荡器的振荡频率越高，所需成本越高。因此，通常对晶体振荡电路输出的时钟采用倍频的方式得到参考时钟，以提高参考时钟的频率。其中，晶体振荡模块为包括晶体振荡器的时钟产生装置。
若晶体振荡电路输出的时钟的占空比偏离50％，则晶体振荡电路输出的时钟经倍频后得到的参考时钟会出现杂散，进而影响使用参考时钟的业务的正常进行，因此，对晶体振荡电路块输出的时钟的占空比进行校准，具有重要的意义。
发明内容
本申请实施例提供一种时钟占空比校准装置，可以准确的将时钟的占空比校准至预设占空比。
第一方面，本申请实施例提供一种时钟占空比校准装置，包括：依次电连接的晶体振荡器、缓冲模块、校准模块；其中，所述缓冲模块包括可调缓冲电路；所述可调缓冲电路的第一输入端与所述校准模块电连接，所述可调缓冲电路的第二输入端与所述晶体振荡器电连接，所述可调缓冲电路的输出端与所述校准模块电连接；所述缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量与时钟的占空比相关；所述校准模块用于向所述可调缓冲电路的第一输入端发送缓冲电路控制信号，所述缓冲电路控制信号用于控制所述缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量。可选地，所述第一类开关为P型MOS管，所述第二类开关为N型MOS管。
本方案中的时钟占空比校准装置的缓冲模块包括可调缓冲电路，可调缓冲电路中处于开启状态的第一类开关的数量和第二类开关的数量可以影响时钟的占空比，而校准模块能够发送缓冲电路控制信号以调节缓冲模块中处于开启状态的第一类开关和第二类开关的数量，因此本实施例的装置可以通过调整缓冲模块中处于开启状态的第一类开关和第二类开关的数量，实现时钟的占空比的校准，且校准结果准确。
在一种可能的实施方式中，所述缓冲模块还包括固定缓冲电路，所述固定缓冲电路中处于开启状态的第一类开关的数量为第一固定数量以及处于开启状态的第二类开关的数量为第二固定数量；所述固定缓冲电路的第一输入端与所述晶体振荡器电连接，所述固定缓冲电路的输出端与所述校准模块电连接。
本方案中固定缓冲电路的设置可使得缓冲模块中同时存在处于开启状态的第一类开关和第二类开关，以保证缓冲模块的正常工作。此外，还可通过调整固定缓冲电路包括的第 一类开关的数量和第二类开关的数量调整时钟占空比校准的精度。
在一种可能的实施方式中，所述可调缓冲电路包括N个串联连接的第一类开关组和M个串联连接的第二类开关组，所述N个第一类开关组中的第一开关组的漏极与所述M个第二类开关组中的第二开关组的漏极电连接后与校准模块电连接；第一开关组的栅极和第二开关组的栅极电连接后与所述晶体振荡器电连接；所述N和M均为大于等于2的整数；所述N个第一类开关组中的其它开关组的栅极与所述M个第二类开关组中的其它开关组的栅极均与所述校准模块电连接。
本方案中的可调缓冲电路简单易实现。且可以实现同一条可调缓冲电路只有一种开关处于开启状态，使得整个缓冲模块中第一类开关的数量和第二类开关的数量较易控制，从而调节时钟的占空比比较高效。
在一种可能的实施方式中，所述校准模块包括相位检测子模块，所述相位检测子模块用于输出所述时钟被延时后的上升沿与所述时钟被反向后的上升沿的对齐结果，所述对齐结果用于所述缓冲电路控制信号的生成。
其中，在所述时钟为第一时钟时，所述相位检测子模块用于输出所述第一时钟被延时后的上升沿与所述时钟被反向后第二时钟的上升沿的第一对齐结果；在所述时钟为第二时钟时，所述相位检测子模块用于输出所述第二时钟被延时后的上升沿与所述第二时钟被反向后第三时钟的上升沿的第二对齐结果。所述第一对齐结果和第二对齐结果共同用于所述缓冲电路控制信号的生成。
本方案提供的校准模块相位检测子模块可以输出时钟被延时后的上升沿与时钟被反向后的上升沿的对齐结果，获取该对齐结果的过程涉及时钟的低电平时间或高电平时间，从而可以使得校准模块实现判断时钟当前的占空比是否为预设占空比的目的。
在一种可能的实施方式中，所述相位检测子模块包括第一多路选择器、第二多路选择器、延时器和相位检测器；所述第一多路选择器的输出端与所述延时器的输入端电连接，所述延时器的输出端还所述相位检测器的输入端电连接，所述第二多路选择器的输出端与所述相位检测器的输入端电连接。其中，所述第一多路选择器的第一通道用于输入第一时钟，所述第二多路选择器的第一通道用于输入所述第一时钟被反向后的第二时钟；所述第一多路选择器的第二通道用于输入所述第二时钟，所述第二多路选择器的第二通道用于输入所述第二反向时钟被反向后的第三时钟。
本方案的相位检测子模块可以减少延时器和相位检测器的数量，降低了相位检测子模块的复杂度。
在一种可能的实施方式中，所述相位检测子模块包括：第一延时器、第二延时器、第一相位检测器和第二相位检测器；所述第一延时器的输出端与所述第一相位检测器的输入端电连接，所述第二延时器的输出端与所述第二相位检测器的输入端电连接。所述第一延时器的输入端用于输入第一时钟，所述第一相位检测器的输入端用于输入第一时钟被所述第一延时器延时后的时钟和所述时钟被反向后的第二时钟；所述第二延时器的输入端用于输入所述第二时钟，所述第二相位检测器的输入端用于输入所述第二时钟被所述第二延时器延时后的时钟和所述第二反向时钟被反向后的第三时钟。
本方案的相位检测子模块可以提高校准时钟占空比的效率。
在一种可能的实施方式中，所述校准模块还包括反向子模块，所述反向子模块与所述 相位检测子模块电连接；所述反向子模块用于对所述时钟进行反向以使所述相位检测子模块输出所述对齐结果。
本方案提供的反向子模块可以输出反向的时钟，从而实现和相位检测子模块、处理器一起实现判断时钟当前的占空比是否为预设占空比的目的。
在一种可能的实施方式中，所述反向子模块包括第一反向器和第二反向器，所述第一反向器的输出端与所述第二反向器的输入端电连接；所述第一反向器和所述第二反向器均与所述相位检测子模块连接。
本方案提供的反向子模块简单易实现。
在一种可能的实施方式中，所述校准模块包括处理器，所述处理器与所述可调缓冲电路的第一输入端电连接；所述处理器用于根据所述时钟被延时后的上升沿与所述时钟被反向后的上升沿的对齐结果输出所述缓冲电路控制信号。
本方案实现了缓冲电路控制信号的输出，即实现了校准时钟占空比的目的。
在一种可能的实施方式中，还包括倍频电路；所述倍频电路与所述校准模块电连接。
本方案中倍频电路的设置可以实现得到不同占空比和/或不同频率的时钟。
第二方面，本申请实施例提供一种时钟占空比校准方法，该方法基于上述的时钟占空比校准装置，该方法包括：获取第一时钟所对应的第一时延，所述第一时钟的上升沿被校准模块的第一延时器延时所述第一时延后能够与所述第二时钟的上升沿对齐；所述第二时钟是所述第一时钟经奇数次反向后得到的；获取所述第二时钟所对应的第二时延，所述第二时钟的上升沿被校准模块的第二延时器延时所述第二时延后能够与所述第三时钟的上升沿对齐，所述第三时钟是所述第二时钟经奇数次反向后得到的；根据所述第一时延和所述第二时延，校准所述第一时钟的占空比。第一延时器和第二延时器可为同一个延时器，还可为不同的延时器。第一时钟所对应的第一时延可称为第一延时器的第一时延，第二时钟所对应的第二时延可称为第二延时器的第二时延。
所述第一时钟是晶体振荡器产生的原始时钟至少经缓冲模块后得到的，所述缓冲模块包括可调缓冲电路；所述根据所述第一时延和所述第二时延，校准所述第一时钟的占空比，包括：若所述第一时延和所述第二时延不相同，则发送缓冲电路控制信号至所述可调缓冲电路，以调节所述可调缓冲电路中处于开启状态的第一类开关的数量和第二类开关的数量，得到被更新的所述第一时钟、所述第二时钟和所述第三时钟；返回获取所述第一时钟所对应的第一时延、所述第二时钟所对应的第二时延的操作，直至所述第一时钟所对应的第一时延与所述第二时钟所对应的第二时延相同，确定所述第一时钟的占空比被校准至预设占空比。
在一种可能的实施方式中，所述获取第一时钟所对应的第一时延，包括：接收来自第一相位检测器的第一对齐结果，所述第一对齐结果指示所述第一时钟的上升沿被第一延时器延时后与所述第二时钟的上升沿对齐；所述第一延时器的输出端与所述第一相位检测器连接；确定与所述第一对齐结果对应的所述第一延时器的时延为所述第一时钟所对应的第一时延。
在一种可能的实施方式中，所述从第一相位检测器接收所述第一对齐结果，包括：接收来自所述第一相位检测器的第一路对齐结果，若所述第一路对齐结果指示第一时钟的上升沿被所述第一延时器延时后与所述第二时钟的上升沿未对齐，则根据所述第一路对齐结 果发送第一类时延控制信号至所述延时器，以更新所述第一延时器的时延；返回从所述第一相位检测器接收第一路对齐结果的步骤，直至接收到所述第一对齐结果。
在一种可能的实施方式中，接收来自第二相位检测器的第二对齐结果，所述第二对齐结果指示所述第二时钟的上升沿被第二延时器延时后与所述第三时钟的上升沿对齐；所述第二延时器的输出端与所述第二相位检测器连接；确定与所述第二对齐结果对应的所述第二延时器的时延为所述第二时钟所对应的第二时延。
在一种可能的实施方式中，所述从第二相位检测器接收所述第二对齐结果，包括：从所述第二相位检测器接收第二路对齐结果，若所述第二路对齐结果指示所述第二时钟的上升沿被所述第二延时器延时后与所述第三时钟的上升沿未对齐，则根据所述第二路对齐结果发送第二类时延控制信号至所述第二延时器，以更新所述第二延时器的时延；返回从所述第二相位检测器接收第二路对齐结果的步骤，直至接收到所述第二对齐结果。
其中，所述第一相位检测器和所述第二相位检测器可为同一个相位检测器，还可为不同的相位检测器。
在一种可能的实施方式中，根据所述第一时延和所述第二时延，校准所述第一时钟的占空比，包括：若所述第一时延和所述第二时延相同，则确定所述第一时钟的占空比被校准至预设占空比。
在一种可能的实施方式中，所述方法还包括：发送第一时延控制信号和第二时延控制信号，至所述倍频电路的延时器，以使所述倍频电路输出占空比为1/N的目标时钟；所述第一时延控制信号用于指示第二固定时延，所述第二固定时延为第一固定时延的1/N倍，所述第二时延第二控制信号用于指示第二调节时延，所述第二调节时延为所述第一调节时延的1/N倍，所述第一固定时延与所述第一调节时延之和为所述第一时钟的占空比被校准至预设占空比时第一延时器或第二延时器的时延；所述倍频电路的延时器的时延为所述第二固定时延与所述第二调节时延之和；所述目标时钟的频率为所述倍频电路的输入时钟的两倍。
在一种可能的实施方式中，所述方法还包括：发送第一时延控制信号和第二时延控制信号，至所述倍频电路的延时器，以使所述倍频电路输出占空比为1/N的目标时钟；所述第一时延控制信号用于指示第一固定时延，所述第二时延控制信号用于指示第一调节时延，所述第一固定时延与所述第一调节时延之和为所述第一时钟的占空比被校准至预设占空比时第一延时器或第二延时器的时延；所述倍频电路的延时器的固定时延为所述第一固定时延的1/N倍，所述倍频电路的延时器的调节时延为所述第一调节时延的1/N倍；所述目标时钟的频率为所述倍频电路的输入时钟的两倍。
在一种可能的实施方式中，所述方法还包括：发送第一时延控制信号和第二时延控制信号至依次串联连接的P个倍频电路中每个倍频电路的延时器，以使所述P个倍频电路中的第p个倍频电路输出占空比为1/2的目标时钟，所述第一时延控制信号用于指示第一固定时延，所述第二时延控制信号用于指示第一调节时延，所述第一固定时延与所述第一调节时延之和为所述第一时钟的占空比被校准至预设占空比时第一延时器或第二延时器的时延；所述目标时钟的频率为所述P个倍频电路中的第1个倍频电路的输入时钟的2 p倍，所述第p个倍频电路的延时器的固定时延为所述第一固定时延的1/2 p倍、调节时延为所述第一调节时延的1/2 p倍。
本方案中的时钟占空比校准装置的缓冲模块包括可调缓冲电路，可调缓冲电路中处于开启状态的第一类开关和第二类开关的数量可以影响时钟的占空比，而校准模块能够发送缓冲电路控制信号以调节可调缓冲电路中处于开启状态的第一类开关和第二类开关的数量，因此本实施例的装置可以通过调整缓冲模块中处于开启状态的第一类开关和第二类开关的数量，准确的将时钟的占空比校准至预设占空比。
附图说明
图1为本申请实施例提供的时钟占空比校准装置的一种结构示意图；
图2为本申请实施例提供的一组第一类开关的结构示意图；
图3为本申请实施例提供的一条可调缓冲电路的一种结构示意图；
图4为本申请实施例提供的一条可调缓冲电路的另一种结构示意图；
图5为本申请实施例提供的缓冲模块的一种示意图；
图6为本申请实施例提供的一条固定缓冲电路的一种结构示意图；
图7为本申请实施例提供的缓冲模块的另一种结构示意图；
图8为本申请实施例提供的一种校准模块的结构示意图；
图9为本申请实施例提供的另一种校准模块的结构示意图；
图10为本申请实施例提供的时钟占空比校准装置的另一种结构示意图；
图11为本申请实施例提供的时钟占空比校准装置的又一种结构示意图；
图12为为本申请实施例提供的倍频电路的结构示意图；
图13为本申请实施例提供的时钟占空比校准装置的又一种结构示意图；
图14为本申请实施例提供的时钟占空比校准装置的又一种结构示意图；
图15为本申请实施例提供的时钟波形示意图；
图16为本申请实施例提供的时钟上升沿对齐示意图一；
图17为本申请实施例提供的时钟上升沿对齐示意图二。
具体实施方式
为了更好的理解本申请，本申请引入如下要素。
占空比：占空比是指有效电平在一个周期之内所占的时间比率。方波的标准占空比为50％或0.5，说明正电平所占时间为0.5个周期，负电平所占时间为0.5个周期。
由于晶体振荡电路输出波形为方波的时钟时，该时钟的占空比可能不为0.5，此时对该时钟进行倍频后得到的参考时钟会出现杂散，进而影响使用参考时钟的业务的正常进行，因此，将晶体振荡电路块输出的波形为方波的时钟的占空比校准至0.5，具有重要的意义。本申请实施例提供了一种将将晶体振荡电路块输出的波形为方波的时钟的占空比校准至0.5的时钟占空比校准装置和基于该装置的时钟占空比校准方法。
下面采用具体的实施对本申请实施例提出的时钟占空比校准装置进行说明。
图1为本申请实施例提供的时钟占空比校准装置的一种结构示意图，参见图1，本实施例的时钟占空比校准装置包括：晶体振荡器101、缓冲模块102、校准模块103。
其中，缓冲模块102包括可调缓冲电路，可调缓冲电路包括第一类开关和第二类开关。 缓冲模块102中处于开启状态的第一类开关的数量和第二类开关的数量与时钟的占空比相关。
可调缓冲电路的第一输入端与校准模块103电连接，可调缓冲电路的第二输入端与晶体振荡器101电连接，可调缓冲电路的输出端与校准模块103电连接。
校准模块103用于向可调缓冲电路的第一输入端发送缓冲电路控制信号，缓冲电路控制信号用于控制缓冲模块102中处于开启状态的第一类开关的数量和第二类开关的数量。
下面分别对缓冲模块102和校准模块103进行详细说明。
首先对缓冲模块102进行详细说明。
可调缓冲电路的数量为一条或多条，同一条缓冲电路接收到的缓冲电路控制信号相同。若可调缓冲电路包括多条，多条可调缓冲电路中接收到的缓冲电路控制信号可相同或者多条可调缓冲电路中至少存在两条可调缓冲电路接收到的缓冲电路控制信号不相同。
其中，每条可调缓冲电路中第一类开关的数量可为多个、第二类开关的数量可为多个。不同条缓冲电路包括的第一类开关的数量可相同也可不相同，不同条缓冲电路包括的第二类开关的数量可相同也可不相同。在一种可选的方式中，可存在L条可调缓冲电路，第1条缓冲电路至第L条可调缓冲电路包括的开关的总数量的比例可为1:……:2 l，l＝0,1,……,L-1；或者，第1条缓冲电路至第L条可调缓冲电路包括的第一类开关的总数量的比例可为1:……:2 l，以及第1条缓冲电路至第L条可调缓冲电路包括的第二类开关的总数量的比例可为1:……:2 l。
可选地，第一类开关为P型MOS管(为了后续表述的方便，后续称P型MOS管为pmos管)；第二类开关为N型MOS管(为了后续表述的方便，后续称N型MOS管为nmos管)。
下面对可调缓冲电路的一种具体结构进行说明。
可调缓冲电路包括N个串联连接的第一类开关组和M个串联连接的第二类开关组，N个第一类开关组中的第一开关组的漏极与M个第二类开关组中的第二开关组的漏极电连接后与校准模块103电连接；第一开关组的栅极和第二开关组的栅极电连接后与晶体振荡器101电连接。N和M均为大于等于2的整数，N和M可相同，比如N＝M＝2。也就是说N个第一类开关组中的第一开关组的栅极和M个第二类开关组中的第二开关组的栅极为可调缓冲电路的第二输入端。
N个第一类开关组中的其它开关组的栅极与M个第二类开关组中的中的其它开关组的栅极均与校准模块103电连接。也就是说N个第一类开关组中的其它开关组的栅极为可调缓冲电路的一个第一输入端，M个第二类开关组中的其它开关组的栅极为可调缓冲电路的另一个第一输入端。
此外，N个第一类开关组中的第三开关组的源极还可与市电电源连接，M个第二类开关组中的第四开关组的源极可接地。第三开关组与第一开关组之间存在N-2个第一类开关组，第四开关组与第二开关组之间存在M-2个第二类开关组。
其中，每个第一类开关组中包括至少一个并联连接的第一类开关，即每个第一类开关组中的各第一类开关的源极连接、各第一类开关的漏极连接，各第一类开关的删极连接。
图2为一个第一类开关组的示意图，参见图2，图2中的一个第一类开关组包括两个pmos管201、202，pmos管201的源极与pmos管202的源极连接，pmos管201的漏极与 pmos管202的漏极连接，pmos管201的漏极与pmos管202的栅极连接。
同样地，每个第二类开关组中包括至少一个并联连接的第二类开关。每个第二类开关组中的各第二类开关的源极连接、各第二类开关的漏极连接，各第二类开关的栅极连接。
值得说明的是，在缓冲模块102包括多条可调缓冲电路的情况下，每条可调缓冲电路中包括的第一类开关组所包括的第一类开关的数量可不相同，每条可调缓冲电路中包括的第二类开关组包括的第二类开关的数量可不相同。同一条可调缓冲电路中：各第一类开关组中包括的第一类开关的数量可相同，各第二类开关组中包括的第二类开关的数量可相同，第一类开关组中包括的第一类开关的数量与第二类开关组中包括的第二类开关的数量可相同。
图3为本申请实施例提供的一条可调缓冲电路的一种结构示意图。参见图3，可调缓冲电路包括2个串联连接的pmos管301和302，2个串联连接的nmos管303和304；其中，pmos管301为一个第一类开关组，pmos管302为一个第一类开关组，nmos管303为一个第二类开关组、nmos管304为一个第二类开关组。pmos管301的栅极、nmos管304的栅极均为可调缓冲电路的第一输入端，校准模块103发送相同的缓冲电路控制信号xo_dac<0>至pmos管301的栅极、nmos管304的栅极；pmos管301的源极与市电电源连接，nmos管304的源极接地。其中，pmos管301即为2个第一类开关组中的第三开关组、nmos管304即为2个第二类开关组中的第四开关组。
pmos管302的漏极与nmos管303的漏极连接后作为可调缓冲电路的输出端与校准模块103电连接，输出信号为buf_out；pmos管302的栅极与nmos管303的栅极均与晶体振荡器101电连接，pmos管302的栅极与nmos管303的栅极为可调缓冲电路的第二输入端，晶体振荡器101生成的时钟xo_out经可调缓冲电路的第二输入端输入可调缓冲电路。其中，pmos管302即为2个第一类开关组中的第一开关组、nmos管303即为2个第二类开关组中的第二开关组。
图4为本申请实施例提供的一条可调缓冲电路的另一种结构示意图。参见图4，可调缓冲电路包括2个串联连接的pmos管组401和402，2个串联连接的nmos管组403和404，其中，pmos管组401包括2个pmos管，pmos管组402包括2个pmos管，nmos管组403包括2个nmos管，nmos管组404包括2个nmos管。pmos管组401的栅极、nmos管组404的栅极均为可调缓冲电路的第一输入端，校准模块103发送相同的缓冲电路控制信号xo_dac<1>至pmos管组401的栅极、nmos管组404的栅极。其中，pmos管组401即为2个第一类开关组中的第三开关组、nmos管组404即为2个第二类开关组中的第四开关组。
pmos管组402的漏极与nmos管组403的漏极连接后作为可调缓冲电路的输出端与校准模块103电连接，输出信号为buf_out。pmos管组402的栅极与nmos管组403的栅极均与晶体振荡器101电连接，pmos管组402的栅极与nmos管组403的栅极为可调缓冲电路的第二输入端，晶体振荡器101生成的时钟xo_out经可调缓冲电路的第二输入端输入可调缓冲电路。其中，pmos管组402即为2个第一类开关组中的第一开关组、nmos管组403即为2个第二类开关组中的第二开关组。
图5为本申请实施例提供的缓冲模块的一种示意图。参见图5，缓冲模块102包括L条可调缓冲电路，每条可调缓冲电路的第一输入端均用于接收校准模块103发送的缓冲电路控制信号xo_dac<l>，即与校准模块103电连接；每条可调缓冲电路的第二输入端均用 于接收晶体振荡器101的输出信号xo_out，即第二输入端均与晶体振荡器101电连接；每条可调缓冲电路的输出端均与校准模块103电连接。每条可调缓冲电路的一端与市电电源连接、另一端接地。比如，可调缓冲电路1可如图3中所示，可调缓冲电路2可如图4中所示。
示例性地，L条可调缓冲电路中每条可调缓冲电路均包括N个第一类开关组，M个第二类开关组。同一条可调缓冲电路中每个第一类开关组包括的第一类开关的数量相同，同一条可调缓冲电路中每个第二类开关组包括的第二类开关的数量相同；第1条缓冲电路至第L条调缓冲电路中每个第一类开关组包括的第一类开关的数量的比例可为1:……:2 l和/或第1条缓冲电路至第L条调缓冲电路中每个第二类开关组包括的第二类开关的数量的比例可为1:……:2 l。
为了使得缓冲模块102中同时存在处于开启状态的第一类开关和第二类开关，以保证缓冲模块102的正常工作，缓冲模块102中还包括固定缓冲电路，固定缓冲电路中处于开启状态的第一类开关的数量为第一固定数量以及处于开启状态的第二类开关的数量为第二固定数量。
固定缓冲电路包括第一输入端、第二输入端和第三输入端，固定缓冲电路的第一输入端与晶体振荡器101的输出端连接、第二输入端用于输入第一预设控制信号、第三输入端用于输入第二预设控制信号，第一预设控制信号为能够使得固定缓冲电路中的第一类开关均处于开启状态的信号，第二预设控制信号为能够使得固定缓冲电路中的第二类开关均处于开启状态的信号。固定缓冲电路还包括输出端，固定缓冲电路的输出端与校准模块103电连接。
其中，固定缓冲电路的数量可为一条或多条。
下面对固定缓冲电路的一种具体结构进行说明。
固定缓冲电路包括P个串联连接的第一类开关组和Q个串联连接的第二类开关组，P个第一类开关组中的第一开关组的漏极与Q个第二类开关组中的第二开关组的漏极电连接后与校准模块103连接；第一开关组的栅极和第二开关组的栅极均电连接后与晶体振荡器101电连接。Q和P均为大于等于2的整数，P和Q可相同，比如P＝Q＝2。也就是说P个第一类开关组中的第一开关组的栅极和Q个第二类开关组中的第二开关组的栅极为固定缓冲电路的第一输入端。
P个第一类开关组中的其它开关组的栅极为固定缓冲电路的第二输入端，用于输入第一预设控制信号，第一预预设控制信号使得P个第一类开关组中的各第一类开关处于开启状态。Q个第二类开关组中的其它开关组的栅极为固定缓冲电路的第三输入端，用于输入第二预设控制信号，第二预设控制信号使得Q个第二类开关组中的各第二类开关处于开启状态。
此外，P个第一类开关组中的第三开关组的源极还可与市电电源连接，Q个第二类开关组中的第四开关组的源极可接地。P个第一类开关组中的第三开关组与第一开关组之间存在P-2个第一类开关组，Q个第二类开关组中的第四开关组与第二开关组之间存在Q-2个第二类开关组。
同样地，P个串联连接的第一类开关组中每个第一类开关组中至少包括一个并联连接的第一类开关。Q个串联连接的第二类开关组中每个第二类开关组中至少包括一个并联连 接的第二类开关。
可以理解的是，固定缓冲电路包括的第一类开关数量和第二类开关的数量的多少，可以影响时钟占空比校准的精度及范围。
图6为本申请实施例提供的一条固定缓冲电路的一种结构示意图。参见图6，固定缓冲电路包括2个串联连接的pmos管601和602，2个串联连接的nmos管603和604；其中，pmos管601为一个第一类开关组，pmos管602为一个第一类开关组，nmos管603为一个第二类开关组、nmos管604为一个第二类开关组。pmos管601的栅极为固定缓冲电路的第二输入端，用于输入第一预设控制信号，nmos管604的栅极为固定缓冲电路的第三输入端，用于输入第二预设控制信号。pmos管601的源极与市电电源连接，nmos管604的源极接地。其中，pmos管601即为2个第一类开关组中的第三开关组、nmos管604即为2个第二类开关组中的第四开关组。
pmos管602的漏极与nmos管603的漏极连接后作为固定缓冲电路的输出端与校准模块103电连接，输出信号为buf_out；pmos管602的栅极与nmos管603的栅极均与晶体振荡器101电连接，pmos管602的栅极与nmos管603的栅极为固定缓冲电路的第一输入端，晶体振荡器101生成的原始时钟xo_out经可调缓冲电路的第二输入端输入可调缓冲电路。其中，pmos管602即为2组第一类开关中的第一开关组、nmos管603即为2组第二类开关中的第二开关组。
图7为本申请实施例提供的缓冲模块的另一种结构示意图。参见图7，缓冲模块102包括L条可调缓冲电路和一条固定缓冲电路，每条可调缓冲电路的第一输入端均用于接收校准模块103发送的缓冲电路控制信号xo_dac<l>，即与校准模块103电连接；每条可调缓冲电路的第二输入端均用于接收晶体振荡器101的输出信号xo_out，即可调缓冲电路的第二输入端均与晶体振荡器101电连接；每条可调缓冲电路的输出端均与校准模块103电连接。每条可调缓冲电路的一端与市电电源连接、另一端接地。固定缓冲电路的第一输入端均用于接收晶体振荡器101的输出信号xo_out，即固定缓冲电路的第一输入端与晶体振荡器101电连接；固定缓冲电路的缓冲电路的输出端与校准模块103电连接；固定缓冲电路的一端与市电电源连接、另一端接地。比如，可调缓冲电路1可如图3中所示，可调缓冲电路2可如图4中所示，一条固定缓冲电路可如图6中所示。
其次，对校准模块103进行详细说明。
校准模块103包括相位检测子模块，相位检测子模块用于输出第一时钟被延时后的上升沿与第一时钟被反向后的上升沿的第一对齐结果；还用于输出第二时钟被延时后的上升沿与第二时钟被反向后的上升沿的第二对齐结果。第一对齐结果和第二对齐结果用于缓冲电路控制信号的生成。其中，第一时钟是晶体振荡器101产生的时钟至少经缓冲模块102后得到的，第二时钟是第一时钟被反向后得到的。
相位检测子模块包括但不限于如下的两种形式：
在第一种形式中：相位检测子模块包括第一多路选择器、第二多路选择器、延时器和相位检测器；第一多路选择器的输出端与延时器的输入端电连接，延时器的输出端还相位检测器的输入端电连接，第二多路选择器的输出端与相位检测器的输入端电连接。
在一种方式中，第一多路选择器的第一通道用于输入第一时钟，第二多路选择器的第一通道用于输入第一时钟被反向后的第二时钟；所述第一多路选择器的第二通道用于输入 所述第二时钟，所述第二多路选择器的第二通道用于输入所述第二时钟被反向后的第三钟。
在第二种形式中：相位检测子模块包括：第一延时器、第二延时器、第一相位检测器和第二相位检测器；第一延时器的输出端与第一相位检测器的输入端电连接，第二延时器的输出端与第二相位检测器的输入端电连接。
在一种方式中，第一延时器的输入端用于输入第一时钟，第一相位检测器的输入端用于输入第一时钟被第一延时器延时后的时钟和第一时钟被反向后的第二时钟。第二延时器的输入端用于输入第二时钟，第二相位检测器的输入端用于输入第二时钟被第二延时器延时后的时钟和第二时钟被反向后的第三时钟。
校准模块103还可包括反向子模块，反向子模块与相位检测子模块电连接；反向子模块用于对第一时钟进行反向以使相位检测子模块输出第一对齐结果以及用于对第二时钟进行反向以使相位检测子模块输出第二对齐结果。
一种方式中，反向子模块包括第一反向器和第二反向器，第一反向器的输出端与第二反向器的输入端电连接；第一反向器和第二反向器均与相位检测子模块连接。其中，第一反向器的输入为上述提及的第一时钟，第一反向器的输出或第二反向器的输入称为上述提及的第二时钟，第二反向器的输出为第三时钟。
校准模块103还可包括处理器，处理器与可调缓冲电路的第一输入端电连接。处理器用于根据第一对齐结果和第二对齐结果输出缓冲电路控制信号。
因此，在一种方式中，校准模块103可包括依次电连接的反向子模块、相位检测子模块、处理器。反向子模块的输入端与缓冲模块102的输出端电连接，处理器的输出端与可调缓冲电路的第一输入端电连接。
在相位检测子模块为第一种形式时，校准模块103的一种具体结构可如下：第一反向器的输入端与第一多路选择器的第一通道的输入端电连接，第一反向器的输出端还与第二多路选择器的第一通道的输入端以及第一多路选择器的第二通道的输入端电连接，第二反向器的输出端与第二多路选择器的第二通道的输入端电连接。
第一多路选择器的输出端与延时器电连接，延时器还与相位检测器的输入端电连接，第二多路选择器的输出端与相位检测器电连接。
相位检测器的输出端与处理器电连接，处理器还与第一多路选择器、第二多路选择器和延时器电连接。
图8为本申请实施例提供的一种校准模块的结构示意图。图8所示的校准模块103对应于相位检测子模块的第一种形式，参见图8，第一反向器801的输入端与第一多路选择器802的第一通道0的输入端以及缓冲模块102的输出端电连接，第一反向器801的输出端与第二反向器803的输入端电连接，第一反向器801的输出端还与第二多路选择器804的第一通道0的输入端以及第一多路选择器802的第二通道1的输入端电连接，第二反向器803的输出端与第二多路选择器804的第二通道1的输入端电连接。
第一多路选择器802的输出端与延时器805电连接，延时器805还与相位检测器806的输入端电连接，第二多路选择器804的输出端与相位检测器806电连接。相位检测器806的输出端与处理器807电连接，处理器807还与第一多路选择器802、第二多路选择器804和延时器805连接。
在相位检测子模块为第二种形式时，校准模块103的另一种具体结构可如下：第一反 向器的输入端与第一延时器的一端电连接，第一延时器的另一端与第一相位检测器的输入端电连接。第一反向器的输出端分别、第一相位检测器的输入端以及第二延时器的一端电连接；第二反向器的输出端与第二相位检测器的输入端电连接，第二延时器的另一端与第二相位检测器电连接。第一相位检测器和第二相位检测器的输出端均与处理器电连接；处理器还与第一延时器、第二延时器电连接。
图9为本申请实施例提供的另一种校准模块的结构示意图。图9所示的校准模块103对应与相位检测子模块的第二种形式，参见图9，第一反向器901的输入端与第一延时器902的一端电连接，第一延时器902的另一端与第一相位检测器903的输入端电连接。第一反向器901的输出端分别与第二反向器904的输入端、第一相位检测器903的输入端以及第二延时器905的一端电连接；第二反向器904的输出端与第二相位检测器906的输入端电连接，第二延时器905的另一端与第二相位检测器906电连接。第一相位检测器903和第二相位检测器906的输出端均与处理器907电连接；处理器907还与第一延时器902、第二延时器905电连接。
缓冲模块102中各条可调缓冲电路和固定缓冲电路的输出端可直接与校准模块103电连接，还可间接与校准模块103电连接。校准模块103中的处理器与缓冲模块102中各条可调缓冲电路的第一输入端连接。
在缓冲模块102中各条可调缓冲电路和固定缓冲电路的输出端间接与校准模块103的第一反向器电连接时，在缓冲模块102中各条可调缓冲电路的输出端和固定缓冲电路的输出端可通过第一电路与校准模块103的第一反向器电连接。
第一电路包括但不限于如下的几种形式：
第一种形式：第一电路包括第一缓冲器，第一缓冲器的一端与缓冲模块102中各条可调缓冲电路和固定缓冲电路的输出端电连接，第一缓冲器的另一端与校准模块103电连接，比如与校准模块103的第一反向器的输入端电连接。
对应与该第一形式的第一电路，时钟占空比校准装置可如图10所示。参见图10，时钟占空比校准装置包括晶体振荡器101、缓冲模块102、第一缓冲器1003和校准模块103。
第二种形式：第一电路包括电容、电感，第三反向器、第四反向器、第一缓冲器。电容的一端与缓冲模块102中各条可调缓冲电路的输出端和固定缓冲电路的输出端电连接，电容的另一端分别与电感的一端和第三反向器的输入端电连接，电感的另一端和第三反向器的输出端分别与第四反向器的输入端电连接，第四反向器的输出端与第一缓冲器的一端电连接，第一缓冲器的另一端与校准模块103电连接，比如第一缓冲器的另一端与校准模块103的第一反向器的输入端电连接。
对应与该第二形式的第一电路，时钟占空比校准装置可如图11所示。参见图11，时钟占空比校准装置包括晶体振荡器101、缓冲模块102、电容1101、电感1103、第三反向器1102、第四反向器1104、第一缓冲器1003和校准模块103。
为了能够输出其它占空比和/或其它频率的时钟，本实施例的时钟占空比校准装置还可包括一个或多个倍频电路。倍频电路与校准模块103电连接。倍频电路包括：电连接的第三延时器和异或器XOR，具体可如图12所示。
在校准模块103的具体结构如上所述时，倍频电路的输入端与校准模块103的第二反向器的输出端电连接，即第二反向器的输出端与第三延时器和异或器XOR电连接。可选 地，第三延时器还与校准模块103的处理器电连接。
倍频电路可与校准模块103直接电连接还可与校准模块103间接电连接。在倍频电路与校校准模块103间接电连接时，校准模块103可与第二缓冲器的输入端电连接(比如校准模块103的第二反向器的输出端与第二缓冲器的输入端电连接)，第二缓冲器与倍频电路电连接(第二缓冲器的输出端与第三延时器和异或器XOR电连接)。
在倍频电路与校校准模块103间接电连接时所对应的时钟占空比校准装置可如图13所示。
参见图13，时钟占空比校准装置包括晶体振荡器101、缓冲模块102、电容1101、电感1103、第三反向器1102、第四反向器1104、第一缓冲器1003、校准模块103、第二缓冲器1301和倍频电路1302。倍频电路1302可包括一个或多个，图中未示出多个倍频电路1302的情况。
为了能够同时输出预设占空比的时钟，以及其它占空比和/或其它频率的时钟，本实施例的时钟占空比校准装置还可包括第三多路选择器。第三多路选择器的第一通道与倍频电路的输出端电连接，第三多路选择器的第二通道与校准模块103电连接。第三多路选择器的第二通道与校准模块103直接电连接或间接电连接。在第三多路选择器的第二通道与校准模块103间接电连接时，校准模块103可与第二缓冲器电连接，第二缓冲器与倍频电路电连接，第二缓冲器还与第三多路选择器的第二通道连接。
第三多路选择器的第二通道与校准模块103间接电连接时所对应的时钟占空比校准装置可如图14所示。
参见图14，时钟占空比校准装置包括晶体振荡器101、缓冲模块102、电容1101、电感1103、第三反向器1102、第四反向器1104、第一缓冲器1003、校准模块103、第二缓冲器1301、倍频电路1302、第三多路选择器1401。倍频电路1302可包括一个或多个，图中未示出多个倍频电路1302的情况。
以上对时钟占空比校准装置进行了说明，下面对基于上述时钟占空比校准装置校准时钟占空比的方法。
如上所述校准模块103的第一反向器输入第一时钟，第一时钟是晶体振荡器101产生的时钟至少经缓冲模块102后得到的。可以理解的是，若时钟占空比校准装置如图10所示，则第一时钟为晶体振荡器101产生的时钟依次经缓冲模块102和第一缓冲器后得到的。若时钟占空比校准装置如图11所示，则第一时钟为晶体振荡器101产生的时钟依次经缓冲模块102、电容、第三反向器、第四反向器、第一缓冲器后得到的。可以理解的是，晶体振荡器101产生的时钟经缓冲模块102后占空比可能发生变化，经电容、反向器、缓冲器等电器元件后占空比不会发生变化。
第一时钟经第一反向器后得到第二时钟，第二时钟为第一反向器的输出、第二反向器的输入；第二时钟经第二反向器后得到第三时钟，第三时钟为第二反向器的输出，第二反向器的输出。可以理解的是，第一时钟、第二时钟、第三时钟的占空比相同。由于第三时钟为最终输出的时钟，或者，第三时钟为最终经倍频电路输出的时钟，因此，在第一时钟或第二时钟或第三时钟的占空比为预设占空比时，则可认为得到了预设占空比的时钟。
以下基于图10所示的时钟占空比校准装置对时钟占空比校准方法进行说明。
参见图15，图15中的a图为第一时钟P1的波形、b图为第一时钟被反向后第二时钟 P2的波形、c图为第二时钟被反向后的第三时钟P3的波形。
若无特别说明，后续出现的延时器为校准模块中的延时器。
若使得第一时钟的上升沿延时时延1后和第二时钟的上升沿对齐，则如图16所示，MUX1 0+Delay1＝INV1+MUX2 0+T1(1)，其中，MUX1 0为第一时钟经第一多路选择器的第一通道产生的时延，Delay1为延时器的时延1，INV1为第一时钟经第一反向器得到第二时钟所产生的时延，MUX2 0为第二时钟经第二多路选择器的第一通道产生的时延，T1为第一时钟或第二时钟高电平的时间。
若使得第二时钟的上升沿延时时延2后和第三时钟的上升沿对齐，则如图17所示，MUX1 1+Delay2＝INV2+MUX2 1+T2(2)，其中，MUX1 1为第二时钟经第一多路选择器的第二通道产生的时延，Delay2为延时器的时延2，INV2为第二时钟经第二反向器得到第三时钟所产生的时延，MUX2 1为第二时钟经第二多路选择器的第二通道产生的时延，T2为第二时钟或第三时钟低电平的时间。
在第一多路选择器和第二多路选择器的性能大致相同时，可认为MUX1 0＝MUX2 0＝MUX1 1＝MUX2 0；在第一反向器和第二反向器的性能大致相同时，可认为INV2和INV1相同。可以理解的是，若T2＝T1，则第一时钟、第二时钟、第三时钟的占空比即为预设占空比0.5。那么，在前述MUX1 0＝MUX2 0＝MUX1 1＝MUX2 0，INV2＝INV1的情况下，若Delay1＝Delay2，则T2＝T1。因此，校准时间的占空比为0.5转化为获取延时器的第一时延，第一时钟的上升沿被延时第一时延后能够与第二时钟的上升沿对齐，获取延时器的第二时延，第二时钟的上升沿被延时第二时延后能够与第三时钟的上升沿对齐，若第一时延和第二时延相等，则第一时钟、第二时钟、第三时钟的占空比即为预设占空比0.5。
首先，对获取延时器的第一时延的过程进行说明。
如上所述，第一多路选择器与延时器电连接，第二多路选择器和延时器与相位检测器电连接，第一反向器的输入端与第一多路选择器的第一通道连接，而第一反向器的输入端为第一时钟，也就是第一时钟依次经第一多路选择器的第一通道、延时器后输入至相位检测器；第二反向器的输入端与第二多路选择器的第一通道连接，第二反向器的输入端为第二时钟，也就是第二时钟经第二多路选择器的第一通道后输入至相位检测器。
在获取延时器的第一时延时，处理器控制第一多路选择器的第一通道和第二多路选择器的第一通道导通，以使第一时钟依次经第一多路选择器的第一通道、延时器延时后输入至相位检测器，第二时钟经第二多路选择器的第一通道后输入至相位检测器。
相位检测器检测第一时钟依次经第一多路选择器的第一通道、延时器延时当前时延后的上升沿与第二时钟经第二多路选择器的第一通道后的上升沿的对齐状态，也可以说是判断第一时钟的上升沿被延时器延时当前时延后与第二时钟的上升沿的对齐状态，以输出第一路对齐结果至处理器。其中，第一路对齐结果指示对齐状态，对齐状态包括但不限于如下的任意一种：两路时钟的上升沿对齐、两路时钟中A路时钟出现上升沿超前B路时钟出现上升沿的超前时长、两路时钟中A路时钟出现上升沿滞后B路时钟出现上升沿的滞后时长。后面两种对齐状态均指示第一时钟的上升沿被延时器延时当前时延后未与第二时钟的上升沿对齐。
若处理器根据第一路对齐结果确定第一时钟的上升沿被延时器延时当前时延后未与第二时钟的上升沿对齐，则根据第一路对齐结果发送第一类时延控制信号至延时器，以更 新延时器的时延。即处理器根据第一路对齐结果确定延时器的时延应该调大还是调小以及调整量，并发送第一类时延控制信号至延时器，以更新延时器的时延。在一种方式中，第一类时延控制信号指示延时器的调节时延，延时器的时延包括固定时延和调节时延。若处理器根据第一路对齐结果确定第一时钟的上升沿被延时器延时后与第二时钟的上升沿对齐，则处理器确定延时器的当前时延为延时器的第一时延。
延时器接收到第一类时延控制信号后，根据第一类时延控制信号更新时延，此时第一时钟依次经第一多路选择器的第一通道、延时器延时新的时延后被输入至相位检测器，相位检测器检测第一时钟依次经第一多路选择器的第一通道、延时器延时新的时延后的上升沿与第二时钟经第二多路选择器的第一通道后的上升沿的对齐状态，也可以说是判断第一时钟的上升沿被延时器延时新的时延后与第二时钟的上升沿的对齐状态，以输出新的第一路对齐结果至处理器。
处理器根据新的第一路对齐结果确定第一时钟的上升沿被延时器延时新的时延后未与第二时钟的上升沿对齐，则根据新的第一路对齐结果发送新的第一类时延控制信号至延时器，以再次更新延时器的时延。若处理器根据新的第一路对齐结果确定第一时钟的上升沿被延时器延时后与第二时钟的上升沿对齐，则处理器确定延时器的新的时延为延时器的第一时延。
重复上述步骤，直至处理器根据接收到的第一路对齐结果确定第一时钟的上升沿被延时器延时后与第二时钟的上升沿对齐，此时延时器的时延即为延时器的第一时延。
接着，对获取延时器的第二时延的过程进行说明。
如上所述，第一多路选择器与延时器电连接，第二多路选择器和延时器与相位检测器电连接，第二反向器的输入端与第一多路选择器的第二通道连接，而第二反向器的输入端为第二时钟，也就是第二时钟依次经第二多路选择器的第二通道、延时器后输入至相位检测器；第二反向器的输出端与第二多路选择器的第二通道连接，第二反向器的输出端为第三时钟，也就是第三时钟经第二多路选择器的第二通道后输入至相位检测器。
在获取延时器的第二时延时，处理器控制第一多路选择器的第二通道和第二多路选择器的第二通道导通，以使第二时钟依次经第一多路选择器的第二通道、延时器延时后输入至相位检测器，第二时钟经第二多路选择器的第二通道后输入至相位检测器。
相位检测器检测第二时钟依次经第一多路选择器的第二通道、延时器延时当前时延后的上升沿与第三时钟经第二多路选择器的第二通道后的上升沿的对齐状态，也可以说是判断第二时钟的上升沿被延时器延时当前时延后与第三时钟的上升沿的对齐状态，以输出第二路对齐结果至处理器。其中，第二路对齐结果指示对齐状态，对齐状态的含义同上述阐述，此处不再赘述。
若处理器根据第二路对齐结果确定第二时钟的上升沿被延时器延时当前时延后未与第三时钟的上升沿对齐，则根据第二路对齐结果发送第二类时延控制信号至延时器，以更新延时器的时延。即处理器根据第二路对齐结果确定延时器的时延应该调大还是调小以及调整量，并发送第二类时延控制信号至延时器，以更新延时器的时延。在一种方式中，第二类时延控制信号指示延时器的调节时延，延时器的时延包括固定时延和调节时延。若处理器根据第二路对齐结果确定第二时钟的上升沿被延时器延时当前时延后与第三时钟的上升沿对齐，则处理器确定延时器的当前时延为延时器的第二时延。
延时器接收到第二类时延控制信号后，根据第二类时延控制信号更新时延，此时第二时钟依次经第一多路选择器的第二通道、延时器延时新的时延后被输入至相位检测器，相位检测器检测第二时钟依次经第一多路选择器的第二通道、延时器延时新的时延后的上升沿与第三时钟经第二多路选择器的第二通道后的上升沿的对齐状态，也可以说是判断第二时钟的上升沿被延时器延时新的时延后与第三时钟的上升沿的对齐状态，以输出新的第二路对齐结果至处理器。
若处理器根据新的第二路对齐结果确定第二时钟的上升沿被延时器延时新的时延后未与第三时钟的上升沿对齐，则根据新的第二路对齐结果发送新的第二类时延控制信号至延时器，以再次更新延时器的时延。若处理器根据第二路对齐结果确定第二时钟的上升沿被延时器延时后与第三时钟的上升沿对齐，则处理器确定延时器的新的时延为延时器的第二时延。
重复上述步骤，直至处理器根据接收到的第二路对齐结果确定第二时钟的上升沿被延时器延时后与第三时钟的上升沿对齐，此时延时器的时延即为延时器的第二时延。
在获取到的延时器的第一时延和第二时延之后，如上所述，若延时器的第一时延和第二时延相等，则第一时钟、第二时钟、第三时钟的占空比即为预设占空比0.5，即时钟校准完成。下面对若延时器的第一时延和第二时延不相等的情况下的处理方法进行说明。
若处理器确定延时器的第一时延和延时器的第二时延不相同，说明晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比不为预设占空比0.5，即低电平时间和高电平时间不相同。因此，处理器向缓冲模块102的可调缓冲电路发送缓冲电路控制信号，以调节可调缓冲电路中处于开启状态的第一类开关和第二类开关的数量，得到被更新的第一时钟、第二时钟和第三时钟。被更新的第一时钟、第二时钟和第三时钟的占空比也被更新。
其中，缓冲模块102中处于开启状态的第一类开关的数量和第二类开关的数量影响晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比，比如在第一类开关为pmos管、第二类开关为nmos管时，nmos管的数量越多，晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比越小。而延时器的第一时延和延时器的第二时延的大小可以反映出低电平时间和高电平时间的长短，即可以反映出占空比相对于预设占空比偏高还是偏低。因此，在处理器据延时器的第一时延和第二时延，确定晶体振荡器101产生的时钟经当前的缓冲模块102后的时钟(比如第一时钟、第二时钟和第三时钟)的占空比偏小时，则生成的缓冲电路控制信号应该为可以增加pmos管处于开启状态的数量的缓冲控制信号。因此，在处理器据延时器的第一时延和延时器的第二时延，确定晶体振荡器101产生的时钟经当前的缓冲模块102后的时钟的占空比偏大时，则生成的缓冲电路控制信号应该为可以增加处于开启状态的nmos管的数量的缓冲控制信号。
继续参见图3，在xo_dac<0>为第一缓冲电路控制信号时，图3中所示的一条可调缓冲电路的pmos管全部处于开启状态，nmos管全部处于关闭状态；在xo_dac<0>为第二缓冲电路控制信号时，图3中所示的一条可调缓冲电路的pmos管全部处于关闭状态，nmos管全部处于开启状态。因此，处理器可通过向各可调缓冲电路输入第一缓冲电路控制信号或者第二缓冲电路控制信号来控制缓冲模块102中处于开启状态的第一类开关的数量和第二类开关的数量。
示例性地，在缓冲模块102存在4条可调缓冲电路的情况下，当前第1条可调缓冲电 路输入第一缓冲电路控制信号，当前第2条可调缓冲电路输入第一缓冲电路控制信号，当前第3条可调缓冲电路输入第二缓冲电路控制信号，当前第4条可调缓冲电路输入第二缓冲电路控制信号，第1条和第2条可调缓冲电路的pmos管全部处于开启状态、第3条和第4条可调缓冲电路的nmos管全部处于开启状态。在处理器据延时器的第一时延和第二时延，确定晶体振荡器101产生的时钟经当前的缓冲模块102后的时钟的占空比偏大时，则可向第1条可调缓冲电路发送第一缓冲电路控制信号，向第2条可调缓冲电路发送第二缓冲电路控制信号，向第3条可调缓冲电路发送第二缓冲电路控制信号，向第4条可调缓冲电路发送第二缓冲电路控制信号，以增加处于开启状态的nmos管的数量。在处理器据延时器的第一时延和第二时延，确定晶体振荡器101产生的时钟经当前的缓冲模块102后的时钟的占空比偏小时，则可向第1条可调缓冲电路发送第一缓冲电路控制信号，向第2条可调缓冲电路发送第一缓冲电路控制信号，向第3条可调缓冲电路发送第一缓冲电路控制信号，向第4条可调缓冲电路发送第二缓冲电路控制信号，以增加处于开启状态的pmos管的数量；或者，第3条可调缓冲电路中pmos管的数量大于第2条可调缓冲电路中pmos管的数量，在处理器据延时器的第一时延和延时器的第二时延，确定晶体振荡器101产生的时钟经当前的缓冲模块102后的时钟的占空比偏小时，则可向第1条可调缓冲电路发送第一缓冲电路控制信号，向第2条可调缓冲电路发送第二缓冲电路控制信号，向第3条可调缓冲电路发送第一缓冲电路控制信号，向第4条可调缓冲电路发送第二缓冲电路控制信号，以增加处于开启状态的pmos管的数量。
缓冲模块102中处于开启状态的第一类开关的数量和第二类开关的数量被调整后，即缓冲模块102被更新，晶体振荡器101产生的时钟经新的缓冲模块102后的时钟的占空比也被更新，即得到更新后的第一时钟、更新后的第二时钟、更新后的第三时钟。
采用根据第一时钟、第二时钟、第三时钟获取延时器的第一时延和第二时延的方法，根据更新后的第一时钟、更新后的第二时钟、更新后的第三时钟获取延时器的新的第一时延和新的第二时延，直至得到的延时器的第一时延和第二时延相同，即将晶体振荡器101产生的时钟经缓冲模块102后的时钟(也就是输出时钟)的占空比调整至预设占空比0.5。
上述仅是一种示例性的基于上述时钟校准装置的时钟校准方法，此外还可以将校准时间的占空比为0.5转化为获取延时器的第三时延，第一时钟的下降沿被延时第三时延后能够与第二时钟的上升沿对齐，获取延时器的第四时延，第二时钟的下降沿被延时第二时延后能够与第三时钟的下降沿对齐，若第三时延和第四时延相等，则第一时钟、第二时钟、第三时钟的占空比即为预设占空比0.5。获取延时器的第三时延和获取延时器的第四时延的方法与获取延时器的第一时延和获取延时器的第二时延的方法类似，此处不再赘述。
输出时钟可直接被输出以生成业务的参考时钟。输出时钟还可以经倍频电路改变频率和/或占空比，得到新的时钟。
在一种可选的方案中，处理器发送第一时延控制信号和第二时延控制信号至倍频电路的延时器，第一时延控制信号用于指示第二固定时延，第二固定时延为第一固定时延的1/N倍，第二时延第二控制信号用于指示第二调节时延，第二调节时延为第一调节时延的1/N倍，第一固定时延与第一调节时延之和为晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比被调整至预设占空比0.5时所对应的校准模块103的延时器的时延。此时，倍频电路的延时器的时延为第二固定时延与第二调节时延之和，倍频电路输出的时钟为占 空比为1/N的目标时钟，目标时钟的频率为倍频电路的输入时钟的两倍。倍频电路的输入时钟即为第三时钟或者第三时钟经第二缓冲器后的时钟。
在另一种可选的方案中，处理器发送第一时延控制信号和第二时延控制信号至倍频电路的延时器，第一时延控制信号用于指示第一固定时延，第二时延控制信号用于指示第一调节时延，第一固定时延与第一调节时延之和为晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比被调整至预设占空比0.5时所对应的校准模块103的延时器的时延。倍频电路的延时器获取1/N倍的第一调节时延和1/N倍的第一固定时延，1/N倍的第一调节时延和1/N倍的第一固定时延之和为倍频电路的延时器的时延。此时，倍频电路输出的时钟为占空比为1/N的目标时钟，目标时钟的频率为倍频电路的输入时钟的两倍。倍频电路的输入时钟即为第三时钟或者第三时钟经第二缓冲器后的时钟。
在又一种可选的方案中，处理器发送第一时延控制信号和第二时延控制信号至依次串联连接的P个倍频电路中每个倍频电路的延时器，第一时延控制信号用于指示第一固定时延，第二时延控制信号用于指示第一调节时延，第一固定时延与第一调节时延之和为晶体振荡器101产生的时钟经缓冲模块102后的时钟的占空比被调整至预设占空比0.5时所对应的校准模块103的延时器的时延。
P个倍频电路中的第p个倍频电路获取1/2 p倍的第一固定时延，1/2 p倍的第一调节时延，以使P个倍频电路中的第p个倍频电路的时延为1/2 p倍的第一固定时延与1/2 p倍的第一调节时延之和。
此时，P个倍频电路中的第p个倍频电路输出占空比为0.5的目标时钟，目标时钟的频率为P个倍频电路中的第1个倍频电路的输入时钟的2 p倍。其中，P个倍频电路中的第1个倍频电路的输入时钟为第三时钟或者第三时钟经第二缓冲器后的时钟。
本方案中的时钟占空比校准装置的缓冲模块包括可调缓冲电路，可调缓冲电路中处于开启状态的第一类开关和第二类开关的数量可以影响时钟的占空比，而校准模块能够发送缓冲电路控制信号以调节可调缓冲电路中处于开启状态的第一类开关和第二类开关的数量，因此本实施例的装置可以通过调整缓冲模块中处于开启状态的第一类开关和第二类开关的数量，准确的将时钟的占空比校准至预设占空比0.5。且简单易实现，校准效率高。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种时钟占空比校准装置，其特征在于，包括：依次电连接的晶体振荡器、缓冲模块、校准模块；
    其中，所述缓冲模块包括可调缓冲电路；所述可调缓冲电路的第一输入端与所述校准模块电连接，所述可调缓冲电路的第二输入端与所述晶体振荡器电连接，所述可调缓冲电路的输出端与所述校准模块电连接；所述缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量与时钟的占空比相关；
    所述校准模块用于向所述可调缓冲电路的第一输入端发送缓冲电路控制信号，所述缓冲电路控制信号用于控制所述缓冲模块中处于开启状态的第一类开关的数量和第二类开关的数量。
  2. 根据权利要求1所述的方法，其特征在于，所述缓冲模块还包括固定缓冲电路，所述固定缓冲电路中处于开启状态的第一类开关的数量为第一固定数量以及处于开启状态的第二类开关的数量为第二固定数量；
    所述固定缓冲电路的第一输入端与所述晶体振荡器电连接，所述固定缓冲电路的输出端与所述校准模块电连接。
  3. 根据权利要求1或2所述的装置，其特征在于，所述可调缓冲电路包括N个串联连接的第一类开关组和M个串联连接的第二类开关组，所述N个第一类开关组中的第一开关组的漏极与所述M个第二类开关组中的第二开关组的漏极电连接后与校准模块电连接；第一开关组的栅极和第二开关组的栅极电连接后与所述晶体振荡器电连接；所述N和M均为大于等于2的整数；
    所述N个第一类开关组中的其它开关组的栅极与所述M个第二类开关组中的其它开关组的栅极均与所述校准模块电连接。
  4. 根据权利要求1～3任一项所述的装置，其特征在于，所述校准模块包括相位检测子模块，所述相位检测子模块用于输出所述时钟被延时后的上升沿与所述时钟被反向后的上升沿的对齐结果，所述对齐结果用于所述缓冲电路控制信号的生成。
  5. 根据权利要求4所述的装置，其特征在于，所述相位检测子模块包括第一多路选择器、第二多路选择器、延时器和相位检测器；所述第一多路选择器的输出端与所述延时器的输入端电连接，所述延时器的输出端还所述相位检测器的输入端电连接，所述第二多路选择器的输出端与所述相位检测器的输入端电连接。
  6. 根据权利要求5所述的装置，其特征在于，所述第一多路选择器的第一通道用于输入第一时钟，所述第二多路选择器的第一通道用于输入所述第一时钟被反向后的第二时钟；所述第一多路选择器的第二通道用于输入所述第二时钟，所述第二多路选择器的第二通道用于输入所述第二反向时钟被反向后的第三时钟。
  7. 根据权利要求4所述的装置，其特征在于，所述相位检测子模块包括：第一延时器、第二延时器、第一相位检测器和第二相位检测器；
    所述第一延时器的输出端与所述第一相位检测器的输入端电连接，所述第二延时器的输出端与所述第二相位检测器的输入端电连接。
  8. 根据权利要求7所述的装置，其特征在于，所述第一延时器的输入端用于输入第一时钟，所述第一相位检测器的输入端用于输入第一时钟被所述第一延时器延时后的时钟 和所述时钟被反向后的第二时钟；
    所述第二延时器的输入端用于输入所述第二时钟，所述第二相位检测器的输入端用于输入所述第二时钟被所述第二延时器延时后的时钟和所述第二反向时钟被反向后的第三时钟。
  9. 根据权利要求4～8任一项所述的装置，其特征在于，所述校准模块还包括反向子模块，所述反向子模块与所述相位检测子模块电连接；
    所述反向子模块用于对所述时钟进行反向以使所述相位检测子模块输出所述对齐结果。
  10. 根据权利要求9所述的装置，其特征在于，所述反向子模块包括第一反向器和第二反向器，所述第一反向器的输出端与所述第二反向器的输入端电连接；
    所述第一反向器和所述第二反向器均与所述相位检测子模块连接。
  11. 根据权利要求1～10任一项所述的装置，其特征在于，所述校准模块包括处理器，所述处理器与所述可调缓冲电路的第一输入端电连接。
    所述处理器用于根据所述时钟被延时后的上升沿与所述时钟被反向后的上升沿的对齐结果输出所述缓冲电路控制信号。
  12. 根据权利要求1～11任一项所述的装置，其特征在于，还包括倍频电路；
    所述倍频电路与所述校准模块电连接。
  13. 根据权利要求1～12任一项所述的装置，其特征在于，所述第一类开关为P型MOS管，所述第二类开关为N型MOS管。
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